Made a schematic and PCB layout of my custom parallel buffered JTAG (Wiggler) device. From a technical standpoint, the schematic and PCB layout are finished, but I keep cleaning up the PCB layout. So far:

* PCB routing mistakes regarding nSRST - fixed
* Potential safety issue between the JTAG header and DC barrel jack - fixed
* via sizes - changed
* identification text labeling - now present