@@ -83,7 +83,6 @@

     <ClCompile Include="vbam\apu\Blip_Buffer.cpp" />

     <ClCompile Include="vbam\apu\Effects_Buffer.cpp" />

     <ClCompile Include="vbam\apu\Gb_Apu.cpp" />

-    <ClCompile Include="vbam\apu\Gb_Apu_State.cpp" />

     <ClCompile Include="vbam\apu\Gb_Oscs.cpp" />

     <ClCompile Include="vbam\apu\Multi_Buffer.cpp" />

     <ClCompile Include="vbam\gba\bios.cpp" />

@@ -106,6 +105,7 @@

     <ClInclude Include="vbam\apu\Multi_Buffer.h" />

     <ClInclude Include="vbam\common\Port.h" />

     <ClInclude Include="vbam\common\SoundDriver.h" />

+    <ClInclude Include="vbam\common\Types.h" />

     <ClInclude Include="vbam\gba\bios.h" />

     <ClInclude Include="vbam\gba\GBA.h" />

     <ClInclude Include="vbam\gba\GBAcpu.h" />

@@ -75,9 +75,6 @@

     <ClCompile Include="XSFConfig_GSF.cpp">

       <Filter>Source Files</Filter>

     </ClCompile>

-    <ClCompile Include="vbam\apu\Gb_Apu_State.cpp">

-      <Filter>Source Files\vbam\apu</Filter>

-    </ClCompile>

   </ItemGroup>

   <ItemGroup>

     <ClInclude Include="vbam\apu\blargg_common.h">

@@ -128,5 +125,8 @@

     <ClInclude Include="vbam\gba\Sound.h">

       <Filter>Header Files\vbam\gba</Filter>

     </ClInclude>

+    <ClInclude Include="vbam\common\Types.h">

+      <Filter>Header Files\vbam\common</Filter>

+    </ClInclude>

   </ItemGroup>

 </Project>

\ No newline at end of file

@@ -29,7 +29,7 @@ int const silent_buf_size = 1; // size used for Silent_Blip_Buffer

 Blip_Buffer::Blip_Buffer()

 {

-	factor_       = (blip_ulong)LONG_MAX;

+	factor_       = LONG_MAX;

 	buffer_       = 0;

 	buffer_size_  = 0;

 	sample_rate_  = 0;

@@ -78,16 +78,6 @@ public:

 	// tempo in a game music player.

 	void set_tempo( double );

-// Save states

-

-	// Saves full emulation state to state_out. Data format is portable and

-	// includes some extra space to avoid expansion in case more state needs

-	// to be stored in the future.

-	void save_state( gb_apu_state_t* state_out );

-

-	// Loads state. You should call reset() BEFORE this.

-	blargg_err_t load_state( gb_apu_state_t const& in );

-

 public:

 	Gb_Apu();

@@ -131,8 +121,6 @@ private:

 	void run_until( blip_time_t );

 	void silence_osc( Gb_Osc& );

 	void write_osc( int index, int reg, int old_data, int data );

-	const char* save_load( gb_apu_state_t*, bool save );

-	void save_load2( gb_apu_state_t*, bool save );

 	friend class Gb_Apu_Tester;

 public:

deleted file mode 100644

@@ -1,119 +0,0 @@

-// Gb_Snd_Emu $vers. http://www.slack.net/~ant/

-

-#include "Gb_Apu.h"

-

-#include <string.h>

-

-/* Copyright (C) 2007 Shay Green. This module is free software; you

-can redistribute it and/or modify it under the terms of the GNU Lesser

-General Public License as published by the Free Software Foundation; either

-version 2.1 of the License, or (at your option) any later version. This

-module is distributed in the hope that it will be useful, but WITHOUT ANY

-WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

-FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more

-details. You should have received a copy of the GNU Lesser General Public

-License along with this module; if not, write to the Free Software Foundation,

-Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */

-

-#include "blargg_source.h"

-

-#if GB_APU_CUSTOM_STATE

-	#define REFLECT( x, y ) (save ?       (io->y) = (x) :         (x) = (io->y)          )

-#else

-	#define REFLECT( x, y ) (save ? set_val( io->y, x ) : (void) ((x) = get_val( io->y )))

-

-	static blargg_ulong get_val( byte const* p )

-	{

-		return  p [3] * 0x1000000 + p [2] * 0x10000 + p [1] * 0x100 + p [0];

-	}

-

-	static void set_val( byte* p, blargg_ulong n )

-	{

-		p [0] = (byte) (n      );

-		p [1] = (byte) (n >>  8);

-		p [2] = (byte) (n >> 16);

-		p [3] = (byte) (n >> 24);

-	}

-#endif

-

-inline const char* Gb_Apu::save_load( gb_apu_state_t* io, bool save )

-{

-	#if !GB_APU_CUSTOM_STATE

-		assert( sizeof (gb_apu_state_t) == 256 );

-	#endif

-

-	int format = io->format0;

-	REFLECT( format, format );

-	if ( format != io->format0 )

-		return "Unsupported sound save state format";

-

-	int version = 0;

-	REFLECT( version, version );

-

-	// Registers and wave RAM

-	assert( regs_size == sizeof io->regs );

-	if ( save )

-		memcpy( io->regs, regs, sizeof io->regs );

-	else

-		memcpy( regs, io->regs, sizeof     regs );

-

-	// Frame sequencer

-	REFLECT( frame_time,  frame_time  );

-	REFLECT( frame_phase, frame_phase );

-

-	REFLECT( square1.sweep_freq,    sweep_freq );

-	REFLECT( square1.sweep_delay,   sweep_delay );

-	REFLECT( square1.sweep_enabled, sweep_enabled );

-	REFLECT( square1.sweep_neg,     sweep_neg );

-

-	REFLECT( noise.divider,         noise_divider );

-	REFLECT( wave.sample_buf,       wave_buf );

-

-	return 0;

-}

-

-// second function to avoid inline limits of some compilers

-inline void Gb_Apu::save_load2( gb_apu_state_t* io, bool save )

-{

-	for ( int i = osc_count; --i >= 0; )

-	{

-		Gb_Osc& osc = *oscs [i];

-		REFLECT( osc.delay,      delay      [i] );

-		REFLECT( osc.length_ctr, length_ctr [i] );

-		REFLECT( osc.phase,      phase      [i] );

-		REFLECT( osc.enabled,    enabled    [i] );

-

-		if ( i != 2 )

-		{

-			int j = min( i, 2 );

-			Gb_Env& env = STATIC_CAST(Gb_Env&,osc);

-			REFLECT( env.env_delay,   env_delay   [j] );

-			REFLECT( env.volume,      env_volume  [j] );

-			REFLECT( env.env_enabled, env_enabled [j] );

-		}

-	}

-}

-

-void Gb_Apu::save_state( gb_apu_state_t* out )

-{

-	(void) save_load( out, true );

-	save_load2( out, true );

-

-	#if !GB_APU_CUSTOM_STATE

-		memset( out->unused, 0, sizeof out->unused );

-	#endif

-}

-

-blargg_err_t Gb_Apu::load_state( gb_apu_state_t const& in )

-{

-	RETURN_ERR( save_load( CONST_CAST(gb_apu_state_t*,&in), false ) );

-	save_load2( CONST_CAST(gb_apu_state_t*,&in), false );

-

-	apply_stereo();

-	synth_volume( 0 );          // suppress output for the moment

-	run_until_( last_time );    // get last_amp updated

-	apply_volume();             // now use correct volume

-

-	return 0;

-}

-

@@ -4,13 +4,13 @@

 #include "Types.h"

 // swaps a 16-bit value

-static inline u16 swap16(u16 v)

+static inline uint16_t swap16(uint16_t v)

 {

   return (v<<8)|(v>>8);

 }

 // swaps a 32-bit value

-static inline u32 swap32(u32 v)

+static inline uint32_t swap32(uint32_t v)

 {

   return (v<<24)|((v<<8)&0xff0000)|((v>>8)&0xff00)|(v>>24);

 }

@@ -36,23 +36,23 @@ static inline u32 swap32(u32 v)

 #else

 #define READ16LE(x) \

-  swap16(*((u16 *)(x)))

+  swap16(*((uint16_t *)(x)))

 #define READ32LE(x) \

-  swap32(*((u32 *)(x)))

+  swap32(*((uint32_t *)(x)))

 #define WRITE16LE(x,v) \

-  *((u16 *)x) = swap16((v))

+  *((uint16_t *)x) = swap16((v))

 #define WRITE32LE(x,v) \

-  *((u32 *)x) = swap32((v))

+  *((uint32_t *)x) = swap32((v))

 #endif

 #else

 #define READ16LE(x) \

-  *((u16 *)x)

+  *((uint16_t *)x)

 #define READ32LE(x) \

-  *((u32 *)x)

+  *((uint32_t *)x)

 #define WRITE16LE(x,v) \

-  *((u16 *)x) = (v)

+  *((uint16_t *)x) = (v)

 #define WRITE32LE(x,v) \

-  *((u32 *)x) = (v)

+  *((uint32_t *)x) = (v)

 #endif

 #endif // PORT_H

@@ -57,7 +57,7 @@ public:

 	/**

 	 * Write length bytes of data from the finalWave buffer to the driver output buffer.

 	 */

-	virtual void write(u16 * finalWave, int length) = 0;

+	virtual void write(uint16_t * finalWave, int length) = 0;

 	virtual void setThrottle(unsigned short throttle) { };

 };

@@ -20,7 +20,7 @@

 #include <stdint.h>

-typedef uint8_t u8;

+/*typedef uint8_t u8;

 typedef uint16_t u16;

 typedef uint32_t u32;

 typedef uint64_t u64;

@@ -28,6 +28,6 @@ typedef uint64_t u64;

 typedef int8_t s8;

 typedef int16_t s16;

 typedef int32_t s32;

-typedef int64_t s64;

+typedef int64_t s64;*/

 #endif // __VBA_TYPES_H__

@@ -35,7 +35,7 @@

 static int clockTicks;

-static INSN_REGPARM void armUnknownInsn(u32 opcode)

+static INSN_REGPARM void armUnknownInsn(uint32_t opcode)

 {

 #ifdef GBA_LOGGING

     if (systemVerbose & VERBOSE_UNDEFINED) {

@@ -47,7 +47,7 @@ static INSN_REGPARM void armUnknownInsn(u32 opcode)

 }

 #ifdef BKPT_SUPPORT

-static INSN_REGPARM void armBreakpoint(u32 opcode)

+static INSN_REGPARM void armBreakpoint(uint32_t opcode)

 {

     reg[15].I -= 4;

     armNextPC -= 4;

@@ -60,7 +60,7 @@ static INSN_REGPARM void armBreakpoint(u32 opcode)

 // Subroutine to count instructions (for debugging/optimizing)

 //#define INSN_COUNTER  // comment out if you don't want it

 #ifdef INSN_COUNTER

-static void count(u32 opcode, int cond_res)

+static void count(uint32_t opcode, int cond_res)

 {

     static int insncount = 0;    // number of insns seen

     static int executed = 0;     // number of insns executed

@@ -716,11 +716,11 @@ static void count(u32 opcode, int cond_res)

 // C core

 #define C_SETCOND_LOGICAL \

-    N_FLAG = ((s32)res < 0) ? true : false;             \

+    N_FLAG = ((int32_t)res < 0) ? true : false;             \

     Z_FLAG = (res == 0) ? true : false;                 \

     C_FLAG = C_OUT;

 #define C_SETCOND_ADD \

-    N_FLAG = ((s32)res < 0) ? true : false;             \

+    N_FLAG = ((int32_t)res < 0) ? true : false;             \

     Z_FLAG = (res == 0) ? true : false;                 \

     V_FLAG = ((NEG(lhs) & NEG(rhs) & POS(res)) |        \

               (POS(lhs) & POS(rhs) & NEG(res))) ? true : false;\

@@ -728,7 +728,7 @@ static void count(u32 opcode, int cond_res)

               (NEG(lhs) & POS(res)) |                   \

               (NEG(rhs) & POS(res))) ? true : false;

 #define C_SETCOND_SUB \

-    N_FLAG = ((s32)res < 0) ? true : false;             \

+    N_FLAG = ((int32_t)res < 0) ? true : false;             \

     Z_FLAG = (res == 0) ? true : false;                 \

     V_FLAG = ((NEG(lhs) & POS(rhs) & POS(res)) |        \

               (POS(lhs) & NEG(rhs) & NEG(res))) ? true : false;\

@@ -740,7 +740,7 @@ static void count(u32 opcode, int cond_res)

  #define ALU_INIT_C \

     int dest = (opcode>>12) & 15;                       \

     bool C_OUT = C_FLAG;                                \

-    u32 value;

+    uint32_t value;

 #endif

 // OP Rd,Rb,Rm LSL #

 #ifndef VALUE_LSL_IMM_C

@@ -749,7 +749,7 @@ static void count(u32 opcode, int cond_res)

     if (LIKELY(!shift)) {  /* LSL #0 most common? */    \

         value = reg[opcode & 0x0F].I;                   \

     } else {                                            \

-        u32 v = reg[opcode & 0x0F].I;                   \

+        uint32_t v = reg[opcode & 0x0F].I;                   \

         C_OUT = (v >> (32 - shift)) & 1 ? true : false; \

         value = v << shift;                             \

     }

@@ -757,8 +757,8 @@ static void count(u32 opcode, int cond_res)

 // OP Rd,Rb,Rm LSL Rs

 #ifndef VALUE_LSL_REG_C

  #define VALUE_LSL_REG_C \

-    u32 shift = reg[(opcode >> 8)&15].B.B0;                  \

-    u32 rm = reg[opcode & 0x0F].I;                           \

+    uint32_t shift = reg[(opcode >> 8)&15].B.B0;                  \

+    uint32_t rm = reg[opcode & 0x0F].I;                           \

     if((opcode & 0x0F) == 15) {                              \

         rm += 4;                                             \

     }                                                        \

@@ -767,7 +767,7 @@ static void count(u32 opcode, int cond_res)

             value = 0;                                  \

             C_OUT = (rm & 1 ? true : false);                 \

         } else if (LIKELY(shift < 32)) {                \

-            u32 v = rm;                                      \

+            uint32_t v = rm;                                      \

             C_OUT = (v >> (32 - shift)) & 1 ? true : false;\

             value = v << shift;                         \

         } else {                                        \

@@ -781,9 +781,9 @@ static void count(u32 opcode, int cond_res)

 // OP Rd,Rb,Rm LSR #

 #ifndef VALUE_LSR_IMM_C

  #define VALUE_LSR_IMM_C \

-    u32 shift = (opcode >> 7) & 0x1F;                   \

+    uint32_t shift = (opcode >> 7) & 0x1F;                   \

     if (LIKELY(shift)) {                                \

-        u32 v = reg[opcode & 0x0F].I;                   \

+        uint32_t v = reg[opcode & 0x0F].I;                   \

         C_OUT = (v >> (shift - 1)) & 1 ? true : false;  \

         value = v >> shift;                             \

     } else {                                            \

@@ -795,7 +795,7 @@ static void count(u32 opcode, int cond_res)

 #ifndef VALUE_LSR_REG_C

  #define VALUE_LSR_REG_C \

     unsigned int shift = reg[(opcode >> 8)&15].B.B0;    \

-    u32 rm = reg[opcode & 0x0F].I;                      \

+    uint32_t rm = reg[opcode & 0x0F].I;                      \

     if((opcode & 0x0F) == 15) {                         \

         rm += 4;                                            \

     }                                                   \

@@ -804,7 +804,7 @@ static void count(u32 opcode, int cond_res)

             value = 0;                                  \

             C_OUT = (rm & 0x80000000 ? true : false);\

         } else if (LIKELY(shift < 32)) {                \

-            u32 v = rm;               \

+            uint32_t v = rm;               \

             C_OUT = (v >> (shift - 1)) & 1 ? true : false;\

             value = v >> shift;                         \

         } else {                                        \

@@ -821,7 +821,7 @@ static void count(u32 opcode, int cond_res)

     unsigned int shift = (opcode >> 7) & 0x1F;          \

     if (LIKELY(shift)) {                                \

         /* VC++ BUG: u32 v; (s32)v>>n is optimized to shr! */ \

-        s32 v = reg[opcode & 0x0F].I;                   \

+        int32_t v = reg[opcode & 0x0F].I;                   \

         C_OUT = (v >> (int)(shift - 1)) & 1 ? true : false;\

         value = v >> (int)shift;                        \

     } else {                                            \

@@ -838,13 +838,13 @@ static void count(u32 opcode, int cond_res)

 #ifndef VALUE_ASR_REG_C

  #define VALUE_ASR_REG_C \

     unsigned int shift = reg[(opcode >> 8)&15].B.B0;    \

-    u32 rm = reg[opcode & 0x0F].I;                      \

+    uint32_t rm = reg[opcode & 0x0F].I;                      \

     if((opcode & 0x0F) == 15) {                         \

         rm += 4;                                            \

     }                                                   \

     if (LIKELY(shift < 32)) {                           \

         if (LIKELY(shift)) {                            \

-            s32 v = rm;               \

+            int32_t v = rm;               \

             C_OUT = (v >> (int)(shift - 1)) & 1 ? true : false;\

             value = v >> (int)shift;                    \

         } else {                                        \

@@ -865,12 +865,12 @@ static void count(u32 opcode, int cond_res)

  #define VALUE_ROR_IMM_C \

     unsigned int shift = (opcode >> 7) & 0x1F;          \

     if (LIKELY(shift)) {                                \

-        u32 v = reg[opcode & 0x0F].I;                   \

+        uint32_t v = reg[opcode & 0x0F].I;                   \

         C_OUT = (v >> (shift - 1)) & 1 ? true : false;  \

         value = ((v << (32 - shift)) |                  \

                  (v >> shift));                         \

     } else {                                            \

-        u32 v = reg[opcode & 0x0F].I;                   \

+        uint32_t v = reg[opcode & 0x0F].I;                   \

         C_OUT = (v & 1) ? true : false;                 \

         value = ((v >> 1) |                             \

                  (C_FLAG << 31));                       \

@@ -880,12 +880,12 @@ static void count(u32 opcode, int cond_res)

 #ifndef VALUE_ROR_REG_C

  #define VALUE_ROR_REG_C \

     unsigned int shift = reg[(opcode >> 8)&15].B.B0;    \

-    u32 rm = reg[opcode & 0x0F].I;                      \

+    uint32_t rm = reg[opcode & 0x0F].I;                      \

     if((opcode & 0x0F) == 15) {                         \

         rm += 4;                                            \

     }                                                   \

     if (LIKELY(shift & 0x1F)) {                         \

-        u32 v = rm;                   \

+        uint32_t v = rm;                   \

         C_OUT = (v >> (shift - 1)) & 1 ? true : false;  \

         value = ((v << (32 - shift)) |                  \

                  (v >> shift));                         \

@@ -900,7 +900,7 @@ static void count(u32 opcode, int cond_res)

  #define VALUE_IMM_C \

     int shift = (opcode & 0xF00) >> 7;                  \

     if (UNLIKELY(shift)) {                              \

-        u32 v = opcode & 0xFF;                          \

+        uint32_t v = opcode & 0xFF;                          \

         C_OUT = (v >> (shift - 1)) & 1 ? true : false;  \

         value = ((v << (32 - shift)) |                  \

                  (v >> shift));                         \

@@ -945,7 +945,7 @@ static void count(u32 opcode, int cond_res)

 #define C_CHECK_PC(SETCOND) if (LIKELY(dest != 15)) { SETCOND }

 #ifndef OP_AND

  #define OP_AND \

-    u32 res = reg[(opcode>>16)&15].I & value;           \

+    uint32_t res = reg[(opcode>>16)&15].I & value;           \

     reg[dest].I = res;

 #endif

 #ifndef OP_ANDS

@@ -953,7 +953,7 @@ static void count(u32 opcode, int cond_res)

 #endif

 #ifndef OP_EOR

  #define OP_EOR \

-    u32 res = reg[(opcode>>16)&15].I ^ value;           \

+    uint32_t res = reg[(opcode>>16)&15].I ^ value;           \

     reg[dest].I = res;

 #endif

 #ifndef OP_EORS

@@ -961,9 +961,9 @@ static void count(u32 opcode, int cond_res)

 #endif

 #ifndef OP_SUB

  #define OP_SUB \

-    u32 lhs = reg[(opcode>>16)&15].I;                   \

-    u32 rhs = value;                                    \

-    u32 res = lhs - rhs;                                \

+    uint32_t lhs = reg[(opcode>>16)&15].I;                   \

+    uint32_t rhs = value;                                    \

+    uint32_t res = lhs - rhs;                                \

     reg[dest].I = res;

 #endif

 #ifndef OP_SUBS

@@ -971,9 +971,9 @@ static void count(u32 opcode, int cond_res)

 #endif

 #ifndef OP_RSB

  #define OP_RSB \

-    u32 lhs = value;                                    \

-    u32 rhs = reg[(opcode>>16)&15].I;                   \

-    u32 res = lhs - rhs;                                \

+    uint32_t lhs = value;                                    \

+    uint32_t rhs = reg[(opcode>>16)&15].I;                   \

+    uint32_t res = lhs - rhs;                                \

     reg[dest].I = res;

 #endif

 #ifndef OP_RSBS

@@ -981,9 +981,9 @@ static void count(u32 opcode, int cond_res)

 #endif

 #ifndef OP_ADD

  #define OP_ADD \

-    u32 lhs = reg[(opcode>>16)&15].I;                   \

-    u32 rhs = value;                                    \

-    u32 res = lhs + rhs;                                \

+    uint32_t lhs = reg[(opcode>>16)&15].I;                   \

+    uint32_t rhs = value;                                    \

+    uint32_t res = lhs + rhs;                                \

     reg[dest].I = res;

 #endif

 #ifndef OP_ADDS

@@ -991,9 +991,9 @@ static void count(u32 opcode, int cond_res)

 #endif

 #ifndef OP_ADC

  #define OP_ADC \

-    u32 lhs = reg[(opcode>>16)&15].I;                   \

-    u32 rhs = value;                                    \

-    u32 res = lhs + rhs + (u32)C_FLAG;                  \

+    uint32_t lhs = reg[(opcode>>16)&15].I;                   \

+    uint32_t rhs = value;                                    \

+    uint32_t res = lhs + rhs + (uint32_t)C_FLAG;                  \

     reg[dest].I = res;

 #endif

 #ifndef OP_ADCS

@@ -1001,9 +1001,9 @@ static void count(u32 opcode, int cond_res)

 #endif

 #ifndef OP_SBC

  #define OP_SBC \

-    u32 lhs = reg[(opcode>>16)&15].I;                   \

-    u32 rhs = value;                                    \

-    u32 res = lhs - rhs - !((u32)C_FLAG);               \

+    uint32_t lhs = reg[(opcode>>16)&15].I;                   \

+    uint32_t rhs = value;                                    \

+    uint32_t res = lhs - rhs - !((uint32_t)C_FLAG);               \

     reg[dest].I = res;

 #endif

 #ifndef OP_SBCS

@@ -1011,9 +1011,9 @@ static void count(u32 opcode, int cond_res)

 #endif

 #ifndef OP_RSC

  #define OP_RSC \

-    u32 lhs = value;                                    \

-    u32 rhs = reg[(opcode>>16)&15].I;                   \

-    u32 res = lhs - rhs - !((u32)C_FLAG);               \

+    uint32_t lhs = value;                                    \

+    uint32_t rhs = reg[(opcode>>16)&15].I;                   \

+    uint32_t res = lhs - rhs - !((uint32_t)C_FLAG);               \

     reg[dest].I = res;

 #endif

 #ifndef OP_RSCS

@@ -1021,31 +1021,31 @@ static void count(u32 opcode, int cond_res)

 #endif

 #ifndef OP_TST

  #define OP_TST \

-    u32 res = reg[(opcode >> 16) & 0x0F].I & value;     \

+    uint32_t res = reg[(opcode >> 16) & 0x0F].I & value;     \

     C_SETCOND_LOGICAL;

 #endif

 #ifndef OP_TEQ

  #define OP_TEQ \

-    u32 res = reg[(opcode >> 16) & 0x0F].I ^ value;     \

+    uint32_t res = reg[(opcode >> 16) & 0x0F].I ^ value;     \

     C_SETCOND_LOGICAL;

 #endif

 #ifndef OP_CMP

  #define OP_CMP \

-    u32 lhs = reg[(opcode>>16)&15].I;                   \

-    u32 rhs = value;                                    \

-    u32 res = lhs - rhs;                                \

+    uint32_t lhs = reg[(opcode>>16)&15].I;                   \

+    uint32_t rhs = value;                                    \

+    uint32_t res = lhs - rhs;                                \

     C_SETCOND_SUB;

 #endif

 #ifndef OP_CMN

  #define OP_CMN \

-    u32 lhs = reg[(opcode>>16)&15].I;                   \

-    u32 rhs = value;                                    \

-    u32 res = lhs + rhs;                                \

+    uint32_t lhs = reg[(opcode>>16)&15].I;                   \

+    uint32_t rhs = value;                                    \

+    uint32_t res = lhs + rhs;                                \

     C_SETCOND_ADD;

 #endif

 #ifndef OP_ORR

  #define OP_ORR \

-    u32 res = reg[(opcode >> 16) & 0x0F].I | value;     \

+    uint32_t res = reg[(opcode >> 16) & 0x0F].I | value;     \

     reg[dest].I = res;

 #endif

 #ifndef OP_ORRS

@@ -1053,7 +1053,7 @@ static void count(u32 opcode, int cond_res)

 #endif

 #ifndef OP_MOV

  #define OP_MOV \

-    u32 res = value;                                    \

+    uint32_t res = value;                                    \

     reg[dest].I = res;

 #endif

 #ifndef OP_MOVS

@@ -1061,7 +1061,7 @@ static void count(u32 opcode, int cond_res)

 #endif

 #ifndef OP_BIC

  #define OP_BIC \

-    u32 res = reg[(opcode >> 16) & 0x0F].I & (~value);  \

+    uint32_t res = reg[(opcode >> 16) & 0x0F].I & (~value);  \

     reg[dest].I = res;

 #endif

 #ifndef OP_BICS

@@ -1069,7 +1069,7 @@ static void count(u32 opcode, int cond_res)

 #endif

 #ifndef OP_MVN

  #define OP_MVN \

-    u32 res = ~value;                                   \

+    uint32_t res = ~value;                                   \

     reg[dest].I = res;

 #endif

 #ifndef OP_MVNS

@@ -1081,7 +1081,7 @@ static void count(u32 opcode, int cond_res)

 #endif

 #ifndef SETCOND_MUL

  #define SETCOND_MUL \

-     N_FLAG = ((s32)reg[dest].I < 0) ? true : false;    \

+     N_FLAG = ((int32_t)reg[dest].I < 0) ? true : false;    \

      Z_FLAG = reg[dest].I ? false : true;

 #endif

 #ifndef SETCOND_MULL

@@ -1096,7 +1096,7 @@ static void count(u32 opcode, int cond_res)

 #ifndef ROR_IMM_MSR

  #define ROR_IMM_MSR \

-    u32 v = opcode & 0xff;                              \

+    uint32_t v = opcode & 0xff;                              \

     value = ((v << (32 - shift)) | (v >> shift));

 #endif

 #ifndef ROR_OFFSET

@@ -1144,25 +1144,25 @@ static void count(u32 opcode, int cond_res)

 #define MODECHANGE_YES CPUSwitchMode(reg[17].I & 0x1f, false);

 #define DEFINE_ALU_INSN_C(CODE1, CODE2, OP, MODECHANGE) \

-  static INSN_REGPARM void arm##CODE1##0(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSL_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\

-  static INSN_REGPARM void arm##CODE1##1(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSL_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\

-  static INSN_REGPARM void arm##CODE1##2(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\

-  static INSN_REGPARM void arm##CODE1##3(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\

-  static INSN_REGPARM void arm##CODE1##4(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_ASR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\

-  static INSN_REGPARM void arm##CODE1##5(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_ASR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\

-  static INSN_REGPARM void arm##CODE1##6(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_ROR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\

-  static INSN_REGPARM void arm##CODE1##7(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_ROR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\

-  static INSN_REGPARM void arm##CODE2##0(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_IMM_C,     OP_##OP, MODECHANGE_##MODECHANGE, 0); }

+  static INSN_REGPARM void arm##CODE1##0(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSL_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\

+  static INSN_REGPARM void arm##CODE1##1(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSL_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\

+  static INSN_REGPARM void arm##CODE1##2(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\

+  static INSN_REGPARM void arm##CODE1##3(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\

+  static INSN_REGPARM void arm##CODE1##4(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_ASR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\

+  static INSN_REGPARM void arm##CODE1##5(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_ASR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\

+  static INSN_REGPARM void arm##CODE1##6(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_ROR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\

+  static INSN_REGPARM void arm##CODE1##7(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_ROR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\

+  static INSN_REGPARM void arm##CODE2##0(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_IMM_C,     OP_##OP, MODECHANGE_##MODECHANGE, 0); }

 #define DEFINE_ALU_INSN_NC(CODE1, CODE2, OP, MODECHANGE) \

-  static INSN_REGPARM void arm##CODE1##0(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSL_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\

-  static INSN_REGPARM void arm##CODE1##1(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSL_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\

-  static INSN_REGPARM void arm##CODE1##2(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\

-  static INSN_REGPARM void arm##CODE1##3(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\

-  static INSN_REGPARM void arm##CODE1##4(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ASR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\

-  static INSN_REGPARM void arm##CODE1##5(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ASR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\

-  static INSN_REGPARM void arm##CODE1##6(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ROR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\

-  static INSN_REGPARM void arm##CODE1##7(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ROR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\

-  static INSN_REGPARM void arm##CODE2##0(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_IMM_NC,     OP_##OP, MODECHANGE_##MODECHANGE, 0); }

+  static INSN_REGPARM void arm##CODE1##0(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSL_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\

+  static INSN_REGPARM void arm##CODE1##1(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSL_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\

+  static INSN_REGPARM void arm##CODE1##2(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\

+  static INSN_REGPARM void arm##CODE1##3(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\

+  static INSN_REGPARM void arm##CODE1##4(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ASR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\

+  static INSN_REGPARM void arm##CODE1##5(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ASR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\

+  static INSN_REGPARM void arm##CODE1##6(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ROR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\

+  static INSN_REGPARM void arm##CODE1##7(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ROR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\

+  static INSN_REGPARM void arm##CODE2##0(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_IMM_NC,     OP_##OP, MODECHANGE_##MODECHANGE, 0); }

 // AND

 DEFINE_ALU_INSN_NC(00, 20, AND,  NO)

@@ -1243,12 +1243,12 @@ DEFINE_ALU_INSN_C (1F, 3F, MVNS, YES)

 // CYCLES: base cycle count (1, 2, or 3)

 #define MUL_INSN(OP, SETCOND, CYCLES) \

     int mult = (opcode & 0x0F);                         \

-    u32 rs = reg[(opcode >> 8) & 0x0F].I;               \

+    uint32_t rs = reg[(opcode >> 8) & 0x0F].I;               \

     int acc = (opcode >> 12) & 0x0F;   /* or destLo */  \

     int dest = (opcode >> 16) & 0x0F;  /* or destHi */  \

     OP;                                                 \

     SETCOND;                                            \

-    if ((s32)rs < 0)                                    \

+    if ((int32_t)rs < 0)                                    \

         rs = ~rs;                                       \

     if ((rs & 0xFFFFFF00) == 0)                         \

         clockTicks += 0;                                \

@@ -1267,58 +1267,58 @@ DEFINE_ALU_INSN_C (1F, 3F, MVNS, YES)

 #define OP_MLA \

     reg[dest].I = reg[mult].I * rs + reg[acc].I;

 #define OP_MULL(SIGN) \

-    SIGN##64 res = (SIGN##64)(SIGN##32)reg[mult].I      \

-                 * (SIGN##64)(SIGN##32)rs;              \

-    reg[acc].I = (u32)res;                              \

-    reg[dest].I = (u32)(res >> 32);

+    SIGN##64_t res = (SIGN##64_t)(SIGN##32_t)reg[mult].I      \

+                 * (SIGN##64_t)(SIGN##32_t)rs;              \

+    reg[acc].I = (uint32_t)res;                              \

+    reg[dest].I = (uint32_t)(res >> 32);

 #define OP_MLAL(SIGN) \

-    SIGN##64 res = ((SIGN##64)reg[dest].I<<32 | reg[acc].I)\

-                 + ((SIGN##64)(SIGN##32)reg[mult].I     \

-                    * (SIGN##64)(SIGN##32)rs);          \

-    reg[acc].I = (u32)res;                              \

-    reg[dest].I = (u32)(res >> 32);

-#define OP_UMULL OP_MULL(u)

-#define OP_UMLAL OP_MLAL(u)

-#define OP_SMULL OP_MULL(s)

-#define OP_SMLAL OP_MLAL(s)

+    SIGN##64_t res = ((SIGN##64_t)reg[dest].I<<32 | reg[acc].I)\

+                 + ((SIGN##64_t)(SIGN##32_t)reg[mult].I     \

+                    * (SIGN##64_t)(SIGN##32_t)rs);          \

+    reg[acc].I = (uint32_t)res;                              \

+    reg[dest].I = (uint32_t)(res >> 32);

+#define OP_UMULL OP_MULL(uint)

+#define OP_UMLAL OP_MLAL(uint)

+#define OP_SMULL OP_MULL(int)

+#define OP_SMLAL OP_MLAL(int)

 // MUL Rd, Rm, Rs

-static INSN_REGPARM void arm009(u32 opcode) { MUL_INSN(OP_MUL, SETCOND_NONE, 1); }

+static INSN_REGPARM void arm009(uint32_t opcode) { MUL_INSN(OP_MUL, SETCOND_NONE, 1); }

 // MULS Rd, Rm, Rs

-static INSN_REGPARM void arm019(u32 opcode) { MUL_INSN(OP_MUL, SETCOND_MUL, 1); }

+static INSN_REGPARM void arm019(uint32_t opcode) { MUL_INSN(OP_MUL, SETCOND_MUL, 1); }

 // MLA Rd, Rm, Rs, Rn

-static INSN_REGPARM void arm029(u32 opcode) { MUL_INSN(OP_MLA, SETCOND_NONE, 2); }

+static INSN_REGPARM void arm029(uint32_t opcode) { MUL_INSN(OP_MLA, SETCOND_NONE, 2); }

 // MLAS Rd, Rm, Rs, Rn

-static INSN_REGPARM void arm039(u32 opcode) { MUL_INSN(OP_MLA, SETCOND_MUL, 2); }

+static INSN_REGPARM void arm039(uint32_t opcode) { MUL_INSN(OP_MLA, SETCOND_MUL, 2); }

 // UMULL RdLo, RdHi, Rn, Rs

-static INSN_REGPARM void arm089(u32 opcode) { MUL_INSN(OP_UMULL, SETCOND_NONE, 2); }

+static INSN_REGPARM void arm089(uint32_t opcode) { MUL_INSN(OP_UMULL, SETCOND_NONE, 2); }

 // UMULLS RdLo, RdHi, Rn, Rs

-static INSN_REGPARM void arm099(u32 opcode) { MUL_INSN(OP_UMULL, SETCOND_MULL, 2); }

+static INSN_REGPARM void arm099(uint32_t opcode) { MUL_INSN(OP_UMULL, SETCOND_MULL, 2); }

 // UMLAL RdLo, RdHi, Rn, Rs

-static INSN_REGPARM void arm0A9(u32 opcode) { MUL_INSN(OP_UMLAL, SETCOND_NONE, 3); }

+static INSN_REGPARM void arm0A9(uint32_t opcode) { MUL_INSN(OP_UMLAL, SETCOND_NONE, 3); }

 // UMLALS RdLo, RdHi, Rn, Rs

-static INSN_REGPARM void arm0B9(u32 opcode) { MUL_INSN(OP_UMLAL, SETCOND_MULL, 3); }

+static INSN_REGPARM void arm0B9(uint32_t opcode) { MUL_INSN(OP_UMLAL, SETCOND_MULL, 3); }

 // SMULL RdLo, RdHi, Rm, Rs

-static INSN_REGPARM void arm0C9(u32 opcode) { MUL_INSN(OP_SMULL, SETCOND_NONE, 2); }

+static INSN_REGPARM void arm0C9(uint32_t opcode) { MUL_INSN(OP_SMULL, SETCOND_NONE, 2); }

 // SMULLS RdLo, RdHi, Rm, Rs

-static INSN_REGPARM void arm0D9(u32 opcode) { MUL_INSN(OP_SMULL, SETCOND_MULL, 2); }

+static INSN_REGPARM void arm0D9(uint32_t opcode) { MUL_INSN(OP_SMULL, SETCOND_MULL, 2); }

 // SMLAL RdLo, RdHi, Rm, Rs

-static INSN_REGPARM void arm0E9(u32 opcode) { MUL_INSN(OP_SMLAL, SETCOND_NONE, 3); }

+static INSN_REGPARM void arm0E9(uint32_t opcode) { MUL_INSN(OP_SMLAL, SETCOND_NONE, 3); }

 // SMLALS RdLo, RdHi, Rm, Rs

-static INSN_REGPARM void arm0F9(u32 opcode) { MUL_INSN(OP_SMLAL, SETCOND_MULL, 3); }

+static INSN_REGPARM void arm0F9(uint32_t opcode) { MUL_INSN(OP_SMLAL, SETCOND_MULL, 3); }

 // Misc instructions //////////////////////////////////////////////////////

 // SWP Rd, Rm, [Rn]

-static INSN_REGPARM void arm109(u32 opcode)

+static INSN_REGPARM void arm109(uint32_t opcode)

 {

-    u32 address = reg[(opcode >> 16) & 15].I;

-    u32 temp = CPUReadMemory(address);

+    uint32_t address = reg[(opcode >> 16) & 15].I;

+    uint32_t temp = CPUReadMemory(address);

     CPUWriteMemory(address, reg[opcode&15].I);

     reg[(opcode >> 12) & 15].I = temp;

     clockTicks = 4 + dataTicksAccess32(address) + dataTicksAccess32(address)

@@ -1326,10 +1326,10 @@ static INSN_REGPARM void arm109(u32 opcode)

 }

 // SWPB Rd, Rm, [Rn]

-static INSN_REGPARM void arm149(u32 opcode)

+static INSN_REGPARM void arm149(uint32_t opcode)

 {

-    u32 address = reg[(opcode >> 16) & 15].I;

-    u32 temp = CPUReadByte(address);

+    uint32_t address = reg[(opcode >> 16) & 15].I;

+    uint32_t temp = CPUReadByte(address);

     CPUWriteByte(address, reg[opcode&15].B.B0);

     reg[(opcode>>12)&15].I = temp;

     clockTicks = 4 + dataTicksAccess32(address) + dataTicksAccess32(address)

@@ -1337,7 +1337,7 @@ static INSN_REGPARM void arm149(u32 opcode)

 }

 // MRS Rd, CPSR

-static INSN_REGPARM void arm100(u32 opcode)

+static INSN_REGPARM void arm100(uint32_t opcode)

 {

     if (LIKELY((opcode & 0x0FFF0FFF) == 0x010F0000)) {

         CPUUpdateCPSR();

@@ -1348,7 +1348,7 @@ static INSN_REGPARM void arm100(u32 opcode)

 }

 // MRS Rd, SPSR

-static INSN_REGPARM void arm140(u32 opcode)

+static INSN_REGPARM void arm140(uint32_t opcode)

 {

     if (LIKELY((opcode & 0x0FFF0FFF) == 0x014F0000)) {

         reg[(opcode >> 12) & 0x0F].I = reg[17].I;

@@ -1358,12 +1358,12 @@ static INSN_REGPARM void arm140(u32 opcode)

 }

 // MSR CPSR_fields, Rm

-static INSN_REGPARM void arm120(u32 opcode)

+static INSN_REGPARM void arm120(uint32_t opcode)

 {

     if (LIKELY((opcode & 0x0FF0FFF0) == 0x0120F000)) {

         CPUUpdateCPSR();

-        u32 value = reg[opcode & 15].I;

-        u32 newValue = reg[16].I;

+        uint32_t value = reg[opcode & 15].I;

+        uint32_t newValue = reg[16].I;

         if (armMode > 0x10) {

             if (opcode & 0x00010000)

                 newValue = (newValue & 0xFFFFFF00) | (value & 0x000000FF);

@@ -1388,10 +1388,10 @@ static INSN_REGPARM void arm120(u32 opcode)

 }

 // MSR SPSR_fields, Rm

-static INSN_REGPARM void arm160(u32 opcode)

+static INSN_REGPARM void arm160(uint32_t opcode)

 {

     if (LIKELY((opcode & 0x0FF0FFF0) == 0x0160F000)) {

-        u32 value = reg[opcode & 15].I;

+        uint32_t value = reg[opcode & 15].I;

         if (armMode > 0x10 && armMode < 0x1F) {

             if (opcode & 0x00010000)

                 reg[17].I = (reg[17].I & 0xFFFFFF00) | (value & 0x000000FF);

@@ -1408,16 +1408,16 @@ static INSN_REGPARM void arm160(u32 opcode)

 }

 // MSR CPSR_fields, #

-static INSN_REGPARM void arm320(u32 opcode)

+static INSN_REGPARM void arm320(uint32_t opcode)

 {

     if (LIKELY((opcode & 0x0FF0F000) == 0x0320F000)) {

         CPUUpdateCPSR();

-        u32 value = opcode & 0xFF;

+        uint32_t value = opcode & 0xFF;

         int shift = (opcode & 0xF00) >> 7;

         if (shift) {

             ROR_IMM_MSR;

         }

-        u32 newValue = reg[16].I;

+        uint32_t newValue = reg[16].I;

         if (armMode > 0x10) {

             if (opcode & 0x00010000)

                 newValue = (newValue & 0xFFFFFF00) | (value & 0x000000FF);

@@ -1444,11 +1444,11 @@ static INSN_REGPARM void arm320(u32 opcode)

 }

 // MSR SPSR_fields, #

-static INSN_REGPARM void arm360(u32 opcode)

+static INSN_REGPARM void arm360(uint32_t opcode)

 {

     if (LIKELY((opcode & 0x0FF0F000) == 0x0360F000)) {

         if (armMode > 0x10 && armMode < 0x1F) {

-            u32 value = opcode & 0xFF;

+            uint32_t value = opcode & 0xFF;

             int shift = (opcode & 0xF00) >> 7;

             if (shift) {

                 ROR_IMM_MSR;

@@ -1468,7 +1468,7 @@ static INSN_REGPARM void arm360(u32 opcode)

 }

 // BX Rm

-static INSN_REGPARM void arm121(u32 opcode)

+static INSN_REGPARM void arm121(uint32_t opcode)

 {

     if (LIKELY((opcode & 0x0FFFFFF0) == 0x012FFF10)) {

         int base = opcode & 0x0F;

@@ -1513,14 +1513,14 @@ static INSN_REGPARM void arm121(u32 opcode)

     int shift = (opcode >> 7) & 31;                     \

     int offset;                                         \

     if (shift)                                          \

-        offset = (int)((s32)reg[opcode & 15].I >> shift);\