Some times the port P1 look "crazy", this means an unexpected pattern is applied on this port and changed with high frequency. In some applications it can cause destruction of peripherals connected to this port.
This can occur only, if reset is active (high), XTAL is working (or external clock is applied) and P3.4 is used as a low driven input.
The described conditions are near on they, needed for reading out the FLASH (see data sheet), and with the clock on XTAL, the byte on the next address is reading out (so if the FLASH is erased, you can not see it). The state P3 = 1x1011xxb is not described in the data sheet and seems to work as well P3 = 1x1001xxb (read code data).
Use never P3.4 as an input and P1 as an output at the same time. Generally it is recommend to set both lock bits after programming. Then a "crazy" P1 occur only, if you apply the pattern for reading signature (P3 = 0x0001xxb). All other input pattern are not critical. The signature on 89C2051 can be read too, if the lock bits are set. The signature on 89C51/52 can only be read, if lock bits are erased.
"The state of port P1 is not defined during the 2051 in reset state. It is
not planned to change this in future."
This is in opposite to all other 51-devices. They are setting all their ports
to 0FFh while in reset.
This problem is known but not published by Atmel:
The first version of the new micro from Atmel (AT90S1300, not produced) used
the same programming algorithm. But the today avaiable AT90S1200 is changed
to reading only, if 12V was applied on RST. So the danger to conflict between
programming and working conditions was removed.
AT89C1051 (I think, but not tested)
Author: Peter Dannegger