It's not believable. Normally you need for both functions separate circuits. And now you can realize it with a simple low cost CMOS logic circuit (CD4536). It contains an oscillator with an selectable divider.
The oscillator works with a XTAL of 32.768kHz and the counter is set to a
low level time of 4sec. On normal operation the counter must be reset within
4sec. It must be done with P3.7 = 1 while P3.5 = 0. If not, then the output
goes high and generate a reset for the CPU. The high level activate the bypass
of the divider stage 2^8. And so the reset pulse duration is shorted to
15.625msec.
But a hanging program can cause a permanently high on P3.7. To avoid this
serve R2. It's value is low, so only the strong pull up on the low to high
transition of the port output can generate a watch dog reset. This occurs
only during the 2 XTAL periods after changing to high level. To do this the
instructions CLR P3.7 and SETB P3.7 must be executed within 4sec.
If no real time clock function is needed, the XTAL can be replaced by a RC
oscillator.
The CPU must count the time internal during normal operation. The comparator
on P1.0, P1.1 is used to detect a power fail state. It compares the input
voltage (P1.1) with the battery voltage (P1.0 = VCC). If power fail occurs,
the ports P1.0 and P3.5 are set to 1 and all other to 0 to reducing external
power consumption. Then the CPU goes in power down. At this time no watch
dog reset is executed and so all 4.015625sec the CPU leave the power down
by a watch dog reset. The task after this is to increment the internal clock
registers by 4.015625sec. Then must be checked, if the power fail state is
still in progress. In this case the power down state must be reentered. The
LED D3 indicate the power fail state by flashing during CPU reset. On return
of power it can need up to 4sec before the next CPU reset is generated and
normal operation is entered. The battery power consumption is about 30µAmp.
On a battery of 1Ah it can be powered over 4 years.
The transistor T1 prevent a resetting of the watchdog by leaving the power
down state of the CPU (all port are set to high on reset active).
In opposition to separate real time clocks you need a little more power to
calculate time every 4 seconds. But you avoid problems with synchronization
(some RTC's gives no time lower one second). Daylight saving time or 2000
years are not supported too on most RTC's. These problems can be removed
by completely time calculation inside the CPU.
The clock input of the CD4536 is realized by a Schmitt-trigger. Normally
need the standard RC oscillator circuit no trigger input, since the positive
feed back is realized over the capacitor. The trigger levels are different
for different manufacturers. This can cause different frequency on using
RC-oscillators. To build a XTAL-oscillator this input cant used, but there
is a second input without trigger characteristic (oscillator inhibit). So
the XTAL oscillator can build with it.
The 4536 contains an additional monostable stage. But on this stage input
is no trigger placed. So I have seen a high frequency oscillation of the
output, while the voltage on the capacitor of the monostable stage is rising.
So this stage is not usable.
To get a short reset pulse I have used the 8 divider stages bypass. So the
high duration is 1/256 of the low time. You can change the divider ratio
to a shorter 2sec low time. But the reset pulse is shorted in the same way
to 7.8125msec. You must check, if it is long enough to reset the CPU
properly.
The reset of the 4536 is done only in the strong pull up time of 2 XTAL cycles
of the CPU after changing an output from low to high level. On 4MHz this
time is 500nsec. On using higher XTAL's it can be to short for resetting
the 4536. On my tests the HCF4536 (ST) works right up to 24MHz CPU-clock
(= 83ns reset pulse).