1.0 link Ami Sapphire's Notices http://cwcyrix.nsupdate.info/gnu-social/public/ Clarissa Walker (amisapphire@cwcyrix.nsupdate.info) http://cwcyrix.nsupdate.info/gnu-social/public/index.php/amisapphire http://cwcyrix.nsupdate.info/gnu-social/public/notice/103 Made a schematic and PCB layout of my custom parallel buffered JTAG (Wiggler) device. From a technical standpoint, the schematic and PCB layout are finished, but I keep cleaning up the PCB layout. So far:<br /> <br /> * PCB routing mistakes regarding nSRST - fixed<br /> * Potential safety issue between the JTAG header and DC barrel jack - fixed<br /> * via sizes - changed<br /> * identification text labeling - now present