{"version":"1.0","provider_name":"Ami Sapphire's Notices","provider_url":"http:\/\/cwcyrix.nsupdate.info\/gnu-social\/public\/","type":"link","title":"Clarissa Walker (amisapphire@cwcyrix.nsupdate.info)'s status on Sunday, 04-Jun-2023 21:10:31 EDT","author_name":"Clarissa Walker (amisapphire@cwcyrix.nsupdate.info)","author_url":"http:\/\/cwcyrix.nsupdate.info\/gnu-social\/public\/index.php\/amisapphire","url":"http:\/\/cwcyrix.nsupdate.info\/gnu-social\/public\/notice\/103","html":"Made a schematic and PCB layout of my custom parallel buffered JTAG (Wiggler) device. From a technical standpoint, the schematic and PCB layout are finished, but I keep cleaning up the PCB layout. So far:<br \/>\n<br \/>\n* PCB routing mistakes regarding nSRST - fixed<br \/>\n* Potential safety issue between the JTAG header and DC barrel jack - fixed<br \/>\n* via sizes - changed<br \/>\n* identification text labeling - now present"}