Updating in_2sf to use a newish version of DeSmuME, 0.9.9 from SVN. Somewhat cleaned up as well, but not everything because it's a pain in the ass.
--- a/src/in_2sf/XSFConfig_2SF.cpp
+++ b/src/in_2sf/XSFConfig_2SF.cpp
@@ -1,7 +1,7 @@
/*
* xSF - 2SF configuration
* By Naram Qashat (CyberBotX) [cyberbotx@cyberbotx.com]
- * Last modification on 2013-03-30
+ * Last modification on 2013-04-17
*
* Partially based on the vio*sf framework
*/
@@ -12,6 +12,7 @@
#include "convert.h"
#include "BigSString.h"
#include "desmume/NDSSystem.h"
+#include "desmume/version.h"
enum
{
@@ -91,7 +92,7 @@
SendMessageW(GetDlgItem(hwndDlg, idInterpolation), CB_ADDSTRING, 0, reinterpret_cast<LPARAM>(L"Cosine Interpolation"));
SendMessageW(GetDlgItem(hwndDlg, idInterpolation), CB_SETCURSEL, this->interpolation, 0);
// Mutes
- for (int x = 0, numMutes = this->mutes.size(); x < numMutes; ++x)
+ for (size_t x = 0, numMutes = this->mutes.size(); x < numMutes; ++x)
{
SendMessageW(GetDlgItem(hwndDlg, idMutes), LB_ADDSTRING, 0, reinterpret_cast<LPARAM>((L"SPU " + wstringify(x + 1)).c_str()));
SendMessageW(GetDlgItem(hwndDlg, idMutes), LB_SETSEL, this->mutes[x], x);
@@ -108,14 +109,14 @@
{
SendMessageW(GetDlgItem(hwndDlg, idInterpolation), CB_SETCURSEL, XSFConfig_2SF::initInterpolation, 0);
auto tmpMutes = std::bitset<16>(XSFConfig_2SF::initMutes);
- for (int x = 0, numMutes = tmpMutes.size(); x < numMutes; ++x)
+ for (size_t x = 0, numMutes = tmpMutes.size(); x < numMutes; ++x)
SendMessageW(GetDlgItem(hwndDlg, idMutes), LB_SETSEL, tmpMutes[x], x);
}
void XSFConfig_2SF::SaveSpecificConfigDialog(HWND hwndDlg)
{
this->interpolation = static_cast<unsigned>(SendMessageW(GetDlgItem(hwndDlg, idInterpolation), CB_GETCURSEL, 0, 0));
- for (int x = 0, numMutes = this->mutes.size(); x < numMutes; ++x)
+ for (size_t x = 0, numMutes = this->mutes.size(); x < numMutes; ++x)
this->mutes[x] = !!SendMessageW(GetDlgItem(hwndDlg, idMutes), LB_GETSEL, x, 0);
}
@@ -124,7 +125,7 @@
if (!preLoad)
{
CommonSettings.spuInterpolationMode = static_cast<SPUInterpolationMode>(this->interpolation);
- for (int x = 0, numMutes = this->mutes.size(); x < numMutes; ++x)
+ for (size_t x = 0, numMutes = this->mutes.size(); x < numMutes; ++x)
CommonSettings.spu_muteChannels[x] = this->mutes[x];
}
}
@@ -132,6 +133,6 @@
void XSFConfig_2SF::About(HWND parent)
{
MessageBox(parent, (XSFConfig::commonName + L" v" + XSFConfig::versionNumber + L", using xSF Winamp plugin framework (based on the vio*sf plugins) by Naram Qashat (CyberBotX) [cyberbotx@cyberbotx.com]\n\n"
- L"Utilizes modified DeSmuME v0.9.8 for audio playback.").c_str(), (XSFConfig::commonName + L" v" + XSFConfig::versionNumber).c_str(), MB_OK);
+ L"Utilizes modified " + String(EMU_DESMUME_NAME_AND_VERSION()).GetWStr() + L" for audio playback.").c_str(), (XSFConfig::commonName + L" v" + XSFConfig::versionNumber).c_str(), MB_OK);
}
--- a/src/in_2sf/XSFPlayer_2SF.cpp
+++ b/src/in_2sf/XSFPlayer_2SF.cpp
@@ -1,13 +1,13 @@
/*
* xSF - 2SF Player
* By Naram Qashat (CyberBotX) [cyberbotx@cyberbotx.com]
- * Last modification on 2013-03-30
+ * Last modification on 2013-04-17
*
* Based on a modified vio2sf v0.22c
*
* Partially based on the vio*sf framework
*
- * Utilizes a modified DeSmuME v0.9.8 for playback
+ * Utilizes a modified DeSmuME v0.9.9 SVN for playback
* http://desmume.org/
*/
@@ -16,10 +16,7 @@
#include "convert.h"
#include "XSFPlayer.h"
#include "XSFCommon.h"
-#include "desmume/armcpu.h"
-#include "desmume/saves.h"
#include "desmume/NDSSystem.h"
-#include "desmume/cp15.h"
class XSFPlayer_2SF : public XSFPlayer
{
@@ -105,6 +102,8 @@
SNDIFMuteAudio,
SNDIFUnMuteAudio,
SNDIFSetVolume,
+ nullptr,
+ nullptr,
nullptr
};
@@ -217,6 +216,7 @@
gameInfo.loadData(reinterpret_cast<char *>(&this->rom[0]), this->rom.size() - 1);
}
+ CommonSettings.use_jit = true;
NDS_Reset();
execute = true;
--- a/src/in_2sf/desmume/FIFO.cpp
+++ b/src/in_2sf/desmume/FIFO.cpp
@@ -18,18 +18,14 @@
*/
#include <cstring>
-
#include "FIFO.h"
#include "armcpu.h"
-//#include "debug.h"
#include "mem.h"
#include "MMU.h"
#include "NDSSystem.h"
-//#include "gfx3d.h"
// ========================================================= IPC FIFO
-IPC_FIFO ipc_fifo[2]; // 0 - ARM9
- // 1 - ARM7
+IPC_FIFO ipc_fifo[2]; // 0 - ARM9, 1 - ARM7
void IPC_FIFOinit(uint8_t proc)
{
@@ -40,8 +36,9 @@
void IPC_FIFOsend(uint8_t proc, uint32_t val)
{
uint16_t cnt_l = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x184);
- if (!(cnt_l & IPCFIFOCNT_FIFOENABLE)) return; // FIFO disabled
- uint8_t proc_remote = proc ^ 1;
+ if (!(cnt_l & IPCFIFOCNT_FIFOENABLE))
+ return; // FIFO disabled
+ uint8_t proc_remote = proc ^ 1;
if (ipc_fifo[proc].size > 15)
{
@@ -52,20 +49,18 @@
uint16_t cnt_r = T1ReadWord(MMU.MMU_MEM[proc_remote][0x40], 0x184);
- //LOG("IPC%s send FIFO 0x%08X size %03i (l 0x%X, tail %02i) (r 0x%X, tail %02i)\n",
- // proc?"7":"9", val, ipc_fifo[proc].size, cnt_l, ipc_fifo[proc].tail, cnt_r, ipc_fifo[proc^1].tail);
-
- cnt_l &= 0xBFFC; // clear send empty bit & full
- cnt_r &= 0xBCFF; // set recv empty bit & full
+ cnt_l &= 0xBFFC; // clear send empty bit & full
+ cnt_r &= 0xBCFF; // set recv empty bit & full
ipc_fifo[proc].buf[ipc_fifo[proc].tail] = val;
- ipc_fifo[proc].tail++;
- ipc_fifo[proc].size++;
- if (ipc_fifo[proc].tail > 15) ipc_fifo[proc].tail = 0;
+ ++ipc_fifo[proc].tail;
+ ++ipc_fifo[proc].size;
+ if (ipc_fifo[proc].tail > 15)
+ ipc_fifo[proc].tail = 0;
if (ipc_fifo[proc].size > 15)
{
- cnt_l |= IPCFIFOCNT_SENDFULL; // set send full bit
- cnt_r |= IPCFIFOCNT_RECVFULL; // set recv full bit
+ cnt_l |= IPCFIFOCNT_SENDFULL; // set send full bit
+ cnt_r |= IPCFIFOCNT_RECVFULL; // set recv full bit
}
T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l);
@@ -80,12 +75,13 @@
uint32_t IPC_FIFOrecv(uint8_t proc)
{
uint16_t cnt_l = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x184);
- if (!(cnt_l & IPCFIFOCNT_FIFOENABLE)) return 0; // FIFO disabled
- uint8_t proc_remote = proc ^ 1;
+ if (!(cnt_l & IPCFIFOCNT_FIFOENABLE))
+ return 0; // FIFO disabled
+ uint8_t proc_remote = proc ^ 1;
uint32_t val = 0;
- if ( ipc_fifo[proc_remote].size == 0 ) // remote FIFO error
+ if (!ipc_fifo[proc_remote].size) // remote FIFO error
{
cnt_l |= IPCFIFOCNT_FIFOERROR;
T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l);
@@ -94,19 +90,16 @@
uint16_t cnt_r = T1ReadWord(MMU.MMU_MEM[proc_remote][0x40], 0x184);
- cnt_l &= 0xBCFF; // clear send full bit & empty
- cnt_r &= 0xBFFC; // set recv full bit & empty
+ cnt_l &= 0xBCFF; // clear send full bit & empty
+ cnt_r &= 0xBFFC; // set recv full bit & empty
val = ipc_fifo[proc_remote].buf[ipc_fifo[proc_remote].head];
- ipc_fifo[proc_remote].head++;
- ipc_fifo[proc_remote].size--;
- if (ipc_fifo[proc_remote].head > 15) ipc_fifo[proc_remote].head = 0;
+ ++ipc_fifo[proc_remote].head;
+ --ipc_fifo[proc_remote].size;
+ if (ipc_fifo[proc_remote].head > 15)
+ ipc_fifo[proc_remote].head = 0;
- //LOG("IPC%s recv FIFO 0x%08X size %03i (l 0x%X, tail %02i) (r 0x%X, tail %02i)\n",
- // proc?"7":"9", val, ipc_fifo[proc].size, cnt_l, ipc_fifo[proc].tail, cnt_r, ipc_fifo[proc^1].tail);
-
-
- if ( ipc_fifo[proc_remote].size == 0 ) // FIFO empty
+ if (!ipc_fifo[proc_remote].size) // FIFO empty
{
cnt_l |= IPCFIFOCNT_RECVEMPTY;
cnt_r |= IPCFIFOCNT_SENDEMPTY;
@@ -129,14 +122,14 @@
uint16_t cnt_r = T1ReadWord(MMU.MMU_MEM[proc^1][0x40], 0x184);
if (val & IPCFIFOCNT_FIFOERROR)
- {
- //at least SPP uses this, maybe every retail game
+ // at least SPP uses this, maybe every retail game
cnt_l &= ~IPCFIFOCNT_FIFOERROR;
- }
if (val & IPCFIFOCNT_SENDCLEAR)
{
- ipc_fifo[proc].head = 0; ipc_fifo[proc].tail = 0; ipc_fifo[proc].size = 0;
+ ipc_fifo[proc].head = 0;
+ ipc_fifo[proc].tail = 0;
+ ipc_fifo[proc].size = 0;
cnt_l |= IPCFIFOCNT_SENDEMPTY;
cnt_r |= IPCFIFOCNT_RECVEMPTY;
@@ -150,14 +143,12 @@
// IPCFIFOCNT_SENDIRQEN may have been set (and/or the fifo may have been cleared) so we may need to trigger this irq
// (this approach is used by libnds fifo system on occasion in fifoInternalSend, and began happening frequently for value32 with r4326)
- if (cnt_l & IPCFIFOCNT_SENDIRQEN)
- if (cnt_l & IPCFIFOCNT_SENDEMPTY)
- NDS_makeIrq(proc, IRQ_BIT_IPCFIFO_SENDEMPTY);
+ if ((cnt_l & IPCFIFOCNT_SENDIRQEN) && (cnt_l & IPCFIFOCNT_SENDEMPTY))
+ NDS_makeIrq(proc, IRQ_BIT_IPCFIFO_SENDEMPTY);
// IPCFIFOCNT_RECVIRQEN may have been set so we may need to trigger this irq
- if(cnt_l & IPCFIFOCNT_RECVIRQEN)
- if (!(cnt_l & IPCFIFOCNT_RECVEMPTY))
- NDS_makeIrq(proc, IRQ_BIT_IPCFIFO_RECVNONEMPTY);
+ if ((cnt_l & IPCFIFOCNT_RECVIRQEN) && !(cnt_l & IPCFIFOCNT_RECVEMPTY))
+ NDS_makeIrq(proc, IRQ_BIT_IPCFIFO_RECVNONEMPTY);
T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l);
T1WriteWord(MMU.MMU_MEM[proc^1][0x40], 0x184, cnt_r);
@@ -165,145 +156,3 @@
NDS_Reschedule();
}
-// ========================================================= GFX FIFO
-//GFX_PIPE gxPIPE;
-//GFX_FIFO gxFIFO;
-
-/*void GFX_PIPEclear()
-{
- gxPIPE.head = 0;
- gxPIPE.tail = 0;
- gxPIPE.size = 0;
-}*/
-
-/*void GFX_FIFOclear()
-{
- gxFIFO.head = 0;
- gxFIFO.tail = 0;
- gxFIFO.size = 0;
-}*/
-
-/*static void GXF_FIFO_handleEvents()
-{
- bool low = gxFIFO.size <= 127;
- bool lowchange = MMU_new.gxstat.fifo_low ^ low;
- MMU_new.gxstat.fifo_low = low;
- if(low) triggerDma(EDMAMode_GXFifo);
-
- bool empty = gxFIFO.size == 0;
- bool emptychange = MMU_new.gxstat.fifo_empty ^ empty;
- MMU_new.gxstat.fifo_empty = empty;
-
- if(emptychange||lowchange) NDS_Reschedule();
-}*/
-
-/*void GFX_FIFOsend(uint8_t cmd, uint32_t param)
-{
- if(cmd==0x41) {
- //int zzz=9;
- }
-
- //INFO("gxFIFO: send 0x%02X = 0x%08X (size %03i/0x%02X) gxstat 0x%08X\n", cmd, param, gxFIFO.size, gxFIFO.size, gxstat);
- //printf("fifo recv: %02X: %08X upto:%d\n",cmd,param,gxFIFO.size+1);
-
- //TODO - WOAH ! NOT HANDLING A TOO-BIG FIFO RIGHT NOW!
- //if (gxFIFO.size > 255)
- //{
- // GXF_FIFO_handleEvents();
- // //NEED TO HANDLE THIS!!!!!!!!!!!!!!!!!!!!!!!!!!
-
- // //gxstat |= 0x08000000; // busy
- // NDS_RescheduleGXFIFO(1);
- // //INFO("ERROR: gxFIFO is full (cmd 0x%02X = 0x%08X) (prev cmd 0x%02X = 0x%08X)\n", cmd, param, gxFIFO.cmd[255], gxFIFO.param[255]);
- // return;
- //}
-
-
- gxFIFO.cmd[gxFIFO.tail] = cmd;
- gxFIFO.param[gxFIFO.tail] = param;
- gxFIFO.tail++;
- gxFIFO.size++;
- if (gxFIFO.tail > HACK_GXIFO_SIZE-1) gxFIFO.tail = 0;
-
- if(gxFIFO.size>=HACK_GXIFO_SIZE) {
- printf("--FIFO FULL-- : %d\n",gxFIFO.size);
- }
-
- //gxstat |= 0x08000000; // set busy flag
-
- GXF_FIFO_handleEvents();
-
- NDS_RescheduleGXFIFO(1);
-}*/
-
-// this function used ONLY in gxFIFO
-/*bool GFX_PIPErecv(uint8_t *cmd, uint32_t *param)
-{
- //gxstat &= 0xF7FFFFFF; // clear busy flag
-
- if (gxFIFO.size == 0)
- {
- GXF_FIFO_handleEvents();
- return false;
- }
-
- *cmd = gxFIFO.cmd[gxFIFO.head];
- *param = gxFIFO.param[gxFIFO.head];
-
- gxFIFO.head++;
- gxFIFO.size--;
- if (gxFIFO.head > HACK_GXIFO_SIZE-1) gxFIFO.head = 0;
-
- GXF_FIFO_handleEvents();
-
- return true;
-}*/
-
-/*void GFX_FIFOcnt(uint32_t val)
-{
- ////INFO("gxFIFO: write cnt 0x%08X (prev 0x%08X) FIFO size %03i PIPE size %03i\n", val, gxstat, gxFIFO.size, gxPIPE.size);
-
- if (val & (1<<29)) // clear? (only in homebrew?)
- {
- GFX_PIPEclear();
- GFX_FIFOclear();
- return;
- }
-
- //zeromus says: what happened to clear stack?
- //if (val & (1<<15)) // projection stack pointer reset
- //{
- // gfx3d_ClearStack();
- // val &= 0xFFFF5FFF; // clear reset (bit15) & stack level (bit13)
- //}
-
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x600, val);
-}*/
-
-// ========================================================= DISP FIFO
-//DISP_FIFO disp_fifo;
-
-/*void DISP_FIFOinit()
-{
- memset(&disp_fifo, 0, sizeof(DISP_FIFO));
-}*/
-
-/*void DISP_FIFOsend(uint32_t val)
-{
- //INFO("DISP_FIFO send value 0x%08X (head 0x%06X, tail 0x%06X)\n", val, disp_fifo.head, disp_fifo.tail);
- disp_fifo.buf[disp_fifo.tail] = val;
- disp_fifo.tail++;
- if (disp_fifo.tail > 0x5FFF)
- disp_fifo.tail = 0;
-}*/
-
-/*uint32_t DISP_FIFOrecv()
-{
- //if (disp_fifo.tail == disp_fifo.head) return 0; // FIFO is empty
- uint32_t val = disp_fifo.buf[disp_fifo.head];
- disp_fifo.head++;
- if (disp_fifo.head > 0x5FFF)
- disp_fifo.head = 0;
- return val;
-}*/
-
--- a/src/in_2sf/desmume/FIFO.h
+++ b/src/in_2sf/desmume/FIFO.h
@@ -38,53 +38,5 @@
extern uint32_t IPC_FIFOrecv(uint8_t proc);
extern void IPC_FIFOcnt(uint8_t proc, uint16_t val);
-//=================================================== GFX FIFO
-
-//yeah, its oversize for now. thats a simpler solution
-//moon seems to overdrive the fifo with immediate dmas
-//i think this might be nintendo code too
-//static const uint32_t HACK_GXIFO_SIZE = 200000;
-
-/*struct GFX_FIFO
-{
- uint8_t cmd[HACK_GXIFO_SIZE];
- uint32_t param[HACK_GXIFO_SIZE];
-
- uint32_t head; // start position
- uint32_t tail; // tail
- uint32_t size; // size FIFO buffer
-};*/
-
-/*struct GFX_PIPE
-{
- uint8_t cmd[4];
- uint32_t param[4];
-
- uint8_t head;
- uint8_t tail;
- uint8_t size;
-};*/
-
-//extern GFX_PIPE gxPIPE;
-//extern GFX_FIFO gxFIFO;
-//extern void GFX_PIPEclear();
-//extern void GFX_FIFOclear();
-//extern void GFX_FIFOsend(uint8_t cmd, uint32_t param);
-//extern bool GFX_PIPErecv(uint8_t *cmd, uint32_t *param);
-//extern void GFX_FIFOcnt(uint32_t val);
-
-//=================================================== Display memory FIFO
-/*struct DISP_FIFO
-{
- uint32_t buf[0x6000]; // 256x192 32K color
- uint32_t head; // head
- uint32_t tail; // tail
-};*/
-
-//extern DISP_FIFO disp_fifo;
-//extern void DISP_FIFOinit();
-//extern void DISP_FIFOsend(uint32_t val);
-//extern uint32_t DISP_FIFOrecv();
-
#endif
--- a/src/in_2sf/desmume/MMU.cpp
+++ b/src/in_2sf/desmume/MMU.cpp
@@ -22,62 +22,46 @@
#include <cmath>
#include <cstring>
#include <cassert>
-
-#include "common.h"
-//#include "debug.h"
#include "NDSSystem.h"
#include "cp15.h"
-//#include "wifi.h"
#include "registers.h"
-//#include "render3D.h"
-//#include "gfx3d.h"
-//#include "rtc.h"
#include "mc.h"
-//#include "addons.h"
#include "slot1.h"
-//#include "mic.h"
-//#include "movie.h"
#include "readwrite.h"
#include "MMU_timing.h"
-//#undef min
-
-/*#ifdef DO_ASSERT_UNALIGNED
-#define ASSERT_UNALIGNED(x) assert(x)
-#else
-#define ASSERT_UNALIGNED(x)
-#endif*/
-
-//http://home.utah.edu/~nahaj/factoring/isqrt.c.html
-static uint64_t isqrt (uint64_t x) {
- uint64_t squaredbit, remainder, root;
-
- if (x<1) return 0;
-
- /* Load the binary constant 01 00 00 ... 00, where the number
- * of zero bits to the right of the single one bit
- * is even, and the one bit is as far left as is consistant
- * with that condition.)
- */
- squaredbit = (uint64_t) ((((uint64_t) ~0LL) >> 1) &
- ~(((uint64_t) ~0LL) >> 2));
- /* This portable load replaces the loop that used to be
- * here, and was donated by legalize@xmission.com
- */
-
- /* Form bits of the answer. */
- remainder = x; root = 0;
- while (squaredbit > 0) {
- if (remainder >= (squaredbit | root)) {
- remainder -= (squaredbit | root);
- root >>= 1; root |= squaredbit;
- } else {
- root >>= 1;
- }
- squaredbit >>= 2;
- }
-
- return root;
+// http://home.utah.edu/~nahaj/factoring/isqrt.c.html
+static uint64_t isqrt(uint64_t x)
+{
+ if (x < 1)
+ return 0;
+
+ /* Load the binary constant 01 00 00 ... 00, where the number
+ * of zero bits to the right of the single one bit
+ * is even, and the one bit is as far left as is consistant
+ * with that condition.)
+ */
+ uint64_t squaredbit = static_cast<uint64_t>((static_cast<uint64_t>(~0LL) >> 1) & ~(static_cast<uint64_t>(~0LL) >> 2));
+ /* This portable load replaces the loop that used to be
+ * here, and was donated by legalize@xmission.com
+ */
+
+ /* Form bits of the answer. */
+ uint64_t remainder = x, root = 0;
+ while (squaredbit > 0)
+ {
+ if (remainder >= (squaredbit | root))
+ {
+ remainder -= squaredbit | root;
+ root >>= 1;
+ root |= squaredbit;
+ }
+ else
+ root >>= 1;
+ squaredbit >>= 2;
+ }
+
+ return root;
}
uint32_t partie = 1;
@@ -85,83 +69,12 @@
uint32_t _MMU_MAIN_MEM_MASK16 = 0x3FFFFF & ~1;
uint32_t _MMU_MAIN_MEM_MASK32 = 0x3FFFFF & ~3;
-//#define _MMU_DEBUG
-
-/*#ifdef _MMU_DEBUG
-
-#include <stdarg.h>
-void mmu_log_debug_ARM9(uint32_t adr, const char *fmt, ...)
-{
- if (adr < 0x4000000) return;
-// if (adr > 0x4100014) return;
-//#if 1
- if (adr >= 0x4000000 && adr <= 0x400006E) return; // Display Engine A
- if (adr >= 0x40000B0 && adr <= 0x4000134) return; // DMA, Timers and Keypad
- if (adr >= 0x4000180 && adr <= 0x40001BC) return; // IPC/ROM
- if (adr >= 0x4000204 && adr <= 0x400024A) return; // Memory & IRQ control
- if (adr >= 0x4000280 && adr <= 0x4000306) return; // Maths
- if (adr >= 0x4000320 && adr <= 0x40006A3) return; // 3D dispaly engine
- if (adr >= 0x4001000 && adr <= 0x400106E) return; // Display Engine B
- if (adr >= 0x4100000 && adr <= 0x4100014) return; // IPC/ROM
-//#endif
- va_list list;
- char msg[512];
-
- memset(msg,0,512);
-
- va_start(list,fmt);
- _vsnprintf(msg,511,fmt,list);
- va_end(list);
-
- INFO("MMU ARM9 0x%08X: %s\n", adr, msg);
-}
-
-void mmu_log_debug_ARM7(uint32_t adr, const char *fmt, ...)
-{
- if (adr < 0x4000004) return;
- if (adr > 0x4808FFF) return;
-#if 1
- if (adr >= 0x4000004 && adr < 0x4000180) return; // ARM7 I/O Map
- if (adr >= 0x4000180 && adr <= 0x40001C4) return; // IPC/ROM
- if (adr >= 0x4000204 && adr <= 0x400030C) return; // Memory and IRQ Control
- if (adr >= 0x4000400 && adr <= 0x400051E) return; // Sound Registers
- if (adr >= 0x4100000 && adr <= 0x4100014) return; // IPC/ROM
- if (adr >= 0x4800000 && adr <= 0x4808FFF) return; // WLAN Registers
-#endif
- va_list list;
- char msg[512];
-
- memset(msg,0,512);
-
- va_start(list,fmt);
- _vsnprintf(msg,511,fmt,list);
- va_end(list);
-
- INFO("MMU ARM7 0x%08X: %s\n", adr, msg);
-
-}
-#else
-#define mmu_log_debug_ARM9(...)
-#define mmu_log_debug_ARM7(...)
-#endif*/
-
-
-//#define LOG_CARD
-//#define LOG_GPU
-//#define LOG_DMA
-//#define LOG_DMA2
-//#define LOG_DIV
-
-#define DUP2(x) x, x
-#define DUP4(x) x, x, x, x
-#define DUP8(x) x, x, x, x, x, x, x, x
-#define DUP16(x) x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x
-
MMU_struct MMU;
MMU_struct_new MMU_new;
MMU_struct_timing MMU_timing;
-uint8_t * MMU_struct::MMU_MEM[2][256] = {
+uint8_t *MMU_struct::MMU_MEM[2][256] =
+{
//arm9
{
/* 0X*/ DUP16(MMU.ARM9_ITCM),
@@ -173,8 +86,8 @@
/* 5X*/ DUP16(MMU.ARM9_VMEM),
/* 6X*/ DUP16(MMU.ARM9_LCD),
/* 7X*/ DUP16(MMU.ARM9_OAM),
- /* 8X*/ DUP16(NULL),
- /* 9X*/ DUP16(NULL),
+ /* 8X*/ DUP16(nullptr),
+ /* 9X*/ DUP16(nullptr),
/* AX*/ DUP16(MMU.UNUSED_RAM),
/* BX*/ DUP16(MMU.UNUSED_RAM),
/* CX*/ DUP16(MMU.UNUSED_RAM),
@@ -194,18 +107,19 @@
/* 5X*/ DUP16(MMU.UNUSED_RAM),
/* 6X*/ DUP16(MMU.ARM9_LCD),
/* 7X*/ DUP16(MMU.UNUSED_RAM),
- /* 8X*/ DUP16(NULL),
- /* 9X*/ DUP16(NULL),
+ /* 8X*/ DUP16(nullptr),
+ /* 9X*/ DUP16(nullptr),
/* AX*/ DUP16(MMU.UNUSED_RAM),
/* BX*/ DUP16(MMU.UNUSED_RAM),
/* CX*/ DUP16(MMU.UNUSED_RAM),
/* DX*/ DUP16(MMU.UNUSED_RAM),
/* EX*/ DUP16(MMU.UNUSED_RAM),
/* FX*/ DUP16(MMU.UNUSED_RAM)
- }
+ }
};
-uint32_t MMU_struct::MMU_MASK[2][256] = {
+uint32_t MMU_struct::MMU_MASK[2][256] =
+{
//arm9
{
/* 0X*/ DUP16(0x00007FFF),
@@ -246,438 +160,434 @@
/* DX*/ DUP16(0x00000003),
/* EX*/ DUP16(0x00000003),
/* FX*/ DUP16(0x00000003)
- }
+ }
};
-// this logic was moved to MMU_timing.h
-//CACHE_ALIGN
-//TWaitState MMU_struct::MMU_WAIT16[2][16] = {
-// { 1, 1, 1, 1, 1, 1, 1, 1, 5, 5, 5, 1, 1, 1, 1, 1 }, //arm9
-// { 1, 1, 1, 1, 1, 1, 1, 1, 5, 5, 5, 1, 1, 1, 1, 1 }, //arm7
-//};
-//
-//CACHE_ALIGN
-//TWaitState MMU_struct::MMU_WAIT32[2][16] = {
-// { 1, 1, 1, 1, 1, 2, 2, 1, 8, 8, 5, 1, 1, 1, 1, 1 }, //arm9
-// { 1, 1, 1, 1, 1, 1, 1, 1, 8, 8, 5, 1, 1, 1, 1, 1 }, //arm7
-//};
-
//////////////////////////////////////////////////////////////
-//-------------
-//VRAM MEMORY MAPPING
-//-------------
-//(Everything is mapped through to ARM9_LCD in blocks of 16KB)
-
-//for all of the below, values = 41 indicate unmapped memory
+// -------------
+// VRAM MEMORY MAPPING
+// -------------
+// (Everything is mapped through to ARM9_LCD in blocks of 16KB)
+
+// for all of the below, values = 41 indicate unmapped memory
static const uint8_t VRAM_PAGE_UNMAPPED = 41;
static const unsigned VRAM_LCDC_PAGES = 41;
uint8_t vram_lcdc_map[VRAM_LCDC_PAGES];
-//in the range of 0x06000000 - 0x06800000 in 16KB pages (the ARM9 vram mappable area)
-//this maps to 16KB pages in the LCDC buffer which is what will actually contain the data
+// in the range of 0x06000000 - 0x06800000 in 16KB pages (the ARM9 vram mappable area)
+// this maps to 16KB pages in the LCDC buffer which is what will actually contain the data
uint8_t vram_arm9_map[VRAM_ARM9_PAGES];
-//this chooses which banks are mapped in the 128K banks starting at 0x06000000 in ARM7
+// this chooses which banks are mapped in the 128K banks starting at 0x06000000 in ARM7
uint8_t vram_arm7_map[2];
-//----->
-//consider these later, for better recordkeeping, instead of using the uint8_t* in MMU
-
-////for each 128KB texture slot, this maps to a 16KB starting page in the LCDC buffer
-//#define VRAM_TEX_SLOTS 4
-//uint8_t vram_tex_map[VRAM_TEX_SLOTS];
-//
-////for each 16KB tex palette slot, this maps to a 16KB starting page in the LCDC buffer
-//#define VRAM_TEX_PALETTE_SLOTS 6
-//uint8_t vram_tex_palette_map[VRAM_TEX_PALETTE_SLOTS];
-
-//<---------
-
-
-//void MMU_VRAM_unmap_all();
-
-struct TVramBankInfo {
+struct TVramBankInfo
+{
uint8_t page_addr, num_pages;
};
-static const TVramBankInfo vram_bank_info[VRAM_BANKS] = {
- {0,8},
- {8,8},
- {16,8},
- {24,8},
- {32,4},
- {36,1},
- {37,1},
- {38,2},
- {40,1}
+static const TVramBankInfo vram_bank_info[VRAM_BANKS] =
+{
+ {0, 8},
+ {8, 8},
+ {16, 8},
+ {24, 8},
+ {32, 4},
+ {36, 1},
+ {37, 1},
+ {38, 2},
+ {40, 1}
};
-//this is to remind you that the LCDC mapping returns a strange value (not 0x06800000) as you would expect
-//in order to play nicely with the MMU address and mask tables
+// this is to remind you that the LCDC mapping returns a strange value (not 0x06800000) as you would expect
+// in order to play nicely with the MMU address and mask tables
static const uint32_t LCDC_HACKY_LOCATION = 0x06000000;
-//maps an ARM9 BG/OBJ or LCDC address into an LCDC address, and informs the caller of whether it isn't mapped
-//TODO - in cases where this does some mapping work, we could bypass the logic at the end of the _read* and _write* routines
-//this is a good optimization to consider
-//template<int PROCNUM>
-static inline uint32_t MMU_LCDmap(uint32_t addr, bool& unmapped, bool& restricted)
+static const uint32_t ARM7_HACKY_IWRAM_LOCATION = 0x03800000;
+static const uint32_t ARM7_HACKY_SIWRAM_LOCATION = 0x03000000;
+
+// maps an ARM9 BG/OBJ or LCDC address into an LCDC address, and informs the caller of whether it isn't mapped
+// TODO - in cases where this does some mapping work, we could bypass the logic at the end of the _read* and _write* routines
+// this is a good optimization to consider
+// NOTE - this whole approach is probably fundamentally wrong.
+// according to dasShiny research, its possible to map multiple banks to the same addresses. something more sophisticated would be needed.
+// however, it hasnt proven necessary yet for any known test case.
+template<int PROCNUM> static inline uint32_t MMU_LCDmap(uint32_t addr, bool &unmapped, bool &restricted)
{
unmapped = false;
- restricted = false; //this will track whether 8bit writes are allowed
-
- //in case the address is entirely outside of the interesting ranges
- if(addr < 0x06000000) return addr;
- if(addr >= 0x07000000) return addr;
-
- //shared wram mapping for arm7
- /*if(PROCNUM==ARMCPU_ARM7)
- {
- //necessary? not sure
- //addr &= 0x3FFFF;
- //addr += 0x06000000;
- uint32_t ofs = addr & 0x1FFFF;
- uint32_t bank = (addr >> 17)&1;
- if(vram_arm7_map[bank] == VRAM_PAGE_UNMAPPED)
- {
- unmapped = true;
- return 0;
- }
- return LCDC_HACKY_LOCATION + (vram_arm7_map[bank]<<14) + ofs;
- }*/
+ restricted = false; // this will track whether 8bit writes are allowed
+
+ // handle SIWRAM and non-shared IWRAM in here too, since it is quite similar to vram.
+ // in fact it is probably implemented with the same pieces of hardware.
+ // its sort of like arm7 non-shared IWRAM is lowest priority, and then SIWRAM goes on top.
+ // however, we implement it differently than vram in emulator for historical reasons.
+ // instead of keeping a page map like we do vram, we just have a list of all possible page maps (there are only 4 each for arm9 and arm7)
+ if (addr >= 0x03000000 && addr < 0x04000000)
+ {
+ // blocks 0,1,2,3 is arm7 non-shared IWRAM and blocks 4,5 is SIWRAM, and block 8 is un-mapped zeroes
+ int iwram_block_16k;
+ int iwram_offset = addr & 0x3FFF;
+ addr &= 0x00FFFFFF;
+ if (PROCNUM == ARMCPU_ARM7)
+ {
+ static const int arm7_siwram_blocks[][4][4] =
+ {
+ {
+ {0, 1, 2, 3}, //WRAMCNT = 0 -> map to IWRAM
+ {4, 4, 4, 4}, //WRAMCNT = 1 -> map to SIWRAM block 0
+ {5, 5, 5, 5}, //WRAMCNT = 2 -> map to SIWRAM block 1
+ {4, 5, 4, 5}, //WRAMCNT = 3 -> map to SIWRAM blocks 0,1
+ },
+ //high region; always maps to non-shared IWRAM
+ {
+ {0, 1, 2, 3},
+ {0, 1, 2, 3},
+ {0, 1, 2, 3},
+ {0, 1, 2, 3}
+ }
+ };
+ int region = (addr >> 23) & 1;
+ int block = (addr >> 14) & 3;
+ assert(region < 2);
+ assert(block < 4);
+ iwram_block_16k = arm7_siwram_blocks[region][MMU.WRAMCNT][block];
+ } //PROCNUM == ARMCPU_ARM7
+ else
+ {
+ // PROCNUM == ARMCPU_ARM9
+ static const int arm9_siwram_blocks[][4] =
+ {
+ {4, 5, 4, 5}, //WRAMCNT = 0 -> map to SIWRAM blocks 0,1
+ {5, 5, 5, 5}, //WRAMCNT = 1 -> map to SIWRAM block 1
+ {4, 4, 4, 4}, //WRAMCNT = 2 -> map to SIWRAM block 0
+ {8, 8, 8, 8}, //WRAMCNT = 3 -> unmapped
+ };
+ int block = (addr >> 14) & 3;
+ assert(block < 4);
+ iwram_block_16k = arm9_siwram_blocks[MMU.WRAMCNT][block];
+ }
+
+ switch (iwram_block_16k >> 2)
+ {
+ case 0: // arm7 non-shared IWRAM
+ return ARM7_HACKY_IWRAM_LOCATION + (iwram_block_16k << 14) + iwram_offset;
+ case 1: //SIWRAM
+ return ARM7_HACKY_SIWRAM_LOCATION + ((iwram_block_16k & 3) << 14) + iwram_offset;
+ case 2: //zeroes
+ CASE2:
+ unmapped = true;
+ return 0;
+ default:
+ assert(false); //how did this happen?
+ goto CASE2;
+ }
+ }
+
+ // in case the address is entirely outside of the interesting VRAM ranges
+ if (addr < 0x06000000)
+ return addr;
+ if (addr >= 0x07000000)
+ return addr;
restricted = true;
- //handle LCD memory mirroring
- if(addr>=0x068A4000)
+ // handle LCD memory mirroring
+ // TODO - this is gross! this should be renovated if the vram mapping is ever done in a more sophisticated way taking into account dasShiny research
+ if (addr >= 0x068A4000)
addr = 0x06800000 +
- //(addr%0xA4000); //yuck!! is this even how it mirrors? but we have to keep from overrunning the buffer somehow
- (addr&0x80000); //just as likely to be right (I have no clue how it should work) but faster.
+ //(addr % 0xA4000); // yuck!! is this even how it mirrors? but we have to keep from overrunning the buffer somehow
+ (addr & 0x80000); // just as likely to be right (I have no clue how it should work) but faster.
uint32_t vram_page;
uint32_t ofs = addr & 0x3FFF;
- //return addresses in LCDC range
- if(addr>=0x06800000)
- {
- //already in LCDC range. just look it up to see whether it is unmapped
- vram_page = (addr>>14)&63;
- assert(vram_page<VRAM_LCDC_PAGES);
+ // return addresses in LCDC range
+ if (addr >= 0x06800000)
+ {
+ // already in LCDC range. just look it up to see whether it is unmapped
+ vram_page = (addr >> 14) & 63;
+ assert(vram_page < VRAM_LCDC_PAGES);
vram_page = vram_lcdc_map[vram_page];
}
else
{
- //map addresses in BG/OBJ range to an LCDC range
- vram_page = (addr>>14)&(VRAM_ARM9_PAGES-1);
- assert(vram_page<VRAM_ARM9_PAGES);
+ // map addresses in BG/OBJ range to an LCDC range
+ vram_page = (addr >> 14) & (VRAM_ARM9_PAGES - 1);
+ assert(vram_page < VRAM_ARM9_PAGES);
vram_page = vram_arm9_map[vram_page];
}
- if(vram_page == VRAM_PAGE_UNMAPPED)
+ if (vram_page == VRAM_PAGE_UNMAPPED)
{
unmapped = true;
return 0;
}
else
- return LCDC_HACKY_LOCATION + (vram_page<<14) + ofs;
-}
-
-
-//#define LOG_VRAM_ERROR() LOG("No data for block %i MST %i\n", block, VRAMBankCnt & 0x07);
+ return LCDC_HACKY_LOCATION + (vram_page << 14) + ofs;
+}
VramConfiguration vramConfiguration;
-/*std::string VramConfiguration::describePurpose(Purpose p) {
- switch(p) {
- case OFF: return "OFF";
- case INVALID: return "INVALID";
- case ABG: return "ABG";
- case BBG: return "BBG";
- case AOBJ: return "AOBJ";
- case BOBJ: return "BOBJ";
- case LCDC: return "LCDC";
- case ARM7: return "ARM7";
- case TEX: return "TEX";
- case TEXPAL: return "TEXPAL";
- case ABGEXTPAL: return "ABGEXTPAL";
- case BBGEXTPAL: return "BBGEXTPAL";
- case AOBJEXTPAL: return "AOBJEXTPAL";
- case BOBJEXTPAL: return "BOBJEXTPAL";
- default: return "UNHANDLED CASE";
- }
-}
-
-std::string VramConfiguration::describe() {
- std::stringstream ret;
- for(int i=0;i<VRAM_BANKS;i++) {
- ret << (char)(i+'A') << ": " << banks[i].ofs << " " << describePurpose(banks[i].purpose) << std::endl;
- }
- return ret.str();
-}*/
-
-//maps the specified bank to LCDC
-static inline void MMU_vram_lcdc(const int bank)
-{
- for(int i=0;i<vram_bank_info[bank].num_pages;i++)
- {
- int page = vram_bank_info[bank].page_addr+i;
+// maps the specified bank to LCDC
+static inline void MMU_vram_lcdc(int bank)
+{
+ for (int i = 0; i < vram_bank_info[bank].num_pages; ++i)
+ {
+ int page = vram_bank_info[bank].page_addr + i;
vram_lcdc_map[page] = page;
}
}
-//maps the specified bank to ARM9 at the provided page offset
-static inline void MMU_vram_arm9(const int bank, const int offset)
-{
- for(int i=0;i<vram_bank_info[bank].num_pages;i++)
- {
- int page = vram_bank_info[bank].page_addr+i;
-
- vram_arm9_map[i+offset] = page;
- }
-}
-
-static inline uint8_t* MMU_vram_physical(const int page)
+// maps the specified bank to ARM9 at the provided page offset
+static inline void MMU_vram_arm9(int bank, int offset)
+{
+ for (int i = 0; i < vram_bank_info[bank].num_pages; ++i)
+ vram_arm9_map[i + offset] = vram_bank_info[bank].page_addr + i;
+}
+
+static inline uint8_t *MMU_vram_physical(int page)
{
return MMU.ARM9_LCD + (page/**ADDRESS_STEP_16KB*/);
}
-//todo - templateize
-static inline void MMU_VRAMmapRefreshBank(const int bank)
+// todo - templateize
+static inline void MMU_VRAMmapRefreshBank(int bank)
{
int block = bank;
- if(bank >= VRAM_BANK_H) block++;
+ if (bank >= VRAM_BANK_H)
+ ++block;
uint8_t VRAMBankCnt = T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x240 + block);
- //do nothing if the bank isnt enabled
+ // do nothing if the bank isnt enabled
uint8_t en = VRAMBankCnt & 0x80;
- if(!en) return;
-
- int mst,ofs=0;
- switch(bank) {
+ if (!en)
+ return;
+
+ int mst, ofs = 0;
+ switch (bank)
+ {
case VRAM_BANK_A:
case VRAM_BANK_B:
mst = VRAMBankCnt & 3;
- ofs = (VRAMBankCnt>>3) & 3;
- switch(mst)
+ ofs = (VRAMBankCnt >> 3) & 3;
+ switch (mst)
{
- case 0: //LCDC
- vramConfiguration.banks[bank].purpose = VramConfiguration::LCDC;
- MMU_vram_lcdc(bank);
- //if(ofs != 0) PROGINFO("Bank %i: MST %i OFS %i\n", mst, ofs);
- break;
- case 1: //ABG
- vramConfiguration.banks[bank].purpose = VramConfiguration::ABG;
- MMU_vram_arm9(bank,VRAM_PAGE_ABG+ofs*8);
- break;
- case 2: //AOBJ
- vramConfiguration.banks[bank].purpose = VramConfiguration::AOBJ;
- switch(ofs) {
- case 0:
- case 1:
- MMU_vram_arm9(bank,VRAM_PAGE_AOBJ+ofs*8);
+ case 0: // LCDC
+ vramConfiguration.banks[bank].purpose = VramConfiguration::LCDC;
+ MMU_vram_lcdc(bank);
break;
- //default:
- //PROGINFO("Unsupported ofs setting %d for engine A OBJ vram bank %c\n", ofs, 'A'+bank);
- }
- break;
- case 3: //texture
- vramConfiguration.banks[bank].purpose = VramConfiguration::TEX;
- MMU.texInfo.textureSlotAddr[ofs] = MMU_vram_physical(vram_bank_info[bank].page_addr);
- break;
- default: goto unsupported_mst;
+ case 1: // ABG
+ vramConfiguration.banks[bank].purpose = VramConfiguration::ABG;
+ MMU_vram_arm9(bank, VRAM_PAGE_ABG + ofs * 8);
+ break;
+ case 2: // AOBJ
+ vramConfiguration.banks[bank].purpose = VramConfiguration::AOBJ;
+ switch (ofs)
+ {
+ case 0:
+ case 1:
+ MMU_vram_arm9(bank, VRAM_PAGE_AOBJ + ofs * 8);
+ }
+ break;
+ case 3: // texture
+ vramConfiguration.banks[bank].purpose = VramConfiguration::TEX;
+ MMU.texInfo.textureSlotAddr[ofs] = MMU_vram_physical(vram_bank_info[bank].page_addr);
+ break;
+ default:
+ goto unsupported_mst;
}
break;
case VRAM_BANK_C:
case VRAM_BANK_D:
mst = VRAMBankCnt & 7;
- ofs = (VRAMBankCnt>>3) & 3;
- switch(mst)
+ ofs = (VRAMBankCnt >> 3) & 3;
+ switch (mst)
{
- case 0: //LCDC
- vramConfiguration.banks[bank].purpose = VramConfiguration::LCDC;
- MMU_vram_lcdc(bank);
- //if(ofs != 0) PROGINFO("Bank %i: MST %i OFS %i\n", mst, ofs);
- break;
- case 1: //ABG
- vramConfiguration.banks[bank].purpose = VramConfiguration::ABG;
- MMU_vram_arm9(bank,VRAM_PAGE_ABG+ofs*8);
- break;
- case 2: //arm7
- vramConfiguration.banks[bank].purpose = VramConfiguration::ARM7;
- if(bank == 2) T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) | 1);
- if(bank == 3) T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) | 2);
- switch(ofs) {
- case 0:
- case 1:
- vram_arm7_map[ofs] = vram_bank_info[bank].page_addr;
+ case 0: // LCDC
+ vramConfiguration.banks[bank].purpose = VramConfiguration::LCDC;
+ MMU_vram_lcdc(bank);
break;
- //default:
- //PROGINFO("Unsupported ofs setting %d for arm7 vram bank %c\n", ofs, 'A'+bank);
- }
-
- break;
- case 3: //texture
- vramConfiguration.banks[bank].purpose = VramConfiguration::TEX;
- MMU.texInfo.textureSlotAddr[ofs] = MMU_vram_physical(vram_bank_info[bank].page_addr);
- break;
- case 4: //BGB or BOBJ
- if(bank == VRAM_BANK_C) {
- vramConfiguration.banks[bank].purpose = VramConfiguration::BBG;
- MMU_vram_arm9(bank,VRAM_PAGE_BBG); //BBG
- } else {
- vramConfiguration.banks[bank].purpose = VramConfiguration::BOBJ;
- MMU_vram_arm9(bank,VRAM_PAGE_BOBJ); //BOBJ
- }
- //if(ofs != 0) PROGINFO("Bank %i: MST %i OFS %i\n", mst, ofs);
- break;
- default: goto unsupported_mst;
+ case 1: // ABG
+ vramConfiguration.banks[bank].purpose = VramConfiguration::ABG;
+ MMU_vram_arm9(bank, VRAM_PAGE_ABG + ofs * 8);
+ break;
+ case 2: // arm7
+ vramConfiguration.banks[bank].purpose = VramConfiguration::ARM7;
+ if (bank == 2)
+ T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) | 1);
+ if (bank == 3)
+ T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) | 2);
+ switch (ofs)
+ {
+ case 0:
+ case 1:
+ vram_arm7_map[ofs] = vram_bank_info[bank].page_addr;
+ }
+ break;
+ case 3: // texture
+ vramConfiguration.banks[bank].purpose = VramConfiguration::TEX;
+ MMU.texInfo.textureSlotAddr[ofs] = MMU_vram_physical(vram_bank_info[bank].page_addr);
+ break;
+ case 4: // BGB or BOBJ
+ if (bank == VRAM_BANK_C)
+ {
+ vramConfiguration.banks[bank].purpose = VramConfiguration::BBG;
+ MMU_vram_arm9(bank, VRAM_PAGE_BBG); // BBG
+ }
+ else
+ {
+ vramConfiguration.banks[bank].purpose = VramConfiguration::BOBJ;
+ MMU_vram_arm9(bank, VRAM_PAGE_BOBJ); // BOBJ
+ }
+ break;
+ default:
+ goto unsupported_mst;
}
break;
case VRAM_BANK_E:
mst = VRAMBankCnt & 7;
- //if(((VRAMBankCnt>>3)&3) != 0) PROGINFO("Bank %i: MST %i OFS %i\n", mst, ofs);
- switch(mst) {
- case 0: //LCDC
- vramConfiguration.banks[bank].purpose = VramConfiguration::LCDC;
- MMU_vram_lcdc(bank);
- break;
- case 1: //ABG
- vramConfiguration.banks[bank].purpose = VramConfiguration::ABG;
- MMU_vram_arm9(bank,VRAM_PAGE_ABG);
- break;
- case 2: //AOBJ
- vramConfiguration.banks[bank].purpose = VramConfiguration::AOBJ;
- MMU_vram_arm9(bank,VRAM_PAGE_AOBJ);
- break;
- case 3: //texture palette
- vramConfiguration.banks[bank].purpose = VramConfiguration::TEXPAL;
- MMU.texInfo.texPalSlot[0] = MMU_vram_physical(vram_bank_info[bank].page_addr);
- MMU.texInfo.texPalSlot[1] = MMU_vram_physical(vram_bank_info[bank].page_addr+1);
- MMU.texInfo.texPalSlot[2] = MMU_vram_physical(vram_bank_info[bank].page_addr+2);
- MMU.texInfo.texPalSlot[3] = MMU_vram_physical(vram_bank_info[bank].page_addr+3);
- break;
- case 4: //A BG extended palette
- vramConfiguration.banks[bank].purpose = VramConfiguration::ABGEXTPAL;
- MMU.ExtPal[0][0] = MMU_vram_physical(vram_bank_info[bank].page_addr);
- MMU.ExtPal[0][1] = MMU.ExtPal[0][0]/* + ADDRESS_STEP_8KB*/;
- MMU.ExtPal[0][2] = MMU.ExtPal[0][1]/* + ADDRESS_STEP_8KB*/;
- MMU.ExtPal[0][3] = MMU.ExtPal[0][2]/* + ADDRESS_STEP_8KB*/;
- break;
- default: goto unsupported_mst;
+ switch (mst)
+ {
+ case 0: // LCDC
+ vramConfiguration.banks[bank].purpose = VramConfiguration::LCDC;
+ MMU_vram_lcdc(bank);
+ break;
+ case 1: // ABG
+ vramConfiguration.banks[bank].purpose = VramConfiguration::ABG;
+ MMU_vram_arm9(bank, VRAM_PAGE_ABG);
+ break;
+ case 2: // AOBJ
+ vramConfiguration.banks[bank].purpose = VramConfiguration::AOBJ;
+ MMU_vram_arm9(bank, VRAM_PAGE_AOBJ);
+ break;
+ case 3: // texture palette
+ vramConfiguration.banks[bank].purpose = VramConfiguration::TEXPAL;
+ MMU.texInfo.texPalSlot[0] = MMU_vram_physical(vram_bank_info[bank].page_addr);
+ MMU.texInfo.texPalSlot[1] = MMU_vram_physical(vram_bank_info[bank].page_addr + 1);
+ MMU.texInfo.texPalSlot[2] = MMU_vram_physical(vram_bank_info[bank].page_addr + 2);
+ MMU.texInfo.texPalSlot[3] = MMU_vram_physical(vram_bank_info[bank].page_addr + 3);
+ break;
+ case 4: // ABG extended palette
+ vramConfiguration.banks[bank].purpose = VramConfiguration::ABGEXTPAL;
+ MMU.ExtPal[0][0] = MMU_vram_physical(vram_bank_info[bank].page_addr);
+ MMU.ExtPal[0][1] = MMU.ExtPal[0][0]/* + ADDRESS_STEP_8KB*/;
+ MMU.ExtPal[0][2] = MMU.ExtPal[0][1]/* + ADDRESS_STEP_8KB*/;
+ MMU.ExtPal[0][3] = MMU.ExtPal[0][2]/* + ADDRESS_STEP_8KB*/;
+ break;
+ default:
+ goto unsupported_mst;
}
break;
case VRAM_BANK_F:
- case VRAM_BANK_G: {
+ case VRAM_BANK_G:
+ {
mst = VRAMBankCnt & 7;
- ofs = (VRAMBankCnt>>3) & 3;
- const int pageofslut[] = {0,1,4,5};
- const int pageofs = pageofslut[ofs];
- switch(mst)
+ ofs = (VRAMBankCnt >> 3) & 3;
+ const int pageofslut[] = {0, 1, 4, 5};
+ int pageofs = pageofslut[ofs];
+ switch (mst)
{
- case 0: //LCDC
- vramConfiguration.banks[bank].purpose = VramConfiguration::LCDC;
- MMU_vram_lcdc(bank);
- //if(ofs != 0) PROGINFO("Bank %i: MST %i OFS %i\n", mst, ofs);
- break;
- case 1: //ABG
- vramConfiguration.banks[bank].purpose = VramConfiguration::ABG;
- MMU_vram_arm9(bank,VRAM_PAGE_ABG+pageofs);
- MMU_vram_arm9(bank,VRAM_PAGE_ABG+pageofs+2); //unexpected mirroring (required by spyro eternal night)
- break;
- case 2: //AOBJ
- vramConfiguration.banks[bank].purpose = VramConfiguration::AOBJ;
- MMU_vram_arm9(bank,VRAM_PAGE_AOBJ+pageofs);
- MMU_vram_arm9(bank,VRAM_PAGE_AOBJ+pageofs+2); //unexpected mirroring - I have no proof, but it is inferred from the ABG above
- break;
- case 3: //texture palette
- vramConfiguration.banks[bank].purpose = VramConfiguration::TEXPAL;
- MMU.texInfo.texPalSlot[pageofs] = MMU_vram_physical(vram_bank_info[bank].page_addr);
- break;
- case 4: //A BG extended palette
- switch(ofs) {
- case 0:
- case 1:
- vramConfiguration.banks[bank].purpose = VramConfiguration::ABGEXTPAL;
- MMU.ExtPal[0][ofs*2] = MMU_vram_physical(vram_bank_info[bank].page_addr);
- MMU.ExtPal[0][ofs*2+1] = MMU.ExtPal[0][ofs*2]/* + ADDRESS_STEP_8KB*/;
+ case 0: // LCDC
+ vramConfiguration.banks[bank].purpose = VramConfiguration::LCDC;
+ MMU_vram_lcdc(bank);
+ break;
+ case 1: // ABG
+ vramConfiguration.banks[bank].purpose = VramConfiguration::ABG;
+ MMU_vram_arm9(bank, VRAM_PAGE_ABG + pageofs);
+ MMU_vram_arm9(bank, VRAM_PAGE_ABG + pageofs + 2); // unexpected mirroring (required by spyro eternal night)
+ break;
+ case 2: // AOBJ
+ vramConfiguration.banks[bank].purpose = VramConfiguration::AOBJ;
+ MMU_vram_arm9(bank, VRAM_PAGE_AOBJ + pageofs);
+ MMU_vram_arm9(bank, VRAM_PAGE_AOBJ + pageofs + 2); // unexpected mirroring - I have no proof, but it is inferred from the ABG above
+ break;
+ case 3: // texture palette
+ vramConfiguration.banks[bank].purpose = VramConfiguration::TEXPAL;
+ MMU.texInfo.texPalSlot[pageofs] = MMU_vram_physical(vram_bank_info[bank].page_addr);
+ break;
+ case 4: // ABG extended palette
+ switch (ofs)
+ {
+ case 0:
+ case 1:
+ vramConfiguration.banks[bank].purpose = VramConfiguration::ABGEXTPAL;
+ MMU.ExtPal[0][ofs * 2] = MMU_vram_physical(vram_bank_info[bank].page_addr);
+ MMU.ExtPal[0][ofs * 2 + 1] = MMU.ExtPal[0][ofs * 2]/* + ADDRESS_STEP_8KB*/;
+ break;
+ default:
+ vramConfiguration.banks[bank].purpose = VramConfiguration::INVALID;
+ }
+ break;
+ case 5: // AOBJ extended palette
+ vramConfiguration.banks[bank].purpose = VramConfiguration::AOBJEXTPAL;
+ MMU.ObjExtPal[0][0] = MMU_vram_physical(vram_bank_info[bank].page_addr);
+ MMU.ObjExtPal[0][1] = MMU.ObjExtPal[0][1]/* + ADDRESS_STEP_8KB*/;
break;
default:
- vramConfiguration.banks[bank].purpose = VramConfiguration::INVALID;
- //PROGINFO("Unsupported ofs setting %d for engine A bgextpal vram bank %c\n", ofs, 'A'+bank);
- break;
- }
- break;
- case 5: //A OBJ extended palette
- vramConfiguration.banks[bank].purpose = VramConfiguration::AOBJEXTPAL;
- MMU.ObjExtPal[0][0] = MMU_vram_physical(vram_bank_info[bank].page_addr);
- MMU.ObjExtPal[0][1] = MMU.ObjExtPal[0][1]/* + ADDRESS_STEP_8KB*/;
- //if(ofs != 0) PROGINFO("Bank %i: MST %i OFS %i\n", mst, ofs);
- break;
- default: goto unsupported_mst;
+ goto unsupported_mst;
}
break;
}
case VRAM_BANK_H:
mst = VRAMBankCnt & 3;
- //if(((VRAMBankCnt>>3)&3) != 0) PROGINFO("Bank %i: MST %i OFS %i\n", mst, ofs);
- switch(mst)
+ switch (mst)
{
- case 0: //LCDC
- vramConfiguration.banks[bank].purpose = VramConfiguration::LCDC;
- MMU_vram_lcdc(bank);
- break;
- case 1: //BBG
- vramConfiguration.banks[bank].purpose = VramConfiguration::BBG;
- MMU_vram_arm9(bank,VRAM_PAGE_BBG);
- MMU_vram_arm9(bank,VRAM_PAGE_BBG + 4); //unexpected mirroring
- break;
- case 2: //B BG extended palette
- vramConfiguration.banks[bank].purpose = VramConfiguration::BBGEXTPAL;
- MMU.ExtPal[1][0] = MMU_vram_physical(vram_bank_info[bank].page_addr);
- MMU.ExtPal[1][1] = MMU.ExtPal[1][0]/* + ADDRESS_STEP_8KB*/;
- MMU.ExtPal[1][2] = MMU.ExtPal[1][1]/* + ADDRESS_STEP_8KB*/;
- MMU.ExtPal[1][3] = MMU.ExtPal[1][2]/* + ADDRESS_STEP_8KB*/;
- break;
- default: goto unsupported_mst;
+ case 0: // LCDC
+ vramConfiguration.banks[bank].purpose = VramConfiguration::LCDC;
+ MMU_vram_lcdc(bank);
+ break;
+ case 1: // BBG
+ vramConfiguration.banks[bank].purpose = VramConfiguration::BBG;
+ MMU_vram_arm9(bank, VRAM_PAGE_BBG);
+ MMU_vram_arm9(bank, VRAM_PAGE_BBG + 4); // unexpected mirroring
+ break;
+ case 2: // BBG extended palette
+ vramConfiguration.banks[bank].purpose = VramConfiguration::BBGEXTPAL;
+ MMU.ExtPal[1][0] = MMU_vram_physical(vram_bank_info[bank].page_addr);
+ MMU.ExtPal[1][1] = MMU.ExtPal[1][0]/* + ADDRESS_STEP_8KB*/;
+ MMU.ExtPal[1][2] = MMU.ExtPal[1][1]/* + ADDRESS_STEP_8KB*/;
+ MMU.ExtPal[1][3] = MMU.ExtPal[1][2]/* + ADDRESS_STEP_8KB*/;
+ break;
+ default:
+ goto unsupported_mst;
}
break;
case VRAM_BANK_I:
mst = VRAMBankCnt & 3;
- //if(((VRAMBankCnt>>3)&3) != 0) PROGINFO("Bank %i: MST %i OFS %i\n", mst, ofs);
- switch(mst)
+ switch (mst)
{
- case 0: //LCDC
- vramConfiguration.banks[bank].purpose = VramConfiguration::LCDC;
- MMU_vram_lcdc(bank);
- break;
- case 1: //BBG
- vramConfiguration.banks[bank].purpose = VramConfiguration::BBG;
- MMU_vram_arm9(bank,VRAM_PAGE_BBG+2);
- MMU_vram_arm9(bank,VRAM_PAGE_BBG+3); //unexpected mirroring
- break;
- case 2: //BOBJ
- vramConfiguration.banks[bank].purpose = VramConfiguration::BOBJ;
- MMU_vram_arm9(bank,VRAM_PAGE_BOBJ);
- MMU_vram_arm9(bank,VRAM_PAGE_BOBJ+1); //FF3 end scene (lens flare sprite) needs this as it renders a sprite off the end of the 16KB and back around
- break;
- case 3: //B OBJ extended palette
- vramConfiguration.banks[bank].purpose = VramConfiguration::BOBJEXTPAL;
- MMU.ObjExtPal[1][0] = MMU_vram_physical(vram_bank_info[bank].page_addr);
- MMU.ObjExtPal[1][1] = MMU.ObjExtPal[1][1]/* + ADDRESS_STEP_8KB*/;
- break;
- default: goto unsupported_mst;
+ case 0: // LCDC
+ vramConfiguration.banks[bank].purpose = VramConfiguration::LCDC;
+ MMU_vram_lcdc(bank);
+ break;
+ case 1: // BBG
+ vramConfiguration.banks[bank].purpose = VramConfiguration::BBG;
+ MMU_vram_arm9(bank, VRAM_PAGE_BBG + 2);
+ MMU_vram_arm9(bank, VRAM_PAGE_BBG + 3); // unexpected mirroring
+ break;
+ case 2: // BOBJ
+ vramConfiguration.banks[bank].purpose = VramConfiguration::BOBJ;
+ MMU_vram_arm9(bank, VRAM_PAGE_BOBJ);
+ MMU_vram_arm9(bank, VRAM_PAGE_BOBJ + 1); // FF3 end scene (lens flare sprite) needs this as it renders a sprite off the end of the 16KB and back around
+ break;
+ case 3: // BOBJ extended palette
+ vramConfiguration.banks[bank].purpose = VramConfiguration::BOBJEXTPAL;
+ MMU.ObjExtPal[1][0] = MMU_vram_physical(vram_bank_info[bank].page_addr);
+ MMU.ObjExtPal[1][1] = MMU.ObjExtPal[1][1]/* + ADDRESS_STEP_8KB*/;
+ break;
+ default:
+ goto unsupported_mst;
}
break;
-
-
- } //switch(bank)
+ } // switch(bank)
vramConfiguration.banks[bank].ofs = ofs;
@@ -685,7 +595,6 @@
unsupported_mst:
vramConfiguration.banks[bank].purpose = VramConfiguration::INVALID;
- //PROGINFO("Unsupported mst setting %d for vram bank %c\n", mst, 'A'+bank);
}
void MMU_VRAM_unmap_all()
@@ -695,12 +604,12 @@
vram_arm7_map[0] = VRAM_PAGE_UNMAPPED;
vram_arm7_map[1] = VRAM_PAGE_UNMAPPED;
- for(int i=0;i<VRAM_LCDC_PAGES;i++)
+ for (int i = 0; i < VRAM_LCDC_PAGES; ++i)
vram_lcdc_map[i] = VRAM_PAGE_UNMAPPED;
- for(int i=0;i<VRAM_ARM9_PAGES;i++)
+ for (int i = 0; i < VRAM_ARM9_PAGES; ++i)
vram_arm9_map[i] = VRAM_PAGE_UNMAPPED;
- for (int i = 0; i < 4; i++)
+ for (int i = 0; i < 4; ++i)
{
MMU.ExtPal[0][i] = MMU.blank_memory;
MMU.ExtPal[1][i] = MMU.blank_memory;
@@ -711,213 +620,161 @@
MMU.ObjExtPal[1][0] = MMU.blank_memory;
MMU.ObjExtPal[1][1] = MMU.blank_memory;
- for(int i=0;i<6;i++)
+ for (int i = 0; i < 6; ++i)
MMU.texInfo.texPalSlot[i] = MMU.blank_memory;
- for(int i=0;i<4;i++)
+ for (int i = 0; i < 4; ++i)
MMU.texInfo.textureSlotAddr[i] = MMU.blank_memory;
}
static inline void MMU_VRAMmapControl(uint8_t block, uint8_t VRAMBankCnt)
{
- //dont handle wram mappings in here
- if(block == 7) {
- //wram
- return;
- }
-
- //first, save the texture info so we can check it for changes and trigger purges of the texcache
+ // handle WRAM, first of all
+ if (block == 7)
+ {
+ MMU.WRAMCNT = VRAMBankCnt & 3;
+ return;
+ }
+
+ //f irst, save the texture info so we can check it for changes and trigger purges of the texcache
MMU_struct::TextureInfo oldTexInfo = MMU.texInfo;
- //unmap everything
+ // unmap everything
MMU_VRAM_unmap_all();
- //unmap VRAM_BANK_C and VRAM_BANK_D from arm7. theyll get mapped again in a moment if necessary
+ // unmap VRAM_BANK_C and VRAM_BANK_D from arm7. theyll get mapped again in a moment if necessary
T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, 0);
- //write the new value to the reg
+ // write the new value to the reg
T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x240 + block, VRAMBankCnt);
- //refresh all bank settings
- //these are enumerated so that we can tune the order they get applied
- //in order to emulate prioritization rules for memory regions
- //with multiple banks mapped.
- //We're probably still not mapping things 100% correctly, but this helped us get closer:
- //goblet of fire "care of magical creatures" maps I and D to BOBJ (the I is an accident)
- //and requires A to override it.
- //This may create other bugs....
+ // refresh all bank settings
+ // zero XX-XX-200X (long before jun 2012)
+ // these are enumerated so that we can tune the order they get applied
+ // in order to emulate prioritization rules for memory regions
+ // with multiple banks mapped.
+ // We're probably still not mapping things 100% correctly, but this helped us get closer:
+ // goblet of fire "care of magical creatures" maps I and D to BOBJ (the I is an accident)
+ // and requires A to override it.
+ // This may create other bugs....
MMU_VRAMmapRefreshBank(VRAM_BANK_I);
MMU_VRAMmapRefreshBank(VRAM_BANK_H);
MMU_VRAMmapRefreshBank(VRAM_BANK_G);
MMU_VRAMmapRefreshBank(VRAM_BANK_F);
MMU_VRAMmapRefreshBank(VRAM_BANK_E);
+ // zero 21-jun-2012
+ // tomwi's streaming music demo sets A and D to ABG (the A is an accident).
+ // in this case, D should get priority.
+ // this is somewhat risky. will it break other things?
+ MMU_VRAMmapRefreshBank(VRAM_BANK_A);
+ MMU_VRAMmapRefreshBank(VRAM_BANK_B);
+ MMU_VRAMmapRefreshBank(VRAM_BANK_C);
MMU_VRAMmapRefreshBank(VRAM_BANK_D);
- MMU_VRAMmapRefreshBank(VRAM_BANK_C);
- MMU_VRAMmapRefreshBank(VRAM_BANK_B);
- MMU_VRAMmapRefreshBank(VRAM_BANK_A);
//printf(vramConfiguration.describe().c_str());
//printf("vram remapped at vcount=%d\n",nds.VCount);
- //if texInfo changed, trigger notifications
- if(memcmp(&oldTexInfo,&MMU.texInfo,sizeof(MMU_struct::TextureInfo)))
- {
- //if(!nds.isIn3dVblank())
- // PROGINFO("Changing texture or texture palette mappings outside of 3d vblank\n");
- //gpu3D->NDS_3D_VramReconfigureSignal();
- }
-
- //-------------------------------
- //set up arm9 mirrorings
- //these are probably not entirely accurate. more study will be necessary.
- //in general, we find that it is not uncommon at all for games to accidentally do this.
+ // -------------------------------
+ // set up arm9 mirrorings
+ // these are probably not entirely accurate. more study will be necessary.
+ // in general, we find that it is not uncommon at all for games to accidentally do this.
//
- //being able to easily do these experiments was one of the primary motivations for this remake of the vram mapping system
-
- //see the "unexpected mirroring" comments above for some more mirroring
- //so far "unexpected mirrorings" are tested by combining these games:
- //despereaux - storybook subtitles
- //NSMB - world map sub screen
- //drill spirits EU - mission select (just for control purposes, as it doesnt use H or I)
- //...
- //note that the "unexpected mirroring" items above may at some point rely on being executed in a certain order.
- //(sequentially A..I)
-
- const int types[] = {VRAM_PAGE_ABG,VRAM_PAGE_BBG,VRAM_PAGE_AOBJ,VRAM_PAGE_BOBJ};
- const int sizes[] = {32,8,16,8};
- for(int t=0;t<4;t++)
- {
- //the idea here is to pad out the mirrored space with copies of the mappable area,
- //without respect to what is mapped within that mappable area.
- //we hope that this is correct in all cases
- //required for driller spirits in mission select (mapping is simple A,B,C,D to each purpose)
- const int size = sizes[t];
- const int mask = size-1;
- const int type = types[t];
- for(int i=size;i<128;i++)
- {
- const int page = type + i;
- vram_arm9_map[page] = vram_arm9_map[type+(i&mask)];
- }
-
- //attempt #1: screen corruption in drill spirits EU
- //it seems like these shouldnt pad out 128K banks (space beyond those should have remained unmapped)
- //int mirrorMask = -1;
- //int type = types[t];
- ////if(type==VRAM_PAGE_BOBJ) continue;
- //if(type==VRAM_PAGE_AOBJ) continue;
- //for(int i=0;i<128;i++)
- //{
- // int page = type + i;
- // if(vram_arm9_map[page] == VRAM_PAGE_UNMAPPED)
- // {
- // if(i==0) break; //can't mirror anything if theres nothing mapped!
- // if(mirrorMask == -1)
- // mirrorMask = i-1;
- // vram_arm9_map[page] = vram_arm9_map[type+(i&mirrorMask)];
- // }
- //}
- }
-
- //-------------------------------
+ // being able to easily do these experiments was one of the primary motivations for this remake of the vram mapping system
+
+ // see the "unexpected mirroring" comments above for some more mirroring
+ // so far "unexpected mirrorings" are tested by combining these games:
+ // despereaux - storybook subtitles
+ // NSMB - world map sub screen
+ // drill spirits EU - mission select (just for control purposes, as it doesnt use H or I)
+ // ...
+ // note that the "unexpected mirroring" items above may at some point rely on being executed in a certain order.
+ // (sequentially A..I)
+
+ const int types[] = { VRAM_PAGE_ABG, VRAM_PAGE_BBG, VRAM_PAGE_AOBJ, VRAM_PAGE_BOBJ };
+ const int sizes[] = {32, 8, 16, 8};
+ for (int t = 0; t < 4; ++t)
+ {
+ // the idea here is to pad out the mirrored space with copies of the mappable area,
+ // without respect to what is mapped within that mappable area.
+ // we hope that this is correct in all cases
+ // required for driller spirits in mission select (mapping is simple A,B,C,D to each purpose)
+ int size = sizes[t];
+ int mask = size - 1;
+ int type = types[t];
+ for (int i = size; i < 128; ++i)
+ {
+ int page = type + i;
+ vram_arm9_map[page] = vram_arm9_map[type + (i & mask)];
+ }
+ }
}
//////////////////////////////////////////////////////////////
//end vram
//////////////////////////////////////////////////////////////
-
-
-void MMU_Init() {
- //LOG("MMU init\n");
-
+void MMU_Init()
+{
memset(&MMU, 0, sizeof(MMU_struct));
MMU.CART_ROM = MMU.UNUSED_RAM;
- //MMU.DTCMRegion = 0x027C0000;
- //even though apps may change dtcm immediately upon startup, this is the correct hardware starting value:
+ // even though apps may change dtcm immediately upon startup, this is the correct hardware starting value:
MMU.DTCMRegion = 0x08000000;
MMU.ITCMRegion = 0x00000000;
IPC_FIFOinit(ARMCPU_ARM9);
IPC_FIFOinit(ARMCPU_ARM7);
- //GFX_PIPEclear();
- //GFX_FIFOclear();
- //DISP_FIFOinit();
new(&MMU_new) MMU_struct_new;
- mc_init(&MMU.fw, MC_TYPE_FLASH); /* init fw device */
+ mc_init(&MMU.fw, MC_TYPE_FLASH); /* init fw device */
mc_alloc(&MMU.fw, NDS_FW_SIZE_V1);
- MMU.fw.fp = NULL;
+ MMU.fw.fp = nullptr;
MMU.fw.isFirmware = true;
-
- // Init Backup Memory device, this should really be done when the rom is loaded
- //mc_init(&MMU.bupmem, MC_TYPE_AUTODETECT);
- //mc_alloc(&MMU.bupmem, 1);
- //MMU.bupmem.fp = NULL;
- //rtcInit();
- //addonsInit();
- //slot1Init();
- /*if(Mic_Init() == false)
- INFO("Microphone init failed.\n");
- else
- INFO("Microphone successfully inited.\n");*/
-}
-
-void MMU_DeInit() {
- //LOG("MMU deinit\n");
- /*if (MMU.fw.fp)
- fclose(MMU.fw.fp);*/
+}
+
+void MMU_DeInit()
+{
mc_free(&MMU.fw);
- //if (MMU.bupmem.fp)
- // fclose(MMU.bupmem.fp);
- //mc_free(&MMU.bupmem);
- //addonsClose();
- //slot1Close();
- //Mic_DeInit();
}
void MMU_Reset()
{
memset(MMU.ARM9_DTCM, 0, sizeof(MMU.ARM9_DTCM));
memset(MMU.ARM9_ITCM, 0, sizeof(MMU.ARM9_ITCM));
- memset(MMU.ARM9_LCD, 0, sizeof(MMU.ARM9_LCD));
- memset(MMU.ARM9_OAM, 0, sizeof(MMU.ARM9_OAM));
- memset(MMU.ARM9_REG, 0, sizeof(MMU.ARM9_REG));
+ memset(MMU.ARM9_LCD, 0, sizeof(MMU.ARM9_LCD));
+ memset(MMU.ARM9_OAM, 0, sizeof(MMU.ARM9_OAM));
+ memset(MMU.ARM9_REG, 0, sizeof(MMU.ARM9_REG));
memset(MMU.ARM9_VMEM, 0, sizeof(MMU.ARM9_VMEM));
- memset(MMU.MAIN_MEM, 0, sizeof(MMU.MAIN_MEM));
-
- memset(MMU.blank_memory, 0, sizeof(MMU.blank_memory));
- memset(MMU.UNUSED_RAM, 0, sizeof(MMU.UNUSED_RAM));
- memset(MMU.MORE_UNUSED_RAM, 0, sizeof(MMU.UNUSED_RAM));
-
- memset(MMU.ARM7_ERAM, 0, sizeof(MMU.ARM7_ERAM));
- memset(MMU.ARM7_REG, 0, sizeof(MMU.ARM7_REG));
- memset(MMU.ARM7_WIRAM, 0, sizeof(MMU.ARM7_WIRAM));
- memset(MMU.SWIRAM, 0, sizeof(MMU.SWIRAM));
+ memset(MMU.MAIN_MEM, 0, sizeof(MMU.MAIN_MEM));
+
+ memset(MMU.blank_memory, 0, sizeof(MMU.blank_memory));
+ memset(MMU.UNUSED_RAM, 0, sizeof(MMU.UNUSED_RAM));
+ memset(MMU.MORE_UNUSED_RAM, 0, sizeof(MMU.UNUSED_RAM));
+
+ memset(MMU.ARM7_ERAM, 0, sizeof(MMU.ARM7_ERAM));
+ memset(MMU.ARM7_REG, 0, sizeof(MMU.ARM7_REG));
+ memset(MMU.ARM7_WIRAM, 0, sizeof(MMU.ARM7_WIRAM));
+ memset(MMU.SWIRAM, 0, sizeof(MMU.SWIRAM));
IPC_FIFOinit(ARMCPU_ARM9);
IPC_FIFOinit(ARMCPU_ARM7);
- //GFX_PIPEclear();
- //GFX_FIFOclear();
- //DISP_FIFOinit();
MMU.DTCMRegion = 0x027C0000;
MMU.ITCMRegion = 0x00000000;
- memset(MMU.timer, 0, sizeof(uint16_t) * 2 * 4);
- memset(MMU.timerMODE, 0, sizeof(int32_t) * 2 * 4);
- memset(MMU.timerON, 0, sizeof(uint32_t) * 2 * 4);
- memset(MMU.timerRUN, 0, sizeof(uint32_t) * 2 * 4);
- memset(MMU.timerReload, 0, sizeof(uint16_t) * 2 * 4);
-
- memset(MMU.reg_IME, 0, sizeof(uint32_t) * 2);
- memset(MMU.reg_IE, 0, sizeof(uint32_t) * 2);
- memset(MMU.reg_IF_bits, 0, sizeof(uint32_t) * 2);
- memset(MMU.reg_IF_pending, 0, sizeof(uint32_t) * 2);
-
- memset(MMU.dscard, 0, sizeof(nds_dscard) * 2);
+ memset(MMU.timer, 0, sizeof(uint16_t) * 8);
+ memset(MMU.timerMODE, 0, sizeof(int32_t) * 8);
+ memset(MMU.timerON, 0, sizeof(uint32_t) * 8);
+ memset(MMU.timerRUN, 0, sizeof(uint32_t) * 8);
+ memset(MMU.timerReload, 0, sizeof(uint16_t) * 8);
+
+ memset(MMU.reg_IME, 0, sizeof(uint32_t) * 2);
+ memset(MMU.reg_IE, 0, sizeof(uint32_t) * 2);
+ memset(MMU.reg_IF_bits, 0, sizeof(uint32_t) * 2);
+ memset(MMU.reg_IF_pending, 0, sizeof(uint32_t) * 2);
+
+ memset(MMU.dscard, 0, sizeof(nds_dscard) * 2);
MMU.divRunning = 0;
MMU.divResult = 0;
@@ -931,11 +788,10 @@
MMU.SPI_CNT = 0;
MMU.AUX_SPI_CNT = 0;
+ MMU.WRAMCNT = 0;
+
// Enable the sound speakers
T1WriteWord(MMU.ARM7_REG, 0x304, 0x0001);
-
- //MainScreen.offset = 0;
- //SubScreen.offset = 192;
MMU_VRAM_unmap_all();
@@ -946,12 +802,7 @@
MMU.powerMan_Reg[2] = 0x01;
MMU.powerMan_Reg[3] = 0x00;
- //rtcInit();
partie = 1;
- //addonsReset();
- //slot1Reset();
- //Mic_Reset();
- //MMU.gfx3dCycles = 0;
memset(MMU.dscard[ARMCPU_ARM9].command, 0, 8);
MMU.dscard[ARMCPU_ARM9].address = 0;
@@ -963,18 +814,12 @@
MMU.dscard[ARMCPU_ARM7].transfer_count = 0;
MMU.dscard[ARMCPU_ARM7].mode = CardMode_Normal;
- //HACK!!!
- //until we improve all our session tracking stuff, we need to save the backup memory filename
+ // HACK!!!
+ // until we improve all our session tracking stuff, we need to save the backup memory filename
std::string bleh = MMU_new.backupDevice.getFilename();
BackupDevice tempBackupDevice;
- //bool bleh2 = MMU_new.backupDevice.isMovieMode;
- //if(bleh2) tempBackupDevice = MMU_new.backupDevice;
reconstruct(&MMU_new);
- /*if(bleh2) {
- MMU_new.backupDevice = tempBackupDevice;
- MMU_new.backupDevice.reset_hardware();
- }
- else*/ MMU_new.backupDevice.load_rom(bleh.c_str());
+ MMU_new.backupDevice.load_rom(bleh);
MMU_timing.arm7codeFetch.Reset();
MMU_timing.arm7dataFetch.Reset();
@@ -984,39 +829,47 @@
MMU_timing.arm9dataCache.Reset();
}
-void SetupMMU(bool debugConsole, bool dsi) {
- if(debugConsole) _MMU_MAIN_MEM_MASK = 0x7FFFFF;
- else _MMU_MAIN_MEM_MASK = 0x3FFFFF;
- if(dsi) _MMU_MAIN_MEM_MASK = 0xFFFFFF;
+void SetupMMU(bool debugConsole, bool dsi)
+{
+ if (debugConsole)
+ _MMU_MAIN_MEM_MASK = 0x7FFFFF;
+ else
+ _MMU_MAIN_MEM_MASK = 0x3FFFFF;
+ if (dsi)
+ _MMU_MAIN_MEM_MASK = 0xFFFFFF;
_MMU_MAIN_MEM_MASK16 = _MMU_MAIN_MEM_MASK & ~1;
_MMU_MAIN_MEM_MASK32 = _MMU_MAIN_MEM_MASK & ~3;
}
-void MMU_setRom(uint8_t * rom, uint32_t)
+void MMU_setRom(uint8_t *rom, uint32_t)
{
MMU.CART_ROM = rom;
}
void MMU_unsetRom()
{
- MMU.CART_ROM=MMU.UNUSED_RAM;
-}
-
-static void execsqrt() {
+ MMU.CART_ROM = MMU.UNUSED_RAM;
+}
+
+static void execsqrt()
+{
uint32_t ret;
uint8_t mode = MMU_new.sqrt.mode;
MMU_new.sqrt.busy = 1;
- if (mode) {
+ if (mode)
+ {
uint64_t v = T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8);
- ret = (uint32_t)isqrt(v);
- } else {
+ ret = static_cast<uint32_t>(isqrt(v));
+ }
+ else
+ {
uint32_t v = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8);
- ret = (uint32_t)isqrt(v);
- }
-
- //clear the result while the sqrt unit is busy
- //todo - is this right? is it reasonable?
+ ret = static_cast<uint32_t>(isqrt(v));
+ }
+
+ // clear the result while the sqrt unit is busy
+ // todo - is this right? is it reasonable?
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B4, 0);
MMU.sqrtCycles = nds_timer + 26;
@@ -1025,42 +878,41 @@
NDS_Reschedule();
}
-static void execdiv() {
-
- int64_t num,den;
- int64_t res,mod;
+static void execdiv()
+{
+ int64_t num, den;
+ int64_t res, mod;
uint8_t mode = MMU_new.div.mode;
MMU_new.div.busy = 1;
MMU_new.div.div0 = 0;
- switch(mode)
- {
- case 0: // 32/32
- num = (int64_t) (int32_t) T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);
- den = (int64_t) (int32_t) T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);
- MMU.divCycles = nds_timer + 36;
- break;
- case 1: // 64/32
- case 3: //gbatek says this is same as mode 1
- num = (int64_t) T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);
- den = (int64_t) (int32_t) T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);
- MMU.divCycles = nds_timer + 68;
- break;
- case 2: // 64/64
- default:
- num = (int64_t) T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);
- den = (int64_t) T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);
- MMU.divCycles = nds_timer + 68;
- break;
- }
-
- if(den==0)
- {
- res = ((num < 0) ? 1 : -1);
+ switch (mode)
+ {
+ case 0: // 32/32
+ num = static_cast<int64_t>(static_cast<int32_t>(T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290)));
+ den = static_cast<int64_t>(static_cast<int32_t>(T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298)));
+ MMU.divCycles = nds_timer + 36;
+ break;
+ case 1: // 64/32
+ case 3: //gbatek says this is same as mode 1
+ num = static_cast<int64_t>(T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290));
+ den = static_cast<int64_t>(static_cast<int32_t>(T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298)));
+ MMU.divCycles = nds_timer + 68;
+ break;
+ case 2: // 64/64
+ default:
+ num = static_cast<int64_t>(T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290));
+ den = static_cast<int64_t>(T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298));
+ MMU.divCycles = nds_timer + 68;
+ }
+
+ if (!den)
+ {
+ res = num < 0 ? 1 : -1;
mod = num;
// the DIV0 flag in DIVCNT is set only if the full 64bit DIV_DENOM value is zero, even in 32bit mode
- if ((uint64_t)T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298) == 0)
+ if (!static_cast<uint64_t>(T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298)))
MMU_new.div.div0 = 1;
}
else
@@ -1068,10 +920,6 @@
res = num / den;
mod = num % den;
}
-
- /*DIVLOG("DIV %08X%08X / %08X%08X = %08X%08X\r\n", (uint32_t)(num>>32), (uint32_t)num,
- (uint32_t)(den>>32), (uint32_t)den,
- (uint32_t)(res>>32), (uint32_t)res);*/
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A0, 0);
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A4, 0);
@@ -1086,39 +934,35 @@
DSI_TSC::DSI_TSC()
{
- for(unsigned i=0;i<ARRAY_SIZE(registers);i++)
- registers[i] = 0x00;
- reset_command();
+ for (unsigned i = 0; i < ARRAY_SIZE(this->registers); ++i)
+ this->registers[i] = 0x00;
+ this->reset_command();
}
void DSI_TSC::reset_command()
{
- state = 0;
- readcount = 0;
- read_flag = 1;
+ this->state = 0;
+ this->readcount = 0;
+ this->read_flag = 1;
}
uint16_t DSI_TSC::write16(uint16_t val)
{
uint16_t ret;
- switch(state)
- {
- case 0:
- reg_selection = (val>>1)&0x7F;
- read_flag = val&1;
- state = 1;
- return read16();
- case 1:
- if(read_flag)
- { }
- else
- {
- registers[reg_selection] = (uint8_t)val;
- }
- ret = read16();
- reg_selection++;
- reg_selection &= 0x7F;
- return ret;
+ switch (state)
+ {
+ case 0:
+ this->reg_selection = (val >> 1) & 0x7F;
+ this->read_flag = val & 1;
+ this->state = 1;
+ return this->read16();
+ case 1:
+ if (!this->read_flag)
+ this->registers[this->reg_selection] = static_cast<uint8_t>(val);
+ ret = this->read16();
+ ++this->reg_selection;
+ this->reg_selection &= 0x7F;
+ return ret;
}
return 0;
}
@@ -1126,98 +970,37 @@
uint16_t DSI_TSC::read16()
{
uint8_t page = registers[0];
- switch(page)
- {
- case 3: //page 3
- switch(reg_selection)
- {
- case 9:
- /*if(nds.isTouch)
- return 0;
- else */return 0x40;
- break;
- case 14:
- /*if(nds.isTouch)
- return 0;
- else */return 0x02;
- break;
- }
- break;
-
- case 252: //page 252
- switch(reg_selection)
- {
- //high byte of X:
- /*case 1: case 3: case 5: case 7: case 9:
- return (nds.scr_touchX>>8)&0xFF;
-
- //low byte of X:
- case 2: case 4: case 6: case 8: case 10:
- return nds.scr_touchX&0xFF;
-
- //high byte of Y:
- case 11: case 13: case 15: case 17: case 19:
- return (nds.scr_touchY>>8)&0xFF;
-
- //low byte of Y:
- case 12: case 14: case 16: case 18: case 20:
- return nds.scr_touchY&0xFF;*/
-
- default:
- return 0xFF;
- }
- break;
- } //switch(page)
-
- //unknown page or register
+ switch (page)
+ {
+ case 3: // page 3
+ switch (this->reg_selection)
+ {
+ case 9:
+ return 0x40;
+ case 14:
+ return 0x02;
+ }
+ } // switch(page)
+
+ // unknown page or register
return 0xFF;
}
-
-/*bool DSI_TSC::save_state(EMUFILE* os)
-{
- uint32_t version = 0;
- write32le(version,os);
-
- write8le(reg_selection,os);
- write8le(read_flag,os);
- write32le(state,os);
- write32le(readcount,os);
- for(int i=0;i<ARRAY_SIZE(registers);i++)
- write8le(registers[i],os);
-
- return true;
-}*/
-
-/*bool DSI_TSC::load_state(EMUFILE* is)
-{
- uint32_t version;
- read32le(&version,is);
-
- read8le(®_selection,is);
- read8le(&read_flag,is);
- read32le(&state,is);
- read32le(&readcount,is);
- for(int i=0;i<ARRAY_SIZE(registers);i++)
- read8le(®isters[i],is);
-
- return true;
-}*/
// TODO:
// NAND flash support (used in Made in Ore/WarioWare D.I.Y.)
-template<int PROCNUM>
-void FASTCALL MMU_writeToGCControl(uint32_t val)
-{
- const int TEST_PROCNUM = PROCNUM;
- nds_dscard& card = MMU.dscard[TEST_PROCNUM];
+template<int PROCNUM> void FASTCALL MMU_writeToGCControl(uint32_t val)
+{
+ int TEST_PROCNUM = PROCNUM;
+ nds_dscard &card = MMU.dscard[TEST_PROCNUM];
memcpy(&card.command[0], &MMU.MMU_MEM[TEST_PROCNUM][0x40][0x1A8], 8);
card.blocklen = 0;
- slot1_device.write32(PROCNUM,0xFFFFFFFF,val); //Special case for some flashcarts
- if(card.blocklen==0x01020304) return;
-
- if(!(val & 0x80000000))
+ slot1_device.write32(PROCNUM, 0xFFFFFFFF, val); // Special case for some flashcarts
+ if (card.blocklen == 0x01020304)
+ return;
+
+ if (!(val & 0x80000000))
{
card.address = 0;
card.transfer_count = 0;
@@ -1227,21 +1010,20 @@
return;
}
- uint32_t shift = (val>>24&7);
- if(shift == 7)
+ uint32_t shift = (val >> 24) & 7;
+ if (shift == 7)
card.transfer_count = 1;
- else if(shift == 0)
+ else if (!shift)
card.transfer_count = 0;
else
- card.transfer_count = (0x100<<shift)/4;
+ card.transfer_count = (0x100 << shift) / 4;
switch (card.mode)
{
- case CardMode_Normal:
- break;
-
- case CardMode_KEY1:
- {
+ case CardMode_Normal:
+ break;
+
+ case CardMode_KEY1:
// TODO
//INFO("Cartridge: KEY1 mode unsupported.\n");
@@ -1251,826 +1033,501 @@
val &= 0x7F7FFFFF;
T1WriteLong(MMU.MMU_MEM[TEST_PROCNUM][0x40], 0x1A4, val);
return;
- }
- break;
- case CardMode_KEY2:
+ case CardMode_KEY2:
//INFO("Cartridge: KEY2 mode unsupported.\n");
- break;
- }
-
- switch(card.command[0])
- {
- case 0x9F: //Dummy
- card.address = 0;
- card.transfer_count = 0x800;
- break;
-
- //case 0x90: //Get ROM chip ID
- // break;
-
- case 0x3C: //Switch to KEY1 mode
- card.mode = CardMode_KEY1;
- break;
-
- default:
- //fall through to the special slot1 handler
- slot1_device.write32(TEST_PROCNUM, REG_GCROMCTRL,val);
- break;
- }
-
- if(card.transfer_count == 0)
+ break;
+ }
+
+ switch (card.command[0])
+ {
+ case 0x9F: // Dummy
+ card.address = 0;
+ card.transfer_count = 0x800;
+ break;
+
+ case 0x3C: // Switch to KEY1 mode
+ card.mode = CardMode_KEY1;
+ break;
+
+ default:
+ // fall through to the special slot1 handler
+ slot1_device.write32(TEST_PROCNUM, REG_GCROMCTRL, val);
+ }
+
+ if (!card.transfer_count)
{
val &= 0x7F7FFFFF;
T1WriteLong(MMU.MMU_MEM[TEST_PROCNUM][0x40], 0x1A4, val);
return;
}
- val |= 0x00800000;
- T1WriteLong(MMU.MMU_MEM[TEST_PROCNUM][0x40], 0x1A4, val);
+ val |= 0x00800000;
+ T1WriteLong(MMU.MMU_MEM[TEST_PROCNUM][0x40], 0x1A4, val);
// Launch DMA if start flag was set to "DS Cart"
//printf("triggering card dma\n");
triggerDma(EDMAMode_Card);
}
-
-
-template<int PROCNUM>
-uint32_t MMU_readFromGC()
-{
- const int TEST_PROCNUM = PROCNUM;
+template<int PROCNUM> uint32_t MMU_readFromGC()
+{
+ int TEST_PROCNUM = PROCNUM;
nds_dscard& card = MMU.dscard[TEST_PROCNUM];
uint32_t val = 0;
- if(card.transfer_count == 0)
+ if (!card.transfer_count)
return 0;
- switch(card.command[0])
- {
- case 0x9F: //Dummy
+ switch (card.command[0])
+ {
+ case 0x9F: // Dummy
val = 0xFFFFFFFF;
break;
- case 0x3C: //Switch to KEY1 mode
+ case 0x3C: // Switch to KEY1 mode
val = 0xFFFFFFFF;
break;
default:
val = slot1_device.read32(TEST_PROCNUM, REG_GCDATAIN);
- break;
- }
-
- card.address += 4; // increment address
-
- card.transfer_count--; // update transfer counter
- if(card.transfer_count) // if transfer is not ended
- return val; // return data
+ }
+
+ card.address += 4; // increment address
+
+ --card.transfer_count; // update transfer counter
+ if (card.transfer_count) // if transfer is not ended
+ return val; // return data
// transfer is done
- T1WriteLong(MMU.MMU_MEM[TEST_PROCNUM][0x40], 0x1A4,
- T1ReadLong(MMU.MMU_MEM[TEST_PROCNUM][0x40], 0x1A4) & 0x7F7FFFFF);
+ T1WriteLong(MMU.MMU_MEM[TEST_PROCNUM][0x40], 0x1A4, T1ReadLong(MMU.MMU_MEM[TEST_PROCNUM][0x40], 0x1A4) & 0x7F7FFFFF);
// if needed, throw irq for the end of transfer
- if(MMU.AUX_SPI_CNT & 0x4000)
+ if (MMU.AUX_SPI_CNT & 0x4000)
NDS_makeIrq(TEST_PROCNUM, IRQ_BIT_GC_TRANSFER_COMPLETE);
return val;
}
-
-
-//does some validation on the game's choice of IF value, correcting it if necessary
-/*static void validateIF_arm9()
-{
-}*/
-
template<int PROCNUM> static void REG_IF_WriteByte(uint32_t addr, uint8_t val)
{
- //the following bits are generated from logic and should not be affected here
- //Bit 21 NDS9 only: Geometry Command FIFO
- //arm9: IF &= ~0x00200000;
- //arm7: IF &= ~0x00000000;
- //UPDATE IN setIF() ALSO!!!!!!!!!!!!!!!!
- //UPDATE IN mmu_loadstate ALSO!!!!!!!!!!!!
- if(addr==2)
- {
- if(PROCNUM==ARMCPU_ARM9)
+ // the following bits are generated from logic and should not be affected here
+ // Bit 21 NDS9 only: Geometry Command FIFO
+ // arm9: IF &= ~0x00200000;
+ // arm7: IF &= ~0x00000000;
+ // UPDATE IN setIF() ALSO!!!!!!!!!!!!!!!!
+ // UPDATE IN mmu_loadstate ALSO!!!!!!!!!!!!
+ if (addr == 2)
+ {
+ if (PROCNUM == ARMCPU_ARM9)
val &= ~0x20;
else
val &= ~0x00;
}
- //ZERO 01-dec-2010 : I am no longer sure this approach is correct.. it proved to be wrong for IPC fifo.......
- //it seems as if IF bits should always be cached (only the user can clear them)
-
- MMU.reg_IF_bits[PROCNUM] &= (~(((uint32_t)val)<<(addr<<3)));
+ // ZERO 01-dec-2010 : I am no longer sure this approach is correct.. it proved to be wrong for IPC fifo.......
+ // it seems as if IF bits should always be cached (only the user can clear them)
+
+ MMU.reg_IF_bits[PROCNUM] &= ~(static_cast<uint32_t>(val) << (addr << 3));
NDS_Reschedule();
}
-template<int PROCNUM> static void REG_IF_WriteWord(uint32_t addr,uint16_t val)
-{
- REG_IF_WriteByte<PROCNUM>(addr,val&0xFF);
- REG_IF_WriteByte<PROCNUM>(addr+1,(val>>8)&0xFF);
+template<int PROCNUM> static void REG_IF_WriteWord(uint32_t addr, uint16_t val)
+{
+ REG_IF_WriteByte<PROCNUM>(addr, val & 0xFF);
+ REG_IF_WriteByte<PROCNUM>(addr + 1, (val >> 8) & 0xFF);
}
template<int PROCNUM> static void REG_IF_WriteLong(uint32_t val)
{
- REG_IF_WriteByte<PROCNUM>(0,val&0xFF);
- REG_IF_WriteByte<PROCNUM>(1,(val>>8)&0xFF);
- REG_IF_WriteByte<PROCNUM>(2,(val>>16)&0xFF);
- REG_IF_WriteByte<PROCNUM>(3,(val>>24)&0xFF);
-}
-
-template<int PROCNUM>
-uint32_t MMU_struct::gen_IF()
-{
- uint32_t IF = reg_IF_bits[PROCNUM];
-
- /*if(PROCNUM==ARMCPU_ARM9)
- {
- //according to gbatek, these flags are forced on until the condition is removed.
- //no proof of this though...
- switch(MMU_new.gxstat.gxfifo_irq)
- {
- case 0: //never
+ REG_IF_WriteByte<PROCNUM>(0, val & 0xFF);
+ REG_IF_WriteByte<PROCNUM>(1, (val >> 8) & 0xFF);
+ REG_IF_WriteByte<PROCNUM>(2, (val >> 16) & 0xFF);
+ REG_IF_WriteByte<PROCNUM>(3, (val >> 24) & 0xFF);
+}
+
+template<int PROCNUM> uint32_t MMU_struct::gen_IF()
+{
+ return this->reg_IF_bits[PROCNUM];
+}
+
+static inline void MMU_IPCSync(uint8_t proc, uint32_t val)
+{
+ uint32_t sync_l = T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x180) & 0xFFFF;
+ uint32_t sync_r = T1ReadLong(MMU.MMU_MEM[proc ^ 1][0x40], 0x180) & 0xFFFF;
+
+ sync_l = (sync_l & 0x000F) | (val & 0x0F00);
+ sync_r = (sync_r & 0x6F00) | ((val >> 8) & 0x000F);
+
+ sync_l |= val & 0x6000;
+
+ T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x180, sync_l);
+ T1WriteLong(MMU.MMU_MEM[proc ^ 1][0x40], 0x180, sync_r);
+
+ if ((sync_l & IPCSYNC_IRQ_SEND) && (sync_r & IPCSYNC_IRQ_RECV))
+ NDS_makeIrq(proc ^ 1, IRQ_BIT_IPCSYNC);
+
+ NDS_Reschedule();
+}
+
+static inline uint16_t read_timer(int proc, int timerIndex)
+{
+ // chained timers are always up to date
+ if (MMU.timerMODE[proc][timerIndex] == 0xFFFF)
+ return MMU.timer[proc][timerIndex];
+
+ // sometimes a timer will be read when it is not enabled.
+ // we should have the value cached
+ if (!MMU.timerON[proc][timerIndex])
+ return MMU.timer[proc][timerIndex];
+
+ // for unchained timers, we do not keep the timer up to date. its value will need to be calculated here
+ int32_t diff = static_cast<int32_t>(nds.timerCycle[proc][timerIndex] - nds_timer);
+ assert(diff >= 0);
+ if (diff < 0)
+ printf("NEW EMULOOP BAD NEWS PLEASE REPORT: TIME READ DIFF < 0 (%d) (%d) (%d)\n", diff, timerIndex, MMU.timerMODE[proc][timerIndex]);
+
+ int32_t units = diff / (1 << MMU.timerMODE[proc][timerIndex]);
+ int32_t ret;
+
+ if (units == 65536)
+ ret = 0; // I'm not sure why this is happening...
+ // whichever instruction setup this counter should advance nds_timer (I think?) and the division should truncate down to 65535 immediately
+ else if (units > 65536)
+ {
+ printf("NEW EMULOOP BAD NEWS PLEASE REPORT: UNITS %d:%d = %d\n", proc, timerIndex, units);
+ ret = 0;
+ }
+ else
+ ret = 65535 - units;
+
+ return static_cast<uint16_t>(ret);
+}
+
+static inline void write_timer(int proc, int timerIndex, uint16_t val)
+{
+ if (val & 0x80)
+ MMU.timer[proc][timerIndex] = MMU.timerReload[proc][timerIndex];
+ else if (MMU.timerON[proc][timerIndex])
+ // read the timer value one last time
+ MMU.timer[proc][timerIndex] = read_timer(proc, timerIndex);
+
+ MMU.timerON[proc][timerIndex] = val & 0x80;
+
+ switch (val & 7)
+ {
+ case 0:
+ MMU.timerMODE[proc][timerIndex] = 1;
break;
- case 1: //less than half full
- if(MMU_new.gxstat.fifo_low)
- IF |= IRQ_MASK_ARM9_GXFIFO;
+ case 1:
+ MMU.timerMODE[proc][timerIndex] = 7;
break;
- case 2: //empty
- if(MMU_new.gxstat.fifo_empty)
- IF |= IRQ_MASK_ARM9_GXFIFO;
+ case 2:
+ MMU.timerMODE[proc][timerIndex] = 9;
break;
- case 3: //reserved/unknown
+ case 3:
+ MMU.timerMODE[proc][timerIndex] = 11;
break;
- }
- }*/
-
- return IF;
-}
-
-/*static void writereg_DISP3DCNT(const int size, const uint32_t adr, const uint32_t val)
-{
- //UGH. rewrite this shite to use individual values and reconstruct the return value instead of packing things in this !@#)ing register
-
- //nanostray2 cutscene will test this vs old desmumes by using some kind of 32bit access for setting up this reg for cutscenes
- switch(size)
- {
- case 8:
- switch(adr)
- {
- case REG_DISPA_DISP3DCNT:
- MMU.reg_DISP3DCNT_bits &= 0xFFFFFF00;
- MMU.reg_DISP3DCNT_bits |= val;
- //gfx3d_Control(MMU.reg_DISP3DCNT_bits);
- break;
- case REG_DISPA_DISP3DCNT+1:
- {
- uint32_t myval = (val & ~0x30) | (~val & ((MMU.reg_DISP3DCNT_bits>>8) & 0x30)); // bits 12,13 are ack bits
- myval &= 0x7F; //top bit isnt connected
- MMU.reg_DISP3DCNT_bits = MMU.reg_DISP3DCNT_bits&0xFFFF00FF;
- MMU.reg_DISP3DCNT_bits |= (myval<<8);
- //gfx3d_Control(MMU.reg_DISP3DCNT_bits);
- }
- break;
- }
- break;
- case 16:
- case 32:
- writereg_DISP3DCNT(8,adr,val&0xFF);
- writereg_DISP3DCNT(8,adr+1,(val>>8)&0xFF);
- break;
- }
-}*/
-
-/*static uint32_t readreg_DISP3DCNT(const int size, const uint32_t adr)
-{
- //UGH. rewrite this shite to use individual values and reconstruct the return value instead of packing things in this !@#)ing register
- switch(size)
- {
- case 8:
- switch(adr)
- {
- case REG_DISPA_DISP3DCNT:
- return MMU.reg_DISP3DCNT_bits & 0xFF;
- case REG_DISPA_DISP3DCNT+1:
- return ((MMU.reg_DISP3DCNT_bits)>>8)& 0xFF;
- }
- break;
- case 16:
- case 32:
- return readreg_DISP3DCNT(8,adr)|(readreg_DISP3DCNT(8,adr+1)<<8);
- }
- assert(false);
- return 0;
-}*/
-
-
-/*static uint32_t readreg_POWCNT1(const int size, const uint32_t adr) {
- switch(size)
- {
- case 8:
- switch(adr)
- {
- case REG_POWCNT1: {
- uint8_t ret = 0;
- ret |= nds.power1.lcd?BIT(0):0;
- ret |= nds.power1.gpuMain?BIT(1):0;
- ret |= nds.power1.gfx3d_render?BIT(2):0;
- ret |= nds.power1.gfx3d_geometry?BIT(3):0;
- return ret;
- }
- case REG_POWCNT1+1: {
- uint8_t ret = 0;
- ret |= nds.power1.gpuSub?BIT(1):0;
- ret |= nds.power1.dispswap?BIT(7):0;
- return ret;
- }
- }
- case 16:
- case 32:
- return readreg_POWCNT1(8,adr)|(readreg_POWCNT1(8,adr+1)<<8);
- }
- assert(false);
- return 0;
-}*/
-/*static void writereg_POWCNT1(const int size, const uint32_t adr, const uint32_t val) {
- switch(size)
- {
- case 8:
- switch(adr)
- {
- case REG_POWCNT1:
- nds.power1.lcd = BIT0(val);
- nds.power1.gpuMain = BIT1(val);
- nds.power1.gfx3d_render = BIT2(val);
- nds.power1.gfx3d_geometry = BIT3(val);
- break;
- case REG_POWCNT1+1:
- nds.power1.gpuSub = BIT1(val);
- nds.power1.dispswap = BIT7(val);
- if(nds.power1.dispswap)
- {
- //printf("Main core on top (vcount=%d)\n",nds.VCount);
- //MainScreen.offset = 0;
- //SubScreen.offset = 192;
- }
- else
- {
- //printf("Main core on bottom (vcount=%d)\n",nds.VCount);
- //MainScreen.offset = 192;
- //SubScreen.offset = 0;
- }
- break;
- }
- break;
- case 16:
- case 32:
- writereg_POWCNT1(8,adr,val&0xFF);
- writereg_POWCNT1(8,adr+1,(val>>8)&0xFF);
- break;
- }
-}*/
-
-static inline void MMU_IPCSync(uint8_t proc, uint32_t val)
-{
- //INFO("IPC%s sync 0x%04X (0x%02X|%02X)\n", proc?"7":"9", val, val >> 8, val & 0xFF);
- uint32_t sync_l = T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x180) & 0xFFFF;
- uint32_t sync_r = T1ReadLong(MMU.MMU_MEM[proc^1][0x40], 0x180) & 0xFFFF;
-
- sync_l = ( sync_l & 0x000F ) | ( val & 0x0F00 );
- sync_r = ( sync_r & 0x6F00 ) | ( (val >> 8) & 0x000F );
-
- sync_l |= val & 0x6000;
-
- /*if(nds.ensataEmulation && proc==1 && nds.ensataIpcSyncCounter<9) {
- uint32_t iteration = (val&0x0F00)>>8;*/
-
- /*if(iteration==8-nds.ensataIpcSyncCounter)
- nds.ensataIpcSyncCounter++;
- else printf("ERROR: ENSATA IPC SYNC HACK FAILED; BAD THINGS MAY HAPPEN\n");*/
-
- //for some reason, the arm9 doesn't handshake when ensata is detected.
- //so we complete the protocol here, which is to mirror the values 8..0 back to
- //the arm7 as they are written by the arm7
- /*sync_r &= 0xF0FF;
- sync_r |= (iteration<<8);
- sync_l &= 0xFFF0;
- sync_l |= iteration;
- }*/
-
- T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x180, sync_l);
- T1WriteLong(MMU.MMU_MEM[proc^1][0x40], 0x180, sync_r);
-
- if ((sync_l & IPCSYNC_IRQ_SEND) && (sync_r & IPCSYNC_IRQ_RECV))
- NDS_makeIrq(proc^1, IRQ_BIT_IPCSYNC);
-
- NDS_Reschedule();
-}
-
-static inline uint16_t read_timer(int proc, int timerIndex)
-{
- //chained timers are always up to date
- if(MMU.timerMODE[proc][timerIndex] == 0xFFFF)
- return MMU.timer[proc][timerIndex];
-
- //sometimes a timer will be read when it is not enabled.
- //we should have the value cached
- if(!MMU.timerON[proc][timerIndex])
- return MMU.timer[proc][timerIndex];
-
- //for unchained timers, we do not keep the timer up to date. its value will need to be calculated here
- int32_t diff = (int32_t)(nds.timerCycle[proc][timerIndex] - nds_timer);
- assert(diff>=0);
- if(diff<0)
- printf("NEW EMULOOP BAD NEWS PLEASE REPORT: TIME READ DIFF < 0 (%d) (%d) (%d)\n",diff,timerIndex,MMU.timerMODE[proc][timerIndex]);
-
- int32_t units = diff / (1<<MMU.timerMODE[proc][timerIndex]);
- int32_t ret;
-
- if(units==65536)
- ret = 0; //I'm not sure why this is happening...
- //whichever instruction setup this counter should advance nds_timer (I think?) and the division should truncate down to 65535 immediately
- else if(units>65536) {
- printf("NEW EMULOOP BAD NEWS PLEASE REPORT: UNITS %d:%d = %d\n",proc,timerIndex,units);
- ret = 0;
- }
- else ret = 65535 - units;
-
- return static_cast<uint16_t>(ret);
-}
-
-static inline void write_timer(int proc, int timerIndex, uint16_t val)
-{
-#if 0
- int mask = ((val&0x80)>>7) << timerIndex;
- MMU.CheckTimers = (MMU.CheckTimers & (~mask)) | mask;
-#endif
-
- if(val&0x80)
- MMU.timer[proc][timerIndex] = MMU.timerReload[proc][timerIndex];
- else
- {
- if(MMU.timerON[proc][timerIndex])
- //read the timer value one last time
- MMU.timer[proc][timerIndex] = read_timer(proc,timerIndex);
- }
-
- MMU.timerON[proc][timerIndex] = val & 0x80;
-
- switch(val&7)
- {
- case 0 :
- MMU.timerMODE[proc][timerIndex] = 0+1;
- break;
- case 1 :
- MMU.timerMODE[proc][timerIndex] = 6+1;
- break;
- case 2 :
- MMU.timerMODE[proc][timerIndex] = 8+1;
- break;
- case 3 :
- MMU.timerMODE[proc][timerIndex] = 10+1;
- break;
- default :
+ default:
MMU.timerMODE[proc][timerIndex] = 0xFFFF;
- break;
}
int remain = 65536 - MMU.timerReload[proc][timerIndex];
- nds.timerCycle[proc][timerIndex] = nds_timer + (remain<<MMU.timerMODE[proc][timerIndex]);
-
- T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x102+timerIndex*4, val);
+ nds.timerCycle[proc][timerIndex] = nds_timer + (remain << MMU.timerMODE[proc][timerIndex]);
+
+ T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x102 + timerIndex * 4, val);
NDS_RescheduleTimers();
}
-//extern CACHE_ALIGN MatrixStack mtxStack[4];
uint32_t TGXSTAT::read32()
{
uint32_t ret = 0;
- ret |= tb|(tr<<1);
-
- //int _hack_getMatrixStackLevel(int which);
-
- // stack position always equal zero. possible timings is wrong
- // using in "The Wild West"
- //ret |= ((_hack_getMatrixStackLevel(0) << 13) | (_hack_getMatrixStackLevel(1) << 8)); //matrix stack levels //no proof that these are needed yet
-
- ret |= sb<<14; //stack busy
- ret |= se<<15;
- ret |= 255<<16;//(std::min(gxFIFO.size,(uint32_t)255))<<16;
- //if(gxFIFO.size>=255) ret |= BIT(24); //fifo full
- //if(gxFIFO.size<128) ret |= BIT(25); //fifo half
- //if(gxFIFO.size==0) ret |= BIT(26); //fifo empty
- //determine busy flag.
- //if we're waiting for a flush, we're busy
- //if(isSwapBuffers) ret |= BIT(27);
- //if fifo is nonempty, we're busy
- //if(gxFIFO.size!=0) ret |= BIT(27);
-
- ret |= ((gxfifo_irq & 0x3) << 30); //user's irq flags
+ ret |= this->tb | (this->tr << 1);
+
+ ret |= this->sb << 14; // stack busy
+ ret |= this->se << 15;
+ ret |= 255 << 16;
+
+ ret |= (this->gxfifo_irq & 0x3) << 30; // user's irq flags
//printf("vc=%03d Returning gxstat read: %08X\n",nds.VCount,ret);
- //ret = (2 << 8);
- //INFO("gxSTAT 0x%08X (proj %i, pos %i)\n", ret, _hack_getMatrixStackLevel(1), _hack_getMatrixStackLevel(2));
return ret;
}
-void TGXSTAT::write32(const uint32_t val)
-{
- gxfifo_irq = (val>>30)&3;
- if(BIT15(val))
+void TGXSTAT::write32(uint32_t val)
+{
+ this->gxfifo_irq = (val >> 30) & 3;
+ if (BIT15(val))
{
// Writing "1" to Bit15 does reset the Error Flag (Bit15),
// and additionally resets the Projection Stack Pointer (Bit13)
//mtxStack[0].position = 0;
- se = 0; //clear stack error flag
+ this->se = 0; // clear stack error flag
}
//printf("gxstat write: %08X while gxfifo.size=%d\n",val,gxFIFO.size);
-
- //if (val & (1<<29)) // clear? (only in homebrew?)
- //{
- // GFX_PIPEclear();
- // GFX_FIFOclear();
- // return;
- //}
-}
-
-/*void TGXSTAT::savestate(EMUFILE *f)
-{
- write32le(1,f); //version
- write8le(tb,f); write8le(tr,f); write8le(se,f); write8le(gxfifo_irq,f); write8le(sb,f);
-}*/
-bool TGXSTAT::loadstate(EMUFILE *f)
-{
- uint32_t version;
- if(read32le(&version,f) != 1) return false;
- if(version > 1) return false;
-
- read8le(&tb,f); read8le(&tr,f); read8le(&se,f); read8le(&gxfifo_irq,f);
- if (version >= 1)
- read8le(&sb,f);
-
- return true;
-}
-
-//this could be inlined...
-void MMU_struct_new::write_dma(const int proc, const int size, const uint32_t _adr, const uint32_t val)
+}
+
+// this could be inlined...
+void MMU_struct_new::write_dma(int proc, int size, uint32_t _adr, uint32_t val)
{
//printf("%08lld -- write_dma: %d %d %08X %08X\n",nds_timer,proc,size,_adr,val);
- const uint32_t adr = _adr - _REG_DMA_CONTROL_MIN;
- const uint32_t chan = adr/12;
- const uint32_t regnum = (adr - chan*12)>>2;
-
- if(proc==0&&chan==0)
- {
- //int zzz=9;
- }
-
- if(proc==1) {
- //int zzz=9;
- }
-
- MMU_new.dma[proc][chan].regs[regnum]->write(size,adr,val);
-}
-
-
-//this could be inlined...
-uint32_t MMU_struct_new::read_dma(const int proc, const int size, const uint32_t _adr)
-{
- const uint32_t adr = _adr - _REG_DMA_CONTROL_MIN;
- const uint32_t chan = adr/12;
- const uint32_t regnum = (adr - chan*12)>>2;
-
- const uint32_t temp = MMU_new.dma[proc][chan].regs[regnum]->read(size,adr);
+ uint32_t adr = _adr - _REG_DMA_CONTROL_MIN;
+ uint32_t chan = adr / 12;
+ uint32_t regnum = (adr - chan * 12) >> 2;
+
+ MMU_new.dma[proc][chan].regs[regnum]->write(size, adr, val);
+}
+
+// this could be inlined...
+uint32_t MMU_struct_new::read_dma(int proc, int size, uint32_t _adr)
+{
+ uint32_t adr = _adr - _REG_DMA_CONTROL_MIN;
+ uint32_t chan = adr / 12;
+ uint32_t regnum = (adr - chan * 12) >> 2;
+
+ uint32_t temp = MMU_new.dma[proc][chan].regs[regnum]->read(size, adr);
//printf("%08lld -- read_dma: %d %d %08X = %08X\n",nds_timer,proc,size,_adr,temp);
-
-
- if(temp == 0xAF00 && size == 16)
- {
- //int zzz=9;
- }
-
return temp;
}
MMU_struct_new::MMU_struct_new()
{
- for(int i=0;i<2;i++)
- for(int j=0;j<4;j++) {
+ for (int i = 0; i < 2; ++i)
+ for (int j = 0; j < 4; ++j)
+ {
dma[i][j].procnum = i;
dma[i][j].chan = j;
}
}
-bool DmaController::loadstate(EMUFILE* f)
-{
- uint32_t version;
- if(read32le(&version,f) != 1) return false;
- if(version >1) return false;
-
- read8le(&enable,f); read8le(&irq,f); read8le(&repeatMode,f); read8le(&_startmode,f);
- read8le(&userEnable,f);
- read32le(&wordcount,f);
- uint8_t temp;
- read8le(&temp,f); startmode = (EDMAMode)temp;
- read8le(&temp,f); bitWidth = (EDMABitWidth)temp;
- read8le(&temp,f); sar = (EDMASourceUpdate)temp;
- read8le(&temp,f); dar = (EDMADestinationUpdate)temp;
- read32le(&saddr,f); read32le(&daddr,f);
- read32le(reinterpret_cast<uint32_t *>(&dmaCheck),f); read32le(reinterpret_cast<uint32_t *>(&running),f); read32le(reinterpret_cast<uint32_t *>(&paused),f); read32le(reinterpret_cast<uint32_t *>(&triggered),f);
- read64le(&nextEvent,f);
-
- if(version==1)
- {
- read32le(&saddr_user,f);
- read32le(&daddr_user,f);
- }
-
- return true;
-}
-
-/*void DmaController::savestate(EMUFILE *f)
-{
- write32le(1,f); //version
- write8le(enable,f); write8le(irq,f); write8le(repeatMode,f); write8le(_startmode,f);
- write8le(userEnable,f);
- write32le(wordcount,f);
- write8le(startmode,f);
- write8le(bitWidth,f);
- write8le(sar,f);
- write8le(dar,f);
- write32le(saddr,f); write32le(daddr,f);
- write32le(check,f); write32le(running,f); write32le(paused,f); write32le(triggered,f);
- write64le(nextEvent,f);
- write32le(saddr_user,f);
- write32le(daddr_user,f);
-}*/
-
-void DmaController::write32(const uint32_t val)
-{
- if(this->chan==0 && this->procnum==0)
- {
- //int zzz=9;
- }
- if(running)
- {
- //desp triggers this a lot. figure out whats going on
- //printf("thats weird..user edited dma control while it was running\n");
- }
+void DmaController::write32(uint32_t val)
+{
//printf("dma %d,%d WRITE %08X\n",procnum,chan,val);
- wordcount = val&0x1FFFFF;
- if(wordcount==0x9FbFC || wordcount == 0x1FFFFC || wordcount == 0x1EFFFC || wordcount == 0x1FFFFF) {
- //int zzz=9;
- }
- //uint8_t wasRepeatMode = repeatMode;
- uint8_t wasEnable = enable;
- uint32_t valhi = val>>16;
- dar = (EDMADestinationUpdate)((valhi>>5)&3);
- sar = (EDMASourceUpdate)((valhi>>7)&3);
- repeatMode = static_cast<uint8_t>(BIT9(valhi));
- bitWidth = (EDMABitWidth)BIT10(valhi);
- _startmode = (valhi>>11)&7;
- if(procnum==ARMCPU_ARM7) _startmode &= 6;
- irq = static_cast<uint8_t>(BIT14(valhi));
- enable = static_cast<uint8_t>(BIT15(valhi));
-
- if(val==0x84400076 && saddr ==0x023BCEC4)
- {
- //int zzz=9;
- }
-
- //if(irq) printf("!!!!!!!!!!!!IRQ!!!!!!!!!!!!!\n");
-
- //make sure we don't get any old triggers
- if(!wasEnable && enable)
- triggered = false;
-
- if(enable)
- {
- //address registers are reloaded from user's settings whenever dma is enabled
- //this is tested well by contra4 classic games, which use this to hdma scroll registers
- //specifically in the fit-screen mode.
- saddr = saddr_user;
- daddr = daddr_user;
+ this->wordcount = val & 0x1FFFFF;
+ uint8_t wasEnable = this->enable;
+ uint32_t valhi = val >> 16;
+ this->dar = static_cast<EDMADestinationUpdate>((valhi >> 5) & 3);
+ this->sar = static_cast<EDMASourceUpdate>((valhi >> 7) & 3);
+ this->repeatMode = static_cast<uint8_t>(BIT9(valhi));
+ this->bitWidth = static_cast<EDMABitWidth>(BIT10(valhi));
+ this->_startmode = (valhi >> 11) & 7;
+ if (this->procnum == ARMCPU_ARM7)
+ this->_startmode &= 6;
+ this->irq = static_cast<uint8_t>(BIT14(valhi));
+ this->enable = static_cast<uint8_t>(BIT15(valhi));
+
+ // make sure we don't get any old triggers
+ if (!wasEnable && this->enable)
+ this->triggered = false;
+
+ if (this->enable)
+ {
+ // address registers are reloaded from user's settings whenever dma is enabled
+ // this is tested well by contra4 classic games, which use this to hdma scroll registers
+ // specifically in the fit-screen mode.
+ this->saddr = this->saddr_user;
+ this->daddr = this->daddr_user;
}
//printf("dma %d,%d set to startmode %d with wordcount set to: %08X\n",procnum,chan,_startmode,wordcount);
-if(_startmode==0 && wordcount==1) {
- //int zzz=9;
-}
- if(enable)
- {
- //int zzz=9;
- }
-
- //analyze enabling and startmode.
- //note that we only do this if the dma was freshly enabled.
- //we should probably also only be latching these other regs in that case too..
- //but for now just this one will do (otherwise the dma repeat stop procedure (in this case the ff4 title menu load with gamecard dma) will fail)
+ // analyze enabling and startmode.
+ // note that we only do this if the dma was freshly enabled.
+ // we should probably also only be latching these other regs in that case too..
+ // but for now just this one will do (otherwise the dma repeat stop procedure (in this case the ff4 title menu load with gamecard dma) will fail)
//if(!running) enable = userEnable;
- //if we were previously in a triggered mode, and were already enabled,
- //then don't re-trigger now. this is rather confusing..
- //we really only want to auto-trigger gxfifo and immediate modes.
- //but we don't know what mode we're in yet.
- //so this is our workaround
- //(otherwise the dma repeat stop procedure (in this case the ff4 title menu load with gamecard dma) will fail)
+ // if we were previously in a triggered mode, and were already enabled,
+ // then don't re-trigger now. this is rather confusing..
+ // we really only want to auto-trigger gxfifo and immediate modes.
+ // but we don't know what mode we're in yet.
+ // so this is our workaround
+ // (otherwise the dma repeat stop procedure (in this case the ff4 title menu load with gamecard dma) will fail)
bool doNotStart = false;
- if(startmode != EDMAMode_Immediate/* && startmode != EDMAMode_GXFifo*/ && wasEnable) doNotStart = true;
-
- //this dma may need to trigger now, so give it a chance
+ if (this->startmode != EDMAMode_Immediate && wasEnable)
+ doNotStart = true;
+
+ // this dma may need to trigger now, so give it a chance
//if(!(wasRepeatMode && !repeatMode)) //this was an older test
- if(!doNotStart)
- doSchedule();
-
- //driver->DEBUG_UpdateIORegView(BaseDriver::EDEBUG_IOREG_DMA);
+ if (!doNotStart)
+ this->doSchedule();
}
void DmaController::exec()
{
- //this function runs when the DMA ends. the dma start actually queues this event after some kind of guess as to how long the DMA should take
-
- //we'll need to unfreeze the arm9 bus now
- if(procnum==ARMCPU_ARM9) nds.freezeBus &= ~(1<<(chan+1));
-
- dmaCheck = false;
-
- if(running)
- {
- switch(startmode) {
- /*case EDMAMode_GXFifo:
- //this dma mode won't finish always its job when it gets signalled
- //sometimes it will have words left to transfer.
- //if(!paused) printf("gxfifo dma ended with %d remaining\n",wordcount); //only print this once
- if(wordcount>0) {
- doPause();
- break;
- }*/
- default:
- doStop();
- //driver->DEBUG_UpdateIORegView(BaseDriver::EDEBUG_IOREG_DMA);
- return;
- }
- }
-
- if(enable)
- {
- //analyze startmode (this only gets latched when a dma begins)
- if(procnum==ARMCPU_ARM9) startmode = (EDMAMode)_startmode;
- else {
- //arm7 startmode analysis:
- static const EDMAMode lookup[] = {EDMAMode_Immediate,EDMAMode_VBlank,EDMAMode_Card,EDMAMode7_Wifi};
- //arm7 has a slightly different startmode encoding
- startmode = lookup[_startmode>>1];
- if(startmode == EDMAMode7_Wifi && (chan==1 || chan==3))
- startmode = EDMAMode7_GBASlot;
- }
-
- //make it run, if it is triggered
- //but first, scan for triggering conditions
- switch(startmode) {
+ // this function runs when the DMA ends. the dma start actually queues this event after some kind of guess as to how long the DMA should take
+
+ // we'll need to unfreeze the arm9 bus now
+ if (this->procnum == ARMCPU_ARM9)
+ nds.freezeBus &= ~(1 << (this->chan + 1));
+
+ this->dmaCheck = false;
+
+ if (this->running)
+ {
+ this->doStop();
+ return;
+ }
+
+ if (this->enable)
+ {
+ // analyze startmode (this only gets latched when a dma begins)
+ if (this->procnum == ARMCPU_ARM9)
+ this->startmode = static_cast<EDMAMode>(this->_startmode);
+ else
+ {
+ // arm7 startmode analysis:
+ static const EDMAMode lookup[] = { EDMAMode_Immediate, EDMAMode_VBlank, EDMAMode_Card, EDMAMode7_Wifi };
+ // arm7 has a slightly different startmode encoding
+ this->startmode = lookup[this->_startmode >> 1];
+ if (this->startmode == EDMAMode7_Wifi && (this->chan == 1 || this->chan == 3))
+ this->startmode = EDMAMode7_GBASlot;
+ }
+
+ // make it run, if it is triggered
+ // but first, scan for triggering conditions
+ switch (this->startmode)
+ {
case EDMAMode_Immediate:
- triggered = true;
- break;
- /*case EDMAMode_GXFifo:
- if(gxFIFO.size<=127)
- triggered = true;
- break;*/
- default:
- break;
- }
-
- if(triggered)
- {
- //if(procnum==0) printf("vc=%03d %08lld trig type %d dma#%d w/words %d at src:%08X dst:%08X gxf:%d",nds.VCount,nds_timer,startmode,chan,wordcount,saddr,daddr,gxFIFO.size);
- if(saddr ==0x023BCCEC && wordcount==118) {
- //int zzz=9;
- }
- if(startmode==0 && daddr == 0x4000400) {
- //int zzz=9;
- }
- running = true;
- paused = false;
- if(procnum == ARMCPU_ARM9) doCopy<ARMCPU_ARM9>();
- else doCopy<ARMCPU_ARM7>();
- //printf(";%d\n",gxFIFO.size);
- }
- }
-
- //driver->DEBUG_UpdateIORegView(BaseDriver::EDEBUG_IOREG_DMA);
-}
-
-template<int PROCNUM>
-void DmaController::doCopy()
-{
- //generate a copy count depending on various copy mode's behavior
- uint32_t todo = wordcount;
- if(todo == 0) todo = 0x200000; //according to gbatek.. //TODO - this should not work this way for arm7 according to gbatek
- if(startmode == EDMAMode_MemDisplay)
- {
- todo = 128; //this is a hack. maybe an alright one though. it should be 4 words at a time. this is a whole scanline
-
- //apparently this dma turns off after it finishes a frame
- if(nds.VCount==191) enable = 0;
- }
- if(startmode == EDMAMode_Card) todo *= 0x80;
- //if(startmode == EDMAMode_GXFifo) todo = std::min(todo,(uint32_t)112);
-
- //determine how we're going to copy
+ this->triggered = true;
+ }
+
+ if (this->triggered)
+ {
+ this->running = true;
+ this->paused = false;
+ if (this->procnum == ARMCPU_ARM9)
+ this->doCopy<ARMCPU_ARM9>();
+ else
+ this->doCopy<ARMCPU_ARM7>();
+ }
+ }
+}
+
+template<int PROCNUM> void DmaController::doCopy()
+{
+ // generate a copy count depending on various copy mode's behavior
+ uint32_t todo = this->wordcount;
+ if (PROCNUM == ARMCPU_ARM9)
+ if (!todo)
+ todo = 0x200000; // according to gbatek.. we've verified this behaviour on the arm7
+ if (this->startmode == EDMAMode_MemDisplay)
+ {
+ todo = 128; // this is a hack. maybe an alright one though. it should be 4 words at a time. this is a whole scanline
+
+ // apparently this dma turns off after it finishes a frame
+ if (nds.VCount == 191)
+ this->enable = 0;
+ }
+ if (this->startmode == EDMAMode_Card)
+ todo *= 0x80;
+
+ // determine how we're going to copy
bool bogarted = false;
- uint32_t sz = (bitWidth==EDMABitWidth_16)?2:4;
- uint32_t dstinc = 0,srcinc = 0;
- switch(dar) {
- case EDMADestinationUpdate_Increment : dstinc = sz; break;
- case EDMADestinationUpdate_Decrement : dstinc = (uint32_t)-(int32_t)sz; break;
- case EDMADestinationUpdate_Fixed : dstinc = 0; break;
- case EDMADestinationUpdate_IncrementReload : dstinc = sz; break;
- default: bogarted = true; break;
- }
- switch(sar) {
- case EDMASourceUpdate_Increment : srcinc = sz; break;
- case EDMASourceUpdate_Decrement : srcinc = (uint32_t)-(int32_t)sz; break;
- case EDMASourceUpdate_Fixed : srcinc = 0; break;
- case EDMASourceUpdate_Invalid : bogarted = true; break;
- default: bogarted = true; break;
- }
-
- //need to figure out what to do about this
- if(bogarted)
+ uint32_t sz = this->bitWidth == EDMABitWidth_16 ? 2 : 4;
+ uint32_t dstinc = 0, srcinc = 0;
+ switch (this->dar)
+ {
+ case EDMADestinationUpdate_Increment:
+ dstinc = sz;
+ break;
+ case EDMADestinationUpdate_Decrement:
+ dstinc = static_cast<uint32_t>(-static_cast<int32_t>(sz));
+ break;
+ case EDMADestinationUpdate_Fixed:
+ dstinc = 0;
+ break;
+ case EDMADestinationUpdate_IncrementReload:
+ dstinc = sz;
+ break;
+ default:
+ bogarted = true;
+ }
+ switch (this->sar)
+ {
+ case EDMASourceUpdate_Increment:
+ srcinc = sz;
+ break;
+ case EDMASourceUpdate_Decrement:
+ srcinc = static_cast<uint32_t>(-static_cast<int32_t>(sz));
+ break;
+ case EDMASourceUpdate_Fixed:
+ srcinc = 0;
+ break;
+ case EDMASourceUpdate_Invalid:
+ default:
+ bogarted = true;
+ }
+
+ // need to figure out what to do about this
+ if (bogarted)
{
printf("YOUR GAME IS BOGARTED!!! PLEASE REPORT!!!\n");
assert(false);
return;
}
- uint32_t src = saddr;
- uint32_t dst = daddr;
-
-
- //if these do not use MMU_AT_DMA and the corresponding code in the read/write routines,
- //then danny phantom title screen will be filled with a garbage char which is made by
- //dmaing from 0x00000000 to 0x06000000
- //TODO - these might be losing out a lot by not going through the templated version anymore.
- //we might make another function to do just the raw copy op which can use them with checks
- //outside the loop
+ uint32_t src = this->saddr;
+ uint32_t dst = this->daddr;
+
+ // if these do not use MMU_AT_DMA and the corresponding code in the read/write routines,
+ // then danny phantom title screen will be filled with a garbage char which is made by
+ // dmaing from 0x00000000 to 0x06000000
+ // TODO - these might be losing out a lot by not going through the templated version anymore.
+ // we might make another function to do just the raw copy op which can use them with checks
+ // outside the loop
int time_elapsed = 0;
- if(sz==4) {
- for(int32_t i=(int32_t)todo; i>0; i--)
- {
- time_elapsed += _MMU_accesstime<PROCNUM,MMU_AT_DMA,32,MMU_AD_READ,true>(src,true);
- time_elapsed += _MMU_accesstime<PROCNUM,MMU_AT_DMA,32,MMU_AD_WRITE,true>(dst,true);
- uint32_t temp = _MMU_read32(procnum,MMU_AT_DMA,src);
- _MMU_write32(procnum,MMU_AT_DMA,dst, temp);
- dst += dstinc;
- src += srcinc;
- }
- } else {
- for(int32_t i=(int32_t)todo; i>0; i--)
- {
- time_elapsed += _MMU_accesstime<PROCNUM,MMU_AT_DMA,16,MMU_AD_READ,true>(src,true);
- time_elapsed += _MMU_accesstime<PROCNUM,MMU_AT_DMA,16,MMU_AD_WRITE,true>(dst,true);
- uint16_t temp = _MMU_read16(procnum,MMU_AT_DMA,src);
- _MMU_write16(procnum,MMU_AT_DMA,dst, temp);
- dst += dstinc;
- src += srcinc;
- }
- }
-
- //reschedule an event for the end of this dma, and figure out how much it cost us
- doSchedule();
+ for (int32_t i = static_cast<int32_t>(todo); i > 0; --i)
+ {
+ if (sz == 4)
+ {
+ time_elapsed += _MMU_accesstime<PROCNUM, MMU_AT_DMA, 32, MMU_AD_READ, true>(src, true);
+ time_elapsed += _MMU_accesstime<PROCNUM, MMU_AT_DMA, 32, MMU_AD_WRITE, true>(dst, true);
+ uint32_t temp = _MMU_read32(procnum, MMU_AT_DMA, src);
+ _MMU_write32(procnum, MMU_AT_DMA, dst, temp);
+ }
+ else
+ {
+ time_elapsed += _MMU_accesstime<PROCNUM, MMU_AT_DMA, 16, MMU_AD_READ, true>(src, true);
+ time_elapsed += _MMU_accesstime<PROCNUM, MMU_AT_DMA, 16, MMU_AD_WRITE, true>(dst, true);
+ uint16_t temp = _MMU_read16(procnum, MMU_AT_DMA, src);
+ _MMU_write16(procnum, MMU_AT_DMA, dst, temp);
+ }
+ dst += dstinc;
+ src += srcinc;
+ }
+
+ // reschedule an event for the end of this dma, and figure out how much it cost us
+ this->doSchedule();
// zeromus, check it
- if (wordcount > todo)
- nextEvent += todo/4; //TODO - surely this is a gross simplification
- //apparently moon has very, very tight timing (i didnt spy it using waitbyloop swi...)
- //so lets bump this down a bit for now,
- //(i think this code is in nintendo libraries)
-
- //write back the addresses
- saddr = src;
- if(dar != EDMADestinationUpdate_IncrementReload) //but dont write back dst if we were supposed to reload
- daddr = dst;
-
- //do wordcount accounting
- if(startmode == EDMAMode_Card)
- todo /= 0x80; //divide this funky one back down before subtracting it
-
- if(!repeatMode)
- wordcount -= todo;
+ if (this->wordcount > todo)
+ this->nextEvent += todo / 4; // TODO - surely this is a gross simplification
+ // apparently moon has very, very tight timing (i didnt spy it using waitbyloop swi...)
+ // so lets bump this down a bit for now,
+ // (i think this code is in nintendo libraries)
+
+ // write back the addresses
+ this->saddr = src;
+ if (this->dar != EDMADestinationUpdate_IncrementReload) // but dont write back dst if we were supposed to reload
+ this->daddr = dst;
+
+ // do wordcount accounting
+ if (this->startmode == EDMAMode_Card)
+ todo /= 0x80; // divide this funky one back down before subtracting it
+
+ if (!this->repeatMode)
+ this->wordcount -= todo;
}
void triggerDma(EDMAMode mode)
{
MACRODO2(0, {
- const int i=X;
+ int i = X;
MACRODO4(0, {
- const int j=X;
+ int j = X;
MMU_new.dma[i][j].tryTrigger(mode);
});
});
@@ -2078,307 +1535,132 @@
void DmaController::tryTrigger(EDMAMode mode)
{
- if(startmode != mode) return;
- if(!enable) return;
-
- //hmm dont trigger it if its already running!
- //but paused things need triggers to continue
- if(running && !paused) return;
- triggered = true;
- doSchedule();
+ if (this->startmode != mode)
+ return;
+ if (!this->enable)
+ return;
+
+ // hmm dont trigger it if its already running!
+ // but paused things need triggers to continue
+ if (this->running && !this->paused)
+ return;
+ this->triggered = true;
+ this->doSchedule();
}
void DmaController::doSchedule()
{
- dmaCheck = true;
- nextEvent = nds_timer;
+ this->dmaCheck = true;
+ this->nextEvent = nds_timer;
NDS_RescheduleDMA();
}
-
void DmaController::doPause()
{
- triggered = false;
- paused = true;
+ this->triggered = false;
+ this->paused = true;
}
void DmaController::doStop()
{
- //if(procnum==0) printf("%08lld stop type %d dma#%d\n",nds_timer,startmode,chan);
- running = false;
- if(!repeatMode) enable = false;
- if(irq) {
- NDS_makeIrq(procnum,IRQ_BIT_DMA_0+chan);
- }
-}
-
-
+ this->running = false;
+ if (!this->repeatMode)
+ this->enable = false;
+ if (this->irq)
+ NDS_makeIrq(this->procnum, IRQ_BIT_DMA_0 + this->chan);
+}
uint32_t DmaController::read32()
{
uint32_t ret = 0;
- ret |= enable<<31;
- ret |= irq<<30;
- ret |= _startmode<<27;
- ret |= bitWidth<<26;
- ret |= repeatMode<<25;
- ret |= sar<<23;
- ret |= dar<<21;
- ret |= wordcount;
+ ret |= this->enable << 31;
+ ret |= this->irq << 30;
+ ret |= this->_startmode << 27;
+ ret |= this->bitWidth << 26;
+ ret |= this->repeatMode << 25;
+ ret |= this->sar << 23;
+ ret |= this->dar << 21;
+ ret |= this->wordcount;
//printf("dma %d,%d READ %08X\n",procnum,chan,ret);
- if(ret == 0xAF000001) {
- //int zzz=9;
- }
return ret;
}
-/*static inline void write_auxspicnt(const int, const int size, const int adr, const int val)
-{
- //why val==0 to reset? is it a particular bit? its not bit 6...
- switch(size) {
- case 16:
- MMU.AUX_SPI_CNT = val;
- if (val == 0) MMU_new.backupDevice.reset_command();
- break;
- case 8:
- switch(adr) {
- case 0:
- T1WriteByte((uint8_t*)&MMU.AUX_SPI_CNT,0,val);
- if (val == 0) MMU_new.backupDevice.reset_command();
- break;
- case 1:
- T1WriteByte((uint8_t*)&MMU.AUX_SPI_CNT,1,val);
- break;
- }
- }
-}*/
-
-
-//================================================================================================== ARM9 *
-//=========================================================================================================
-//=========================================================================================================
-//================================================= MMU write 08
+// ================================================================================================== ARM9 *
+// =========================================================================================================
+// =========================================================================================================
+// ================================================= MMU write 08
void FASTCALL _MMU_ARM9_write08(uint32_t adr, uint8_t val)
{
adr &= 0x0FFFFFFF;
- //mmu_log_debug_ARM9(adr, "(write08) 0x%02X", val);
-
- if(adr < 0x02000000)
- {
- T1WriteByte(MMU.ARM9_ITCM, adr&0x7FFF, val);
- return;
- }
-
- if ( (adr >= 0x08000000) && (adr < 0x0A010000) )
- {
- //addon.write08(adr, val);
- return;
- }
-
- //block 8bit writes to OAM and palette memory
- if((adr&0x0F000000)==0x07000000) return;
- if((adr&0x0F000000)==0x05000000) return;
-
- if (adr >> 24 == 4)
- {
-
- // TODO: add pal reg
- /*if (nds.power1.gpuMain == 0)
- if ((adr >= 0x04000008) && (adr<=0x0400005F)) return;*/
- /*if (nds.power1.gpuSub == 0)
- if ((adr >= 0x04001008) && (adr<=0x0400105F)) return;*/
- /*if (nds.power1.gfx3d_geometry == 0)
- if ((adr >= 0x04000400) && (adr<=0x040006FF)) return;
- if (nds.power1.gfx3d_render == 0)
- if ((adr >= 0x04000320) && (adr<=0x040003FF)) return;*/
-
- if(MMU_new.is_dma(adr)) {
- MMU_new.write_dma(ARMCPU_ARM9,8,adr,val);
+ if (adr < 0x02000000)
+ {
+#ifdef HAVE_JIT
+ JIT_COMPILED_FUNC_KNOWNBANK(adr, ARM9_ITCM, 0x7FFF, 0) = 0;
+#endif
+ T1WriteByte(MMU.ARM9_ITCM, adr & 0x7FFF, val);
+ return;
+ }
+
+ if (adr >= 0x08000000 && adr < 0x0A010000)
+ return;
+
+ // block 8bit writes to OAM and palette memory
+ if ((adr & 0x0F000000) == 0x07000000)
+ return;
+ if ((adr & 0x0F000000) == 0x05000000)
+ return;
+
+ if ((adr >> 24) == 4)
+ {
+ if (MMU_new.is_dma(adr))
+ {
+ MMU_new.write_dma(ARMCPU_ARM9, 8, adr, val);
return;
}
- switch(adr)
- {
- case REG_SQRTCNT: printf("ERROR 8bit SQRTCNT WRITE\n"); return;
- case REG_SQRTCNT+1: printf("ERROR 8bit SQRTCNT1 WRITE\n"); return;
- case REG_SQRTCNT+2: printf("ERROR 8bit SQRTCNT2 WRITE\n"); return;
- case REG_SQRTCNT+3: printf("ERROR 8bit SQRTCNT3 WRITE\n"); return;
+ switch (adr)
+ {
+ case REG_SQRTCNT:
+ printf("ERROR 8bit SQRTCNT WRITE\n");
+ return;
+ case REG_SQRTCNT + 1:
+ printf("ERROR 8bit SQRTCNT1 WRITE\n");
+ return;
+ case REG_SQRTCNT + 2:
+ printf("ERROR 8bit SQRTCNT2 WRITE\n");
+ return;
+ case REG_SQRTCNT + 3:
+ printf("ERROR 8bit SQRTCNT3 WRITE\n");
+ return;
#if 1
- case REG_DIVCNT: printf("ERROR 8bit DIVCNT WRITE\n"); return;
- case REG_DIVCNT+1: printf("ERROR 8bit DIVCNT1 WRITE\n"); return;
- case REG_DIVCNT+2: printf("ERROR 8bit DIVCNT2 WRITE\n"); return;
- case REG_DIVCNT+3: printf("ERROR 8bit DIVCNT3 WRITE\n"); return;
+ case REG_DIVCNT:
+ printf("ERROR 8bit DIVCNT WRITE\n");
+ return;
+ case REG_DIVCNT + 1:
+ printf("ERROR 8bit DIVCNT+1 WRITE\n");
+ return;
+ case REG_DIVCNT + 2:
+ printf("ERROR 8bit DIVCNT+2 WRITE\n");
+ return;
+ case REG_DIVCNT + 3:
+ printf("ERROR 8bit DIVCNT+3 WRITE\n");
+ return;
#endif
- //fog table: only write bottom 7 bits
- /*case eng_3D_FOG_TABLE+0x00: case eng_3D_FOG_TABLE+0x01: case eng_3D_FOG_TABLE+0x02: case eng_3D_FOG_TABLE+0x03:
- case eng_3D_FOG_TABLE+0x04: case eng_3D_FOG_TABLE+0x05: case eng_3D_FOG_TABLE+0x06: case eng_3D_FOG_TABLE+0x07:
- case eng_3D_FOG_TABLE+0x08: case eng_3D_FOG_TABLE+0x09: case eng_3D_FOG_TABLE+0x0A: case eng_3D_FOG_TABLE+0x0B:
- case eng_3D_FOG_TABLE+0x0C: case eng_3D_FOG_TABLE+0x0D: case eng_3D_FOG_TABLE+0x0E: case eng_3D_FOG_TABLE+0x0F:
- case eng_3D_FOG_TABLE+0x10: case eng_3D_FOG_TABLE+0x11: case eng_3D_FOG_TABLE+0x12: case eng_3D_FOG_TABLE+0x13:
- case eng_3D_FOG_TABLE+0x14: case eng_3D_FOG_TABLE+0x15: case eng_3D_FOG_TABLE+0x16: case eng_3D_FOG_TABLE+0x17:
- case eng_3D_FOG_TABLE+0x18: case eng_3D_FOG_TABLE+0x19: case eng_3D_FOG_TABLE+0x1A: case eng_3D_FOG_TABLE+0x1B:
- case eng_3D_FOG_TABLE+0x1C: case eng_3D_FOG_TABLE+0x1D: case eng_3D_FOG_TABLE+0x1E: case eng_3D_FOG_TABLE+0x1F:
- val &= 0x7F;
- break;*/
-
- //ensata putchar port
- /*case 0x04FFF000:
- if(nds.ensataEmulation)
- printf("%c",val);
+ case REG_IF:
+ REG_IF_WriteByte<ARMCPU_ARM9>(0, val);
break;
-
- case eng_3D_GXSTAT:
- MMU_new.gxstat.write(8,adr,val);
- break;*/
-
- /*case REG_DISPA_WIN0H:
- GPU_setWIN0_H1(MainScreen.gpu, val);
- break ;
- case REG_DISPA_WIN0H+1:
- GPU_setWIN0_H0 (MainScreen.gpu, val);
- break ;
- case REG_DISPA_WIN1H:
- GPU_setWIN1_H1 (MainScreen.gpu,val);
- break ;
- case REG_DISPA_WIN1H+1:
- GPU_setWIN1_H0 (MainScreen.gpu,val);
- break ; */
-
- /*case REG_DISPB_WIN0H:
- GPU_setWIN0_H1(SubScreen.gpu,val);
- break ;
- case REG_DISPB_WIN0H+1:
- GPU_setWIN0_H0(SubScreen.gpu,val);
- break ;
- case REG_DISPB_WIN1H:
- GPU_setWIN1_H1(SubScreen.gpu,val);
- break ;
- case REG_DISPB_WIN1H+1:
- GPU_setWIN1_H0(SubScreen.gpu,val);
- break ;*/
-
- /*case REG_DISPA_WIN0V:
- GPU_setWIN0_V1(MainScreen.gpu,val) ;
- break ;
- case REG_DISPA_WIN0V+1:
- GPU_setWIN0_V0(MainScreen.gpu,val) ;
- break ;
- case REG_DISPA_WIN1V:
- GPU_setWIN1_V1(MainScreen.gpu,val) ;
- break ;
- case REG_DISPA_WIN1V+1:
- GPU_setWIN1_V0(MainScreen.gpu,val) ;
- break ; */
-
- /*case REG_DISPB_WIN0V:
- GPU_setWIN0_V1(SubScreen.gpu,val) ;
- break ;
- case REG_DISPB_WIN0V+1:
- GPU_setWIN0_V0(SubScreen.gpu,val) ;
- break ;
- case REG_DISPB_WIN1V:
- GPU_setWIN1_V1(SubScreen.gpu,val) ;
- break ;
- case REG_DISPB_WIN1V+1:
- GPU_setWIN1_V0(SubScreen.gpu,val) ;
- break ;*/
-
- /*case REG_DISPA_WININ:
- GPU_setWININ0(MainScreen.gpu,val) ;
- break ;
- case REG_DISPA_WININ+1:
- GPU_setWININ1(MainScreen.gpu,val) ;
- break ;
- case REG_DISPA_WINOUT:
- GPU_setWINOUT(MainScreen.gpu,val) ;
- break ;
- case REG_DISPA_WINOUT+1:
- GPU_setWINOBJ(MainScreen.gpu,val);
- break ; */
-
- /*case REG_DISPB_WININ:
- GPU_setWININ0(SubScreen.gpu,val) ;
- break ;
- case REG_DISPB_WININ+1:
- GPU_setWININ1(SubScreen.gpu,val) ;
- break ;
- case REG_DISPB_WINOUT:
- GPU_setWINOUT(SubScreen.gpu,val) ;
- break ;
- case REG_DISPB_WINOUT+1:
- GPU_setWINOBJ(SubScreen.gpu,val) ;
- break ;*/
-
- /*case REG_DISPA_BLDCNT:
- GPU_setBLDCNT_HIGH(MainScreen.gpu,val);
+ case REG_IF + 1:
+ REG_IF_WriteByte<ARMCPU_ARM9>(1, val);
break;
- case REG_DISPA_BLDCNT+1:
- GPU_setBLDCNT_LOW (MainScreen.gpu,val);
- break;*/
-
- /*case REG_DISPB_BLDCNT:
- GPU_setBLDCNT_HIGH (SubScreen.gpu,val);
+ case REG_IF + 2:
+ REG_IF_WriteByte<ARMCPU_ARM9>(2, val);
break;
- case REG_DISPB_BLDCNT+1:
- GPU_setBLDCNT_LOW (SubScreen.gpu,val);
- break;*/
-
- /*case REG_DISPA_BLDALPHA:
- MainScreen.gpu->setBLDALPHA_EVB(val);
+ case REG_IF + 3:
+ REG_IF_WriteByte<ARMCPU_ARM9>(3, val);
break;
- case REG_DISPA_BLDALPHA+1:
- MainScreen.gpu->setBLDALPHA_EVA(val);
- break;*/
-
- /*case REG_DISPB_BLDALPHA:
- SubScreen.gpu->setBLDALPHA_EVB(val);
- break;
- case REG_DISPB_BLDALPHA+1:
- SubScreen.gpu->setBLDALPHA_EVA(val);
- break;*/
-
- /*case REG_DISPA_BLDY:
- GPU_setBLDY_EVY(MainScreen.gpu,val) ;
- break ;
- case REG_DISPB_BLDY:
- GPU_setBLDY_EVY(SubScreen.gpu,val) ;
- break;*/
-
- /*case REG_AUXSPICNT:
- write_auxspicnt(9,8,0,val);
- return;
- case REG_AUXSPICNT+1:
- write_auxspicnt(9,8,1,val);
- return;
-
- case REG_AUXSPIDATA:
- if(val!=0) MMU.AUX_SPI_CMD = val & 0xFF;
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][(REG_AUXSPIDATA >> 20) & 0xff], REG_AUXSPIDATA & 0xfff, MMU_new.backupDevice.data_command((uint8_t)val,ARMCPU_ARM9));
- MMU.AUX_SPI_CNT &= ~0x80; //remove busy flag
- return;*/
-
- case REG_WRAMCNT:
- /* Update WRAMSTAT at the ARM7 side */
- T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x241, val);
- break;
-
- //case REG_POWCNT1: writereg_POWCNT1(8,adr,val); break;
-
- //case REG_DISPA_DISP3DCNT: writereg_DISP3DCNT(8,adr,val); return;
- //case REG_DISPA_DISP3DCNT+1: writereg_DISP3DCNT(8,adr,val); return;
-
- case REG_IF: REG_IF_WriteByte<ARMCPU_ARM9>(0,val); break;
- case REG_IF+1: REG_IF_WriteByte<ARMCPU_ARM9>(1,val); break;
- case REG_IF+2: REG_IF_WriteByte<ARMCPU_ARM9>(2,val); break;
- case REG_IF+3: REG_IF_WriteByte<ARMCPU_ARM9>(3,val); break;
-
- /*case eng_3D_CLEAR_COLOR+0: case eng_3D_CLEAR_COLOR+1:
- case eng_3D_CLEAR_COLOR+2: case eng_3D_CLEAR_COLOR+3:
- //T1WriteByte((uint8_t*)&gfx3d.state.clearColor,adr-eng_3D_CLEAR_COLOR,val);
- break;*/
case REG_VRAMCNTA:
case REG_VRAMCNTB:
@@ -2387,178 +1669,77 @@
case REG_VRAMCNTE:
case REG_VRAMCNTF:
case REG_VRAMCNTG:
+ case REG_WRAMCNT:
case REG_VRAMCNTH:
case REG_VRAMCNTI:
- MMU_VRAMmapControl(static_cast<uint8_t>(adr-REG_VRAMCNTA), val);
- break;
- /*case REG_DISPA_DISPMMEMFIFO:
- {
- DISP_FIFOsend(val);
- return;
- }*/
- #ifdef LOG_CARD
- case 0x040001A0 : /* TODO (clear): ??? */
- case 0x040001A1 :
- case 0x040001A2 :
- case 0x040001A8 :
- case 0x040001A9 :
- case 0x040001AA :
- case 0x040001AB :
- case 0x040001AC :
- case 0x040001AD :
- case 0x040001AE :
- case 0x040001AF :
- LOG("%08X : %02X\r\n", adr, val);
- #endif
-
- }
-
- MMU.MMU_MEM[ARMCPU_ARM9][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM9][adr>>20]]=val;
- return;
- }
-
- //bool unmapped = false, restricted = false;
- //adr = MMU_LCDmap<ARMCPU_ARM9>(adr, unmapped, restricted);
- //if(unmapped) return;
- //if(restricted) return; //block 8bit vram writes
+ MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA), val);
+ }
+
+ MMU.MMU_MEM[ARMCPU_ARM9][adr >> 20][adr & MMU.MMU_MASK[ARMCPU_ARM9][adr >> 20]] = val;
+ return;
+ }
+
+#ifdef HAVE_JIT
+ if (JIT_MAPPED(adr, ARMCPU_ARM9))
+ JIT_COMPILED_FUNC_PREMASKED(adr, ARMCPU_ARM9, 0) = 0;
+#endif
// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF [shash]
- MMU.MMU_MEM[ARMCPU_ARM9][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM9][adr>>20]]=val;
-}
-
-//================================================= MMU ARM9 write 16
+ MMU.MMU_MEM[ARMCPU_ARM9][adr >> 20][adr & MMU.MMU_MASK[ARMCPU_ARM9][adr >> 20]] = val;
+}
+
+// ================================================= MMU ARM9 write 16
void FASTCALL _MMU_ARM9_write16(uint32_t adr, uint16_t val)
{
adr &= 0x0FFFFFFE;
- //mmu_log_debug_ARM9(adr, "(write16) 0x%04X", val);
-
if (adr < 0x02000000)
{
- T1WriteWord(MMU.ARM9_ITCM, adr&0x7FFF, val);
- return;
- }
-
- if ( (adr >= 0x08000000) && (adr < 0x0A010000) )
- {
- //addon.write16(adr, val);
- return;
- }
-
- if((adr >> 24) == 4)
- {
- // TODO: add pal reg
- /*if (nds.power1.gpuMain == 0)
- if ((adr >= 0x04000008) && (adr<=0x0400005F)) return;*/
- /*if (nds.power1.gpuSub == 0)
- if ((adr >= 0x04001008) && (adr<=0x0400105F)) return;*/
- /*if (nds.power1.gfx3d_geometry == 0)
- if ((adr >= 0x04000400) && (adr<=0x040006FF)) return;
- if (nds.power1.gfx3d_render == 0)
- if ((adr >= 0x04000320) && (adr<=0x040003FF)) return;*/
-
- if(MMU_new.is_dma(adr)) {
- if(val==0x02e9) {
- //int zzz=9;
- }
- MMU_new.write_dma(ARMCPU_ARM9,16,adr,val);
+#ifdef HAVE_JIT
+ JIT_COMPILED_FUNC_KNOWNBANK(adr, ARM9_ITCM, 0x7FFF, 0) = 0;
+#endif
+ T1WriteWord(MMU.ARM9_ITCM, adr & 0x7FFF, val);
+ return;
+ }
+
+ if (adr >= 0x08000000 && adr < 0x0A010000)
+ return;
+
+ if ((adr >> 24) == 4)
+ {
+ if (MMU_new.is_dma(adr))
+ {
+ MMU_new.write_dma(ARMCPU_ARM9, 16, adr, val);
return;
}
switch (adr >> 4)
{
- //toon table
+ // toon table
case 0x0400038:
case 0x0400039:
case 0x040003A:
case 0x040003B:
- ((uint16_t *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[(adr & 0xFFF)>>1] = val;
- //gfx3d_UpdateToonTable((adr & 0x3F) >> 1, val);
- return;
+ reinterpret_cast<uint16_t *>(MMU.MMU_MEM[ARMCPU_ARM9][0x40])[(adr & 0xFFF) >> 1] = val;
+ return;
}
// Address is an IO register
- switch(adr)
- {
- /*case eng_3D_GXSTAT:
- MMU_new.gxstat.write(16,adr,val);
- break;*/
-
- //fog table: only write bottom 7 bits
- /*case eng_3D_FOG_TABLE+0x00: case eng_3D_FOG_TABLE+0x02: case eng_3D_FOG_TABLE+0x04: case eng_3D_FOG_TABLE+0x06:
- case eng_3D_FOG_TABLE+0x08: case eng_3D_FOG_TABLE+0x0A: case eng_3D_FOG_TABLE+0x0C: case eng_3D_FOG_TABLE+0x0E:
- case eng_3D_FOG_TABLE+0x10: case eng_3D_FOG_TABLE+0x12: case eng_3D_FOG_TABLE+0x14: case eng_3D_FOG_TABLE+0x16:
- case eng_3D_FOG_TABLE+0x18: case eng_3D_FOG_TABLE+0x1A: case eng_3D_FOG_TABLE+0x1C: case eng_3D_FOG_TABLE+0x1E:
- val &= 0x7F7F;
- break;*/
-
- /*case REG_DISPA_BG2XL: MainScreen.gpu->setAffineStartWord(2,0,val,0); break;
- case REG_DISPA_BG2XH: MainScreen.gpu->setAffineStartWord(2,0,val,1); break;
- case REG_DISPA_BG2YL: MainScreen.gpu->setAffineStartWord(2,1,val,0); break;
- case REG_DISPA_BG2YH: MainScreen.gpu->setAffineStartWord(2,1,val,1); break;
- case REG_DISPA_BG3XL: MainScreen.gpu->setAffineStartWord(3,0,val,0); break;
- case REG_DISPA_BG3XH: MainScreen.gpu->setAffineStartWord(3,0,val,1); break;
- case REG_DISPA_BG3YL: MainScreen.gpu->setAffineStartWord(3,1,val,0); break;
- case REG_DISPA_BG3YH: MainScreen.gpu->setAffineStartWord(3,1,val,1); break;
- case REG_DISPB_BG2XL: SubScreen.gpu->setAffineStartWord(2,0,val,0); break;
- case REG_DISPB_BG2XH: SubScreen.gpu->setAffineStartWord(2,0,val,1); break;
- case REG_DISPB_BG2YL: SubScreen.gpu->setAffineStartWord(2,1,val,0); break;
- case REG_DISPB_BG2YH: SubScreen.gpu->setAffineStartWord(2,1,val,1); break;
- case REG_DISPB_BG3XL: SubScreen.gpu->setAffineStartWord(3,0,val,0); break;
- case REG_DISPB_BG3XH: SubScreen.gpu->setAffineStartWord(3,0,val,1); break;
- case REG_DISPB_BG3YL: SubScreen.gpu->setAffineStartWord(3,1,val,0); break;
- case REG_DISPB_BG3YH: SubScreen.gpu->setAffineStartWord(3,1,val,1); break;*/
-
- //case REG_DISPA_DISP3DCNT: writereg_DISP3DCNT(16,adr,val); return;
-
- // Alpha test reference value - Parameters:1
- /*case eng_3D_ALPHA_TEST_REF:
- {
- ((uint16_t *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[0x340>>1] = val;
- //gfx3d_glAlphaFunc(val);
- return;
- }
-
- case eng_3D_CLEAR_COLOR:
- case eng_3D_CLEAR_COLOR+2:
- {
- //T1WriteWord((uint8_t*)&gfx3d.state.clearColor,adr-eng_3D_CLEAR_COLOR,val);
- break;
- }
-
- // Clear background depth setup - Parameters:2
- case eng_3D_CLEAR_DEPTH:
- {
- ((uint16_t *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[0x354>>1] = val;
- //gfx3d_glClearDepth(val);
- return;
- }
- // Fog Color - Parameters:4b
- case eng_3D_FOG_COLOR:
- {
- ((uint16_t *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[0x358>>1] = val;
- //gfx3d_glFogColor(val);
- return;
- }
- case eng_3D_FOG_OFFSET:
- {
- ((uint32_t *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[0x35C>>1] = val;
- //gfx3d_glFogOffset(val);
- return;
- }*/
-
+ switch (adr)
+ {
case REG_DIVCNT:
MMU_new.div.write16(val);
execdiv();
return;
+
#if 1
case REG_DIVNUMER:
- case REG_DIVNUMER+2:
- case REG_DIVNUMER+4:
+ case REG_DIVNUMER + 2:
+ case REG_DIVNUMER + 4:
printf("DIV: 16 write NUMER %08X. PLEASE REPORT! \n", val);
break;
case REG_DIVDENOM:
- case REG_DIVDENOM+2:
- case REG_DIVDENOM+4:
+ case REG_DIVDENOM + 2:
+ case REG_DIVDENOM + 4:
printf("DIV: 16 write DENOM %08X. PLEASE REPORT! \n", val);
break;
#endif
@@ -2567,131 +1748,6 @@
execsqrt();
return;
- /*case REG_DISPA_BLDCNT:
- GPU_setBLDCNT(MainScreen.gpu,val) ;
- break ;
- case REG_DISPB_BLDCNT:
- GPU_setBLDCNT(SubScreen.gpu,val) ;
- break ;
- case REG_DISPA_BLDALPHA:
- MainScreen.gpu->setBLDALPHA(val);
- break ;
- case REG_DISPB_BLDALPHA:
- SubScreen.gpu->setBLDALPHA(val);
- break ;
- case REG_DISPA_BLDY:
- GPU_setBLDY_EVY(MainScreen.gpu,val) ;
- break ;
- case REG_DISPB_BLDY:
- GPU_setBLDY_EVY(SubScreen.gpu,val) ;
- break;
- case REG_DISPA_MASTERBRIGHT:
- GPU_setMasterBrightness (MainScreen.gpu, val);
- break;*/
- /*
- case REG_DISPA_MOSAIC:
- GPU_setMOSAIC(MainScreen.gpu,val) ;
- break ;
- case REG_DISPB_MOSAIC:
- GPU_setMOSAIC(SubScreen.gpu,val) ;
- break ;
- */
- //case REG_DISPA_BG0HOFS:
- // GPU_setBGxHOFS(0, MainScreen.gpu, val);
- // break;
- //case REG_DISPA_BG0VOFS:
- // GPU_setBGxVOFS(0, MainScreen.gpu, val);
- // break;
- //case REG_DISPA_BG1HOFS:
- // GPU_setBGxHOFS(1, MainScreen.gpu, val);
- // break;
- //case REG_DISPA_BG1VOFS:
- // GPU_setBGxVOFS(1, MainScreen.gpu, val);
- // break;
- //case REG_DISPA_BG2HOFS:
- // GPU_setBGxHOFS(2, MainScreen.gpu, val);
- // break;
- //case REG_DISPA_BG2VOFS:
- // GPU_setBGxVOFS(2, MainScreen.gpu, val);
- // break;
- //case REG_DISPA_BG3HOFS:
- // GPU_setBGxHOFS(3, MainScreen.gpu, val);
- // break;
- //case REG_DISPA_BG3VOFS:
- // GPU_setBGxVOFS(3, MainScreen.gpu, val);
- // break;
-
- /*case REG_DISPA_WIN0H:
- GPU_setWIN0_H (MainScreen.gpu,val) ;
- break ;
- case REG_DISPA_WIN1H:
- GPU_setWIN1_H(MainScreen.gpu,val) ;
- break ;
- case REG_DISPB_WIN0H:
- GPU_setWIN0_H(SubScreen.gpu,val) ;
- break ;
- case REG_DISPB_WIN1H:
- GPU_setWIN1_H(SubScreen.gpu,val) ;
- break ;
- case REG_DISPA_WIN0V:
- GPU_setWIN0_V(MainScreen.gpu,val) ;
- break ;
- case REG_DISPA_WIN1V:
- GPU_setWIN1_V(MainScreen.gpu,val) ;
- break ;
- case REG_DISPB_WIN0V:
- GPU_setWIN0_V(SubScreen.gpu,val) ;
- break ;
- case REG_DISPB_WIN1V:
- GPU_setWIN1_V(SubScreen.gpu,val) ;
- break ;
- case REG_DISPA_WININ:
- GPU_setWININ(MainScreen.gpu, val) ;
- break ;
- case REG_DISPA_WINOUT:
- GPU_setWINOUT16(MainScreen.gpu, val) ;
- break ; */
-
- /* case REG_DISPB_BG0HOFS:
- GPU_setBGxHOFS(0, SubScreen.gpu, val);
- break;
- case REG_DISPB_BG0VOFS:
- GPU_setBGxVOFS(0, SubScreen.gpu, val);
- break;
- case REG_DISPB_BG1HOFS:
- GPU_setBGxHOFS(1, SubScreen.gpu, val);
- break;
- case REG_DISPB_BG1VOFS:
- GPU_setBGxVOFS(1, SubScreen.gpu, val);
- break;
- case REG_DISPB_BG2HOFS:
- GPU_setBGxHOFS(2, SubScreen.gpu, val);
- break;
- case REG_DISPB_BG2VOFS:
- GPU_setBGxVOFS(2, SubScreen.gpu, val);
- break;
- case REG_DISPB_BG3HOFS:
- GPU_setBGxHOFS(3, SubScreen.gpu, val);
- break;
- case REG_DISPB_BG3VOFS:
- GPU_setBGxVOFS(3, SubScreen.gpu, val);
- break;*/
-
- /*case REG_DISPB_WININ:
- GPU_setWININ(SubScreen.gpu, val) ;
- break ;
- case REG_DISPB_WINOUT:
- GPU_setWINOUT16(SubScreen.gpu, val) ;
- break ;*/
-
- /*case REG_DISPB_MASTERBRIGHT:
- GPU_setMasterBrightness (SubScreen.gpu, val);
- break;*/
-
- /*case REG_POWCNT1:
- writereg_POWCNT1(16,adr,val);
- return;*/
-
case REG_EXMEMCNT:
{
uint16_t remote_proc = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x204);
@@ -2700,74 +1756,13 @@
return;
}
- /*case REG_AUXSPICNT:
- write_auxspicnt(9,16,0,val);
- return;
-
- case REG_AUXSPIDATA:
- if(val!=0)
- MMU.AUX_SPI_CMD = val & 0xFF;
-
- //T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_AUXSPIDATA >> 20) & 0xff], REG_AUXSPIDATA & 0xfff, bm_transfer(&MMU.bupmem, val));
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][(REG_AUXSPIDATA >> 20) & 0xff], REG_AUXSPIDATA & 0xfff, MMU_new.backupDevice.data_command((uint8_t)val,ARMCPU_ARM9));
- MMU.AUX_SPI_CNT &= ~0x80; //remove busy flag
- return;*/
-
- /*case REG_DISPA_BG0CNT :
- //GPULOG("MAIN BG0 SETPROP 16B %08X\r\n", val);
- //GPU_setBGProp(MainScreen.gpu, 0, val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x8, val);
- return;
- case REG_DISPA_BG1CNT :
- //GPULOG("MAIN BG1 SETPROP 16B %08X\r\n", val);
- //GPU_setBGProp(MainScreen.gpu, 1, val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xA, val);
- return;
- case REG_DISPA_BG2CNT :
- //GPULOG("MAIN BG2 SETPROP 16B %08X\r\n", val);
- //GPU_setBGProp(MainScreen.gpu, 2, val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xC, val);
- return;
- case REG_DISPA_BG3CNT :
- //GPULOG("MAIN BG3 SETPROP 16B %08X\r\n", val);
- //GPU_setBGProp(MainScreen.gpu, 3, val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xE, val);
- return;
- case REG_DISPB_BG0CNT :
- //GPULOG("SUB BG0 SETPROP 16B %08X\r\n", val);
- //GPU_setBGProp(SubScreen.gpu, 0, val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1008, val);
- return;
- case REG_DISPB_BG1CNT :
- //GPULOG("SUB BG1 SETPROP 16B %08X\r\n", val);
- //GPU_setBGProp(SubScreen.gpu, 1, val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x100A, val);
- return;
- case REG_DISPB_BG2CNT :
- //GPULOG("SUB BG2 SETPROP 16B %08X\r\n", val);
- //GPU_setBGProp(SubScreen.gpu, 2, val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x100C, val);
- return;
- case REG_DISPB_BG3CNT :
- //GPULOG("SUB BG3 SETPROP 16B %08X\r\n", val);
- //GPU_setBGProp(SubScreen.gpu, 3, val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x100E, val);
- return;*/
-
case REG_VRAMCNTA:
case REG_VRAMCNTC:
case REG_VRAMCNTE:
- MMU_VRAMmapControl(static_cast<uint8_t>(adr-REG_VRAMCNTA), val & 0xFF);
- MMU_VRAMmapControl(static_cast<uint8_t>(adr-REG_VRAMCNTA+1), val >> 8);
- break;
case REG_VRAMCNTG:
- MMU_VRAMmapControl(static_cast<uint8_t>(adr-REG_VRAMCNTA), val & 0xFF);
- /* Update WRAMSTAT at the ARM7 side */
- T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x241, val >> 8);
- break;
case REG_VRAMCNTH:
- MMU_VRAMmapControl(static_cast<uint8_t>(adr-REG_VRAMCNTA), val & 0xFF);
- MMU_VRAMmapControl(static_cast<uint8_t>(adr-REG_VRAMCNTA+1), val >> 8);
+ MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA), val & 0xFF);
+ MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA + 1), val >> 8);
break;
case REG_IME:
@@ -2775,444 +1770,140 @@
MMU.reg_IME[ARMCPU_ARM9] = val & 0x01;
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x208, val);
return;
- case REG_IE :
+ case REG_IE:
NDS_Reschedule();
- MMU.reg_IE[ARMCPU_ARM9] = (MMU.reg_IE[ARMCPU_ARM9]&0xFFFF0000) | val;
- return;
- case REG_IE + 2 :
+ MMU.reg_IE[ARMCPU_ARM9] = (MMU.reg_IE[ARMCPU_ARM9] & 0xFFFF0000) | val;
+ return;
+ case REG_IE + 2:
NDS_Reschedule();
- MMU.reg_IE[ARMCPU_ARM9] = (MMU.reg_IE[ARMCPU_ARM9]&0xFFFF) | (((uint32_t)val)<<16);
- return;
- case REG_IF: REG_IF_WriteWord<ARMCPU_ARM9>(0,val); return;
- case REG_IF+2: REG_IF_WriteWord<ARMCPU_ARM9>(2,val); return;
-
- case REG_IPCSYNC :
- MMU_IPCSync(ARMCPU_ARM9, val);
- return;
-
- case REG_IPCFIFOCNT :
- IPC_FIFOcnt(ARMCPU_ARM9, val);
- return;
- case REG_TM0CNTL :
- case REG_TM1CNTL :
- case REG_TM2CNTL :
- case REG_TM3CNTL :
- MMU.timerReload[ARMCPU_ARM9][(adr>>2)&3] = val;
- return;
- case REG_TM0CNTH :
- case REG_TM1CNTH :
- case REG_TM2CNTH :
- case REG_TM3CNTH :
+ MMU.reg_IE[ARMCPU_ARM9] = (MMU.reg_IE[ARMCPU_ARM9] & 0xFFFF) | (static_cast<uint32_t>(val) << 16);
+ return;
+ case REG_IF:
+ REG_IF_WriteWord<ARMCPU_ARM9>(0, val);
+ return;
+ case REG_IF+2:
+ REG_IF_WriteWord<ARMCPU_ARM9>(2, val); return;
+
+ case REG_IPCSYNC:
+ MMU_IPCSync(ARMCPU_ARM9, val);
+ return;
+
+ case REG_IPCFIFOCNT:
+ IPC_FIFOcnt(ARMCPU_ARM9, val);
+ return;
+ case REG_TM0CNTL:
+ case REG_TM1CNTL:
+ case REG_TM2CNTL:
+ case REG_TM3CNTL:
+ MMU.timerReload[ARMCPU_ARM9][(adr >> 2) & 3] = val;
+ return;
+ case REG_TM0CNTH:
+ case REG_TM1CNTH:
+ case REG_TM2CNTH:
+ case REG_TM3CNTH:
{
- int timerIndex = ((adr-2)>>2)&0x3;
+ int timerIndex = ((adr - 2) >> 2) & 0x3;
write_timer(ARMCPU_ARM9, timerIndex, val);
return;
}
- /*case REG_DISPA_DISPCNT :
- {
- uint32_t v = (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0) & 0xFFFF0000) | val;
- //GPU_setVideoProp(MainScreen.gpu, v);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0, v);
- return;
- }
- case REG_DISPA_DISPCNT+2 :
- {
- uint32_t v = (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0) & 0xFFFF) | ((uint32_t) val << 16);
- //GPU_setVideoProp(MainScreen.gpu, v);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0, v);
- }
- return;
- case REG_DISPA_DISPCAPCNT :
- {
- uint32_t v = (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x64) & 0xFFFF0000) | val;
- //GPU_set_DISPCAPCNT(v);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x64, v);
- return;
- }
- case REG_DISPA_DISPCAPCNT + 2:
- {
- uint32_t v = (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x64) & 0xFFFF) | ((uint32_t)val << 16);
- //GPU_set_DISPCAPCNT(v);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x64, v);
- return;
- }
-
- case REG_DISPB_DISPCNT :
- {
- uint32_t v = (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1000) & 0xFFFF0000) | val;
- //GPU_setVideoProp(SubScreen.gpu, v);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1000, v);
- return;
- }
- case REG_DISPB_DISPCNT+2 :
- {
- //emu_halt();
- uint32_t v = (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1000) & 0xFFFF) | ((uint32_t) val << 16);
- //GPU_setVideoProp(SubScreen.gpu, v);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1000, v);
- return;
- }*/
-
- /*case REG_DISPA_DISPMMEMFIFO:
- {
- DISP_FIFOsend(val);
- return;
- }*/
-
- case REG_GCROMCTRL :
- MMU_writeToGCControl<ARMCPU_ARM9>( (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1A4) & 0xFFFF0000) | val);
- return;
- case REG_GCROMCTRL+2 :
- MMU_writeToGCControl<ARMCPU_ARM9>( (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1A4) & 0xFFFF) | ((uint32_t) val << 16));
- return;
- }
-
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][adr>>20], adr&MMU.MMU_MASK[ARMCPU_ARM9][adr>>20], val);
- return;
- }
-
+ case REG_GCROMCTRL:
+ MMU_writeToGCControl<ARMCPU_ARM9>((T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1A4) & 0xFFFF0000) | val);
+ return;
+ case REG_GCROMCTRL + 2:
+ MMU_writeToGCControl<ARMCPU_ARM9>((T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1A4) & 0xFFFF) | (static_cast<uint32_t>(val) << 16));
+ return;
+ }
+
+ T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr >> 20], val);
+ return;
+ }
bool unmapped, restricted;
- adr = MMU_LCDmap/*<ARMCPU_ARM9>*/(adr, unmapped, restricted);
- if(unmapped) return;
+ adr = MMU_LCDmap<ARMCPU_ARM9>(adr, unmapped, restricted);
+ if (unmapped)
+ return;
+
+#ifdef HAVE_JIT
+ if (JIT_MAPPED(adr, ARMCPU_ARM9))
+ JIT_COMPILED_FUNC_PREMASKED(adr, ARMCPU_ARM9, 0) = 0;
+#endif
// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF [shash]
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][adr>>20], adr&MMU.MMU_MASK[ARMCPU_ARM9][adr>>20], val);
-}
-
-//================================================= MMU ARM9 write 32
+ T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr >> 20], val);
+}
+
+// ================================================= MMU ARM9 write 32
void FASTCALL _MMU_ARM9_write32(uint32_t adr, uint32_t val)
{
adr &= 0x0FFFFFFC;
- //mmu_log_debug_ARM9(adr, "(write32) 0x%08X", val);
-
- if(adr<0x02000000)
- {
- T1WriteLong(MMU.ARM9_ITCM, adr&0x7FFF, val);
- return ;
- }
-
-
- if ( (adr >= 0x08000000) && (adr < 0x0A010000) )
- {
- //addon.write32(adr, val);
- return;
- }
-
- if((adr&0x0F000000)==0x05000000)
- {
- //int zzz=9;
- }
-
-#if 0
- if ((adr & 0xFF800000) == 0x04800000) {
- // access to non regular hw registers
- // return to not overwrite valid data
- return ;
- }
+ if (adr < 0x02000000)
+ {
+#ifdef HAVE_JIT
+ JIT_COMPILED_FUNC_KNOWNBANK(adr, ARM9_ITCM, 0x7FFF, 0) = 0;
+ JIT_COMPILED_FUNC_KNOWNBANK(adr, ARM9_ITCM, 0x7FFF, 1) = 0;
#endif
-
- if((adr>>24)==4)
- {
- // TODO: add pal reg
- /*if (nds.power1.gpuMain == 0)
- if ((adr >= 0x04000008) && (adr<=0x0400005F)) return;*/
- /*if (nds.power1.gpuSub == 0)
- if ((adr >= 0x04001008) && (adr<=0x0400105F)) return;*/
- /*if (nds.power1.gfx3d_geometry == 0)
- if ((adr >= 0x04000400) && (adr<=0x040006FF)) return;
- if (nds.power1.gfx3d_render == 0)
- if ((adr >= 0x04000320) && (adr<=0x040003FF)) return;*/
-
- // MightyMax: no need to do several ifs, when only one can happen
- // switch/case instead
- // both comparison >=,< per if can be replaced by one bit comparison since
- // they are 2^4 aligned and 2^4n wide
- // this looks ugly but should reduce load on register writes, they are done as
- // lookups by the compiler
- /*switch (adr >> 4)
- {
- case 0x400033: //edge color table
- ((uint32_t *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[(adr & 0xFFF) >> 2] = val;
- return;
-
- case 0x400038:
- case 0x400039:
- case 0x40003A:
- case 0x40003B: //toon table
- ((uint32_t *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[(adr & 0xFFF) >> 2] = val;
- //gfx3d_UpdateToonTable((adr & 0x3F) >> 1, val);
- return;
-
- case 0x400040:
- case 0x400041:
- case 0x400042:
- case 0x400043: // FIFO Commands
- ((uint32_t *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[(adr & 0xFFF) >> 2] = val;
- //gfx3d_sendCommandToFIFO(val);
- return;
-
- case 0x400044:
- case 0x400045:
- case 0x400046:
- case 0x400047:
- case 0x400048:
- case 0x400049:
- case 0x40004A:
- case 0x40004B:
- case 0x40004C:
- case 0x40004D:
- case 0x40004E:
- case 0x40004F:
- case 0x400050:
- case 0x400051:
- case 0x400052:
- case 0x400053:
- case 0x400054:
- case 0x400055:
- case 0x400056:
- case 0x400057:
- case 0x400058:
- case 0x400059:
- case 0x40005A:
- case 0x40005B:
- case 0x40005C: // Individual Commands
- if (gxFIFO.size > 254)
- nds.freezeBus = true;
-
- ((uint32_t *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[(adr & 0xFFF) >> 2] = val;
- //gfx3d_sendCommand(adr, val);
- return;
-
- default:
- break;
- }*/
-
- if(MMU_new.is_dma(adr)) {
- MMU_new.write_dma(ARMCPU_ARM9,32,adr,val);
+ T1WriteLong(MMU.ARM9_ITCM, adr & 0x7FFF, val);
+ return;
+ }
+
+ if (adr >= 0x08000000 && adr < 0x0A010000)
+ return;
+
+ if ((adr >> 24) == 4)
+ {
+ if (MMU_new.is_dma(adr))
+ {
+ MMU_new.write_dma(ARMCPU_ARM9, 32, adr, val);
return;
}
- switch(adr)
- {
- case REG_SQRTCNT: MMU_new.sqrt.write16((uint16_t)val); return;
- case REG_DIVCNT: MMU_new.div.write16((uint16_t)val); return;
-
- //case REG_POWCNT1: writereg_POWCNT1(32,adr,val); break;
-
- //fog table: only write bottom 7 bits
- /*case eng_3D_FOG_TABLE+0x00: case eng_3D_FOG_TABLE+0x04: case eng_3D_FOG_TABLE+0x08: case eng_3D_FOG_TABLE+0x0C:
- case eng_3D_FOG_TABLE+0x10: case eng_3D_FOG_TABLE+0x14: case eng_3D_FOG_TABLE+0x18: case eng_3D_FOG_TABLE+0x1C:
- val &= 0x7F7F7F7F;
- break;*/
-
-
- //ensata handshaking port?
- /*case 0x04FFF010:
- if(nds.ensataEmulation && nds.ensataHandshake == ENSATA_HANDSHAKE_ack && val == 0x13579bdf)
- nds.ensataHandshake = ENSATA_HANDSHAKE_confirm;
- if(nds.ensataEmulation && nds.ensataHandshake == ENSATA_HANDSHAKE_confirm && val == 0xfdb97531)
- {
- printf("ENSATA HANDSHAKE COMPLETE\n");
- nds.ensataHandshake = ENSATA_HANDSHAKE_complete;
- }
- break;*/
-
- //todo - these are usually write only regs (these and 1000 more)
- //shouldnt we block them from getting written? ugh
- /*case eng_3D_CLIPMTX_RESULT:
- if(nds.ensataEmulation && nds.ensataHandshake == ENSATA_HANDSHAKE_none && val==0x2468ace0)
- {
- printf("ENSATA HANDSHAKE BEGIN\n");
- nds.ensataHandshake = ENSATA_HANDSHAKE_query;
- }
- break;
-
- case eng_3D_GXSTAT:
- MMU_new.gxstat.write32(val);
- break;*/
- /*case REG_DISPA_BG2XL:
- MainScreen.gpu->setAffineStart(2,0,val);
- return;
- case REG_DISPA_BG2YL:
- MainScreen.gpu->setAffineStart(2,1,val);
- return;
- case REG_DISPB_BG2XL:
- SubScreen.gpu->setAffineStart(2,0,val);
- return;
- case REG_DISPB_BG2YL:
- SubScreen.gpu->setAffineStart(2,1,val);
- return;
- case REG_DISPA_BG3XL:
- MainScreen.gpu->setAffineStart(3,0,val);
- return;
- case REG_DISPA_BG3YL:
- MainScreen.gpu->setAffineStart(3,1,val);
- return;
- case REG_DISPB_BG3XL:
- SubScreen.gpu->setAffineStart(3,0,val);
- return;
- case REG_DISPB_BG3YL:
- SubScreen.gpu->setAffineStart(3,1,val);
- return;*/
-
- // Alpha test reference value - Parameters:1
- /*case eng_3D_ALPHA_TEST_REF:
- {
- ((uint32_t *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[0x340>>2] = val;
- //gfx3d_glAlphaFunc(val);
- return;
- }
-
- case eng_3D_CLEAR_COLOR:
- //T1WriteLong((uint8_t*)&gfx3d.state.clearColor,0,val);
- break;
-
- // Clear background depth setup - Parameters:2
- case eng_3D_CLEAR_DEPTH:
- {
- ((uint32_t *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[0x354>>2] = val;
- //gfx3d_glClearDepth(val);
- return;
- }
- // Fog Color - Parameters:4b
- case 0x04000358:
- {
- ((uint32_t *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[0x358>>2] = val;
- //gfx3d_glFogColor(val);
- return;
- }
- case 0x0400035C:
- {
- ((uint32_t *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[0x35C>>2] = val;
- //gfx3d_glFogOffset(val);
- return;
- }*/
-
- //case REG_DISPA_BG0HOFS:
- // GPU_setBGxHOFS(0, MainScreen.gpu, val&0xFFFF);
- // GPU_setBGxVOFS(0, MainScreen.gpu, (val>>16));
- // break;
-
- /*case REG_DISPA_WININ:
- {
- GPU_setWININ(MainScreen.gpu, val & 0xFFFF) ;
- GPU_setWINOUT16(MainScreen.gpu, (val >> 16) & 0xFFFF) ;
- break;
- }
- case REG_DISPB_WININ:
- {
- GPU_setWININ(SubScreen.gpu, val & 0xFFFF) ;
- GPU_setWINOUT16(SubScreen.gpu, (val >> 16) & 0xFFFF) ;
- break;
- }*/
-
- /*case REG_DISPA_WIN0H:
- {
- GPU_setWIN0_H(MainScreen.gpu, val&0xFFFF);
- GPU_setWIN1_H(MainScreen.gpu, val>>16);
- break;
- }
- case REG_DISPA_WIN0V:
- {
- GPU_setWIN0_V(MainScreen.gpu, val&0xFFFF);
- GPU_setWIN1_V(MainScreen.gpu, val>>16);
- break;
- }
- case REG_DISPB_WIN0H:
- {
- GPU_setWIN0_H(SubScreen.gpu, val&0xFFFF);
- GPU_setWIN1_H(SubScreen.gpu, val>>16);
- break;
- }
- case REG_DISPB_WIN0V:
- {
- GPU_setWIN0_V(SubScreen.gpu, val&0xFFFF);
- GPU_setWIN1_V(SubScreen.gpu, val>>16);
- break;
- }*/
-
- /*case REG_DISPA_MASTERBRIGHT:
- GPU_setMasterBrightness(MainScreen.gpu, val & 0xFFFF);
- break;
- case REG_DISPB_MASTERBRIGHT:
- GPU_setMasterBrightness(SubScreen.gpu, val & 0xFFFF);
- break;*/
-
- /*case REG_DISPA_BLDCNT:
- {
- GPU_setBLDCNT (MainScreen.gpu,val&0xffff);
- MainScreen.gpu->setBLDALPHA(val>>16);
- break;
- }
- case REG_DISPB_BLDCNT:
- {
- GPU_setBLDCNT (SubScreen.gpu,val&0xffff);
- SubScreen.gpu->setBLDALPHA(val>>16);
- break;
- }*/
-
- /*case REG_DISPA_BLDY:
- GPU_setBLDY_EVY(MainScreen.gpu,val&0xFFFF) ;
- break ;
- case REG_DISPB_BLDY:
- GPU_setBLDY_EVY(SubScreen.gpu,val&0xFFFF);
- break;*/
-
- /*case REG_DISPA_DISPCNT :
- //GPU_setVideoProp(MainScreen.gpu, val);
- //GPULOG("MAIN INIT 32B %08X\r\n", val);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0, val);
- return;
-
- case REG_DISPB_DISPCNT :
- //GPU_setVideoProp(SubScreen.gpu, val);
- //GPULOG("SUB INIT 32B %08X\r\n", val);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1000, val);
- return;*/
+ switch (adr)
+ {
+ case REG_SQRTCNT:
+ MMU_new.sqrt.write16(static_cast<uint16_t>(val));
+ return;
+ case REG_DIVCNT:
+ MMU_new.div.write16(static_cast<uint16_t>(val));
+ return;
case REG_VRAMCNTA:
- MMU_VRAMmapControl(static_cast<uint8_t>(adr-REG_VRAMCNTA), val & 0xFF);
- MMU_VRAMmapControl(static_cast<uint8_t>(adr-REG_VRAMCNTA+1), (val >> 8) & 0xFF);
- MMU_VRAMmapControl(static_cast<uint8_t>(adr-REG_VRAMCNTA+2), (val >> 16) & 0xFF);
- MMU_VRAMmapControl(static_cast<uint8_t>(adr-REG_VRAMCNTA+3), (val >> 24) & 0xFF);
- break;
case REG_VRAMCNTE:
- MMU_VRAMmapControl(static_cast<uint8_t>(adr-REG_VRAMCNTA), val & 0xFF);
- MMU_VRAMmapControl(static_cast<uint8_t>(adr-REG_VRAMCNTA+1), (val >> 8) & 0xFF);
- MMU_VRAMmapControl(static_cast<uint8_t>(adr-REG_VRAMCNTA+2), (val >> 16) & 0xFF);
- /* Update WRAMSTAT at the ARM7 side */
- T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x241, (val >> 24) & 0xFF);
+ MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA), val & 0xFF);
+ MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA + 1), (val >> 8) & 0xFF);
+ MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA + 2), (val >> 16) & 0xFF);
+ MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA + 3), (val >> 24) & 0xFF);
break;
case REG_VRAMCNTH:
- MMU_VRAMmapControl(static_cast<uint8_t>(adr-REG_VRAMCNTA), val & 0xFF);
- MMU_VRAMmapControl(static_cast<uint8_t>(adr-REG_VRAMCNTA+1), (val >> 8) & 0xFF);
+ MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA), val & 0xFF);
+ MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA + 1), (val >> 8) & 0xFF);
break;
- case REG_IME :
+ case REG_IME:
NDS_Reschedule();
MMU.reg_IME[ARMCPU_ARM9] = val & 0x01;
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x208, val);
return;
- case REG_IE :
+ case REG_IE:
NDS_Reschedule();
MMU.reg_IE[ARMCPU_ARM9] = val;
return;
- case REG_IF: REG_IF_WriteLong<ARMCPU_ARM9>(val); return;
-
- case REG_TM0CNTL:
- case REG_TM1CNTL:
- case REG_TM2CNTL:
- case REG_TM3CNTL:
+ case REG_IF:
+ REG_IF_WriteLong<ARMCPU_ARM9>(val);
+ return;
+
+ case REG_TM0CNTL:
+ case REG_TM1CNTL:
+ case REG_TM2CNTL:
+ case REG_TM3CNTL:
{
- int timerIndex = (adr>>2)&0x3;
- MMU.timerReload[ARMCPU_ARM9][timerIndex] = (uint16_t)val;
+ int timerIndex = (adr >> 2) & 0x3;
+ MMU.timerReload[ARMCPU_ARM9][timerIndex] = static_cast<uint16_t>(val);
T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & 0xFFF, static_cast<uint16_t>(val));
- write_timer(ARMCPU_ARM9, timerIndex, val>>16);
+ write_timer(ARMCPU_ARM9, timerIndex, val >> 16);
return;
}
@@ -3220,31 +1911,31 @@
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290, val);
execdiv();
return;
- case REG_DIVNUMER+4:
+ case REG_DIVNUMER + 4:
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x294, val);
execdiv();
return;
- case REG_DIVDENOM :
- {
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298, val);
- execdiv();
- return;
- }
- case REG_DIVDENOM+4 :
- {
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x29C, val);
- execdiv();
- return;
- }
-
- case REG_SQRTPARAM :
+ case REG_DIVDENOM:
+ {
+ T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298, val);
+ execdiv();
+ return;
+ }
+ case REG_DIVDENOM + 4:
+ {
+ T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x29C, val);
+ execdiv();
+ return;
+ }
+
+ case REG_SQRTPARAM:
{
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8, val);
execsqrt();
return;
}
- case REG_SQRTPARAM+4 :
+ case REG_SQRTPARAM + 4:
{
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2BC, val);
execsqrt();
@@ -3261,416 +1952,302 @@
IPC_FIFOsend(ARMCPU_ARM9, val);
return;
-
- case REG_GCROMCTRL :
+ case REG_GCROMCTRL:
MMU_writeToGCControl<ARMCPU_ARM9>(val);
return;
- case REG_DISPA_DISPCAPCNT :
- //INFO("MMU write32: REG_DISPA_DISPCAPCNT 0x%X\n", val);
- //GPU_set_DISPCAPCNT(val);
+ case REG_DISPA_DISPCAPCNT:
T1WriteLong(MMU.ARM9_REG, 0x64, val);
return;
- /*case REG_DISPA_BG0CNT :
- //GPU_setBGProp(MainScreen.gpu, 0, (val&0xFFFF));
- //GPU_setBGProp(MainScreen.gpu, 1, (val>>16));
- //if((val>>16)==0x400) emu_halt();
- T1WriteLong(MMU.ARM9_REG, 8, val);
- return;
- case REG_DISPA_BG2CNT :
- //GPU_setBGProp(MainScreen.gpu, 2, (val&0xFFFF));
- //GPU_setBGProp(MainScreen.gpu, 3, (val>>16));
- T1WriteLong(MMU.ARM9_REG, 0xC, val);
- return;
- case REG_DISPB_BG0CNT :
- //GPU_setBGProp(SubScreen.gpu, 0, (val&0xFFFF));
- //GPU_setBGProp(SubScreen.gpu, 1, (val>>16));
- T1WriteLong(MMU.ARM9_REG, 0x1008, val);
- return;
- case REG_DISPB_BG2CNT :
- //GPU_setBGProp(SubScreen.gpu, 2, (val&0xFFFF));
- //GPU_setBGProp(SubScreen.gpu, 3, (val>>16));
- T1WriteLong(MMU.ARM9_REG, 0x100C, val);
- return;*/
- /*case REG_DISPA_DISPMMEMFIFO:
- {
- DISP_FIFOsend(val);
- return;
- }*/
-
- //case REG_DISPA_DISP3DCNT: writereg_DISP3DCNT(32,adr,val); return;
-
case REG_GCDATAIN:
- slot1_device.write32(ARMCPU_ARM9, REG_GCDATAIN,val);
- return;
- }
-
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][adr>>20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr>>20], val);
+ slot1_device.write32(ARMCPU_ARM9, REG_GCDATAIN, val);
+ return;
+ }
+
+ T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr >> 20], val);
return;
}
bool unmapped, restricted;
- adr = MMU_LCDmap/*<ARMCPU_ARM9>*/(adr, unmapped, restricted);
- if(unmapped) return;
+ adr = MMU_LCDmap<ARMCPU_ARM9>(adr, unmapped, restricted);
+ if (unmapped)
+ return;
+
+#ifdef HAVE_JIT
+ if (JIT_MAPPED(adr, ARMCPU_ARM9))
+ {
+ JIT_COMPILED_FUNC_PREMASKED(adr, ARMCPU_ARM9, 0) = 0;
+ JIT_COMPILED_FUNC_PREMASKED(adr, ARMCPU_ARM9, 1) = 0;
+ }
+#endif
// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF [shash]
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][adr>>20], adr&MMU.MMU_MASK[ARMCPU_ARM9][adr>>20], val);
-}
-
-//================================================= MMU ARM9 read 08
+ T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr >> 20], val);
+}
+
+// ================================================= MMU ARM9 read 08
uint8_t FASTCALL _MMU_ARM9_read08(uint32_t adr)
{
adr &= 0x0FFFFFFF;
- //mmu_log_debug_ARM9(adr, "(read08) 0x%02X", MMU.MMU_MEM[ARMCPU_ARM9][(adr>>20)&0xFF][adr&MMU.MMU_MASK[ARMCPU_ARM9][(adr>>20)&0xFF]]);
-
- if(adr<0x02000000)
- return T1ReadByte(MMU.ARM9_ITCM, adr&0x7FFF);
-
- if ( (adr >= 0x08000000) && (adr < 0x0A010000) )
- return 0/*addon.read08(adr)*/;
-
- if (adr >> 24 == 4)
- { //Address is an IO register
-
- if(MMU_new.is_dma(adr)) return static_cast<uint8_t>(MMU_new.read_dma(ARMCPU_ARM9,8,adr));
-
- switch(adr)
- {
- case REG_IF: return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM9>());
- case REG_IF+1: return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM9>()>>8);
- case REG_IF+2: return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM9>()>>16);
- case REG_IF+3: return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM9>()>>24);
-
- /*case REG_DISPA_DISPSTAT:
- break;
- case REG_DISPA_DISPSTAT+1:
- break;
- case REG_DISPx_VCOUNT: return nds.VCount & 0xFF;
- case REG_DISPx_VCOUNT+1: return (nds.VCount>>8) & 0xFF;*/
-#if 0
- case REG_SQRTCNT: printf("ERROR 8bit SQRTCNT READ\n"); return 0;
- case REG_SQRTCNT+1: printf("ERROR 8bit SQRTCNT1 READ\n"); return 0;//(MMU_new.sqrt.read16() & 0xFF00)>>8;
-#else
- case REG_SQRTCNT: return MMU_new.sqrt.read16() & 0xFF;
- case REG_SQRTCNT+1: return (MMU_new.sqrt.read16()>>8) & 0xFF;
-#endif
- case REG_SQRTCNT+2: printf("ERROR 8bit SQRTCNT2 READ\n"); return 0;
- case REG_SQRTCNT+3: printf("ERROR 8bit SQRTCNT3 READ\n"); return 0;
-#if 1
- case REG_DIVCNT: printf("ERROR 8bit DIVCNT READ\n"); return 0;
- case REG_DIVCNT+1: printf("ERROR 8bit DIVCNT1 READ\n"); return 0;
-#else
- case REG_DIVCNT: return MMU_new.div.read16() & 0xFF;
- case REG_DIVCNT+1: return (MMU_new.div.read16()>>8) & 0xFF;
-#endif
- case REG_DIVCNT+2: printf("ERROR 8bit DIVCNT2 READ\n"); return 0;
- case REG_DIVCNT+3: printf("ERROR 8bit DIVCNT3 READ\n"); return 0;
-
- //fog table: write only
- /*case eng_3D_FOG_TABLE+0x00: case eng_3D_FOG_TABLE+0x01: case eng_3D_FOG_TABLE+0x02: case eng_3D_FOG_TABLE+0x03:
- case eng_3D_FOG_TABLE+0x04: case eng_3D_FOG_TABLE+0x05: case eng_3D_FOG_TABLE+0x06: case eng_3D_FOG_TABLE+0x07:
- case eng_3D_FOG_TABLE+0x08: case eng_3D_FOG_TABLE+0x09: case eng_3D_FOG_TABLE+0x0A: case eng_3D_FOG_TABLE+0x0B:
- case eng_3D_FOG_TABLE+0x0C: case eng_3D_FOG_TABLE+0x0D: case eng_3D_FOG_TABLE+0x0E: case eng_3D_FOG_TABLE+0x0F:
- case eng_3D_FOG_TABLE+0x10: case eng_3D_FOG_TABLE+0x11: case eng_3D_FOG_TABLE+0x12: case eng_3D_FOG_TABLE+0x13:
- case eng_3D_FOG_TABLE+0x14: case eng_3D_FOG_TABLE+0x15: case eng_3D_FOG_TABLE+0x16: case eng_3D_FOG_TABLE+0x17:
- case eng_3D_FOG_TABLE+0x18: case eng_3D_FOG_TABLE+0x19: case eng_3D_FOG_TABLE+0x1A: case eng_3D_FOG_TABLE+0x1B:
- case eng_3D_FOG_TABLE+0x1C: case eng_3D_FOG_TABLE+0x1D: case eng_3D_FOG_TABLE+0x1E: case eng_3D_FOG_TABLE+0x1F:
- return 0;*/
-
- /*case REG_POWCNT1:
- case REG_POWCNT1+1:
- case REG_POWCNT1+2:
- case REG_POWCNT1+3:
- return readreg_POWCNT1(8,adr);*/
-
- /*case eng_3D_GXSTAT:
- return MMU_new.gxstat.read(8,adr);*/
-
- //case REG_DISPA_DISP3DCNT: return readreg_DISP3DCNT(8,adr);
- //case REG_DISPA_DISP3DCNT+1: return readreg_DISP3DCNT(8,adr);
- //case REG_DISPA_DISP3DCNT+2: return readreg_DISP3DCNT(8,adr);
- //case REG_DISPA_DISP3DCNT+3: return readreg_DISP3DCNT(8,adr);
+ if (adr<0x02000000)
+ return T1ReadByte(MMU.ARM9_ITCM, adr & 0x7FFF);
+
+ if (adr >= 0x08000000 && adr < 0x0A010000)
+ return 0;
+
+ if ((adr >> 24) == 4)
+ {
+ //Address is an IO register
+
+ if (MMU_new.is_dma(adr))
+ return static_cast<uint8_t>(MMU_new.read_dma(ARMCPU_ARM9, 8, adr));
+
+ switch (adr)
+ {
+ case REG_IF:
+ return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM9>());
+ case REG_IF + 1:
+ return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM9>() >> 8);
+ case REG_IF + 2:
+ return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM9>() >> 16);
+ case REG_IF + 3:
+ return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM9>() >> 24);
+
+ case REG_WRAMCNT:
+ return MMU.WRAMCNT;
+
+ case REG_SQRTCNT:
+ return MMU_new.sqrt.read16() & 0xFF;
+ case REG_SQRTCNT + 1:
+ return (MMU_new.sqrt.read16() >> 8) & 0xFF;
+
+ // sqrtcnt isnt big enough for these to exist. but they'd probably return 0 so its ok
+ case REG_SQRTCNT + 2:
+ printf("ERROR 8bit SQRTCNT+2 READ\n");
+ return 0;
+ case REG_SQRTCNT + 3:
+ printf("ERROR 8bit SQRTCNT+3 READ\n");
+ return 0;
+
+ // Nostalgia's options menu requires that these work
+ case REG_DIVCNT:
+ return MMU_new.div.read16() & 0xFF;
+ case REG_DIVCNT + 1:
+ return (MMU_new.div.read16() >> 8) & 0xFF;
+
+ // divcnt isnt big enough for these to exist. but they'd probably return 0 so its ok
+ case REG_DIVCNT + 2:
+ printf("ERROR 8bit DIVCNT+2 READ\n");
+ return 0;
+ case REG_DIVCNT + 3:
+ printf("ERROR 8bit DIVCNT+3 READ\n");
+ return 0;
}
}
bool unmapped, restricted;
- adr = MMU_LCDmap/*<ARMCPU_ARM9>*/(adr, unmapped, restricted);
- if(unmapped) return 0;
-
- return MMU.MMU_MEM[ARMCPU_ARM9][(adr>>20)&0xFF][adr&MMU.MMU_MASK[ARMCPU_ARM9][(adr>>20)&0xFF]];
-}
-
-//================================================= MMU ARM9 read 16
+ adr = MMU_LCDmap<ARMCPU_ARM9>(adr, unmapped, restricted);
+ if (unmapped)
+ return 0;
+
+ return MMU.MMU_MEM[ARMCPU_ARM9][(adr >> 20) & 0xFF][adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20) & 0xFF]];
+}
+
+// ================================================= MMU ARM9 read 16
uint16_t FASTCALL _MMU_ARM9_read16(uint32_t adr)
{
adr &= 0x0FFFFFFE;
- //mmu_log_debug_ARM9(adr, "(read16) 0x%04X", T1ReadWord_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr >> 20]));
-
- if(adr<0x02000000)
+ if (adr < 0x02000000)
return T1ReadWord_guaranteedAligned(MMU.ARM9_ITCM, adr & 0x7FFE);
- if ( (adr >= 0x08000000) && (adr < 0x0A010000) )
- return 0/*addon.read16(adr)*/;
-
- if (adr >> 24 == 4)
- {
- if(MMU_new.is_dma(adr)) return static_cast<uint16_t>(MMU_new.read_dma(ARMCPU_ARM9,16,adr));
+ if (adr >= 0x08000000 && adr < 0x0A010000)
+ return 0;
+
+ if ((adr >> 24) == 4)
+ {
+ if (MMU_new.is_dma(adr))
+ return static_cast<uint16_t>(MMU_new.read_dma(ARMCPU_ARM9, 16, adr));
// Address is an IO register
- switch(adr)
- {
- /*case REG_DISPA_DISPSTAT:
- break;*/
-
- case REG_SQRTCNT: return MMU_new.sqrt.read16();
- case REG_DIVCNT: return MMU_new.div.read16();
- //case eng_3D_GXSTAT: return MMU_new.gxstat.read(16,adr);
-
- /*case REG_DISPA_VCOUNT:
- if(nds.ensataEmulation && nds.ensataHandshake == ENSATA_HANDSHAKE_query)
- {
- nds.ensataHandshake = ENSATA_HANDSHAKE_ack;
- return 270;
- } else return nds.VCount;
-
- // ============================================= 3D
- case eng_3D_RAM_COUNT:
+ switch (adr)
+ {
+ case REG_SQRTCNT:
+ return MMU_new.sqrt.read16();
+ // sqrtcnt isnt big enough for this to exist. but it'd probably return 0 so its ok
+ case REG_SQRTCNT + 2:
+ printf("ERROR 16bit SQRTCNT+2 READ\n");
return 0;
- //almost worthless for now
- //return gfx3d_GetNumPolys();
- case eng_3D_RAM_COUNT+2:
+
+ case REG_DIVCNT:
+ return MMU_new.div.read16();
+ // divcnt isnt big enough for this to exist. but it'd probably return 0 so its ok
+ case REG_DIVCNT + 2:
+ printf("ERROR 16bit DIVCNT+2 READ\n");
return 0;
- //almost worthless for now
- //return gfx3d_GetNumVertex();*/
- // ============================================= 3D end
- case REG_IME :
- return (uint16_t)MMU.reg_IME[ARMCPU_ARM9];
-
- case REG_IE :
- return (uint16_t)MMU.reg_IE[ARMCPU_ARM9];
- case REG_IE + 2 :
- return (uint16_t)(MMU.reg_IE[ARMCPU_ARM9]>>16);
-
- case REG_IF: return static_cast<uint16_t>(MMU.gen_IF<ARMCPU_ARM9>());
- case REG_IF+2: return static_cast<uint16_t>(MMU.gen_IF<ARMCPU_ARM9>()>>16);
-
- case REG_TM0CNTL :
- case REG_TM1CNTL :
- case REG_TM2CNTL :
- case REG_TM3CNTL :
- return read_timer(ARMCPU_ARM9,(adr&0xF)>>2);
+
+ case REG_IME:
+ return static_cast<uint16_t>(MMU.reg_IME[ARMCPU_ARM9]);
+
+ // WRAMCNT is readable but VRAMCNT is not, so just return WRAM's value
+ case REG_VRAMCNTG:
+ return MMU.WRAMCNT << 8;
+
+ case REG_IE:
+ return static_cast<uint16_t>(MMU.reg_IE[ARMCPU_ARM9]);
+ case REG_IE + 2:
+ return static_cast<uint16_t>(MMU.reg_IE[ARMCPU_ARM9] >> 16);
+
+ case REG_IF:
+ return static_cast<uint16_t>(MMU.gen_IF<ARMCPU_ARM9>());
+ case REG_IF + 2:
+ return static_cast<uint16_t>(MMU.gen_IF<ARMCPU_ARM9>() >> 16);
+
+ case REG_TM0CNTL:
+ case REG_TM1CNTL:
+ case REG_TM2CNTL:
+ case REG_TM3CNTL:
+ return read_timer(ARMCPU_ARM9, (adr & 0xF) >> 2);
case REG_AUXSPICNT:
return MMU.AUX_SPI_CNT;
-
- /*case REG_POWCNT1:
- case REG_POWCNT1+2:
- return readreg_POWCNT1(16,adr);*/
-
- //case REG_DISPA_DISP3DCNT: return readreg_DISP3DCNT(16,adr);
- //case REG_DISPA_DISP3DCNT+2: return readreg_DISP3DCNT(16,adr);
-
- /*case 0x04000130:
- case 0x04000136:
- //not sure whether these should trigger from byte reads
- LagFrameFlag=0;
- break;*/
-
- //fog table: write only
- /*case eng_3D_FOG_TABLE+0x00: case eng_3D_FOG_TABLE+0x02: case eng_3D_FOG_TABLE+0x04: case eng_3D_FOG_TABLE+0x06:
- case eng_3D_FOG_TABLE+0x08: case eng_3D_FOG_TABLE+0x0A: case eng_3D_FOG_TABLE+0x0C: case eng_3D_FOG_TABLE+0x0E:
- case eng_3D_FOG_TABLE+0x10: case eng_3D_FOG_TABLE+0x12: case eng_3D_FOG_TABLE+0x14: case eng_3D_FOG_TABLE+0x16:
- case eng_3D_FOG_TABLE+0x18: case eng_3D_FOG_TABLE+0x1A: case eng_3D_FOG_TABLE+0x1C: case eng_3D_FOG_TABLE+0x1E:
- return 0;*/
- }
-
- return T1ReadWord_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][adr>>20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr>>20]);
- }
-
- //bool unmapped = false/*, restricted*/;
- //adr = MMU_LCDmap<ARMCPU_ARM9>(adr,unmapped, restricted);
- //if(unmapped) return 0;
+ }
+
+ return T1ReadWord_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr >> 20]);
+ }
// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF
return T1ReadWord_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr >> 20]);
}
-//================================================= MMU ARM9 read 32
+// ================================================= MMU ARM9 read 32
uint32_t FASTCALL _MMU_ARM9_read32(uint32_t adr)
{
adr &= 0x0FFFFFFC;
- //mmu_log_debug_ARM9(adr, "(read32) 0x%08X", T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr>>20]));
-
- if(adr<0x02000000)
- return T1ReadLong_guaranteedAligned(MMU.ARM9_ITCM, adr&0x7FFC);
-
- if ( (adr >= 0x08000000) && (adr < 0x0A010000) )
- return 0/*addon.read32(adr)*/;
+ if (adr < 0x02000000)
+ return T1ReadLong_guaranteedAligned(MMU.ARM9_ITCM, adr & 0x7FFC);
+
+ if (adr >= 0x08000000 && adr < 0x0A010000)
+ return 0;
// Address is an IO register
- if((adr >> 24) == 4)
- {
- if(MMU_new.is_dma(adr)) return MMU_new.read_dma(ARMCPU_ARM9,32,adr);
-
- switch(adr)
+ if ((adr >> 24) == 4)
+ {
+ if (MMU_new.is_dma(adr))
+ return MMU_new.read_dma(ARMCPU_ARM9, 32, adr);
+
+ switch (adr)
{
case REG_DSIMODE:
- if(!nds.Is_DSI()) break;
+ if (!nds.Is_DSI())
+ break;
return 1;
case 0x04004008:
- if(!nds.Is_DSI()) break;
+ if (!nds.Is_DSI())
+ break;
return 0x8000;
- /*case REG_DISPA_DISPSTAT:
- break;
-
- case REG_DISPx_VCOUNT: return nds.VCount;*/
-
- //Dolphin Island Underwater Adventures uses this amidst seemingly reasonable divs so we're going to emulate it.
- case REG_DIVCNT: return MMU_new.div.read16();
- //I guess we'll do this also
- case REG_SQRTCNT: return MMU_new.sqrt.read16();
-
- //fog table: write only
- /*case eng_3D_FOG_TABLE+0x00: case eng_3D_FOG_TABLE+0x04: case eng_3D_FOG_TABLE+0x08: case eng_3D_FOG_TABLE+0x0C:
- case eng_3D_FOG_TABLE+0x10: case eng_3D_FOG_TABLE+0x14: case eng_3D_FOG_TABLE+0x18: case eng_3D_FOG_TABLE+0x1C:
- return 0;*/
-
- /*case eng_3D_CLIPMTX_RESULT:
- case eng_3D_CLIPMTX_RESULT+4:
- case eng_3D_CLIPMTX_RESULT+8:
- case eng_3D_CLIPMTX_RESULT+12:
- case eng_3D_CLIPMTX_RESULT+16:
- case eng_3D_CLIPMTX_RESULT+20:
- case eng_3D_CLIPMTX_RESULT+24:
- case eng_3D_CLIPMTX_RESULT+28:
- case eng_3D_CLIPMTX_RESULT+32:
- case eng_3D_CLIPMTX_RESULT+36:
- case eng_3D_CLIPMTX_RESULT+40:
- case eng_3D_CLIPMTX_RESULT+44:
- case eng_3D_CLIPMTX_RESULT+48:
- case eng_3D_CLIPMTX_RESULT+52:
- case eng_3D_CLIPMTX_RESULT+56:
- case eng_3D_CLIPMTX_RESULT+60:
+ // WRAMCNT is readable but VRAMCNT is not, so just return WRAM's value
+ case REG_VRAMCNTE:
+ return MMU.WRAMCNT << 24;
+
+ // despite these being 16bit regs,
+ // Dolphin Island Underwater Adventures uses this amidst seemingly reasonable divs so we're going to emulate it.
+ // well, it's pretty reasonable to read them as 32bits though, isnt it?
+ case REG_DIVCNT:
+ return MMU_new.div.read16();
+ case REG_SQRTCNT:
+ return MMU_new.sqrt.read16(); // I guess we'll do this also
+
+ case REG_IME:
+ return MMU.reg_IME[ARMCPU_ARM9];
+ case REG_IE:
+ return MMU.reg_IE[ARMCPU_ARM9];
+
+ case REG_IF:
+ return MMU.gen_IF<ARMCPU_ARM9>();
+
+ case REG_IPCFIFORECV:
+ return IPC_FIFOrecv(ARMCPU_ARM9);
+ case REG_TM0CNTL:
+ case REG_TM1CNTL:
+ case REG_TM2CNTL:
+ case REG_TM3CNTL:
{
- //LOG("4000640h..67Fh - CLIPMTX_RESULT - Read Current Clip Coordinates Matrix (R)");
- return gfx3d_GetClipMatrix ((adr-0x04000640)/4);
- }*/
- /*case eng_3D_VECMTX_RESULT:
- case eng_3D_VECMTX_RESULT+4:
- case eng_3D_VECMTX_RESULT+8:
- case eng_3D_VECMTX_RESULT+12:
- case eng_3D_VECMTX_RESULT+16:
- case eng_3D_VECMTX_RESULT+20:
- case eng_3D_VECMTX_RESULT+24:
- case eng_3D_VECMTX_RESULT+28:
- case eng_3D_VECMTX_RESULT+32:
- {
- //LOG("4000680h..6A3h - VECMTX_RESULT - Read Current Directional Vector Matrix (R)");
- return gfx3d_GetDirectionalMatrix ((adr-0x04000680)/4);
- }*/
-
- /*case eng_3D_RAM_COUNT:
- {
- return gfx3d_GetNumPolys() | ((gfx3d_GetNumVertex()) << 16);
- //LOG ("read32 - RAM_COUNT -> 0x%X", ((uint32_t *)(MMU.MMU_MEM[ARMCPU_ARM9][(adr>>20)&0xFF]))[(adr&MMU.MMU_MASK[ARMCPU_ARM9][(adr>>20)&0xFF])>>2]);
- }*/
-
- /*case eng_3D_POS_RESULT:
- case eng_3D_POS_RESULT+4:
- case eng_3D_POS_RESULT+8:
- case eng_3D_POS_RESULT+12:
- {
- return gfx3d_glGetPosRes((adr & 0xF) >> 2);
- }*/
- /*case eng_3D_GXSTAT:
- return MMU_new.gxstat.read(32,adr);*/
- // ======================================== 3D end
-
-
- case REG_IME :
- return MMU.reg_IME[ARMCPU_ARM9];
- case REG_IE :
- return MMU.reg_IE[ARMCPU_ARM9];
-
- case REG_IF: return MMU.gen_IF<ARMCPU_ARM9>();
-
- case REG_IPCFIFORECV :
- return IPC_FIFOrecv(ARMCPU_ARM9);
- case REG_TM0CNTL :
- case REG_TM1CNTL :
- case REG_TM2CNTL :
- case REG_TM3CNTL :
- {
- uint32_t val = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], (adr + 2) & 0xFFF);
- return MMU.timer[ARMCPU_ARM9][(adr&0xF)>>2] | (val<<16);
- }
-
- case REG_GCDATAIN: return MMU_readFromGC<ARMCPU_ARM9>();
- //case REG_POWCNT1: return readreg_POWCNT1(32,adr);
- //case REG_DISPA_DISP3DCNT: return readreg_DISP3DCNT(32,adr);
- }
- return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][adr>>20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr>>20]);
- }
-
- //bool unmapped = false/*, restricted*/;
- //adr = MMU_LCDmap<ARMCPU_ARM9>(adr,unmapped, restricted);
- //if(unmapped) return 0;
+ uint32_t val = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], (adr + 2) & 0xFFF);
+ return MMU.timer[ARMCPU_ARM9][(adr & 0xF) >> 2] | (val << 16);
+ }
+
+ case REG_GCDATAIN:
+ return MMU_readFromGC<ARMCPU_ARM9>();
+ }
+ return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr >> 20]);
+ }
// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF [zeromus, inspired by shash]
- return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr>>20]);
-}
-//================================================================================================== ARM7 *
-//=========================================================================================================
-//=========================================================================================================
-//================================================= MMU ARM7 write 08
+ return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr >> 20]);
+}
+
+// ================================================================================================== ARM7 *
+// =========================================================================================================
+// =========================================================================================================
+// ================================================= MMU ARM7 write 08
void FASTCALL _MMU_ARM7_write08(uint32_t adr, uint8_t val)
{
adr &= 0x0FFFFFFF;
- //mmu_log_debug_ARM7(adr, "(write08) 0x%02X", val);
-
- if (adr < 0x4000) return; // PU BIOS
-
- if ( (adr >= 0x08000000) && (adr < 0x0A010000) )
- {
- //addon.write08(adr, val);
- return;
- }
-
- if ((adr>=0x04000400)&&(adr<0x04000520))
+ if (adr < 0x02000000)
+ return; // can't write to bios or entire area below main memory
+
+ if (adr >= 0x08000000 && adr < 0x0A010000)
+ return;
+
+ if (adr >= 0x04000400 && adr < 0x04000520)
{
SPU_WriteByte(adr, val);
return;
- }
+ }
if ((adr & 0xFFFF0000) == 0x04800000)
- {
/* is wifi hardware, dont intermix with regular hardware registers */
// 8-bit writes to wifi I/O and RAM are ignored
// Reference: http://nocash.emubase.de/gbatek.htm#dswifiiomap
return;
- }
-
- if (adr >> 24 == 4)
- {
- if(MMU_new.is_dma(adr)) { MMU_new.write_dma(ARMCPU_ARM7,8,adr,val); return; }
-
- switch(adr)
- {
- case REG_IF: REG_IF_WriteByte<ARMCPU_ARM7>(0,val); break;
- case REG_IF+1: REG_IF_WriteByte<ARMCPU_ARM7>(1,val); break;
- case REG_IF+2: REG_IF_WriteByte<ARMCPU_ARM7>(2,val); break;
- case REG_IF+3: REG_IF_WriteByte<ARMCPU_ARM7>(3,val); break;
+
+ if ((adr >> 24) == 4)
+ {
+ if (MMU_new.is_dma(adr))
+ {
+ MMU_new.write_dma(ARMCPU_ARM7, 8, adr, val);
+ return;
+ }
+
+ switch (adr)
+ {
+ case REG_IF:
+ REG_IF_WriteByte<ARMCPU_ARM7>(0, val);
+ break;
+ case REG_IF + 1:
+ REG_IF_WriteByte<ARMCPU_ARM7>(1, val);
+ break;
+ case REG_IF + 2:
+ REG_IF_WriteByte<ARMCPU_ARM7>(2, val);
+ break;
+ case REG_IF + 3:
+ REG_IF_WriteByte<ARMCPU_ARM7>(3, val);
+ break;
case REG_POSTFLG:
+ // The NDS7 register can be written to only from code executed in BIOS.
+ if (NDS_ARM7.instruct_adr > 0x3FFF)
+ return;
+
// hack for patched firmwares
if (val == 1)
{
- if (_MMU_ARM7_read08(REG_POSTFLG) != 0)
+ if (_MMU_ARM7_read08(REG_POSTFLG))
break;
_MMU_write32<ARMCPU_ARM9>(0x27FFE24, gameInfo.header.ARM9exe);
_MMU_write32<ARMCPU_ARM7>(0x27FFE34, gameInfo.header.ARM7exe);
@@ -3679,77 +2256,56 @@
case REG_HALTCNT:
//printf("halt 0x%02X\n", val);
- switch(val)
+ switch (val)
{
- case 0xC0: NDS_Sleep(); break;
- case 0x80: armcpu_Wait4IRQ(&NDS_ARM7); break;
- default: break;
+ case 0xC0:
+ NDS_Sleep();
+ break;
+ case 0x80:
+ armcpu_Wait4IRQ(&NDS_ARM7);
}
break;
-
- /*case REG_RTC:
- rtcWrite(val);
- return;*/
-
- /*case REG_AUXSPICNT:
- write_auxspicnt(9,8,0,val);
- return;
- case REG_AUXSPICNT+1:
- write_auxspicnt(9,8,1,val);
- return;
- case REG_AUXSPIDATA:
- if(val!=0) MMU.AUX_SPI_CMD = val & 0xFF;
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_AUXSPIDATA >> 20) & 0xff], REG_AUXSPIDATA & 0xfff, MMU_new.backupDevice.data_command((uint8_t)val,ARMCPU_ARM7));
- MMU.AUX_SPI_CNT &= ~0x80; //remove busy flag
- return;*/
- }
- MMU.MMU_MEM[ARMCPU_ARM7][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20]]=val;
- return;
- }
-
- //bool unmapped = false/*, restricted*/;
- //adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped, restricted);
- //if(unmapped) return;
+ }
+ MMU.MMU_MEM[ARMCPU_ARM7][adr >> 20][adr & MMU.MMU_MASK[ARMCPU_ARM7][adr >> 20]] = val;
+ return;
+ }
+
+#ifdef HAVE_JIT
+ if (JIT_MAPPED(adr, ARMCPU_ARM7))
+ JIT_COMPILED_FUNC_PREMASKED(adr, ARMCPU_ARM7, 0) = 0;
+#endif
// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF [shash]
- MMU.MMU_MEM[ARMCPU_ARM7][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20]]=val;
-}
-
-//================================================= MMU ARM7 write 16
+ MMU.MMU_MEM[ARMCPU_ARM7][adr >> 20][adr & MMU.MMU_MASK[ARMCPU_ARM7][adr >> 20]] = val;
+}
+
+// ================================================= MMU ARM7 write 16
void FASTCALL _MMU_ARM7_write16(uint32_t adr, uint16_t val)
{
adr &= 0x0FFFFFFE;
- //mmu_log_debug_ARM7(adr, "(write16) 0x%04X", val);
-
- if (adr < 0x4000) return; // PU BIOS
-
- if ( (adr >= 0x08000000) && (adr < 0x0A010000) )
- {
- //addon.write16(adr, val);
- return;
- }
-
- //wifi mac access
- /*if ((adr & 0xFFFF0000) == 0x04800000)
- {
- WIFI_write16(adr,val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x48], adr&MMU.MMU_MASK[ARMCPU_ARM7][0x48], val);
- return;
- }*/
-
- if ((adr>=0x04000400)&&(adr<0x04000520))
+ if (adr < 0x02000000)
+ return; // can't write to bios or entire area below main memory
+
+ if (adr >= 0x08000000 && adr < 0x0A010000)
+ return;
+
+ if (adr >= 0x04000400 && adr < 0x04000520)
{
SPU_WriteWord(adr, val);
return;
}
- if((adr >> 24) == 4)
- {
- if(MMU_new.is_dma(adr)) { MMU_new.write_dma(ARMCPU_ARM7,16,adr,val); return; }
-
- //Address is an IO register
- switch(adr)
+ if ((adr >> 24) == 4)
+ {
+ if (MMU_new.is_dma(adr))
+ {
+ MMU_new.write_dma(ARMCPU_ARM7, 16, adr, val);
+ return;
+ }
+
+ // Address is an IO register
+ switch (adr)
{
case REG_DISPA_VCOUNT:
if (nds.VCount >= 202 && nds.VCount <= 212)
@@ -3761,416 +2317,320 @@
printf("Attempt to set VCOUNT while not within 202-212 (%i), ignored\n", nds.VCount);
return;
- /*case REG_RTC:
- rtcWrite(val);
- break;*/
-
case REG_EXMEMCNT:
{
uint16_t remote_proc = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x204);
T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x204, (val & 0x7F) | (remote_proc & 0xFF80));
+ return;
}
- return;
-
- /*case REG_EXTKEYIN: //readonly
- return;*/
-
-
- /*case REG_POWCNT2:
+
+ case REG_SPICNT:
+ {
+ bool reset_firmware = true;
+
+ if (((MMU.SPI_CNT >> 8) & 0x3) == 1 && ((val >> 8) & 0x3) == 1 && BIT11(MMU.SPI_CNT))
+ // select held
+ reset_firmware = false;
+
+ //MMU.fw.com == 0; // reset fw device communication
+ if (reset_firmware)
+ // reset fw device communication
+ fw_reset_com(&MMU.fw);
+ MMU.SPI_CNT = val;
+
+ T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_SPICNT >> 20) & 0xff], REG_SPICNT & 0xfff, val);
+ return;
+ }
+
+ case REG_SPIDATA:
+ {
+ if (val)
+ MMU.SPI_CMD = val;
+
+ uint16_t spicnt = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_SPICNT >> 20) & 0xff], REG_SPICNT & 0xfff);
+
+ switch ((spicnt >> 8) & 0x3)
{
- nds.power2.speakers = BIT0(val);
- nds.power2.wifi = BIT0(val);
- }
- return;*/
-
-
- /*case REG_AUXSPICNT:
- write_auxspicnt(7,16,0,val);
- return;
-
- case REG_AUXSPIDATA:
- if(val!=0)
- MMU.AUX_SPI_CMD = val & 0xFF;
-
- //T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_AUXSPIDATA >> 20) & 0xff], REG_AUXSPIDATA & 0xfff, bm_transfer(&MMU.bupmem, val));
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_AUXSPIDATA >> 20) & 0xff], REG_AUXSPIDATA & 0xfff, MMU_new.backupDevice.data_command((uint8_t)val,ARMCPU_ARM7));
- MMU.AUX_SPI_CNT &= ~0x80; //remove busy flag
- return;*/
-
- case REG_SPICNT :
- {
- int reset_firmware = 1;
-
- if ( ((MMU.SPI_CNT >> 8) & 0x3) == 1)
+ case 0:
{
- if ( ((val >> 8) & 0x3) == 1)
+ if (!MMU.powerMan_CntRegWritten)
{
- if ( BIT11(MMU.SPI_CNT))
+ MMU.powerMan_CntReg = val & 0xFF;
+ MMU.powerMan_CntRegWritten = true;
+ }
+ else
+ {
+ uint16_t reg = MMU.powerMan_CntReg & 0x7F;
+ reg &= 0x7;
+ if (reg == 5 || reg == 6 || reg == 7)
+ reg = 4;
+
+ // (let's start with emulating a DS lite, since it is the more complex case)
+ if (MMU.powerMan_CntReg & 0x80)
+ // read
+ val = MMU.powerMan_Reg[reg];
+ else
{
- // select held
- reset_firmware = 0;
+ // write
+ MMU.powerMan_Reg[reg] = static_cast<uint8_t>(val);
+
+ static const uint32_t PM_SYSTEM_PWR = BIT(6); /*!< \brief Turn the power *off* if set */
+
+ // our totally pathetic register handling, only the one thing we've wanted so far
+ if (MMU.powerMan_Reg[0] & PM_SYSTEM_PWR)
+ {
+ printf("SYSTEM POWERED OFF VIA ARM7 SPI POWER DEVICE\n");
+ execute = false;
+ }
}
+
+ MMU.powerMan_CntRegWritten = false;
+ }
+ break;
+ }
+
+ case 1: /* firmware memory device */
+ if (spicnt & 0x3) /* check SPI baudrate (must be 4mhz) */
+ {
+ T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_SPIDATA >> 20) & 0xff], REG_SPIDATA & 0xfff, 0);
+ break;
+ }
+ T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_SPIDATA >> 20) & 0xff], REG_SPIDATA & 0xfff, fw_transfer(&MMU.fw, static_cast<uint8_t>(val)));
+ return;
+
+ case 2:
+ {
+ if (nds.Is_DSI())
+ {
+ // pass data to TSC
+ val = MMU_new.dsi_tsc.write16(val);
+
+ // apply reset command if appropriate
+ if (!BIT11(MMU.SPI_CNT))
+ MMU_new.dsi_tsc.reset_command();
+
+ break;
+ }
+
+ int channel = (MMU.SPI_CMD & 0x70) >> 4;
+ //printf("%08X\n",channel);
+ switch (channel)
+ {
+ case TSC_MEASURE_TEMP1:
+ if (spicnt & 0x800)
+ {
+ if (partie)
+ {
+ val = 1632;
+ partie = 0;
+ break;
+ }
+ val = 716 >> 5;
+ partie = 1;
+ break;
+ }
+ val = 1632;
+ partie = 1;
+ break;
+ case TSC_MEASURE_TEMP2:
+ if(spicnt & 0x800)
+ {
+ if(partie)
+ {
+ val = 776;
+ partie = 0;
+ break;
+ }
+ val = 865 >> 5;
+ partie = 1;
+ break;
+ }
+ val = 776;
+ partie = 1;
+ break;
+ case TSC_MEASURE_Y:
+ if (MMU.SPI_CNT & (1 << 11))
+ {
+ if (partie)
+ {
+ partie = 0;
+ break;
+ }
+ partie = 1;
+ break;
+ }
+ partie = 1;
+ break;
+ case TSC_MEASURE_Z1: // Z1
+ if (spicnt & 0x800)
+ {
+ if (partie)
+ {
+ val = (val << 3) & 0x7FF;
+ partie = 0;
+ break;
+ }
+ val >>= 5;
+ partie = 1;
+ break;
+ }
+ val = (val << 3) & 0x7FF;
+ partie = 1;
+ break;
+ case TSC_MEASURE_Z2: // Z2
+ if (spicnt & 0x800)
+ {
+ if (partie)
+ {
+ val = (val << 3) & 0x7FF;
+ partie = 0;
+ break;
+ }
+ val >>= 5;
+ partie = 1;
+ break;
+ }
+ val = (val << 3) & 0x7FF;
+ partie = 1;
+ break;
+ case TSC_MEASURE_X:
+ if (spicnt & 0x800)
+ {
+ if (partie)
+ {
+ partie = 0;
+ break;
+ }
+ partie = 1;
+ break;
+ }
+ partie = 1;
}
}
-
- //MMU.fw.com == 0; // reset fw device communication
- if ( reset_firmware)
- {
- // reset fw device communication
- fw_reset_com(&MMU.fw);
- }
- MMU.SPI_CNT = val;
-
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_SPICNT >> 20) & 0xff], REG_SPICNT & 0xfff, val);
}
- return;
-
- case REG_SPIDATA :
- {
- uint16_t spicnt;
-
- if(val!=0)
- MMU.SPI_CMD = val;
-
- spicnt = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_SPICNT >> 20) & 0xff], REG_SPICNT & 0xfff);
-
- switch((spicnt >> 8) & 0x3)
- {
- case 0 :
- {
- if(!MMU.powerMan_CntRegWritten)
- {
- MMU.powerMan_CntReg = (val & 0xFF);
- MMU.powerMan_CntRegWritten = true;
- }
- else
- {
- uint16_t reg = MMU.powerMan_CntReg&0x7F;
- reg &= 0x7;
- if(reg==5 || reg==6 || reg==7) reg = 4;
-
- //(let's start with emulating a DS lite, since it is the more complex case)
- if(MMU.powerMan_CntReg & 0x80)
- {
- //read
- val = MMU.powerMan_Reg[reg];
- }
- else
- {
- //write
- MMU.powerMan_Reg[reg] = (uint8_t)val;
-
- //enum PM_Bits //from libnds
- //{
- //PM_SOUND_AMP = BIT(0) , /*!< \brief Power the sound hardware (needed to hear stuff in GBA mode too) */
- //PM_SOUND_MUTE = BIT(1), /*!< \brief Mute the main speakers, headphone output will still work. */
- //PM_BACKLIGHT_BOTTOM = BIT(2), /*!< \brief Enable the top backlight if set */
- //PM_BACKLIGHT_TOP = BIT(3) , /*!< \brief Enable the bottom backlight if set */
- static const uint32_t PM_SYSTEM_PWR = BIT(6); /*!< \brief Turn the power *off* if set */
- //};
-
- //our totally pathetic register handling, only the one thing we've wanted so far
- if(MMU.powerMan_Reg[0]&PM_SYSTEM_PWR) {
- printf("SYSTEM POWERED OFF VIA ARM7 SPI POWER DEVICE\n");
- //emu_halt();
- execute = false;
- }
- }
-
- MMU.powerMan_CntRegWritten = false;
- }
- }
- break;
-
- case 1 : /* firmware memory device */
- if((spicnt & 0x3) != 0) /* check SPI baudrate (must be 4mhz) */
- {
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_SPIDATA >> 20) & 0xff], REG_SPIDATA & 0xfff, 0);
- break;
- }
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_SPIDATA >> 20) & 0xff], REG_SPIDATA & 0xfff, fw_transfer(&MMU.fw, (uint8_t)val));
- return;
-
- case 2:
- {
- if(nds.Is_DSI())
- {
- //pass data to TSC
- val = MMU_new.dsi_tsc.write16(val);
-
- //apply reset command if appropriate
- if(!BIT11(MMU.SPI_CNT))
- MMU_new.dsi_tsc.reset_command();
-
- break;
- }
-
- int channel = (MMU.SPI_CMD&0x70)>>4;
- //printf("%08X\n",channel);
- switch(channel)
- {
- case TSC_MEASURE_TEMP1:
- if(spicnt & 0x800)
- {
- if(partie)
- {
- val = ((716<<3)&0x7FF);
- partie = 0;
- break;
- }
- val = (716>>5);
- partie = 1;
- break;
- }
- val = ((716<<3)&0x7FF);
- partie = 1;
- break;
- case TSC_MEASURE_TEMP2:
- if(spicnt & 0x800)
- {
- if(partie)
- {
- val = ((865<<3)&0x7FF);
- partie = 0;
- break;
- }
- val = (865>>5);
- partie = 1;
- break;
- }
- val = ((865<<3)&0x7FF);
- partie = 1;
- break;
-
- case TSC_MEASURE_Y:
- {
- //counter the number of adc touch coord reads and jitter it after a while to simulate a shaky human hand or multiple reads
- /*nds.adc_jitterctr++;
- if(nds.adc_jitterctr == 25)
- {
- nds.adc_jitterctr = 0;
- nds.adc_touchY ^= 16;
- nds.adc_touchX ^= 16;
- }*/
- if(MMU.SPI_CNT&(1<<11))
- {
- if(partie)
- {
- //val = (nds.adc_touchY<<3) & 0xFF;
- partie = 0;
- break;
- }
-
- //val = (nds.adc_touchY>>5) & 0xFF;
- partie = 1;
- break;
- }
- //val = (nds.adc_touchY<<3)&0xFF;
- partie = 1;
- break;
- }
- case TSC_MEASURE_Z1: //Z1
- //used for pressure calculation - must be nonzero or else some softwares will think the stylus is up.
- //something is wrong in here and some of these LSB dont make it back to libnds... whatever.
- /*{
- u16 scratch;
- CalculateTouchPressure(CommonSettings.StylusPressure,val,scratch);
- }*/
- if(spicnt & 0x800)
- {
- if(partie)
- {
- val = ((val<<3)&0x7FF);
- partie = 0;
- break;
- }
- val = (val>>5);
- partie = 1;
- break;
- }
- val = ((val<<3)&0x7FF);
- partie = 1;
- break;
- case TSC_MEASURE_Z2: //Z2
- //used for pressure calculation - must be nonzero or else some softwares will think the stylus is up.
- //something is wrong in here and some of these LSB dont make it back to libnds... whatever.
- /*{
- u16 scratch;
- CalculateTouchPressure(CommonSettings.StylusPressure,scratch,val);
- }*/
- if(spicnt & 0x800)
- {
- if(partie)
- {
- val = ((val<<3)&0x7FF);
- partie = 0;
- break;
- }
- val = (val>>5);
- partie = 1;
- break;
- }
- val = ((val<<3)&0x7FF);
- partie = 1;
- break;
- case TSC_MEASURE_X:
- if(spicnt & 0x800)
- {
- if(partie)
- {
- //val = (nds.adc_touchX << 3) & 0xFF;
- partie = 0;
- break;
- }
- //val = (nds.adc_touchX>>5) & 0xFF;
- partie = 1;
- break;
- }
- //val = (nds.adc_touchX<<3) & 0xFF;
- partie = 1;
- break;
- case TSC_MEASURE_AUX:
- /*if(!(val & 0x80))
- val = (Mic_ReadSample() & 0xFF);
- else*/
- val = 0;
- break;
- }
- break;
- }
-
- case 3 :
- /* NOTICE: Device 3 of SPI is reserved (unused and unusable) */
- break;
- }
- }
T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_SPIDATA >> 20) & 0xff], REG_SPIDATA & 0xfff, val);
return;
-
- /* NOTICE: Perhaps we have to use gbatek-like reg names instead of libnds-like ones ...*/
-
- case REG_IME :
+ }
+
+ /* NOTICE: Perhaps we have to use gbatek-like reg names instead of libnds-like ones ...*/
+
+ case REG_IME:
NDS_Reschedule();
MMU.reg_IME[ARMCPU_ARM7] = val & 0x01;
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x208, val);
return;
- case REG_IE :
+ case REG_IE:
NDS_Reschedule();
- MMU.reg_IE[ARMCPU_ARM7] = (MMU.reg_IE[ARMCPU_ARM7]&0xFFFF0000) | val;
- return;
- case REG_IE + 2 :
+ MMU.reg_IE[ARMCPU_ARM7] = (MMU.reg_IE[ARMCPU_ARM7] & 0xFFFF0000) | val;
+ return;
+ case REG_IE + 2:
NDS_Reschedule();
- //emu_halt();
- MMU.reg_IE[ARMCPU_ARM7] = (MMU.reg_IE[ARMCPU_ARM7]&0xFFFF) | (((uint32_t)val)<<16);
- return;
-
- case REG_IF: REG_IF_WriteWord<ARMCPU_ARM7>(0,val); return;
- case REG_IF+2: REG_IF_WriteWord<ARMCPU_ARM7>(2,val); return;
-
- case REG_IPCSYNC :
+ MMU.reg_IE[ARMCPU_ARM7] = (MMU.reg_IE[ARMCPU_ARM7] & 0xFFFF) | (static_cast<uint32_t>(val) << 16);
+ return;
+
+ case REG_IF:
+ REG_IF_WriteWord<ARMCPU_ARM7>(0, val);
+ return;
+ case REG_IF + 2:
+ REG_IF_WriteWord<ARMCPU_ARM7>(2, val);
+ return;
+
+ case REG_IPCSYNC:
MMU_IPCSync(ARMCPU_ARM7, val);
return;
- case REG_IPCFIFOCNT :
+ case REG_IPCFIFOCNT:
IPC_FIFOcnt(ARMCPU_ARM7, val);
return;
- case REG_TM0CNTL :
- case REG_TM1CNTL :
- case REG_TM2CNTL :
- case REG_TM3CNTL :
- MMU.timerReload[ARMCPU_ARM7][(adr>>2)&3] = val;
- return;
- case REG_TM0CNTH :
- case REG_TM1CNTH :
- case REG_TM2CNTH :
- case REG_TM3CNTH :
+ case REG_TM0CNTL:
+ case REG_TM1CNTL:
+ case REG_TM2CNTL:
+ case REG_TM3CNTL:
+ MMU.timerReload[ARMCPU_ARM7][(adr >> 2) & 3] = val;
+ return;
+ case REG_TM0CNTH:
+ case REG_TM1CNTH:
+ case REG_TM2CNTH:
+ case REG_TM3CNTH:
{
- int timerIndex = ((adr-2)>>2)&0x3;
+ int timerIndex = ((adr - 2) >> 2) & 0x3;
write_timer(ARMCPU_ARM7, timerIndex, val);
return;
}
- case REG_GCROMCTRL :
- MMU_writeToGCControl<ARMCPU_ARM7>( (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x1A4) & 0xFFFF0000) | val);
- return;
- case REG_GCROMCTRL+2 :
- MMU_writeToGCControl<ARMCPU_ARM7>( (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x1A4) & 0xFFFF) | ((uint32_t) val << 16));
- return;
- }
-
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20], val);
- return;
- }
-
- //bool unmapped = false/*, restricted*/;
- //adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped, restricted);
- //if(unmapped) return;
+ case REG_GCROMCTRL:
+ MMU_writeToGCControl<ARMCPU_ARM7>((T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x1A4) & 0xFFFF0000) | val);
+ return;
+ case REG_GCROMCTRL + 2:
+ MMU_writeToGCControl<ARMCPU_ARM7>((T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x1A4) & 0xFFFF) | (static_cast<uint32_t>(val) << 16));
+ return;
+ }
+
+ T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr >> 20], val);
+ return;
+ }
+
+#ifdef HAVE_JIT
+ if (JIT_MAPPED(adr, ARMCPU_ARM7))
+ JIT_COMPILED_FUNC_PREMASKED(adr, ARMCPU_ARM7, 0) = 0;
+#endif
// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF [shash]
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20], val);
-}
-//================================================= MMU ARM7 write 32
+ T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr >> 20], val);
+}
+
+// ================================================= MMU ARM7 write 32
void FASTCALL _MMU_ARM7_write32(uint32_t adr, uint32_t val)
{
adr &= 0x0FFFFFFC;
- //mmu_log_debug_ARM7(adr, "(write32) 0x%08X", val);
-
- if (adr < 0x4000) return; // PU BIOS
-
- if ( (adr >= 0x08000000) && (adr < 0x0A010000) )
- {
- //addon.write32(adr, val);
- return;
- }
-
- /*if ((adr & 0xFFFF0000) == 0x04800000)
- {
- WIFI_write16(adr, val & 0xFFFF);
- WIFI_write16(adr+2, val >> 16);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM7][0x48], adr&MMU.MMU_MASK[ARMCPU_ARM7][0x48], val);
- return;
- }*/
-
- if ((adr>=0x04000400)&&(adr<0x04000520))
- {
- SPU_WriteLong(adr, val);
- return;
- }
-
- if((adr>>24)==4)
- {
- if(MMU_new.is_dma(adr)) { MMU_new.write_dma(ARMCPU_ARM7,32,adr,val); return; }
-
- switch(adr)
- {
- /*case REG_RTC:
- rtcWrite((uint16_t)val);
- break;*/
-
- case REG_IME :
+ if (adr < 0x02000000)
+ return; // can't write to bios or entire area below main memory
+
+ if (adr >= 0x08000000 && adr < 0x0A010000)
+ return;
+
+ if (adr >= 0x04000400 && adr < 0x04000520)
+ {
+ SPU_WriteLong(adr, val);
+ return;
+ }
+
+ if ((adr >> 24) == 4)
+ {
+ if (MMU_new.is_dma(adr))
+ {
+ MMU_new.write_dma(ARMCPU_ARM7, 32, adr, val);
+ return;
+ }
+
+ switch (adr)
+ {
+ case REG_IME:
NDS_Reschedule();
MMU.reg_IME[ARMCPU_ARM7] = val & 0x01;
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x208, val);
return;
- case REG_IE :
+ case REG_IE:
NDS_Reschedule();
MMU.reg_IE[ARMCPU_ARM7] = val;
return;
- case REG_IF: REG_IF_WriteLong<ARMCPU_ARM7>(val); return;
-
- case REG_TM0CNTL:
- case REG_TM1CNTL:
- case REG_TM2CNTL:
- case REG_TM3CNTL:
+ case REG_IF:
+ REG_IF_WriteLong<ARMCPU_ARM7>(val);
+ return;
+
+ case REG_TM0CNTL:
+ case REG_TM1CNTL:
+ case REG_TM2CNTL:
+ case REG_TM3CNTL:
{
- int timerIndex = (adr>>2)&0x3;
- MMU.timerReload[ARMCPU_ARM7][timerIndex] = (uint16_t)val;
+ int timerIndex = (adr >> 2) & 0x3;
+ MMU.timerReload[ARMCPU_ARM7][timerIndex] = static_cast<uint16_t>(val);
T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], adr & 0xFFF, static_cast<uint16_t>(val));
- write_timer(ARMCPU_ARM7, timerIndex, val>>16);
+ write_timer(ARMCPU_ARM7, timerIndex, val >> 16);
return;
}
@@ -4184,7 +2644,7 @@
IPC_FIFOsend(ARMCPU_ARM7, val);
return;
- case REG_GCROMCTRL :
+ case REG_GCROMCTRL:
MMU_writeToGCControl<ARMCPU_ARM7>(val);
return;
@@ -4192,573 +2652,191 @@
slot1_device.write32(ARMCPU_ARM7, REG_GCDATAIN,val);
return;
}
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr>>20], val);
- return;
- }
-
- //bool unmapped = false/*, restricted*/;
- //adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped, restricted);
- //if(unmapped) return;
+ T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM7][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr >> 20], val);
+ return;
+ }
+
+#ifdef HAVE_JIT
+ if (JIT_MAPPED(adr, ARMCPU_ARM7))
+ {
+ JIT_COMPILED_FUNC_PREMASKED(adr, ARMCPU_ARM7, 0) = 0;
+ JIT_COMPILED_FUNC_PREMASKED(adr, ARMCPU_ARM7, 1) = 0;
+ }
+#endif
// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF [shash]
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20], val);
-}
-
-//================================================= MMU ARM7 read 08
+ T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM7][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr >> 20], val);
+}
+
+// ================================================= MMU ARM7 read 08
uint8_t FASTCALL _MMU_ARM7_read08(uint32_t adr)
{
adr &= 0x0FFFFFFF;
- //mmu_log_debug_ARM7(adr, "(read08) 0x%02X", MMU.MMU_MEM[ARMCPU_ARM7][(adr>>20)&0xFF][adr&MMU.MMU_MASK[ARMCPU_ARM7][(adr>>20)&0xFF]]);
-
if (adr < 0x4000)
{
- //uint32_t prot = T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x04000308 & MMU.MMU_MASK[ARMCPU_ARM7][0x40]);
- //if (prot) INFO("MMU7 read 08 at 0x%08X (PC 0x%08X) BIOSPROT address 0x%08X\n", adr, NDS_ARM7.R[15], prot);
-
- //How accurate is this? our R[15] may not be exactly what the hardware uses (may use something less by up to 0x08)
- //This may be inaccurate at the very edge cases.
- if (NDS_ARM7.R[15] > 0x3FFF)
+ // How accurate is this? our R[15] may not be exactly what the hardware uses (may use something less by up to 0x08)
+ // This may be inaccurate at the very edge cases.
+ if (NDS_ARM7.instruct_adr > 0x3FFF)
return 0xFF;
}
- // wifi mac access
- /*if ((adr & 0xFFFF0000) == 0x04800000)
- {
- if (adr & 1)
- return (WIFI_read16(adr-1) >> 8) & 0xFF;
- else
- return WIFI_read16(adr) & 0xFF;
- }*/
-
- if ( (adr >= 0x08000000) && (adr < 0x0A010000) )
- return 0/*addon.read08(adr)*/;
-
- if ((adr>=0x04000400)&&(adr<0x04000520))
- {
- return SPU_ReadByte(adr);
- }
-
- //if (adr == REG_RTC) return (uint8_t)rtcRead();
-
- if (adr >> 24 == 4)
- {
- if(MMU_new.is_dma(adr)) return static_cast<uint8_t>(MMU_new.read_dma(ARMCPU_ARM7,8,adr));
+ if (adr >= 0x08000000 && adr < 0x0A010000)
+ return 0;
+
+ if (adr >= 0x04000400 && adr < 0x04000520)
+ return SPU_ReadByte(adr);
+
+ if ((adr >> 24) == 4)
+ {
+ if (MMU_new.is_dma(adr))
+ return static_cast<uint8_t>(MMU_new.read_dma(ARMCPU_ARM7, 8, adr));
// Address is an IO register
- switch(adr)
- {
- case REG_IF: return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM7>());
- case REG_IF+1: return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM7>()>>8);
- case REG_IF+2: return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM7>()>>16);
- case REG_IF+3: return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM7>()>>24);
-
- /*case REG_DISPx_VCOUNT: return nds.VCount&0xFF;
- case REG_DISPx_VCOUNT+1: return (nds.VCount>>8)&0xFF;*/
- }
-
- return MMU.MMU_MEM[ARMCPU_ARM7][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20]];
- }
-
- //bool unmapped = false/*, restricted*/;
- //adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped, restricted);
- //if(unmapped) return 0;
-
- return MMU.MMU_MEM[ARMCPU_ARM7][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20]];
-}
-//================================================= MMU ARM7 read 16
+ switch (adr)
+ {
+ case REG_IF:
+ return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM7>());
+ case REG_IF + 1:
+ return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM7>() >> 8);
+ case REG_IF + 2:
+ return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM7>() >> 16);
+ case REG_IF + 3:
+ return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM7>() >> 24);
+
+ case REG_WRAMSTAT:
+ return MMU.WRAMCNT;
+ }
+
+ return MMU.MMU_MEM[ARMCPU_ARM7][adr >> 20][adr & MMU.MMU_MASK[ARMCPU_ARM7][adr >> 20]];
+ }
+
+ return MMU.MMU_MEM[ARMCPU_ARM7][adr >> 20][adr & MMU.MMU_MASK[ARMCPU_ARM7][adr >> 20]];
+}
+
+// ================================================= MMU ARM7 read 16
uint16_t FASTCALL _MMU_ARM7_read16(uint32_t adr)
{
adr &= 0x0FFFFFFE;
- //mmu_log_debug_ARM7(adr, "(read16) 0x%04X", T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][(adr>>20)&0xFF], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr>>20)&0xFF]));
-
if (adr < 0x4000)
{
- //uint32_t prot = T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x04000308 & MMU.MMU_MASK[ARMCPU_ARM7][0x40]);
- //if (prot) INFO("MMU7 read 16 at 0x%08X (PC 0x%08X) BIOSPROT address 0x%08X\n", adr, NDS_ARM7.R[15], prot);
- if (NDS_ARM7.R[15] > 0x3FFF)
+ if (NDS_ARM7.instruct_adr > 0x3FFF)
return 0xFFFF;
}
- //wifi mac access
- /*if ((adr & 0xFFFF0000) == 0x04800000)
- return WIFI_read16(adr) ;*/
-
- if ( (adr >= 0x08000000) && (adr < 0x0A010000) )
- return 0/*addon.read16(adr)*/;
-
- if ((adr>=0x04000400)&&(adr<0x04000520))
- {
- return SPU_ReadWord(adr);
- }
-
- if(adr>>24==4)
- { //Address is an IO register
-
- if(MMU_new.is_dma(adr)) return static_cast<uint16_t>(MMU_new.read_dma(ARMCPU_ARM7,16,adr));
-
- switch(adr)
- {
- /*case REG_POWCNT2:
- {
- uint16_t ret = 0;
- ret |= nds.power2.speakers?BIT(0):0;
- ret |= nds.power2.wifi?BIT(1):0;
- return ret;
- }*/
-
- //case REG_DISPx_VCOUNT: return nds.VCount;
- //case REG_RTC: return rtcRead();
- case REG_IME: return (uint16_t)MMU.reg_IME[ARMCPU_ARM7];
+ if (adr >= 0x08000000 && adr < 0x0A010000)
+ return 0;
+
+ if (adr >= 0x04000400 && adr < 0x04000520)
+ return SPU_ReadWord(adr);
+
+ if ((adr >> 24) == 4)
+ {
+ // Address is an IO register
+
+ if (MMU_new.is_dma(adr))
+ return static_cast<uint16_t>(MMU_new.read_dma(ARMCPU_ARM7, 16, adr));
+
+ switch (adr)
+ {
+ case REG_IME:
+ return static_cast<uint16_t>(MMU.reg_IME[ARMCPU_ARM7]);
case REG_IE:
- return (uint16_t)MMU.reg_IE[ARMCPU_ARM7];
+ return static_cast<uint16_t>(MMU.reg_IE[ARMCPU_ARM7]);
case REG_IE + 2:
- return (uint16_t)(MMU.reg_IE[ARMCPU_ARM7]>>16);
-
- case REG_IF: return static_cast<uint16_t>(MMU.gen_IF<ARMCPU_ARM7>());
- case REG_IF+2: return static_cast<uint16_t>(MMU.gen_IF<ARMCPU_ARM7>()>>16);
-
- case REG_TM0CNTL :
- case REG_TM1CNTL :
- case REG_TM2CNTL :
- case REG_TM3CNTL :
- return read_timer(ARMCPU_ARM7,(adr&0xF)>>2);
-
- /*case REG_AUXSPICNT:
- return MMU.AUX_SPI_CNT;*/
-
- /*case REG_KEYINPUT:
- //here is an example of what not to do:
- //since the arm7 polls this (and EXTKEYIN) every frame, we shouldnt count this as an input check
- //LagFrameFlag=0;
- break;*/
-
- /*case REG_EXTKEYIN:
- {
- //this is gross. we should generate this whole reg instead of poking it in ndssystem
- uint16_t ret = MMU.ARM7_REG[0x136];
- if(nds.isTouch) ret &= ~64;
- else ret |= 64;
- return ret;
- }*/
- }
- return T1ReadWord_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr>>20]);
- }
-
- //bool unmapped = false/*, restricted*/;
- //adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped, restricted);
- //if(unmapped) return 0;
+ return static_cast<uint16_t>(MMU.reg_IE[ARMCPU_ARM7] >> 16);
+
+ case REG_IF:
+ return static_cast<uint16_t>(MMU.gen_IF<ARMCPU_ARM7>());
+ case REG_IF + 2:
+ return static_cast<uint16_t>(MMU.gen_IF<ARMCPU_ARM7>() >> 16);
+
+ case REG_TM0CNTL:
+ case REG_TM1CNTL:
+ case REG_TM2CNTL:
+ case REG_TM3CNTL:
+ return read_timer(ARMCPU_ARM7, (adr & 0xF) >> 2);
+
+ case REG_VRAMSTAT:
+ // make sure WRAMSTAT is stashed and then fallthrough to return the value from memory. i know, gross.
+ T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x241, MMU.WRAMCNT);
+ break;
+ }
+ return T1ReadWord_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr >> 20]);
+ }
/* Returns data from memory */
// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF
return T1ReadWord_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr >> 20]);
}
-//================================================= MMU ARM7 read 32
+
+// ================================================= MMU ARM7 read 32
uint32_t FASTCALL _MMU_ARM7_read32(uint32_t adr)
{
adr &= 0x0FFFFFFC;
- //mmu_log_debug_ARM7(adr, "(read32) 0x%08X", T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][(adr>>20)&0xFF], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr>>20)&0xFF]));
-
if (adr < 0x4000)
{
- //uint32_t prot = T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x04000308 & MMU.MMU_MASK[ARMCPU_ARM7][0x40]);
- //if (prot) INFO("MMU7 read 32 at 0x%08X (PC 0x%08X) BIOSPROT address 0x%08X\n", adr, NDS_ARM7.R[15], prot);
- if (NDS_ARM7.R[15] > 0x3FFF)
+ if (NDS_ARM7.instruct_adr > 0x3FFF)
return 0xFFFFFFFF;
}
- //wifi mac access
- /*if ((adr & 0xFFFF0000) == 0x04800000)
- return WIFI_read16(adr) | (WIFI_read16(adr+2) << 16);*/
-
- if ( (adr >= 0x08000000) && (adr < 0x0A010000) )
- return 0/*addon.read32(adr)*/;
-
- if ((adr>=0x04000400)&&(adr<0x04000520))
- {
- return SPU_ReadLong(adr);
- }
-
- if((adr >> 24) == 4)
- { //Address is an IO register
-
- if(MMU_new.is_dma(adr)) return MMU_new.read_dma(ARMCPU_ARM7,32,adr);
-
- switch(adr)
- {
- //case REG_RTC: return (uint32_t)rtcRead();
- //case REG_DISPx_VCOUNT: return nds.VCount;
-
- case REG_IME :
+ if (adr >= 0x08000000 && adr < 0x0A010000)
+ return 0;
+
+ if (adr >= 0x04000400 && adr < 0x04000520)
+ return SPU_ReadLong(adr);
+
+ if ((adr >> 24) == 4)
+ {
+ // Address is an IO register
+
+ if (MMU_new.is_dma(adr))
+ return MMU_new.read_dma(ARMCPU_ARM7, 32, adr);
+
+ switch (adr)
+ {
+ case REG_IME:
return MMU.reg_IME[ARMCPU_ARM7];
- case REG_IE :
+ case REG_IE:
return MMU.reg_IE[ARMCPU_ARM7];
- case REG_IF: return MMU.gen_IF<ARMCPU_ARM7>();
- case REG_IPCFIFORECV :
+ case REG_IF:
+ return MMU.gen_IF<ARMCPU_ARM7>();
+ case REG_IPCFIFORECV:
return IPC_FIFOrecv(ARMCPU_ARM7);
- case REG_TM0CNTL :
- case REG_TM1CNTL :
- case REG_TM2CNTL :
- case REG_TM3CNTL :
+ case REG_TM0CNTL:
+ case REG_TM1CNTL:
+ case REG_TM2CNTL:
+ case REG_TM3CNTL:
{
uint32_t val = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], (adr + 2) & 0xFFF);
- return MMU.timer[ARMCPU_ARM7][(adr&0xF)>>2] | (val<<16);
+ return MMU.timer[ARMCPU_ARM7][(adr & 0xF) >> 2] | (val << 16);
}
case REG_GCROMCTRL:
- {
- //INFO("arm7 romctrl read\n");
break;
- }
- case REG_GCDATAIN:
+ case REG_GCDATAIN:
return MMU_readFromGC<ARMCPU_ARM7>();
- }
- return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr>>20]);
- }
-
- //bool unmapped = false/*, restricted*/;
- //adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped, restricted);
- //if(unmapped) return 0;
-
- //Returns data from memory
+ case REG_VRAMSTAT:
+ // make sure WRAMSTAT is stashed and then fallthrough return the value from memory. i know, gross.
+ T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x241, MMU.WRAMCNT);
+ break;
+ }
+
+ return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr >> 20]);
+ }
+
+ // Returns data from memory
// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF [zeromus, inspired by shash]
return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr >> 20]);
}
-//=========================================================================================================
-
-/*uint32_t FASTCALL MMU_read32(uint32_t proc, uint32_t adr)
-{
- ASSERT_UNALIGNED((adr&3)==0);
-
- if(proc==0)
- return _MMU_ARM9_read32(adr);
- else
- return _MMU_ARM7_read32(adr);
-}*/
-
-/*uint16_t FASTCALL MMU_read16(uint32_t proc, uint32_t adr)
-{
- ASSERT_UNALIGNED((adr&1)==0);
-
- if(proc==0)
- return _MMU_ARM9_read16(adr);
- else
- return _MMU_ARM7_read16(adr);
-}*/
-
-/*uint8_t FASTCALL MMU_read8(uint32_t proc, uint32_t adr)
-{
- if(proc==0)
- return _MMU_ARM9_read08(adr);
- else
- return _MMU_ARM7_read08(adr);
-}*/
-
-/*void FASTCALL MMU_write32(uint32_t proc, uint32_t adr, uint32_t val)
-{
- ASSERT_UNALIGNED((adr&3)==0);
-
- if(proc==0)
- _MMU_ARM9_write32(adr, val);
- else
- _MMU_ARM7_write32(adr,val);
-}*/
-
-/*void FASTCALL MMU_write16(uint32_t proc, uint32_t adr, uint16_t val)
-{
- ASSERT_UNALIGNED((adr&1)==0);
-
- if(proc==0)
- _MMU_ARM9_write16(adr, val);
- else
- _MMU_ARM7_write16(adr,val);
-}*/
-
-/*void FASTCALL MMU_write8(uint32_t proc, uint32_t adr, uint8_t val)
-{
- if(proc==0)
- _MMU_ARM9_write08(adr, val);
- else
- _MMU_ARM7_write08(adr,val);
-}*/
-
-/*void FASTCALL MMU_DumpMemBlock(uint8_t proc, uint32_t address, uint32_t size, uint8_t *buffer)
-{
- uint32_t i;
- uint32_t curaddr;
-
- for(i = 0, curaddr = address; i < size; i++, curaddr++)
- {
- buffer[i] = _MMU_read08(proc,MMU_AT_DEBUG,curaddr);
- }
-}*/
-
-
-//these templates needed to be instantiated manually
+// =========================================================================================================
+
+// these templates needed to be instantiated manually
template uint32_t MMU_struct::gen_IF<ARMCPU_ARM9>();
template uint32_t MMU_struct::gen_IF<ARMCPU_ARM7>();
-////////////////////////////////////////////////////////////
-//function pointer handlers for gdb stub stuff
-
-/*static uint16_t FASTCALL arm9_prefetch16( void *, uint32_t adr) {
- return _MMU_read16<ARMCPU_ARM9,MMU_AT_CODE>(adr);
-}
-
-static uint32_t FASTCALL arm9_prefetch32( void *, uint32_t adr) {
- return _MMU_read32<ARMCPU_ARM9,MMU_AT_CODE>(adr);
-}
-
-static uint8_t FASTCALL arm9_read8( void *, uint32_t adr) {
- return _MMU_read08<ARMCPU_ARM9>(adr);
-}
-
-static uint16_t FASTCALL arm9_read16( void *, uint32_t adr) {
- return _MMU_read16<ARMCPU_ARM9>(adr);
-}
-
-static uint32_t FASTCALL arm9_read32( void *, uint32_t adr) {
- return _MMU_read32<ARMCPU_ARM9>(adr);
-}
-
-static void FASTCALL arm9_write8(void *, uint32_t adr, uint8_t val) {
- _MMU_write08<ARMCPU_ARM9>(adr, val);
-}
-
-static void FASTCALL arm9_write16(void *, uint32_t adr, uint16_t val) {
- _MMU_write16<ARMCPU_ARM9>(adr, val);
-}
-
-static void FASTCALL arm9_write32(void *, uint32_t adr, uint32_t val) {
- _MMU_write32<ARMCPU_ARM9>(adr, val);
-}
-
-static uint16_t FASTCALL arm7_prefetch16( void *, uint32_t adr) {
- return _MMU_read16<ARMCPU_ARM7,MMU_AT_CODE>(adr);
-}
-
-static uint32_t FASTCALL arm7_prefetch32( void *, uint32_t adr) {
- return _MMU_read32<ARMCPU_ARM7,MMU_AT_CODE>(adr);
-}
-
-static uint8_t FASTCALL arm7_read8( void *, uint32_t adr) {
- return _MMU_read08<ARMCPU_ARM7>(adr);
-}
-
-static uint16_t FASTCALL arm7_read16( void *, uint32_t adr) {
- return _MMU_read16<ARMCPU_ARM7>(adr);
-}
-
-static uint32_t FASTCALL arm7_read32( void *, uint32_t adr) {
- return _MMU_read32<ARMCPU_ARM7>(adr);
-}
-
-static void FASTCALL arm7_write8(void *, uint32_t adr, uint8_t val) {
- _MMU_write08<ARMCPU_ARM7>(adr, val);
-}
-
-static void FASTCALL arm7_write16(void *, uint32_t adr, uint16_t val) {
- _MMU_write16<ARMCPU_ARM7>(adr, val);
-}
-
-static void FASTCALL arm7_write32(void *, uint32_t adr, uint32_t val) {
- _MMU_write32<ARMCPU_ARM7>(adr, val);
-}*/
-
-
-
-/*
- * the base memory interfaces
- */
-/*struct armcpu_memory_iface arm9_base_memory_iface = {
- arm9_prefetch32,
- arm9_prefetch16,
-
- arm9_read8,
- arm9_read16,
- arm9_read32,
-
- arm9_write8,
- arm9_write16,
- arm9_write32
-};
-
-struct armcpu_memory_iface arm7_base_memory_iface = {
- arm7_prefetch32,
- arm7_prefetch16,
-
- arm7_read8,
- arm7_read16,
- arm7_read32,
-
- arm7_write8,
- arm7_write16,
- arm7_write32
-};*/
-
-/*
- * The direct memory interface for the ARM9.
- * This avoids the ARM9 protection unit when accessing
- * memory.
- */
-/*struct armcpu_memory_iface arm9_direct_memory_iface = {
- NULL,
- NULL,
-
- arm9_read8,
- arm9_read16,
- arm9_read32,
-
- arm9_write8,
- arm9_write16,
- arm9_write32
-};*/
-
-
-/////////////////////////////////////////////////////////////////
-/////////////////////////////////////////////////////////////////
-/////////////////////////////////////////////////////////////////
-/////////////////////////////////////////////////////////////////
-/////////////////////////////////////////////////////////////////
-/////////////////////////////////////////////////////////////////
-
-//#ifdef PROFILE_MEMORY_ACCESS
-//
-//#define PROFILE_PREFETCH 0
-//#define PROFILE_READ 1
-//#define PROFILE_WRITE 2
-//
-//struct mem_access_profile {
-// uint64_t num_accesses;
-// uint32_t address_mask;
-// uint32_t masked_value;
-//};
-//
-//#define PROFILE_NUM_MEM_ACCESS_PROFILES 4
-//
-//static uint64_t profile_num_accesses[2][3];
-//static uint64_t profile_unknown_addresses[2][3];
-//static struct mem_access_profile
-//profile_memory_accesses[2][3][PROFILE_NUM_MEM_ACCESS_PROFILES];
-//
-//static void
-//setup_profiling() {
-// int i;
-//
-// for ( i = 0; i < 2; i++) {
-// int access_type;
-//
-// for ( access_type = 0; access_type < 3; access_type++) {
-// profile_num_accesses[i][access_type] = 0;
-// profile_unknown_addresses[i][access_type] = 0;
-//
-// /*
-// * Setup the access testing structures
-// */
-// profile_memory_accesses[i][access_type][0].address_mask = 0x0e000000;
-// profile_memory_accesses[i][access_type][0].masked_value = 0x00000000;
-// profile_memory_accesses[i][access_type][0].num_accesses = 0;
-//
-// /* main memory */
-// profile_memory_accesses[i][access_type][1].address_mask = 0x0f000000;
-// profile_memory_accesses[i][access_type][1].masked_value = 0x02000000;
-// profile_memory_accesses[i][access_type][1].num_accesses = 0;
-//
-// /* shared memory */
-// profile_memory_accesses[i][access_type][2].address_mask = 0x0f800000;
-// profile_memory_accesses[i][access_type][2].masked_value = 0x03000000;
-// profile_memory_accesses[i][access_type][2].num_accesses = 0;
-//
-// /* arm7 memory */
-// profile_memory_accesses[i][access_type][3].address_mask = 0x0f800000;
-// profile_memory_accesses[i][access_type][3].masked_value = 0x03800000;
-// profile_memory_accesses[i][access_type][3].num_accesses = 0;
-// }
-// }
-//}
-//
-//static void
-//profile_memory_access( int arm9, uint32_t adr, int access_type) {
-// static int first = 1;
-// int mem_profile;
-// int address_found = 0;
-//
-// if ( first) {
-// setup_profiling();
-// first = 0;
-// }
-//
-// profile_num_accesses[arm9][access_type] += 1;
-//
-// for ( mem_profile = 0;
-// mem_profile < PROFILE_NUM_MEM_ACCESS_PROFILES &&
-// !address_found;
-// mem_profile++) {
-// if ( (adr & profile_memory_accesses[arm9][access_type][mem_profile].address_mask) ==
-// profile_memory_accesses[arm9][access_type][mem_profile].masked_value) {
-// /*printf( "adr %08x mask %08x res %08x expected %08x\n",
-// adr,
-// profile_memory_accesses[arm9][access_type][mem_profile].address_mask,
-// adr & profile_memory_accesses[arm9][access_type][mem_profile].address_mask,
-// profile_memory_accesses[arm9][access_type][mem_profile].masked_value);*/
-// address_found = 1;
-// profile_memory_accesses[arm9][access_type][mem_profile].num_accesses += 1;
-// }
-// }
-//
-// if ( !address_found) {
-// profile_unknown_addresses[arm9][access_type] += 1;
-// }
-//}
-//
-//
-//static const char *access_type_strings[] = {
-// "prefetch",
-// "read ",
-// "write "
-//};
-//
-//void
-//print_memory_profiling() {
-// int arm;
-//
-// printf("------ Memory access profile ------\n");
-//
-// for ( arm = 0; arm < 2; arm++) {
-// int access_type;
-//
-// for ( access_type = 0; access_type < 3; access_type++) {
-// int mem_profile;
-// printf("ARM%c: num of %s %lld\n",
-// arm ? '9' : '7',
-// access_type_strings[access_type],
-// profile_num_accesses[arm][access_type]);
-//
-// for ( mem_profile = 0;
-// mem_profile < PROFILE_NUM_MEM_ACCESS_PROFILES;
-// mem_profile++) {
-// printf( "address %08x: %lld\n",
-// profile_memory_accesses[arm][access_type][mem_profile].masked_value,
-// profile_memory_accesses[arm][access_type][mem_profile].num_accesses);
-// }
-//
-// printf( "unknown addresses %lld\n",
-// profile_unknown_addresses[arm][access_type]);
-//
-// printf( "\n");
-// }
-// }
-//
-// printf("------ End of Memory access profile ------\n\n");
-//}
-//#else
-//void
-//print_memory_profiling() {
-//}
-//#endif /* End of PROFILE_MEMORY_ACCESS area */
-
--- a/src/in_2sf/desmume/MMU.h
+++ b/src/in_2sf/desmume/MMU.h
@@ -26,15 +26,18 @@
#include "mc.h"
#include "bits.h"
#include "readwrite.h"
-//#include "debug.h"
#ifdef HAVE_LUA
#include "lua-engine.h"
+#endif
+
+#ifdef HAVE_JIT
+#include "arm_jit.h"
#endif
#define ARMCPU_ARM7 1
#define ARMCPU_ARM9 0
-#define ARMPROC (PROCNUM ? NDS_ARM7:NDS_ARM9)
+#define ARMPROC (PROCNUM ? NDS_ARM7 : NDS_ARM9)
typedef const uint8_t TWaitState;
@@ -74,61 +77,71 @@
EDMADestinationUpdate_IncrementReload = 3
};
-//TODO
-//n.b. this may be a bad idea, for complex registers like the dma control register.
-//we need to know exactly what part was written to, instead of assuming all 32bits were written.
+// TODO
+// n.b. this may be a bad idea, for complex registers like the dma control register.
+// we need to know exactly what part was written to, instead of assuming all 32bits were written.
class TRegister_32
{
public:
virtual uint32_t read32() = 0;
- virtual void write32(const uint32_t val) = 0;
- void write(const int size, const uint32_t adr, const uint32_t val) {
- if(size==32) write32(val);
- else {
- const uint32_t offset = adr&3;
- if(size==8) {
+ virtual void write32(uint32_t val) = 0;
+ void write(int size, uint32_t adr, uint32_t val)
+ {
+ if (size == 32)
+ this->write32(val);
+ else
+ {
+ uint32_t offset = adr & 3;
+ if (size == 8)
+ {
printf("WARNING! 8BIT DMA ACCESS\n");
- uint32_t mask = 0xFF<<(offset<<3);
- write32((read32()&~mask)|(val<<(offset<<3)));
+ uint32_t mask = 0xFF << (offset << 3);
+ this->write32((this->read32() & ~mask) | (val << (offset << 3)));
}
- else if(size==16) {
- uint32_t mask = 0xFFFF<<(offset<<3);
- write32((read32()&~mask)|(val<<(offset<<3)));
+ else if (size == 16)
+ {
+ uint32_t mask = 0xFFFF << (offset << 3);
+ this->write32((this->read32() & ~mask) | (val << (offset << 3)));
}
}
}
- uint32_t read(const int size, const uint32_t adr)
- {
- if(size==32) return read32();
- else {
- const uint32_t offset = adr&3;
- if(size==8) { printf("WARNING! 8BIT DMA ACCESS\n"); return (read32()>>(offset<<3))&0xFF; }
- else return (read32()>>(offset<<3))&0xFFFF;
+ uint32_t read(int size, uint32_t adr)
+ {
+ if (size == 32)
+ return this->read32();
+ else
+ {
+ uint32_t offset = adr & 3;
+ if (size == 8)
+ {
+ printf("WARNING! 8BIT DMA ACCESS\n");
+ return (this->read32() >> (offset << 3)) & 0xFF;
+ }
+ else
+ return (this->read32() >> (offset << 3)) & 0xFFFF;
}
}
};
struct TGXSTAT : public TRegister_32
{
- TGXSTAT() {
- gxfifo_irq = se = tr = tb = sb = 0;
- fifo_empty = true;
- fifo_low = false;
- }
- uint8_t tb; //test busy
- uint8_t tr; //test result
- uint8_t se; //stack error
- uint8_t sb; //stack busy
- uint8_t gxfifo_irq; //irq configuration
+ TGXSTAT()
+ {
+ this->gxfifo_irq = this->se = this->tr = this->tb = this->sb = 0;
+ this->fifo_empty = true;
+ this->fifo_low = false;
+ }
+ uint8_t tb; // test busy
+ uint8_t tr; // test result
+ uint8_t se; // stack error
+ uint8_t sb; // stack busy
+ uint8_t gxfifo_irq; // irq configuration
bool fifo_empty, fifo_low;
virtual uint32_t read32();
- virtual void write32(const uint32_t val);
-
- //void savestate(EMUFILE *f);
- bool loadstate(EMUFILE *f);
+ virtual void write32(uint32_t val);
};
void triggerDma(EDMAMode mode);
@@ -136,54 +149,25 @@
class DivController
{
public:
- DivController()
- : mode(0), busy(0)
- {}
+ DivController() : mode(0), busy(0) { }
void exec();
uint8_t mode, busy, div0;
- uint16_t read16() { return mode|(busy<<15)|(div0<<14); }
- void write16(uint16_t val) {
- mode = val&3;
- //todo - do we clear the div0 flag here or is that strictly done by the divider unit?
- }
- /*void savestate(EMUFILE* os)
- {
- write8le(&mode,os);
- write8le(&busy,os);
- write8le(&div0,os);
- }*/
- bool loadstate(EMUFILE* is, int)
- {
- int ret = 1;
- ret &= read8le(&mode,is);
- ret &= read8le(&busy,is);
- ret &= read8le(&div0,is);
- return ret==1;
+ uint16_t read16() { return this->mode | (this->busy << 15) | (this->div0 << 14); }
+ void write16(uint16_t val)
+ {
+ this->mode = val & 3;
+ // todo - do we clear the div0 flag here or is that strictly done by the divider unit?
}
};
class SqrtController
{
public:
- SqrtController()
- : mode(0), busy(0)
- {}
+ SqrtController() : mode(0), busy(0) { }
void exec();
uint8_t mode, busy;
- uint16_t read16() { return mode|(busy<<15); }
- void write16(uint16_t val) { mode = val&1; }
- /*void savestate(EMUFILE* os)
- {
- write8le(&mode,os);
- write8le(&busy,os);
- }*/
- bool loadstate(EMUFILE* is, int)
- {
- int ret=1;
- ret &= read8le(&mode,is);
- ret &= read8le(&busy,is);
- return ret==1;
- }
+ uint16_t read16() { return this->mode | (this->busy << 15); }
+ void write16(uint16_t val) { this->mode = val & 1; }
};
class DmaController
@@ -199,25 +183,22 @@
uint32_t saddr, daddr;
uint32_t saddr_user, daddr_user;
- //indicates whether the dma needs to be checked for triggering
+ // indicates whether the dma needs to be checked for triggering
bool dmaCheck;
- //indicates whether the dma right now is logically running
- //(though for now we copy all the data when it triggers)
+ // indicates whether the dma right now is logically running
+ // (though for now we copy all the data when it triggers)
bool running;
bool paused;
- //this flag will sometimes be set when a start condition is triggered
- //other conditions may be automatically triggered based on scanning conditions
+ // this flag will sometimes be set when a start condition is triggered
+ // other conditions may be automatically triggered based on scanning conditions
bool triggered;
uint64_t nextEvent;
int procnum, chan;
-
- //void savestate(EMUFILE *f);
- bool loadstate(EMUFILE *f);
void exec();
template<int PROCNUM> void doCopy();
@@ -231,8 +212,8 @@
wordcount(0), startmode(EDMAMode_Immediate),
bitWidth(EDMABitWidth_16),
sar(EDMASourceUpdate_Increment), dar(EDMADestinationUpdate_Increment),
- //if saddr isnt cleared then rings of fate will trigger copy protection
- //by inspecting dma3 saddr when it boots
+ // if saddr isnt cleared then rings of fate will trigger copy protection
+ // by inspecting dma3 saddr when it boots
saddr(0), daddr(0),
saddr_user(0), daddr_user(0),
dmaCheck(false),
@@ -243,50 +224,53 @@
sad(&saddr_user),
dad(&daddr_user)
{
- sad.controller = this;
- dad.controller = this;
- ctrl.controller = this;
- regs[0] = &sad;
- regs[1] = &dad;
- regs[2] = &ctrl;
- }
-
- class AddressRegister : public TRegister_32 {
+ this->sad.controller = this;
+ this->dad.controller = this;
+ this->ctrl.controller = this;
+ this->regs[0] = &this->sad;
+ this->regs[1] = &this->dad;
+ this->regs[2] = &this->ctrl;
+ }
+
+ class AddressRegister : public TRegister_32
+ {
public:
- //we pass in a pointer to the controller here so we can alert it if anything changes
- DmaController* controller;
- uint32_t * const ptr;
- AddressRegister(uint32_t* _ptr)
- : ptr(_ptr)
- {}
- virtual uint32_t read32() {
- return *ptr;
+ // we pass in a pointer to the controller here so we can alert it if anything changes
+ DmaController *controller;
+ uint32_t *const ptr;
+ AddressRegister(uint32_t *_ptr) : ptr(_ptr) { }
+ virtual uint32_t read32()
+ {
+ return *this->ptr;
}
- virtual void write32(const uint32_t val) {
- *ptr = val;
+ virtual void write32(uint32_t val)
+ {
+ *this->ptr = val;
}
};
- class ControlRegister : public TRegister_32 {
+ class ControlRegister : public TRegister_32
+ {
public:
- //we pass in a pointer to the controller here so we can alert it if anything changes
- DmaController* controller;
- ControlRegister() {}
- virtual uint32_t read32() {
- return controller->read32();
+ // we pass in a pointer to the controller here so we can alert it if anything changes
+ DmaController *controller;
+ ControlRegister() { }
+ virtual uint32_t read32()
+ {
+ return this->controller->read32();
}
- virtual void write32(const uint32_t val) {
- return controller->write32(val);
+ virtual void write32(uint32_t val)
+ {
+ return this->controller->write32(val);
}
};
AddressRegister sad, dad;
ControlRegister ctrl;
- TRegister_32* regs[3];
-
- void write32(const uint32_t val);
+ TRegister_32 *regs[3];
+
+ void write32(uint32_t val);
uint32_t read32();
-
};
enum ECardMode
@@ -296,9 +280,8 @@
CardMode_KEY2
};
-typedef struct
-{
-
+struct nds_dscard
+{
uint8_t command[8];
uint32_t address;
@@ -308,68 +291,74 @@
// NJSD stuff
int blocklen;
-
-} nds_dscard;
+};
+
+#define DUP2(x) x, x
+#define DUP4(x) x, x, x, x
+#define DUP8(x) x, x, x, x, x, x, x, x
+#define DUP16(x) x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x
struct MMU_struct
{
//ARM9 mem
uint8_t ARM9_ITCM[0x8000];
- uint8_t ARM9_DTCM[0x4000];
-
- //u8 MAIN_MEM[4*1024*1024]; //expanded from 4MB to 8MB to support debug consoles
- //u8 MAIN_MEM[8*1024*1024]; //expanded from 8MB to 16MB to support dsi
- uint8_t MAIN_MEM[16*1024*1024]; //expanded from 8MB to 16MB to support dsi
- uint8_t ARM9_REG[0x1000000];
- uint8_t ARM9_BIOS[0x8000];
- uint8_t ARM9_VMEM[0x800];
-
- #include "PACKED.h"
- struct {
+ uint8_t ARM9_DTCM[0x4000];
+
+ //u8 MAIN_MEM[4*1024*1024]; // expanded from 4MB to 8MB to support debug consoles
+ //u8 MAIN_MEM[8*1024*1024]; // expanded from 8MB to 16MB to support dsi
+ uint8_t MAIN_MEM[16*1024*1024]; // expanded from 8MB to 16MB to support dsi
+ uint8_t ARM9_REG[0x1000000];
+ uint8_t ARM9_BIOS[0x8000];
+ uint8_t ARM9_VMEM[0x800];
+
+#include "PACKED.h"
+ struct
+ {
uint8_t ARM9_LCD[0xA4000];
- //an extra 128KB for blank memory, directly after arm9_lcd, so that
- //we can easily map things to the end of arm9_lcd to represent
- //an unmapped state
+ // an extra 128KB for blank memory, directly after arm9_lcd, so that
+ // we can easily map things to the end of arm9_lcd to represent
+ // an unmapped state
uint8_t blank_memory[0x20000];
};
- #include "PACKED_END.h"
-
- uint8_t ARM9_OAM[0x800];
-
- uint8_t* ExtPal[2][4];
- uint8_t* ObjExtPal[2][2];
-
- struct TextureInfo {
- uint8_t* texPalSlot[6];
- uint8_t* textureSlotAddr[4];
+#include "PACKED_END.h"
+
+ uint8_t ARM9_OAM[0x800];
+
+ uint8_t *ExtPal[2][4];
+ uint8_t *ObjExtPal[2][2];
+
+ struct TextureInfo
+ {
+ uint8_t *texPalSlot[6];
+ uint8_t *textureSlotAddr[4];
} texInfo;
- //ARM7 mem
+ // ARM7 mem
uint8_t ARM7_BIOS[0x4000];
- uint8_t ARM7_ERAM[0x10000];
+ uint8_t ARM7_ERAM[0x10000]; // 64KB of exclusive WRAM
uint8_t ARM7_REG[0x10000];
- uint8_t ARM7_WIRAM[0x10000];
+ uint8_t ARM7_WIRAM[0x10000]; // WIFI ram
// VRAM mapping
uint8_t VRAM_MAP[4][32];
uint32_t LCD_VRAM_ADDR[10];
uint8_t LCDCenable[10];
- //Shared ram
+ // 32KB of shared WRAM - can be switched between ARM7 & ARM9 in two blocks
uint8_t SWIRAM[0x8000];
- //Card rom & ram
+ // Card rom & ram
uint8_t * CART_ROM;
- //Unused ram
+ // Unused ram
uint8_t UNUSED_RAM[4];
- //this is here so that we can trap glitchy emulator code
- //which is accessing offsets 5,6,7 of unused ram due to unaligned accesses
- //(also since the emulator doesn't prevent unaligned accesses)
+ // this is here so that we can trap glitchy emulator code
+ // which is accessing offsets 5,6,7 of unused ram due to unaligned accesses
+ // (also since the emulator doesn't prevent unaligned accesses)
uint8_t MORE_UNUSED_RAM[4];
- static uint8_t * MMU_MEM[2][256];
+ static uint8_t *MMU_MEM[2][256];
static uint32_t MMU_MASK[2][256];
uint8_t ARM9_RW_MODE;
@@ -386,12 +375,10 @@
uint32_t reg_IME[2];
uint32_t reg_IE[2];
- //these are the user-controlled IF bits. some IF bits are generated as necessary from hardware conditions
+ // these are the user-controlled IF bits. some IF bits are generated as necessary from hardware conditions
uint32_t reg_IF_bits[2];
- //these flags are set occasionally to indicate that an irq should have entered the pipeline, and processing will be deferred a tiny bit to help emulate things
+ // these flags are set occasionally to indicate that an irq should have entered the pipeline, and processing will be deferred a tiny bit to help emulate things
uint32_t reg_IF_pending[2];
-
- //uint32_t reg_DISP3DCNT_bits;
template<int PROCNUM> uint32_t gen_IF();
@@ -409,7 +396,7 @@
uint16_t AUX_SPI_CNT;
uint16_t AUX_SPI_CMD;
- //uint64_t gfx3dCycles;
+ uint8_t WRAMCNT;
uint8_t powerMan_CntReg;
bool powerMan_CntRegWritten;
@@ -420,16 +407,13 @@
nds_dscard dscard[2];
};
-//everything in here is derived from libnds behaviours. no hardware tests yet
+// everything in here is derived from libnds behaviours. no hardware tests yet
class DSI_TSC
{
public:
DSI_TSC();
void reset_command();
uint16_t write16(uint16_t val);
- //bool save_state(EMUFILE* os);
- //bool load_state(EMUFILE* is);
-
private:
uint16_t read16();
uint8_t reg_selection;
@@ -437,17 +421,17 @@
int32_t state;
int32_t readcount;
- //registers[0] contains the current page.
- //we are going to go ahead and save these out in case we want to change the way this is emulated in the future..
- //we may want to poke registers in here at more convenient times and have the TSC dumbly pluck them out,
- //rather than generate the values on the fly
+ // registers[0] contains the current page.
+ // we are going to go ahead and save these out in case we want to change the way this is emulated in the future..
+ // we may want to poke registers in here at more convenient times and have the TSC dumbly pluck them out,
+ // rather than generate the values on the fly
uint8_t registers[0x80];
};
-//this contains things which can't be memzeroed because they are smarter classes
+// this contains things which can't be memzeroed because they are smarter classes
struct MMU_struct_new
{
- MMU_struct_new() ;
+ MMU_struct_new();
BackupDevice backupDevice;
DmaController dma[2][4];
TGXSTAT gxstat;
@@ -455,64 +439,21 @@
DivController div;
DSI_TSC dsi_tsc;
- void write_dma(const int proc, const int size, const uint32_t adr, const uint32_t val);
- uint32_t read_dma(const int proc, const int size, const uint32_t adr);
- bool is_dma(const uint32_t adr) { return adr >= _REG_DMA_CONTROL_MIN && adr <= _REG_DMA_CONTROL_MAX; }
+ void write_dma(int proc, int size, uint32_t adr, uint32_t val);
+ uint32_t read_dma(int proc, int size, uint32_t adr);
+ bool is_dma(uint32_t adr) { return adr >= _REG_DMA_CONTROL_MIN && adr <= _REG_DMA_CONTROL_MAX; }
};
extern MMU_struct MMU;
extern MMU_struct_new MMU_new;
-
-/*struct armcpu_memory_iface {*/
- /** the 32 bit instruction prefetch */
- //uint32_t FASTCALL (*prefetch32)( void *data, uint32_t adr);
-
- /** the 16 bit instruction prefetch */
- //uint16_t FASTCALL (*prefetch16)( void *data, uint32_t adr);
-
- /** read 8 bit data value */
- //uint8_t FASTCALL (*read8)( void *data, uint32_t adr);
- /** read 16 bit data value */
- //uint16_t FASTCALL (*read16)( void *data, uint32_t adr);
- /** read 32 bit data value */
- //uint32_t FASTCALL (*read32)( void *data, uint32_t adr);
-
- /** write 8 bit data value */
- //void FASTCALL (*write8)( void *data, uint32_t adr, uint8_t val);
- /** write 16 bit data value */
- //void FASTCALL (*write16)( void *data, uint32_t adr, uint16_t val);
- /** write 32 bit data value */
- /*void FASTCALL (*write32)( void *data, uint32_t adr, uint32_t val);
-
- void *data;
-};*/
-
-
void MMU_Init();
void MMU_DeInit();
void MMU_Reset();
-void MMU_setRom(uint8_t * rom, uint32_t mask);
+void MMU_setRom(uint8_t *rom, uint32_t mask);
void MMU_unsetRom();
-
-//void print_memory_profiling();
-
-// Memory reading/writing (old)
-//uint8_t FASTCALL MMU_read8(uint32_t proc, uint32_t adr);
-//uint16_t FASTCALL MMU_read16(uint32_t proc, uint32_t adr);
-//uint32_t FASTCALL MMU_read32(uint32_t proc, uint32_t adr);
-//void FASTCALL MMU_write8(uint32_t proc, uint32_t adr, uint8_t val);
-//void FASTCALL MMU_write16(uint32_t proc, uint32_t adr, uint16_t val);
-//void FASTCALL MMU_write32(uint32_t proc, uint32_t adr, uint32_t val);
-
-//template<int PROCNUM> void FASTCALL MMU_doDMA(uint32_t num);
-
-//The base ARM memory interfaces
-//extern struct armcpu_memory_iface arm9_base_memory_iface;
-//extern struct armcpu_memory_iface arm7_base_memory_iface;
-//extern struct armcpu_memory_iface arm9_direct_memory_iface;
#define VRAM_BANKS 9
#define VRAM_BANK_A 0
@@ -530,54 +471,46 @@
#define VRAM_PAGE_AOBJ 256
#define VRAM_PAGE_BOBJ 384
-
-struct VramConfiguration {
-
- enum Purpose {
- OFF, INVALID, ABG, BBG, AOBJ, BOBJ, LCDC, ARM7, TEX, TEXPAL, ABGEXTPAL, BBGEXTPAL, AOBJEXTPAL, BOBJEXTPAL
+struct VramConfiguration
+{
+ enum Purpose
+ {
+ OFF,
+ INVALID,
+ ABG,
+ BBG,
+ AOBJ,
+ BOBJ,
+ LCDC,
+ ARM7,
+ TEX,
+ TEXPAL,
+ ABGEXTPAL,
+ BBGEXTPAL,
+ AOBJEXTPAL,
+ BOBJEXTPAL
};
- struct BankInfo {
+ struct BankInfo
+ {
Purpose purpose;
int ofs;
} banks[VRAM_BANKS];
- inline void clear() {
- for(int i=0;i<VRAM_BANKS;i++) {
+ void clear()
+ {
+ for (int i = 0; i < VRAM_BANKS; ++i)
+ {
banks[i].ofs = 0;
banks[i].purpose = OFF;
}
}
-
- //std::string describePurpose(Purpose p);
- //std::string describe();
};
extern VramConfiguration vramConfiguration;
-#define VRAM_ARM9_PAGES 512
+const int VRAM_ARM9_PAGES = 512;
extern uint8_t vram_arm9_map[VRAM_ARM9_PAGES];
-/*inline void* MMU_gpu_map(uint32_t vram_addr)
-{
- //this is supposed to map a single gpu vram address to emulator host memory
- //but it returns a pointer to some zero memory in case of accesses to unmapped memory.
- //this correctly handles the case with tile accesses to unmapped memory.
- //it could also potentially go through a different LUT than vram_arm9_map in case we discover
- //that it needs to be set up with different or no mirroring
- //(I think it is a reasonable possibility that only the cpu has the nutty mirroring rules)
- //
- //if this system isn't used, Fantasy Aquarium displays garbage in the first ingame screen
- //due to it storing 0x0F0F or somesuch in screen memory which points to a ridiculously big tile
- //which should contain all 0 pixels
-
- uint32_t vram_page = (vram_addr>>14)&(VRAM_ARM9_PAGES-1);
- uint32_t ofs = vram_addr & 0x3FFF;
- vram_page = vram_arm9_map[vram_page];
- //blank pages are handled by the extra 16KB of blank memory at the end of ARM9_LCD
- //and the fact that blank pages are mapped to appear at that location
- return MMU.ARM9_LCD + (vram_page<<14) + ofs;
-}*/
-
template<int PROCNUM, MMU_ACCESS_TYPE AT> uint8_t _MMU_read08(uint32_t addr);
template<int PROCNUM, MMU_ACCESS_TYPE AT> uint16_t _MMU_read16(uint32_t addr);
@@ -612,191 +545,161 @@
extern uint32_t _MMU_MAIN_MEM_MASK;
extern uint32_t _MMU_MAIN_MEM_MASK16;
extern uint32_t _MMU_MAIN_MEM_MASK32;
-/*inline void SetupMMU(bool debugConsole) {
- if(debugConsole) _MMU_MAIN_MEM_MASK = 0x7FFFFF;
- else _MMU_MAIN_MEM_MASK = 0x3FFFFF;
- _MMU_MAIN_MEM_MASK16 = _MMU_MAIN_MEM_MASK & ~1;
- _MMU_MAIN_MEM_MASK32 = _MMU_MAIN_MEM_MASK & ~3;
-}*/
void SetupMMU(bool debugConsole, bool dsi);
-/*inline void CheckMemoryDebugEvent(EDEBUG_EVENT event, const MMU_ACCESS_TYPE type, const uint32_t procnum, const uint32_t addr, const uint32_t size, const uint32_t val)
-{
- //TODO - ugh work out a better prefetch event system
- if(type == MMU_AT_CODE && event == DEBUG_EVENT_READ)
- event = DEBUG_EVENT_EXECUTE;
- if(CheckDebugEvent(event))
- {
- DebugEventData.memAccessType = type;
- DebugEventData.procnum = procnum;
- DebugEventData.addr = addr;
- DebugEventData.size = size;
- DebugEventData.val = val;
- HandleDebugEvent(event);
- }
-}*/
-
-
-//ALERT!!!!!!!!!!!!!!
-//the following inline functions dont do the 0x0FFFFFFF mask.
-//this may result in some unexpected behavior
-
-inline uint8_t _MMU_read08(const int PROCNUM, const MMU_ACCESS_TYPE AT, const uint32_t addr)
-{
- //CheckMemoryDebugEvent(DEBUG_EVENT_READ,AT,PROCNUM,addr,8,0);
-
- //special handling for DMA: read 0 from TCM
- if(PROCNUM==ARMCPU_ARM9 && AT == MMU_AT_DMA)
- {
- if(addr<0x02000000) return 0; //itcm
- if((addr&(~0x3FFF)) == MMU.DTCMRegion) return 0; //dtcm
+// ALERT!!!!!!!!!!!!!!
+// the following inline functions dont do the 0x0FFFFFFF mask.
+// this may result in some unexpected behavior
+
+inline uint8_t _MMU_read08(int PROCNUM, MMU_ACCESS_TYPE AT, uint32_t addr)
+{
+ // special handling for DMA: read 0 from TCM
+ if (PROCNUM == ARMCPU_ARM9 && AT == MMU_AT_DMA)
+ {
+ if (addr < 0x02000000)
+ return 0; // itcm
+ if ((addr & ~0x3FFF) == MMU.DTCMRegion)
+ return 0; // dtcm
}
#ifdef HAVE_LUA
CallRegisteredLuaMemHook(addr, 1, /*FIXME*/ 0, LUAMEMHOOK_READ);
#endif
- if(PROCNUM==ARMCPU_ARM9)
- if((addr&(~0x3FFF)) == MMU.DTCMRegion)
- {
- //Returns data from DTCM (ARM9 only)
- return T1ReadByte(MMU.ARM9_DTCM, addr & 0x3FFF);
- }
-
- if ( (addr & 0x0F000000) == 0x02000000)
- return T1ReadByte( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK);
-
- if(PROCNUM==ARMCPU_ARM9) return _MMU_ARM9_read08(addr);
- else return _MMU_ARM7_read08(addr);
+ if (PROCNUM == ARMCPU_ARM9 && (addr & ~0x3FFF) == MMU.DTCMRegion)
+ // Returns data from DTCM (ARM9 only)
+ return T1ReadByte(MMU.ARM9_DTCM, addr & 0x3FFF);
+
+ if ((addr & 0x0F000000) == 0x02000000)
+ return T1ReadByte(MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK);
+
+ if (PROCNUM == ARMCPU_ARM9)
+ return _MMU_ARM9_read08(addr);
+ else
+ return _MMU_ARM7_read08(addr);
}
-inline uint16_t _MMU_read16(const int PROCNUM, const MMU_ACCESS_TYPE AT, const uint32_t addr)
-{
- //CheckMemoryDebugEvent(DEBUG_EVENT_READ,AT,PROCNUM,addr,16,0);
-
- //special handling for DMA: read 0 from TCM
- if(PROCNUM==ARMCPU_ARM9 && AT == MMU_AT_DMA)
- {
- if(addr<0x02000000) return 0; //itcm
- if((addr&(~0x3FFF)) == MMU.DTCMRegion) return 0; //dtcm
+inline uint16_t _MMU_read16(int PROCNUM, MMU_ACCESS_TYPE AT, uint32_t addr)
+{
+ // special handling for DMA: read 0 from TCM
+ if (PROCNUM == ARMCPU_ARM9 && AT == MMU_AT_DMA)
+ {
+ if (addr < 0x02000000)
+ return 0; // itcm
+ if ((addr & ~0x3FFF) == MMU.DTCMRegion)
+ return 0; // dtcm
}
#ifdef HAVE_LUA
CallRegisteredLuaMemHook(addr, 2, /*FIXME*/ 0, LUAMEMHOOK_READ);
#endif
- //special handling for execution from arm9, since we spend so much time in there
- if(PROCNUM==ARMCPU_ARM9 && AT == MMU_AT_CODE)
+ // special handling for execution from arm9, since we spend so much time in there
+ if (PROCNUM == ARMCPU_ARM9 && AT == MMU_AT_CODE)
{
if ((addr & 0x0F000000) == 0x02000000)
- return T1ReadWord_guaranteedAligned( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK16);
-
- if(addr<0x02000000)
+ return T1ReadWord_guaranteedAligned(MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK16);
+
+ if (addr < 0x02000000)
return T1ReadWord_guaranteedAligned(MMU.ARM9_ITCM, addr&0x7FFE);
goto dunno;
}
- if(PROCNUM==ARMCPU_ARM9)
- if((addr&(~0x3FFF)) == MMU.DTCMRegion)
- {
- //Returns data from DTCM (ARM9 only)
- return T1ReadWord_guaranteedAligned(MMU.ARM9_DTCM, addr & 0x3FFE);
- }
-
- if ( (addr & 0x0F000000) == 0x02000000)
- return T1ReadWord_guaranteedAligned( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK16);
+ if (PROCNUM == ARMCPU_ARM9 && (addr & ~0x3FFF) == MMU.DTCMRegion)
+ // Returns data from DTCM (ARM9 only)
+ return T1ReadWord_guaranteedAligned(MMU.ARM9_DTCM, addr & 0x3FFE);
+
+ if ((addr & 0x0F000000) == 0x02000000)
+ return T1ReadWord_guaranteedAligned(MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK16);
dunno:
- if(PROCNUM==ARMCPU_ARM9) return _MMU_ARM9_read16(addr);
- else return _MMU_ARM7_read16(addr);
+ if (PROCNUM == ARMCPU_ARM9)
+ return _MMU_ARM9_read16(addr);
+ else
+ return _MMU_ARM7_read16(addr);
}
-inline uint32_t _MMU_read32(const int PROCNUM, const MMU_ACCESS_TYPE AT, const uint32_t addr)
-{
- //CheckMemoryDebugEvent(DEBUG_EVENT_READ,AT,PROCNUM,addr,32,0);
-
- //special handling for DMA: read 0 from TCM
- if(PROCNUM==ARMCPU_ARM9 && AT == MMU_AT_DMA)
- {
- if(addr<0x02000000) return 0; //itcm
- if((addr&(~0x3FFF)) == MMU.DTCMRegion) return 0; //dtcm
+inline uint32_t _MMU_read32(int PROCNUM, MMU_ACCESS_TYPE AT, uint32_t addr)
+{
+ // special handling for DMA: read 0 from TCM
+ if (PROCNUM == ARMCPU_ARM9 && AT == MMU_AT_DMA)
+ {
+ if (addr < 0x02000000)
+ return 0; // itcm
+ if ((addr & ~0x3FFF) == MMU.DTCMRegion)
+ return 0; // dtcm
}
#ifdef HAVE_LUA
CallRegisteredLuaMemHook(addr, 4, /*FIXME*/ 0, LUAMEMHOOK_READ);
#endif
- //special handling for execution from arm9, since we spend so much time in there
- if(PROCNUM==ARMCPU_ARM9 && AT == MMU_AT_CODE)
- {
- if ( (addr & 0x0F000000) == 0x02000000)
- return T1ReadLong_guaranteedAligned( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK32);
-
- if(addr<0x02000000)
+ //s pecial handling for execution from arm9, since we spend so much time in there
+ if (PROCNUM == ARMCPU_ARM9 && AT == MMU_AT_CODE)
+ {
+ if ((addr & 0x0F000000) == 0x02000000)
+ return T1ReadLong_guaranteedAligned(MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK32);
+
+ if (addr < 0x02000000)
return T1ReadLong_guaranteedAligned(MMU.ARM9_ITCM, addr&0x7FFC);
- //what happens when we execute from DTCM? nocash makes it look like we get 0xFFFFFFFF but i can't seem to verify it
- //historically, desmume would fall through to its old memory map struct
- //which would return unused memory (0)
- //it seems the hardware returns 0 or something benign because in actuality 0xFFFFFFFF is an undefined opcode
- //and we know our handling for that is solid
+ // what happens when we execute from DTCM? nocash makes it look like we get 0xFFFFFFFF but i can't seem to verify it
+ // historically, desmume would fall through to its old memory map struct
+ // which would return unused memory (0)
+ // it seems the hardware returns 0 or something benign because in actuality 0xFFFFFFFF is an undefined opcode
+ // and we know our handling for that is solid
goto dunno;
}
- //special handling for execution from arm7. try reading from main memory first
- if(PROCNUM==ARMCPU_ARM7)
- {
- if ( (addr & 0x0F000000) == 0x02000000)
- return T1ReadLong_guaranteedAligned( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK32);
- else if((addr & 0xFF800000) == 0x03800000)
- return T1ReadLong_guaranteedAligned(MMU.ARM7_ERAM, addr&0xFFFC);
- else if((addr & 0xFF800000) == 0x03000000)
- return T1ReadLong_guaranteedAligned(MMU.SWIRAM, addr&0x7FFC);
- }
-
-
- //for other arm9 cases, we have to check from dtcm first because it is patched on top of the main memory range
- if(PROCNUM==ARMCPU_ARM9)
- {
- if((addr&(~0x3FFF)) == MMU.DTCMRegion)
- {
- //Returns data from DTCM (ARM9 only)
+ // special handling for execution from arm7. try reading from main memory first
+ if (PROCNUM == ARMCPU_ARM7 && (addr & 0x0F000000) == 0x02000000)
+ return T1ReadLong_guaranteedAligned(MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK32);
+
+ // for other arm9 cases, we have to check from dtcm first because it is patched on top of the main memory range
+ if (PROCNUM == ARMCPU_ARM9)
+ {
+ if ((addr & ~0x3FFF) == MMU.DTCMRegion)
+ // Returns data from DTCM (ARM9 only)
return T1ReadLong_guaranteedAligned(MMU.ARM9_DTCM, addr & 0x3FFC);
- }
-
- if ( (addr & 0x0F000000) == 0x02000000)
- return T1ReadLong_guaranteedAligned( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK32);
+
+ if ((addr & 0x0F000000) == 0x02000000)
+ return T1ReadLong_guaranteedAligned(MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK32);
}
dunno:
- if(PROCNUM==ARMCPU_ARM9) return _MMU_ARM9_read32(addr);
- else return _MMU_ARM7_read32(addr);
+ if (PROCNUM == ARMCPU_ARM9)
+ return _MMU_ARM9_read32(addr);
+ else
+ return _MMU_ARM7_read32(addr);
}
-inline void _MMU_write08(const int PROCNUM, const MMU_ACCESS_TYPE AT, const uint32_t addr, uint8_t val)
-{
- //CheckMemoryDebugEvent(DEBUG_EVENT_WRITE,AT,PROCNUM,addr,8,val);
-
- //special handling for DMA: discard writes to TCM
- if(PROCNUM==ARMCPU_ARM9 && AT == MMU_AT_DMA)
- {
- if(addr<0x02000000) return; //itcm
- if((addr&(~0x3FFF)) == MMU.DTCMRegion) return; //dtcm
- }
-
- if(PROCNUM==ARMCPU_ARM9)
- if((addr&(~0x3FFF)) == MMU.DTCMRegion)
- {
- T1WriteByte(MMU.ARM9_DTCM, addr & 0x3FFF, val);
-#ifdef HAVE_LUA
- CallRegisteredLuaMemHook(addr, 1, val, LUAMEMHOOK_WRITE);
-#endif
- return;
- }
-
- if ( (addr & 0x0F000000) == 0x02000000) {
+inline void _MMU_write08(int PROCNUM, MMU_ACCESS_TYPE AT, uint32_t addr, uint8_t val)
+{
+ // special handling for DMA: discard writes to TCM
+ if (PROCNUM == ARMCPU_ARM9 && AT == MMU_AT_DMA)
+ {
+ if (addr < 0x02000000)
+ return; // itcm
+ if ((addr & ~0x3FFF) == MMU.DTCMRegion)
+ return; // dtcm
+ }
+
+ if (PROCNUM == ARMCPU_ARM9 && (addr & ~0x3FFF) == MMU.DTCMRegion)
+ {
+ T1WriteByte(MMU.ARM9_DTCM, addr & 0x3FFF, val);
+#ifdef HAVE_LUA
+ CallRegisteredLuaMemHook(addr, 1, val, LUAMEMHOOK_WRITE);
+#endif
+ return;
+ }
+
+ if ((addr & 0x0F000000) == 0x02000000)
+ {
+#ifdef HAVE_JIT
+ JIT_COMPILED_FUNC_KNOWNBANK(addr, MAIN_MEM, _MMU_MAIN_MEM_MASK, 0) = 0;
+#endif
T1WriteByte( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK, val);
#ifdef HAVE_LUA
CallRegisteredLuaMemHook(addr, 1, val, LUAMEMHOOK_WRITE);
@@ -804,35 +707,40 @@
return;
}
- if(PROCNUM==ARMCPU_ARM9) _MMU_ARM9_write08(addr,val);
- else _MMU_ARM7_write08(addr,val);
+ if (PROCNUM == ARMCPU_ARM9)
+ _MMU_ARM9_write08(addr, val);
+ else
+ _MMU_ARM7_write08(addr, val);
#ifdef HAVE_LUA
CallRegisteredLuaMemHook(addr, 1, val, LUAMEMHOOK_WRITE);
#endif
}
-inline void _MMU_write16(const int PROCNUM, const MMU_ACCESS_TYPE AT, const uint32_t addr, uint16_t val)
-{
- //CheckMemoryDebugEvent(DEBUG_EVENT_WRITE,AT,PROCNUM,addr,16,val);
-
- //special handling for DMA: discard writes to TCM
- if(PROCNUM==ARMCPU_ARM9 && AT == MMU_AT_DMA)
- {
- if(addr<0x02000000) return; //itcm
- if((addr&(~0x3FFF)) == MMU.DTCMRegion) return; //dtcm
- }
-
- if(PROCNUM==ARMCPU_ARM9)
- if((addr&(~0x3FFF)) == MMU.DTCMRegion)
- {
- T1WriteWord(MMU.ARM9_DTCM, addr & 0x3FFE, val);
-#ifdef HAVE_LUA
- CallRegisteredLuaMemHook(addr, 2, val, LUAMEMHOOK_WRITE);
-#endif
- return;
- }
-
- if ( (addr & 0x0F000000) == 0x02000000) {
+inline void _MMU_write16(int PROCNUM, MMU_ACCESS_TYPE AT, uint32_t addr, uint16_t val)
+{
+ // special handling for DMA: discard writes to TCM
+ if (PROCNUM == ARMCPU_ARM9 && AT == MMU_AT_DMA)
+ {
+ if (addr < 0x02000000)
+ return; // itcm
+ if ((addr & ~0x3FFF) == MMU.DTCMRegion)
+ return; // dtcm
+ }
+
+ if (PROCNUM == ARMCPU_ARM9 && (addr & ~0x3FFF) == MMU.DTCMRegion)
+ {
+ T1WriteWord(MMU.ARM9_DTCM, addr & 0x3FFE, val);
+#ifdef HAVE_LUA
+ CallRegisteredLuaMemHook(addr, 2, val, LUAMEMHOOK_WRITE);
+#endif
+ return;
+ }
+
+ if ((addr & 0x0F000000) == 0x02000000)
+ {
+#ifdef HAVE_JIT
+ JIT_COMPILED_FUNC_KNOWNBANK(addr, MAIN_MEM, _MMU_MAIN_MEM_MASK16, 0) = 0;
+#endif
T1WriteWord( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK16, val);
#ifdef HAVE_LUA
CallRegisteredLuaMemHook(addr, 2, val, LUAMEMHOOK_WRITE);
@@ -840,35 +748,41 @@
return;
}
- if(PROCNUM==ARMCPU_ARM9) _MMU_ARM9_write16(addr,val);
- else _MMU_ARM7_write16(addr,val);
+ if (PROCNUM == ARMCPU_ARM9)
+ _MMU_ARM9_write16(addr, val);
+ else
+ _MMU_ARM7_write16(addr, val);
#ifdef HAVE_LUA
CallRegisteredLuaMemHook(addr, 2, val, LUAMEMHOOK_WRITE);
#endif
}
-inline void _MMU_write32(const int PROCNUM, const MMU_ACCESS_TYPE AT, const uint32_t addr, uint32_t val)
-{
- //CheckMemoryDebugEvent(DEBUG_EVENT_WRITE,AT,PROCNUM,addr,32,val);
-
- //special handling for DMA: discard writes to TCM
- if(PROCNUM==ARMCPU_ARM9 && AT == MMU_AT_DMA)
- {
- if(addr<0x02000000) return; //itcm
- if((addr&(~0x3FFF)) == MMU.DTCMRegion) return; //dtcm
- }
-
- if(PROCNUM==ARMCPU_ARM9)
- if((addr&(~0x3FFF)) == MMU.DTCMRegion)
- {
- T1WriteLong(MMU.ARM9_DTCM, addr & 0x3FFC, val);
-#ifdef HAVE_LUA
- CallRegisteredLuaMemHook(addr, 4, val, LUAMEMHOOK_WRITE);
-#endif
- return;
- }
-
- if ( (addr & 0x0F000000) == 0x02000000) {
+inline void _MMU_write32(int PROCNUM, MMU_ACCESS_TYPE AT, uint32_t addr, uint32_t val)
+{
+ // special handling for DMA: discard writes to TCM
+ if (PROCNUM == ARMCPU_ARM9 && AT == MMU_AT_DMA)
+ {
+ if (addr < 0x02000000)
+ return; // itcm
+ if ((addr & ~0x3FFF) == MMU.DTCMRegion)
+ return; // dtcm
+ }
+
+ if (PROCNUM == ARMCPU_ARM9 && (addr & ~0x3FFF) == MMU.DTCMRegion)
+ {
+ T1WriteLong(MMU.ARM9_DTCM, addr & 0x3FFC, val);
+#ifdef HAVE_LUA
+ CallRegisteredLuaMemHook(addr, 4, val, LUAMEMHOOK_WRITE);
+#endif
+ return;
+ }
+
+ if ((addr & 0x0F000000) == 0x02000000)
+ {
+#ifdef HAVE_JIT
+ JIT_COMPILED_FUNC_KNOWNBANK(addr, MAIN_MEM, _MMU_MAIN_MEM_MASK32, 0) = 0;
+ JIT_COMPILED_FUNC_KNOWNBANK(addr, MAIN_MEM, _MMU_MAIN_MEM_MASK32, 1) = 0;
+#endif
T1WriteLong( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK32, val);
#ifdef HAVE_LUA
CallRegisteredLuaMemHook(addr, 4, val, LUAMEMHOOK_WRITE);
@@ -876,66 +790,28 @@
return;
}
- if(PROCNUM==ARMCPU_ARM9) _MMU_ARM9_write32(addr,val);
- else _MMU_ARM7_write32(addr,val);
+ if (PROCNUM == ARMCPU_ARM9)
+ _MMU_ARM9_write32(addr, val);
+ else
+ _MMU_ARM7_write32(addr, val);
#ifdef HAVE_LUA
CallRegisteredLuaMemHook(addr, 4, val, LUAMEMHOOK_WRITE);
#endif
}
-
-//#ifdef MMU_ENABLE_ACL
-// void FASTCALL MMU_write8_acl(uint32_t proc, uint32_t adr, uint8_t val);
-// void FASTCALL MMU_write16_acl(uint32_t proc, uint32_t adr, uint16_t val);
-// void FASTCALL MMU_write32_acl(uint32_t proc, uint32_t adr, uint32_t val);
-// uint8_t FASTCALL MMU_read8_acl(uint32_t proc, uint32_t adr, uint32_t access);
-// uint16_t FASTCALL MMU_read16_acl(uint32_t proc, uint32_t adr, uint32_t access);
-// uint32_t FASTCALL MMU_read32_acl(uint32_t proc, uint32_t adr, uint32_t access);
-//#else
-// #define MMU_write8_acl(proc, adr, val) _MMU_write08<proc>(adr, val)
-// #define MMU_write16_acl(proc, adr, val) _MMU_write16<proc>(adr, val)
-// #define MMU_write32_acl(proc, adr, val) _MMU_write32<proc>(adr, val)
-// #define MMU_read8_acl(proc,adr,access) _MMU_read08<proc>(adr)
-// #define MMU_read16_acl(proc,adr,access) ((access==CP15_ACCESS_EXECUTE)?_MMU_read16<proc,MMU_AT_CODE>(adr):_MMU_read16<proc,MMU_AT_DATA>(adr))
-// #define MMU_read32_acl(proc,adr,access) ((access==CP15_ACCESS_EXECUTE)?_MMU_read32<proc,MMU_AT_CODE>(adr):_MMU_read32<proc,MMU_AT_DATA>(adr))
-//#endif
-
-// Use this macros for reading/writing, so the GDB stub isn't broken
-#ifdef GDB_STUB
- #define READ32(a,b) cpu->mem_if->read32(a,(b) & 0xFFFFFFFC)
- #define WRITE32(a,b,c) cpu->mem_if->write32(a,(b) & 0xFFFFFFFC,c)
- #define READ16(a,b) cpu->mem_if->read16(a,(b) & 0xFFFFFFFE)
- #define WRITE16(a,b,c) cpu->mem_if->write16(a,(b) & 0xFFFFFFFE,c)
- #define READ8(a,b) cpu->mem_if->read8(a,b)
- #define WRITE8(a,b,c) cpu->mem_if->write8(a,b,c)
-#else
- #define READ32(a,b) _MMU_read32<PROCNUM>((b) & 0xFFFFFFFC)
- #define WRITE32(a,b,c) _MMU_write32<PROCNUM>((b) & 0xFFFFFFFC,c)
- #define READ16(a,b) _MMU_read16<PROCNUM>((b) & 0xFFFFFFFE)
- #define WRITE16(a,b,c) _MMU_write16<PROCNUM>((b) & 0xFFFFFFFE,c)
- #define READ8(a,b) _MMU_read08<PROCNUM>(b)
- #define WRITE8(a,b,c) _MMU_write08<PROCNUM>(b, c)
-#endif
-
-template<int PROCNUM, MMU_ACCESS_TYPE AT>
-inline uint8_t _MMU_read08(uint32_t addr) { return _MMU_read08(PROCNUM, AT, addr); }
-
-template<int PROCNUM, MMU_ACCESS_TYPE AT>
-inline uint16_t _MMU_read16(uint32_t addr) { return _MMU_read16(PROCNUM, AT, addr); }
-
-template<int PROCNUM, MMU_ACCESS_TYPE AT>
-inline uint32_t _MMU_read32(uint32_t addr) { return _MMU_read32(PROCNUM, AT, addr); }
-
-template<int PROCNUM, MMU_ACCESS_TYPE AT>
-inline void _MMU_write08(uint32_t addr, uint8_t val) { _MMU_write08(PROCNUM, AT, addr, val); }
-
-template<int PROCNUM, MMU_ACCESS_TYPE AT>
-inline void _MMU_write16(uint32_t addr, uint16_t val) { _MMU_write16(PROCNUM, AT, addr, val); }
-
-template<int PROCNUM, MMU_ACCESS_TYPE AT>
-inline void _MMU_write32(uint32_t addr, uint32_t val) { _MMU_write32(PROCNUM, AT, addr, val); }
-
-//void FASTCALL MMU_DumpMemBlock(uint8_t proc, uint32_t address, uint32_t size, uint8_t *buffer);
-
-#endif
-
+#define READ32(a,b) _MMU_read32<PROCNUM>((b) & 0xFFFFFFFC)
+#define WRITE32(a,b,c) _MMU_write32<PROCNUM>((b) & 0xFFFFFFFC,c)
+#define READ16(a,b) _MMU_read16<PROCNUM>((b) & 0xFFFFFFFE)
+#define WRITE16(a,b,c) _MMU_write16<PROCNUM>((b) & 0xFFFFFFFE,c)
+#define READ8(a,b) _MMU_read08<PROCNUM>(b)
+#define WRITE8(a,b,c) _MMU_write08<PROCNUM>(b, c)
+
+template<int PROCNUM, MMU_ACCESS_TYPE AT> inline uint8_t _MMU_read08(uint32_t addr) { return _MMU_read08(PROCNUM, AT, addr); }
+template<int PROCNUM, MMU_ACCESS_TYPE AT> inline uint16_t _MMU_read16(uint32_t addr) { return _MMU_read16(PROCNUM, AT, addr); }
+template<int PROCNUM, MMU_ACCESS_TYPE AT> inline uint32_t _MMU_read32(uint32_t addr) { return _MMU_read32(PROCNUM, AT, addr); }
+template<int PROCNUM, MMU_ACCESS_TYPE AT> inline void _MMU_write08(uint32_t addr, uint8_t val) { _MMU_write08(PROCNUM, AT, addr, val); }
+template<int PROCNUM, MMU_ACCESS_TYPE AT> inline void _MMU_write16(uint32_t addr, uint16_t val) { _MMU_write16(PROCNUM, AT, addr, val); }
+template<int PROCNUM, MMU_ACCESS_TYPE AT> inline void _MMU_write32(uint32_t addr, uint32_t val) { _MMU_write32(PROCNUM, AT, addr, val); }
+
+#endif
+
--- a/src/in_2sf/desmume/MMU_timing.h
+++ b/src/in_2sf/desmume/MMU_timing.h
@@ -19,12 +19,12 @@
// this file is split from MMU.h for the purpose of avoiding ridiculous recompile times
// when changing it, because practically everything includes MMU.h.
+
#ifndef MMUTIMING_H
#define MMUTIMING_H
#include <algorithm>
#include <cmath>
-
#include "MMU.h"
#include "cp15.h"
#include "readwrite.h"
@@ -40,21 +40,21 @@
// obviously, these defines don't cover all the variables or features needed,
// and in particular, DMA or code+data access bus contention is still missing.
- //disable this to prevent the advanced timing logic from ever running at all
+// disable this to prevent the advanced timing logic from ever running at all
//#define ENABLE_ADVANCED_TIMING
#ifdef ENABLE_ADVANCED_TIMING
- // makes non-sequential accesses slower than sequential ones.
+// makes non-sequential accesses slower than sequential ones.
#define ACCOUNT_FOR_NON_SEQUENTIAL_ACCESS
- //(SOMETIMES THIS IS A BIG SPEED HIT!)
-
- // enables emulation of code fetch waits.
+// (SOMETIMES THIS IS A BIG SPEED HIT!)
+
+// enables emulation of code fetch waits.
#define ACCOUNT_FOR_CODE_FETCH_CYCLES
- // makes access to DTCM (arm9 only) fast.
+// makes access to DTCM (arm9 only) fast.
#define ACCOUNT_FOR_DATA_TCM_SPEED
- // enables simulation of cache hits and cache misses.
+// enables simulation of cache hits and cache misses.
#define ENABLE_CACHE_CONTROLLER_EMULATION
#endif //ENABLE_ADVANCED_TIMING
@@ -62,7 +62,8 @@
//
////////////////////////////////////////////////////////////////
-inline bool USE_TIMING() {
+inline bool USE_TIMING()
+{
#ifdef ENABLE_ADVANCED_TIMING
return CommonSettings.advanced_timing;
#else
@@ -70,25 +71,21 @@
#endif
}
-
enum MMU_ACCESS_DIRECTION
{
MMU_AD_READ, MMU_AD_WRITE
};
-
// note that we don't actually emulate the cache contents here,
// only enough to guess what would be a cache hit or a cache miss.
// this doesn't really get used unless ENABLE_CACHE_CONTROLLER_EMULATION is defined.
-template<int SIZESHIFT, int ASSOCIATIVESHIFT, int BLOCKSIZESHIFT>
-class CacheController
+template<int SIZESHIFT, int ASSOCIATIVESHIFT, int BLOCKSIZESHIFT> class CacheController
{
public:
- template<MMU_ACCESS_DIRECTION DIR>
- inline bool Cached(uint32_t addr)
+ template<MMU_ACCESS_DIRECTION DIR> bool Cached(uint32_t addr)
{
uint32_t blockMasked = addr & BLOCKMASK;
- if(blockMasked == m_cacheCache)
+ if (blockMasked == this->m_cacheCache)
return true;
else
return this->CachedInternal<DIR>(addr, blockMasked);
@@ -96,58 +93,35 @@
void Reset()
{
- for(int blockIndex = 0; blockIndex < NUMBLOCKS; blockIndex++)
- m_blocks[blockIndex].Reset();
- m_cacheCache = ~0;
+ for (int blockIndex = 0; blockIndex < NUMBLOCKS; ++blockIndex)
+ this->m_blocks[blockIndex].Reset();
+ this->m_cacheCache = ~0;
}
CacheController()
{
- Reset();
- }
-
- /*void savestate(EMUFILE* os, int)
- {
- write32le(m_cacheCache, os);
- for(int i = 0; i < NUMBLOCKS; i++)
- {
- for(int j = 0; j < ASSOCIATIVITY; j++)
- write32le(m_blocks[i].tag[j],os);
- write32le(m_blocks[i].nextWay,os);
- }
- }*/
- bool loadstate(EMUFILE* is, int)
- {
- read32le(&m_cacheCache, is);
- for(int i = 0; i < NUMBLOCKS; i++)
- {
- for(int j = 0; j < ASSOCIATIVITY; j++)
- read32le(&m_blocks[i].tag[j],is);
- read32le(&m_blocks[i].nextWay,is);
- }
- return true;
+ this->Reset();
}
private:
- template<MMU_ACCESS_DIRECTION DIR>
- bool CachedInternal(uint32_t addr, uint32_t blockMasked)
+ template<MMU_ACCESS_DIRECTION DIR> bool CachedInternal(uint32_t addr, uint32_t blockMasked)
{
uint32_t blockIndex = blockMasked >> BLOCKSIZESHIFT;
- CacheBlock& block = m_blocks[blockIndex];
+ CacheBlock &block = this->m_blocks[blockIndex];
addr &= TAGMASK;
- for(int way = 0; way < ASSOCIATIVITY; way++)
- if(addr == block.tag[way])
+ for (int way = 0; way < ASSOCIATIVITY; ++way)
+ if (addr == block.tag[way])
{
// found it, already allocated
- m_cacheCache = blockMasked;
+ this->m_cacheCache = blockMasked;
return true;
}
- if(DIR == MMU_AD_READ)
+ if (DIR == MMU_AD_READ)
{
// TODO: support other allocation orders?
block.tag[block.nextWay++] = addr;
block.nextWay %= ASSOCIATIVITY;
- m_cacheCache = blockMasked;
+ this->m_cacheCache = blockMasked;
}
return false;
}
@@ -156,8 +130,8 @@
enum { ASSOCIATIVITY = 1 << ASSOCIATIVESHIFT };
enum { BLOCKSIZE = 1 << BLOCKSIZESHIFT };
enum { TAGSHIFT = SIZESHIFT - ASSOCIATIVESHIFT };
- enum { TAGMASK = (uint32_t)(~0 << TAGSHIFT) };
- enum { BLOCKMASK = ((uint32_t)~0 >> (32 - TAGSHIFT)) & (uint32_t)(~0 << BLOCKSIZESHIFT) };
+ enum { TAGMASK = static_cast<uint32_t>(~0 << TAGSHIFT) };
+ enum { BLOCKMASK = (static_cast<uint32_t>(~0) >> (32 - TAGSHIFT)) & static_cast<uint32_t>(~0 << BLOCKSIZESHIFT) };
enum { WORDSIZE = sizeof(uint32_t) };
enum { WORDSPERBLOCK = (1 << BLOCKSIZESHIFT) / WORDSIZE };
enum { DATAPERWORD = WORDSIZE * ASSOCIATIVITY };
@@ -166,58 +140,48 @@
struct CacheBlock
{
- uint32_t tag [ASSOCIATIVITY];
+ uint32_t tag[ASSOCIATIVITY];
uint32_t nextWay;
void Reset()
{
- nextWay = 0;
- for(int way = 0; way < ASSOCIATIVITY; way++)
- tag[way] = 0;
+ this->nextWay = 0;
+ for (int way = 0; way < ASSOCIATIVITY; ++way)
+ this->tag[way] = 0;
}
};
uint32_t m_cacheCache; // optimization
- CacheBlock m_blocks [NUMBLOCKS];
+ CacheBlock m_blocks[NUMBLOCKS];
};
-
-template<int PROCNUM, MMU_ACCESS_TYPE AT, int READSIZE, MMU_ACCESS_DIRECTION DIRECTION, bool TIMING>
-inline uint32_t _MMU_accesstime(uint32_t addr, bool sequential);
-
-
-template<int PROCNUM, MMU_ACCESS_TYPE AT>
-class FetchAccessUnit
+template<int PROCNUM, MMU_ACCESS_TYPE AT, int READSIZE, MMU_ACCESS_DIRECTION DIRECTION, bool TIMING> inline uint32_t _MMU_accesstime(uint32_t addr, bool sequential);
+
+template<int PROCNUM, MMU_ACCESS_TYPE AT> class FetchAccessUnit
{
public:
- template<int READSIZE, MMU_ACCESS_DIRECTION DIRECTION, bool TIMING>
- inline uint32_t Fetch(uint32_t address)
- {
- #ifdef ACCOUNT_FOR_CODE_FETCH_CYCLES
- const bool prohibit = TIMING;
- #else
- const bool prohibit = false;
- #endif
-
- if(AT == MMU_AT_CODE && !prohibit)
- {
+ template<int READSIZE, MMU_ACCESS_DIRECTION DIRECTION, bool TIMING> uint32_t Fetch(uint32_t address)
+ {
+#ifdef ACCOUNT_FOR_CODE_FETCH_CYCLES
+ bool prohibit = TIMING;
+#else
+ bool prohibit = false;
+#endif
+
+ if (AT == MMU_AT_CODE && !prohibit)
return 1;
- }
uint32_t time = _MMU_accesstime<PROCNUM, AT, READSIZE, DIRECTION,TIMING>(address,
#ifdef ACCOUNT_FOR_NON_SEQUENTIAL_ACCESS
- (TIMING?
- (address == (m_lastAddress + (READSIZE>>3)))
- :true
- )
+ TIMING ? (address == m_lastAddress + (READSIZE >> 3)) : true
#else
true
#endif
);
#ifdef ACCOUNT_FOR_NON_SEQUENTIAL_ACCESS
- m_lastAddress = address;
+ this->m_lastAddress = address;
#endif
return time;
@@ -225,98 +189,81 @@
void Reset()
{
- m_lastAddress = ~0;
- }
- FetchAccessUnit() { this->Reset(); }
-
- /*void savestate(EMUFILE* os, int)
- {
- write32le(m_lastAddress,os);
- }*/
- bool loadstate(EMUFILE* is, int)
- {
- read32le(&m_lastAddress,is);
- return true;
+ this->m_lastAddress = ~0;
+ }
+ FetchAccessUnit()
+ {
+ this->Reset();
}
private:
uint32_t m_lastAddress;
};
-
-
-
-
struct MMU_struct_timing
{
// technically part of the cp15, but I didn't want the dereferencing penalty.
// these template values correspond with the value of armcp15->cacheType.
- CacheController<13,2,5> arm9codeCache; // 8192 bytes, 4-way associative, 32-byte blocks
- CacheController<12,2,5> arm9dataCache; // 4096 bytes, 4-way associative, 32-byte blocks
+ CacheController<13, 2, 5> arm9codeCache; // 8192 bytes, 4-way associative, 32-byte blocks
+ CacheController<12, 2, 5> arm9dataCache; // 4096 bytes, 4-way associative, 32-byte blocks
// technically part of armcpu_t, but that struct isn't templated on PROCNUM
- FetchAccessUnit<0,MMU_AT_CODE> arm9codeFetch;
- FetchAccessUnit<0,MMU_AT_DATA> arm9dataFetch;
- FetchAccessUnit<1,MMU_AT_CODE> arm7codeFetch;
- FetchAccessUnit<1,MMU_AT_DATA> arm7dataFetch;
-
- template<int PROCNUM> inline FetchAccessUnit<PROCNUM,MMU_AT_CODE>& armCodeFetch();
- template<int PROCNUM> inline FetchAccessUnit<PROCNUM,MMU_AT_DATA>& armDataFetch();
+ FetchAccessUnit<0, MMU_AT_CODE> arm9codeFetch;
+ FetchAccessUnit<0, MMU_AT_DATA> arm9dataFetch;
+ FetchAccessUnit<1, MMU_AT_CODE> arm7codeFetch;
+ FetchAccessUnit<1, MMU_AT_DATA> arm7dataFetch;
+
+ template<int PROCNUM> FetchAccessUnit<PROCNUM, MMU_AT_CODE> &armCodeFetch();
+ template<int PROCNUM> FetchAccessUnit<PROCNUM, MMU_AT_DATA> &armDataFetch();
};
-template<> inline FetchAccessUnit<0,MMU_AT_CODE>& MMU_struct_timing::armCodeFetch<0>() { return this->arm9codeFetch; }
-template<> inline FetchAccessUnit<1,MMU_AT_CODE>& MMU_struct_timing::armCodeFetch<1>() { return this->arm7codeFetch; }
-template<> inline FetchAccessUnit<0,MMU_AT_DATA>& MMU_struct_timing::armDataFetch<0>() { return this->arm9dataFetch; }
-template<> inline FetchAccessUnit<1,MMU_AT_DATA>& MMU_struct_timing::armDataFetch<1>() { return this->arm7dataFetch; }
-
+template<> inline FetchAccessUnit<0, MMU_AT_CODE> &MMU_struct_timing::armCodeFetch<0>() { return this->arm9codeFetch; }
+template<> inline FetchAccessUnit<1, MMU_AT_CODE> &MMU_struct_timing::armCodeFetch<1>() { return this->arm7codeFetch; }
+template<> inline FetchAccessUnit<0, MMU_AT_DATA> &MMU_struct_timing::armDataFetch<0>() { return this->arm9dataFetch; }
+template<> inline FetchAccessUnit<1, MMU_AT_DATA> &MMU_struct_timing::armDataFetch<1>() { return this->arm7dataFetch; }
extern MMU_struct_timing MMU_timing;
-
-
// calculates the time a single memory access takes,
// in units of cycles of the current processor.
// this function replaces what used to be MMU_WAIT16 and MMU_WAIT32.
// this may have side effects, so don't call it more than necessary.
-template<int PROCNUM, MMU_ACCESS_TYPE AT, int READSIZE, MMU_ACCESS_DIRECTION DIRECTION, bool TIMING>
-inline uint32_t _MMU_accesstime(uint32_t addr, bool sequential)
+template<int PROCNUM, MMU_ACCESS_TYPE AT, int READSIZE, MMU_ACCESS_DIRECTION DIRECTION, bool TIMING> inline uint32_t _MMU_accesstime(uint32_t addr, bool sequential)
{
static const int MC = 1; // cached or tcm memory speed
- static const int M32 = (PROCNUM==ARMCPU_ARM9) ? 2 : 1; // access through 32-bit bus
- static const int M16 = M32 * ((READSIZE>16) ? 2 : 1); // access through 16-bit bus
+ static const int M32 = PROCNUM == ARMCPU_ARM9 ? 2 : 1; // access through 32-bit bus
+ static const int M16 = M32 * (READSIZE > 16 ? 2 : 1); // access through 16-bit bus
static const int MSLW = M16 * 8; // this needs tuning
- if(PROCNUM==ARMCPU_ARM9 && AT == MMU_AT_CODE && addr < 0x02000000)
+ if (PROCNUM == ARMCPU_ARM9 && AT == MMU_AT_CODE && addr < 0x02000000)
return MC; // ITCM
#ifdef ACCOUNT_FOR_DATA_TCM_SPEED
- if(TIMING && PROCNUM==ARMCPU_ARM9 && AT==MMU_AT_DATA && (addr&(~0x3FFF)) == MMU.DTCMRegion)
+ if (TIMING && PROCNUM == ARMCPU_ARM9 && AT == MMU_AT_DATA && (addr & ~0x3FFF) == MMU.DTCMRegion)
return MC; // DTCM
#endif
// for now, assume the cache is always enabled for all of main memory
- if(AT != MMU_AT_DMA && TIMING && PROCNUM==ARMCPU_ARM9 && (addr & 0x0F000000) == 0x02000000)
+ if (AT != MMU_AT_DMA && TIMING && PROCNUM == ARMCPU_ARM9 && (addr & 0x0F000000) == 0x02000000)
{
#ifdef ENABLE_CACHE_CONTROLLER_EMULATION
bool cached = false;
- if(AT==MMU_AT_CODE)
+ if (AT == MMU_AT_CODE)
cached = MMU_timing.arm9codeCache.Cached<DIRECTION>(addr);
- if(AT==MMU_AT_DATA)
+ if (AT == MMU_AT_DATA)
cached = MMU_timing.arm9dataCache.Cached<DIRECTION>(addr);
- if(cached)
+ if (cached)
return MC;
uint32_t c;
- if(sequential && AT==MMU_AT_DATA)
+ if (sequential && AT == MMU_AT_DATA)
c = M16; // bonus for sequential data access
- else if(DIRECTION == MMU_AD_READ)
+ else if (DIRECTION == MMU_AD_READ)
c = M16 * 5;
else
c = M16 * 2; // should be 4, but write buffer isn't emulated yet.
- if(DIRECTION == MMU_AD_READ)
- {
+ if (DIRECTION == MMU_AD_READ)
// cache miss while reading means it has to fill a whole cache line
// by reading 32 bytes...
- c += 8 * M32*2;
- }
+ c += 8 * M32 * 2;
return c;
#elif defined(ACCOUNT_FOR_NON_SEQUENTIAL_ACCESS)
// this is the closest approximation I could find
@@ -326,99 +273,88 @@
#endif
}
- static const TWaitState MMU_WAIT[16*16] = {
- // ITCM, ITCM, MAIN, SWI, REG, VMEM, LCD, OAM, ROM, ROM, RAM, U, U, U, U, BIOS
+ static const TWaitState MMU_WAIT[] =
+ {
+ // ITCM, ITCM, MAIN, SWI, REG, VMEM, LCD, OAM, ROM, ROM, RAM, U, U, U, U, BIOS
#define X MC, MC, M16, M32, M32, M16, M16, M32, MSLW, MSLW, MSLW, M32,M32,M32,M32, M32,
// duplicate it 16 times (this was somehow faster than using a mask of 0xF)
X X X X X X X X X X X X X X X X
#undef X
};
- uint32_t c = MMU_WAIT[(addr >> 24)];
+ uint32_t c = MMU_WAIT[addr >> 24];
#ifdef ACCOUNT_FOR_NON_SEQUENTIAL_ACCESS
- if(TIMING && !sequential)
+ if (TIMING && !sequential)
{
//if(c != MC || PROCNUM==ARMCPU_ARM7) // check not needed anymore because ITCM/DTCM return earlier
{
- c += (PROCNUM==ARMCPU_ARM9) ? 3*2 : 1;
+ c += PROCNUM == ARMCPU_ARM9 ? 6 : 1;
}
}
#endif
return c;
}
-
-
-
-
// calculates the cycle time of a single memory access in the MEM stage.
// to be used to calculate the memCycles argument for MMU_aluMemCycles.
// this may have side effects, so don't call it more than necessary.
-template<int PROCNUM, int READSIZE, MMU_ACCESS_DIRECTION DIRECTION, bool TIMING>
-inline uint32_t MMU_memAccessCycles(uint32_t addr)
-{
- if(TIMING)
- return MMU_timing.armDataFetch<PROCNUM>().template Fetch<READSIZE,DIRECTION,true>((addr)&(~((READSIZE>>3)-1)));
- else
- return MMU_timing.armDataFetch<PROCNUM>().template Fetch<READSIZE,DIRECTION,false>((addr)&(~((READSIZE>>3)-1)));
-}
-
-template<int PROCNUM, int READSIZE, MMU_ACCESS_DIRECTION DIRECTION>
-inline uint32_t MMU_memAccessCycles(uint32_t addr)
-{
- if(USE_TIMING())
- return MMU_memAccessCycles<PROCNUM,READSIZE,DIRECTION,true>(addr);
- else
- return MMU_memAccessCycles<PROCNUM,READSIZE,DIRECTION,false>(addr);
+template<int PROCNUM, int READSIZE, MMU_ACCESS_DIRECTION DIRECTION, bool TIMING> inline uint32_t MMU_memAccessCycles(uint32_t addr)
+{
+ if (TIMING)
+ return MMU_timing.armDataFetch<PROCNUM>().template Fetch<READSIZE, DIRECTION, true>(addr & (~((READSIZE >> 3) - 1)));
+ else
+ return MMU_timing.armDataFetch<PROCNUM>().template Fetch<READSIZE, DIRECTION, false>(addr & (~((READSIZE >> 3) - 1)));
+}
+
+template<int PROCNUM, int READSIZE, MMU_ACCESS_DIRECTION DIRECTION> inline uint32_t MMU_memAccessCycles(uint32_t addr)
+{
+ if (USE_TIMING())
+ return MMU_memAccessCycles<PROCNUM, READSIZE, DIRECTION, true>(addr);
+ else
+ return MMU_memAccessCycles<PROCNUM, READSIZE, DIRECTION, false>(addr);
}
// calculates the cycle time of a single code fetch in the FETCH stage
// to be used to calculate the fetchCycles argument for MMU_fetchExecuteCycles.
// this may have side effects, so don't call it more than necessary.
-template<int PROCNUM, int READSIZE>
-inline uint32_t MMU_codeFetchCycles(uint32_t addr)
-{
- if(USE_TIMING())
- return MMU_timing.armCodeFetch<PROCNUM>().template Fetch<READSIZE,MMU_AD_READ,true>((addr)&(~((READSIZE>>3)-1)));
- else
- return MMU_timing.armCodeFetch<PROCNUM>().template Fetch<READSIZE,MMU_AD_READ,false>((addr)&(~((READSIZE>>3)-1)));
+template<int PROCNUM, int READSIZE> inline uint32_t MMU_codeFetchCycles(uint32_t addr)
+{
+ if (USE_TIMING())
+ return MMU_timing.armCodeFetch<PROCNUM>().template Fetch<READSIZE, MMU_AD_READ, true>(addr & (~((READSIZE >> 3) - 1)));
+ else
+ return MMU_timing.armCodeFetch<PROCNUM>().template Fetch<READSIZE, MMU_AD_READ, false>(addr & (~((READSIZE >> 3) - 1)));
}
// calculates the cycle contribution of ALU + MEM stages (= EXECUTE)
// given ALU cycle time and the summation of multiple memory access cycle times.
// this function might belong more in armcpu, but I don't think it matters.
-template<int PROCNUM>
-inline uint32_t MMU_aluMemCycles(uint32_t aluCycles, uint32_t memCycles)
-{
- if(PROCNUM==ARMCPU_ARM9)
- {
+template<int PROCNUM> inline uint32_t MMU_aluMemCycles(uint32_t aluCycles, uint32_t memCycles)
+{
+ if (PROCNUM == ARMCPU_ARM9)
// ALU and MEM are different stages of the 5-stage pipeline.
// we approximate the pipeline throughput using max,
// since simply adding the cycles of each instruction together
// fails to take into account the parallelism of the arm pipeline
// and would make the emulated system unnaturally slow.
return std::max(aluCycles, memCycles);
- }
- else
- {
+ else
// ALU and MEM are part of the same stage of the 3-stage pipeline,
// thus they occur in sequence and we can simply add the counts together.
return aluCycles + memCycles;
- }
}
// calculates the cycle contribution of ALU + MEM stages (= EXECUTE)
// given ALU cycle time and the description of a single memory access.
// this may have side effects, so don't call it more than necessary.
-template<int PROCNUM, int READSIZE, MMU_ACCESS_DIRECTION DIRECTION>
-inline uint32_t MMU_aluMemAccessCycles(uint32_t aluCycles, uint32_t addr)
+template<int PROCNUM, int READSIZE, MMU_ACCESS_DIRECTION DIRECTION> inline uint32_t MMU_aluMemAccessCycles(uint32_t aluCycles, uint32_t addr)
{
uint32_t memCycles;
- if(USE_TIMING())
- memCycles = MMU_memAccessCycles<PROCNUM,READSIZE,DIRECTION,true>(addr);
- else memCycles = MMU_memAccessCycles<PROCNUM,READSIZE,DIRECTION,false>(addr);
+ if (USE_TIMING())
+ memCycles = MMU_memAccessCycles<PROCNUM, READSIZE, DIRECTION, true>(addr);
+ else
+ memCycles = MMU_memAccessCycles<PROCNUM, READSIZE, DIRECTION, false>(addr);
return MMU_aluMemCycles<PROCNUM>(aluCycles, memCycles);
}
@@ -426,16 +362,15 @@
// given executeCycles = the combined ALU+MEM cycles
// and fetchCycles = the cycle time of the FETCH stage
// this function might belong more in armcpu, but I don't think it matters.
-template<int PROCNUM>
-inline uint32_t MMU_fetchExecuteCycles(uint32_t executeCycles, uint32_t fetchCycles)
-{
- #ifdef ACCOUNT_FOR_CODE_FETCH_CYCLES
- const bool allow = true;
- #else
- const bool allow = false;
- #endif
-
- if(USE_TIMING() && allow)
+template<int PROCNUM> inline uint32_t MMU_fetchExecuteCycles(uint32_t executeCycles, uint32_t fetchCycles)
+{
+#ifdef ACCOUNT_FOR_CODE_FETCH_CYCLES
+ bool allow = true;
+#else
+ bool allow = false;
+#endif
+
+ if (USE_TIMING() && allow)
{
// execute and fetch are different stages of the pipeline for both arm7 and arm9.
// again, we approximate the pipeline throughput using max.
@@ -448,5 +383,5 @@
return executeCycles;
}
-#endif //MMUTIMING_H
-
+#endif // MMUTIMING_H
+
--- a/src/in_2sf/desmume/NDSSystem.cpp
+++ b/src/in_2sf/desmume/NDSSystem.cpp
@@ -1,6 +1,6 @@
/*
Copyright (C) 2006 yopyop
- Copyright (C) 2008-2012 DeSmuME team
+ Copyright (C) 2008-2013 DeSmuME team
This file is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -21,176 +21,72 @@
#include <cstdlib>
#include <cmath>
#include <zlib.h>
-
-#include "common.h"
#include "NDSSystem.h"
-//#include "render3D.h"
#include "MMU.h"
-//#include "ROMReader.h"
-//#include "gfx3d.h"
-//#include "utils/decrypt/decrypt.h"
-//#include "utils/decrypt/crc.h"
+#include "cp15.h"
#include "bios.h"
-//#include "debug.h"
-//#include "cheatSystem.h"
-//#include "movie.h"
-//#include "Disassembler.h"
#include "readwrite.h"
-//#include "debug.h"
#include "firmware.h"
#include "version.h"
#include "slot1.h"
-#include "path.h"
-
-//#define LOG_ARM9
-//#define LOG_ARM7
-//bool dolog = false;
-//#define LOG_TO_FILE
-//#define LOG_TO_FILE_REGS
-
-//===============================================================
-//FILE *fp_dis7 = NULL;
-//FILE *fp_dis9 = NULL;
-
-PathInfo path;
+// ===============================================================
TCommonSettings CommonSettings;
-//static BaseDriver _stub_driver;
-//BaseDriver* driver = &_stub_driver;
-//std::string InputDisplayString;
-
-//static bool LidClosed = false;
-//static uint8_t countLid = 0;
GameInfo gameInfo;
NDSSystem nds;
-CFIRMWARE *firmware = NULL;
-//ADVANsCEne advsc;
+std::unique_ptr<CFIRMWARE> firmware;
bool singleStep;
-//bool nds_debug_continuing[2];
-//int lagframecounter;
-//int LagFrameFlag;
-//int lastLag;
-//int TotalLagFrames;
-
-//TSCalInfo TSCal;
namespace DLDI
{
- bool tryPatch(void* data, size_t size);
-}
-
-/*void Desmume_InitOnce()
-{
- static bool initOnce = false;
- if(initOnce) return;
- initOnce = true;*/
-
-/*#ifdef HAVE_LIBAGG
- extern void Agg_init(); //no need to include just for this
- Agg_init();
-#endif*/
-//}
-
-#ifdef GDB_STUB
-int NDS_Init( struct armcpu_memory_iface *arm9_mem_if,
-struct armcpu_ctrl_iface **arm9_ctrl_iface,
-struct armcpu_memory_iface *arm7_mem_if,
-struct armcpu_ctrl_iface **arm7_ctrl_iface) {
-#else
-int NDS_Init() {
-#endif
- //nds.idleFrameCounter = 0;
- //memset(nds.runCycleCollector,0,sizeof(nds.runCycleCollector));
+ bool tryPatch(void *data, size_t size);
+}
+
+int NDS_Init()
+{
MMU_Init();
nds.VCount = 0;
- //got to print this somewhere..
+ // got to print this somewhere..
printf("%s\n", EMU_DESMUME_NAME_AND_VERSION());
- /*if (Screen_Init(GFXCORE_DUMMY) != 0)
- return -1;*/
-
- //gfx3d_init();
-
-#ifdef GDB_STUB
- armcpu_new(&NDS_ARM7,1, arm7_mem_if, arm7_ctrl_iface);
- armcpu_new(&NDS_ARM9,0, arm9_mem_if, arm9_ctrl_iface);
-#else
- armcpu_new(&NDS_ARM7,1);
- armcpu_new(&NDS_ARM9,0);
+ armcpu_new(&NDS_ARM7, 1);
+ armcpu_new(&NDS_ARM9, 0);
+
+ if (SPU_Init(SNDCORE_DUMMY, 740))
+ return -1;
+
+ return 0;
+}
+
+void NDS_DeInit()
+{
+ if (MMU.CART_ROM != MMU.UNUSED_RAM)
+ NDS_FreeROM();
+
+ SPU_DeInit();
+ MMU_DeInit();
+
+#ifdef HAVE_JIT
+ arm_jit_close();
#endif
-
- if (SPU_Init(SNDCORE_DUMMY, 740) != 0)
- return -1;
-
- //WIFI_Init() ;
-
- // Init calibration info
- //TSCal.adc.x1 = 0x0200;
- //TSCal.adc.y1 = 0x0200;
- //TSCal.scr.x1 = 0x20 + 1; // calibration screen coords are 1-based,
- //TSCal.scr.y1 = 0x20 + 1; // either that or NDS_getADCTouchPosX/Y are wrong.
- //TSCal.adc.x2 = 0x0E00;
- //TSCal.adc.y2 = 0x0800;
- //TSCal.scr.x2 = 0xE0 + 1;
- //TSCal.scr.y2 = 0x80 + 1;
- //TSCal.adc.width = (TSCal.adc.x2 - TSCal.adc.x1);
- //TSCal.adc.height = (TSCal.adc.y2 - TSCal.adc.y1);
- //TSCal.scr.width = (TSCal.scr.x2 - TSCal.scr.x1);
- //TSCal.scr.height = (TSCal.scr.y2 - TSCal.scr.y1);
-
- //cheats = new CHEATS();
- //cheatSearch = new CHEATSEARCH();
-
- return 0;
-}
-
-void NDS_DeInit() {
- if(MMU.CART_ROM != MMU.UNUSED_RAM)
- NDS_FreeROM();
-
- SPU_DeInit();
- //Screen_DeInit();
- MMU_DeInit();
- //gpu3D->NDS_3D_Close();
-
- //WIFI_DeInit();
- /*if (cheats)
- delete cheats;*/
- /*if (cheatSearch)
- delete cheatSearch;*/
-
-#ifdef LOG_ARM7
- if (fp_dis7 != NULL)
- {
- fclose(fp_dis7);
- fp_dis7 = NULL;
- }
-#endif
-
-#ifdef LOG_ARM9
- if (fp_dis9 != NULL)
- {
- fclose(fp_dis9);
- fp_dis9 = NULL;
- }
-#endif
-}
-
-bool NDS_SetROM(uint8_t * rom, uint32_t mask)
+}
+
+bool NDS_SetROM(uint8_t *rom, uint32_t mask)
{
MMU_setRom(rom, mask);
return true;
}
-NDS_header * NDS_getROMHeader()
-{
- if(MMU.CART_ROM == MMU.UNUSED_RAM) return NULL;
- NDS_header * header = new NDS_header;
+std::unique_ptr<NDS_header> NDS_getROMHeader()
+{
+ if (MMU.CART_ROM == MMU.UNUSED_RAM)
+ return std::unique_ptr<NDS_header>();
+ auto header = std::unique_ptr<NDS_header>(new NDS_header);
memcpy(header->gameTile, MMU.CART_ROM, 12);
memcpy(header->gameCode, MMU.CART_ROM + 12, 4);
@@ -231,800 +127,34 @@
memcpy(header->logo, MMU.CART_ROM + 192, 156);
header->logoCRC16 = T1ReadWord(MMU.CART_ROM, 348);
header->headerCRC16 = T1ReadWord(MMU.CART_ROM, 350);
- memcpy(header->reserved, MMU.CART_ROM + 352, std::min(160, (int)gameInfo.romsize - 352));
+ memcpy(header->reserved, MMU.CART_ROM + 352, std::min(160, static_cast<int>(gameInfo.romsize) - 352));
return header;
}
-
-
-
-/*void debug()
-{
- //if(NDS_ARM9.R[15]==0x020520DC) emu_halt();
- //DSLinux
- //if(NDS_ARM9.CPSR.bits.mode == 0) emu_halt();
- //if((NDS_ARM9.R[15]&0xFFFFF000)==0) emu_halt();
- //if((NDS_ARM9.R[15]==0x0201B4F4)&&(NDS_ARM9.R[1]==0x0)) emu_halt();
- //AOE
- //if((NDS_ARM9.R[15]==0x01FFE194)&&(NDS_ARM9.R[0]==0)) emu_halt();
- //if((NDS_ARM9.R[15]==0x01FFE134)&&(NDS_ARM9.R[0]==0)) emu_halt();
-
- //BBMAN
- //if(NDS_ARM9.R[15]==0x02098B4C) emu_halt();
- //if(NDS_ARM9.R[15]==0x02004924) emu_halt();
- //if(NDS_ARM9.R[15]==0x02004890) emu_halt();
-
- //if(NDS_ARM9.R[15]==0x0202B800) emu_halt();
- //if(NDS_ARM9.R[15]==0x0202B3DC) emu_halt();
- //if((NDS_ARM9.R[1]==0x9AC29AC1)&&(!fait)) {emu_halt();fait = true;}
- //if(NDS_ARM9.R[1]==0x0400004A) {emu_halt();fait = true;}
- if(NDS_ARM9.R[4]==0x2E33373C) emu_halt();
- if(NDS_ARM9.R[15]==0x02036668) //emu_halt();
- {
- nds.logcount++;
- sprintf(logbuf, "%d %08X", nds.logcount, NDS_ARM9.R[13]);
- log::ajouter(logbuf);
- if(nds.logcount==89) execute=false;
- }
- //if(NDS_ARM9.instruction==0) emu_halt();
- //if((NDS_ARM9.R[15]>>28)) emu_halt();
-}*/
-
-//#define DSGBA_LOADER_SIZE 512
-/*enum
-{
- ROM_NDS = 0,
- ROM_DSGBA
-};*/
-
-#if 0 /* not used */
-//http://www.aggregate.org/MAGIC/#Population%20Count%20(Ones%20Count)
-static uint32_t ones32(uint32_t x)
-{
- /* 32-bit recursive reduction using SWAR...
- but first step is mapping 2-bit values
- into sum of 2 1-bit values in sneaky way
- */
- x -= ((x >> 1) & 0x55555555);
- x = (((x >> 2) & 0x33333333) + (x & 0x33333333));
- x = (((x >> 4) + x) & 0x0f0f0f0f);
- x += (x >> 8);
- x += (x >> 16);
- return x & 0x0000003f;
-}
-#endif
-
RomBanner::RomBanner(bool defaultInit)
{
- if(!defaultInit) return;
- version = 1; //Version (0001h)
- crc16 = 0; //CRC16 across entries 020h..83Fh
- memset(reserved,0,sizeof(reserved));
- memset(bitmap,0,sizeof(bitmap));
- memset(palette,0,sizeof(palette));
- memset(titles,0,sizeof(titles));
- memset(end0xFF,0,sizeof(end0xFF));
-}
-
-/*bool GameInfo::hasRomBanner()
-{
- if(header.IconOff + sizeof(RomBanner) > romsize)
- return false;
- else return true;
-}*/
-
-/*const RomBanner& GameInfo::getRomBanner()
-{
- //we may not have a valid banner. return a default one
- if(!hasRomBanner())
- {
- static RomBanner defaultBanner(true);
- return defaultBanner;
- }
-
- return *(RomBanner*)(romdata+header.IconOff);
-}*/
-
-/*void GameInfo::populate()
-{
- const char *regions[] = { "JPFSEDIRKH",
- "JPN",
- "EUR",
- "FRA",
- "ESP",
- "USA",
- "NOE",
- "ITA",
- "RUS",
- "KOR",
- "HOL",
-
- };
-
- NDS_header * _header = NDS_getROMHeader();
- header = *_header;
- delete _header;
-
- memset(ROMserial, 0, sizeof(ROMserial));
- memset(ROMname, 0, sizeof(ROMname));
-
- if (
- //Option 1. - look for this instruction in the game title
- //(did this ever work?)
- //(header->gameTile[0] == 0x2E) &&
- //(header->gameTile[1] == 0x00) &&
- //(header->gameTile[2] == 0x00) &&
- //(header->gameTile[3] == 0xEA)
- //) &&
- //option 2. - look for gamecode #### (default for ndstool)
- //or an invalid gamecode
- (
- ((header.gameCode[0] == 0x23) &&
- (header.gameCode[1] == 0x23) &&
- (header.gameCode[2] == 0x23) &&
- (header.gameCode[3] == 0x23)
- ) ||
- (header.gameCode[0] == 0x00)
- )
- &&
- header.makerCode == 0x0
- )
- {
- //we can't really make a serial for a homebrew game that hasnt set a game code
- strcpy(ROMserial, "Homebrew");
- }
- else
- {
- strcpy(ROMserial,"NTR- -");
- memcpy(ROMserial+4, header.gameCode, 4);
-
- uint32_t region = (uint32_t)(std::max<int32_t>(strchr(regions[0],header.gameCode[3]) - regions[0] + 1, 0));
- if (region != 0)
- strcat(ROMserial, regions[region]);
- else
- strcat(ROMserial, "Unknown");
- }
-
- //rom name is probably set even in homebrew
- memset(ROMname, 0, sizeof(ROMname));
- memcpy(ROMname, header.gameTile, 12);
- trim(ROMname,20);
-
- if(header.IconOff < romsize)
- {
- uint8_t num = (T1ReadByte((uint8_t*)romdata, header.IconOff) == 1)?6:7;
- for (int i = 0; i < num; i++)
- {
- wcstombs(ROMfullName[i], (wchar_t *)(romdata+header.IconOff+0x240+(i*0x100)), 0x100);
- trim(ROMfullName[i]);
- }
- }
-
- //this may look like a poor heuristic for detecting homebrew, but it is actually pretty good.
- //setting your own game code is stupid, so homebrew should just leave it.
- //however, non-devkitARM-default makefiles may not have set this.
- isHomebrew = !memcmp(header.gameCode,"####",4);
-}*/
-
-/*#ifdef _WINDOWS
-
-//static std::vector<char> buffer;
-//static std::vector<char> v;
-
-static void loadrom(std::string fname) {
-
- FILE* inf = fopen(fname.c_str(),"rb");
- if(!inf) return;
-
- fseek(inf,0,SEEK_END);
- int size = ftell(inf);
- fseek(inf,0,SEEK_SET);
-
- gameInfo.resize(size);
- fread(gameInfo.romdata,1,size,inf);
- gameInfo.fillGap();
-
- fclose(inf);
-}
-
-static int rom_init_path(const char *filename, const char *logicalFilename)
-{
- int type = ROM_NDS;
-
- path.init(logicalFilename);
-
- if ( path.isdsgba(path.path)) {
- type = ROM_DSGBA;
- loadrom(path.path);
- }
- else if ( !strcasecmp(path.extension().c_str(), "nds")) {
- type = ROM_NDS;
- loadrom(path.path); //n.b. this does nothing if the file can't be found (i.e. if it was an extracted tempfile)...
- //...but since the data was extracted to gameInfo then it is ok
- }
- //ds.gba in archives, it's already been loaded into memory at this point
- else if (path.isdsgba(std::string(logicalFilename))) {
- type = ROM_DSGBA;
- } else {
- //well, try to load it as an nds rom anyway
- type = ROM_NDS;
- loadrom(path.path);
- }
-
- if(type == ROM_DSGBA)
- {
- std::vector<char> v(gameInfo.romdata + DSGBA_LOADER_SIZE, gameInfo.romdata + gameInfo.romsize);
- gameInfo.loadData(&v[0],gameInfo.romsize - DSGBA_LOADER_SIZE);
- }
-
- //check that size is at least the size of the header
- if (gameInfo.romsize < 352) {
- return -1;
- }
-
- return 1;
-}
-#else
-static int rom_init_path(const char *filename, const char *logicalFilename)
-{
- int ret;
- int type;
- ROMReader_struct *reader;
- void *file;
- uint32_t size;
- char *noext;
-
- noext = strdup(filename);
- reader = ROMReaderInit(&noext);
- free(noext);
-
- if (logicalFilename)
- path.init(logicalFilename);
- else
- path.init(filename);
-
- if (!strcasecmp(path.extension().c_str(), "zip"))
- type = ROM_NDS;
- else if (!strcasecmp(path.extension().c_str(), "nds"))
- type = ROM_NDS;
- else if (path.isdsgba(path.path))
- type = ROM_DSGBA;
- else
- type = ROM_NDS;
-
- file = reader->Init(filename);
- if (!file)
- {
- reader->DeInit(file);
- return -1;
- }
-
- size = reader->Size(file);
-
- if(type == ROM_DSGBA)
- {
- reader->Seek(file, DSGBA_LOADER_SIZE, SEEK_SET);
- size -= DSGBA_LOADER_SIZE;
- }
-
- //check that size is at least the size of the header
- if (size < 352) {
- reader->DeInit(file);
- return -1;
- }
-
- // Make sure old ROM is freed first(at least this way we won't be eating
- // up a ton of ram before the old ROM is freed)
- if(MMU.CART_ROM != MMU.UNUSED_RAM)
- NDS_FreeROM();
-
- gameInfo.resize(size);
- ret = reader->Read(file, gameInfo.romdata, size);
- gameInfo.fillGap();
- reader->DeInit(file);
-
- return ret;
-}
-#endif*/
-
-/*int NDS_LoadROM(const char *filename, const char *logicalFilename)
-{
- int ret;
- char buf[MAX_PATH];
-
- if (filename == NULL)
- return -1;
-
- ret = rom_init_path(filename, logicalFilename);
- if (ret < 1)
- return ret;
-
- //decrypt if necessary..
- //but this is untested and suspected to fail on big endian, so lets not support this on big endian
-#ifndef WORDS_BIGENDIAN
- bool okRom = DecryptSecureArea((uint8_t*)gameInfo.romdata,gameInfo.romsize);
-
- if(!okRom) {
- printf("Specified file is not a valid rom\n");
- return -1;
- }
-#endif
-
- if (cheatSearch)
- cheatSearch->close();
- FCEUI_StopMovie();
-
- MMU_unsetRom();
- NDS_SetROM((uint8_t*)gameInfo.romdata, gameInfo.mask);
-
- gameInfo.populate();
- gameInfo.crc = crc32(0,(uint8_t*)gameInfo.romdata,gameInfo.romsize);
- //INFO("\nROM game code: %c%c%c%c\n", gameInfo.header.gameCode[0], gameInfo.header.gameCode[1], gameInfo.header.gameCode[2], gameInfo.header.gameCode[3]);
- //INFO("ROM crc: %08X\n", gameInfo.crc);
- //INFO("ROM serial: %s\n", gameInfo.ROMserial);
- //INFO("ROM internal name: %s\n", gameInfo.ROMname);
-
- memset(buf, 0, MAX_PATH);
- strcpy(buf, path.pathToModule);
- strcat(buf, "desmume.ddb"); // DeSmuME database :)
- advsc.setDatabase(buf);
- buf[0] = gameInfo.header.gameCode[0];
- buf[1] = gameInfo.header.gameCode[1];
- buf[2] = gameInfo.header.gameCode[2];
- buf[3] = gameInfo.header.gameCode[3];
- buf[4] = 0;
- if (advsc.checkDB(buf))
- {
- u8 sv = advsc.getSaveType();
- printf("ADVANsCEne database:\n");
- printf("\t* ROM save type: ");
- if (sv == 0xFF)
- printf("Unknown");
- else
- if (sv == 0xFE)
- printf("None");
- else
- {
- printf("%s", save_names[sv]);
- if (CommonSettings.autodetectBackupMethod == 1)
- backup_setManualBackupType(sv+1);
- }
- printf("\n\t* ROM crc: %08X\n", advsc.getCRC32());
- }
- printf("\n");
-
- //for homebrew, try auto-patching DLDI. should be benign if there is no DLDI or if it fails
- if(gameInfo.isHomebrew)
- DLDI::tryPatch((void*)gameInfo.romdata, gameInfo.romsize);
-
- memset(buf, 0, MAX_PATH);
- path.getpathnoext(path.BATTERY, buf);
- strcat(buf, ".dsv"); // DeSmuME memory card :)
- MMU_new.backupDevice.load_rom(buf);
-
- memset(buf, 0, MAX_PATH);
- path.getpathnoext(path.CHEATS, buf);
- strcat(buf, ".dct"); // DeSmuME cheat :)
- cheats->init(buf);
-
- NDS_Reset();
-
- return ret;
-}*/
+ if (!defaultInit)
+ return;
+ this->version = 1; //Version (0001h)
+ this->crc16 = 0; //CRC16 across entries 020h..83Fh
+ memset(this->reserved, 0, sizeof(this->reserved));
+ memset(this->bitmap, 0, sizeof(this->bitmap));
+ memset(this->palette, 0, sizeof(this->palette));
+ memset(this->titles, 0, sizeof(this->titles));
+ memset(this->end0xFF, 0, sizeof(this->end0xFF));
+}
void NDS_FreeROM()
{
- //FCEUI_StopMovie();
- if ((uint8_t*)MMU.CART_ROM == (uint8_t*)gameInfo.romdata)
- gameInfo.romdata = NULL;
+ if (MMU.CART_ROM == reinterpret_cast<uint8_t *>(&gameInfo.romdata[0]))
+ gameInfo.romdata.reset();
if (MMU.CART_ROM != MMU.UNUSED_RAM)
delete [] MMU.CART_ROM;
MMU_unsetRom();
}
-
-
-/*int NDS_ImportSave(const char *filename)
-{
- if (strlen(filename) < 4)
- return 0;
-
- if (memcmp(filename+strlen(filename)-4, ".duc", 4) == 0)
- return MMU_new.backupDevice.load_duc(filename);
- else
- if (MMU_new.backupDevice.load_no_gba(filename))
- return 1;
- else
- return MMU_new.backupDevice.load_raw(filename);
-
- //return 0;
-}*/
-
-/*bool NDS_ExportSave(const char *filename)
-{
- if (strlen(filename) < 4)
- return false;
-
- if (memcmp(filename+strlen(filename)-5, ".sav*", 5) == 0)
- {
- char tmp[MAX_PATH];
- memset(tmp, 0, MAX_PATH);
- strcpy(tmp, filename);
- tmp[strlen(tmp)-1] = 0;
- return MMU_new.backupDevice.save_no_gba(tmp);
- }
-
- if (memcmp(filename+strlen(filename)-4, ".sav", 4) == 0)
- return MMU_new.backupDevice.save_raw(filename);
-
- return false;
-}*/
-
-/*static int WritePNGChunk(FILE *fp, uint32 size, const char *type, const uint8 *data)
-{
- uint32 crc;
-
- uint8 tempo[4];
-
- tempo[0]=size>>24;
- tempo[1]=size>>16;
- tempo[2]=size>>8;
- tempo[3]=size;
-
- if(fwrite(tempo,4,1,fp)!=1)
- return 0;
- if(fwrite(type,4,1,fp)!=1)
- return 0;
-
- if(size)
- if(fwrite(data,1,size,fp)!=size)
- return 0;
-
- crc = crc32(0,(uint8 *)type,4);
- if(size)
- crc = crc32(crc,data,size);
-
- tempo[0]=crc>>24;
- tempo[1]=crc>>16;
- tempo[2]=crc>>8;
- tempo[3]=crc;
-
- if(fwrite(tempo,4,1,fp)!=1)
- return 0;
- return 1;
-}*/
-/*int NDS_WritePNG(const char *fname)
-{
- int x, y;
- int width=256;
- int height=192*2;
- uint16_t * bmp = (uint16_t *)GPU_screen;
- FILE *pp=NULL;
- uint8 *compmem = NULL;
- uLongf compmemsize = (uLongf)( (height * (width + 1) * 3 * 1.001 + 1) + 12 );
-
- if(!(compmem=(uint8 *)malloc(compmemsize)))
- return 0;
-
- if(!(pp=fopen(fname, "wb")))
- {
- goto PNGerr;
- }
- {
- const uint8 header[8]={137,80,78,71,13,10,26,10};
- if(fwrite(header,8,1,pp)!=1)
- goto PNGerr;
- }
-
- {
- uint8 chunko[13];
-
- chunko[0] = width >> 24; // Width
- chunko[1] = width >> 16;
- chunko[2] = width >> 8;
- chunko[3] = width;
-
- chunko[4] = height >> 24; // Height
- chunko[5] = height >> 16;
- chunko[6] = height >> 8;
- chunko[7] = height;
-
- chunko[8]=8; // 8 bits per sample(24 bits per pixel)
- chunko[9]=2; // Color type; RGB triplet
- chunko[10]=0; // compression: deflate
- chunko[11]=0; // Basic adapative filter set(though none are used).
- chunko[12]=0; // No interlace.
-
- if(!WritePNGChunk(pp,13,"IHDR",chunko))
- goto PNGerr;
- }
-
- {
- uint8 *tmp_buffer;
- uint8 *tmp_inc;
- tmp_inc = tmp_buffer = (uint8 *)malloc((width * 3 + 1) * height);
-
- for(y=0;y<height;y++)
- {
- *tmp_inc = 0;
- tmp_inc++;
- for(x=0;x<width;x++)
- {
- int r,g,b;
- uint16_t pixel = bmp[y*256+x];
- r = pixel>>10;
- pixel-=r<<10;
- g = pixel>>5;
- pixel-=g<<5;
- b = pixel;
- r*=255/31;
- g*=255/31;
- b*=255/31;
- tmp_inc[0] = b;
- tmp_inc[1] = g;
- tmp_inc[2] = r;
- tmp_inc += 3;
- }
- }
-
- if(compress(compmem, &compmemsize, tmp_buffer, height * (width * 3 + 1))!=Z_OK)
- {
- if(tmp_buffer) free(tmp_buffer);
- goto PNGerr;
- }
- if(tmp_buffer) free(tmp_buffer);
- if(!WritePNGChunk(pp,compmemsize,"IDAT",compmem))
- goto PNGerr;
- }
- if(!WritePNGChunk(pp,0,"IEND",0))
- goto PNGerr;
-
- free(compmem);
- fclose(pp);
-
- return 1;
-
-PNGerr:
- if(compmem)
- free(compmem);
- if(pp)
- fclose(pp);
- return 0;
-}*/
-
-/*typedef struct
-{
- uint32_t size;
- int32_t width;
- int32_t height;
- uint16_t planes;
- uint16_t bpp;
- uint32_t cmptype;
- uint32_t imgsize;
- int32_t hppm;
- int32_t vppm;
- uint32_t numcol;
- uint32_t numimpcol;
-} bmpimgheader_struct;
-
-#include "PACKED.h"
-typedef struct
-{
- uint16_t id __PACKED;
- uint32_t size __PACKED;
- uint16_t reserved1 __PACKED;
- uint16_t reserved2 __PACKED;
- uint32_t imgoffset __PACKED;
-} bmpfileheader_struct;
-#include "PACKED_END.h"*/
-
-/*int NDS_WriteBMP(const char *filename)
-{
- bmpfileheader_struct fileheader;
- bmpimgheader_struct imageheader;
- FILE *file;
- int i,j;
- uint16_t * bmp = (uint16_t *)GPU_screen;
- size_t elems_written = 0;
-
- memset(&fileheader, 0, sizeof(fileheader));
- fileheader.size = sizeof(fileheader);
- fileheader.id = 'B' | ('M' << 8);
- fileheader.imgoffset = sizeof(fileheader)+sizeof(imageheader);
-
- memset(&imageheader, 0, sizeof(imageheader));
- imageheader.size = sizeof(imageheader);
- imageheader.width = 256;
- imageheader.height = 192*2;
- imageheader.planes = 1;
- imageheader.bpp = 24;
- imageheader.cmptype = 0; // None
- imageheader.imgsize = imageheader.width * imageheader.height * 3;
-
- if ((file = fopen(filename,"wb")) == NULL)
- return 0;
-
- elems_written += fwrite(&fileheader, 1, sizeof(fileheader), file);
- elems_written += fwrite(&imageheader, 1, sizeof(imageheader), file);
-
- for(j=0;j<192*2;j++)
- {
- for(i=0;i<256;i++)
- {
- uint8_t r,g,b;
- uint16_t pixel = bmp[(192*2-j-1)*256+i];
- r = pixel>>10;
- pixel-=r<<10;
- g = pixel>>5;
- pixel-=g<<5;
- b = (uint8_t)pixel;
- r*=255/31;
- g*=255/31;
- b*=255/31;
- elems_written += fwrite(&r, 1, sizeof(uint8_t), file);
- elems_written += fwrite(&g, 1, sizeof(uint8_t), file);
- elems_written += fwrite(&b, 1, sizeof(uint8_t), file);
- }
- }
- fclose(file);
-
- return 1;
-}*/
-
-/*int NDS_WriteBMP_32bppBuffer(int width, int height, const void* buf, const char *filename)
-{
- bmpfileheader_struct fileheader;
- bmpimgheader_struct imageheader;
- FILE *file;
- size_t elems_written = 0;
- memset(&fileheader, 0, sizeof(fileheader));
- fileheader.size = sizeof(fileheader);
- fileheader.id = 'B' | ('M' << 8);
- fileheader.imgoffset = sizeof(fileheader)+sizeof(imageheader);
-
- memset(&imageheader, 0, sizeof(imageheader));
- imageheader.size = sizeof(imageheader);
- imageheader.width = width;
- imageheader.height = height;
- imageheader.planes = 1;
- imageheader.bpp = 32;
- imageheader.cmptype = 0; // None
- imageheader.imgsize = imageheader.width * imageheader.height * 4;
-
- if ((file = fopen(filename,"wb")) == NULL)
- return 0;
-
- elems_written += fwrite(&fileheader, 1, sizeof(fileheader), file);
- elems_written += fwrite(&imageheader, 1, sizeof(imageheader), file);
-
- for(int i=0;i<height;i++)
- for(int x=0;x<width;x++)
- {
- uint8_t* pixel = (uint8_t*)buf + (height-i-1)*width*4;
- pixel += (x*4);
- elems_written += fwrite(pixel+2,1,1,file);
- elems_written += fwrite(pixel+1,1,1,file);
- elems_written += fwrite(pixel+0,1,1,file);
- elems_written += fwrite(pixel+3,1,1,file);
- }
- fclose(file);
-
- return 1;
-}*/
-
void NDS_Sleep() { nds.sleeping = true; }
-/*void NDS_ToggleCardEject()
-{
- if(!nds.cardEjected)
- {
- //staff of kings will test this (it also uses the arm9 0xB8 poll)
- NDS_makeIrq(ARMCPU_ARM7, IRQ_BIT_GC_IREQ_MC);
- }
- nds.cardEjected ^= true;
-}*/
-
-
-/*class FrameSkipper
-{
-public:
- void RequestSkip()
- {
- nextSkip = true;
- }
- void OmitSkip(bool force, bool forceEvenIfCapturing=false)
- {
- nextSkip = false;
- if((force && consecutiveNonCaptures > 30) || forceEvenIfCapturing)
- {
- SkipCur2DFrame = false;
- SkipCur3DFrame = false;
- SkipNext2DFrame = false;
- if(forceEvenIfCapturing)
- consecutiveNonCaptures = 0;
- }
- }
- void Advance()
- {
- bool capturing = false*//*(MainScreen.gpu->dispCapCnt.enabled || (MainScreen.gpu->dispCapCnt.val & 0x80000000))*//*;
-
- if(capturing && consecutiveNonCaptures > 30)
- {
- // the worst-looking graphics corruption problems from frameskip
- // are the result of skipping the capture on first frame it turns on.
- // so we do this to handle the capture immediately,
- // despite the risk of 1 frame of 2d/3d mismatch or wrong screen display.
- SkipNext2DFrame = false;
- nextSkip = false;
- }
- else if(*//*lastOffset != MainScreen.offset && *//*lastSkip && !skipped)
- {
- // if we're switching from not skipping to skipping
- // and the screens are also switching around this frame,
- // go for 1 extra frame without skipping.
- // this avoids the scenario where we only draw one of the two screens
- // when a game is switching screens every frame.
- nextSkip = false;
- }
-
- if(capturing)
- consecutiveNonCaptures = 0;
- else if(!(consecutiveNonCaptures > 9000)) // arbitrary cap to avoid eventual wrap
- consecutiveNonCaptures++;
- lastLastOffset = lastOffset;
- //lastOffset = MainScreen.offset;
- lastSkip = skipped;
- skipped = nextSkip;
- nextSkip = false;
-
- SkipCur2DFrame = SkipNext2DFrame;
- SkipCur3DFrame = skipped;
- SkipNext2DFrame = skipped;
- }
- inline bool ShouldSkip2D()
- {
- return SkipCur2DFrame;
- }
- inline bool ShouldSkip3D()
- {
- return SkipCur3DFrame;
- }
- FrameSkipper()
- {
- nextSkip = false;
- skipped = false;
- lastSkip = false;
- lastOffset = 0;
- SkipCur2DFrame = false;
- SkipCur3DFrame = false;
- SkipNext2DFrame = false;
- consecutiveNonCaptures = 0;
- }
-private:
- bool nextSkip;
- bool skipped;
- bool lastSkip;
- int lastOffset;
- int lastLastOffset;
- int consecutiveNonCaptures;
- bool SkipCur2DFrame;
- bool SkipCur3DFrame;
- bool SkipNext2DFrame;
-};*/
-//static FrameSkipper frameSkipper;
-
-
-/*void NDS_SkipNextFrame() {
- //if (!driver->AVI_IsRecording()) {
- //frameSkipper.RequestSkip();
- //}
-}*/
-/*void NDS_OmitFrameSkip(int force) {
- //frameSkipper.OmitSkip(force > 0, force > 1);
-}*/
-
-//#define INDEX(i) ((((i)>>16)&0xFF0)|(((i)>>4)&0xF))
-
enum ESI_DISPCNT
{
@@ -1042,235 +172,164 @@
uint32_t param;
bool enabled;
- /*virtual void save(EMUFILE* os)
- {
- write64le(timestamp,os);
- write32le(param,os);
- writebool(enabled,os);
- }*/
-
- virtual bool load(EMUFILE* is)
- {
- if(read64le(×tamp,is) != 1) return false;
- if(read32le(¶m,is) != 1) return false;
- if(readbool(&enabled,is) != 1) return false;
- return true;
- }
-
- inline bool isTriggered()
- {
- return enabled && nds_timer >= timestamp;
- }
-
- inline uint64_t next()
- {
- return timestamp;
+ virtual bool isTriggered() const
+ {
+ return this->enabled && nds_timer >= this->timestamp;
+ }
+
+ virtual uint64_t next() const
+ {
+ return this->timestamp;
}
};
-/*struct TSequenceItem_GXFIFO : public TSequenceItem
-{
- inline bool isTriggered()
- {
- return enabled && nds_timer >= MMU.gfx3dCycles;
- }
-
- inline void exec()
- {
- IF_DEVELOPER(DEBUG_statistics.sequencerExecutionCounters[4]++);
- while(isTriggered()) {
- enabled = false;
- //gfx3d_execute3D();
- }
- }
-
- inline uint64_t next()
- {
- if(enabled) return MMU.gfx3dCycles;
- else return kNever;
- }
-};*/
-
template<int procnum, int num> struct TSequenceItem_Timer : public TSequenceItem
{
- inline bool isTriggered()
- {
- return enabled && nds_timer >= nds.timerCycle[procnum][num];
- }
-
- inline void schedule()
- {
- enabled = MMU.timerON[procnum][num] && MMU.timerMODE[procnum][num] != 0xFFFF;
- }
-
- inline uint64_t next()
+ bool isTriggered() const
+ {
+ return this->enabled && nds_timer >= nds.timerCycle[procnum][num];
+ }
+
+ void schedule()
+ {
+ this->enabled = MMU.timerON[procnum][num] && MMU.timerMODE[procnum][num] != 0xFFFF;
+ }
+
+ uint64_t next() const
{
return nds.timerCycle[procnum][num];
}
- inline void exec()
- {
- IF_DEVELOPER(DEBUG_statistics.sequencerExecutionCounters[13+procnum*4+num]++);
- uint8_t* regs = procnum==0?MMU.ARM9_REG:MMU.ARM7_REG;
+ void exec()
+ {
+ uint8_t *regs = !procnum ? MMU.ARM9_REG : MMU.ARM7_REG;
bool first = true, over;
- //we'll need to check chained timers..
- for(int i=num;i<4;i++)
+ // we'll need to check chained timers..
+ for (int i = num; i < 4; ++i)
{
- //maybe too many checks if this is here, but we need it here for now
- if(!MMU.timerON[procnum][i]) return;
-
- if(MMU.timerMODE[procnum][i] == 0xFFFF)
+ // maybe too many checks if this is here, but we need it here for now
+ if (!MMU.timerON[procnum][i])
+ return;
+
+ if (MMU.timerMODE[procnum][i] == 0xFFFF)
{
- ++(MMU.timer[procnum][i]);
+ ++MMU.timer[procnum][i];
over = !MMU.timer[procnum][i];
}
else
{
- if(!first) break; //this timer isn't chained. break the chain
+ if (!first)
+ break; // this timer isn't chained. break the chain
first = false;
over = true;
int remain = 65536 - MMU.timerReload[procnum][i];
- int ctr=0;
- while(nds.timerCycle[procnum][i] <= nds_timer) {
- nds.timerCycle[procnum][i] += (remain << MMU.timerMODE[procnum][i]);
- ctr++;
+ int ctr = 0;
+ while (nds.timerCycle[procnum][i] <= nds_timer)
+ {
+ nds.timerCycle[procnum][i] += remain << MMU.timerMODE[procnum][i];
+ ++ctr;
}
#ifndef NDEBUG
- if(ctr>1) {
+ if (ctr > 1)
printf("yikes!!!!! please report!\n");
- }
#endif
}
- if(over)
+ if (over)
{
MMU.timer[procnum][i] = MMU.timerReload[procnum][i];
- if(T1ReadWord(regs, 0x102 + i*4) & 0x40)
- {
+ if (T1ReadWord(regs, 0x102 + i * 4) & 0x40)
NDS_makeIrq(procnum, IRQ_BIT_TIMER_0 + i);
- }
}
else
- break; //no more chained timers to trigger. we're done here
+ break; // no more chained timers to trigger. we're done here
}
}
};
template<int procnum, int chan> struct TSequenceItem_DMA : public TSequenceItem
{
- DmaController* controller;
-
- inline bool isTriggered()
- {
- return controller->dmaCheck && nds_timer>= controller->nextEvent;
- }
-
- inline bool isEnabled() {
- return controller->dmaCheck?true:false;
- }
-
- inline uint64_t next()
- {
- return controller->nextEvent;
- }
-
- inline void exec()
- {
- IF_DEVELOPER(DEBUG_statistics.sequencerExecutionCounters[5+procnum*4+chan]++);
-
- //if (nds.freezeBus) return;
-
+ DmaController *controller;
+
+ bool isTriggered() const
+ {
+ return this->controller->dmaCheck && nds_timer>= this->controller->nextEvent;
+ }
+
+ bool isEnabled() const
+ {
+ return this->controller->dmaCheck;
+ }
+
+ uint64_t next() const
+ {
+ return this->controller->nextEvent;
+ }
+
+ void exec()
+ {
//printf("exec from TSequenceItem_DMA: %d %d\n",procnum,chan);
- controller->exec();
-// //give gxfifo dmas a chance to re-trigger
-// if(MMU.DMAStartTime[procnum][chan] == EDMAMode_GXFifo) {
-// MMU.DMAing[procnum][chan] = false;
-// if (gxFIFO.size <= 127)
-// {
-// execHardware_doDma(procnum,chan,EDMAMode_GXFifo);
-// if (MMU.DMACompleted[procnum][chan])
-// goto docomplete;
-// else return;
-// }
-// }
-//
-//docomplete:
-// if (MMU.DMACompleted[procnum][chan])
-// {
-// uint8_t* regs = procnum==0?MMU.ARM9_REG:MMU.ARM7_REG;
-//
-// //disable the channel
-// if(MMU.DMAStartTime[procnum][chan] != EDMAMode_GXFifo) {
-// T1WriteLong(regs, 0xB8 + (0xC*chan), T1ReadLong(regs, 0xB8 + (0xC*chan)) & 0x7FFFFFFF);
-// MMU.DMACrt[procnum][chan] &= 0x7FFFFFFF; //blehhh i hate this shit being mirrored in memory
-// }
-//
-// if((MMU.DMACrt[procnum][chan])&(1<<30)) {
-// if(procnum==0) NDS_makeARM9Int(8+chan);
-// else NDS_makeARM7Int(8+chan);
-// }
-//
-// MMU.DMAing[procnum][chan] = false;
-// }
-
+ this->controller->exec();
}
};
struct TSequenceItem_divider : public TSequenceItem
{
- inline bool isTriggered()
+ bool isTriggered() const
{
return MMU.divRunning && nds_timer >= MMU.divCycles;
}
- bool isEnabled() { return MMU.divRunning!=0; }
-
- inline uint64_t next()
+ bool isEnabled()
+ {
+ return MMU.divRunning;
+ }
+
+ uint64_t next() const
{
return MMU.divCycles;
}
void exec()
{
- IF_DEVELOPER(DEBUG_statistics.sequencerExecutionCounters[2]++);
MMU_new.div.busy = 0;
#ifdef _WIN64
T1WriteQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A0, MMU.divResult);
T1WriteQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A8, MMU.divMod);
#else
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A0, (uint32_t)MMU.divResult);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A4, (uint32_t)(MMU.divResult >> 32));
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A8, (uint32_t)MMU.divMod);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2AC, (uint32_t)(MMU.divMod >> 32));
+ T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A0, static_cast<uint32_t>(MMU.divResult));
+ T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A4, static_cast<uint32_t>(MMU.divResult >> 32));
+ T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A8, static_cast<uint32_t>(MMU.divMod));
+ T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2AC, static_cast<uint32_t>(MMU.divMod >> 32));
#endif
MMU.divRunning = false;
}
-
};
struct TSequenceItem_sqrtunit : public TSequenceItem
{
- inline bool isTriggered()
+ bool isTriggered() const
{
return MMU.sqrtRunning && nds_timer >= MMU.sqrtCycles;
}
- bool isEnabled() { return MMU.sqrtRunning!=0; }
-
- inline uint64_t next()
+ bool isEnabled()
+ {
+ return MMU.sqrtRunning;
+ }
+
+ uint64_t next() const
{
return MMU.sqrtCycles;
}
- inline void exec()
- {
- IF_DEVELOPER(DEBUG_statistics.sequencerExecutionCounters[3]++);
+ void exec()
+ {
MMU_new.sqrt.busy = 0;
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B4, MMU.sqrtResult);
MMU.sqrtRunning = false;
}
-
};
struct Sequencer
@@ -1282,75 +341,26 @@
TSequenceItem_divider divider;
TSequenceItem_sqrtunit sqrtunit;
TSequenceItem/*_GXFIFO*/ gxfifo;
- TSequenceItem_DMA<0,0> dma_0_0; TSequenceItem_DMA<0,1> dma_0_1;
- TSequenceItem_DMA<0,2> dma_0_2; TSequenceItem_DMA<0,3> dma_0_3;
- TSequenceItem_DMA<1,0> dma_1_0; TSequenceItem_DMA<1,1> dma_1_1;
- TSequenceItem_DMA<1,2> dma_1_2; TSequenceItem_DMA<1,3> dma_1_3;
- TSequenceItem_Timer<0,0> timer_0_0; TSequenceItem_Timer<0,1> timer_0_1;
- TSequenceItem_Timer<0,2> timer_0_2; TSequenceItem_Timer<0,3> timer_0_3;
- TSequenceItem_Timer<1,0> timer_1_0; TSequenceItem_Timer<1,1> timer_1_1;
- TSequenceItem_Timer<1,2> timer_1_2; TSequenceItem_Timer<1,3> timer_1_3;
+ TSequenceItem_DMA<0, 0> dma_0_0; TSequenceItem_DMA<0, 1> dma_0_1;
+ TSequenceItem_DMA<0, 2> dma_0_2; TSequenceItem_DMA<0, 3> dma_0_3;
+ TSequenceItem_DMA<1, 0> dma_1_0; TSequenceItem_DMA<1, 1> dma_1_1;
+ TSequenceItem_DMA<1, 2> dma_1_2; TSequenceItem_DMA<1, 3> dma_1_3;
+ TSequenceItem_Timer<0, 0> timer_0_0; TSequenceItem_Timer<0, 1> timer_0_1;
+ TSequenceItem_Timer<0, 2> timer_0_2; TSequenceItem_Timer<0, 3> timer_0_3;
+ TSequenceItem_Timer<1, 0> timer_1_0; TSequenceItem_Timer<1, 1> timer_1_1;
+ TSequenceItem_Timer<1, 2> timer_1_2; TSequenceItem_Timer<1, 3> timer_1_3;
void init();
void execHardware();
uint64_t findNext();
-
- /*void save(EMUFILE* os)
- {
- write64le(nds_timer,os);
- write64le(nds_arm9_timer,os);
- write64le(nds_arm7_timer,os);
- dispcnt.save(os);
- divider.save(os);
- sqrtunit.save(os);
- gxfifo.save(os);
- wifi.save(os);
-#define SAVE(I,X,Y) I##_##X##_##Y .save(os);
- SAVE(timer,0,0); SAVE(timer,0,1); SAVE(timer,0,2); SAVE(timer,0,3);
- SAVE(timer,1,0); SAVE(timer,1,1); SAVE(timer,1,2); SAVE(timer,1,3);
- SAVE(dma,0,0); SAVE(dma,0,1); SAVE(dma,0,2); SAVE(dma,0,3);
- SAVE(dma,1,0); SAVE(dma,1,1); SAVE(dma,1,2); SAVE(dma,1,3);
-#undef SAVE
- }*/
-
- bool load(EMUFILE* is, int version)
- {
- if(read64le(&nds_timer,is) != 1) return false;
- if(read64le(&nds_arm9_timer,is) != 1) return false;
- if(read64le(&nds_arm7_timer,is) != 1) return false;
- if(!dispcnt.load(is)) return false;
- if(!divider.load(is)) return false;
- if(!sqrtunit.load(is)) return false;
- if(!gxfifo.load(is)) return false;
- if(version >= 1) if(!wifi.load(is)) return false;
-#define LOAD(I,X,Y) if(!I##_##X##_##Y .load(is)) return false;
- LOAD(timer,0,0); LOAD(timer,0,1); LOAD(timer,0,2); LOAD(timer,0,3);
- LOAD(timer,1,0); LOAD(timer,1,1); LOAD(timer,1,2); LOAD(timer,1,3);
- LOAD(dma,0,0); LOAD(dma,0,1); LOAD(dma,0,2); LOAD(dma,0,3);
- LOAD(dma,1,0); LOAD(dma,1,1); LOAD(dma,1,2); LOAD(dma,1,3);
-#undef LOAD
-
- return true;
- }
-
} sequencer;
-/*void NDS_RescheduleGXFIFO(uint32_t cost)
-{
- //if(!sequencer.gxfifo.enabled) {
- //MMU.gfx3dCycles = nds_timer;
- //sequencer.gxfifo.enabled = true;
- //}
- //MMU.gfx3dCycles += cost;
- NDS_Reschedule();
-}*/
-
void NDS_RescheduleTimers()
{
-#define check(X,Y) sequencer.timer_##X##_##Y .schedule();
- check(0,0); check(0,1); check(0,2); check(0,3);
- check(1,0); check(1,1); check(1,2); check(1,3);
+#define check(X, Y) sequencer.timer_##X##_##Y .schedule();
+ check(0, 0); check(0, 1); check(0, 2); check(0, 3);
+ check(1, 0); check(1, 1); check(1, 2); check(1, 3);
#undef check
NDS_Reschedule();
@@ -1360,20 +370,18 @@
{
//TBD
NDS_Reschedule();
-
}
static void initSchedule()
{
sequencer.init();
- //begin at the very end of the last scanline
- //so that at t=0 we can increment to scanline=0
+ // begin at the very end of the last scanline
+ // so that at t=0 we can increment to scanline=0
nds.VCount = 262;
sequencer.nds_vblankEnded = false;
}
-
// 2196372 ~= (ARM7_CLOCK << 16) / 1000000
// This value makes more sense to me, because:
@@ -1388,93 +396,51 @@
NDS_RescheduleTimers();
NDS_RescheduleDMA();
- reschedule = false;
+ this->reschedule = false;
nds_timer = 0;
nds_arm9_timer = 0;
nds_arm7_timer = 0;
- dispcnt.enabled = true;
- dispcnt.param = ESI_DISPCNT_HStart;
- dispcnt.timestamp = 0;
-
- //gxfifo.enabled = false;
-
- dma_0_0.controller = &MMU_new.dma[0][0];
- dma_0_1.controller = &MMU_new.dma[0][1];
- dma_0_2.controller = &MMU_new.dma[0][2];
- dma_0_3.controller = &MMU_new.dma[0][3];
- dma_1_0.controller = &MMU_new.dma[1][0];
- dma_1_1.controller = &MMU_new.dma[1][1];
- dma_1_2.controller = &MMU_new.dma[1][2];
- dma_1_3.controller = &MMU_new.dma[1][3];
-
-
- /*#ifdef EXPERIMENTAL_WIFI_COMM
- wifi.enabled = true;
- wifi.timestamp = kWifiCycles;
- #else
- wifi.enabled = false;
- #endif*/
-}
-
-//this isnt helping much right now. work on it later
-//#include "utils/task.h"
-//Task taskSubGpu(true);
-//void* renderSubScreen(void*)
-//{
-// GPU_RenderLine(&SubScreen, nds.VCount, SkipCur2DFrame);
-// return NULL;
-//}
+ this->dispcnt.enabled = true;
+ this->dispcnt.param = ESI_DISPCNT_HStart;
+ this->dispcnt.timestamp = 0;
+
+ this->dma_0_0.controller = &MMU_new.dma[0][0];
+ this->dma_0_1.controller = &MMU_new.dma[0][1];
+ this->dma_0_2.controller = &MMU_new.dma[0][2];
+ this->dma_0_3.controller = &MMU_new.dma[0][3];
+ this->dma_1_0.controller = &MMU_new.dma[1][0];
+ this->dma_1_1.controller = &MMU_new.dma[1][1];
+ this->dma_1_2.controller = &MMU_new.dma[1][2];
+ this->dma_1_3.controller = &MMU_new.dma[1][3];
+}
static void execHardware_hblank()
{
- //this logic keeps moving around.
- //now, we try and give the game as much time as possible to finish doing its work for the scanline,
- //by drawing scanline N at the end of drawing time (but before subsequent interrupt or hdma-driven events happen)
- //don't try to do this at the end of the scanline, because some games (sonic classics) may use hblank IRQ to set
- //scroll regs for the next scanline
- if(nds.VCount<192)
- {
- //taskSubGpu.execute(renderSubScreen,NULL);
- //GPU_RenderLine(&MainScreen, nds.VCount, frameSkipper.ShouldSkip2D());
- //GPU_RenderLine(&SubScreen, nds.VCount, frameSkipper.ShouldSkip2D());
- //taskSubGpu.finish();
-
- //trigger hblank dmas
- //but notice, we do that just after we finished drawing the line
- //(values copied by this hdma should not be used until the next scanline)
+ // this logic keeps moving around.
+ // now, we try and give the game as much time as possible to finish doing its work for the scanline,
+ // by drawing scanline N at the end of drawing time (but before subsequent interrupt or hdma-driven events happen)
+ // don't try to do this at the end of the scanline, because some games (sonic classics) may use hblank IRQ to set
+ // scroll regs for the next scanline
+ if (nds.VCount < 192)
+ // trigger hblank dmas
+ // but notice, we do that just after we finished drawing the line
+ // (values copied by this hdma should not be used until the next scanline)
triggerDma(EDMAMode_HBlank);
- }
-
- if(nds.VCount==262)
- {
- //we need to trigger one last hblank dma since
- //a. we're sort of lagged behind by one scanline
- //b. i think that 193 hblanks actually fire (one for the hblank in scanline 262)
- //this is demonstrated by NSMB splot-parallaxing clouds
- //for some reason the game will setup two hdma scroll register buffers
- //to be run consecutively, and unless we do this, the second buffer will be offset by one scanline
- //causing a glitch in the 0th scanline
- //triggerDma(EDMAMode_HBlank);
-
- //BUT! this was removed in order to make glitches in megaman zero collection (mmz 4 1st level) work.
- //and, it seems that it is no longer necessary in nsmb. perhaps something else fixed it
- }
-
-
- //turn on hblank status bit
+
+ // turn on hblank status bit
T1WriteWord(MMU.ARM9_REG, 4, T1ReadWord(MMU.ARM9_REG, 4) | 2);
T1WriteWord(MMU.ARM7_REG, 4, T1ReadWord(MMU.ARM7_REG, 4) | 2);
- //fire hblank interrupts if necessary
- if(T1ReadWord(MMU.ARM9_REG, 4) & 0x10) NDS_makeIrq(ARMCPU_ARM9,IRQ_BIT_LCD_HBLANK);
- if(T1ReadWord(MMU.ARM7_REG, 4) & 0x10) NDS_makeIrq(ARMCPU_ARM7,IRQ_BIT_LCD_HBLANK);
-
- //emulation housekeeping. for some reason we always do this at hblank,
- //even though it sounds more reasonable to do it at hstart
+ // fire hblank interrupts if necessary
+ if (T1ReadWord(MMU.ARM9_REG, 4) & 0x10)
+ NDS_makeIrq(ARMCPU_ARM9, IRQ_BIT_LCD_HBLANK);
+ if (T1ReadWord(MMU.ARM7_REG, 4) & 0x10)
+ NDS_makeIrq(ARMCPU_ARM7, IRQ_BIT_LCD_HBLANK);
+
+ // emulation housekeeping. for some reason we always do this at hblank,
+ // even though it sounds more reasonable to do it at hstart
SPU_Emulate_core();
- //driver->AVI_SoundUpdate(SPU_core->outbuf,spu_core_samples);
- //WAV_WavSoundUpdate(SPU_core->outbuf,spu_core_samples);
}
static void execHardware_hstart_vblankEnd()
@@ -1482,201 +448,156 @@
sequencer.nds_vblankEnded = true;
sequencer.reschedule = true;
- //turn off vblank status bit
+ // turn off vblank status bit
T1WriteWord(MMU.ARM9_REG, 4, T1ReadWord(MMU.ARM9_REG, 4) & ~1);
T1WriteWord(MMU.ARM7_REG, 4, T1ReadWord(MMU.ARM7_REG, 4) & ~1);
-
- //some emulation housekeeping
- //frameSkipper.Advance();
}
static void execHardware_hstart_vblankStart()
{
//printf("--------VBLANK!!!--------\n");
- //fire vblank interrupts if necessary
- for(int i=0;i<2;i++)
- if(MMU.reg_IF_pending[i] & (1<<IRQ_BIT_LCD_VBLANK))
+ // fire vblank interrupts if necessary
+ for (int i = 0; i < 2; ++i)
+ if (MMU.reg_IF_pending[i] & (1 << IRQ_BIT_LCD_VBLANK))
{
- MMU.reg_IF_pending[i] &= ~(1<<IRQ_BIT_LCD_VBLANK);
- NDS_makeIrq(i,IRQ_BIT_LCD_VBLANK);
+ MMU.reg_IF_pending[i] &= ~(1 << IRQ_BIT_LCD_VBLANK);
+ NDS_makeIrq(i, IRQ_BIT_LCD_VBLANK);
}
- //trigger vblank dmas
+ // trigger vblank dmas
triggerDma(EDMAMode_VBlank);
-
- //tracking for arm9 load average
- //nds.runCycleCollector[0][nds.idleFrameCounter] = 1120380-nds.idleCycles[0];
- //nds.runCycleCollector[1][nds.idleFrameCounter] = 1120380-nds.idleCycles[1];
- //nds.idleFrameCounter++;
- //nds.idleFrameCounter &= 15;
- //nds.idleCycles[0] = 0;
- //nds.idleCycles[1] = 0;
}
static uint16_t execHardware_gen_vmatch_goal()
{
uint16_t vmatch = T1ReadWord(MMU.ARM9_REG, 4);
- vmatch = ((vmatch>>8)|((vmatch<<1)&(1<<8)));
+ vmatch = (vmatch >> 8) | ((vmatch << 1) & (1 << 8));
return vmatch;
}
static void execHardware_hstart_vcount_irq()
{
- //trigger pending VMATCH irqs
- if(MMU.reg_IF_pending[ARMCPU_ARM9] & (1<<IRQ_BIT_LCD_VMATCH))
- {
- MMU.reg_IF_pending[ARMCPU_ARM9] &= ~(1<<IRQ_BIT_LCD_VMATCH);
- NDS_makeIrq(ARMCPU_ARM9,IRQ_BIT_LCD_VMATCH);
- }
- if(MMU.reg_IF_pending[ARMCPU_ARM7] & (1<<IRQ_BIT_LCD_VMATCH))
- {
- MMU.reg_IF_pending[ARMCPU_ARM7] &= ~(1<<IRQ_BIT_LCD_VMATCH);
- NDS_makeIrq(ARMCPU_ARM7,IRQ_BIT_LCD_VMATCH);
+ // trigger pending VMATCH irqs
+ if (MMU.reg_IF_pending[ARMCPU_ARM9] & (1 << IRQ_BIT_LCD_VMATCH))
+ {
+ MMU.reg_IF_pending[ARMCPU_ARM9] &= ~(1 << IRQ_BIT_LCD_VMATCH);
+ NDS_makeIrq(ARMCPU_ARM9, IRQ_BIT_LCD_VMATCH);
+ }
+ if(MMU.reg_IF_pending[ARMCPU_ARM7] & (1 << IRQ_BIT_LCD_VMATCH))
+ {
+ MMU.reg_IF_pending[ARMCPU_ARM7] &= ~(1 << IRQ_BIT_LCD_VMATCH);
+ NDS_makeIrq(ARMCPU_ARM7, IRQ_BIT_LCD_VMATCH);
}
}
static void execHardware_hstart_vcount()
{
uint16_t vmatch = execHardware_gen_vmatch_goal();
- if(nds.VCount==vmatch)
- {
- //arm9 vmatch
+ if (nds.VCount == vmatch)
+ {
+ // arm9 vmatch
T1WriteWord(MMU.ARM9_REG, 4, T1ReadWord(MMU.ARM9_REG, 4) | 4);
- if(T1ReadWord(MMU.ARM9_REG, 4) & 32) {
- MMU.reg_IF_pending[ARMCPU_ARM9] |= (1<<IRQ_BIT_LCD_VMATCH);
- }
+ if (T1ReadWord(MMU.ARM9_REG, 4) & 32)
+ MMU.reg_IF_pending[ARMCPU_ARM9] |= 1 << IRQ_BIT_LCD_VMATCH;
}
else
T1WriteWord(MMU.ARM9_REG, 4, T1ReadWord(MMU.ARM9_REG, 4) & 0xFFFB);
vmatch = T1ReadWord(MMU.ARM7_REG, 4);
- vmatch = ((vmatch>>8)|((vmatch<<1)&(1<<8)));
- if(nds.VCount==vmatch)
- {
- //arm7 vmatch
+ vmatch = (vmatch >> 8) | ((vmatch << 1) & (1 << 8));
+ if (nds.VCount == vmatch)
+ {
+ // arm7 vmatch
T1WriteWord(MMU.ARM7_REG, 4, T1ReadWord(MMU.ARM7_REG, 4) | 4);
- if(T1ReadWord(MMU.ARM7_REG, 4) & 32)
- MMU.reg_IF_pending[ARMCPU_ARM7] |= (1<<IRQ_BIT_LCD_VMATCH);
+ if (T1ReadWord(MMU.ARM7_REG, 4) & 32)
+ MMU.reg_IF_pending[ARMCPU_ARM7] |= 1 << IRQ_BIT_LCD_VMATCH;
}
else
T1WriteWord(MMU.ARM7_REG, 4, T1ReadWord(MMU.ARM7_REG, 4) & 0xFFFB);
}
-static void execHardware_hdraw()
-{
- //due to hacks in our selection of rendering time, we do not actually render here as intended.
- //consider changing this if there is some problem with raster fx timing but check the documentation near the gpu rendering calls
- //to make sure you check for regressions (nsmb, sonic classics, et al)
-}
-
static void execHardware_hstart_irq()
{
- //this function very soon after the registers get updated to trigger IRQs
- //this is necessary to fix "egokoro kyoushitsu" which idles waiting for vcount=192, which never happens due to a long vblank irq
- //100% accurate emulation would require the read of VCOUNT to be in the pipeline already with the irq coming in behind it, thus
- //allowing the vcount to register as 192 occasionally (maybe about 1 out of 28 frames)
- //the actual length of the delay is in execHardware() where the events are scheduled
+ // this function very soon after the registers get updated to trigger IRQs
+ // this is necessary to fix "egokoro kyoushitsu" which idles waiting for vcount=192, which never happens due to a long vblank irq
+ // 100% accurate emulation would require the read of VCOUNT to be in the pipeline already with the irq coming in behind it, thus
+ // allowing the vcount to register as 192 occasionally (maybe about 1 out of 28 frames)
+ // the actual length of the delay is in execHardware() where the events are scheduled
sequencer.reschedule = true;
- if(nds.VCount==192)
- {
- //when the vcount hits 192, vblank begins
+ if (nds.VCount == 192)
+ // when the vcount hits 192, vblank begins
execHardware_hstart_vblankStart();
- }
execHardware_hstart_vcount_irq();
}
static void execHardware_hstart()
{
- nds.VCount++;
-
- //end of 3d vblank
- //this should be 214, but we are going to be generous for games with tight timing
- //they shouldnt be changing any textures at 262 but they might accidentally still be at 214
- //so..
- /*if((CommonSettings.rigorous_timing && nds.VCount==214) || (!CommonSettings.rigorous_timing && nds.VCount==262))
- {
- gfx3d_VBlankEndSignal(frameSkipper.ShouldSkip3D());
- }*/
-
- if(nds.VCount==263)
- {
- //when the vcount hits 263 it rolls over to 0
- nds.VCount=0;
- }
- if(nds.VCount==262)
- {
- //when the vcount hits 262, vblank ends (oam pre-renders by one scanline)
+ ++nds.VCount;
+
+ if (nds.VCount == 263)
+ // when the vcount hits 263 it rolls over to 0
+ nds.VCount = 0;
+ if (nds.VCount == 262)
+ // when the vcount hits 262, vblank ends (oam pre-renders by one scanline)
execHardware_hstart_vblankEnd();
- }
- /*else if(nds.VCount==191)
- {
- //when the vcount hits 191, the 3d vblank occurs (maybe because OAM doesnt need to run anymore, so we can power it down, and give the 3d as much time as possible?)
- gfx3d_VBlankSignal();
- }*/
- else if(nds.VCount==192)
- {
- //turn on vblank status bit
+ else if (nds.VCount == 192)
+ {
+ // turn on vblank status bit
T1WriteWord(MMU.ARM9_REG, 4, T1ReadWord(MMU.ARM9_REG, 4) | 1);
T1WriteWord(MMU.ARM7_REG, 4, T1ReadWord(MMU.ARM7_REG, 4) | 1);
- //check whether we'll need to fire vblank irqs
- if(T1ReadWord(MMU.ARM9_REG, 4) & 0x8) MMU.reg_IF_pending[ARMCPU_ARM9] |= (1<<IRQ_BIT_LCD_VBLANK);
- if(T1ReadWord(MMU.ARM7_REG, 4) & 0x8) MMU.reg_IF_pending[ARMCPU_ARM7] |= (1<<IRQ_BIT_LCD_VBLANK);
- }
-
- //write the new vcount
+ // check whether we'll need to fire vblank irqs
+ if (T1ReadWord(MMU.ARM9_REG, 4) & 0x8)
+ MMU.reg_IF_pending[ARMCPU_ARM9] |= 1 << IRQ_BIT_LCD_VBLANK;
+ if (T1ReadWord(MMU.ARM7_REG, 4) & 0x8)
+ MMU.reg_IF_pending[ARMCPU_ARM7] |= 1 << IRQ_BIT_LCD_VBLANK;
+ }
+
+ // write the new vcount
T1WriteWord(MMU.ARM9_REG, 6, static_cast<uint16_t>(nds.VCount));
T1WriteWord(MMU.ARM9_REG, 0x1006, static_cast<uint16_t>(nds.VCount));
T1WriteWord(MMU.ARM7_REG, 6, static_cast<uint16_t>(nds.VCount));
T1WriteWord(MMU.ARM7_REG, 0x1006, static_cast<uint16_t>(nds.VCount));
- //turn off hblank status bit
+ // turn off hblank status bit
T1WriteWord(MMU.ARM9_REG, 4, T1ReadWord(MMU.ARM9_REG, 4) & 0xFFFD);
T1WriteWord(MMU.ARM7_REG, 4, T1ReadWord(MMU.ARM7_REG, 4) & 0xFFFD);
- //handle vcount status
+ // handle vcount status
execHardware_hstart_vcount();
- //trigger hstart dmas
+ // trigger hstart dmas
triggerDma(EDMAMode_HStart);
- if(nds.VCount<192)
- {
- //this is hacky.
- //there is a corresponding hack in doDMA.
- //it should be driven by a fifo (and generate just in time as the scanline is displayed)
- //but that isnt even possible until we have some sort of sub-scanline timing.
- //it may not be necessary.
+ if (nds.VCount < 192)
+ // this is hacky.
+ // there is a corresponding hack in doDMA.
+ // it should be driven by a fifo (and generate just in time as the scanline is displayed)
+ // but that isnt even possible until we have some sort of sub-scanline timing.
+ // it may not be necessary.
triggerDma(EDMAMode_MemDisplay);
- }
}
void NDS_Reschedule()
{
- IF_DEVELOPER(if(!sequencer.reschedule) DEBUG_statistics.sequencerExecutionCounters[0]++;);
sequencer.reschedule = true;
}
-/*inline uint32_t _fast_min32(uint32_t a, uint32_t b, uint32_t c, uint32_t d)
-{
- return (( ((int32_t)(a-b)) >> (32-1)) & (c^d)) ^ d;
-}*/
-
-inline uint64_t _fast_min(uint64_t a, uint64_t b)
-{
- //you might find that this is faster on a 64bit system; someone should try it
- //http://aggregate.org/MAGIC/#Integer%20Selection
+static inline uint64_t _fast_min(uint64_t a, uint64_t b)
+{
+ // you might find that this is faster on a 64bit system; someone should try it
+ // http://aggregate.org/MAGIC/#Integer%20Selection
//uint64_t ret = (((((s64)(a-b)) >> (64-1)) & (a^b)) ^ b);
//assert(ret==min(a,b));
//return ret;
- //but this ends up being the fastest on 32bits
+ // but this ends up being the fastest on 32bits
return a<b?a:b;
- //just for the record, I tried to do the 64bit math on a 32bit proc
- //using sse2 and it was really slow
+ // just for the record, I tried to do the 64bit math on a 32bit proc
+ // using sse2 and it was really slow
//__m128i __a; __a.m128i_u64[0] = a;
//__m128i __b; __b.m128i_u64[0] = b;
//__m128i xorval = _mm_xor_si128(__a,__b);
@@ -1687,28 +608,27 @@
//return temp.m128i_u64[0];
}
-
-
uint64_t Sequencer::findNext()
{
- //this one is always enabled so dont bother to check it
- uint64_t next = dispcnt.next();
-
- if(divider.isEnabled()) next = _fast_min(next,divider.next());
- if(sqrtunit.isEnabled()) next = _fast_min(next,sqrtunit.next());
- //if(gxfifo.enabled) next = _fast_min(next,gxfifo.next());
-
-#ifdef EXPERIMENTAL_WIFI_COMM
- next = _fast_min(next,wifi.next());
-#endif
-
-#define test(X,Y) if(dma_##X##_##Y .isEnabled()) next = _fast_min(next,dma_##X##_##Y .next());
- test(0,0); test(0,1); test(0,2); test(0,3);
- test(1,0); test(1,1); test(1,2); test(1,3);
+ // this one is always enabled so dont bother to check it
+ uint64_t next = this->dispcnt.next();
+
+ if (this->divider.isEnabled())
+ next = _fast_min(next, this->divider.next());
+ if (this->sqrtunit.isEnabled())
+ next = _fast_min(next, this->sqrtunit.next());
+
+#define test(X, Y) \
+ if (this->dma_##X##_##Y .isEnabled()) \
+ next = _fast_min(next, this->dma_##X##_##Y .next());
+ test(0, 0); test(0, 1); test(0, 2); test(0, 3);
+ test(1, 0); test(1, 1); test(1, 2); test(1, 3);
#undef test
-#define test(X,Y) if(timer_##X##_##Y .enabled) next = _fast_min(next,timer_##X##_##Y .next());
- test(0,0); test(0,1); test(0,2); test(0,3);
- test(1,0); test(1,1); test(1,2); test(1,3);
+#define test(X, Y) \
+ if (this->timer_##X##_##Y .enabled) \
+ next = _fast_min(next, this->timer_##X##_##Y .next());
+ test(0, 0); test(0, 1); test(0, 2); test(0, 3);
+ test(1, 0); test(1, 1); test(1, 2); test(1, 3);
#undef test
return next;
@@ -1716,197 +636,70 @@
void Sequencer::execHardware()
{
- if(dispcnt.isTriggered())
- {
-
- IF_DEVELOPER(DEBUG_statistics.sequencerExecutionCounters[1]++);
-
- switch(dispcnt.param)
+ if (this->dispcnt.isTriggered())
+ {
+ switch (this->dispcnt.param)
{
- case ESI_DISPCNT_HStart:
- execHardware_hstart();
- //(used to be 3168)
- //hstart is actually 8 dots before the visible drawing begins
- //we're going to run 1 here and then run 7 in the next case
- dispcnt.timestamp += 1*6*2;
- dispcnt.param = ESI_DISPCNT_HStartIRQ;
- break;
- case ESI_DISPCNT_HStartIRQ:
- execHardware_hstart_irq();
- dispcnt.timestamp += 7*6*2;
- dispcnt.param = ESI_DISPCNT_HDraw;
- break;
-
- case ESI_DISPCNT_HDraw:
- execHardware_hdraw();
- //duration of non-blanking period is ~1606 clocks (gbatek agrees) [but says its different on arm7]
- //im gonna call this 267 dots = 267*6=1602
- //so, this event lasts 267 dots minus the 8 dot preroll
- dispcnt.timestamp += (267-8)*6*2;
- dispcnt.param = ESI_DISPCNT_HBlank;
- break;
-
- case ESI_DISPCNT_HBlank:
- execHardware_hblank();
- //(once this was 1092 or 1092/12=91 dots.)
- //there are surely 355 dots per scanline, less 267 for non-blanking period. the rest is hblank and then after that is hstart
- dispcnt.timestamp += (355-267)*6*2;
- dispcnt.param = ESI_DISPCNT_HStart;
- break;
+ case ESI_DISPCNT_HStart:
+ execHardware_hstart();
+ // (used to be 3168)
+ // hstart is actually 8 dots before the visible drawing begins
+ // we're going to run 1 here and then run 7 in the next case
+ this->dispcnt.timestamp += 12;
+ this->dispcnt.param = ESI_DISPCNT_HStartIRQ;
+ break;
+ case ESI_DISPCNT_HStartIRQ:
+ execHardware_hstart_irq();
+ this->dispcnt.timestamp += 84;
+ this->dispcnt.param = ESI_DISPCNT_HDraw;
+ break;
+ case ESI_DISPCNT_HDraw:
+ // duration of non-blanking period is ~1606 clocks (gbatek agrees) [but says its different on arm7]
+ // im gonna call this 267 dots = 267*6=1602
+ // so, this event lasts 267 dots minus the 8 dot preroll
+ this->dispcnt.timestamp += 3108;
+ this->dispcnt.param = ESI_DISPCNT_HBlank;
+ break;
+ case ESI_DISPCNT_HBlank:
+ execHardware_hblank();
+ // (once this was 1092 or 1092/12=91 dots.)
+ // there are surely 355 dots per scanline, less 267 for non-blanking period. the rest is hblank and then after that is hstart
+ this->dispcnt.timestamp += 1056;
+ this->dispcnt.param = ESI_DISPCNT_HStart;
}
}
-#ifdef EXPERIMENTAL_WIFI_COMM
- if(wifi.isTriggered())
- {
- WIFI_usTrigger();
- wifi.timestamp += kWifiCycles;
- }
-#endif
-
- if(divider.isTriggered()) divider.exec();
- if(sqrtunit.isTriggered()) sqrtunit.exec();
- //if(gxfifo.isTriggered()) gxfifo.exec();
-
-
-#define test(X,Y) if(dma_##X##_##Y .isTriggered()) dma_##X##_##Y .exec();
- test(0,0); test(0,1); test(0,2); test(0,3);
- test(1,0); test(1,1); test(1,2); test(1,3);
+ if (this->divider.isTriggered())
+ this->divider.exec();
+ if (this->sqrtunit.isTriggered())
+ this->sqrtunit.exec();
+
+#define test(X, Y) \
+ if (this->dma_##X##_##Y .isTriggered()) \
+ this->dma_##X##_##Y .exec();
+ test(0, 0); test(0, 1); test(0, 2); test(0, 3);
+ test(1, 0); test(1, 1); test(1, 2); test(1, 3);
#undef test
-#define test(X,Y) if(timer_##X##_##Y .enabled) if(timer_##X##_##Y .isTriggered()) timer_##X##_##Y .exec();
- test(0,0); test(0,1); test(0,2); test(0,3);
- test(1,0); test(1,1); test(1,2); test(1,3);
+#define test(X, Y) \
+ if (this->timer_##X##_##Y .enabled && this->timer_##X##_##Y .isTriggered()) \
+ this->timer_##X##_##Y .exec();
+ test(0, 0); test(0, 1); test(0, 2); test(0, 3);
+ test(1, 0); test(1, 1); test(1, 2); test(1, 3);
#undef test
}
void execHardware_interrupts();
-//static void saveUserInput(EMUFILE* os);
-static bool loadUserInput(EMUFILE* is, int version);
-
-/*void nds_savestate(EMUFILE* os)
-{
- //version
- write32le(3,os);
-
- //sequencer.save(os);
-
- saveUserInput(os);
-
- write32le(LidClosed,os);
- write8le(countLid,os);
-}*/
-
-bool nds_loadstate(EMUFILE* is, int)
-{
- // this isn't part of the savestate loading logic, but
- // don't skip the next frame after loading a savestate
- //frameSkipper.OmitSkip(true, true);
-
- //read version
- uint32_t version;
- if(read32le(&version,is) != 1) return false;
-
- if(version > 3) return false;
-
- bool temp = true;
- temp &= sequencer.load(is, version);
- if(version <= 1 || !temp) return temp;
- temp &= loadUserInput(is, version);
-
- if(version < 3) return temp;
-
- uint32_t tmpu32;
- read32le(&tmpu32,is);
- uint8_t tmpu8;
- read8le(&tmpu8,is);
-
- return temp;
-}
-
-/*inline void arm9log()
-{
-#ifdef LOG_ARM9
- if(dolog)
- {
- char dasmbuf[4096];
- if(NDS_ARM9.CPSR.bits.T)
- des_thumb_instructions_set[((NDS_ARM9.instruction)>>6)&1023](NDS_ARM9.instruct_adr, NDS_ARM9.instruction, dasmbuf);
- else
- des_arm_instructions_set[INDEX(NDS_ARM9.instruction)](NDS_ARM9.instruct_adr, NDS_ARM9.instruction, dasmbuf);
-
-#ifdef LOG_TO_FILE
- if (!fp_dis9) return;
-#ifdef LOG_TO_FILE_REGS
- fprintf(fp_dis9, "\t\t;R0:%08X R1:%08X R2:%08X R3:%08X R4:%08X R5:%08X R6:%08X R7:%08X R8:%08X R9:%08X\n\t\t;R10:%08X R11:%08X R12:%08X R13:%08X R14:%08X R15:%08X| next %08X, N:%i Z:%i C:%i V:%i\n",
- NDS_ARM9.R[0], NDS_ARM9.R[1], NDS_ARM9.R[2], NDS_ARM9.R[3], NDS_ARM9.R[4], NDS_ARM9.R[5], NDS_ARM9.R[6], NDS_ARM9.R[7],
- NDS_ARM9.R[8], NDS_ARM9.R[9], NDS_ARM9.R[10], NDS_ARM9.R[11], NDS_ARM9.R[12], NDS_ARM9.R[13], NDS_ARM9.R[14], NDS_ARM9.R[15],
- NDS_ARM9.next_instruction, NDS_ARM9.CPSR.bits.N, NDS_ARM9.CPSR.bits.Z, NDS_ARM9.CPSR.bits.C, NDS_ARM9.CPSR.bits.V);
-#endif
- fprintf(fp_dis9, "%s %08X\t%08X \t%s\n", NDS_ARM9.CPSR.bits.T?"THUMB":"ARM", NDS_ARM9.instruct_adr, NDS_ARM9.instruction, dasmbuf);*/
- /*if (NDS_ARM9.instruction == 0)
- {
- dolog = false;
- INFO("Disassembler is stopped\n");
- }*/
-/*#else
- printf("%05d:%03d %12lld 9:%08X %08X %-30s R00:%08X R01:%08X R02:%08X R03:%08X R04:%08X R05:%08X R06:%08X R07:%08X R08:%08X R09:%08X R10:%08X R11:%08X R12:%08X R13:%08X R14:%08X R15:%08X\n",
- currFrameCounter, nds.VCount, nds_timer,
- NDS_ARM9.instruct_adr,NDS_ARM9.instruction, dasmbuf,
- NDS_ARM9.R[0], NDS_ARM9.R[1], NDS_ARM9.R[2], NDS_ARM9.R[3], NDS_ARM9.R[4], NDS_ARM9.R[5], NDS_ARM9.R[6], NDS_ARM9.R[7],
- NDS_ARM9.R[8], NDS_ARM9.R[9], NDS_ARM9.R[10], NDS_ARM9.R[11], NDS_ARM9.R[12], NDS_ARM9.R[13], NDS_ARM9.R[14], NDS_ARM9.R[15]);
-#endif
- }
-#endif
-}*/
-
-/*inline void arm7log()
-{
-#ifdef LOG_ARM7
- if(dolog)
- {
- char dasmbuf[4096];
- if(NDS_ARM7.CPSR.bits.T)
- des_thumb_instructions_set[((NDS_ARM7.instruction)>>6)&1023](NDS_ARM7.instruct_adr, NDS_ARM7.instruction, dasmbuf);
- else
- des_arm_instructions_set[INDEX(NDS_ARM7.instruction)](NDS_ARM7.instruct_adr, NDS_ARM7.instruction, dasmbuf);
-#ifdef LOG_TO_FILE
- if (!fp_dis7) return;
-#ifdef LOG_TO_FILE_REGS
- fprintf(fp_dis7, "\t\t;R0:%08X R1:%08X R2:%08X R3:%08X R4:%08X R5:%08X R6:%08X R7:%08X R8:%08X R9:%08X\n\t\t;R10:%08X R11:%08X R12:%08X R13:%08X R14:%08X R15:%08X| next %08X, N:%i Z:%i C:%i V:%i\n",
- NDS_ARM7.R[0], NDS_ARM7.R[1], NDS_ARM7.R[2], NDS_ARM7.R[3], NDS_ARM7.R[4], NDS_ARM7.R[5], NDS_ARM7.R[6], NDS_ARM7.R[7],
- NDS_ARM7.R[8], NDS_ARM7.R[9], NDS_ARM7.R[10], NDS_ARM7.R[11], NDS_ARM7.R[12], NDS_ARM7.R[13], NDS_ARM7.R[14], NDS_ARM7.R[15],
- NDS_ARM7.next_instruction, NDS_ARM7.CPSR.bits.N, NDS_ARM7.CPSR.bits.Z, NDS_ARM7.CPSR.bits.C, NDS_ARM7.CPSR.bits.V);
-#endif
- fprintf(fp_dis7, "%s %08X\t%08X \t%s\n", NDS_ARM7.CPSR.bits.T?"THUMB":"ARM", NDS_ARM7.instruct_adr, NDS_ARM7.instruction, dasmbuf);*/
- /*if (NDS_ARM7.instruction == 0)
- {
- dolog = false;
- INFO("Disassembler is stopped\n");
- }*/
-/*#else
- printf("%05d:%03d %12lld 7:%08X %08X %-30s R00:%08X R01:%08X R02:%08X R03:%08X R04:%08X R05:%08X R06:%08X R07:%08X R08:%08X R09:%08X R10:%08X R11:%08X R12:%08X R13:%08X R14:%08X R15:%08X\n",
- currFrameCounter, nds.VCount, nds_timer,
- NDS_ARM7.instruct_adr,NDS_ARM7.instruction, dasmbuf,
- NDS_ARM7.R[0], NDS_ARM7.R[1], NDS_ARM7.R[2], NDS_ARM7.R[3], NDS_ARM7.R[4], NDS_ARM7.R[5], NDS_ARM7.R[6], NDS_ARM7.R[7],
- NDS_ARM7.R[8], NDS_ARM7.R[9], NDS_ARM7.R[10], NDS_ARM7.R[11], NDS_ARM7.R[12], NDS_ARM7.R[13], NDS_ARM7.R[14], NDS_ARM7.R[15]);
-#endif
- }
-#endif
-}*/
-
-//these have not been tuned very well yet.
+// these have not been tuned very well yet.
static const int kMaxWork = 4000;
static const int kIrqWait = 4000;
-
-template<bool doarm9, bool doarm7>
-static inline int32_t minarmtime(int32_t arm9, int32_t arm7)
-{
- if(doarm9)
- {
- if(doarm7)
- return std::min(arm9,arm7);
+template<bool doarm9, bool doarm7> static inline int32_t minarmtime(int32_t arm9, int32_t arm7)
+{
+ if (doarm9)
+ {
+ if (doarm7)
+ return std::min(arm9, arm7);
else
return arm9;
}
@@ -1914,206 +707,124 @@
return arm7;
}
+#ifdef HAVE_JIT
+template<bool doarm9, bool doarm7, bool jit>
+#else
template<bool doarm9, bool doarm7>
-static /*donotinline*/ std::pair<int32_t,int32_t> armInnerLoop(
- const uint64_t nds_timer_base, const int32_t s32next, int32_t arm9, int32_t arm7)
-{
- int32_t timer = minarmtime<doarm9,doarm7>(arm9,arm7);
- while(timer < s32next && !sequencer.reschedule && execute)
- {
- if(doarm9 && (!doarm7 || arm9 <= timer))
+#endif
+static std::pair<int32_t, int32_t> armInnerLoop(uint64_t nds_timer_base, int32_t s32next, int32_t arm9, int32_t arm7)
+{
+ int32_t timer = minarmtime<doarm9, doarm7>(arm9, arm7);
+ while (timer < s32next && !sequencer.reschedule && execute)
+ {
+ if (doarm9 && (!doarm7 || arm9 <= timer))
{
- if(!NDS_ARM9.waitIRQ&&!nds.freezeBus)
+ if (!NDS_ARM9.waitIRQ && !nds.freezeBus)
{
- //arm9log();
+#ifdef HAVE_JIT
+ arm9 += armcpu_exec<ARMCPU_ARM9, jit>();
+#else
arm9 += armcpu_exec<ARMCPU_ARM9>();
- #ifdef DEVELOPER
- nds_debug_continuing[0] = false;
- #endif
+#endif
+ }
+ else
+ arm9 = std::min(s32next, arm9 + kIrqWait);
+ }
+ if (doarm7 && (!doarm9 || arm7 <= timer))
+ {
+ if (!NDS_ARM7.waitIRQ && !nds.freezeBus)
+ {
+#ifdef HAVE_JIT
+ arm7 += armcpu_exec<ARMCPU_ARM7, jit>() << 1;
+#else
+ arm7 += armcpu_exec<ARMCPU_ARM7>() << 1;
+#endif
}
else
{
- //int32_t temp = arm9;
- arm9 = std::min(s32next, arm9 + kIrqWait);
- //nds.idleCycles[0] += arm9-temp;
- //if (gxFIFO.size < 255) nds.freezeBus = false;
- }
- }
- if(doarm7 && (!doarm9 || arm7 <= timer))
- {
- if(!NDS_ARM7.waitIRQ&&!nds.freezeBus)
- {
- //arm7log();
- arm7 += (armcpu_exec<ARMCPU_ARM7>()<<1);
- #ifdef DEVELOPER
- nds_debug_continuing[1] = false;
- #endif
- }
- else
- {
- //int32_t temp = arm7;
arm7 = std::min(s32next, arm7 + kIrqWait);
- //nds.idleCycles[1] += arm7-temp;
- if(arm7 == s32next)
+ if (arm7 == s32next)
{
- nds_timer = nds_timer_base + minarmtime<doarm9,false>(arm9,arm7);
- return armInnerLoop<doarm9,false>(nds_timer_base, s32next, arm9, arm7);
+ nds_timer = nds_timer_base + minarmtime<doarm9, false>(arm9, arm7);
+#ifdef HAVE_JIT
+ return armInnerLoop<doarm9, false, jit>(nds_timer_base, s32next, arm9, arm7);
+#else
+ return armInnerLoop<doarm9, false>(nds_timer_base, s32next, arm9, arm7);
+#endif
}
}
}
- timer = minarmtime<doarm9,doarm7>(arm9,arm7);
+ timer = minarmtime<doarm9, doarm7>(arm9, arm7);
nds_timer = nds_timer_base + timer;
}
return std::make_pair(arm9, arm7);
}
-/*void NDS_debug_break()
-{
- NDS_ARM9.stalled = NDS_ARM7.stalled = 1;
-
- //triggers an immediate exit from the cpu loop
- NDS_Reschedule();
-}*/
-
-/*void NDS_debug_continue()
-{
- NDS_ARM9.stalled = NDS_ARM7.stalled = 0;
-}*/
-
-/*void NDS_debug_step()
-{
- NDS_debug_continue();
- singleStep = true;
-}*/
-
-template<bool FORCE>
-void NDS_exec(int32_t)
-{
- //LagFrameFlag=1;
-
- /*if((currFrameCounter&63) == 0)
- MMU_new.backupDevice.lazy_flush();*/
-
+template<bool FORCE> void NDS_exec(int32_t)
+{
sequencer.nds_vblankEnded = false;
- //nds.cpuloopIterationCount = 0;
-
- IF_DEVELOPER(for(int i=0;i<32;i++) DEBUG_statistics.sequencerExecutionCounters[i] = 0);
-
- if(nds.sleeping)
- {
- //speculative code: if ANY irq happens, wake up the arm7.
- //I think the arm7 program analyzes the system and may decide not to wake up
- //if it is dissatisfied with the conditions
- if((MMU.reg_IE[1] & MMU.gen_IF<1>()))
+ if (nds.sleeping)
+ {
+ // speculative code: if ANY irq happens, wake up the arm7.
+ // I think the arm7 program analyzes the system and may decide not to wake up
+ // if it is dissatisfied with the conditions
+ if (MMU.reg_IE[1] & MMU.gen_IF<1>())
+ nds.sleeping = false;
+ }
+ else
+ {
+ for (;;)
{
- nds.sleeping = false;
- }
- }
- else
- {
- for(;;)
- {
- //trap the debug-stalled condition
- #ifdef DEVELOPER
- singleStep = false;
- //(gdb stub doesnt yet know how to trigger these immediately by calling reschedule)
- while((NDS_ARM9.stalled || NDS_ARM7.stalled) && execute)
- {
- driver->EMU_DebugIdleUpdate();
- nds_debug_continuing[0] = nds_debug_continuing[1] = true;
- }
- #endif
-
- //nds.cpuloopIterationCount++;
sequencer.execHardware();
- //break out once per frame
- if(sequencer.nds_vblankEnded) break;
- //it should be benign to execute execHardware in the next frame,
- //since there won't be anything for it to do (everything should be scheduled in the future)
-
- //bail in case the system halted
- if(!execute) break;
+ // break out once per frame
+ if (sequencer.nds_vblankEnded)
+ break;
+ // it should be benign to execute execHardware in the next frame,
+ // since there won't be anything for it to do (everything should be scheduled in the future)
+
+ // bail in case the system halted
+ if (!execute)
+ break;
execHardware_interrupts();
- //find next work unit:
+ // find next work unit:
uint64_t next = sequencer.findNext();
- next = std::min(next,nds_timer+kMaxWork); //lets set an upper limit for now
-
- //printf("%d\n",(next-nds_timer));
+ next = std::min(next, nds_timer + kMaxWork); // lets set an upper limit for now
+
+ //printf("%d\n", next - nds_timer);
sequencer.reschedule = false;
- //cast these down to 32bits so that things run faster on 32bit procs
+ // cast these down to 32bits so that things run faster on 32bit procs
uint64_t nds_timer_base = nds_timer;
- int32_t arm9 = (int32_t)(nds_arm9_timer-nds_timer);
- int32_t arm7 = (int32_t)(nds_arm7_timer-nds_timer);
- int32_t s32next = (int32_t)(next-nds_timer);
-
- #ifdef DEVELOPER
- if(singleStep)
- {
- s32next = 1;
- }
- #endif
-
- std::pair<int32_t,int32_t> arm9arm7 = armInnerLoop<true,true>(nds_timer_base,s32next,arm9,arm7);
-
- #ifdef DEVELOPER
- if(singleStep)
- {
- NDS_ARM9.stalled = NDS_ARM7.stalled = 1;
- }
- #endif
+ int32_t arm9 = static_cast<int32_t>(nds_arm9_timer - nds_timer);
+ int32_t arm7 = static_cast<int32_t>(nds_arm7_timer - nds_timer);
+ int32_t s32next = static_cast<int32_t>(next - nds_timer);
+
+#ifdef HAVE_JIT
+ auto arm9arm7 = CommonSettings.use_jit ? armInnerLoop<true, true, true>(nds_timer_base, s32next, arm9, arm7) : armInnerLoop<true, true, false>(nds_timer_base, s32next, arm9, arm7);
+#else
+ auto arm9arm7 = armInnerLoop<true, true>(nds_timer_base, s32next, arm9, arm7);
+#endif
arm9 = arm9arm7.first;
arm7 = arm9arm7.second;
- nds_arm7_timer = nds_timer_base+arm7;
- nds_arm9_timer = nds_timer_base+arm9;
-
-#ifndef NDEBUG
- //what we find here is dependent on the timing constants above
- //if(nds_timer>next && (nds_timer-next)>22)
- // printf("curious. please report: over by %d\n",(int)(nds_timer-next));
-#endif
-
- //if we were waiting for an irq, don't wait too long:
- //let's re-analyze it after this hardware event (this rolls back a big burst of irq waiting which may have been interrupted by a resynch)
- if(NDS_ARM9.waitIRQ)
- {
- //nds.idleCycles[0] -= (int32_t)(nds_arm9_timer-nds_timer);
+ nds_arm7_timer = nds_timer_base + arm7;
+ nds_arm9_timer = nds_timer_base + arm9;
+
+ // if we were waiting for an irq, don't wait too long:
+ // let's re-analyze it after this hardware event (this rolls back a big burst of irq waiting which may have been interrupted by a resynch)
+ if (NDS_ARM9.waitIRQ)
nds_arm9_timer = nds_timer;
- }
- if(NDS_ARM7.waitIRQ)
- {
- //nds.idleCycles[1] -= (int32_t)(nds_arm7_timer-nds_timer);
+ if (NDS_ARM7.waitIRQ)
nds_arm7_timer = nds_timer;
- }
}
}
-
- //DEBUG_statistics.printSequencerExecutionCounters();
- //DEBUG_statistics.print();
-
- //end of frame emulation housekeeping
- /*if(LagFrameFlag)
- {
- lagframecounter++;
- TotalLagFrames++;
- }
- else
- {
- lastLag = lagframecounter;
- lagframecounter = 0;
- }*/
- //currFrameCounter++;
- //DEBUG_Notify.NextFrame();
- /*if (cheats)
- cheats->process();*/
}
template<int PROCNUM> static void execHardware_interrupts_core()
@@ -2121,13 +832,13 @@
uint32_t IF = MMU.gen_IF<PROCNUM>();
uint32_t IE = MMU.reg_IE[PROCNUM];
uint32_t masked = IF & IE;
- if(ARMPROC.halt_IE_and_IF && masked)
+ if (ARMPROC.halt_IE_and_IF && masked)
{
ARMPROC.halt_IE_and_IF = false;
ARMPROC.waitIRQ = false;
}
- if(masked && MMU.reg_IME[PROCNUM] && !ARMPROC.CPSR.bits.I)
+ if (masked && MMU.reg_IME[PROCNUM] && !ARMPROC.CPSR.bits.I)
{
//printf("Executing IRQ on procnum %d with IF = %08X and IE = %08X\n",PROCNUM,IF,IE);
armcpu_irqException(&ARMPROC);
@@ -2140,115 +851,45 @@
execHardware_interrupts_core<ARMCPU_ARM7>();
}
-//static void resetUserInput();
-
-//bool _HACK_DONT_STOPMOVIE = false;
-void NDS_Reset()
-{
- singleStep = false;
- //nds_debug_continuing[0] = nds_debug_continuing[1] = false;
- uint32_t src = 0;
- uint32_t dst = 0;
- bool fw_success = false;
- FILE* inf = NULL;
- NDS_header * header = NDS_getROMHeader();
-
- //DEBUG_reset();
-
- if (!header) return ;
-
- nds.sleeping = false;
- nds.cardEjected = false;
- nds.freezeBus = 0;
- //nds.power1.lcd = nds.power1.gpuMain = nds.power1.gfx3d_render = nds.power1.gfx3d_geometry = nds.power1.gpuSub = nds.power1.dispswap = 1;
- //nds.power2.speakers = 1;
- //nds.power2.wifi = 0;
-
- nds_timer = 0;
- nds_arm9_timer = 0;
- nds_arm7_timer = 0;
-
- /*if(movieMode != MOVIEMODE_INACTIVE && !_HACK_DONT_STOPMOVIE)
- movie_reset_command = true;*/
-
- /*if(movieMode == MOVIEMODE_INACTIVE) {
- //currFrameCounter = 0;
- lagframecounter = 0;
- LagFrameFlag = 0;
- lastLag = 0;
- TotalLagFrames = 0;
- }*/
-
- SPU_DeInit();
-
- MMU_Reset();
-
- //put random garbage in vram for homebrew games, to help mimic the situation where libnds does not clear out junk
- //which the card's launcher may or may not have left behind
- //1. retail games dont clear TCM, so why should we jumble it and expect homebrew to clear it?
- //2. some retail games _dont boot_ if main memory is jumbled. wha...?
- //3. clearing this is not as useful as tracking uninitialized reads in dev+ builds
- //4. the vram clearing causes lots of graphical corruptions in badly coded homebrews. this reduces compatibility substantially
- //conclusion: disable it for now and bring it back as an option
- //if(gameInfo.isHomebrew)
- //{
- // uint32_t w=100000,x=99,y=117,z=19382173;
- // CTASSERT(sizeof(MMU.ARM9_LCD) < sizeof(MMU.MAIN_MEM));
- // CTASSERT(sizeof(MMU.ARM9_VMEM) < sizeof(MMU.MAIN_MEM));
- // CTASSERT(sizeof(MMU.ARM9_ITCM) < sizeof(MMU.MAIN_MEM));
- // CTASSERT(sizeof(MMU.ARM9_DTCM) < sizeof(MMU.MAIN_MEM));
- // for(int i=0;i<sizeof(MMU.MAIN_MEM);i++)
- // {
- // uint32_t t= (x^(x<<11));
- // x=y;
- // y=z;
- // z=w;
- // t = (w= (w^(w>>19))^(t^(t>>8)));
- // //MMU.MAIN_MEM[i] = t;
- // if (i<sizeof(MMU.ARM9_LCD)) MMU.ARM9_LCD[i] = t;
- // if (i<sizeof(MMU.ARM9_VMEM)) MMU.ARM9_VMEM[i] = t;
- // //if (i<sizeof(MMU.ARM9_ITCM)) MMU.ARM9_ITCM[i] = t;
- // //if (i<sizeof(MMU.ARM9_DTCM)) MMU.ARM9_DTCM[i] = t;
- // }
- //}
-
+static void PrepareBiosARM7()
+{
NDS_ARM7.BIOS_loaded = false;
- NDS_ARM9.BIOS_loaded = false;
memset(MMU.ARM7_BIOS, 0, sizeof(MMU.ARM7_BIOS));
- memset(MMU.ARM9_BIOS, 0, sizeof(MMU.ARM9_BIOS));
-
- //ARM7 BIOS IRQ HANDLER
- if(CommonSettings.UseExtBIOS == true)
- inf = fopen(CommonSettings.ARM7BIOS,"rb");
- else
- inf = NULL;
-
- if(inf)
- {
- if (fread(MMU.ARM7_BIOS,1,16384,inf) == 16384) NDS_ARM7.BIOS_loaded = true;
- fclose(inf);
-
- if((CommonSettings.SWIFromBIOS) && (NDS_ARM7.BIOS_loaded)) NDS_ARM7.swi_tab = 0;
- else NDS_ARM7.swi_tab = ARM7_swi_tab;
-
+ if (CommonSettings.UseExtBIOS)
+ {
+ // read arm7 bios from inputfile and flag it if it succeeds
+ FILE *arm7inf = fopen(CommonSettings.ARM7BIOS, "rb");
+ if (fread(MMU.ARM7_BIOS, 1, 16384, arm7inf) == 16384)
+ NDS_ARM7.BIOS_loaded = true;
+ fclose(arm7inf);
+ }
+
+ // choose to use SWI emulation or routines from bios
+ if (CommonSettings.SWIFromBIOS && NDS_ARM7.BIOS_loaded)
+ {
+ NDS_ARM7.swi_tab = 0;
+
+ // if we used routines from bios, apply patches
if (CommonSettings.PatchSWI3)
_MMU_write16<ARMCPU_ARM7>(0x00002F08, 0x4770);
-
- //INFO("ARM7 BIOS is %s.\n", NDS_ARM7.BIOS_loaded?"loaded":"failed");
}
else
- {
- NDS_ARM7.swi_tab = ARM7_swi_tab;
+ NDS_ARM7.swi_tab = ARM_swi_tab[ARMCPU_ARM7];
+
+ if (!NDS_ARM7.BIOS_loaded)
+ {
+ // fake bios content, critical to normal operations, since we dont have a real bios.
#if 0
+ // someone please document what is in progress here
// TODO
- T1WriteLong(MMU.ARM7_BIOS, 0x0000, 0xEAFFFFFE); // loop for Reset !!!
- T1WriteLong(MMU.ARM7_BIOS, 0x0004, 0xEAFFFFFE); // loop for Undef instr expection
- T1WriteLong(MMU.ARM7_BIOS, 0x0008, 0xEA00009C); // SWI
- T1WriteLong(MMU.ARM7_BIOS, 0x000C, 0xEAFFFFFE); // loop for Prefetch Abort
- T1WriteLong(MMU.ARM7_BIOS, 0x0010, 0xEAFFFFFE); // loop for Data Abort
- T1WriteLong(MMU.ARM7_BIOS, 0x0014, 0x00000000); // Reserved
- T1WriteLong(MMU.ARM7_BIOS, 0x001C, 0x00000000); // Fast IRQ
+ T1WriteLong(MMU.ARM7_BIOS, 0x0000, 0xEAFFFFFE); // loop for Reset !!!
+ T1WriteLong(MMU.ARM7_BIOS, 0x0004, 0xEAFFFFFE); // loop for Undef instr expection
+ T1WriteLong(MMU.ARM7_BIOS, 0x0008, 0xEA00009C); // SWI
+ T1WriteLong(MMU.ARM7_BIOS, 0x000C, 0xEAFFFFFE); // loop for Prefetch Abort
+ T1WriteLong(MMU.ARM7_BIOS, 0x0010, 0xEAFFFFFE); // loop for Data Abort
+ T1WriteLong(MMU.ARM7_BIOS, 0x0014, 0x00000000); // Reserved
+ T1WriteLong(MMU.ARM7_BIOS, 0x001C, 0x00000000); // Fast IRQ
#endif
T1WriteLong(MMU.ARM7_BIOS, 0x0000, 0xE25EF002);
T1WriteLong(MMU.ARM7_BIOS, 0x0018, 0xEA000000);
@@ -2259,52 +900,75 @@
T1WriteLong(MMU.ARM7_BIOS, 0x0030, 0xE8BD500F);
T1WriteLong(MMU.ARM7_BIOS, 0x0034, 0xE25EF004);
}
-
- //ARM9 BIOS IRQ HANDLER
- if(CommonSettings.UseExtBIOS == true)
- inf = fopen(CommonSettings.ARM9BIOS,"rb");
- else
- inf = NULL;
-
- if(inf)
- {
- if (fread(MMU.ARM9_BIOS,1,4096,inf) == 4096) NDS_ARM9.BIOS_loaded = true;
- fclose(inf);
-
- if((CommonSettings.SWIFromBIOS) && (NDS_ARM9.BIOS_loaded)) NDS_ARM9.swi_tab = 0;
- else NDS_ARM9.swi_tab = ARM9_swi_tab;
-
+}
+
+static void PrepareBiosARM9()
+{
+ memset(MMU.ARM9_BIOS, 0, sizeof(MMU.ARM9_BIOS));
+ NDS_ARM9.BIOS_loaded = false;
+ if (CommonSettings.UseExtBIOS)
+ {
+ // read arm9 bios from inputfile and flag it if it succeeds
+ FILE *arm9inf = fopen(CommonSettings.ARM9BIOS, "rb");
+ if (fread(MMU.ARM9_BIOS, 1, 4096, arm9inf) == 4096)
+ NDS_ARM9.BIOS_loaded = true;
+ fclose(arm9inf);
+ }
+
+ // choose to use SWI emulation or routines from bios
+ if (CommonSettings.SWIFromBIOS && NDS_ARM9.BIOS_loaded)
+ {
+ NDS_ARM9.swi_tab = 0;
+
+ // if we used routines from bios, apply patches
if (CommonSettings.PatchSWI3)
_MMU_write16<ARMCPU_ARM9>(0xFFFF07CC, 0x4770);
-
- //INFO("ARM9 BIOS is %s.\n", NDS_ARM9.BIOS_loaded?"loaded":"failed");
}
else
- {
- NDS_ARM9.swi_tab = ARM9_swi_tab;
-
- //bios chains data abort to fast irq
-
- //exception vectors:
- T1WriteLong(MMU.ARM9_BIOS, 0x0000, 0xEAFFFFFE); // (infinite loop for) Reset !!!
- //T1WriteLong(MMU.ARM9_BIOS, 0x0004, 0xEAFFFFFE); // (infinite loop for) Undefined instruction
- T1WriteLong(MMU.ARM9_BIOS, 0x0004, 0xEA000004); // Undefined instruction -> Fast IRQ (just guessing)
- T1WriteLong(MMU.ARM9_BIOS, 0x0008, 0xEA00009C); // SWI -> ?????
- T1WriteLong(MMU.ARM9_BIOS, 0x000C, 0xEAFFFFFE); // (infinite loop for) Prefetch Abort
- T1WriteLong(MMU.ARM9_BIOS, 0x0010, 0xEA000001); // Data Abort -> Fast IRQ
- T1WriteLong(MMU.ARM9_BIOS, 0x0014, 0x00000000); // Reserved
- T1WriteLong(MMU.ARM9_BIOS, 0x0018, 0xEA000095); // Normal IRQ -> 0x0274
- T1WriteLong(MMU.ARM9_BIOS, 0x001C, 0xEA00009D); // Fast IRQ -> 0x0298
+ NDS_ARM9.swi_tab = ARM_swi_tab[ARMCPU_ARM9];
+
+ if (!NDS_ARM9.BIOS_loaded)
+ {
+ // fake bios content, critical to normal operations, since we dont have a real bios.
+ // it'd be cool if we could write this in some kind of assembly language, inline or otherwise, without some bulky dependencies
+ // perhaps we could build it with devkitarm? but thats bulky (offline) dependencies, to be sure..
+
+ // reminder: bios chains data abort to fast irq
+
+ // exception vectors:
+ T1WriteLong(MMU.ARM9_BIOS, 0x0000, 0xEAFFFFFE); // (infinite loop for) Reset !!!
+ //T1WriteLong(MMU.ARM9_BIOS, 0x0004, 0xEAFFFFFE); // (infinite loop for) Undefined instruction
+ T1WriteLong(MMU.ARM9_BIOS, 0x0004, 0xEA000004); // Undefined instruction -> Fast IRQ (just guessing)
+ T1WriteLong(MMU.ARM9_BIOS, 0x0008, 0xEA00009C); // SWI -> ?????
+ T1WriteLong(MMU.ARM9_BIOS, 0x000C, 0xEAFFFFFE); // (infinite loop for) Prefetch Abort
+ T1WriteLong(MMU.ARM9_BIOS, 0x0010, 0xEA000001); // Data Abort -> Fast IRQ
+ T1WriteLong(MMU.ARM9_BIOS, 0x0014, 0x00000000); // Reserved
+ T1WriteLong(MMU.ARM9_BIOS, 0x0018, 0xEA000095); // Normal IRQ -> 0x0274
+ T1WriteLong(MMU.ARM9_BIOS, 0x001C, 0xEA00009D); // Fast IRQ -> 0x0298
+
+ static const uint8_t logo_data[] =
+ {
+ 0x24, 0xFF, 0xAE, 0x51, 0x69, 0x9A, 0xA2, 0x21, 0x3D, 0x84, 0x82, 0x0A, 0x84, 0xE4, 0x09, 0xAD,
+ 0x11, 0x24, 0x8B, 0x98, 0xC0, 0x81, 0x7F, 0x21, 0xA3, 0x52, 0xBE, 0x19, 0x93, 0x09, 0xCE, 0x20,
+ 0x10, 0x46, 0x4A, 0x4A, 0xF8, 0x27, 0x31, 0xEC, 0x58, 0xC7, 0xE8, 0x33, 0x82, 0xE3, 0xCE, 0xBF,
+ 0x85, 0xF4, 0xDF, 0x94, 0xCE, 0x4B, 0x09, 0xC1, 0x94, 0x56, 0x8A, 0xC0, 0x13, 0x72, 0xA7, 0xFC,
+ 0x9F, 0x84, 0x4D, 0x73, 0xA3, 0xCA, 0x9A, 0x61, 0x58, 0x97, 0xA3, 0x27, 0xFC, 0x03, 0x98, 0x76,
+ 0x23, 0x1D, 0xC7, 0x61, 0x03, 0x04, 0xAE, 0x56, 0xBF, 0x38, 0x84, 0x00, 0x40, 0xA7, 0x0E, 0xFD,
+ 0xFF, 0x52, 0xFE, 0x03, 0x6F, 0x95, 0x30, 0xF1, 0x97, 0xFB, 0xC0, 0x85, 0x60, 0xD6, 0x80, 0x25,
+ 0xA9, 0x63, 0xBE, 0x03, 0x01, 0x4E, 0x38, 0xE2, 0xF9, 0xA2, 0x34, 0xFF, 0xBB, 0x3E, 0x03, 0x44,
+ 0x78, 0x00, 0x90, 0xCB, 0x88, 0x11, 0x3A, 0x94, 0x65, 0xC0, 0x7C, 0x63, 0x87, 0xF0, 0x3C, 0xAF,
+ 0xD6, 0x25, 0xE4, 0x8B, 0x38, 0x0A, 0xAC, 0x72, 0x21, 0xD4, 0xF8, 0x07
+ };
// logo (do some games fail to boot without this? example?)
- for (int t = 0; t < 0x9C; t++)
+ for (int t = 0; t < 0x9C; ++t)
MMU.ARM9_BIOS[t + 0x20] = logo_data[t];
//...0xBC:
- //(now what goes in this gap??)
-
- //IRQ handler: get dtcm address and jump to a vector in it
+ // (now what goes in this gap??)
+
+ // IRQ handler: get dtcm address and jump to a vector in it
T1WriteLong(MMU.ARM9_BIOS, 0x0274, 0xE92D500F); //STMDB SP!, {R0-R3,R12,LR}
T1WriteLong(MMU.ARM9_BIOS, 0x0278, 0xEE190F11); //MRC CP15, 0, R0, CR9, CR1, 0
T1WriteLong(MMU.ARM9_BIOS, 0x027C, 0xE1A00620); //MOV R0, R0, LSR #C
@@ -2313,81 +977,100 @@
T1WriteLong(MMU.ARM9_BIOS, 0x0288, 0xE28FE000); //ADD LR, PC, #0
T1WriteLong(MMU.ARM9_BIOS, 0x028C, 0xE510F004); //LDR PC, [R0, -#4]
- //????
- T1WriteLong(MMU.ARM9_BIOS, 0x0290, 0xE8BD500F); //LDMIA SP!, {R0-R3,R12,LR}
- T1WriteLong(MMU.ARM9_BIOS, 0x0294, 0xE25EF004); //SUBS PC, LR, #4
-
- //-------
- //FIQ and abort exception handler
- //TODO - this code is copied from the bios. refactor it
- //friendly reminder: to calculate an immediate offset: encoded = (desired_address-cur_address-8)
-
- T1WriteLong(MMU.ARM9_BIOS, 0x0298, 0xE10FD000); //MRS SP, CPSR
- T1WriteLong(MMU.ARM9_BIOS, 0x029C, 0xE38DD0C0); //ORR SP, SP, #C0
-
- T1WriteLong(MMU.ARM9_BIOS, 0x02A0, 0xE12FF00D); //MSR CPSR_fsxc, SP
- T1WriteLong(MMU.ARM9_BIOS, 0x02A4, 0xE59FD000 | (0x2D4-0x2A4-8)); //LDR SP, [FFFF02D4]
- T1WriteLong(MMU.ARM9_BIOS, 0x02A8, 0xE28DD001); //ADD SP, SP, #1
- T1WriteLong(MMU.ARM9_BIOS, 0x02AC, 0xE92D5000); //STMDB SP!, {R12,LR}
-
- T1WriteLong(MMU.ARM9_BIOS, 0x02B0, 0xE14FE000); //MRS LR, SPSR
- T1WriteLong(MMU.ARM9_BIOS, 0x02B4, 0xEE11CF10); //MRC CP15, 0, R12, CR1, CR0, 0
- T1WriteLong(MMU.ARM9_BIOS, 0x02B8, 0xE92D5000); //STMDB SP!, {R12,LR}
- T1WriteLong(MMU.ARM9_BIOS, 0x02BC, 0xE3CCC001); //BIC R12, R12, #1
-
- T1WriteLong(MMU.ARM9_BIOS, 0x02C0, 0xEE01CF10); //MCR CP15, 0, R12, CR1, CR0, 0
- T1WriteLong(MMU.ARM9_BIOS, 0x02C4, 0xE3CDC001); //BIC R12, SP, #1
- T1WriteLong(MMU.ARM9_BIOS, 0x02C8, 0xE59CC010); //LDR R12, [R12, #10]
- T1WriteLong(MMU.ARM9_BIOS, 0x02CC, 0xE35C0000); //CMP R12, #0
-
- T1WriteLong(MMU.ARM9_BIOS, 0x02D0, 0x112FFF3C); //BLXNE R12
- T1WriteLong(MMU.ARM9_BIOS, 0x02D4, 0x027FFD9C); //0x027FFD9C
- //---------
-
- }
-
-#ifdef LOG_ARM7
- if (fp_dis7 != NULL)
- {
- fclose(fp_dis7);
- fp_dis7 = NULL;
- }
- fp_dis7 = fopen("D:\\desmume_dis7.asm", "w");
+ // ????
+ T1WriteLong(MMU.ARM9_BIOS, 0x0290, 0xE8BD500F); // LDMIA SP!, {R0-R3,R12,LR}
+ T1WriteLong(MMU.ARM9_BIOS, 0x0294, 0xE25EF004); // SUBS PC, LR, #4
+
+ // -------
+ // FIQ and abort exception handler
+ // TODO - this code is copied from the bios. refactor it
+ // friendly reminder: to calculate an immediate offset: encoded = (desired_address-cur_address-8)
+
+ T1WriteLong(MMU.ARM9_BIOS, 0x0298, 0xE10FD000); // MRS SP, CPSR
+ T1WriteLong(MMU.ARM9_BIOS, 0x029C, 0xE38DD0C0); // ORR SP, SP, #C0
+
+ T1WriteLong(MMU.ARM9_BIOS, 0x02A0, 0xE12FF00D); // MSR CPSR_fsxc, SP
+ T1WriteLong(MMU.ARM9_BIOS, 0x02A4, 0xE59FD028); // LDR SP, [FFFF02D4]
+ T1WriteLong(MMU.ARM9_BIOS, 0x02A8, 0xE28DD001); // ADD SP, SP, #1
+ T1WriteLong(MMU.ARM9_BIOS, 0x02AC, 0xE92D5000); // STMDB SP!, {R12,LR}
+
+ T1WriteLong(MMU.ARM9_BIOS, 0x02B0, 0xE14FE000); // MRS LR, SPSR
+ T1WriteLong(MMU.ARM9_BIOS, 0x02B4, 0xEE11CF10); // MRC CP15, 0, R12, CR1, CR0, 0
+ T1WriteLong(MMU.ARM9_BIOS, 0x02B8, 0xE92D5000); // STMDB SP!, {R12,LR}
+ T1WriteLong(MMU.ARM9_BIOS, 0x02BC, 0xE3CCC001); // BIC R12, R12, #1
+
+ T1WriteLong(MMU.ARM9_BIOS, 0x02C0, 0xEE01CF10); // MCR CP15, 0, R12, CR1, CR0, 0
+ T1WriteLong(MMU.ARM9_BIOS, 0x02C4, 0xE3CDC001); // BIC R12, SP, #1
+ T1WriteLong(MMU.ARM9_BIOS, 0x02C8, 0xE59CC010); // LDR R12, [R12, #10]
+ T1WriteLong(MMU.ARM9_BIOS, 0x02CC, 0xE35C0000); // CMP R12, #0
+
+ T1WriteLong(MMU.ARM9_BIOS, 0x02D0, 0x112FFF3C); // BLXNE R12
+ T1WriteLong(MMU.ARM9_BIOS, 0x02D4, 0x027FFD9C); // 0x027FFD9C
+ // ---------
+ }
+}
+
+void NDS_Reset()
+{
+ singleStep = false;
+ bool fw_success = false;
+ auto header = NDS_getROMHeader();
+
+ if (!header)
+ return;
+
+ nds.sleeping = false;
+ nds.cardEjected = false;
+ nds.freezeBus = 0;
+
+ nds_timer = 0;
+ nds_arm9_timer = 0;
+ nds_arm7_timer = 0;
+
+ SPU_DeInit();
+
+ MMU_Reset();
+
+#ifdef HAVE_JIT
+ arm_jit_reset(CommonSettings.use_jit);
#endif
-#ifdef LOG_ARM9
- if (fp_dis9 != NULL)
- {
- fclose(fp_dis9);
- fp_dis9 = NULL;
- }
- fp_dis9 = fopen("D:\\desmume_dis9.asm", "w");
-#endif
-
- if (firmware)
- {
- delete firmware;
- firmware = NULL;
- }
- firmware = new CFIRMWARE();
+ PrepareBiosARM7();
+ PrepareBiosARM9();
+
+ // according to smea, this is initialized to 3 by the time we get into a user game program. who does this?
+ // well, the firmware load process is about to write a boot program into SIWRAM for the arm7. so we need it setup by now.
+ // but, this is a bit weird.. I would be expecting the bioses to do that. maybe we have some more detail to emulate.
+ // * is this setting the default, or does the bios do it before loading the firmware programs?
+ // at any, it's important that this be done long before the user code ever runs
+ _MMU_write08<ARMCPU_ARM9>(REG_WRAMCNT, 3);
+
+ firmware.reset(new CFIRMWARE());
fw_success = firmware->load();
+
if (NDS_ARM7.BIOS_loaded && NDS_ARM9.BIOS_loaded && CommonSettings.BootFromFirmware && fw_success)
{
- // Copy secure area to memory if needed
- if ((header->ARM9src >= 0x4000) && (header->ARM9src < 0x8000))
+ // Copy secure area to memory if needed.
+ // could we get a comment about what's going on here?
+ // how does this stuff get copied before anything ever even runs?
+ // does it get mapped straight to the rom somehow?
+ // This code could be made more clear too.
+ if (header->ARM9src >= 0x4000 && header->ARM9src < 0x8000)
{
- src = header->ARM9src;
- dst = header->ARM9cpy;
+ uint32_t src = header->ARM9src;
+ uint32_t dst = header->ARM9cpy;
uint32_t size = (0x8000 - src) >> 2;
- //INFO("Copy secure area from 0x%08X to 0x%08X (size %i/0x%08X)\n", src, dst, size, size);
- for (uint32_t i = 0; i < size; i++)
+
+ for (uint32_t i = 0; i < size; ++i)
{
_MMU_write32<ARMCPU_ARM9>(dst, T1ReadLong(MMU.CART_ROM, src));
- src += 4; dst += 4;
+ src += 4;
+ dst += 4;
}
}
+ // TODO someone describe why here
if (firmware->patched)
{
armcpu_init(&NDS_ARM7, 0x00000008);
@@ -2395,138 +1078,107 @@
}
else
{
- //INFO("Booting at ARM9: 0x%08X, ARM7: 0x%08X\n", firmware->ARM9bootAddr, firmware->ARM7bootAddr);
- // need for firmware
- //armcpu_init(&NDS_ARM7, 0x00000008);
- //armcpu_init(&NDS_ARM9, 0xFFFF0008);
+ // set the cpus to an initial state with their respective firmware program entrypoints
armcpu_init(&NDS_ARM7, firmware->ARM7bootAddr);
armcpu_init(&NDS_ARM9, firmware->ARM9bootAddr);
}
- _MMU_write08<ARMCPU_ARM9>(0x04000300, 0);
- _MMU_write08<ARMCPU_ARM7>(0x04000300, 0);
+ // set REG_POSTFLG to the value indicating pre-firmware status
+ MMU.ARM9_REG[0x300] = 0;
+ MMU.ARM7_REG[0x300] = 0;
}
else
{
- src = header->ARM9src;
- dst = header->ARM9cpy;
-
- for(uint32_t i = 0; i < (header->ARM9binSize>>2); ++i)
+ // fake firmware boot-up process
+
+ // copy the arm9 program to the address specified by rom header
+ uint32_t src = header->ARM9src;
+ uint32_t dst = header->ARM9cpy;
+ for (uint32_t i = 0; i < (header->ARM9binSize >> 2); ++i)
{
_MMU_write32<ARMCPU_ARM9>(dst, T1ReadLong(MMU.CART_ROM, src));
dst += 4;
src += 4;
}
+ // copy the arm7 program to the address specified by rom header
src = header->ARM7src;
dst = header->ARM7cpy;
- for(uint32_t i = 0; i < (header->ARM7binSize>>2); ++i)
+ for (uint32_t i = 0; i < (header->ARM7binSize >> 2); ++i)
{
_MMU_write32<ARMCPU_ARM7>(dst, T1ReadLong(MMU.CART_ROM, src));
dst += 4;
src += 4;
}
+ // set the cpus to an initial state with their respective programs entrypoints
armcpu_init(&NDS_ARM7, header->ARM7exe);
armcpu_init(&NDS_ARM9, header->ARM9exe);
- _MMU_write08<ARMCPU_ARM9>(REG_POSTFLG, 1);
- _MMU_write08<ARMCPU_ARM7>(REG_POSTFLG, 1);
- }
- //bitbox 4k demo is so stripped down it relies on default stack values
- //otherwise the arm7 will crash before making a sound
- //(these according to gbatek softreset bios docs)
+ // set REG_POSTFLG to the value indicating post-firmware status
+ MMU.ARM9_REG[0x300] = 1;
+ MMU.ARM7_REG[0x300] = 1;
+ }
+
+ // only ARM9 have co-processor
+ reconstruct(&cp15);
+ cp15.reset(&NDS_ARM9);
+
+ // bitbox 4k demo is so stripped down it relies on default stack values
+ // otherwise the arm7 will crash before making a sound
+ // (these according to gbatek softreset bios docs)
NDS_ARM7.R13_svc = 0x0380FFDC;
NDS_ARM7.R13_irq = 0x0380FFB0;
NDS_ARM7.R13_usr = 0x0380FF00;
NDS_ARM7.R[13] = NDS_ARM7.R13_usr;
- //and let's set these for the arm9 while we're at it, though we have no proof
+ // and let's set these for the arm9 while we're at it, though we have no proof
NDS_ARM9.R13_svc = 0x00803FC0;
NDS_ARM9.R13_irq = 0x00803FA0;
NDS_ARM9.R13_usr = 0x00803EC0;
- NDS_ARM9.R13_abt = NDS_ARM9.R13_usr; //?????
- //I think it is wrong to take gbatek's "SYS" and put it in USR--maybe USR doesnt matter.
- //i think SYS is all the misc modes. please verify by setting nonsensical stack values for USR here
+ NDS_ARM9.R13_abt = NDS_ARM9.R13_usr; // ?????
+ // I think it is wrong to take gbatek's "SYS" and put it in USR--maybe USR doesnt matter.
+ // i think SYS is all the misc modes. please verify by setting nonsensical stack values for USR here
NDS_ARM9.R[13] = NDS_ARM9.R13_usr;
- //n.b.: im not sure about all these, I dont know enough about arm9 svc/irq/etc modes
- //and how theyre named in desmume to match them up correctly. i just guessed.
-
- //nds.wifiCycle = 0;
- memset(nds.timerCycle, 0, sizeof(uint64_t) * 2 * 4);
+ // n.b.: im not sure about all these, I dont know enough about arm9 svc/irq/etc modes
+ // and how theyre named in desmume to match them up correctly. i just guessed.
+
+ memset(nds.timerCycle, 0, sizeof(uint64_t) * 8);
nds.old = 0;
- //nds.touchX = nds.touchY = 0;
- //nds.isTouch = 0;
- //nds.debugConsole = CommonSettings.DebugConsole;
- //nds.ensataEmulation = CommonSettings.EnsataEmulation;
- //nds.ensataHandshake = ENSATA_HANDSHAKE_none;
- //nds.ensataIpcSyncCounter = 0;
- SetupMMU(/*nds.Is_DebugConsole()*/false,nds.Is_DSI());
+ SetupMMU(false, nds.Is_DSI());
_MMU_write16<ARMCPU_ARM9>(REG_KEYINPUT, 0x3FF);
_MMU_write16<ARMCPU_ARM7>(REG_KEYINPUT, 0x3FF);
_MMU_write08<ARMCPU_ARM7>(REG_EXTKEYIN, 0x43);
- //LidClosed = false;
- //countLid = 0;
-
- //resetUserInput();
-
- //Setup a copy of the firmware user settings in memory.
- //(this is what the DS firmware would do).
+ // Setup a copy of the firmware user settings in memory.
+ // (this is what the DS firmware would do).
{
uint8_t temp_buffer[NDS_FW_USER_SETTINGS_MEM_BYTE_COUNT];
- int fw_index;
-
- if ( copy_firmware_user_data( temp_buffer, &MMU.fw.data[0])) {
- for ( fw_index = 0; fw_index < NDS_FW_USER_SETTINGS_MEM_BYTE_COUNT; fw_index++)
+
+ if (copy_firmware_user_data(temp_buffer, &MMU.fw.data[0]))
+ for (int fw_index = 0; fw_index < NDS_FW_USER_SETTINGS_MEM_BYTE_COUNT; ++fw_index)
_MMU_write08<ARMCPU_ARM9>(0x027FFC80 + fw_index, temp_buffer[fw_index]);
- }
}
// Copy the whole header to Main RAM 0x27FFE00 on startup. (http://nocash.emubase.de/gbatek.htm#dscartridgeheader)
- //once upon a time this copied 0x90 more. this was thought to be wrong, and changed.
- if(nds.Is_DSI())
- {
- //dsi needs this copied later in memory. there are probably a number of things that get copied to a later location in memory.. thats where the NDS consoles tend to stash stuff.
- for (int i = 0; i < ((0x170)/4); i++)
- _MMU_write32<ARMCPU_ARM9>(0x02FFFE00+i*4, LE_TO_LOCAL_32(((uint32_t*)MMU.CART_ROM)[i]));
+ // once upon a time this copied 0x90 more. this was thought to be wrong, and changed.
+ if (nds.Is_DSI())
+ {
+ // dsi needs this copied later in memory. there are probably a number of things that get copied to a later location in memory.. thats where the NDS consoles tend to stash stuff.
+ for (int i = 0; i < 92; ++i)
+ _MMU_write32<ARMCPU_ARM9>(0x02FFFE00 + i * 4, LE_TO_LOCAL_32(reinterpret_cast<uint32_t *>(MMU.CART_ROM)[i]));
}
else
{
- for (int i = 0; i < ((0x170)/4); i++)
- _MMU_write32<ARMCPU_ARM9>(0x027FFE00+i*4, LE_TO_LOCAL_32(((uint32_t*)MMU.CART_ROM)[i]));
+ for (int i = 0; i < 92; ++i)
+ _MMU_write32<ARMCPU_ARM9>(0x027FFE00 + i * 4, LE_TO_LOCAL_32(reinterpret_cast<uint32_t *>(MMU.CART_ROM)[i]));
}
// Write the header checksum to memory (the firmware needs it to see the cart)
_MMU_write16<ARMCPU_ARM9>(0x027FF808, T1ReadWord(MMU.CART_ROM, 0x15E));
- //--------------------------------
- //setup the homebrew argv
- //this is useful for nitrofs apps which are emulating themselves via cflash
- //struct __argv {
- // int argvMagic; //!< argv magic number, set to 0x5f617267 ('_arg') if valid
- // char *commandLine; //!< base address of command line, set of null terminated strings
- // int length; //!< total length of command line
- // int argc; //!< internal use, number of arguments
- // char **argv; //!< internal use, argv pointer
- //};
- std::string rompath = "fat:/" + path.RomName;
- const uint32_t kCommandline = 0x027E0000;
- //const uint32_t kCommandline = 0x027FFF84;
-
- //
- _MMU_write32<ARMCPU_ARM9>(0x02FFFE70, 0x5f617267);
- _MMU_write32<ARMCPU_ARM9>(0x02FFFE74, kCommandline); //(commandline starts here)
- _MMU_write32<ARMCPU_ARM9>(0x02FFFE78, rompath.size()+1);
- //0x027FFF7C (argc)
- //0x027FFF80 (argv)
- for(size_t i=0;i<rompath.size();i++)
- _MMU_write08<ARMCPU_ARM9>(kCommandline+i, rompath[i]);
- _MMU_write08<ARMCPU_ARM9>(kCommandline+rompath.size(), 0);
- //--------------------------------
-
- if ((firmware->patched) && (CommonSettings.UseExtBIOS == true) && (CommonSettings.BootFromFirmware == true) && (fw_success == true))
+ if (firmware->patched && CommonSettings.UseExtBIOS && CommonSettings.BootFromFirmware && fw_success)
{
// HACK! for flashme
_MMU_write32<ARMCPU_ARM9>(0x27FFE24, firmware->ARM9bootAddr);
@@ -2534,474 +1186,15 @@
}
// make system think it's booted from card -- EXTREMELY IMPORTANT!!! Thanks to cReDiAr
- _MMU_write08<ARMCPU_ARM9>(0x02FFFC40,0x1);
- _MMU_write08<ARMCPU_ARM7>(0x02FFFC40,0x1);
-
- // Save touchscreen calibration info in a structure
- // so we can easily access it at any time
- //TSCal.adc.x1 = _MMU_read16<ARMCPU_ARM7>(0x027FFC80 + 0x58);
- //TSCal.adc.y1 = _MMU_read16<ARMCPU_ARM7>(0x027FFC80 + 0x5A);
- //TSCal.scr.x1 = _MMU_read08<ARMCPU_ARM7>(0x027FFC80 + 0x5C);
- //TSCal.scr.y1 = _MMU_read08<ARMCPU_ARM7>(0x027FFC80 + 0x5D);
- //TSCal.adc.x2 = _MMU_read16<ARMCPU_ARM7>(0x027FFC80 + 0x5E);
- //TSCal.adc.y2 = _MMU_read16<ARMCPU_ARM7>(0x027FFC80 + 0x60);
- //TSCal.scr.x2 = _MMU_read08<ARMCPU_ARM7>(0x027FFC80 + 0x62);
- //TSCal.scr.y2 = _MMU_read08<ARMCPU_ARM7>(0x027FFC80 + 0x63);
-
- //TSCal.adc.width = (TSCal.adc.x2 - TSCal.adc.x1);
- //TSCal.adc.height = (TSCal.adc.y2 - TSCal.adc.y1);
- //TSCal.scr.width = (TSCal.scr.x2 - TSCal.scr.x1);
- //TSCal.scr.height = (TSCal.scr.y2 - TSCal.scr.y1);
-
- //MainScreen.offset = 0;
- //SubScreen.offset = 192;
-
- //_MMU_write32[ARMCPU_ARM9](0x02007FFC, 0xE92D4030);
-
- delete header;
-
- //Screen_Reset();
- //gfx3d_reset();
- //gpu3D->NDS_3D_Reset();
- //slot1Reset();
-
- //WIFI_Reset();
-
- //memcpy(FW_Mac, (MMU.fw.data + 0x36), 6);
+ _MMU_write08<ARMCPU_ARM9>(0x02FFFC40, 0x1);
+ _MMU_write08<ARMCPU_ARM7>(0x02FFFC40, 0x1);
initSchedule();
SPU_ReInit();
}
-/*static std::string MakeInputDisplayString(uint16_t pad, const std::string* Buttons, int count) {
- std::string s;
- for (int x = 0; x < count; x++) {
- if (pad & (1 << x))
- s.append(Buttons[x].size(), ' ');
- else
- s += Buttons[x];
- }
- return s;
-}*/
-
-/*static std::string MakeInputDisplayString(uint16_t pad, uint16_t padExt) {
- const std::string Buttons[] = {"A", "B", "Sl", "St", "R", "L", "U", "D", "Rs", "Ls"};
- const std::string Ext[] = {"X", "Y"};
-
- std::string s = MakeInputDisplayString(pad, Ext, ARRAY_SIZE(Ext));
- s += MakeInputDisplayString(padExt, Buttons, ARRAY_SIZE(Buttons));
-
- return s;
-}*/
-
-
-//buttonstruct<bool> Turbo;
-buttonstruct<int> TurboTime;
-//buttonstruct<bool> AutoHold;
-
-/*void ClearAutoHold() {
-
- for (uint32_t i=0; i < ARRAY_SIZE(AutoHold.array); i++) {
- AutoHold.array[i]=false;
- }
-}*/
-
-
-/*inline uint16_t NDS_getADCTouchPosX(uint16_t scrX)
-{
- // this is a little iffy,
- // we're basically adjusting the ADC results to
- // compensate for how they will be interpreted.
- // the actual system doesn't do this transformation.
- int rv = (scrX - TSCal.scr.x1 + 1) * TSCal.adc.width / TSCal.scr.width + TSCal.adc.x1;
- rv = min(0xFFF, max(0, rv));
- return (uint16_t)rv;
-}*/
-/*inline uint16_t NDS_getADCTouchPosY(uint16_t scrY)
-{
- int rv = (scrY - TSCal.scr.y1 + 1) * TSCal.adc.height / TSCal.scr.height + TSCal.adc.y1;
- rv = min(0xFFF, max(0, rv));
- return (uint16_t)rv;
-}*/
-
-//static UserInput rawUserInput = {}; // requested input, generally what the user is physically pressing
-static UserInput intermediateUserInput; // intermediate buffer for modifications (seperated from finalUserInput for safety reasons)
-static UserInput finalUserInput; // what gets sent to the game and possibly recorded
-bool validToProcessInput = false;
-
-/*const UserInput& NDS_getRawUserInput()
-{
- return rawUserInput;
-}*/
-/*UserInput& NDS_getProcessingUserInput()
-{
- assert(validToProcessInput);
- return intermediateUserInput;
-}*/
-/*bool NDS_isProcessingUserInput()
-{
- return validToProcessInput;
-}*/
-/*const UserInput& NDS_getFinalUserInput()
-{
- return finalUserInput;
-}*/
-
-
-/*static void saveUserInput(EMUFILE* os, UserInput& input)
-{
- os->fwrite((const char*)input.buttons.array, 14);
- writebool(input.touch.isTouch, os);
- write16le(input.touch.touchX, os);
- write16le(input.touch.touchY, os);
- write32le(input.mic.micButtonPressed, os);
-}*/
-static bool loadUserInput(EMUFILE* is, UserInput& input, int)
-{
- is->fread((char*)input.buttons.array, 14);
- readbool(&input.touch.isTouch, is);
- read16le(&input.touch.touchX, is);
- read16le(&input.touch.touchY, is);
- read32le(&input.mic.micButtonPressed, is);
- return true;
-}
-/*static void resetUserInput(UserInput& input)
-{
- memset(&input, 0, sizeof(UserInput));
-}*/
-// (userinput is kind of a misnomer, e.g. finalUserInput has to mirror nds.pad, nds.touchX, etc.)
-/*static void saveUserInput(EMUFILE* os)
-{
- saveUserInput(os, finalUserInput);
- saveUserInput(os, intermediateUserInput); // saved in case a savestate is made during input processing (which Lua could do if nothing else)
- writebool(validToProcessInput, os);
- for(int i = 0; i < 14; i++)
- write32le(TurboTime.array[i], os); // saved to make autofire more tolerable to use with re-recording
-}*/
-static bool loadUserInput(EMUFILE* is, int version)
-{
- bool rv = true;
- rv &= loadUserInput(is, finalUserInput, version);
- rv &= loadUserInput(is, intermediateUserInput, version);
- readbool(&validToProcessInput, is);
- for(int i = 0; i < 14; i++)
- read32le((uint32_t*)&TurboTime.array[i], is);
- return rv;
-}
-/*static void resetUserInput()
-{
- resetUserInput(finalUserInput);
- resetUserInput(intermediateUserInput);
-}*/
-
-/*static inline void gotInputRequest()
-{
- // nobody should set the raw input while we're processing the input.
- // it might not screw anything up but it would be completely useless.
- assert(!validToProcessInput);
-}*/
-
-/*void NDS_setPad(bool R,bool L,bool D,bool U,bool T,bool S,bool B,bool A,bool Y,bool X,bool W,bool E,bool G, bool F)
-{
- gotInputRequest();
- UserButtons& rawButtons = rawUserInput.buttons;
- rawButtons.R = R;
- rawButtons.L = L;
- rawButtons.D = D;
- rawButtons.U = U;
- rawButtons.T = T;
- rawButtons.S = S;
- rawButtons.B = B;
- rawButtons.A = A;
- rawButtons.Y = Y;
- rawButtons.X = X;
- rawButtons.W = W;
- rawButtons.E = E;
- rawButtons.G = G;
- rawButtons.F = F;
-}*/
-/*void NDS_setTouchPos(uint16_t x, uint16_t y)
-{
- gotInputRequest();
- rawUserInput.touch.touchX = NDS_getADCTouchPosX(x);
- rawUserInput.touch.touchY = NDS_getADCTouchPosY(y);
- rawUserInput.touch.isTouch = true;*/
-
- /*if(movieMode != MOVIEMODE_INACTIVE && movieMode != MOVIEMODE_FINISHED)
- {
- // just in case, since the movie only stores 8 bits per touch coord
- rawUserInput.touch.touchX &= 0x0FF0;
- rawUserInput.touch.touchY &= 0x0FF0;
- }*/
-/*
-#ifndef WIN32
- // FIXME: this code should be deleted from here,
- // other platforms should call NDS_beginProcessingInput,NDS_endProcessingInput once per frame instead
- // (see the function called "StepRunLoop_Core" in src/windows/main.cpp),
- // but I'm leaving this here for now since I can't test those other platforms myself.
- nds.touchX = rawUserInput.touch.touchX;
- nds.touchY = rawUserInput.touch.touchY;
- nds.isTouch = 1;
- MMU.ARM7_REG[0x136] &= 0xBF;
-#endif
-}*/
-/*void NDS_releaseTouch()
-{
- gotInputRequest();
- rawUserInput.touch.touchX = 0;
- rawUserInput.touch.touchY = 0;
- rawUserInput.touch.isTouch = false;
-
-#ifndef WIN32
- // FIXME: this code should be deleted from here,
- // other platforms should call NDS_beginProcessingInput,NDS_endProcessingInput once per frame instead
- // (see the function called "StepRunLoop_Core" in src/windows/main.cpp),
- // but I'm leaving this here for now since I can't test those other platforms myself.
- nds.touchX = 0;
- nds.touchY = 0;
- nds.isTouch = 0;
- MMU.ARM7_REG[0x136] |= 0x40;
-#endif
-}*/
-/*void NDS_setMic(bool pressed)
-{
- gotInputRequest();
- rawUserInput.mic.micButtonPressed = (pressed ? true : false);
-}*/
-
-
-//static void NDS_applyFinalInput();
-
-
-/*void NDS_beginProcessingInput()
-{
- // start off from the raw input
- intermediateUserInput = rawUserInput;
-
- // processing is valid now
- validToProcessInput = true;
-}*/
-
-/*void NDS_endProcessingInput()
-{
- // transfer the processed input
- finalUserInput = intermediateUserInput;
-
- // processing is invalid now
- validToProcessInput = false;
-
- // use the final input for a few things right away
- NDS_applyFinalInput();
-}*/
-
-
-
-
-
-
-
-
-/*static void NDS_applyFinalInput()
-{
- const UserInput& input = NDS_getFinalUserInput();
-
- uint16_t pad = (0 |
- ((input.buttons.A ? 0 : 0x80) >> 7) |
- ((input.buttons.B ? 0 : 0x80) >> 6) |
- ((input.buttons.T ? 0 : 0x80) >> 5) |
- ((input.buttons.S ? 0 : 0x80) >> 4) |
- ((input.buttons.R ? 0 : 0x80) >> 3) |
- ((input.buttons.L ? 0 : 0x80) >> 2) |
- ((input.buttons.U ? 0 : 0x80) >> 1) |
- ((input.buttons.D ? 0 : 0x80) ) |
- ((input.buttons.E ? 0 : 0x80) << 1) |
- ((input.buttons.W ? 0 : 0x80) << 2)) ;
-
- ((uint16_t *)MMU.ARM9_REG)[0x130>>1] = (uint16_t)pad;
- ((uint16_t *)MMU.ARM7_REG)[0x130>>1] = (uint16_t)pad;
-
- uint16_t k_cnt = ((uint16_t *)MMU.ARM9_REG)[0x132>>1];
- if ( k_cnt & (1<<14))
- {
- //INFO("ARM9: KeyPad IRQ (pad 0x%04X, cnt 0x%04X (condition %s))\n", pad, k_cnt, k_cnt&(1<<15)?"AND":"OR");
- uint16_t k_cnt_selected = (k_cnt & 0x3F);
- if (k_cnt&(1<<15)) // AND
- {
- if ((~pad & k_cnt_selected) == k_cnt_selected) NDS_makeIrq(ARMCPU_ARM9,IRQ_BIT_KEYPAD);
- }
- else // OR
- {
- if (~pad & k_cnt_selected) NDS_makeIrq(ARMCPU_ARM9,IRQ_BIT_KEYPAD);
- }
- }
-
- k_cnt = ((uint16_t *)MMU.ARM7_REG)[0x132>>1];
- if ( k_cnt & (1<<14))
- {
- //INFO("ARM7: KeyPad IRQ (pad 0x%04X, cnt 0x%04X (condition %s))\n", pad, k_cnt, k_cnt&(1<<15)?"AND":"OR");
- uint16_t k_cnt_selected = (k_cnt & 0x3F);
- if (k_cnt&(1<<15)) // AND
- {
- if ((~pad & k_cnt_selected) == k_cnt_selected) NDS_makeIrq(ARMCPU_ARM7,IRQ_BIT_KEYPAD);
- }
- else // OR
- {
- if (~pad & k_cnt_selected) NDS_makeIrq(ARMCPU_ARM7,IRQ_BIT_KEYPAD);
- }
- }
-
-
- if(input.touch.isTouch)
- {
- nds.touchX = input.touch.touchX;
- nds.touchY = input.touch.touchY;
- nds.isTouch = 1;
-
- MMU.ARM7_REG[0x136] &= 0xBF;
- }
- else
- {
-
- nds.touchX = 0;
- nds.touchY = 0;
- nds.isTouch = 0;
-
- MMU.ARM7_REG[0x136] |= 0x40;
- }
-
-
- if (input.buttons.F && !countLid)
- {
- LidClosed = (!LidClosed) & 0x01;
- if (!LidClosed)
- {
- // SPU_Pause(false);
- NDS_makeIrq(ARMCPU_ARM7,IRQ_BIT_ARM7_FOLD);
-
- }
- //else
- //SPU_Pause(true);
-
- countLid = 30;
- }
- else
- {
- if (countLid > 0)
- countLid--;
- }
-
- uint16_t padExt = (((uint16_t *)MMU.ARM7_REG)[0x136>>1] & 0x0070) |
- ((input.buttons.X ? 0 : 0x80) >> 7) |
- ((input.buttons.Y ? 0 : 0x80) >> 6) |
- ((input.buttons.G ? 0 : 0x80) >> 4) |
- ((LidClosed) << 7) |
- 0x0034;
-
- ((uint16_t *)MMU.ARM7_REG)[0x136>>1] = (uint16_t)padExt;
-
- InputDisplayString=MakeInputDisplayString(padExt, pad);
-
- //put into the format we want for the movie system
- //fRLDUTSBAYXWEg
- //we don't really need nds.pad anymore, but removing it would be a pain
-
- nds.pad =
- ((input.buttons.R ? 1 : 0) << 12)|
- ((input.buttons.L ? 1 : 0) << 11)|
- ((input.buttons.D ? 1 : 0) << 10)|
- ((input.buttons.U ? 1 : 0) << 9)|
- ((input.buttons.T ? 1 : 0) << 8)|
- ((input.buttons.S ? 1 : 0) << 7)|
- ((input.buttons.B ? 1 : 0) << 6)|
- ((input.buttons.A ? 1 : 0) << 5)|
- ((input.buttons.Y ? 1 : 0) << 4)|
- ((input.buttons.X ? 1 : 0) << 3)|
- ((input.buttons.W ? 1 : 0) << 2)|
- ((input.buttons.E ? 1 : 0) << 1);
-
- // TODO: low power IRQ
-}*/
-
-
-/*void NDS_suspendProcessingInput(bool suspend)
-{
- static int suspendCount = 0;
- if(suspend)
- {
- // enter non-processing block
- assert(validToProcessInput);
- validToProcessInput = false;
- suspendCount++;
- }
- else if(suspendCount)
- {
- // exit non-processing block
- validToProcessInput = true;
- suspendCount--;
- }
- else
- {
- // unwound past first time -> not processing
- validToProcessInput = false;
- }
-}*/
-
-
-/*void emu_halt() {
- //printf("halting emu: ARM9 PC=%08X/%08X, ARM7 PC=%08X/%08X\n", NDS_ARM9.R[15], NDS_ARM9.instruct_adr, NDS_ARM7.R[15], NDS_ARM7.instruct_adr);
- execute = false;
-#ifdef LOG_ARM9
- if (fp_dis9)
- {
- char buf[256] = { 0 };
- sprintf(buf, "halting emu: ARM9 PC=%08X/%08X\n", NDS_ARM9.R[15], NDS_ARM9.instruct_adr);
- fwrite(buf, 1, strlen(buf), fp_dis9);
- INFO("ARM9 halted\n");
- }
-#endif
-
-#ifdef LOG_ARM7
- if (fp_dis7)
- {
- char buf[256] = { 0 };
- sprintf(buf, "halting emu: ARM7 PC=%08X/%08X\n", NDS_ARM7.R[15], NDS_ARM7.instruct_adr);
- fwrite(buf, 1, strlen(buf), fp_dis7);
- INFO("ARM7 halted\n");
- }
-#endif
-}*/
-
-//returns true if exmemcnt specifies satisfactory parameters for the device, which calls this function
-/*bool ValidateSlot2Access(uint32_t procnum, uint32_t demandSRAMSpeed, uint32_t demand1stROMSpeed, uint32_t demand2ndROMSpeed, int clockbits)
-{
- static const uint32_t _sramSpeeds[] = {10,8,6,18};
- static const uint32_t _rom1Speeds[] = {10,8,6,18};
- static const uint32_t _rom2Speeds[] = {6,4};
- uint16_t exmemcnt = T1ReadWord(MMU.MMU_MEM[procnum][0x40], 0x204);
- uint16_t exmemcnt9 = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x204);
- uint32_t arm7access = (exmemcnt9 & EXMEMCNT_MASK_SLOT2_ARM7);
- uint32_t sramSpeed = _sramSpeeds[(exmemcnt & EXMEMCNT_MASK_SLOT2_SRAM_TIME)];
- uint32_t romSpeed1 = _rom1Speeds[(exmemcnt & EXMEMCNT_MASK_SLOT2_ROM_1ST_TIME)>>2];
- uint32_t romSpeed2 = _rom2Speeds[(exmemcnt & EXMEMCNT_MASK_SLOT2_ROM_2ND_TIME)>>4];
- uint32_t curclockbits = (exmemcnt & EXMEMCNT_MASK_SLOT2_CLOCKRATE)>>5;
-
- if(procnum==ARMCPU_ARM9 && arm7access) return false;
- if(procnum==ARMCPU_ARM7 && !arm7access) return false;
-
- //what we're interested in here is whether the rom/ram are too low -> too fast. then accesses won't have enough time to work.
- //i'm not sure if this gives us enough flexibility, but it is good enough for now.
- //should make the arguments to this function bitmasks later if we need better.
- if(sramSpeed < demandSRAMSpeed) return false;
- if(romSpeed1 < demand1stROMSpeed) return false;
- if(romSpeed2 < demand2ndROMSpeed) return false;
-
- if(clockbits != -1 && clockbits != (int)curclockbits) return false;
-
- return true;
-}*/
-
-//these templates needed to be instantiated manually
+// these templates needed to be instantiated manually
template void NDS_exec<false>(int32_t nb);
template void NDS_exec<true>(int32_t nb);
--- a/src/in_2sf/desmume/NDSSystem.h
+++ b/src/in_2sf/desmume/NDSSystem.h
@@ -1,6 +1,6 @@
/*
Copyright (C) 2006 yopyop
- Copyright (C) 2008-2012 DeSmuME team
+ Copyright (C) 2008-2013 DeSmuME team
This file is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -19,28 +19,22 @@
#ifndef NDSSYSTEM_H
#define NDSSYSTEM_H
+#include <memory>
+#include <string>
#include <cstring>
-
#include "armcpu.h"
#include "MMU.h"
-//#include "driver.h"
-//#include "GPU.h"
#include "SPU.h"
#include "mem.h"
-//#include "wifi.h"
#include "emufile.h"
#include "firmware.h"
-#include <string>
-
-#if defined(_WINDOWS) && !defined(WXPORT)
-#include "pathsettings.h"
-#endif
-
-template<typename Type>
-struct buttonstruct {
- union {
- struct {
+template<typename Type> struct buttonstruct
+{
+ union
+ {
+ struct
+ {
// changing the order of these fields would break stuff
//fRLDUTSBAYXWEg
Type G; // debug
@@ -62,100 +56,64 @@
};
};
-//extern buttonstruct<bool> Turbo;
-extern buttonstruct<int> TurboTime;
-//extern buttonstruct<bool> AutoHold;
-
-//int NDS_WritePNG(const char *fname);
-
extern volatile bool execute;
-//extern bool click;
-
-/*
- * The firmware language values
- */
-/*#define NDS_FW_LANG_JAP 0
-#define NDS_FW_LANG_ENG 1
-#define NDS_FW_LANG_FRE 2
-#define NDS_FW_LANG_GER 3
-#define NDS_FW_LANG_ITA 4
-#define NDS_FW_LANG_SPA 5
-#define NDS_FW_LANG_CHI 6
-#define NDS_FW_LANG_RES 7*/
-
-
-//#define LOG_ARM9
-//#define LOG_ARM7
struct NDS_header
{
- char gameTile[12];
- char gameCode[4];
- uint16_t makerCode;
- uint8_t unitCode;
- uint8_t deviceCode;
- uint8_t cardSize;
- uint8_t cardInfo[8];
- uint8_t flags;
- uint8_t romversion;
-
- uint32_t ARM9src;
- uint32_t ARM9exe;
- uint32_t ARM9cpy;
- uint32_t ARM9binSize;
-
- uint32_t ARM7src;
- uint32_t ARM7exe;
- uint32_t ARM7cpy;
- uint32_t ARM7binSize;
-
- uint32_t FNameTblOff;
- uint32_t FNameTblSize;
-
- uint32_t FATOff;
- uint32_t FATSize;
-
- uint32_t ARM9OverlayOff;
- uint32_t ARM9OverlaySize;
- uint32_t ARM7OverlayOff;
- uint32_t ARM7OverlaySize;
-
- uint32_t unknown2a;
- uint32_t unknown2b;
-
- uint32_t IconOff;
- uint16_t CRC16;
- uint16_t ROMtimeout;
- uint32_t ARM9unk;
- uint32_t ARM7unk;
-
- uint8_t unknown3c[8];
- uint32_t ROMSize;
- uint32_t HeaderSize;
- uint8_t unknown5[56];
- uint8_t logo[156];
- uint16_t logoCRC16;
- uint16_t headerCRC16;
- uint8_t reserved[160];
-};
-
-//extern void debug();
-//void emu_halt();
+ char gameTile[12];
+ char gameCode[4];
+ uint16_t makerCode;
+ uint8_t unitCode;
+ uint8_t deviceCode;
+ uint8_t cardSize;
+ uint8_t cardInfo[8];
+ uint8_t flags;
+ uint8_t romversion;
+
+ uint32_t ARM9src;
+ uint32_t ARM9exe;
+ uint32_t ARM9cpy;
+ uint32_t ARM9binSize;
+
+ uint32_t ARM7src;
+ uint32_t ARM7exe;
+ uint32_t ARM7cpy;
+ uint32_t ARM7binSize;
+
+ uint32_t FNameTblOff;
+ uint32_t FNameTblSize;
+
+ uint32_t FATOff;
+ uint32_t FATSize;
+
+ uint32_t ARM9OverlayOff;
+ uint32_t ARM9OverlaySize;
+ uint32_t ARM7OverlayOff;
+ uint32_t ARM7OverlaySize;
+
+ uint32_t unknown2a;
+ uint32_t unknown2b;
+
+ uint32_t IconOff;
+ uint16_t CRC16;
+ uint16_t ROMtimeout;
+ uint32_t ARM9unk;
+ uint32_t ARM7unk;
+
+ uint8_t unknown3c[8];
+ uint32_t ROMSize;
+ uint32_t HeaderSize;
+ uint8_t unknown5[56];
+ uint8_t logo[156];
+ uint16_t logoCRC16;
+ uint16_t headerCRC16;
+ uint8_t reserved[160];
+};
extern uint64_t nds_timer;
void NDS_Reschedule();
-//void NDS_RescheduleGXFIFO(uint32_t cost);
void NDS_RescheduleDMA();
void NDS_RescheduleTimers();
-
-/*enum ENSATA_HANDSHAKE
-{
- ENSATA_HANDSHAKE_none = 0,
- ENSATA_HANDSHAKE_query = 1,
- ENSATA_HANDSHAKE_ack = 2,
- ENSATA_HANDSHAKE_confirm = 3,
- ENSATA_HANDSHAKE_complete = 4
-};*/
enum NDS_CONSOLE_TYPE
{
@@ -167,16 +125,10 @@
struct NDSSystem
{
- //int32_t wifiCycle;
int32_t cycles;
uint64_t timerCycle[2][4];
uint32_t VCount;
uint32_t old;
-
- //uint16_t touchX;
- //uint16_t touchY;
- //bool isTouch;
- //uint16_t pad;
uint8_t *FW_ARM9BootCode;
uint8_t *FW_ARM7BootCode;
@@ -189,92 +141,41 @@
bool cardEjected;
uint32_t freezeBus;
- //this is not essential NDS runtime state.
- //it was perhaps a mistake to put it here.
- //it is far less important than the above.
- //maybe I should move it.
- //int32_t idleCycles[2];
- //int32_t runCycleCollector[2][16];
- //int32_t idleFrameCounter;
- //int32_t cpuloopIterationCount; //counts the number of times during a frame that a reschedule happened
-
- //if the game was booted on a debug console, this is set
- //bool debugConsole;
-
- //console type must be copied in when the system boots. it can't be changed on the fly.
+ // console type must be copied in when the system boots. it can't be changed on the fly.
int ConsoleType;
- bool Is_DSI() { return ConsoleType == NDS_CONSOLE_TYPE_DSI; }
-
- //set if the user requests ensata emulation
- //bool ensataEmulation;
-
- //there is a hack in the ipc sync for ensata. this tracks its state
- //uint32_t ensataIpcSyncCounter;
-
- //maintains the state of the ensata handshaking protocol
- //uint32_t ensataHandshake;
-
- /*struct {
- uint8_t lcd, gpuMain, gfx3d_render, gfx3d_geometry, gpuSub, dispswap;
- } power1;*/ //POWCNT1
-
- /*struct {
- uint8_t speakers, wifi*/ /*(initial value=0)*//*;
- } power2;*/ //POWCNT2
-
- bool isInVblank() const { return VCount >= 192; }
- bool isIn3dVblank() const { return VCount >= 192 && VCount<215; }
-};
-
-/** /brief A touchscreen calibration point.
- */
-/*struct NDS_fw_touchscreen_cal {
- uint16_t adc_x;
- uint16_t adc_y;
-
- uint8_t screen_x;
- uint8_t screen_y;
-};*/
+ bool Is_DSI() { return this->ConsoleType == NDS_CONSOLE_TYPE_DSI; }
+
+ bool isInVblank() const { return this->VCount >= 192; }
+ bool isIn3dVblank() const { return this->VCount >= 192 && this->VCount < 215; }
+};
#define MAX_FW_NICKNAME_LENGTH 10
#define MAX_FW_MESSAGE_LENGTH 26
-struct NDS_fw_config_data {
- NDS_CONSOLE_TYPE ds_type;
-
- uint8_t fav_colour;
- uint8_t birth_month;
- uint8_t birth_day;
-
- uint16_t nickname[MAX_FW_NICKNAME_LENGTH];
- uint8_t nickname_len;
-
- uint16_t message[MAX_FW_MESSAGE_LENGTH];
- uint8_t message_len;
-
- uint8_t language;
-
- /* touchscreen calibration */
- //struct NDS_fw_touchscreen_cal touch_cal[2];
+struct NDS_fw_config_data
+{
+ NDS_CONSOLE_TYPE ds_type;
+
+ uint8_t fav_colour;
+ uint8_t birth_month;
+ uint8_t birth_day;
+
+ uint16_t nickname[MAX_FW_NICKNAME_LENGTH];
+ uint8_t nickname_len;
+
+ uint16_t message[MAX_FW_MESSAGE_LENGTH];
+ uint8_t message_len;
+
+ uint8_t language;
};
extern NDSSystem nds;
-#ifdef GDB_STUB
-int NDS_Init( struct armcpu_memory_iface *arm9_mem_if,
- struct armcpu_ctrl_iface **arm9_ctrl_iface,
- struct armcpu_memory_iface *arm7_mem_if,
- struct armcpu_ctrl_iface **arm7_ctrl_iface);
-#else
int NDS_Init ();
-#endif
-
-//void Desmume_InitOnce();
void NDS_DeInit();
bool NDS_SetROM(uint8_t * rom, uint32_t mask);
-NDS_header * NDS_getROMHeader();
struct RomBanner
{
@@ -285,96 +186,70 @@
uint8_t bitmap[0x200]; //Icon Bitmap (32x32 pix) (4x4 tiles, each 4x8 bytes, 4bit depth)
uint16_t palette[0x10]; //Icon Palette (16 colors, 16bit, range 0000h-7FFFh) (Color 0 is transparent, so the 1st palette entry is ignored)
enum { NUM_TITLES = 6 };
- union {
- struct {
- uint16_t title_jp[0x80]; //Title 0 Japanese (128 characters, 16bit Unicode)
- uint16_t title_en[0x80]; //Title 1 English ("")
- uint16_t title_fr[0x80]; //Title 2 French ("")
- uint16_t title_de[0x80]; //Title 3 German ("")
- uint16_t title_it[0x80]; //Title 4 Italian ("")
- uint16_t title_es[0x80]; //Title 5 Spanish ("")
+ union
+ {
+ struct
+ {
+ uint16_t title_jp[0x80]; // Title 0 Japanese (128 characters, 16bit Unicode)
+ uint16_t title_en[0x80]; // Title 1 English ("")
+ uint16_t title_fr[0x80]; // Title 2 French ("")
+ uint16_t title_de[0x80]; // Title 3 German ("")
+ uint16_t title_it[0x80]; // Title 4 Italian ("")
+ uint16_t title_es[0x80]; // Title 5 Spanish ("")
};
uint16_t titles[NUM_TITLES][0x80];
};
uint8_t end0xFF[0x1C0];
- //840h ? (Maybe newer/chinese firmware do also support chinese title?)
- //840h - End of Icon/Title structure (next 1C0h bytes usually FFh-filled)
+ //840h ? (Maybe newer/chinese firmware do also support chinese title?)
+ //840h - End of Icon/Title structure (next 1C0h bytes usually FFh-filled)
};
struct GameInfo
{
- GameInfo()
- : romdata(NULL)
- {}
-
- void loadData(char* buf, int size)
- {
- resize(size);
- memcpy(romdata,buf,size);
- romsize = (uint32_t)size;
- fillGap();
+ GameInfo() : romdata() { }
+
+ void loadData(char *buf, int size)
+ {
+ this->resize(size);
+ memcpy(&this->romdata[0], buf, size);
+ this->romsize = static_cast<uint32_t>(size);
+ this->fillGap();
}
void fillGap()
{
- memset(romdata+romsize,0xFF,allocatedSize-romsize);
+ memset(&this->romdata[this->romsize], 0xFF, this->allocatedSize - this->romsize);
}
- void resize(int size) {
- if(romdata != NULL) delete[] romdata;
-
- //calculate the necessary mask for the requested size
- mask = size-1;
- mask |= (mask >>1);
- mask |= (mask >>2);
- mask |= (mask >>4);
- mask |= (mask >>8);
- mask |= (mask >>16);
-
- //now, we actually need to over-allocate, because bytes from anywhere protected by that mask
- //could be read from the rom
- allocatedSize = mask+4;
-
- romdata = new char[allocatedSize];
- romsize = size;
+ void resize(int size)
+ {
+ // calculate the necessary mask for the requested size
+ mask = size - 1;
+ mask |= mask >> 1;
+ mask |= mask >> 2;
+ mask |= mask >> 4;
+ mask |= mask >> 8;
+ mask |= mask >> 16;
+
+ // now, we actually need to over-allocate, because bytes from anywhere protected by that mask
+ // could be read from the rom
+ this->allocatedSize = mask + 4;
+
+ this->romdata.reset(new char[allocatedSize]);
+ this->romsize = size;
}
uint32_t crc;
NDS_header header;
char ROMserial[20];
char ROMname[20];
- //char ROMfullName[7][0x100];
- //void populate();
- char* romdata;
+ std::unique_ptr<char[]> romdata;
uint32_t romsize;
uint32_t allocatedSize;
uint32_t mask;
- //const RomBanner& getRomBanner();
- //bool hasRomBanner();
bool isHomebrew;
};
-/*typedef struct TSCalInfo
-{
- struct adc
- {
- uint16_t x1, x2;
- uint16_t y1, y2;
- uint16_t width;
- uint16_t height;
- } adc;
-
- struct scr
- {
- uint8_t x1, x2;
- uint8_t y1, y2;
- uint16_t width;
- uint16_t height;
- } scr;
-
-} TSCalInfo;*/
-
extern GameInfo gameInfo;
-
struct UserButtons : buttonstruct<bool>
{
@@ -396,126 +271,36 @@
UserMicrophone mic;
};
-// set physical user input
-// these functions merely request the input to be changed.
-// the actual change happens later at a specific time during the frame.
-// this is to minimize the risk of desyncs.
-//void NDS_setTouchPos(uint16_t x, uint16_t y);
-//void NDS_releaseTouch();
-//void NDS_setPad(bool right,bool left,bool down,bool up,bool select,bool start,bool B,bool A,bool Y,bool X,bool leftShoulder,bool rightShoulder,bool debug, bool lid);
-//void NDS_setMic(bool pressed);
-
-// get physical user input
-// not including the results of autofire/etc.
-// the effects of calls to "set physical user input" functions will be immediately reflected here though.
-//const UserInput& NDS_getRawUserInput();
-//const UserInput& NDS_getPrevRawUserInput();
-
-// get final (fully processed) user input
-// this should match whatever was or would be sent to the game
-//const UserInput& NDS_getFinalUserInput();
-
-// set/get to-be-processed or in-the-middle-of-being-processed user input
-// to process input, simply call this function and edit the return value.
-// (applying autofire is one example of processing the input.)
-// (movie playback is another example.)
-// this must be done after the raw user input is set
-// and before that input is sent to the game's memory.
-//UserInput& NDS_getProcessingUserInput();
-//bool NDS_isProcessingUserInput();
-// call once per frame to prepare input for processing
-//void NDS_beginProcessingInput();
-// call once per frame to copy the processed input to the final input
-//void NDS_endProcessingInput();
-
-// this is in case something needs reentrancy while processing input
-//void NDS_suspendProcessingInput(bool suspend);
-
-
-
-//int NDS_LoadROM(const char *filename, const char* logicalFilename=0);
void NDS_FreeROM();
void NDS_Reset();
-//int NDS_ImportSave(const char *filename);
-//bool NDS_ExportSave(const char *filename);
-
-//void nds_savestate(EMUFILE* os);
-bool nds_loadstate(EMUFILE* is, int size);
-
-//int NDS_WriteBMP(const char *filename);
void NDS_Sleep();
-//void NDS_ToggleCardEject();
-
-//void NDS_SkipNextFrame();
-//#define NDS_SkipFrame(s) if(s) NDS_SkipNext2DFrame();
-//void NDS_OmitFrameSkip(int force=0);
-
-//void NDS_debug_break();
-//void NDS_debug_continue();
-//void NDS_debug_step();
void execHardware_doAllDma(EDMAMode modeNum);
-template<bool FORCE> void NDS_exec(int32_t nb = 560190<<1);
-
-//extern int lagframecounter;
-
-/*static INLINE void NDS_swapScreen()
-{
- uint16_t tmp = MainScreen.offset;
- MainScreen.offset = SubScreen.offset;
- SubScreen.offset = tmp;
-}*/
-
-//int NDS_WriteBMP_32bppBuffer(int width, int height, const void* buf, const char *filename);
-
-extern struct TCommonSettings {
- TCommonSettings()
- : //GFX3D_HighResolutionInterpolateColor(true)
- //, GFX3D_EdgeMark(true)
- //, GFX3D_Fog(true)
- //, GFX3D_Texture(true)
- //, GFX3D_Zelda_Shadow_Depth_Hack(0)
- /*,*/ UseExtBIOS(false)
- , SWIFromBIOS(false)
- , PatchSWI3(false)
- , UseExtFirmware(false)
- , BootFromFirmware(false)
- , ConsoleType(NDS_CONSOLE_TYPE_FAT)
- //, DebugConsole(false)
- //, EnsataEmulation(false)
- //, cheatsDisable(false)
- //, num_cores(1)
- , rigorous_timing(false)
- , advanced_timing(true)
- //, micMode(InternalNoise)
- , spuInterpolationMode(SPUInterpolation_Linear)
- , manualBackupType(0)
- , spu_captureMuted(false)
- , spu_advanced(false)
- {
- strcpy(ARM9BIOS, "biosnds9.bin");
- strcpy(ARM7BIOS, "biosnds7.bin");
- strcpy(Firmware, "firmware.bin");
- NDS_FillDefaultFirmwareConfigData(&InternalFirmConf);
-
- /* WIFI mode: adhoc = 0, infrastructure = 1 */
- //wifi.mode = 1;
- //wifi.infraBridgeAdapter = 0;
-
- for(int i=0;i<16;i++)
- spu_muteChannels[i] = false;
-
- /*for(int g=0;g<2;g++)
- for(int x=0;x<5;x++)
- dispLayers[g][x]=true;*/
+template<bool FORCE> void NDS_exec(int32_t nb = 560190 << 1);
+
+extern struct TCommonSettings
+{
+ TCommonSettings() : UseExtBIOS(false), SWIFromBIOS(false), PatchSWI3(false), UseExtFirmware(false), BootFromFirmware(false), ConsoleType(NDS_CONSOLE_TYPE_FAT), rigorous_timing(false), advanced_timing(true),
+ spuInterpolationMode(SPUInterpolation_Linear), manualBackupType(0), spu_captureMuted(false), spu_advanced(false)
+ {
+ strcpy(this->ARM9BIOS, "biosnds9.bin");
+ strcpy(this->ARM7BIOS, "biosnds7.bin");
+ strcpy(this->Firmware, "firmware.bin");
+ NDS_FillDefaultFirmwareConfigData(&this->InternalFirmConf);
+
+ for (int i = 0; i < 16; ++i)
+ this->spu_muteChannels[i] = false;
+
+#ifdef HAVE_JIT
+ // zero 06-sep-2012 - shouldnt be defaulting this to true for now, since the jit is buggy.
+ // id rather have people discover a bonus speedhack than discover new bugs in a new version
+ this->use_jit = false;
+#else
+ this->use_jit = false;
+#endif
}
- //bool GFX3D_HighResolutionInterpolateColor;
- //bool GFX3D_EdgeMark;
- //bool GFX3D_Fog;
- //bool GFX3D_Texture;
- //int GFX3D_Zelda_Shadow_Depth_Hack;
bool UseExtBIOS;
char ARM9BIOS[256];
@@ -529,78 +314,23 @@
struct NDS_fw_config_data InternalFirmConf;
NDS_CONSOLE_TYPE ConsoleType;
- //bool DebugConsole;
- //bool EnsataEmulation;
-
- //bool cheatsDisable;
-
- //int num_cores;
- //bool single_core() { return num_cores==1; }
+
bool rigorous_timing;
- //bool dispLayers[2][5];
-
- /*FAST_ALIGN*/ bool advanced_timing;
-
- /*struct _Wifi {
- int mode;
- int infraBridgeAdapter;
- } wifi;*/
-
- /*enum MicMode
- {
- InternalNoise = 0,
- Sample = 1,
- Random = 2,
- Physical = 3
- } micMode;*/
-
+ bool advanced_timing;
+
+ bool use_jit;
+ uint32_t jit_max_block_size;
SPUInterpolationMode spuInterpolationMode;
- //this is a temporary hack until we straighten out the flushing logic and/or gxfifo
- //int gfx3d_flushMode;
-
- //this is the user's choice of manual backup type, for cases when the autodetection can't be trusted
+ // this is the user's choice of manual backup type, for cases when the autodetection can't be trusted
int manualBackupType;
bool spu_muteChannels[16];
bool spu_captureMuted;
bool spu_advanced;
-
- /*struct _ShowGpu {
- _ShowGpu() : main(true), sub(true) {}
- union {
- struct { bool main,sub; };
- bool screens[2];
- };
- } showGpu;*/
-
- /*struct _Hud {
- _Hud()
- : ShowInputDisplay(false)
- , ShowGraphicalInputDisplay(false)
- , FpsDisplay(false)
- , FrameCounterDisplay(false)
- , ShowLagFrameCounter(false)
- , ShowMicrophone(false)
- , ShowRTC(false)
- {}
- bool ShowInputDisplay, ShowGraphicalInputDisplay, FpsDisplay, FrameCounterDisplay, ShowLagFrameCounter, ShowMicrophone, ShowRTC;
- } hud;*/
-
} CommonSettings;
-
-//extern std::string InputDisplayString;
-//extern int LagFrameFlag;
-//extern int lastLag, TotalLagFrames;
-
-//void MovieSRAM();
-
-//void ClearAutoHold();
-
-//bool ValidateSlot2Access(uint32_t procnum, uint32_t demandSRAMSpeed, uint32_t demand1stROMSpeed, uint32_t demand2ndROMSpeed, int clockbits);
-
#endif
--- a/src/in_2sf/desmume/PACKED.h
+++ b/src/in_2sf/desmume/PACKED.h
@@ -4,10 +4,10 @@
#endif
#ifndef __PACKED
- #ifdef __GNUC__
- #define __PACKED __attribute__((__packed__))
- #else
- #define __PACKED
- #endif
+# ifdef __GNUC__
+# define __PACKED __attribute__((__packed__))
+# else
+# define __PACKED
+# endif
#endif
--- a/src/in_2sf/desmume/SPU.cpp
+++ b/src/in_2sf/desmume/SPU.cpp
@@ -26,10 +26,8 @@
#include <cstdlib>
#include <cstring>
#ifndef M_PI
-#define M_PI 3.14159265358979323846
+static const double M_PI = 3.14159265358979323846;
#endif
-
-//#include "debug.h"
#include "MMU.h"
#include "SPU.h"
#include "mem.h"
@@ -38,28 +36,27 @@
#include "NDSSystem.h"
#include "matrix.h"
-#include "metaspu/metaspu.h"
+static inline int16_t read16(uint32_t addr) { return static_cast<int16_t>(_MMU_read16<ARMCPU_ARM7,MMU_AT_DEBUG>(addr)); }
+static inline uint8_t read08(uint32_t addr) { return _MMU_read08<ARMCPU_ARM7,MMU_AT_DEBUG>(addr); }
+static inline int8_t read_s8(uint32_t addr) { return static_cast<int8_t>(_MMU_read08<ARMCPU_ARM7,MMU_AT_DEBUG>(addr)); }
static const int K_ADPCM_LOOPING_RECOVERY_INDEX = 99999;
static const int COSINE_INTERPOLATION_RESOLUTION = 8192;
-//static ISynchronizingAudioBuffer* synchronizer = metaspu_construct(ESynchMethod_Z);
-static ISynchronizingAudioBuffer* synchronizer = metaspu_construct(ESynchMethod_N);
-
-SPU_struct *SPU_core = 0;
-SPU_struct *SPU_user = 0;
+static auto synchronizer = std::unique_ptr<ISynchronizingAudioBuffer>(metaspu_construct(ESynchMethod_N));
+
+std::unique_ptr<SPU_struct> SPU_core, SPU_user;
int SPU_currentCoreNum = SNDCORE_DUMMY;
static int volume = 100;
-static int buffersize = 0;
+static size_t buffersize = 0;
static ESynchMode synchmode = ESynchMode_DualSynchAsynch;
static ESynchMethod synchmethod = ESynchMethod_N;
-static int SNDCoreId=-1;
-static SoundInterface_struct *SNDCore=NULL;
+static int SNDCoreId = -1;
+static SoundInterface_struct *SNDCore = nullptr;
extern SoundInterface_struct *SNDCoreList[];
-//const int shift = (FORMAT == 0 ? 2 : 1);
static const int format_shift[] = { 2, 1, 3, 0 };
static const int8_t indextbl[8] =
@@ -102,26 +99,23 @@
static double samples = 0;
-template<typename T>
-static inline T MinMax(T val, T min, T max)
+template<typename T> static inline T MinMax(T val, T min, T max)
{
if (val < min)
return min;
else if (val > max)
return max;
-
- return val;
+ else
+ return val;
}
//--------------external spu interface---------------
int SPU_ChangeSoundCore(int coreid, int Buffersize)
{
- int i;
-
buffersize = Buffersize;
- delete SPU_user; SPU_user = NULL;
+ SPU_user.reset();
// Make sure the old core is freed
if (SNDCore)
@@ -134,45 +128,38 @@
SPU_currentCoreNum = coreid;
// Go through core list and find the id
- for (i = 0; SNDCoreList[i] != NULL; i++)
- {
+ for (int i = 0; SNDCoreList[i]; ++i)
if (SNDCoreList[i]->id == coreid)
{
// Set to current core
SNDCore = SNDCoreList[i];
break;
}
- }
SNDCoreId = coreid;
- //If the user picked the dummy core, disable the user spu
- if(SNDCore == &SNDDummy)
+ // If the user picked the dummy core, disable the user spu
+ if (SNDCore == &SNDDummy)
return 0;
- //If the core wasnt found in the list for some reason, disable the user spu
- if (SNDCore == NULL)
+ // If the core wasnt found in the list for some reason, disable the user spu
+ if (!SNDCore)
return -1;
// Since it failed, instead of it being fatal, disable the user spu
if (SNDCore->Init(buffersize * 2) == -1)
{
- SNDCore = 0;
+ SNDCore = nullptr;
return -1;
}
SNDCore->SetVolume(volume);
- SPU_SetSynchMode(synchmode,synchmethod);
+ SPU_SetSynchMode(synchmode, synchmethod);
return 0;
}
-/*SoundInterface_struct *SPU_SoundCore()
-{
- return SNDCore;
-}*/
-
void SPU_ReInit()
{
SPU_Init(SNDCoreId, buffersize);
@@ -180,49 +167,35 @@
int SPU_Init(int coreid, int Buffersize)
{
- int i, j;
-
// Build the cosine interpolation LUT
- for(i = 0; i < COSINE_INTERPOLATION_RESOLUTION; i++)
- cos_lut[i] = (1.0 - cos(((double)i/(double)COSINE_INTERPOLATION_RESOLUTION) * M_PI)) * 0.5;
-
- SPU_core = new SPU_struct((int)ceil(samples_per_hline));
+ int i;
+ for (i = 0; i < COSINE_INTERPOLATION_RESOLUTION; ++i)
+ cos_lut[i] = (1.0 - std::cos((static_cast<double>(i) / COSINE_INTERPOLATION_RESOLUTION) * M_PI)) * 0.5;
+
+ SPU_core.reset(new SPU_struct(static_cast<int>(std::ceil(samples_per_hline))));
SPU_Reset();
- //create adpcm decode accelerator lookups
- for(i = 0; i < 16; i++)
- {
- for(j = 0; j < 89; j++)
- {
- precalcdifftbl[j][i] = (((i & 0x7) * 2 + 1) * adpcmtbl[j] / 8);
- if(i & 0x8) precalcdifftbl[j][i] = -precalcdifftbl[j][i];
- }
- }
- for(i = 0; i < 8; i++)
- {
- for(j = 0; j < 89; j++)
- {
- precalcindextbl[j][i] = MinMax((j + indextbl[i]), 0, 88);
- }
- }
+ int j;
+ // create adpcm decode accelerator lookups
+ for (i = 0; i < 16; ++i)
+ for (j = 0; j < 89; ++j)
+ {
+ precalcdifftbl[j][i] = ((i & 0x7) * 2 + 1) * adpcmtbl[j] / 8;
+ if (i & 0x8)
+ precalcdifftbl[j][i] = -precalcdifftbl[j][i];
+ }
+ for (i = 0; i < 8; ++i)
+ for (j = 0; j < 89; ++j)
+ precalcindextbl[j][i] = MinMax(j + indextbl[i], 0, 88);
return SPU_ChangeSoundCore(coreid, Buffersize);
}
-/*void SPU_Pause(int pause)
-{
- if (SNDCore == NULL) return;
-
- if(pause)
- SNDCore->MuteAudio();
- else
- SNDCore->UnMuteAudio();
-}*/
-
void SPU_CloneUser()
{
- if(SPU_user) {
- memcpy(SPU_user->channels,SPU_core->channels,sizeof(SPU_core->channels));
+ if (SPU_user)
+ {
+ memcpy(SPU_user->channels, SPU_core->channels, sizeof(SPU_core->channels));
SPU_user->regs = SPU_core->regs;
}
}
@@ -230,510 +203,538 @@
void SPU_SetSynchMode(ESynchMode mode, ESynchMethod method)
{
synchmode = mode;
- if(synchmethod != method)
+ if (synchmethod != method)
{
synchmethod = method;
- delete synchronizer;
- //grr does this need to be locked? spu might need a lock method
- // or maybe not, maybe the platform-specific code that calls this function can deal with it.
- synchronizer = metaspu_construct(synchmethod);
- }
-
- delete SPU_user;
- SPU_user = NULL;
-
- if(synchmode == ESynchMode_DualSynchAsynch)
- {
- SPU_user = new SPU_struct(buffersize);
+ // grr does this need to be locked? spu might need a lock method
+ // or maybe not, maybe the platform-specific code that calls this function can deal with it.
+ synchronizer.reset(metaspu_construct(synchmethod));
+ }
+
+ SPU_user.reset();
+
+ if (synchmode == ESynchMode_DualSynchAsynch)
+ {
+ SPU_user.reset(new SPU_struct(buffersize));
SPU_CloneUser();
}
}
-/*void SPU_ClearOutputBuffer()
-{
- if(SNDCore && SNDCore->ClearBuffer)
- SNDCore->ClearBuffer();
-}*/
-
-/*void SPU_SetVolume(int vol)
-{
- volume = vol;
+void SPU_Reset()
+{
+ SPU_core->reset();
+
+ if (SPU_user)
+ {
+ if (SNDCore)
+ {
+ SNDCore->DeInit();
+ SNDCore->Init(SPU_user->bufsize * 2);
+ SNDCore->SetVolume(volume);
+ }
+ SPU_user->reset();
+ }
+
+ // zero - 09-apr-2010: this concerns me, regarding savestate synch.
+ // After 0.9.6, lets experiment with removing it and just properly zapping the spu instead
+ // Reset Registers
+ for (int i = 0x400; i < 0x51D; ++i)
+ T1WriteByte(MMU.ARM7_REG, i, 0);
+
+ samples = 0;
+}
+
+//------------------------------------------
+
+void SPU_struct::reset()
+{
+ memset(&this->sndbuf[0], 0, bufsize * 2 * 4);
+ memset(&this->outbuf[0], 0, bufsize * 2 * 2);
+
+ memset(this->channels, 0, sizeof(channel_struct) * 16);
+
+ reconstruct(&this->regs);
+
+ for (int i = 0; i < 16; ++i)
+ this->channels[i].num = i;
+}
+
+SPU_struct::SPU_struct(int Buffersize) : bufpos(0), buflength(0), sndbuf(new int32_t[Buffersize * 2]), outbuf(new int16_t[Buffersize * 2]), bufsize(Buffersize)
+{
+ this->reset();
+}
+
+void SPU_DeInit()
+{
if (SNDCore)
- SNDCore->SetVolume(vol);
-}*/
-
-
-void SPU_Reset()
-{
- int i;
-
- SPU_core->reset();
-
- if(SPU_user) {
- if(SNDCore)
- {
- SNDCore->DeInit();
- SNDCore->Init(SPU_user->bufsize*2);
- SNDCore->SetVolume(volume);
- }
- SPU_user->reset();
- }
-
- //zero - 09-apr-2010: this concerns me, regarding savestate synch.
- //After 0.9.6, lets experiment with removing it and just properly zapping the spu instead
- // Reset Registers
- for (i = 0x400; i < 0x51D; i++)
- T1WriteByte(MMU.ARM7_REG, i, 0);
-
- samples = 0;
-}
-
-//------------------------------------------
-
-void SPU_struct::reset()
-{
- memset(sndbuf,0,bufsize*2*4);
- memset(outbuf,0,bufsize*2*2);
-
- memset((void *)channels, 0, sizeof(channel_struct) * 16);
-
- reconstruct(®s);
-
- for(int i = 0; i < 16; i++)
- {
- channels[i].num = i;
- }
-}
-
-SPU_struct::SPU_struct(int Buffersize)
- : bufpos(0)
- , buflength(0)
- , sndbuf(0)
- , outbuf(0)
- , bufsize(Buffersize)
-{
- sndbuf = new int32_t[Buffersize*2];
- outbuf = new int16_t[Buffersize*2];
- reset();
-}
-
-SPU_struct::~SPU_struct()
-{
- if(sndbuf) delete[] sndbuf;
- if(outbuf) delete[] outbuf;
-}
-
-void SPU_DeInit()
-{
- if(SNDCore)
SNDCore->DeInit();
- SNDCore = 0;
-
- delete SPU_core; SPU_core=0;
- delete SPU_user; SPU_user=0;
+ SNDCore = nullptr;
+
+ SPU_core.reset();
+ SPU_user.reset();
}
//////////////////////////////////////////////////////////////////////////////
void SPU_struct::ShutUp()
{
- for(int i=0;i<16;i++)
- channels[i].status = CHANSTAT_STOPPED;
+ for (int i = 0; i < 16; ++i)
+ this->channels[i].status = CHANSTAT_STOPPED;
}
static inline void adjust_channel_timer(channel_struct *chan)
{
- chan->sampinc = (((double)ARM7_CLOCK) / (DESMUME_SAMPLE_RATE * 2)) / (double)(0x10000 - chan->timer);
+ chan->sampinc = (ARM7_CLOCK / (DESMUME_SAMPLE_RATE * 2)) / (0x10000 - chan->timer);
}
void SPU_struct::KeyProbe(int chan_num)
{
- channel_struct &thischan = channels[chan_num];
- if(thischan.status == CHANSTAT_STOPPED)
- {
- if(thischan.keyon && regs.masteren)
- KeyOn(chan_num);
- }
- else if(thischan.status == CHANSTAT_PLAY)
- {
- if(!thischan.keyon || !regs.masteren)
- KeyOff(chan_num);
+ channel_struct &thischan = this->channels[chan_num];
+ if (thischan.status == CHANSTAT_STOPPED)
+ {
+ if (thischan.keyon && this->regs.masteren)
+ this->KeyOn(chan_num);
+ }
+ else if (thischan.status == CHANSTAT_PLAY)
+ {
+ if (!thischan.keyon || !this->regs.masteren)
+ this->KeyOff(chan_num);
}
}
void SPU_struct::KeyOff(int channel)
{
//printf("keyoff%d\n",channel);
- channel_struct &thischan = channels[channel];
+ channel_struct &thischan = this->channels[channel];
thischan.status = CHANSTAT_STOPPED;
}
void SPU_struct::KeyOn(int channel)
{
- channel_struct &thischan = channels[channel];
+ channel_struct &thischan = this->channels[channel];
thischan.status = CHANSTAT_PLAY;
thischan.totlength = thischan.length + thischan.loopstart;
adjust_channel_timer(&thischan);
//printf("keyon %d totlength:%d\n",channel,thischan.totlength);
-
//LOG("Channel %d key on: vol = %d, datashift = %d, hold = %d, pan = %d, waveduty = %d, repeat = %d, format = %d, source address = %07X,"
// "timer = %04X, loop start = %04X, length = %06X, MMU.ARM7_REG[0x501] = %02X\n", channel, chan->vol, chan->datashift, chan->hold,
// chan->pan, chan->waveduty, chan->repeat, chan->format, chan->addr, chan->timer, chan->loopstart, chan->length, T1ReadByte(MMU.ARM7_REG, 0x501));
- switch(thischan.format)
- {
- case 0: // 8-bit
- thischan.buf8 = (int8_t*)&MMU.MMU_MEM[1][(thischan.addr>>20)&0xFF][(thischan.addr & MMU.MMU_MASK[1][(thischan.addr >> 20) & 0xFF])];
- // thischan.loopstart = thischan.loopstart << 2;
- // thischan.length = (thischan.length << 2) + thischan.loopstart;
- thischan.sampcnt = -3;
- break;
- case 1: // 16-bit
- thischan.buf16 = (int16_t *)&MMU.MMU_MEM[1][(thischan.addr>>20)&0xFF][(thischan.addr & MMU.MMU_MASK[1][(thischan.addr >> 20) & 0xFF])];
- // thischan.loopstart = thischan.loopstart << 1;
- // thischan.length = (thischan.length << 1) + thischan.loopstart;
- thischan.sampcnt = -3;
- break;
- case 2: // ADPCM
- {
- thischan.buf8 = (int8_t*)&MMU.MMU_MEM[1][(thischan.addr>>20)&0xFF][(thischan.addr & MMU.MMU_MASK[1][(thischan.addr >> 20) & 0xFF])];
- thischan.pcm16b = (int16_t)((thischan.buf8[1] << 8) | thischan.buf8[0]);
+ switch (thischan.format)
+ {
+ case 0: // 8-bit
+ //hischan.loopstart = thischan.loopstart << 2;
+ //hischan.length = (thischan.length << 2) + thischan.loopstart;
+ thischan.sampcnt = -3;
+ break;
+ case 1: // 16-bit
+ //thischan.loopstart = thischan.loopstart << 1;
+ //thischan.length = (thischan.length << 1) + thischan.loopstart;
+ thischan.sampcnt = -3;
+ break;
+ case 2: // ADPCM
+ thischan.pcm16b = read16(thischan.addr);
thischan.pcm16b_last = thischan.pcm16b;
- thischan.index = thischan.buf8[2] & 0x7F;
+ thischan.index = read08(thischan.addr + 2) & 0x7F;
thischan.lastsampcnt = 7;
thischan.sampcnt = -3;
thischan.loop_index = K_ADPCM_LOOPING_RECOVERY_INDEX;
- // thischan.loopstart = thischan.loopstart << 3;
- // thischan.length = (thischan.length << 3) + thischan.loopstart;
- break;
- }
- case 3: // PSG
- {
+ //thischan.loopstart = thischan.loopstart << 3;
+ //hischan.length = (thischan.length << 3) + thischan.loopstart;
+ break;
+ case 3: // PSG
thischan.sampcnt = -1;
thischan.x = 0x7FFF;
- break;
- }
- default: break;
- }
-
- thischan.double_totlength_shifted = (double)(thischan.totlength << format_shift[thischan.format]);
-
- if(thischan.format != 3)
- {
- if(fEqual(thischan.double_totlength_shifted, 0.0))
- {
- printf("INFO: Stopping channel %d due to zero length\n",channel);
- thischan.status = CHANSTAT_STOPPED;
- }
+ }
+
+ thischan.double_totlength_shifted = static_cast<double>(thischan.totlength << format_shift[thischan.format]);
+
+ if (thischan.format != 3 && fEqual(thischan.double_totlength_shifted, 0.0))
+ {
+ printf("INFO: Stopping channel %d due to zero length\n", channel);
+ thischan.status = CHANSTAT_STOPPED;
}
}
//////////////////////////////////////////////////////////////////////////////
-//#define SETBYTE(which,oldval,newval) oldval = (oldval & (~(0xFF<<(which*8)))) | ((newval)<<(which*8))
-template<typename T> static inline void SETBYTE(uint32_t which, T &oldval, uint8_t newval) { oldval = (oldval & (~(0xFF << (which*8)))) | (newval << (which*8)); }
-//#define GETBYTE(which,val) ((val>>(which*8))&0xFF)
+template<typename T> static inline void SETBYTE(uint32_t which, T &oldval, uint8_t newval) { oldval = (oldval & (~(0xFF << (which * 8)))) | (newval << (which * 8)); }
static inline uint8_t GETBYTE(uint32_t which, uint32_t val) { return (val >> (which * 8)) & 0xFF; }
-uint8_t SPU_ReadByte(uint32_t addr) {
+uint8_t SPU_ReadByte(uint32_t addr)
+{
addr &= 0xFFF;
return SPU_core->ReadByte(addr);
}
-uint16_t SPU_ReadWord(uint32_t addr) {
+uint16_t SPU_ReadWord(uint32_t addr)
+{
addr &= 0xFFF;
return SPU_core->ReadWord(addr);
}
-uint32_t SPU_ReadLong(uint32_t addr) {
+uint32_t SPU_ReadLong(uint32_t addr)
+{
addr &= 0xFFF;
return SPU_core->ReadLong(addr);
}
uint16_t SPU_struct::ReadWord(uint32_t addr)
{
- return ReadByte(addr)|(ReadByte(addr+1)<<8);
+ return this->ReadByte(addr) | (this->ReadByte(addr + 1) << 8);
}
uint32_t SPU_struct::ReadLong(uint32_t addr)
{
- return ReadByte(addr)|(ReadByte(addr+1)<<8)|(ReadByte(addr+2)<<16)|(ReadByte(addr+3)<<24);
+ return this->ReadByte(addr) | (this->ReadByte(addr + 1) << 8) | (this->ReadByte(addr + 2) << 16) | (ReadByte(addr + 3) << 24);
}
uint8_t SPU_struct::ReadByte(uint32_t addr)
{
- switch(addr)
- {
- //SOUNDCNT
- case 0x500: return regs.mastervol;
- case 0x501:
- return (regs.ctl_left)|(regs.ctl_right<<2)|(regs.ctl_ch1bypass<<4)|(regs.ctl_ch3bypass<<5)|(regs.masteren<<7);
- case 0x502: return 0;
- case 0x503: return 0;
-
- //SOUNDBIAS
- case 0x504: return regs.soundbias&0xFF;
- case 0x505: return (regs.soundbias>>8)&0xFF;
- case 0x506: return 0;
- case 0x507: return 0;
-
- //SNDCAP0CNT/SNDCAP1CNT
- case 0x508:
- case 0x509: {
- uint32_t which = addr-0x508;
- return regs.cap[which].add
- | (regs.cap[which].source<<1)
- | (regs.cap[which].oneshot<<2)
- | (regs.cap[which].bits8<<3)
- //| (regs.cap[which].active<<7); //? which is right? need test
- | (regs.cap[which].runtime.running<<7);
- }
-
- //SNDCAP0DAD
- case 0x510: return GETBYTE(0,regs.cap[0].dad);
- case 0x511: return GETBYTE(1,regs.cap[0].dad);
- case 0x512: return GETBYTE(2,regs.cap[0].dad);
- case 0x513: return GETBYTE(3,regs.cap[0].dad);
-
- //SNDCAP0LEN
- case 0x514: return GETBYTE(0,regs.cap[0].len);
- case 0x515: return GETBYTE(1,regs.cap[0].len);
- case 0x516: return 0; //not used
- case 0x517: return 0; //not used
-
- //SNDCAP1DAD
- case 0x518: return GETBYTE(0,regs.cap[1].dad);
- case 0x519: return GETBYTE(1,regs.cap[1].dad);
- case 0x51A: return GETBYTE(2,regs.cap[1].dad);
- case 0x51B: return GETBYTE(3,regs.cap[1].dad);
-
- //SNDCAP1LEN
- case 0x51C: return GETBYTE(0,regs.cap[1].len);
- case 0x51D: return GETBYTE(1,regs.cap[1].len);
- case 0x51E: return 0; //not used
- case 0x51F: return 0; //not used
-
- default: {
- //individual channel regs
-
- uint32_t chan_num = (addr >> 4) & 0xF;
- if(chan_num>0xF) return 0;
- channel_struct &thischan=channels[chan_num];
-
- switch(addr & 0xF) {
- case 0x0: return thischan.vol;
- case 0x1: {
- uint8_t ret = thischan.datashift;
- if(ret==4) ret=3;
- ret |= thischan.hold<<7;
- return ret;
- }
- case 0x2: return thischan.pan;
- case 0x3: return thischan.waveduty|(thischan.repeat<<3)|(thischan.format<<5)|((thischan.status == CHANSTAT_PLAY)?0x80:0);
- case 0x4: return 0; //return GETBYTE(0,thischan.addr); //not readable
- case 0x5: return 0; //return GETBYTE(1,thischan.addr); //not readable
- case 0x6: return 0; //return GETBYTE(2,thischan.addr); //not readable
- case 0x7: return 0; //return GETBYTE(3,thischan.addr); //not readable
- case 0x8: return GETBYTE(0,thischan.timer);
- case 0x9: return GETBYTE(1,thischan.timer);
- case 0xA: return GETBYTE(0,thischan.loopstart);
- case 0xB: return GETBYTE(1,thischan.loopstart);
- case 0xC: return 0; //return GETBYTE(0,thischan.length); //not readable
- case 0xD: return 0; //return GETBYTE(1,thischan.length); //not readable
- case 0xE: return 0; //return GETBYTE(2,thischan.length); //not readable
- case 0xF: return 0; //return GETBYTE(3,thischan.length); //not readable
- default: return 0; //impossible
- } //switch on individual channel regs
- } //default case
- } //switch on address
+ switch (addr)
+ {
+ // SOUNDCNT
+ case 0x500:
+ return this->regs.mastervol;
+ case 0x501:
+ return this->regs.ctl_left | (this->regs.ctl_right << 2) | (this->regs.ctl_ch1bypass << 4) | (this->regs.ctl_ch3bypass << 5) | (this->regs.masteren << 7);
+ case 0x502:
+ case 0x503:
+ return 0;
+
+ // SOUNDBIAS
+ case 0x504:
+ return this->regs.soundbias & 0xFF;
+ case 0x505:
+ return (this->regs.soundbias >> 8) & 0xFF;
+ case 0x506:
+ case 0x507:
+ return 0;
+
+ // SNDCAP0CNT/SNDCAP1CNT
+ case 0x508:
+ case 0x509:
+ {
+ uint32_t which = addr - 0x508;
+ return this->regs.cap[which].add | (this->regs.cap[which].source << 1) | (this->regs.cap[which].oneshot << 2) | (this->regs.cap[which].bits8 << 3)
+ //| (regs.cap[which].active<<7); //? which is right? need test
+ | (this->regs.cap[which].runtime.running << 7);
+ }
+
+ // SNDCAP0DAD
+ case 0x510:
+ return GETBYTE(0, this->regs.cap[0].dad);
+ case 0x511:
+ return GETBYTE(1, this->regs.cap[0].dad);
+ case 0x512:
+ return GETBYTE(2, this->regs.cap[0].dad);
+ case 0x513:
+ return GETBYTE(3, this->regs.cap[0].dad);
+
+ // SNDCAP0LEN
+ case 0x514:
+ return GETBYTE(0, this->regs.cap[0].len);
+ case 0x515:
+ return GETBYTE(1, this->regs.cap[0].len);
+ case 0x516:
+ case 0x517:
+ return 0; //not used
+
+ // SNDCAP1DAD
+ case 0x518:
+ return GETBYTE(0, this->regs.cap[1].dad);
+ case 0x519:
+ return GETBYTE(1, this->regs.cap[1].dad);
+ case 0x51A:
+ return GETBYTE(2, this->regs.cap[1].dad);
+ case 0x51B:
+ return GETBYTE(3, this->regs.cap[1].dad);
+
+ // SNDCAP1LEN
+ case 0x51C:
+ return GETBYTE(0, this->regs.cap[1].len);
+ case 0x51D:
+ return GETBYTE(1, this->regs.cap[1].len);
+ case 0x51E:
+ case 0x51F:
+ return 0; //not used
+
+ default:
+ {
+ // individual channel regs
+
+ uint32_t chan_num = (addr >> 4) & 0xF;
+ if (chan_num > 0xF)
+ return 0;
+ channel_struct &thischan = this->channels[chan_num];
+
+ switch (addr & 0xF)
+ {
+ case 0x0:
+ return thischan.vol;
+ case 0x1:
+ {
+ uint8_t ret = thischan.datashift;
+ if (ret == 4)
+ ret = 3;
+ ret |= thischan.hold << 7;
+ return ret;
+ }
+ case 0x2:
+ return thischan.pan;
+ case 0x3:
+ return thischan.waveduty | (thischan.repeat << 3) | (thischan.format << 5) | (thischan.status == CHANSTAT_PLAY ? 0x80 : 0);
+ case 0x4:
+ return 0; //return GETBYTE(0, thischan.addr); //not readable
+ case 0x5:
+ return 0; //return GETBYTE(1, thischan.addr); //not readable
+ case 0x6:
+ return 0; //return GETBYTE(2, thischan.addr); //not readable
+ case 0x7:
+ return 0; //return GETBYTE(3, thischan.addr); //not readable
+ case 0x8:
+ return GETBYTE(0, thischan.timer);
+ case 0x9:
+ return GETBYTE(1, thischan.timer);
+ case 0xA:
+ return GETBYTE(0, thischan.loopstart);
+ case 0xB:
+ return GETBYTE(1, thischan.loopstart);
+ case 0xC:
+ return 0; //return GETBYTE(0, thischan.length); //not readable
+ case 0xD:
+ return 0; //return GETBYTE(1, thischan.length); //not readable
+ case 0xE:
+ return 0; //return GETBYTE(2, thischan.length); //not readable
+ case 0xF:
+ return 0; //return GETBYTE(3, thischan.length); //not readable
+ default:
+ return 0; //impossible
+ } // switch on individual channel regs
+ } // default case
+ } // switch on address
}
SPUFifo::SPUFifo()
{
- reset();
+ this->reset();
}
void SPUFifo::reset()
{
- head = tail = size = 0;
+ this->head = this->tail = this->size = 0;
}
void SPUFifo::enqueue(int16_t val)
{
- if(size==16) return;
- buffer[tail] = val;
- tail++;
- tail &= 15;
- size++;
+ if (this->size == 16)
+ return;
+ this->buffer[this->tail] = val;
+ ++this->tail;
+ this->tail &= 15;
+ ++this->size;
}
int16_t SPUFifo::dequeue()
{
- if(size==0) return 0;
- head++;
- head &= 15;
- int16_t ret = buffer[head];
- size--;
+ if (!this->size)
+ return 0;
+ ++this->head;
+ this->head &= 15;
+ int16_t ret = this->buffer[this->head];
+ --this->size;
return ret;
}
-/*void SPUFifo::save(EMUFILE* fp)
-{
- uint32_t version = 1;
- write32le(version,fp);
- write32le(head,fp);
- write32le(tail,fp);
- write32le(size,fp);
- for(int i=0;i<16;i++)
- write16le(buffer[i],fp);
-}*/
-
-bool SPUFifo::load(EMUFILE* fp)
-{
- uint32_t version;
- if(read32le(&version,fp) != 1) return false;
- read32le(&head,fp);
- read32le(&tail,fp);
- read32le(&size,fp);
- for(int i=0;i<16;i++)
- read16le(&buffer[i],fp);
- return true;
-}
-
void SPU_struct::ProbeCapture(int which)
{
- //VERY UNTESTED -- HOW MUCH OF THIS RESETS, AND WHEN?
-
- if(!regs.cap[which].active)
- {
- regs.cap[which].runtime.running = 0;
+ // VERY UNTESTED -- HOW MUCH OF THIS RESETS, AND WHEN?
+
+ if (!this->regs.cap[which].active)
+ {
+ this->regs.cap[which].runtime.running = 0;
return;
}
- REGS::CAP &cap = regs.cap[which];
+ REGS::CAP &cap = this->regs.cap[which];
cap.runtime.running = 1;
cap.runtime.curdad = cap.dad;
uint32_t len = cap.len;
- if(len==0) len=1;
- cap.runtime.maxdad = cap.dad + len*4;
+ if (!len)
+ len = 1;
+ cap.runtime.maxdad = cap.dad + len * 4;
cap.runtime.sampcnt = 0;
cap.runtime.fifo.reset();
}
void SPU_struct::WriteByte(uint32_t addr, uint8_t val)
{
- switch(addr)
- {
- //SOUNDCNT
- case 0x500:
- regs.mastervol = val&0x7F;
- break;
- case 0x501:
- regs.ctl_left = (val>>0)&3;
- regs.ctl_right = (val>>2)&3;
- regs.ctl_ch1bypass = (val>>4)&1;
- regs.ctl_ch3bypass = (val>>5)&1;
- regs.masteren = (val>>7)&1;
- for(int i=0;i<16;i++)
- KeyProbe(i);
- break;
- case 0x502: break; //not used
- case 0x503: break; //not used
-
- //SOUNDBIAS
- case 0x504: SETBYTE(0,regs.soundbias, val); break;
- case 0x505: SETBYTE(1,regs.soundbias, val&3); break;
- case 0x506: break; //these dont answer anyway
- case 0x507: break; //these dont answer anyway
-
- //SNDCAP0CNT/SNDCAP1CNT
- case 0x508:
- case 0x509: {
- uint32_t which = addr-0x508;
- regs.cap[which].add = static_cast<uint8_t>(BIT0(val));
- regs.cap[which].source = static_cast<uint8_t>(BIT1(val));
- regs.cap[which].oneshot = static_cast<uint8_t>(BIT2(val));
- regs.cap[which].bits8 = static_cast<uint8_t>(BIT3(val));
- regs.cap[which].active = static_cast<uint8_t>(BIT7(val));
- ProbeCapture(which);
- break;
- }
-
- //SNDCAP0DAD
- case 0x510: SETBYTE(0,regs.cap[0].dad,val); break;
- case 0x511: SETBYTE(1,regs.cap[0].dad,val); break;
- case 0x512: SETBYTE(2,regs.cap[0].dad,val); break;
- case 0x513: SETBYTE(3,regs.cap[0].dad,val&7); break;
-
- //SNDCAP0LEN
- case 0x514: SETBYTE(0,regs.cap[0].len,val); break;
- case 0x515: SETBYTE(1,regs.cap[0].len,val); break;
- case 0x516: break; //not used
- case 0x517: break; //not used
-
- //SNDCAP1DAD
- case 0x518: SETBYTE(0,regs.cap[1].dad,val); break;
- case 0x519: SETBYTE(1,regs.cap[1].dad,val); break;
- case 0x51A: SETBYTE(2,regs.cap[1].dad,val); break;
- case 0x51B: SETBYTE(3,regs.cap[1].dad,val&7); break;
-
- //SNDCAP1LEN
- case 0x51C: SETBYTE(0,regs.cap[1].len,val); break;
- case 0x51D: SETBYTE(1,regs.cap[1].len,val); break;
- case 0x51E: break; //not used
- case 0x51F: break; //not used
-
-
-
- default: {
- //individual channel regs
-
- uint32_t chan_num = (addr >> 4) & 0xF;
- if(chan_num>0xF) break;
- channel_struct &thischan=channels[chan_num];
-
- switch(addr & 0xF) {
- case 0x0:
- thischan.vol = val & 0x7F;
+ switch (addr)
+ {
+ // SOUNDCNT
+ case 0x500:
+ this->regs.mastervol = val & 0x7F;
+ break;
+ case 0x501:
+ this->regs.ctl_left = val & 3;
+ this->regs.ctl_right = (val >> 2) & 3;
+ this->regs.ctl_ch1bypass = (val >> 4) & 1;
+ this->regs.ctl_ch3bypass = (val >> 5) & 1;
+ this->regs.masteren = (val >> 7) & 1;
+ for (int i = 0; i < 16; ++i)
+ this->KeyProbe(i);
+ break;
+ case 0x502:
+ case 0x503:
+ break; // not used
+
+ // SOUNDBIAS
+ case 0x504:
+ SETBYTE(0, this->regs.soundbias, val);
+ break;
+ case 0x505:
+ SETBYTE(1, this->regs.soundbias, val & 3);
+ break;
+ case 0x506:
+ case 0x507:
+ break; // these dont answer anyway
+
+ // SNDCAP0CNT/SNDCAP1CNT
+ case 0x508:
+ case 0x509:
+ {
+ uint32_t which = addr - 0x508;
+ this->regs.cap[which].add = static_cast<uint8_t>(BIT0(val));
+ this->regs.cap[which].source = static_cast<uint8_t>(BIT1(val));
+ this->regs.cap[which].oneshot = static_cast<uint8_t>(BIT2(val));
+ this->regs.cap[which].bits8 = static_cast<uint8_t>(BIT3(val));
+ this->regs.cap[which].active = static_cast<uint8_t>(BIT7(val));
+ this->ProbeCapture(which);
+ break;
+ }
+
+ // SNDCAP0DAD
+ case 0x510:
+ SETBYTE(0, this->regs.cap[0].dad, val);
+ break;
+ case 0x511:
+ SETBYTE(1, this->regs.cap[0].dad, val);
+ break;
+ case 0x512:
+ SETBYTE(2, this->regs.cap[0].dad, val);
+ break;
+ case 0x513:
+ SETBYTE(3, this->regs.cap[0].dad, val & 7);
+ break;
+
+ // SNDCAP0LEN
+ case 0x514:
+ SETBYTE(0, this->regs.cap[0].len, val);
+ break;
+ case 0x515:
+ SETBYTE(1, this->regs.cap[0].len, val);
+ break;
+ case 0x516:
+ case 0x517:
+ break; // not used
+
+ // SNDCAP1DAD
+ case 0x518:
+ SETBYTE(0, this->regs.cap[1].dad, val);
+ break;
+ case 0x519:
+ SETBYTE(1, this->regs.cap[1].dad, val);
+ break;
+ case 0x51A:
+ SETBYTE(2, this->regs.cap[1].dad, val);
+ break;
+ case 0x51B:
+ SETBYTE(3, this->regs.cap[1].dad, val & 7);
+ break;
+
+ // SNDCAP1LEN
+ case 0x51C:
+ SETBYTE(0, this->regs.cap[1].len, val);
+ break;
+ case 0x51D:
+ SETBYTE(1, this->regs.cap[1].len, val);
+ break;
+ case 0x51E:
+ case 0x51F:
+ break; // not used
+
+ default:
+ {
+ // individual channel regs
+
+ uint32_t chan_num = (addr >> 4) & 0xF;
+ if (chan_num>0xF)
break;
- case 0x1:
- thischan.datashift = val & 0x3;
- if (thischan.datashift == 3)
- thischan.datashift = 4;
- thischan.hold = (val >> 7) & 0x1;
- break;
- case 0x2:
- thischan.pan = val & 0x7F;
- break;
- case 0x3:
- thischan.waveduty = val & 0x7;
- thischan.repeat = (val >> 3) & 0x3;
- thischan.format = (val >> 5) & 0x3;
- thischan.keyon = static_cast<uint8_t>(BIT7(val));
- KeyProbe(chan_num);
- break;
- case 0x4: SETBYTE(0,thischan.addr,val); break;
- case 0x5: SETBYTE(1,thischan.addr,val); break;
- case 0x6: SETBYTE(2,thischan.addr,val); break;
- case 0x7: SETBYTE(3,thischan.addr,val&0x7); break; //only 27 bits of this register are used
- case 0x8:
- SETBYTE(0,thischan.timer,val);
- adjust_channel_timer(&thischan);
- break;
- case 0x9:
- SETBYTE(1,thischan.timer,val);
- adjust_channel_timer(&thischan);
- break;
- case 0xA: SETBYTE(0,thischan.loopstart,val); break;
- case 0xB: SETBYTE(1,thischan.loopstart,val); break;
- case 0xC: SETBYTE(0,thischan.length,val); break;
- case 0xD: SETBYTE(1,thischan.length,val); break;
- case 0xE: SETBYTE(2,thischan.length,val & 0x3F); break; //only 22 bits of this register are used
- case 0xF: SETBYTE(3,thischan.length,0); break;
- } //switch on individual channel regs
- } //default case
- } //switch on address
+ channel_struct &thischan = this->channels[chan_num];
+
+ switch (addr & 0xF)
+ {
+ case 0x0:
+ thischan.vol = val & 0x7F;
+ break;
+ case 0x1:
+ thischan.datashift = val & 0x3;
+ if (thischan.datashift == 3)
+ thischan.datashift = 4;
+ thischan.hold = (val >> 7) & 0x1;
+ break;
+ case 0x2:
+ thischan.pan = val & 0x7F;
+ break;
+ case 0x3:
+ thischan.waveduty = val & 0x7;
+ thischan.repeat = (val >> 3) & 0x3;
+ thischan.format = (val >> 5) & 0x3;
+ thischan.keyon = static_cast<uint8_t>(BIT7(val));
+ this->KeyProbe(chan_num);
+ break;
+ case 0x4:
+ SETBYTE(0, thischan.addr, val);
+ break;
+ case 0x5:
+ SETBYTE(1, thischan.addr, val);
+ break;
+ case 0x6:
+ SETBYTE(2, thischan.addr, val);
+ break;
+ case 0x7:
+ SETBYTE(3, thischan.addr, val & 0x7);
+ break; // only 27 bits of this register are used
+ case 0x8:
+ SETBYTE(0, thischan.timer, val);
+ adjust_channel_timer(&thischan);
+ break;
+ case 0x9:
+ SETBYTE(1, thischan.timer, val);
+ adjust_channel_timer(&thischan);
+ break;
+ case 0xA:
+ SETBYTE(0, thischan.loopstart, val);
+ break;
+ case 0xB:
+ SETBYTE(1, thischan.loopstart, val);
+ break;
+ case 0xC:
+ SETBYTE(0, thischan.length, val);
+ break;
+ case 0xD:
+ SETBYTE(1, thischan.length, val);
+ break;
+ case 0xE:
+ SETBYTE(2, thischan.length, val & 0x3F);
+ break; // only 22 bits of this register are used
+ case 0xF:
+ SETBYTE(3, thischan.length, 0);
+ break;
+ } // switch on individual channel regs
+ } // default case
+ } // switch on address
}
void SPU_WriteByte(uint32_t addr, uint8_t val)
@@ -741,16 +742,17 @@
//printf("%08X: chan:%02X reg:%02X val:%02X\n",addr,(addr>>4)&0xF,addr&0xF,val);
addr &= 0xFFF;
- SPU_core->WriteByte(addr,val);
- if(SPU_user) SPU_user->WriteByte(addr,val);
+ SPU_core->WriteByte(addr, val);
+ if (SPU_user)
+ SPU_user->WriteByte(addr, val);
}
//////////////////////////////////////////////////////////////////////////////
void SPU_struct::WriteWord(uint32_t addr, uint16_t val)
{
- WriteByte(addr,val&0xFF);
- WriteByte(addr+1,(val>>8)&0xFF);
+ this->WriteByte(addr, val & 0xFF);
+ this->WriteByte(addr + 1, (val >> 8) & 0xFF);
}
void SPU_WriteWord(uint32_t addr, uint16_t val)
@@ -758,18 +760,19 @@
//printf("%08X: chan:%02X reg:%02X val:%04X\n",addr,(addr>>4)&0xF,addr&0xF,val);
addr &= 0xFFF;
- SPU_core->WriteWord(addr,val);
- if(SPU_user) SPU_user->WriteWord(addr,val);
+ SPU_core->WriteWord(addr, val);
+ if (SPU_user)
+ SPU_user->WriteWord(addr, val);
}
//////////////////////////////////////////////////////////////////////////////
void SPU_struct::WriteLong(uint32_t addr, uint32_t val)
{
- WriteByte(addr,val&0xFF);
- WriteByte(addr+1,(val>>8)&0xFF);
- WriteByte(addr+2,(val>>16)&0xFF);
- WriteByte(addr+3,(val>>24)&0xFF);
+ this->WriteByte(addr,val & 0xFF);
+ this->WriteByte(addr + 1,(val >> 8) & 0xFF);
+ this->WriteByte(addr + 2,(val >> 16) & 0xFF);
+ this->WriteByte(addr + 3,(val >> 24) & 0xFF);
}
void SPU_WriteLong(uint32_t addr, uint32_t val)
@@ -777,16 +780,17 @@
//printf("%08X: chan:%02X reg:%02X val:%08X\n",addr,(addr>>4)&0xF,addr&0xF,val);
addr &= 0xFFF;
- SPU_core->WriteLong(addr,val);
- if(SPU_user) SPU_user->WriteLong(addr,val);
+ SPU_core->WriteLong(addr, val);
+ if (SPU_user)
+ SPU_user->WriteLong(addr, val);
}
//////////////////////////////////////////////////////////////////////////////
template<SPUInterpolationMode INTERPOLATE_MODE> static inline int32_t Interpolate(int32_t a, int32_t b, double ratio)
{
- double sampleA = (double)a;
- double sampleB = (double)b;
+ double sampleA = static_cast<double>(a);
+ double sampleB = static_cast<double>(b);
ratio = ratio - u32floor(ratio);
switch (INTERPOLATE_MODE)
@@ -795,7 +799,7 @@
// Cosine Interpolation Formula:
// ratio2 = (1 - cos(ratio * M_PI)) / 2
// sampleI = sampleA * (1 - ratio2) + sampleB * ratio2
- return s32floor((cos_lut[(unsigned int)(ratio * (double)COSINE_INTERPOLATION_RESOLUTION)] * (sampleB - sampleA)) + sampleA);
+ return s32floor((cos_lut[static_cast<unsigned>(ratio * COSINE_INTERPOLATION_RESOLUTION)] * (sampleB - sampleA)) + sampleA);
break;
case SPUInterpolation_Linear:
@@ -822,17 +826,18 @@
}
uint32_t loc = u32floor(chan->sampcnt);
- if(INTERPOLATE_MODE != SPUInterpolation_None)
- {
- int32_t a = (int32_t)(chan->buf8[loc] << 8);
- if(loc < (chan->totlength << 2) - 1) {
- int32_t b = (int32_t)(chan->buf8[loc + 1] << 8);
+ if (INTERPOLATE_MODE != SPUInterpolation_None)
+ {
+ int32_t a = static_cast<int32_t>(read_s8(chan->addr + loc) << 8);
+ if (loc < (chan->totlength << 2) - 1)
+ {
+ int32_t b = static_cast<int32_t>(read_s8(chan->addr + loc + 1) << 8);
a = Interpolate<INTERPOLATE_MODE>(a, b, chan->sampcnt);
}
*data = a;
}
else
- *data = (int32_t)chan->buf8[loc] << 8;
+ *data = static_cast<int32_t>(read_s8(chan->addr + loc) << 8);
}
template<SPUInterpolationMode INTERPOLATE_MODE> static inline void Fetch16BitData(const channel_struct * const chan, int32_t *data)
@@ -846,16 +851,17 @@
if(INTERPOLATE_MODE != SPUInterpolation_None)
{
uint32_t loc = u32floor(chan->sampcnt);
- int32_t a = (int32_t)chan->buf16[loc], b;
- if(loc < (chan->totlength << 1) - 1)
- {
- b = (int32_t)chan->buf16[loc + 1];
+
+ int32_t a = static_cast<int32_t>(read16(loc * 2 + chan->addr));
+ if (loc < (chan->totlength << 1) - 1)
+ {
+ int32_t b = static_cast<int32_t>(read16(loc * 2 + chan->addr + 2));
a = Interpolate<INTERPOLATE_MODE>(a, b, chan->sampcnt);
}
*data = a;
}
else
- *data = (int32_t)chan->buf16[u32floor(chan->sampcnt)];
+ *data = read16(chan->addr + u32floor(chan->sampcnt) * 2);
}
template<SPUInterpolationMode INTERPOLATE_MODE> static inline void FetchADPCMData(channel_struct * const chan, int32_t * const data)
@@ -867,34 +873,36 @@
}
// No sense decoding, just return the last sample
- if (chan->lastsampcnt != u32floor(chan->sampcnt)){
-
- const uint32_t endExclusive = u32floor(chan->sampcnt+1);
- for (uint32_t i = chan->lastsampcnt+1; i < endExclusive; i++)
- {
- const uint32_t shift = (i&1)<<2;
- const uint32_t data4bit = (((uint32_t)chan->buf8[i >> 1]) >> shift);
-
- const int32_t diff = precalcdifftbl[chan->index][data4bit & 0xF];
- chan->index = precalcindextbl[chan->index][data4bit & 0x7];
-
- chan->pcm16b_last = chan->pcm16b;
- chan->pcm16b = static_cast<int16_t>(MinMax<int32_t>(chan->pcm16b+diff, -0x8000, 0x7FFF));
-
- if(i == static_cast<uint32_t>(chan->loopstart<<3)) {
- if(chan->loop_index != K_ADPCM_LOOPING_RECOVERY_INDEX) printf("over-snagging\n");
+ if (chan->lastsampcnt != u32floor(chan->sampcnt))
+ {
+ uint32_t endExclusive = u32floor(chan->sampcnt + 1);
+ for (uint32_t i = chan->lastsampcnt + 1; i < endExclusive; ++i)
+ {
+ uint32_t shift = (i & 1) << 2;
+ uint32_t data4bit = static_cast<uint32_t>(read08(chan->addr + (i >> 1))) >> shift;
+
+ int32_t diff = precalcdifftbl[chan->index][data4bit & 0xF];
+ chan->index = precalcindextbl[chan->index][data4bit & 0x7];
+
+ chan->pcm16b_last = chan->pcm16b;
+ chan->pcm16b = MinMax(chan->pcm16b+diff, -0x8000, 0x7FFF);
+
+ if (i == static_cast<uint32_t>(chan->loopstart << 3))
+ {
+ if (chan->loop_index != K_ADPCM_LOOPING_RECOVERY_INDEX)
+ printf("over-snagging\n");
chan->loop_pcm16b = chan->pcm16b;
chan->loop_index = chan->index;
}
- }
-
- chan->lastsampcnt = u32floor(chan->sampcnt);
- }
-
- if(INTERPOLATE_MODE != SPUInterpolation_None)
- *data = Interpolate<INTERPOLATE_MODE>((int32_t)chan->pcm16b_last,(int32_t)chan->pcm16b,chan->sampcnt);
+ }
+
+ chan->lastsampcnt = u32floor(chan->sampcnt);
+ }
+
+ if (INTERPOLATE_MODE != SPUInterpolation_None)
+ *data = Interpolate<INTERPOLATE_MODE>(static_cast<int32_t>(chan->pcm16b_last), static_cast<int32_t>(chan->pcm16b), chan->sampcnt);
else
- *data = (int32_t)chan->pcm16b;
+ *data = static_cast<int32_t>(chan->pcm16b);
}
static inline void FetchPSGData(channel_struct *chan, int32_t *data)
@@ -905,26 +913,22 @@
return;
}
- if(chan->num < 8)
- {
+ if (chan->num < 8)
*data = 0;
- }
- else if(chan->num < 14)
- {
- *data = (int32_t)wavedutytbl[chan->waveduty][(u32floor(chan->sampcnt)) & 0x7];
- }
+ else if (chan->num < 14)
+ *data = static_cast<int32_t>(wavedutytbl[chan->waveduty][u32floor(chan->sampcnt) & 0x7]);
else
{
- if(chan->lastsampcnt == u32floor(chan->sampcnt))
- {
- *data = (int32_t)chan->psgnoise_last;
+ if (chan->lastsampcnt == u32floor(chan->sampcnt))
+ {
+ *data = static_cast<int32_t>(chan->psgnoise_last);
return;
}
uint32_t max = u32floor(chan->sampcnt);
- for(uint32_t i = chan->lastsampcnt; i < max; i++)
- {
- if(chan->x & 0x1)
+ for (uint32_t i = chan->lastsampcnt; i < max; ++i)
+ {
+ if (chan->x & 0x1)
{
chan->x = (chan->x >> 1) ^ 0x6000;
chan->psgnoise_last = -0x7FFF;
@@ -938,36 +942,36 @@
chan->lastsampcnt = u32floor(chan->sampcnt);
- *data = (int32_t)chan->psgnoise_last;
+ *data = static_cast<int32_t>(chan->psgnoise_last);
}
}
//////////////////////////////////////////////////////////////////////////////
-static inline void MixL(SPU_struct* SPU, channel_struct *chan, int32_t data)
+static inline void MixL(SPU_struct *SPU, channel_struct *chan, int32_t data)
{
data = spumuldiv7(data, chan->vol) >> chan->datashift;
- SPU->sndbuf[SPU->bufpos<<1] += data;
-}
-
-static inline void MixR(SPU_struct* SPU, channel_struct *chan, int32_t data)
+ SPU->sndbuf[SPU->bufpos << 1] += data;
+}
+
+static inline void MixR(SPU_struct *SPU, channel_struct *chan, int32_t data)
{
data = spumuldiv7(data, chan->vol) >> chan->datashift;
- SPU->sndbuf[(SPU->bufpos<<1)+1] += data;
-}
-
-static inline void MixLR(SPU_struct* SPU, channel_struct *chan, int32_t data)
+ SPU->sndbuf[(SPU->bufpos << 1) + 1] += data;
+}
+
+static inline void MixLR(SPU_struct *SPU, channel_struct *chan, int32_t data)
{
data = spumuldiv7(data, chan->vol) >> chan->datashift;
- SPU->sndbuf[SPU->bufpos<<1] += spumuldiv7(data, 127 - chan->pan);
- SPU->sndbuf[(SPU->bufpos<<1)+1] += spumuldiv7(data, chan->pan);
+ SPU->sndbuf[SPU->bufpos << 1] += spumuldiv7(data, 127 - chan->pan);
+ SPU->sndbuf[(SPU->bufpos << 1) + 1] += spumuldiv7(data, chan->pan);
}
//////////////////////////////////////////////////////////////////////////////
template<int FORMAT> static inline void TestForLoop(SPU_struct *SPU, channel_struct *chan)
{
- const int shift = (FORMAT == 0 ? 2 : 1);
+ int shift = !FORMAT ? 2 : 1;
chan->sampcnt += chan->sampinc;
@@ -977,7 +981,7 @@
if (chan->repeat == 1)
{
while (chan->sampcnt > chan->double_totlength_shifted)
- chan->sampcnt -= chan->double_totlength_shifted - (double)(chan->loopstart << shift);
+ chan->sampcnt -= chan->double_totlength_shifted - static_cast<double>(chan->loopstart << shift);
//chan->sampcnt = (double)(chan->loopstart << shift);
}
else
@@ -998,19 +1002,19 @@
if (chan->repeat == 1)
{
while (chan->sampcnt > chan->double_totlength_shifted)
- chan->sampcnt -= chan->double_totlength_shifted - (double)(chan->loopstart << 3);
-
- if(chan->loop_index == K_ADPCM_LOOPING_RECOVERY_INDEX)
+ chan->sampcnt -= chan->double_totlength_shifted - static_cast<double>(chan->loopstart << 3);
+
+ if (chan->loop_index == K_ADPCM_LOOPING_RECOVERY_INDEX)
{
- chan->pcm16b = (int16_t)((chan->buf8[1] << 8) | chan->buf8[0]);
- chan->index = chan->buf8[2] & 0x7F;
+ chan->pcm16b = read16(chan->addr);
+ chan->index = read08(chan->addr + 2) & 0x7F;
chan->lastsampcnt = 7;
}
else
{
chan->pcm16b = chan->loop_pcm16b;
chan->index = chan->loop_index;
- chan->lastsampcnt = (chan->loopstart << 3);
+ chan->lastsampcnt = chan->loopstart << 3;
}
}
else
@@ -1022,116 +1026,146 @@
}
}
-template<int CHANNELS> inline static void SPU_Mix(SPU_struct* SPU, channel_struct *chan, int32_t data)
-{
- switch(CHANNELS)
- {
- case 0: MixL(SPU, chan, data); break;
- case 1: MixLR(SPU, chan, data); break;
- case 2: MixR(SPU, chan, data); break;
+template<int CHANNELS> static inline void SPU_Mix(SPU_struct *SPU, channel_struct *chan, int32_t data)
+{
+ switch (CHANNELS)
+ {
+ case 0:
+ MixL(SPU, chan, data);
+ break;
+ case 1:
+ MixLR(SPU, chan, data);
+ break;
+ case 2:
+ MixR(SPU, chan, data);
}
SPU->lastdata = data;
}
-//WORK
-template<int FORMAT, SPUInterpolationMode INTERPOLATE_MODE, int CHANNELS>
- inline static void ____SPU_ChanUpdate(SPU_struct* const SPU, channel_struct* const chan)
-{
- for (; SPU->bufpos < SPU->buflength; SPU->bufpos++)
- {
- if(CHANNELS != -1)
+// WORK
+template<int FORMAT, SPUInterpolationMode INTERPOLATE_MODE, int CHANNELS> static inline void ____SPU_ChanUpdate(SPU_struct *const SPU, channel_struct *const chan)
+{
+ for (; SPU->bufpos < SPU->buflength; ++SPU->bufpos)
+ {
+ if (CHANNELS != -1)
{
int32_t data = 0;
- switch(FORMAT)
+ switch (FORMAT)
{
- case 0: Fetch8BitData<INTERPOLATE_MODE>(chan, &data); break;
- case 1: Fetch16BitData<INTERPOLATE_MODE>(chan, &data); break;
- case 2: FetchADPCMData<INTERPOLATE_MODE>(chan, &data); break;
- case 3: FetchPSGData(chan, &data); break;
+ case 0:
+ Fetch8BitData<INTERPOLATE_MODE>(chan, &data);
+ break;
+ case 1:
+ Fetch16BitData<INTERPOLATE_MODE>(chan, &data);
+ break;
+ case 2:
+ FetchADPCMData<INTERPOLATE_MODE>(chan, &data);
+ break;
+ case 3:
+ FetchPSGData(chan, &data);
}
SPU_Mix<CHANNELS>(SPU, chan, data);
}
- switch(FORMAT) {
- case 0: case 1: TestForLoop<FORMAT>(SPU, chan); break;
- case 2: TestForLoop2(SPU, chan); break;
- case 3: chan->sampcnt += chan->sampinc; break;
- }
- }
-}
-
-template<int FORMAT, SPUInterpolationMode INTERPOLATE_MODE>
- inline static void ___SPU_ChanUpdate(const bool actuallyMix, SPU_struct* const SPU, channel_struct* const chan)
-{
- if(!actuallyMix)
- ____SPU_ChanUpdate<FORMAT,INTERPOLATE_MODE,-1>(SPU,chan);
- else if (chan->pan == 0)
- ____SPU_ChanUpdate<FORMAT,INTERPOLATE_MODE,0>(SPU,chan);
+ switch (FORMAT)
+ {
+ case 0:
+ case 1:
+ TestForLoop<FORMAT>(SPU, chan);
+ break;
+ case 2:
+ TestForLoop2(SPU, chan);
+ break;
+ case 3:
+ chan->sampcnt += chan->sampinc;
+ }
+ }
+}
+
+template<int FORMAT, SPUInterpolationMode INTERPOLATE_MODE> static inline void ___SPU_ChanUpdate(bool actuallyMix, SPU_struct *const SPU, channel_struct *const chan)
+{
+ if (!actuallyMix)
+ ____SPU_ChanUpdate<FORMAT, INTERPOLATE_MODE, -1>(SPU, chan);
+ else if (!chan->pan)
+ ____SPU_ChanUpdate<FORMAT, INTERPOLATE_MODE, 0>(SPU, chan);
else if (chan->pan == 127)
- ____SPU_ChanUpdate<FORMAT,INTERPOLATE_MODE,2>(SPU,chan);
+ ____SPU_ChanUpdate<FORMAT, INTERPOLATE_MODE, 2>(SPU, chan);
else
- ____SPU_ChanUpdate<FORMAT,INTERPOLATE_MODE,1>(SPU,chan);
-}
-
-template<SPUInterpolationMode INTERPOLATE_MODE>
- inline static void __SPU_ChanUpdate(const bool actuallyMix, SPU_struct* const SPU, channel_struct* const chan)
-{
- switch(chan->format)
- {
- case 0: ___SPU_ChanUpdate<0,INTERPOLATE_MODE>(actuallyMix, SPU, chan); break;
- case 1: ___SPU_ChanUpdate<1,INTERPOLATE_MODE>(actuallyMix, SPU, chan); break;
- case 2: ___SPU_ChanUpdate<2,INTERPOLATE_MODE>(actuallyMix, SPU, chan); break;
- case 3: ___SPU_ChanUpdate<3,INTERPOLATE_MODE>(actuallyMix, SPU, chan); break;
- default: assert(false);
- }
-}
-
-inline static void _SPU_ChanUpdate(const bool actuallyMix, SPU_struct* const SPU, channel_struct* const chan)
-{
- switch(CommonSettings.spuInterpolationMode)
- {
- case SPUInterpolation_None: __SPU_ChanUpdate<SPUInterpolation_None>(actuallyMix, SPU, chan); break;
- case SPUInterpolation_Linear: __SPU_ChanUpdate<SPUInterpolation_Linear>(actuallyMix, SPU, chan); break;
- case SPUInterpolation_Cosine: __SPU_ChanUpdate<SPUInterpolation_Cosine>(actuallyMix, SPU, chan); break;
- default: assert(false);
- }
-}
-
-//ENTERNEW
+ ____SPU_ChanUpdate<FORMAT, INTERPOLATE_MODE, 1>(SPU, chan);
+}
+
+template<SPUInterpolationMode INTERPOLATE_MODE> static inline void __SPU_ChanUpdate(bool actuallyMix, SPU_struct *const SPU, channel_struct *const chan)
+{
+ switch (chan->format)
+ {
+ case 0:
+ ___SPU_ChanUpdate<0, INTERPOLATE_MODE>(actuallyMix, SPU, chan);
+ break;
+ case 1:
+ ___SPU_ChanUpdate<1, INTERPOLATE_MODE>(actuallyMix, SPU, chan);
+ break;
+ case 2:
+ ___SPU_ChanUpdate<2, INTERPOLATE_MODE>(actuallyMix, SPU, chan);
+ break;
+ case 3:
+ ___SPU_ChanUpdate<3, INTERPOLATE_MODE>(actuallyMix, SPU, chan);
+ break;
+ default:
+ assert(false);
+ }
+}
+
+static inline void _SPU_ChanUpdate(bool actuallyMix, SPU_struct *const SPU, channel_struct *const chan)
+{
+ switch (CommonSettings.spuInterpolationMode)
+ {
+ case SPUInterpolation_None:
+ __SPU_ChanUpdate<SPUInterpolation_None>(actuallyMix, SPU, chan);
+ break;
+ case SPUInterpolation_Linear:
+ __SPU_ChanUpdate<SPUInterpolation_Linear>(actuallyMix, SPU, chan);
+ break;
+ case SPUInterpolation_Cosine:
+ __SPU_ChanUpdate<SPUInterpolation_Cosine>(actuallyMix, SPU, chan);
+ break;
+ default:
+ assert(false);
+ }
+}
+
+// ENTERNEW
static void SPU_MixAudio_Advanced(bool, SPU_struct *SPU, int length)
{
- //the advanced spu function correctly handles all sound control mixing options, as well as capture
- //this code is not entirely optimal, as it relies on sort of manhandling the core mixing functions
- //in order to get the results it needs.
-
- //THIS IS MAX HACKS!!!!
- //AND NEEDS TO BE REWRITTEN ALONG WITH THE DEEPEST PARTS OF THE SPU
- //ONCE WE KNOW THAT IT WORKS
-
- //BIAS gets ignored since our spu is still not bit perfect,
- //and it doesnt matter for purposes of capture
-
- //-----------DEBUG CODE
+ // the advanced spu function correctly handles all sound control mixing options, as well as capture
+ // this code is not entirely optimal, as it relies on sort of manhandling the core mixing functions
+ // in order to get the results it needs.
+
+ // THIS IS MAX HACKS!!!!
+ // AND NEEDS TO BE REWRITTEN ALONG WITH THE DEEPEST PARTS OF THE SPU
+ // ONCE WE KNOW THAT IT WORKS
+
+ // BIAS gets ignored since our spu is still not bit perfect,
+ // and it doesnt matter for purposes of capture
+
+ // -----------DEBUG CODE
bool skipcap = false;
- //-----------------
-
- int32_t samp0[2] = {0,0};
-
- //believe it or not, we are going to do this one sample at a time.
- //like i said, it is slower.
- for(int samp=0;samp<length;samp++)
- {
- SPU->sndbuf[0] = 0;
- SPU->sndbuf[1] = 0;
+ // -----------------
+
+ int32_t samp0[] = { 0, 0 };
+
+ // believe it or not, we are going to do this one sample at a time.
+ // like i said, it is slower.
+ for (int samp = 0; samp < length; ++samp)
+ {
+ SPU->sndbuf[0] = SPU->sndbuf[1] = 0;
SPU->buflength = 1;
- int32_t capmix[2] = {0,0};
- int32_t mix[2] = {0,0};
+ int32_t capmix[] = { 0, 0 }, mix[] = { 0, 0 };
int32_t chanout[16];
int32_t submix[32];
- //generate each channel, and helpfully mix it at the same time
- for(int i=0;i<16;i++)
+ // generate each channel, and helpfully mix it at the same time
+ for (int i = 0; i < 16; ++i)
{
channel_struct *chan = &SPU->channels[i];
@@ -1140,201 +1174,216 @@
SPU->bufpos = 0;
bool bypass = false;
- if(i==1 && SPU->regs.ctl_ch1bypass) bypass=true;
- if(i==3 && SPU->regs.ctl_ch3bypass) bypass=true;
-
-
- //output to mixer unless we are bypassed.
- //dont output to mixer if the user muted us
+ if (i == 1 && SPU->regs.ctl_ch1bypass)
+ bypass = true;
+ if (i == 3 && SPU->regs.ctl_ch3bypass)
+ bypass = true;
+
+ // output to mixer unless we are bypassed.
+ // dont output to mixer if the user muted us
bool outputToMix = true;
- if(CommonSettings.spu_muteChannels[i]) outputToMix = false;
- if(bypass) outputToMix = false;
+ if (CommonSettings.spu_muteChannels[i])
+ outputToMix = false;
+ if (bypass)
+ outputToMix = false;
bool outputToCap = outputToMix;
- if(CommonSettings.spu_captureMuted && !bypass) outputToCap = true;
-
- //channels 1 and 3 should probably always generate their audio
- //internally at least, just in case they get used by the spu output
- bool domix = outputToCap || outputToMix || i==1 || i==3;
-
- //clear the output buffer since this is where _SPU_ChanUpdate wants to accumulate things
+ if (CommonSettings.spu_captureMuted && !bypass)
+ outputToCap = true;
+
+ // channels 1 and 3 should probably always generate their audio
+ // internally at least, just in case they get used by the spu output
+ bool domix = outputToCap || outputToMix || i == 1 || i == 3;
+
+ // clear the output buffer since this is where _SPU_ChanUpdate wants to accumulate things
SPU->sndbuf[0] = SPU->sndbuf[1] = 0;
- //get channel's next output sample.
+ // get channel's next output sample.
_SPU_ChanUpdate(domix, SPU, chan);
chanout[i] = SPU->lastdata >> chan->datashift;
- //save the panned results
- submix[i*2] = SPU->sndbuf[0];
- submix[i*2+1] = SPU->sndbuf[1];
-
- //send sample to our capture mix
- if(outputToCap)
+ // save the panned results
+ submix[i * 2] = SPU->sndbuf[0];
+ submix[i * 2 + 1] = SPU->sndbuf[1];
+
+ // send sample to our capture mix
+ if (outputToCap)
{
- capmix[0] += submix[i*2];
- capmix[1] += submix[i*2+1];
+ capmix[0] += submix[i * 2];
+ capmix[1] += submix[i * 2 + 1];
}
- //send sample to our main mixer
- if(outputToMix)
+ // send sample to our main mixer
+ if (outputToMix)
{
- mix[0] += submix[i*2];
- mix[1] += submix[i*2+1];
+ mix[0] += submix[i * 2];
+ mix[1] += submix[i * 2 + 1];
}
}
else
- {
- chanout[i] = 0;
- submix[i*2] = 0;
- submix[i*2+1] = 0;
- }
- } //foreach channel
-
- int32_t mixout[2] = {mix[0],mix[1]};
- int32_t capmixout[2] = {capmix[0],capmix[1]};
- int32_t sndout[2] = {0,0};
+ chanout[i] = submix[i * 2] = submix[i * 2 + 1] = 0;
+ } // foreach channel
+
+ int32_t mixout[] = { mix[0], mix[1] };
+ int32_t capmixout[] = { capmix[0], capmix[1] };
+ int32_t sndout[] = { 0, 0 };
int32_t capout[2];
- //create SPU output
- switch(SPU->regs.ctl_left)
- {
- case SPU_struct::REGS::LOM_LEFT_MIXER: sndout[0] = mixout[0]; break;
- case SPU_struct::REGS::LOM_CH1: sndout[0] = submix[1*2+0]; break;
- case SPU_struct::REGS::LOM_CH3: sndout[0] = submix[3*2+0]; break;
- case SPU_struct::REGS::LOM_CH1_PLUS_CH3: sndout[0] = submix[1*2+0] + submix[3*2+0]; break;
- }
- switch(SPU->regs.ctl_right)
- {
- case SPU_struct::REGS::ROM_RIGHT_MIXER: sndout[1] = mixout[1]; break;
- case SPU_struct::REGS::ROM_CH1: sndout[1] = submix[1*2+1]; break;
- case SPU_struct::REGS::ROM_CH3: sndout[1] = submix[3*2+1]; break;
- case SPU_struct::REGS::ROM_CH1_PLUS_CH3: sndout[1] = submix[1*2+1] + submix[3*2+1]; break;
- }
-
-
- //generate capture output ("capture bugs" from gbatek are not emulated)
- if(SPU->regs.cap[0].source==0)
- capout[0] = capmixout[0]; //cap0 = L-mix
- else if(SPU->regs.cap[0].add)
- capout[0] = chanout[0] + chanout[1]; //cap0 = ch0+ch1
- else capout[0] = chanout[0]; //cap0 = ch0
-
- if(SPU->regs.cap[1].source==0)
- capout[1] = capmixout[1]; //cap1 = R-mix
- else if(SPU->regs.cap[1].add)
- capout[1] = chanout[2] + chanout[3]; //cap1 = ch2+ch3
- else capout[1] = chanout[2]; //cap1 = ch2
-
- capout[0] = MinMax<int32_t>(capout[0],-0x8000,0x7FFF);
- capout[1] = MinMax<int32_t>(capout[1],-0x8000,0x7FFF);
-
- //write the output sample where it is supposed to go
- if(samp==0)
+ // create SPU output
+ switch (SPU->regs.ctl_left)
+ {
+ case SPU_struct::REGS::LOM_LEFT_MIXER:
+ sndout[0] = mixout[0];
+ break;
+ case SPU_struct::REGS::LOM_CH1:
+ sndout[0] = submix[2];
+ break;
+ case SPU_struct::REGS::LOM_CH3:
+ sndout[0] = submix[6];
+ break;
+ case SPU_struct::REGS::LOM_CH1_PLUS_CH3:
+ sndout[0] = submix[2] + submix[6];
+ }
+ switch (SPU->regs.ctl_right)
+ {
+ case SPU_struct::REGS::ROM_RIGHT_MIXER:
+ sndout[1] = mixout[1];
+ break;
+ case SPU_struct::REGS::ROM_CH1:
+ sndout[1] = submix[3];
+ break;
+ case SPU_struct::REGS::ROM_CH3:
+ sndout[1] = submix[7];
+ break;
+ case SPU_struct::REGS::ROM_CH1_PLUS_CH3:
+ sndout[1] = submix[3] + submix[7];
+ }
+
+ // generate capture output ("capture bugs" from gbatek are not emulated)
+ if (!SPU->regs.cap[0].source)
+ capout[0] = capmixout[0]; // cap0 = L-mix
+ else if (SPU->regs.cap[0].add)
+ capout[0] = chanout[0] + chanout[1]; // cap0 = ch0+ch1
+ else
+ capout[0] = chanout[0]; // cap0 = ch0
+
+ if (!SPU->regs.cap[1].source)
+ capout[1] = capmixout[1]; // cap1 = R-mix
+ else if (SPU->regs.cap[1].add)
+ capout[1] = chanout[2] + chanout[3]; // cap1 = ch2+ch3
+ else
+ capout[1] = chanout[2]; // cap1 = ch2
+
+ capout[0] = MinMax(capout[0], -0x8000, 0x7FFF);
+ capout[1] = MinMax(capout[1], -0x8000, 0x7FFF);
+
+ // write the output sample where it is supposed to go
+ if (!samp)
{
samp0[0] = sndout[0];
samp0[1] = sndout[1];
}
else
{
- SPU->sndbuf[samp*2+0] = sndout[0];
- SPU->sndbuf[samp*2+1] = sndout[1];
- }
-
- for(int capchan=0;capchan<2;capchan++)
- {
- if(SPU->regs.cap[capchan].runtime.running)
+ SPU->sndbuf[samp * 2] = sndout[0];
+ SPU->sndbuf[samp * 2 + 1] = sndout[1];
+ }
+
+ for (int capchan = 0; capchan < 2; ++capchan)
+ {
+ if (SPU->regs.cap[capchan].runtime.running)
{
- SPU_struct::REGS::CAP& cap = SPU->regs.cap[capchan];
+ SPU_struct::REGS::CAP &cap = SPU->regs.cap[capchan];
uint32_t last = u32floor(cap.runtime.sampcnt);
- cap.runtime.sampcnt += SPU->channels[1+2*capchan].sampinc;
+ cap.runtime.sampcnt += SPU->channels[2 * capchan + 1].sampinc;
uint32_t curr = u32floor(cap.runtime.sampcnt);
- for(uint32_t j=last;j<curr;j++)
+ for (uint32_t j = last; j < curr; ++j)
{
- //so, this is a little strange. why go through a fifo?
- //it seems that some games will set up a reverb effect by capturing
- //to the nearly same address as playback, but ahead by a couple.
- //So, playback will always end up being what was captured a couple of samples ago.
- //This system counts on playback always having read ahead 16 samples.
- //In that case, playback will end up being what was processed at one entire buffer length ago,
- //since the 16 samples would have read ahead before they got captured over
-
- //It's actually the source channels which should have a fifo, but we are
- //not going to take the hit in speed and complexity. Save it for a future rewrite.
- //Instead, what we do here is delay the capture by 16 samples to create a similar effect.
- //Subjectively, it seems to be working.
-
- //Don't do anything until the fifo is filled, so as to delay it
- if(cap.runtime.fifo.size<16)
+ // so, this is a little strange. why go through a fifo?
+ // it seems that some games will set up a reverb effect by capturing
+ // to the nearly same address as playback, but ahead by a couple.
+ // So, playback will always end up being what was captured a couple of samples ago.
+ // This system counts on playback always having read ahead 16 samples.
+ // In that case, playback will end up being what was processed at one entire buffer length ago,
+ // since the 16 samples would have read ahead before they got captured over
+
+ // It's actually the source channels which should have a fifo, but we are
+ // not going to take the hit in speed and complexity. Save it for a future rewrite.
+ // Instead, what we do here is delay the capture by 16 samples to create a similar effect.
+ // Subjectively, it seems to be working.
+
+ // Don't do anything until the fifo is filled, so as to delay it
+ if (cap.runtime.fifo.size < 16)
{
cap.runtime.fifo.enqueue(static_cast<int16_t>(capout[capchan]));
continue;
}
- //(actually capture sample from fifo instead of most recently generated)
- uint32_t multiplier;
+ // (actually capture sample from fifo instead of most recently generated)
int32_t sample = cap.runtime.fifo.dequeue();
cap.runtime.fifo.enqueue(static_cast<int16_t>(capout[capchan]));
- //static FILE* fp = NULL;
- //if(!fp) fp = fopen("d:\\capout.raw","wb");
- //fwrite(&sample,2,1,fp);
-
- if(cap.bits8)
+ uint32_t multiplier;
+ if (cap.bits8)
{
- int8_t sample8 = static_cast<int8_t>(sample>>8);
- if(skipcap) _MMU_write08<1,MMU_AT_DMA>(cap.runtime.curdad,0);
- else _MMU_write08<1,MMU_AT_DMA>(cap.runtime.curdad,sample8);
- cap.runtime.curdad++;
+ int8_t sample8 = static_cast<int8_t>(sample >> 8);
+ if (skipcap)
+ _MMU_write08<1, MMU_AT_DMA>(cap.runtime.curdad, 0);
+ else
+ _MMU_write08<1, MMU_AT_DMA>(cap.runtime.curdad, sample8);
+ ++cap.runtime.curdad;
multiplier = 4;
}
else
{
int16_t sample16 = static_cast<int16_t>(sample);
- if(skipcap) _MMU_write16<1,MMU_AT_DMA>(cap.runtime.curdad,0);
- else _MMU_write16<1,MMU_AT_DMA>(cap.runtime.curdad,sample16);
- cap.runtime.curdad+=2;
+ if (skipcap)
+ _MMU_write16<1, MMU_AT_DMA>(cap.runtime.curdad, 0);
+ else
+ _MMU_write16<1, MMU_AT_DMA>(cap.runtime.curdad, sample16);
+ cap.runtime.curdad += 2;
multiplier = 2;
}
- if(cap.runtime.curdad>=cap.runtime.maxdad) {
+ if (cap.runtime.curdad >= cap.runtime.maxdad)
+ {
cap.runtime.curdad = cap.dad;
- cap.runtime.sampcnt -= cap.len*multiplier;
+ cap.runtime.sampcnt -= cap.len * multiplier;
}
- } //sampinc loop
- } //if capchan running
- } //capchan loop
- } //main sample loop
+ } // sampinc loop
+ } // if capchan running
+ } // capchan loop
+ } // main sample loop
SPU->sndbuf[0] = samp0[0];
SPU->sndbuf[1] = samp0[1];
}
-//ENTER
+// ENTER
static void SPU_MixAudio(bool actuallyMix, SPU_struct *SPU, int length)
{
- if(actuallyMix)
- {
- memset(SPU->sndbuf, 0, length*4*2);
- memset(SPU->outbuf, 0, length*2*2);
- }
-
- //we used to use master enable here, and do nothing if audio is disabled.
- //now, master enable is emulated better..
- //but for a speed optimization we will still do it
- if(!SPU->regs.masteren) return;
-
- bool advanced = CommonSettings.spu_advanced ;
-
- //branch here so that slow computers don't have to take the advanced (slower) codepath.
- //it remainds to be seen exactly how much slower it is
- //if it isnt much slower then we should refactor everything to be simpler, once it is working
- if(advanced && SPU == SPU_core)
- {
+ if (actuallyMix)
+ {
+ memset(&SPU->sndbuf[0], 0, length * 4 * 2);
+ memset(&SPU->outbuf[0], 0, length * 2 * 2);
+ }
+
+ // we used to use master enable here, and do nothing if audio is disabled.
+ // now, master enable is emulated better..
+ // but for a speed optimization we will still do it
+ if (!SPU->regs.masteren)
+ return;
+
+ bool advanced = CommonSettings.spu_advanced;
+
+ // branch here so that slow computers don't have to take the advanced (slower) codepath.
+ // it remainds to be seen exactly how much slower it is
+ // if it isnt much slower then we should refactor everything to be simpler, once it is working
+ if (advanced && SPU == SPU_core.get())
SPU_MixAudio_Advanced(actuallyMix, SPU, length);
- }
else
{
- //non-advanced mode
- for(int i=0;i<16;i++)
+ // non-advanced mode
+ for (int i = 0; i < 16; ++i)
{
channel_struct *chan = &SPU->channels[i];
@@ -1349,83 +1398,119 @@
}
}
- //we used to bail out if speakers were disabled.
- //this is technically wrong. sound may still be captured, or something.
- //in all likelihood, any game doing this probably master disabled the SPU also
- //so, optimization of this case is probably not necessary.
- //later, we'll just silence the output
+ // we used to bail out if speakers were disabled.
+ // this is technically wrong. sound may still be captured, or something.
+ // in all likelihood, any game doing this probably master disabled the SPU also
+ // so, optimization of this case is probably not necessary.
+ // later, we'll just silence the output
bool speakers = T1ReadWord(MMU.ARM7_REG, 0x304) & 0x01;
uint8_t vol = SPU->regs.mastervol;
// convert from 32-bit->16-bit
- if(actuallyMix && speakers)
- for (int i = 0; i < length*2; i++)
+ if (actuallyMix && speakers)
+ for (int i = 0; i < length * 2; ++i)
{
// Apply Master Volume
SPU->sndbuf[i] = spumuldiv7(SPU->sndbuf[i], vol);
- int16_t outsample = static_cast<int16_t>(MinMax<int32_t>(SPU->sndbuf[i],-0x8000,0x7FFF));
+ int16_t outsample = static_cast<int16_t>(MinMax(SPU->sndbuf[i], -0x8000, 0x7FFF));
SPU->outbuf[i] = outsample;
}
-
-
}
//////////////////////////////////////////////////////////////////////////////
-
-//emulates one hline of the cpu core.
-//this will produce a variable number of samples, calculated to keep a 44100hz output
-//in sync with the emulator framerate
+// emulates one hline of the cpu core.
+// this will produce a variable number of samples, calculated to keep a 44100hz output
+// in sync with the emulator framerate
int spu_core_samples = 0;
void SPU_Emulate_core()
{
+ bool needToMix = true;
+
samples += samples_per_hline;
- spu_core_samples = (int)(samples);
+ spu_core_samples = static_cast<int>(samples);
samples -= spu_core_samples;
- bool synchronize = (synchmode == ESynchMode_Synchronous);
- bool mix = /*driver->AVI_IsRecording() || driver->WAV_IsRecording() ||*/ synchronize;
-
- SPU_MixAudio(mix,SPU_core,spu_core_samples);
- if(synchronize && SPU_currentCoreNum != SNDCORE_DUMMY)
- synchronizer->enqueue_samples(SPU_core->outbuf, spu_core_samples);
+ // We don't need to mix audio for Dual Synch/Asynch mode since we do this
+ // later in SPU_Emulate_user(). Disable mixing here to speed up processing.
+ // However, recording still needs to mix the audio, so make sure we're also
+ // not recording before we disable mixing.
+ if (synchmode == ESynchMode_DualSynchAsynch)
+ needToMix = false;
+
+ SPU_MixAudio(needToMix, SPU_core.get(), spu_core_samples);
+
+ if (!SNDCore)
+ return;
+
+ if (SNDCore->FetchSamples)
+ SNDCore->FetchSamples(&SPU_core->outbuf[0], spu_core_samples, synchmode, synchronizer.get());
+ else
+ SPU_DefaultFetchSamples(&SPU_core->outbuf[0], spu_core_samples, synchmode, synchronizer.get());
}
void SPU_Emulate_user(bool mix)
{
- uint32_t audiosize;
-
- // Check to see how much free space there is
- // If there is some, fill up the buffer
- if(!SNDCore) return;
- audiosize = SNDCore->GetAudioSpace();
-
- if (audiosize > 0)
- {
- //printf("mix %i samples\n", audiosize);
- if (audiosize > (uint32_t)buffersize)
- audiosize = buffersize;
-
- int16_t* outbuf;
- int samplesOutput;
- if(synchmode == ESynchMode_Synchronous)
- {
- static std::vector<int16_t> tempbuf;
- if(tempbuf.size() < audiosize*2) tempbuf.resize(audiosize*2);
- outbuf = &tempbuf[0];
- samplesOutput = synchronizer->output_samples(outbuf, audiosize);
- }
- else if(SPU_user)
- {
- outbuf = SPU_user->outbuf;
- samplesOutput = (SPU_MixAudio(mix,SPU_user,audiosize), audiosize);
- }
- else return;
-
- SNDCore->UpdateAudio(outbuf, samplesOutput);
- //WAV_WavSoundUpdate(SPU_user->outbuf, samplesOutput, WAVMODE_USER);
- }
+ static std::vector<int16_t> postProcessBuffer;
+ static size_t postProcessBufferSize = 0;
+ size_t processedSampleCount = 0;
+
+ if (!SNDCore)
+ return;
+
+ // Check to see how many free samples are available.
+ // If there are some, fill up the output buffer.
+ size_t freeSampleCount = SNDCore->GetAudioSpace();
+ if (!freeSampleCount)
+ return;
+
+ //printf("mix %i samples\n", audiosize);
+ if (freeSampleCount > buffersize)
+ freeSampleCount = buffersize;
+
+ // If needed, resize the post-process buffer to guarantee that
+ // we can store all the sound data.
+ if (postProcessBufferSize < freeSampleCount * 2 * sizeof(int16_t))
+ {
+ postProcessBufferSize = freeSampleCount * 2 * sizeof(int16_t);
+ postProcessBuffer.resize(postProcessBufferSize);
+ }
+
+ if (SNDCore->PostProcessSamples)
+ processedSampleCount = SNDCore->PostProcessSamples(&postProcessBuffer[0], freeSampleCount, synchmode, synchronizer.get());
+ else
+ processedSampleCount = SPU_DefaultPostProcessSamples(&postProcessBuffer[0], freeSampleCount, synchmode, synchronizer.get());
+
+ SNDCore->UpdateAudio(&postProcessBuffer[0], processedSampleCount);
+}
+
+void SPU_DefaultFetchSamples(int16_t *sampleBuffer, size_t sampleCount, ESynchMode synchMode, ISynchronizingAudioBuffer *theSynchronizer)
+{
+ if (synchMode == ESynchMode_Synchronous)
+ theSynchronizer->enqueue_samples(sampleBuffer, sampleCount);
+}
+
+size_t SPU_DefaultPostProcessSamples(int16_t *postProcessBuffer, size_t requestedSampleCount, ESynchMode synchMode, ISynchronizingAudioBuffer *theSynchronizer)
+{
+ size_t processedSampleCount = 0;
+
+ switch (synchMode)
+ {
+ case ESynchMode_DualSynchAsynch:
+ if (SPU_user)
+ {
+ SPU_MixAudio(true, SPU_user.get(), requestedSampleCount);
+ memcpy(postProcessBuffer, &SPU_user->outbuf[0], requestedSampleCount * 2 * sizeof(int16_t));
+ processedSampleCount = requestedSampleCount;
+ }
+ break;
+
+ case ESynchMode_Synchronous:
+ processedSampleCount = theSynchronizer->output_samples(postProcessBuffer, requestedSampleCount);
+ }
+
+ return processedSampleCount;
}
//////////////////////////////////////////////////////////////////////////////
@@ -1435,12 +1520,16 @@
int SNDDummyInit(int) { return 0; }
void SNDDummyDeInit() {}
void SNDDummyUpdateAudio(int16_t *, uint32_t) { }
-uint32_t SNDDummyGetAudioSpace() { return DESMUME_SAMPLE_RATE/60 + 5; }
+uint32_t SNDDummyGetAudioSpace() { return DESMUME_SAMPLE_RATE / 60 + 5; }
void SNDDummyMuteAudio() {}
void SNDDummyUnMuteAudio() {}
void SNDDummySetVolume(int) {}
-
-SoundInterface_struct SNDDummy = {
+void SNDDummyClearBuffer() {}
+void SNDDummyFetchSamples(int16_t *sampleBuffer, size_t sampleCount, ESynchMode synchMode, ISynchronizingAudioBuffer *theSynchronizer) {}
+size_t SNDDummyPostProcessSamples(int16_t *postProcessBuffer, size_t requestedSampleCount, ESynchMode synchMode, ISynchronizingAudioBuffer *theSynchronizer) { return 0; }
+
+SoundInterface_struct SNDDummy =
+{
SNDCORE_DUMMY,
"Dummy Sound Interface",
SNDDummyInit,
@@ -1450,309 +1539,8 @@
SNDDummyMuteAudio,
SNDDummyUnMuteAudio,
SNDDummySetVolume,
- NULL
+ SNDDummyClearBuffer,
+ SNDDummyFetchSamples,
+ SNDDummyPostProcessSamples
};
-//---------wav writer------------
-
-/*typedef struct {
- char id[4];
- uint32_t size;
-} chunk_struct;
-
-typedef struct {
- chunk_struct riff;
- char rifftype[4];
-} waveheader_struct;
-
-typedef struct {
- chunk_struct chunk;
- uint16_t compress;
- uint16_t numchan;
- uint32_t rate;
- uint32_t bytespersec;
- uint16_t blockalign;
- uint16_t bitspersample;
-} fmt_struct;
-
-WavWriter::WavWriter()
-: spufp(NULL)
-{
-}
-bool WavWriter::open(const std::string & fname)
-{
- waveheader_struct waveheader;
- fmt_struct fmt;
- chunk_struct data;
- size_t elems_written = 0;
-
- if ((spufp = fopen(fname.c_str(), "wb")) == NULL)
- return false;
-
- // Do wave header
- memcpy(waveheader.riff.id, "RIFF", 4);
- waveheader.riff.size = 0; // we'll fix this after the file is closed
- memcpy(waveheader.rifftype, "WAVE", 4);
- elems_written += fwrite((void *)&waveheader, 1, sizeof(waveheader_struct), spufp);
-
- // fmt chunk
- memcpy(fmt.chunk.id, "fmt ", 4);
- fmt.chunk.size = 16; // we'll fix this at the end
- fmt.compress = 1; // PCM
- fmt.numchan = 2; // Stereo
- fmt.rate = DESMUME_SAMPLE_RATE;
- fmt.bitspersample = 16;
- fmt.blockalign = fmt.bitspersample / 8 * fmt.numchan;
- fmt.bytespersec = fmt.rate * fmt.blockalign;
- elems_written += fwrite((void *)&fmt, 1, sizeof(fmt_struct), spufp);
-
- // data chunk
- memcpy(data.id, "data", 4);
- data.size = 0; // we'll fix this at the end
- elems_written += fwrite((void *)&data, 1, sizeof(chunk_struct), spufp);
-
- return true;
-}
-
-void WavWriter::close()
-{
- if(!spufp) return;
- size_t elems_written = 0;
- long length = ftell(spufp);
-
- // Let's fix the riff chunk size and the data chunk size
- fseek(spufp, sizeof(waveheader_struct)-0x8, SEEK_SET);
- length -= 0x8;
- elems_written += fwrite((void *)&length, 1, 4, spufp);
-
- fseek(spufp, sizeof(waveheader_struct)+sizeof(fmt_struct)+0x4, SEEK_SET);
- length -= sizeof(waveheader_struct)+sizeof(fmt_struct);
- elems_written += fwrite((void *)&length, 1, 4, spufp);
- fclose(spufp);
- spufp = NULL;
-}
-
-void WavWriter::update(void* soundData, int numSamples)
-{
- if(!spufp) return;
- //TODO - big endian for the int16_t samples??*/
- /*size_t elems_written = *//*fwrite(soundData, numSamples*2, 2, spufp);
-}
-
-bool WavWriter::isRecording() const
-{
- return spufp != NULL;
-}*/
-
-
-//static WavWriter wavWriter;
-
-/*void WAV_End()
-{
- wavWriter.close();
-}*/
-
-/*bool WAV_Begin(const char* fname, WAVMode mode)
-{
- WAV_End();
-
- if(!wavWriter.open(fname))
- return false;
-
- if(mode == WAVMODE_ANY)
- mode = WAVMODE_CORE;
- wavWriter.mode = mode;
-
- driver->USR_InfoMessage("WAV recording started.");
-
- return true;
-}*/
-
-/*bool WAV_IsRecording(WAVMode mode)
-{
- if(wavWriter.mode == mode || mode == WAVMODE_ANY)
- return wavWriter.isRecording();
- return false;
-}*/
-
-/*void WAV_WavSoundUpdate(void* soundData, int numSamples, WAVMode mode)
-{
- if(wavWriter.mode == mode || mode == WAVMODE_ANY)
- wavWriter.update(soundData, numSamples);
-}*/
-
-
-
-//////////////////////////////////////////////////////////////////////////////
-
-/*void spu_savestate(EMUFILE* os)
-{
- //version
- write32le(6,os);
-
- SPU_struct *spu = SPU_core;
-
- for(int j=0;j<16;j++) {
- channel_struct &chan = spu->channels[j];
- write32le(chan.num,os);
- write8le(chan.vol,os);
- write8le(chan.datashift,os);
- write8le(chan.hold,os);
- write8le(chan.pan,os);
- write8le(chan.waveduty,os);
- write8le(chan.repeat,os);
- write8le(chan.format,os);
- write8le(chan.status,os);
- write32le(chan.addr,os);
- write16le(chan.timer,os);
- write16le(chan.loopstart,os);
- write32le(chan.length,os);
- write64le(double_to_u64(chan.sampcnt),os);
- write64le(double_to_u64(chan.sampinc),os);
- write32le(chan.lastsampcnt,os);
- write16le(chan.pcm16b,os);
- write16le(chan.pcm16b_last,os);
- write32le(chan.index,os);
- write16le(chan.x,os);
- write16le(chan.psgnoise_last,os);
- write8le(chan.keyon,os);
- }
-
- write64le(double_to_u64(samples),os);
-
- write8le(spu->regs.mastervol,os);
- write8le(spu->regs.ctl_left,os);
- write8le(spu->regs.ctl_right,os);
- write8le(spu->regs.ctl_ch1bypass,os);
- write8le(spu->regs.ctl_ch3bypass,os);
- write8le(spu->regs.masteren,os);
- write16le(spu->regs.soundbias,os);
-
- for(int i=0;i<2;i++)
- {
- write8le(spu->regs.cap[i].add,os);
- write8le(spu->regs.cap[i].source,os);
- write8le(spu->regs.cap[i].oneshot,os);
- write8le(spu->regs.cap[i].bits8,os);
- write8le(spu->regs.cap[i].active,os);
- write32le(spu->regs.cap[i].dad,os);
- write16le(spu->regs.cap[i].len,os);
- write8le(spu->regs.cap[i].runtime.running,os);
- write32le(spu->regs.cap[i].runtime.curdad,os);
- write32le(spu->regs.cap[i].runtime.maxdad,os);
- write_double_le(spu->regs.cap[i].runtime.sampcnt,os);
- }
-
- for(int i=0;i<2;i++)
- spu->regs.cap[i].runtime.fifo.save(os);
-}*/
-
-bool spu_loadstate(EMUFILE* is, int)
-{
- uint64_t temp64;
-
- //read version
- uint32_t version;
- if(read32le(&version,is) != 1) return false;
-
- SPU_struct *spu = SPU_core;
- reconstruct(&SPU_core->regs);
-
- for(int j=0;j<16;j++) {
- channel_struct &chan = spu->channels[j];
- read32le(&chan.num,is);
- read8le(&chan.vol,is);
- read8le(&chan.datashift,is);
- read8le(&chan.hold,is);
- read8le(&chan.pan,is);
- read8le(&chan.waveduty,is);
- read8le(&chan.repeat,is);
- read8le(&chan.format,is);
- read8le(&chan.status,is);
- read32le(&chan.addr,is);
- read16le(&chan.timer,is);
- read16le(&chan.loopstart,is);
- read32le(&chan.length,is);
- chan.totlength = chan.length + chan.loopstart;
- chan.double_totlength_shifted = (double)(chan.totlength << format_shift[chan.format]);
- //printf("%f\n",chan.double_totlength_shifted);
- if(version >= 2)
- {
- read64le(&temp64,is); chan.sampcnt = u64_to_double(temp64);
- read64le(&temp64,is); chan.sampinc = u64_to_double(temp64);
- }
- else
- {
- read32le((uint32_t*)&chan.sampcnt,is);
- read32le((uint32_t*)&chan.sampinc,is);
- }
- read32le(&chan.lastsampcnt,is);
- read16le(&chan.pcm16b,is);
- read16le(&chan.pcm16b_last,is);
- read32le(&chan.index,is);
- read16le(&chan.x,is);
- read16le(&chan.psgnoise_last,is);
-
- if(version>=4)
- read8le(&chan.keyon,is);
-
- //hopefully trigger a recovery of the adpcm looping system
- chan.loop_index = K_ADPCM_LOOPING_RECOVERY_INDEX;
-
- //fixup the pointers which we had are supposed to keep cached
- chan.buf8 = (int8_t*)&MMU.MMU_MEM[1][(chan.addr>>20)&0xFF][(chan.addr & MMU.MMU_MASK[1][(chan.addr >> 20) & 0xFF])];
- chan.buf16 = (int16_t*)chan.buf8;
- }
-
- if(version>=2) {
- read64le(&temp64,is); samples = u64_to_double(temp64);
- }
-
- if(version>=4)
- {
- read8le(&spu->regs.mastervol,is);
- read8le(&spu->regs.ctl_left,is);
- read8le(&spu->regs.ctl_right,is);
- read8le(&spu->regs.ctl_ch1bypass,is);
- read8le(&spu->regs.ctl_ch3bypass,is);
- read8le(&spu->regs.masteren,is);
- read16le(&spu->regs.soundbias,is);
- }
-
- if(version>=5)
- {
- for(int i=0;i<2;i++)
- {
- read8le(&spu->regs.cap[i].add,is);
- read8le(&spu->regs.cap[i].source,is);
- read8le(&spu->regs.cap[i].oneshot,is);
- read8le(&spu->regs.cap[i].bits8,is);
- read8le(&spu->regs.cap[i].active,is);
- read32le(&spu->regs.cap[i].dad,is);
- read16le(&spu->regs.cap[i].len,is);
- read8le(&spu->regs.cap[i].runtime.running,is);
- read32le(&spu->regs.cap[i].runtime.curdad,is);
- read32le(&spu->regs.cap[i].runtime.maxdad,is);
- read_double_le(&spu->regs.cap[i].runtime.sampcnt,is);
- }
- }
-
- if(version>=6)
- for(int i=0;i<2;i++) spu->regs.cap[i].runtime.fifo.load(is);
- else
- for(int i=0;i<2;i++) spu->regs.cap[i].runtime.fifo.reset();
-
- //older versions didnt store a mastervol;
- //we must reload this or else games will start silent
- if(version<4)
- {
- spu->regs.mastervol = T1ReadByte(MMU.ARM7_REG, 0x500) & 0x7F;
- spu->regs.masteren = static_cast<uint8_t>(BIT15(T1ReadWord(MMU.ARM7_REG, 0x500)));
- }
-
- //copy the core spu (the more accurate) to the user spu
- SPU_CloneUser();
-
- return true;
-}
-
--- a/src/in_2sf/desmume/SPU.h
+++ b/src/in_2sf/desmume/SPU.h
@@ -22,46 +22,44 @@
#include <iosfwd>
#include <string>
#include <cassert>
-
#include "types.h"
#include "matrix.h"
#include "emufile.h"
-
#include "metaspu/metaspu.h"
-#define SNDCORE_DEFAULT -1
-#define SNDCORE_DUMMY 0
-
-#define CHANSTAT_STOPPED 0
-#define CHANSTAT_PLAY 1
-
-//who made these static? theyre used in multiple places.
-//inline uint32_t sputrunc(float f) { return u32floor(f); }
-//inline uint32_t sputrunc(double d) { return u32floor(d); }
-inline int32_t spumuldiv7(int32_t val, uint8_t multiplier) {
+const int SNDCORE_DEFAULT = -1;
+const int SNDCORE_DUMMY = 0;
+
+const uint8_t CHANSTAT_STOPPED = 0;
+const uint8_t CHANSTAT_PLAY = 1;
+
+inline int32_t spumuldiv7(int32_t val, uint8_t multiplier)
+{
assert(multiplier <= 127);
return multiplier == 127 ? val : ((val * multiplier) >> 7);
}
enum SPUInterpolationMode
{
- SPUInterpolation_None = 0,
- SPUInterpolation_Linear = 1,
- SPUInterpolation_Cosine = 2
+ SPUInterpolation_None ,
+ SPUInterpolation_Linear,
+ SPUInterpolation_Cosine
};
struct SoundInterface_struct
{
- int id;
- const char *Name;
- int (*Init)(int buffersize);
- void (*DeInit)();
- void (*UpdateAudio)(int16_t *buffer, uint32_t num_samples);
- uint32_t (*GetAudioSpace)();
- void (*MuteAudio)();
- void (*UnMuteAudio)();
- void (*SetVolume)(int volume);
- void (*ClearBuffer)();
+ int id;
+ const char *Name;
+ int (*Init)(int buffersize);
+ void (*DeInit)();
+ void (*UpdateAudio)(int16_t *buffer, uint32_t num_samples);
+ uint32_t (*GetAudioSpace)();
+ void (*MuteAudio)();
+ void (*UnMuteAudio)();
+ void (*SetVolume)(int volume);
+ void (*ClearBuffer)();
+ void (*FetchSamples)(int16_t *sampleBuffer, size_t sampleCount, ESynchMode synchMode, ISynchronizingAudioBuffer *theSynchronizer);
+ size_t (*PostProcessSamples)(int16_t *postProcessBuffer, size_t requestedSampleCount, ESynchMode synchMode, ISynchronizingAudioBuffer *theSynchronizer);
};
extern SoundInterface_struct SNDDummy;
@@ -70,38 +68,33 @@
struct channel_struct
{
- channel_struct()
- {}
+ channel_struct() { }
uint32_t num;
- uint8_t vol;
- uint8_t datashift;
- uint8_t hold;
- uint8_t pan;
- uint8_t waveduty;
- uint8_t repeat;
- uint8_t format;
- uint8_t keyon;
- uint8_t status;
- uint32_t addr;
- uint16_t timer;
- uint16_t loopstart;
- uint32_t length;
- uint32_t totlength;
- double double_totlength_shifted;
- union {
- int8_t *buf8;
- int16_t *buf16;
- };
- double sampcnt;
- double sampinc;
- // ADPCM specific
- uint32_t lastsampcnt;
- int16_t pcm16b, pcm16b_last;
- int16_t loop_pcm16b;
- int32_t index;
- int loop_index;
- uint16_t x;
- int16_t psgnoise_last;
+ uint8_t vol;
+ uint8_t datashift;
+ uint8_t hold;
+ uint8_t pan;
+ uint8_t waveduty;
+ uint8_t repeat;
+ uint8_t format;
+ uint8_t keyon;
+ uint8_t status;
+ uint32_t addr;
+ uint16_t timer;
+ uint16_t loopstart;
+ uint32_t length;
+ uint32_t totlength;
+ double double_totlength_shifted;
+ double sampcnt;
+ double sampinc;
+ // ADPCM specific
+ uint32_t lastsampcnt;
+ int16_t pcm16b, pcm16b_last;
+ int16_t loop_pcm16b;
+ int32_t index;
+ int loop_index;
+ uint16_t x;
+ int16_t psgnoise_last;
};
class SPUFifo
@@ -111,9 +104,7 @@
void enqueue(int16_t val);
int16_t dequeue();
int16_t buffer[16];
- int32_t head,tail,size;
- //void save(EMUFILE* fp);
- bool load(EMUFILE* fp);
+ int32_t head, tail, size;
void reset();
};
@@ -121,88 +112,80 @@
{
public:
SPU_struct(int buffersize);
- uint32_t bufpos;
- uint32_t buflength;
- int32_t *sndbuf;
- int32_t lastdata; //the last sample that a channel generated
- int16_t *outbuf;
- uint32_t bufsize;
- channel_struct channels[16];
-
- //registers
- struct REGS {
- REGS()
- : mastervol(0)
- , ctl_left(0)
- , ctl_right(0)
- , ctl_ch1bypass(0)
- , ctl_ch3bypass(0)
- , masteren(0)
- , soundbias(0)
- {}
-
- uint8_t mastervol;
- uint8_t ctl_left, ctl_right;
- uint8_t ctl_ch1bypass, ctl_ch3bypass;
- uint8_t masteren;
- uint16_t soundbias;
-
- enum LeftOutputMode
- {
- LOM_LEFT_MIXER=0, LOM_CH1=1, LOM_CH3=2, LOM_CH1_PLUS_CH3=3
- };
-
- enum RightOutputMode
- {
- ROM_RIGHT_MIXER=0, ROM_CH1=1, ROM_CH3=2, ROM_CH1_PLUS_CH3=3
- };
-
- struct CAP {
- CAP()
- : add(0), source(0), oneshot(0), bits8(0), active(0), dad(0), len(0)
- {}
- uint8_t add, source, oneshot, bits8, active;
- uint32_t dad;
- uint16_t len;
- struct Runtime {
- Runtime()
- : running(0), curdad(0), maxdad(0)
- {}
- uint8_t running;
- uint32_t curdad;
- uint32_t maxdad;
- double sampcnt;
- SPUFifo fifo;
- } runtime;
- } cap[2];
- } regs;
-
- void reset();
- ~SPU_struct();
- void KeyOff(int channel);
- void KeyOn(int channel);
- void KeyProbe(int channel);
- void ProbeCapture(int which);
- void WriteByte(uint32_t addr, uint8_t val);
- uint8_t ReadByte(uint32_t addr);
- uint16_t ReadWord(uint32_t addr);
- uint32_t ReadLong(uint32_t addr);
- void WriteWord(uint32_t addr, uint16_t val);
- void WriteLong(uint32_t addr, uint32_t val);
-
- //kills all channels but leaves SPU otherwise running normally
- void ShutUp();
+ uint32_t bufpos;
+ uint32_t buflength;
+ std::unique_ptr<int32_t[]> sndbuf;
+ int32_t lastdata; //the last sample that a channel generated
+ std::unique_ptr<int16_t[]> outbuf;
+ uint32_t bufsize;
+ channel_struct channels[16];
+
+ // registers
+ struct REGS
+ {
+ REGS() : mastervol(0), ctl_left(0), ctl_right(0), ctl_ch1bypass(0), ctl_ch3bypass(0), masteren(0), soundbias(0) { }
+
+ uint8_t mastervol;
+ uint8_t ctl_left, ctl_right;
+ uint8_t ctl_ch1bypass, ctl_ch3bypass;
+ uint8_t masteren;
+ uint16_t soundbias;
+
+ enum LeftOutputMode
+ {
+ LOM_LEFT_MIXER,
+ LOM_CH1,
+ LOM_CH3,
+ LOM_CH1_PLUS_CH3
+ };
+
+ enum RightOutputMode
+ {
+ ROM_RIGHT_MIXER,
+ ROM_CH1,
+ ROM_CH3,
+ ROM_CH1_PLUS_CH3
+ };
+
+ struct CAP
+ {
+ CAP() : add(0), source(0), oneshot(0), bits8(0), active(0), dad(0), len(0) { }
+ uint8_t add, source, oneshot, bits8, active;
+ uint32_t dad;
+ uint16_t len;
+ struct Runtime
+ {
+ Runtime() : running(0), curdad(0), maxdad(0) { }
+ uint8_t running;
+ uint32_t curdad;
+ uint32_t maxdad;
+ double sampcnt;
+ SPUFifo fifo;
+ } runtime;
+ } cap[2];
+ } regs;
+
+ void reset();
+ void KeyOff(int channel);
+ void KeyOn(int channel);
+ void KeyProbe(int channel);
+ void ProbeCapture(int which);
+ void WriteByte(uint32_t addr, uint8_t val);
+ uint8_t ReadByte(uint32_t addr);
+ uint16_t ReadWord(uint32_t addr);
+ uint32_t ReadLong(uint32_t addr);
+ void WriteWord(uint32_t addr, uint16_t val);
+ void WriteLong(uint32_t addr, uint32_t val);
+
+ // kills all channels but leaves SPU otherwise running normally
+ void ShutUp();
};
int SPU_ChangeSoundCore(int coreid, int buffersize);
-//SoundInterface_struct *SPU_SoundCore();
void SPU_ReInit();
int SPU_Init(int coreid, int buffersize);
-//void SPU_Pause(int pause);
-//void SPU_SetVolume(int volume);
void SPU_SetSynchMode(ESynchMode mode, ESynchMethod method);
-//void SPU_ClearOutputBuffer();
void SPU_Reset();
void SPU_DeInit();
void SPU_KeyOn(int channel);
@@ -214,41 +197,15 @@
uint32_t SPU_ReadLong(uint32_t addr);
void SPU_Emulate_core();
void SPU_Emulate_user(bool mix = true);
-
-extern SPU_struct *SPU_core, *SPU_user;
+void SPU_DefaultFetchSamples(int16_t *sampleBuffer, size_t sampleCount, ESynchMode synchMode, ISynchronizingAudioBuffer *theSynchronizer);
+size_t SPU_DefaultPostProcessSamples(int16_t *postProcessBuffer, size_t requestedSampleCount, ESynchMode synchMode, ISynchronizingAudioBuffer *theSynchronizer);
+
+extern std::unique_ptr<SPU_struct> SPU_core, SPU_user;
extern int spu_core_samples;
-
-//void spu_savestate(EMUFILE* os);
-bool spu_loadstate(EMUFILE* is, int size);
-
-/*enum WAVMode
-{
- WAVMODE_ANY = -1,
- WAVMODE_CORE = 0,
- WAVMODE_USER = 1
-};*/
-
-/*class WavWriter
-{
-public:
- WavWriter();
- bool open(const std::string & fname);
- void close();
- void update(void* soundData, int numSamples);
- bool isRecording() const;
- WAVMode mode;
-private:
- FILE *spufp;
-};*/
-
-//void WAV_End();
-//bool WAV_Begin(const char* fname, WAVMode mode=WAVMODE_CORE);
-//bool WAV_IsRecording(WAVMode mode=WAVMODE_ANY);
-//void WAV_WavSoundUpdate(void* soundData, int numSamples, WAVMode mode=WAVMODE_CORE);
// we should make this configurable eventually
// but at least defining it somewhere is probably a step in the right direction
-#define DESMUME_SAMPLE_RATE 44100
+const int DESMUME_SAMPLE_RATE = 44100;
//#define DESMUME_SAMPLE_RATE 48000
#endif
--- a/src/in_2sf/desmume/addons/slot1_retail.cpp
+++ b/src/in_2sf/desmume/addons/slot1_retail.cpp
@@ -40,7 +40,7 @@
switch (card.command[0])
{
- case 0x00: //Data read
+ case 0x00: // Data read
case 0xB7:
card.address = (card.command[1] << 24) | (card.command[2] << 16) | (card.command[3] << 8) | card.command[4];
card.transfer_count = 0x80;
@@ -90,9 +90,12 @@
// Most games continuously compare the chip ID with
// the value in memory, probably to know if the card
// was removed.
- // As DeSmuME boots directly from the game, the chip
+ // As DeSmuME normally boots directly from the game, the chip
// ID in main mem is zero and this value needs to be
// zero too.
+
+ // note that even if desmume was booting from firmware, and reading this chip ID to store in main memory,
+ // this still works, since it will have read 00 originally and then read 00 to validate.
// staff of kings verifies this (it also uses the arm7 IRQ 20)
if (nds.cardEjected) // TODO - handle this with ejected card slot1 device (and verify using this case)
@@ -106,20 +109,20 @@
case 0x00:
case 0xB7:
{
- //it seems that etrian odyssey 3 doesnt work unless we mask this to cart size.
- //but, a thought: does the internal rom address counter register wrap around? we may be making a mistake by keeping the extra precision
- //but there is no test case yet
- uint32_t address = card.address & (gameInfo.mask);
+ // it seems that etrian odyssey 3 doesnt work unless we mask this to cart size.
+ // but, a thought: does the internal rom address counter register wrap around? we may be making a mistake by keeping the extra precision
+ // but there is no test case yet
+ uint32_t address = card.address & gameInfo.mask;
// Make sure any reads below 0x8000 redirect to 0x8000+(adr&0x1FF) as on real cart
- if((card.command[0] == 0xB7) && (address < 0x8000))
+ if (card.command[0] == 0xB7 && address < 0x8000)
{
// TODO - refactor this to include the PROCNUM, for debugging purposes if nothing else
// (can refactor gbaslot also)
//INFO("Read below 0x8000 (0x%04X) from: ARM%s %08X\n", card.address, (PROCNUM ? "7":"9"), (PROCNUM ? NDS_ARM7:NDS_ARM9).instruct_adr);
- address = (0x8000 + (address&0x1FF));
+ address = 0x8000 + (address & 0x1FF);
}
// as a sanity measure for funny-sized roms (homebrew and perhaps truncated retail roms)
@@ -140,7 +143,7 @@
static uint32_t read32(uint8_t PROCNUM, uint32_t adr)
{
- switch(adr)
+ switch (adr)
{
case REG_GCDATAIN:
return read32_GCDATAIN(PROCNUM);
@@ -165,115 +168,3 @@
info
};
- // ///writetoGCControl:
- //// --- Ninja SD commands -------------------------------------
-
- // // NJSD init/reset
- // case 0x20:
- // {
- // card.address = 0;
- // card.transfer_count = 0;
- // }
- // break;
-
- // // NJSD_sendCLK()
- // case 0xE0:
- // {
- // card.address = 0;
- // card.transfer_count = 0;
- // NDS_makeInt(PROCNUM, 20);
- // }
- // break;
-
- // // NJSD_sendCMDN() / NJSD_sendCMDR()
- // case 0xF0:
- // case 0xF1:
- // switch (card.command[2])
- // {
- // // GO_IDLE_STATE
- // case 0x40:
- // card.address = 0;
- // card.transfer_count = 0;
- // NDS_makeInt(PROCNUM, 20);
- // break;
-
- // case 0x42: // ALL_SEND_CID
- // case 0x43: // SEND_RELATIVE_ADDR
- // case 0x47: // SELECT_CARD
- // case 0x49: // SEND_CSD
- // case 0x4D:
- // case 0x77: // APP_CMD
- // case 0x69: // SD_APP_OP_COND
- // card.address = 0;
- // card.transfer_count = 6;
- // NDS_makeInt(PROCNUM, 20);
- // break;
-
- // // SET_BLOCKLEN
- // case 0x50:
- // card.address = 0;
- // card.transfer_count = 6;
- // card.blocklen = card.command[6] | (card.command[5] << 8) | (card.command[4] << 16) | (card.command[3] << 24);
- // NDS_makeInt(PROCNUM, 20);
- // break;
-
- // // READ_SINGLE_BLOCK
- // case 0x51:
- // card.address = card.command[6] | (card.command[5] << 8) | (card.command[4] << 16) | (card.command[3] << 24);
- // card.transfer_count = (card.blocklen + 3) >> 2;
- // NDS_makeInt(PROCNUM, 20);
- // break;
- // }
- // break;
-
- // // --- Ninja SD commands end ---------------------------------
-
-
-
- // //GCDATAIN:
- // // --- Ninja SD commands -------------------------------------
-
- // // NJSD_sendCMDN() / NJSD_sendCMDR()
- // case 0xF0:
- // case 0xF1:
- // switch (card.command[2])
- // {
- // // ALL_SEND_CID
- // case 0x42:
- // if (card.transfer_count == 2) val = 0x44534A4E;
- // else val = 0x00000000;
-
- // // SEND_RELATIVE_ADDR
- // case 0x43:
- // case 0x47:
- // case 0x49:
- // case 0x50:
- // val = 0x00000000;
- // break;
-
- // case 0x4D:
- // if (card.transfer_count == 2) val = 0x09000000;
- // else val = 0x00000000;
- // break;
-
- // // APP_CMD
- // case 0x77:
- // if (card.transfer_count == 2) val = 0x00000037;
- // else val = 0x00000000;
- // break;
-
- // // SD_APP_OP_COND
- // case 0x69:
- // if (card.transfer_count == 2) val = 0x00008000;
- // else val = 0x00000000;
- // break;
-
- // // READ_SINGLE_BLOCK
- // case 0x51:
- // val = 0x00000000;
- // break;
- // }
- // break;
-
- // // --- Ninja SD commands end ---------------------------------
-
--- a/src/in_2sf/desmume/arm_instructions.cpp
+++ b/src/in_2sf/desmume/arm_instructions.cpp
@@ -25,59 +25,54 @@
// - Check LDMxx2/STMxx2 (those opcodes that act on User mode registers instead
// of current ones)
-//#define UNTESTEDOPCODEDEBUG
#include "cp15.h"
-//#include "debug.h"
#include "MMU.h"
#include "armcpu.h"
#include "NDSSystem.h"
-#include "arm_instructions.h"
#include "MMU_timing.h"
#define cpu (&ARMPROC)
#define TEMPLATE template<int PROCNUM>
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// Shifting macros
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define LSL_IMM \
- uint32_t shift_op = cpu->R[REG_POS(i,0)]<<((i>>7)&0x1F);
+ uint32_t shift_op = cpu->R[REG_POS(i, 0)] << ((i >> 7) & 0x1F);
#define S_LSL_IMM \
- uint32_t shift_op = ((i>>7)&0x1F); \
+ uint32_t shift_op = (i >> 7) & 0x1F; \
uint32_t c = cpu->CPSR.bits.C; \
- if(shift_op==0) \
- shift_op=cpu->R[REG_POS(i,0)]; \
+ if (!shift_op) \
+ shift_op = cpu->R[REG_POS(i, 0)]; \
else \
{ \
- c = BIT_N(cpu->R[REG_POS(i,0)], 32-shift_op); \
- shift_op = cpu->R[REG_POS(i,0)]<<shift_op; \
+ c = BIT_N(cpu->R[REG_POS(i, 0)], 32 - shift_op); \
+ shift_op = cpu->R[REG_POS(i, 0)] << shift_op; \
}
#define LSL_REG \
- uint32_t shift_op = (cpu->R[REG_POS(i,8)])&0xFF; \
- if(shift_op>=32) \
- shift_op=0; \
+ uint32_t shift_op = cpu->R[REG_POS(i, 8)] & 0xFF; \
+ if (shift_op >= 32) \
+ shift_op = 0; \
else \
- shift_op=cpu->R[REG_POS(i,0)]<<shift_op;
+ shift_op = cpu->R[REG_POS(i, 0)] << shift_op;
#define S_LSL_REG \
- uint32_t shift_op = (cpu->R[REG_POS(i,8)])&0xFF; \
+ uint32_t shift_op = cpu->R[REG_POS(i,8)] & 0xFF; \
uint32_t c = cpu->CPSR.bits.C; \
- if(shift_op==0) \
- shift_op=cpu->R[REG_POS(i,0)]; \
- else \
- if(shift_op<32) \
+ if (!shift_op) \
+ shift_op = cpu->R[REG_POS(i, 0)]; \
+ else if (shift_op < 32) \
{ \
- c = BIT_N(cpu->R[REG_POS(i,0)], 32-shift_op); \
- shift_op = cpu->R[REG_POS(i,0)]<<shift_op; \
+ c = BIT_N(cpu->R[REG_POS(i, 0)], 32 - shift_op); \
+ shift_op = cpu->R[REG_POS(i, 0)] << shift_op; \
} \
- else \
- if(shift_op==32) \
+ else if (shift_op == 32) \
{ \
shift_op = 0; \
- c = BIT0(cpu->R[REG_POS(i,0)]); \
+ c = BIT0(cpu->R[REG_POS(i, 0)]); \
} \
else \
{ \
@@ -86,47 +81,41 @@
}
#define LSR_IMM \
- uint32_t shift_op = ((i>>7)&0x1F); \
- if(shift_op!=0) \
- shift_op = cpu->R[REG_POS(i,0)]>>shift_op;
+ uint32_t shift_op = (i >> 7) & 0x1F; \
+ if (shift_op) \
+ shift_op = cpu->R[REG_POS(i, 0)] >> shift_op;
#define S_LSR_IMM \
- uint32_t shift_op = ((i>>7)&0x1F); \
+ uint32_t shift_op = (i >> 7) & 0x1F; \
uint32_t c = cpu->CPSR.bits.C; \
- if(shift_op==0) \
- { \
- c = BIT31(cpu->R[REG_POS(i,0)]); \
- } \
+ if (!shift_op) \
+ c = BIT31(cpu->R[REG_POS(i, 0)]); \
else \
{ \
- c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1); \
- shift_op = cpu->R[REG_POS(i,0)]>>shift_op; \
+ c = BIT_N(cpu->R[REG_POS(i, 0)], shift_op - 1); \
+ shift_op = cpu->R[REG_POS(i, 0)]>>shift_op; \
}
#define LSR_REG \
- uint32_t shift_op = (cpu->R[REG_POS(i,8)])&0xFF; \
- if(shift_op>=32) \
+ uint32_t shift_op = cpu->R[REG_POS(i,8)] & 0xFF; \
+ if (shift_op >= 32) \
shift_op = 0; \
else \
- shift_op = cpu->R[REG_POS(i,0)]>>shift_op;
+ shift_op = cpu->R[REG_POS(i, 0)] >> shift_op;
#define S_LSR_REG \
- uint32_t shift_op = (cpu->R[REG_POS(i,8)])&0xFF; \
+ uint32_t shift_op = cpu->R[REG_POS(i,8)] & 0xFF; \
uint32_t c = cpu->CPSR.bits.C; \
- if(shift_op==0) \
+ if (!shift_op) \
+ shift_op = cpu->R[REG_POS(i ,0)]; \
+ else if (shift_op < 32) \
{ \
- shift_op = cpu->R[REG_POS(i,0)]; \
+ c = BIT_N(cpu->R[REG_POS(i, 0)], shift_op - 1); \
+ shift_op = cpu->R[REG_POS(i, 0)] >> shift_op; \
} \
- else \
- if(shift_op<32) \
+ else if (shift_op == 32) \
{ \
- c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1); \
- shift_op = cpu->R[REG_POS(i,0)]>>shift_op; \
- } \
- else \
- if(shift_op==32) \
- { \
- c = BIT31(cpu->R[REG_POS(i,0)]); \
+ c = BIT31(cpu->R[REG_POS(i, 0)]); \
shift_op = 0; \
} \
else \
@@ -136,134 +125,130 @@
}
#define ASR_IMM \
- uint32_t shift_op = ((i>>7)&0x1F); \
- if(shift_op==0) \
- shift_op=BIT31(cpu->R[REG_POS(i,0)])*0xFFFFFFFF; \
+ uint32_t shift_op = (i >> 7) & 0x1F; \
+ if (!shift_op) \
+ shift_op = BIT31(cpu->R[REG_POS(i, 0)]) * 0xFFFFFFFF; \
else \
- shift_op = (uint32_t)((int32_t)cpu->R[REG_POS(i,0)]>>shift_op);
+ shift_op = static_cast<uint32_t>(static_cast<int32_t>(cpu->R[REG_POS(i, 0)]) >> shift_op);
#define S_ASR_IMM \
- uint32_t shift_op = ((i>>7)&0x1F); \
+ uint32_t shift_op = (i >> 7) & 0x1F; \
uint32_t c = cpu->CPSR.bits.C; \
- if(shift_op==0) \
+ if (!shift_op) \
{ \
- shift_op=BIT31(cpu->R[REG_POS(i,0)])*0xFFFFFFFF; \
- c = BIT31(cpu->R[REG_POS(i,0)]); \
+ shift_op = BIT31(cpu->R[REG_POS(i, 0)]) * 0xFFFFFFFF; \
+ c = BIT31(cpu->R[REG_POS(i, 0)]); \
} \
else \
{ \
- c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1); \
- shift_op = (uint32_t)((int32_t)cpu->R[REG_POS(i,0)]>>shift_op); \
+ c = BIT_N(cpu->R[REG_POS(i, 0)], shift_op - 1); \
+ shift_op = static_cast<uint32_t>(static_cast<int32_t>(cpu->R[REG_POS(i, 0)]) >> shift_op); \
}
#define ASR_REG \
- uint32_t shift_op = (cpu->R[REG_POS(i,8)])&0xFF; \
- if(shift_op==0) \
- shift_op=cpu->R[REG_POS(i,0)]; \
+ uint32_t shift_op = cpu->R[REG_POS(i,8)] & 0xFF; \
+ if (!shift_op) \
+ shift_op = cpu->R[REG_POS(i, 0)]; \
+ else if (shift_op < 32) \
+ shift_op = static_cast<uint32_t>(static_cast<int32_t>(cpu->R[REG_POS(i, 0)]) >> shift_op); \
else \
- if(shift_op<32) \
- shift_op = (uint32_t)((int32_t)cpu->R[REG_POS(i,0)]>>shift_op); \
- else \
- shift_op=BIT31(cpu->R[REG_POS(i,0)])*0xFFFFFFFF;
+ shift_op = BIT31(cpu->R[REG_POS(i, 0)]) * 0xFFFFFFFF;
#define S_ASR_REG \
- uint32_t shift_op = (cpu->R[REG_POS(i,8)])&0xFF; \
+ uint32_t shift_op = cpu->R[REG_POS(i, 8)] & 0xFF; \
uint32_t c = cpu->CPSR.bits.C; \
- if(shift_op==0) \
- shift_op=cpu->R[REG_POS(i,0)]; \
- else \
- if(shift_op<32) \
+ if (!shift_op) \
+ shift_op = cpu->R[REG_POS(i, 0)]; \
+ else if (shift_op < 32) \
{ \
- c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1); \
- shift_op = (uint32_t)((int32_t)cpu->R[REG_POS(i,0)]>>shift_op); \
+ c = BIT_N(cpu->R[REG_POS(i, 0)], shift_op - 1); \
+ shift_op = static_cast<uint32_t>(static_cast<int32_t>(cpu->R[REG_POS(i, 0)]) >> shift_op); \
} \
else \
{ \
- c = BIT31(cpu->R[REG_POS(i,0)]); \
- shift_op=BIT31(cpu->R[REG_POS(i,0)])*0xFFFFFFFF; \
+ c = BIT31(cpu->R[REG_POS(i, 0)]); \
+ shift_op = BIT31(cpu->R[REG_POS(i, 0)]) * 0xFFFFFFFF; \
}
#define ROR_IMM \
- uint32_t shift_op = ((i>>7)&0x1F); \
- if(shift_op==0) \
+ uint32_t shift_op = (i >> 7) & 0x1F; \
+ if (!shift_op) \
+ shift_op = (static_cast<uint32_t>(cpu->CPSR.bits.C) << 31) | (cpu->R[REG_POS(i, 0)] >> 1); \
+ else \
+ shift_op = ROR(cpu->R[REG_POS(i, 0)], shift_op);
+
+#define S_ROR_IMM \
+ uint32_t shift_op = (i >> 7) & 0x1F; \
+ uint32_t c = cpu->CPSR.bits.C; \
+ if (!shift_op) \
{ \
- shift_op = ((uint32_t)cpu->CPSR.bits.C<<31)|(cpu->R[REG_POS(i,0)]>>1); \
- } \
- else \
- shift_op = ROR(cpu->R[REG_POS(i,0)],shift_op);
-
-#define S_ROR_IMM \
- uint32_t shift_op = ((i>>7)&0x1F); \
- uint32_t c = cpu->CPSR.bits.C; \
- if(shift_op==0) \
- { \
- shift_op = ((uint32_t)cpu->CPSR.bits.C<<31)|(cpu->R[REG_POS(i,0)]>>1); \
- c = BIT0(cpu->R[REG_POS(i,0)]); \
+ shift_op = (static_cast<uint32_t>(cpu->CPSR.bits.C) << 31) | (cpu->R[REG_POS(i, 0)] >> 1); \
+ c = BIT0(cpu->R[REG_POS(i, 0)]); \
} \
else \
{ \
- c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1); \
- shift_op = ROR(cpu->R[REG_POS(i,0)],shift_op); \
+ c = BIT_N(cpu->R[REG_POS(i, 0)], shift_op - 1); \
+ shift_op = ROR(cpu->R[REG_POS(i, 0)], shift_op); \
}
#define ROR_REG \
- uint32_t shift_op = (cpu->R[REG_POS(i,8)])&0xFF; \
- if((shift_op==0)||((shift_op&0x1F)==0)) \
- shift_op=cpu->R[REG_POS(i,0)]; \
+ uint32_t shift_op = cpu->R[REG_POS(i, 8)] & 0xFF; \
+ if (!shift_op || !(shift_op & 0x1F)) \
+ shift_op = cpu->R[REG_POS(i, 0)]; \
else \
- shift_op = ROR(cpu->R[REG_POS(i,0)],(shift_op&0x1F));
+ shift_op = ROR(cpu->R[REG_POS(i, 0)], shift_op & 0x1F);
#define S_ROR_REG \
- uint32_t shift_op = (cpu->R[REG_POS(i,8)])&0xFF; \
+ uint32_t shift_op = cpu->R[REG_POS(i, 8)] & 0xFF; \
uint32_t c = cpu->CPSR.bits.C; \
- if(shift_op==0) \
- shift_op=cpu->R[REG_POS(i,0)]; \
+ if (!shift_op) \
+ shift_op = cpu->R[REG_POS(i, 0)]; \
else \
{ \
- shift_op&=0x1F; \
- if(shift_op==0) \
+ shift_op &= 0x1F; \
+ if (!shift_op) \
{ \
- shift_op=cpu->R[REG_POS(i,0)]; \
- c = BIT31(cpu->R[REG_POS(i,0)]); \
+ shift_op = cpu->R[REG_POS(i, 0)]; \
+ c = BIT31(cpu->R[REG_POS(i, 0)]); \
} \
else \
{ \
- c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1); \
- shift_op = ROR(cpu->R[REG_POS(i,0)],shift_op); \
+ c = BIT_N(cpu->R[REG_POS(i, 0)], shift_op - 1); \
+ shift_op = ROR(cpu->R[REG_POS(i, 0)], shift_op); \
} \
}
#define IMM_VALUE \
- uint32_t shift_op = ROR((i&0xFF), (i>>7)&0x1E);
+ uint32_t shift_op = ROR(i & 0xFF, (i >> 7) & 0x1E);
#define S_IMM_VALUE \
- uint32_t shift_op = ROR((i&0xFF), (i>>7)&0x1E); \
+ uint32_t shift_op = ROR(i & 0xFF, (i >> 7) & 0x1E); \
uint32_t c = cpu->CPSR.bits.C; \
- if((i>>8)&0xF) \
+ if ((i >> 8) & 0xF) \
c = BIT31(shift_op);
-#define IMM_OFF (((i>>4)&0xF0)+(i&0xF))
-
-#define IMM_OFF_12 ((i)&0xFFF)
-
-//-----------------------------------------------------------------------------
+#define IMM_OFF (((i >> 4) & 0xF0) + (i & 0xF))
+
+#define IMM_OFF_12 ((i) & 0xFFF)
+
+// -----------------------------------------------------------------------------
// Undefined instruction
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_UND(const uint32_t)
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_UND(uint32_t)
{
TRAPUNDEF(cpu);
return 1;
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// AND / ANDS
// Timing: OK
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define OP_AND(a, b) \
- cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] & shift_op; \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 12)] = cpu->R[REG_POS(i, 16)] & shift_op; \
+ if (REG_POS(i, 12) == 15) \
{ \
cpu->next_instruction = cpu->R[15]; \
return b; \
@@ -271,138 +256,138 @@
return a;
#define OP_ANDS(a, b) \
- cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] & shift_op; \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 12)] = cpu->R[REG_POS(i, 16)] & shift_op; \
+ if (REG_POS(i, 12) == 15) \
{ \
Status_Reg SPSR = cpu->SPSR; \
armcpu_switchMode(cpu, SPSR.bits.mode); \
- cpu->CPSR=SPSR; \
+ cpu->CPSR = SPSR; \
cpu->changeCPSR(); \
- cpu->R[15] &= (0xFFFFFFFC|(((uint32_t)cpu->CPSR.bits.T)<<1)); \
+ cpu->R[15] &= 0xFFFFFFFC | (static_cast<uint32_t>(cpu->CPSR.bits.T) << 1); \
cpu->next_instruction = cpu->R[15]; \
return b; \
} \
cpu->CPSR.bits.C = c; \
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \
- cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i, 12)]); \
+ cpu->CPSR.bits.Z = !cpu->R[REG_POS(i, 12)]; \
return a;
-TEMPLATE static uint32_t FASTCALL OP_AND_LSL_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_AND_LSL_IMM(uint32_t i)
{
LSL_IMM;
OP_AND(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_AND_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_AND_LSL_REG(uint32_t i)
{
LSL_REG;
OP_AND(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_AND_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_AND_LSR_IMM(uint32_t i)
{
LSR_IMM;
OP_AND(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_AND_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_AND_LSR_REG(uint32_t i)
{
LSR_REG;
OP_AND(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_AND_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_AND_ASR_IMM(uint32_t i)
{
ASR_IMM;
OP_AND(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_AND_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_AND_ASR_REG(uint32_t i)
{
ASR_REG;
OP_AND(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_AND_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_AND_ROR_IMM(uint32_t i)
{
ROR_IMM;
OP_AND(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_AND_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_AND_ROR_REG(uint32_t i)
{
ROR_REG;
OP_AND(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_AND_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_AND_IMM_VAL(uint32_t i)
{
IMM_VALUE;
OP_AND(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_AND_S_LSL_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_AND_S_LSL_IMM(uint32_t i)
{
S_LSL_IMM;
OP_ANDS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_AND_S_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_AND_S_LSL_REG(uint32_t i)
{
S_LSL_REG;
OP_ANDS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_AND_S_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_AND_S_LSR_IMM(uint32_t i)
{
S_LSR_IMM;
OP_ANDS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_AND_S_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_AND_S_LSR_REG(uint32_t i)
{
S_LSR_REG;
OP_ANDS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_AND_S_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_AND_S_ASR_IMM(uint32_t i)
{
S_ASR_IMM;
OP_ANDS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_AND_S_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_AND_S_ASR_REG(uint32_t i)
{
S_ASR_REG;
OP_ANDS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_AND_S_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_AND_S_ROR_IMM(uint32_t i)
{
S_ROR_IMM;
OP_ANDS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_AND_S_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_AND_S_ROR_REG(uint32_t i)
{
S_ROR_REG;
OP_ANDS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_AND_S_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_AND_S_IMM_VAL(uint32_t i)
{
S_IMM_VALUE;
OP_ANDS(1, 3);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// EOR / EORS
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define OP_EOR(a, b) \
- cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] ^ shift_op; \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 12)] = cpu->R[REG_POS(i, 16)] ^ shift_op; \
+ if (REG_POS(i, 12) == 15) \
{ \
cpu->next_instruction = cpu->R[15]; \
return b; \
@@ -410,138 +395,138 @@
return a;
#define OP_EORS(a, b) \
- cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] ^ shift_op; \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 12)] = cpu->R[REG_POS(i, 16)] ^ shift_op; \
+ if (REG_POS(i, 12) == 15) \
{ \
Status_Reg SPSR = cpu->SPSR; \
armcpu_switchMode(cpu, SPSR.bits.mode); \
- cpu->CPSR=SPSR; \
+ cpu->CPSR = SPSR; \
cpu->changeCPSR(); \
- cpu->R[15] &= (0xFFFFFFFC|(((uint32_t)cpu->CPSR.bits.T)<<1)); \
+ cpu->R[15] &= 0xFFFFFFFC | (static_cast<uint32_t>(cpu->CPSR.bits.T) << 1); \
cpu->next_instruction = cpu->R[15]; \
return b; \
} \
cpu->CPSR.bits.C = c; \
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \
- cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i, 12)]); \
+ cpu->CPSR.bits.Z = !cpu->R[REG_POS(i, 12)]; \
return a;
-TEMPLATE static uint32_t FASTCALL OP_EOR_LSL_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_EOR_LSL_IMM(uint32_t i)
{
LSL_IMM;
OP_EOR(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_EOR_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_EOR_LSL_REG(uint32_t i)
{
LSL_REG;
OP_EOR(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_EOR_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_EOR_LSR_IMM(uint32_t i)
{
LSR_IMM;
OP_EOR(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_EOR_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_EOR_LSR_REG(uint32_t i)
{
LSR_REG;
OP_EOR(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_EOR_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_EOR_ASR_IMM(uint32_t i)
{
ASR_IMM;
OP_EOR(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_EOR_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_EOR_ASR_REG(uint32_t i)
{
ASR_REG;
OP_EOR(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_EOR_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_EOR_ROR_IMM(uint32_t i)
{
ROR_IMM;
OP_EOR(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_EOR_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_EOR_ROR_REG(uint32_t i)
{
ROR_REG;
OP_EOR(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_EOR_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_EOR_IMM_VAL(uint32_t i)
{
IMM_VALUE;
OP_EOR(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_EOR_S_LSL_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_EOR_S_LSL_IMM(uint32_t i)
{
S_LSL_IMM;
OP_EORS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_EOR_S_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_EOR_S_LSL_REG(uint32_t i)
{
S_LSL_REG;
OP_EORS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_EOR_S_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_EOR_S_LSR_IMM(uint32_t i)
{
S_LSR_IMM;
OP_EORS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_EOR_S_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_EOR_S_LSR_REG(uint32_t i)
{
S_LSR_REG;
OP_EORS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_EOR_S_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_EOR_S_ASR_IMM(uint32_t i)
{
S_ASR_IMM;
OP_EORS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_EOR_S_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_EOR_S_ASR_REG(uint32_t i)
{
S_ASR_REG;
OP_EORS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_EOR_S_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_EOR_S_ROR_IMM(uint32_t i)
{
S_ROR_IMM;
OP_EORS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_EOR_S_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_EOR_S_ROR_REG(uint32_t i)
{
S_ROR_REG;
OP_EORS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_EOR_S_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_EOR_S_IMM_VAL(uint32_t i)
{
S_IMM_VALUE;
OP_EORS(1, 3);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// SUB / SUBS
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define OP_SUB(a, b) \
- cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] - shift_op; \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 12)] = cpu->R[REG_POS(i, 16)] - shift_op; \
+ if (REG_POS(i, 12) == 15) \
{ \
cpu->next_instruction = cpu->R[15]; \
return b; \
@@ -549,148 +534,148 @@
return a;
#define OP_SUBS(a, b) \
- cpu->R[REG_POS(i,12)] = v - shift_op; \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 12)] = v - shift_op; \
+ if (REG_POS(i, 12) == 15) \
{ \
Status_Reg SPSR = cpu->SPSR; \
armcpu_switchMode(cpu, SPSR.bits.mode); \
- cpu->CPSR=SPSR; \
+ cpu->CPSR = SPSR; \
cpu->changeCPSR(); \
- cpu->R[15] &= (0xFFFFFFFC|(((uint32_t)cpu->CPSR.bits.T)<<1)); \
+ cpu->R[15] &= 0xFFFFFFFC | (static_cast<uint32_t>(cpu->CPSR.bits.T) << 1); \
cpu->next_instruction = cpu->R[15]; \
return b; \
} \
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \
- cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i, 12)]); \
+ cpu->CPSR.bits.Z = !cpu->R[REG_POS(i, 12)]; \
cpu->CPSR.bits.C = !BorrowFrom(v, shift_op); \
cpu->CPSR.bits.V = OverflowFromSUB(cpu->R[REG_POS(i,12)], v, shift_op); \
return a;
-TEMPLATE static uint32_t FASTCALL OP_SUB_LSL_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_SUB_LSL_IMM(uint32_t i)
{
LSL_IMM;
OP_SUB(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_SUB_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_SUB_LSL_REG(uint32_t i)
{
LSL_REG;
OP_SUB(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_SUB_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_SUB_LSR_IMM(uint32_t i)
{
LSR_IMM;
OP_SUB(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_SUB_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_SUB_LSR_REG(uint32_t i)
{
LSR_REG;
OP_SUB(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_SUB_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_SUB_ASR_IMM(uint32_t i)
{
ASR_IMM;
OP_SUB(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_SUB_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_SUB_ASR_REG(uint32_t i)
{
ASR_REG;
OP_SUB(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_SUB_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_SUB_ROR_IMM(uint32_t i)
{
ROR_IMM;
OP_SUB(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_SUB_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_SUB_ROR_REG(uint32_t i)
{
ROR_REG;
OP_SUB(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_SUB_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_SUB_IMM_VAL(uint32_t i)
{
IMM_VALUE;
OP_SUB(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_SUB_S_LSL_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_SUB_S_LSL_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSL_IMM;
OP_SUBS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_SUB_S_LSL_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_SUB_S_LSL_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSL_REG;
OP_SUBS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_SUB_S_LSR_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_SUB_S_LSR_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSR_IMM;
OP_SUBS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_SUB_S_LSR_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_SUB_S_LSR_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSR_REG;
OP_SUBS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_SUB_S_ASR_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_SUB_S_ASR_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ASR_IMM;
OP_SUBS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_SUB_S_ASR_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_SUB_S_ASR_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ASR_REG;
OP_SUBS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_SUB_S_ROR_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_SUB_S_ROR_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ROR_IMM;
OP_SUBS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_SUB_S_ROR_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_SUB_S_ROR_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ROR_REG;
OP_SUBS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_SUB_S_IMM_VAL(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_SUB_S_IMM_VAL(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
IMM_VALUE;
OP_SUBS(1, 3);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// RSB / RSBS
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define OP_RSB(a, b) \
- cpu->R[REG_POS(i,12)] = shift_op - cpu->R[REG_POS(i,16)]; \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 12)] = shift_op - cpu->R[REG_POS(i, 16)]; \
+ if (REG_POS(i, 12) == 15) \
{ \
cpu->next_instruction = cpu->R[15]; \
return b; \
@@ -698,148 +683,147 @@
return a;
#define OP_RSBS(a, b) \
- cpu->R[REG_POS(i,12)] = shift_op - v; \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 12)] = shift_op - v; \
+ if (REG_POS(i, 12) == 15) \
{ \
Status_Reg SPSR = cpu->SPSR; \
armcpu_switchMode(cpu, SPSR.bits.mode); \
- cpu->CPSR=SPSR; \
+ cpu->CPSR = SPSR; \
cpu->changeCPSR(); \
- cpu->R[15] &= (0xFFFFFFFC|(((uint32_t)cpu->CPSR.bits.T)<<1)); \
+ cpu->R[15] &= 0xFFFFFFFC | (static_cast<uint32_t>(cpu->CPSR.bits.T) << 1); \
cpu->next_instruction = cpu->R[15]; \
return b; \
} \
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \
- cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i, 12)]); \
+ cpu->CPSR.bits.Z = !cpu->R[REG_POS(i, 12)]; \
cpu->CPSR.bits.C = !BorrowFrom(shift_op, v); \
- cpu->CPSR.bits.V = OverflowFromSUB(cpu->R[REG_POS(i,12)], shift_op, v); \
+ cpu->CPSR.bits.V = OverflowFromSUB(cpu->R[REG_POS(i, 12)], shift_op, v); \
return a;
-TEMPLATE static uint32_t FASTCALL OP_RSB_LSL_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_RSB_LSL_IMM(uint32_t i)
{
LSL_IMM;
OP_RSB(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_RSB_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_RSB_LSL_REG(uint32_t i)
{
LSL_REG;
OP_RSB(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_RSB_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_RSB_LSR_IMM(uint32_t i)
{
LSR_IMM;
OP_RSB(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_RSB_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_RSB_LSR_REG(uint32_t i)
{
LSR_REG;
OP_RSB(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_RSB_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_RSB_ASR_IMM(uint32_t i)
{
ASR_IMM;
OP_RSB(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_RSB_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_RSB_ASR_REG(uint32_t i)
{
ASR_REG;
OP_RSB(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_RSB_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_RSB_ROR_IMM(uint32_t i)
{
ROR_IMM;
OP_RSB(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_RSB_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_RSB_ROR_REG(uint32_t i)
{
ROR_REG;
OP_RSB(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_RSB_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_RSB_IMM_VAL(uint32_t i)
{
IMM_VALUE;
OP_RSB(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_RSB_S_LSL_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_RSB_S_LSL_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSL_IMM;
OP_RSBS(1, 3);
}
-
-TEMPLATE static uint32_t FASTCALL OP_RSB_S_LSL_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_RSB_S_LSL_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSL_REG;
OP_RSBS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_RSB_S_LSR_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_RSB_S_LSR_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSR_IMM;
OP_RSBS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_RSB_S_LSR_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_RSB_S_LSR_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSR_REG;
OP_RSBS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_RSB_S_ASR_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_RSB_S_ASR_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ASR_IMM;
OP_RSBS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_RSB_S_ASR_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_RSB_S_ASR_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ASR_REG;
OP_RSBS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_RSB_S_ROR_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_RSB_S_ROR_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ROR_IMM;
OP_RSBS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_RSB_S_ROR_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_RSB_S_ROR_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ROR_REG;
OP_RSBS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_RSB_S_IMM_VAL(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_RSB_S_IMM_VAL(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
IMM_VALUE;
OP_RSBS(1, 3);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// ADD / ADDS
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define OP_ADD(a, b) \
- cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] + shift_op; \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 12)] = cpu->R[REG_POS(i, 16)] + shift_op; \
+ if (REG_POS(i, 12) == 15) \
{ \
cpu->next_instruction = cpu->R[15]; \
return b; \
@@ -848,146 +832,145 @@
#define OP_ADDS(a, b) \
cpu->R[REG_POS(i,12)] = v + shift_op; \
- if(REG_POS(i,12)==15) \
+ if (REG_POS(i, 12) == 15) \
{ \
Status_Reg SPSR = cpu->SPSR; \
armcpu_switchMode(cpu, SPSR.bits.mode); \
- cpu->CPSR=SPSR; \
+ cpu->CPSR = SPSR; \
cpu->changeCPSR(); \
- cpu->R[15] &= (0xFFFFFFFC|(((uint32_t)cpu->CPSR.bits.T)<<1)); \
+ cpu->R[15] &= 0xFFFFFFFC | (static_cast<uint32_t>(cpu->CPSR.bits.T) << 1); \
cpu->next_instruction = cpu->R[15]; \
return b; \
} \
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \
- cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i, 12)]); \
+ cpu->CPSR.bits.Z = !cpu->R[REG_POS(i, 12)]; \
cpu->CPSR.bits.C = CarryFrom(v, shift_op); \
- cpu->CPSR.bits.V = OverflowFromADD(cpu->R[REG_POS(i,12)], v, shift_op); \
+ cpu->CPSR.bits.V = OverflowFromADD(cpu->R[REG_POS(i, 12)], v, shift_op); \
return a;
-TEMPLATE static uint32_t FASTCALL OP_ADD_LSL_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADD_LSL_IMM(uint32_t i)
{
LSL_IMM;
OP_ADD(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ADD_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADD_LSL_REG(uint32_t i)
{
LSL_REG;
OP_ADD(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_ADD_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADD_LSR_IMM(uint32_t i)
{
LSR_IMM;
OP_ADD(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ADD_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADD_LSR_REG(uint32_t i)
{
LSR_REG;
OP_ADD(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_ADD_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADD_ASR_IMM(uint32_t i)
{
ASR_IMM;
OP_ADD(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ADD_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADD_ASR_REG(uint32_t i)
{
ASR_REG;
OP_ADD(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_ADD_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADD_ROR_IMM(uint32_t i)
{
ROR_IMM;
OP_ADD(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ADD_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADD_ROR_REG(uint32_t i)
{
ROR_REG;
OP_ADD(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_ADD_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADD_IMM_VAL(uint32_t i)
{
IMM_VALUE;
OP_ADD(1, 3);
}
-
-TEMPLATE static uint32_t FASTCALL OP_ADD_S_LSL_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_ADD_S_LSL_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSL_IMM;
OP_ADDS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ADD_S_LSL_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_ADD_S_LSL_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSL_REG;
OP_ADDS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_ADD_S_LSR_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_ADD_S_LSR_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSR_IMM;
OP_ADDS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ADD_S_LSR_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_ADD_S_LSR_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSR_REG;
OP_ADDS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_ADD_S_ASR_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_ADD_S_ASR_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ASR_IMM;
OP_ADDS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ADD_S_ASR_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_ADD_S_ASR_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ASR_REG;
OP_ADDS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_ADD_S_ROR_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_ADD_S_ROR_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ROR_IMM;
OP_ADDS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ADD_S_ROR_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_ADD_S_ROR_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ROR_REG;
OP_ADDS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_ADD_S_IMM_VAL(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_ADD_S_IMM_VAL(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
IMM_VALUE;
OP_ADDS(1, 3);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// ADC / ADCS
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define OP_ADC(a, b) \
- cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] + shift_op + cpu->CPSR.bits.C; \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 12)] = cpu->R[REG_POS(i, 16)] + shift_op + cpu->CPSR.bits.C; \
+ if (REG_POS(i, 12) == 15) \
{ \
cpu->next_instruction = cpu->R[15]; \
return b; \
@@ -995,159 +978,159 @@
return a;
#define OP_ADCS(a, b) \
+{ \
+ if (REG_POS(i, 12) == 15) \
{ \
- if(REG_POS(i,12)==15) \
- { \
- cpu->R[REG_POS(i,12)] = v + shift_op + cpu->CPSR.bits.C; \
+ cpu->R[REG_POS(i, 12)] = v + shift_op + cpu->CPSR.bits.C; \
Status_Reg SPSR = cpu->SPSR; \
armcpu_switchMode(cpu, SPSR.bits.mode); \
- cpu->CPSR=SPSR; \
+ cpu->CPSR = SPSR; \
cpu->changeCPSR(); \
- cpu->R[15] &= (0xFFFFFFFC|(((uint32_t)cpu->CPSR.bits.T)<<1)); \
+ cpu->R[15] &= 0xFFFFFFFC | (static_cast<uint32_t>(cpu->CPSR.bits.T) << 1); \
cpu->next_instruction = cpu->R[15]; \
return b; \
} \
if (!cpu->CPSR.bits.C) \
{ \
- cpu->R[REG_POS(i,12)] = v + shift_op; \
- cpu->CPSR.bits.C = cpu->R[REG_POS(i,12)] < v; \
+ cpu->R[REG_POS(i, 12)] = v + shift_op; \
+ cpu->CPSR.bits.C = cpu->R[REG_POS(i, 12)] < v; \
} \
else \
{ \
- cpu->R[REG_POS(i,12)] = v + shift_op + 1; \
- cpu->CPSR.bits.C = cpu->R[REG_POS(i,12)] <= v; \
+ cpu->R[REG_POS(i, 12)] = v + shift_op + 1; \
+ cpu->CPSR.bits.C = cpu->R[REG_POS(i, 12)] <= v; \
} \
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \
- cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \
- cpu->CPSR.bits.V = BIT31((v ^ shift_op ^ -1) & (v ^ cpu->R[REG_POS(i, 12)]));\
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i, 12)]); \
+ cpu->CPSR.bits.Z = !cpu->R[REG_POS(i, 12)]; \
+ cpu->CPSR.bits.V = BIT31((v ^ shift_op ^ -1) & (v ^ cpu->R[REG_POS(i, 12)])); \
return a; \
- }
-
-TEMPLATE static uint32_t FASTCALL OP_ADC_LSL_IMM(const uint32_t i)
+}
+
+TEMPLATE static uint32_t FASTCALL OP_ADC_LSL_IMM(uint32_t i)
{
LSL_IMM;
OP_ADC(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ADC_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADC_LSL_REG(uint32_t i)
{
LSL_REG;
OP_ADC(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_ADC_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADC_LSR_IMM(uint32_t i)
{
LSR_IMM;
OP_ADC(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ADC_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADC_LSR_REG(uint32_t i)
{
LSR_REG;
OP_ADC(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_ADC_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADC_ASR_IMM(uint32_t i)
{
ASR_IMM;
OP_ADC(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ADC_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADC_ASR_REG(uint32_t i)
{
ASR_REG;
OP_ADC(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_ADC_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADC_ROR_IMM(uint32_t i)
{
ROR_IMM;
OP_ADC(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ADC_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADC_ROR_REG(uint32_t i)
{
ROR_REG;
OP_ADC(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_ADC_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADC_IMM_VAL(uint32_t i)
{
IMM_VALUE;
OP_ADC(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ADC_S_LSL_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_ADC_S_LSL_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSL_IMM;
OP_ADCS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ADC_S_LSL_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_ADC_S_LSL_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSL_REG;
OP_ADCS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_ADC_S_LSR_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_ADC_S_LSR_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSR_IMM;
OP_ADCS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ADC_S_LSR_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_ADC_S_LSR_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSR_REG;
OP_ADCS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_ADC_S_ASR_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_ADC_S_ASR_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ASR_IMM;
OP_ADCS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ADC_S_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADC_S_ASR_REG(uint32_t i)
{
uint32_t v = cpu->R[REG_POS(i,16)];
ASR_REG;
OP_ADCS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_ADC_S_ROR_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_ADC_S_ROR_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ROR_IMM;
OP_ADCS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ADC_S_ROR_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_ADC_S_ROR_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ROR_REG;
OP_ADCS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_ADC_S_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADC_S_IMM_VAL(uint32_t i)
{
uint32_t v = cpu->R[REG_POS(i,16)];
IMM_VALUE;
OP_ADCS(1, 3);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// SBC / SBCS
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define OP_SBC(a, b) \
- cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] - shift_op - !cpu->CPSR.bits.C; \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 12)] = cpu->R[REG_POS(i, 16)] - shift_op - !cpu->CPSR.bits.C; \
+ if (REG_POS(i, 12) == 15) \
{ \
cpu->next_instruction = cpu->R[15]; \
return b; \
@@ -1155,159 +1138,159 @@
return a;
#define OP_SBCS(a, b) \
- { \
- if(REG_POS(i,12)==15) \
+{ \
+ if (REG_POS(i, 12) == 15) \
{ \
cpu->R[REG_POS(i,12)] = v - shift_op - !cpu->CPSR.bits.C; \
Status_Reg SPSR = cpu->SPSR; \
armcpu_switchMode(cpu, SPSR.bits.mode); \
- cpu->CPSR=SPSR; \
+ cpu->CPSR = SPSR; \
cpu->changeCPSR(); \
- cpu->R[15] &= (0xFFFFFFFC|(((uint32_t)cpu->CPSR.bits.T)<<1)); \
+ cpu->R[15] &= 0xFFFFFFFC | (static_cast<uint32_t>(cpu->CPSR.bits.T) << 1); \
cpu->next_instruction = cpu->R[15]; \
return b; \
} \
if (!cpu->CPSR.bits.C) \
{ \
- cpu->R[REG_POS(i,12)] = v - shift_op - 1; \
+ cpu->R[REG_POS(i, 12)] = v - shift_op - 1; \
cpu->CPSR.bits.C = v > shift_op; \
} \
else \
{ \
- cpu->R[REG_POS(i,12)] = v - shift_op; \
+ cpu->R[REG_POS(i, 12)] = v - shift_op; \
cpu->CPSR.bits.C = v >= shift_op; \
} \
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \
- cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i, 12)]); \
+ cpu->CPSR.bits.Z = !cpu->R[REG_POS(i, 12)]; \
cpu->CPSR.bits.V = BIT31((v ^ shift_op) & (v ^ cpu->R[REG_POS(i, 12)])); \
return a; \
- }
-
-TEMPLATE static uint32_t FASTCALL OP_SBC_LSL_IMM(const uint32_t i)
+}
+
+TEMPLATE static uint32_t FASTCALL OP_SBC_LSL_IMM(uint32_t i)
{
LSL_IMM;
OP_SBC(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_SBC_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_SBC_LSL_REG(uint32_t i)
{
LSL_REG;
OP_SBC(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_SBC_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_SBC_LSR_IMM(uint32_t i)
{
LSR_IMM;
OP_SBC(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_SBC_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_SBC_LSR_REG(uint32_t i)
{
LSR_REG;
OP_SBC(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_SBC_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_SBC_ASR_IMM(uint32_t i)
{
ASR_IMM;
OP_SBC(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_SBC_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_SBC_ASR_REG(uint32_t i)
{
ASR_REG;
OP_SBC(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_SBC_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_SBC_ROR_IMM(uint32_t i)
{
ROR_IMM;
OP_SBC(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_SBC_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_SBC_ROR_REG(uint32_t i)
{
ROR_REG;
OP_SBC(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_SBC_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_SBC_IMM_VAL(uint32_t i)
{
IMM_VALUE;
OP_SBC(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_SBC_S_LSL_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_SBC_S_LSL_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSL_IMM;
OP_SBCS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_SBC_S_LSL_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_SBC_S_LSL_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSL_REG;
OP_SBCS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_SBC_S_LSR_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_SBC_S_LSR_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSR_IMM;
OP_SBCS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_SBC_S_LSR_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_SBC_S_LSR_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSR_REG;
OP_SBCS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_SBC_S_ASR_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_SBC_S_ASR_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ASR_IMM;
OP_SBCS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_SBC_S_ASR_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_SBC_S_ASR_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ASR_REG;
OP_SBCS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_SBC_S_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_SBC_S_ROR_IMM(uint32_t i)
{
uint32_t v = cpu->R[REG_POS(i,16)];
ROR_IMM;
OP_SBCS(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_SBC_S_ROR_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_SBC_S_ROR_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ROR_REG;
OP_SBCS(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_SBC_S_IMM_VAL(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_SBC_S_IMM_VAL(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
IMM_VALUE;
OP_SBCS(1, 3);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// RSC / RSCS
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define OP_RSC(a, b) \
- cpu->R[REG_POS(i,12)] = shift_op - cpu->R[REG_POS(i,16)] + cpu->CPSR.bits.C - 1; \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 12)] = shift_op - cpu->R[REG_POS(i, 16)] + cpu->CPSR.bits.C - 1; \
+ if (REG_POS(i, 12) == 15) \
{ \
cpu->next_instruction = cpu->R[15]; \
return b; \
@@ -1315,429 +1298,428 @@
return a;
#define OP_RSCS(a, b) \
+{ \
+ if (REG_POS(i, 12) == 15) \
{ \
- if(REG_POS(i,12)==15) \
- { \
- cpu->R[REG_POS(i,12)] = shift_op - v - !cpu->CPSR.bits.C; \
+ cpu->R[REG_POS(i, 12)] = shift_op - v - !cpu->CPSR.bits.C; \
Status_Reg SPSR = cpu->SPSR; \
armcpu_switchMode(cpu, SPSR.bits.mode); \
- cpu->CPSR=SPSR; \
+ cpu->CPSR = SPSR; \
cpu->changeCPSR(); \
- cpu->R[15] &= (0xFFFFFFFC|(((uint32_t)cpu->CPSR.bits.T)<<1)); \
+ cpu->R[15] &= 0xFFFFFFFC | (static_cast<uint32_t>(cpu->CPSR.bits.T) << 1); \
cpu->next_instruction = cpu->R[15]; \
return b; \
} \
if (!cpu->CPSR.bits.C) \
{ \
- cpu->R[REG_POS(i,12)] = shift_op - v - 1; \
+ cpu->R[REG_POS(i, 12)] = shift_op - v - 1; \
cpu->CPSR.bits.C = shift_op > v; \
} \
else \
{ \
- cpu->R[REG_POS(i,12)] = shift_op - v; \
+ cpu->R[REG_POS(i, 12)] = shift_op - v; \
cpu->CPSR.bits.C = shift_op >= v; \
} \
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \
- cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i, 12)]); \
+ cpu->CPSR.bits.Z = !cpu->R[REG_POS(i, 12)]; \
cpu->CPSR.bits.V = BIT31((shift_op ^ v) & (shift_op ^ cpu->R[REG_POS(i, 12)])); \
return a; \
- }
-
-TEMPLATE static uint32_t FASTCALL OP_RSC_LSL_IMM(const uint32_t i)
+}
+
+TEMPLATE static uint32_t FASTCALL OP_RSC_LSL_IMM(uint32_t i)
{
LSL_IMM;
OP_RSC(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_RSC_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_RSC_LSL_REG(uint32_t i)
{
LSL_REG;
OP_RSC(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_RSC_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_RSC_LSR_IMM(uint32_t i)
{
LSR_IMM;
OP_RSC(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_RSC_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_RSC_LSR_REG(uint32_t i)
{
LSR_REG;
OP_RSC(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_RSC_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_RSC_ASR_IMM(uint32_t i)
{
ASR_IMM;
OP_RSC(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_RSC_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_RSC_ASR_REG(uint32_t i)
{
ASR_REG;
OP_RSC(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_RSC_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_RSC_ROR_IMM(uint32_t i)
{
ROR_IMM;
OP_RSC(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_RSC_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_RSC_ROR_REG(uint32_t i)
{
ROR_REG;
OP_RSC(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_RSC_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_RSC_IMM_VAL(uint32_t i)
{
IMM_VALUE;
OP_RSC(1, 3);
}
-
-TEMPLATE static uint32_t FASTCALL OP_RSC_S_LSL_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_RSC_S_LSL_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSL_IMM;
OP_RSCS(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_RSC_S_LSL_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_RSC_S_LSL_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSL_REG;
OP_RSCS(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_RSC_S_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_RSC_S_LSR_IMM(uint32_t i)
{
uint32_t v = cpu->R[REG_POS(i,16)];
LSR_IMM;
OP_RSCS(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_RSC_S_LSR_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_RSC_S_LSR_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
LSR_REG;
OP_RSCS(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_RSC_S_ASR_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_RSC_S_ASR_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ASR_IMM;
OP_RSCS(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_RSC_S_ASR_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_RSC_S_ASR_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ASR_REG;
OP_RSCS(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_RSC_S_ROR_IMM(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_RSC_S_ROR_IMM(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ROR_IMM;
OP_RSCS(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_RSC_S_ROR_REG(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_RSC_S_ROR_REG(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
ROR_REG;
OP_RSCS(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_RSC_S_IMM_VAL(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_RSC_S_IMM_VAL(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 16)];
IMM_VALUE;
OP_RSCS(1,3);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// TST
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define OP_TST(a) \
- { \
- uint32_t tmp = cpu->R[REG_POS(i,16)] & shift_op; \
+{ \
+ uint32_t tmp = cpu->R[REG_POS(i, 16)] & shift_op; \
cpu->CPSR.bits.C = c; \
cpu->CPSR.bits.N = BIT31(tmp); \
- cpu->CPSR.bits.Z = (tmp==0); \
+ cpu->CPSR.bits.Z = !tmp; \
return a; \
- }
-
-TEMPLATE static uint32_t FASTCALL OP_TST_LSL_IMM(const uint32_t i)
+}
+
+TEMPLATE static uint32_t FASTCALL OP_TST_LSL_IMM(uint32_t i)
{
S_LSL_IMM;
OP_TST(1);
}
-TEMPLATE static uint32_t FASTCALL OP_TST_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_TST_LSL_REG(uint32_t i)
{
S_LSL_REG;
OP_TST(2);
}
-TEMPLATE static uint32_t FASTCALL OP_TST_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_TST_LSR_IMM(uint32_t i)
{
S_LSR_IMM;
OP_TST(1);
}
-TEMPLATE static uint32_t FASTCALL OP_TST_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_TST_LSR_REG(uint32_t i)
{
S_LSR_REG;
OP_TST(2);
}
-TEMPLATE static uint32_t FASTCALL OP_TST_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_TST_ASR_IMM(uint32_t i)
{
S_ASR_IMM;
OP_TST(1);
}
-TEMPLATE static uint32_t FASTCALL OP_TST_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_TST_ASR_REG(uint32_t i)
{
S_ASR_REG;
OP_TST(2);
}
-TEMPLATE static uint32_t FASTCALL OP_TST_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_TST_ROR_IMM(uint32_t i)
{
S_ROR_IMM;
OP_TST(1);
}
-TEMPLATE static uint32_t FASTCALL OP_TST_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_TST_ROR_REG(uint32_t i)
{
S_ROR_REG;
OP_TST(2);
}
-TEMPLATE static uint32_t FASTCALL OP_TST_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_TST_IMM_VAL(uint32_t i)
{
S_IMM_VALUE;
OP_TST(1);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// TEQ
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define OP_TEQ(a) \
- { \
- unsigned tmp = cpu->R[REG_POS(i,16)] ^ shift_op; \
+{ \
+ unsigned tmp = cpu->R[REG_POS(i, 16)] ^ shift_op; \
cpu->CPSR.bits.C = c; \
cpu->CPSR.bits.N = BIT31(tmp); \
- cpu->CPSR.bits.Z = (tmp==0); \
+ cpu->CPSR.bits.Z = !tmp; \
return a; \
- }
-
-TEMPLATE static uint32_t FASTCALL OP_TEQ_LSL_IMM(const uint32_t i)
+}
+
+TEMPLATE static uint32_t FASTCALL OP_TEQ_LSL_IMM(uint32_t i)
{
S_LSL_IMM;
OP_TEQ(1);
}
-TEMPLATE static uint32_t FASTCALL OP_TEQ_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_TEQ_LSL_REG(uint32_t i)
{
S_LSL_REG;
OP_TEQ(2);
}
-TEMPLATE static uint32_t FASTCALL OP_TEQ_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_TEQ_LSR_IMM(uint32_t i)
{
S_LSR_IMM;
OP_TEQ(1);
}
-TEMPLATE static uint32_t FASTCALL OP_TEQ_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_TEQ_LSR_REG(uint32_t i)
{
S_LSR_REG;
OP_TEQ(2);
}
-TEMPLATE static uint32_t FASTCALL OP_TEQ_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_TEQ_ASR_IMM(uint32_t i)
{
S_ASR_IMM;
OP_TEQ(1);
}
-TEMPLATE static uint32_t FASTCALL OP_TEQ_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_TEQ_ASR_REG(uint32_t i)
{
S_ASR_REG;
OP_TEQ(2);
}
-TEMPLATE static uint32_t FASTCALL OP_TEQ_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_TEQ_ROR_IMM(uint32_t i)
{
S_ROR_IMM;
OP_TEQ(1);
}
-TEMPLATE static uint32_t FASTCALL OP_TEQ_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_TEQ_ROR_REG(uint32_t i)
{
S_ROR_REG;
OP_TEQ(2);
}
-TEMPLATE static uint32_t FASTCALL OP_TEQ_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_TEQ_IMM_VAL(uint32_t i)
{
S_IMM_VALUE;
OP_TEQ(1);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// CMP
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define OP_CMP(a) \
- { \
- uint32_t tmp = cpu->R[REG_POS(i,16)] - shift_op; \
+{ \
+ uint32_t tmp = cpu->R[REG_POS(i, 16)] - shift_op; \
cpu->CPSR.bits.N = BIT31(tmp); \
- cpu->CPSR.bits.Z = (tmp==0); \
- cpu->CPSR.bits.C = !BorrowFrom(cpu->R[REG_POS(i,16)], shift_op); \
- cpu->CPSR.bits.V = OverflowFromSUB(tmp, cpu->R[REG_POS(i,16)], shift_op); \
+ cpu->CPSR.bits.Z = !tmp; \
+ cpu->CPSR.bits.C = !BorrowFrom(cpu->R[REG_POS(i, 16)], shift_op); \
+ cpu->CPSR.bits.V = OverflowFromSUB(tmp, cpu->R[REG_POS(i, 16)], shift_op); \
return a; \
- }
-
-TEMPLATE static uint32_t FASTCALL OP_CMP_LSL_IMM(const uint32_t i)
+}
+
+TEMPLATE static uint32_t FASTCALL OP_CMP_LSL_IMM(uint32_t i)
{
LSL_IMM;
OP_CMP(1);
}
-TEMPLATE static uint32_t FASTCALL OP_CMP_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_CMP_LSL_REG(uint32_t i)
{
LSL_REG;
OP_CMP(2);
}
-TEMPLATE static uint32_t FASTCALL OP_CMP_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_CMP_LSR_IMM(uint32_t i)
{
LSR_IMM;
OP_CMP(1);
}
-TEMPLATE static uint32_t FASTCALL OP_CMP_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_CMP_LSR_REG(uint32_t i)
{
LSR_REG;
OP_CMP(2);
}
-TEMPLATE static uint32_t FASTCALL OP_CMP_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_CMP_ASR_IMM(uint32_t i)
{
ASR_IMM;
OP_CMP(1);
}
-TEMPLATE static uint32_t FASTCALL OP_CMP_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_CMP_ASR_REG(uint32_t i)
{
ASR_REG;
OP_CMP(2);
}
-TEMPLATE static uint32_t FASTCALL OP_CMP_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_CMP_ROR_IMM(uint32_t i)
{
ROR_IMM;
OP_CMP(1);
}
-TEMPLATE static uint32_t FASTCALL OP_CMP_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_CMP_ROR_REG(uint32_t i)
{
ROR_REG;
OP_CMP(2);
}
-TEMPLATE static uint32_t FASTCALL OP_CMP_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_CMP_IMM_VAL(uint32_t i)
{
IMM_VALUE;
OP_CMP(1);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// CMN
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define OP_CMN(a) \
- { \
- uint32_t tmp = cpu->R[REG_POS(i,16)] + shift_op; \
+{ \
+ uint32_t tmp = cpu->R[REG_POS(i, 16)] + shift_op; \
cpu->CPSR.bits.N = BIT31(tmp); \
- cpu->CPSR.bits.Z = (tmp==0); \
- cpu->CPSR.bits.C = CarryFrom(cpu->R[REG_POS(i,16)], shift_op); \
- cpu->CPSR.bits.V = OverflowFromADD(tmp, cpu->R[REG_POS(i,16)], shift_op); \
+ cpu->CPSR.bits.Z = !tmp; \
+ cpu->CPSR.bits.C = CarryFrom(cpu->R[REG_POS(i, 16)], shift_op); \
+ cpu->CPSR.bits.V = OverflowFromADD(tmp, cpu->R[REG_POS(i, 16)], shift_op); \
return a; \
- }
-
-TEMPLATE static uint32_t FASTCALL OP_CMN_LSL_IMM(const uint32_t i)
+}
+
+TEMPLATE static uint32_t FASTCALL OP_CMN_LSL_IMM(uint32_t i)
{
LSL_IMM;
OP_CMN(1);
}
-TEMPLATE static uint32_t FASTCALL OP_CMN_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_CMN_LSL_REG(uint32_t i)
{
LSL_REG;
OP_CMN(2);
}
-TEMPLATE static uint32_t FASTCALL OP_CMN_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_CMN_LSR_IMM(uint32_t i)
{
LSR_IMM;
OP_CMN(1);
}
-TEMPLATE static uint32_t FASTCALL OP_CMN_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_CMN_LSR_REG(uint32_t i)
{
LSR_REG;
OP_CMN(2);
}
-TEMPLATE static uint32_t FASTCALL OP_CMN_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_CMN_ASR_IMM(uint32_t i)
{
ASR_IMM;
OP_CMN(1);
}
-TEMPLATE static uint32_t FASTCALL OP_CMN_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_CMN_ASR_REG(uint32_t i)
{
ASR_REG;
OP_CMN(2);
}
-TEMPLATE static uint32_t FASTCALL OP_CMN_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_CMN_ROR_IMM(uint32_t i)
{
ROR_IMM;
OP_CMN(1);
}
-TEMPLATE static uint32_t FASTCALL OP_CMN_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_CMN_ROR_REG(uint32_t i)
{
ROR_REG;
OP_CMN(2);
}
-TEMPLATE static uint32_t FASTCALL OP_CMN_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_CMN_IMM_VAL(uint32_t i)
{
IMM_VALUE;
OP_CMN(1);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// ORR / ORRS
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define OP_ORR(a, b) \
- cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] | shift_op; \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 12)] = cpu->R[REG_POS(i, 16)] | shift_op; \
+ if (REG_POS(i, 12) == 15) \
{ \
cpu->next_instruction = cpu->R[15]; \
return b; \
@@ -1745,140 +1727,140 @@
return a;
#define OP_ORRS(a,b) \
- { \
- cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] | shift_op; \
- if(REG_POS(i,12)==15) \
+{ \
+ cpu->R[REG_POS(i, 12)] = cpu->R[REG_POS(i, 16)] | shift_op; \
+ if (REG_POS(i, 12) == 15) \
{ \
Status_Reg SPSR = cpu->SPSR; \
armcpu_switchMode(cpu, SPSR.bits.mode); \
- cpu->CPSR=SPSR; \
+ cpu->CPSR = SPSR; \
cpu->changeCPSR(); \
- cpu->R[15] &= (0xFFFFFFFC|(((uint32_t)cpu->CPSR.bits.T)<<1)); \
+ cpu->R[15] &= 0xFFFFFFFC | (static_cast<uint32_t>(cpu->CPSR.bits.T) << 1); \
cpu->next_instruction = cpu->R[15]; \
return b; \
} \
cpu->CPSR.bits.C = c; \
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \
- cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i, 12)]); \
+ cpu->CPSR.bits.Z = !cpu->R[REG_POS(i, 12)]; \
return a; \
- }
-
-TEMPLATE static uint32_t FASTCALL OP_ORR_LSL_IMM(const uint32_t i)
+}
+
+TEMPLATE static uint32_t FASTCALL OP_ORR_LSL_IMM(uint32_t i)
{
LSL_IMM;
OP_ORR(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ORR_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ORR_LSL_REG(uint32_t i)
{
LSL_REG;
OP_ORR(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_ORR_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ORR_LSR_IMM(uint32_t i)
{
LSR_IMM;
OP_ORR(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ORR_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ORR_LSR_REG(uint32_t i)
{
LSR_REG;
OP_ORR(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_ORR_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ORR_ASR_IMM(uint32_t i)
{
ASR_IMM;
OP_ORR(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ORR_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ORR_ASR_REG(uint32_t i)
{
ASR_REG;
OP_ORR(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_ORR_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ORR_ROR_IMM(uint32_t i)
{
ROR_IMM;
OP_ORR(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ORR_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ORR_ROR_REG(uint32_t i)
{
ROR_REG;
OP_ORR(2, 4);
}
-TEMPLATE static uint32_t FASTCALL OP_ORR_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ORR_IMM_VAL(uint32_t i)
{
IMM_VALUE;
OP_ORR(1, 3);
}
-TEMPLATE static uint32_t FASTCALL OP_ORR_S_LSL_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ORR_S_LSL_IMM(uint32_t i)
{
S_LSL_IMM;
OP_ORRS(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_ORR_S_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ORR_S_LSL_REG(uint32_t i)
{
S_LSL_REG;
OP_ORRS(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_ORR_S_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ORR_S_LSR_IMM(uint32_t i)
{
S_LSR_IMM;
OP_ORRS(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_ORR_S_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ORR_S_LSR_REG(uint32_t i)
{
S_LSR_REG;
OP_ORRS(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_ORR_S_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ORR_S_ASR_IMM(uint32_t i)
{
S_ASR_IMM;
OP_ORRS(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_ORR_S_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ORR_S_ASR_REG(uint32_t i)
{
S_ASR_REG;
OP_ORRS(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_ORR_S_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ORR_S_ROR_IMM(uint32_t i)
{
S_ROR_IMM;
OP_ORRS(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_ORR_S_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ORR_S_ROR_REG(uint32_t i)
{
S_ROR_REG;
OP_ORRS(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_ORR_S_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ORR_S_IMM_VAL(uint32_t i)
{
S_IMM_VALUE;
OP_ORRS(1,3);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// MOV / MOVS
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define OP_MOV(a, b) \
- cpu->R[REG_POS(i,12)] = shift_op; \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 12)] = shift_op; \
+ if (REG_POS(i, 12) == 15) \
{ \
cpu->next_instruction = shift_op; \
return b; \
@@ -1886,142 +1868,148 @@
return a;
#define OP_MOVS(a, b) \
- cpu->R[REG_POS(i,12)] = shift_op; \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 12)] = shift_op; \
+ if (REG_POS(i, 12) == 15) \
{ \
Status_Reg SPSR = cpu->SPSR; \
armcpu_switchMode(cpu, SPSR.bits.mode); \
- cpu->CPSR=SPSR; \
+ cpu->CPSR = SPSR; \
cpu->changeCPSR(); \
- cpu->R[15] &= (0xFFFFFFFC|(((uint32_t)cpu->CPSR.bits.T)<<1)); \
+ cpu->R[15] &= 0xFFFFFFFC | (static_cast<uint32_t>(cpu->CPSR.bits.T) << 1); \
cpu->next_instruction = cpu->R[15]; \
return b; \
} \
cpu->CPSR.bits.C = c; \
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \
- cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \
- return a; \
-
-TEMPLATE static uint32_t FASTCALL OP_MOV_LSL_IMM(const uint32_t i)
-{
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i, 12)]); \
+ cpu->CPSR.bits.Z = !cpu->R[REG_POS(i, 12)]; \
+ return a;
+
+TEMPLATE static uint32_t FASTCALL OP_MOV_LSL_IMM(uint32_t i)
+{
+ if (i == 0xE1A00000) // nop: MOV R0, R0
+ return 1;
+
LSL_IMM;
OP_MOV(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_MOV_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MOV_LSL_REG(uint32_t i)
{
LSL_REG;
- if (REG_POS(i,0) == 15) shift_op += 4;
+ if (REG_POS(i, 0) == 15)
+ shift_op += 4;
OP_MOV(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_MOV_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MOV_LSR_IMM(uint32_t i)
{
LSR_IMM;
OP_MOV(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_MOV_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MOV_LSR_REG(uint32_t i)
{
LSR_REG;
- if (REG_POS(i,0) == 15) shift_op += 4;
+ if (REG_POS(i, 0) == 15)
+ shift_op += 4;
OP_MOV(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_MOV_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MOV_ASR_IMM(uint32_t i)
{
ASR_IMM;
OP_MOV(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_MOV_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MOV_ASR_REG(uint32_t i)
{
ASR_REG;
OP_MOV(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_MOV_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MOV_ROR_IMM(uint32_t i)
{
ROR_IMM;
OP_MOV(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_MOV_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MOV_ROR_REG(uint32_t i)
{
ROR_REG;
OP_MOV(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_MOV_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MOV_IMM_VAL(uint32_t i)
{
IMM_VALUE;
OP_MOV(1,3);
}
-
-TEMPLATE static uint32_t FASTCALL OP_MOV_S_LSL_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MOV_S_LSL_IMM(uint32_t i)
{
S_LSL_IMM;
OP_MOVS(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_MOV_S_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MOV_S_LSL_REG(uint32_t i)
{
S_LSL_REG;
- if (REG_POS(i,0) == 15) shift_op += 4;
+ if (REG_POS(i, 0) == 15)
+ shift_op += 4;
OP_MOVS(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_MOV_S_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MOV_S_LSR_IMM(uint32_t i)
{
S_LSR_IMM;
OP_MOVS(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_MOV_S_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MOV_S_LSR_REG(uint32_t i)
{
S_LSR_REG;
- if (REG_POS(i,0) == 15) shift_op += 4;
+ if (REG_POS(i, 0) == 15)
+ shift_op += 4;
OP_MOVS(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_MOV_S_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MOV_S_ASR_IMM(uint32_t i)
{
S_ASR_IMM;
OP_MOVS(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_MOV_S_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MOV_S_ASR_REG(uint32_t i)
{
S_ASR_REG;
OP_MOVS(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_MOV_S_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MOV_S_ROR_IMM(uint32_t i)
{
S_ROR_IMM;
OP_MOVS(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_MOV_S_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MOV_S_ROR_REG(uint32_t i)
{
S_ROR_REG;
OP_MOVS(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_MOV_S_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MOV_S_IMM_VAL(uint32_t i)
{
S_IMM_VALUE;
OP_MOVS(1,3);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// BIC / BICS
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define OP_BIC(a, b) \
- cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] & (~shift_op); \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 12)] = cpu->R[REG_POS(i, 16)] & ~shift_op; \
+ if (REG_POS(i, 12) == 15) \
{ \
cpu->next_instruction = cpu->R[15]; \
return b; \
@@ -2029,138 +2017,138 @@
return a;
#define OP_BICS(a, b) \
- cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] & (~shift_op); \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 12)] = cpu->R[REG_POS(i, 16)] & ~shift_op; \
+ if (REG_POS(i, 12) == 15) \
{ \
Status_Reg SPSR = cpu->SPSR; \
armcpu_switchMode(cpu, SPSR.bits.mode); \
- cpu->CPSR=SPSR; \
+ cpu->CPSR = SPSR; \
cpu->changeCPSR(); \
- cpu->R[15] &= (0xFFFFFFFC|(((uint32_t)cpu->CPSR.bits.T)<<1)); \
+ cpu->R[15] &= 0xFFFFFFFC | (static_cast<uint32_t>(cpu->CPSR.bits.T) << 1); \
cpu->next_instruction = cpu->R[15]; \
return b; \
} \
cpu->CPSR.bits.C = c; \
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \
- cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i, 12)]); \
+ cpu->CPSR.bits.Z = !cpu->R[REG_POS(i, 12)]; \
return a;
-TEMPLATE static uint32_t FASTCALL OP_BIC_LSL_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BIC_LSL_IMM(uint32_t i)
{
LSL_IMM;
OP_BIC(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_BIC_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BIC_LSL_REG(uint32_t i)
{
LSL_REG;
OP_BIC(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_BIC_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BIC_LSR_IMM(uint32_t i)
{
LSR_IMM;
OP_BIC(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_BIC_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BIC_LSR_REG(uint32_t i)
{
LSR_REG;
OP_BIC(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_BIC_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BIC_ASR_IMM(uint32_t i)
{
ASR_IMM;
OP_BIC(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_BIC_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BIC_ASR_REG(uint32_t i)
{
ASR_REG;
OP_BIC(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_BIC_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BIC_ROR_IMM(uint32_t i)
{
ROR_IMM;
OP_BIC(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_BIC_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BIC_ROR_REG(uint32_t i)
{
ROR_REG;
OP_BIC(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_BIC_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BIC_IMM_VAL(uint32_t i)
{
IMM_VALUE;
OP_BIC(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_BIC_S_LSL_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BIC_S_LSL_IMM(uint32_t i)
{
S_LSL_IMM;
OP_BICS(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_BIC_S_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BIC_S_LSL_REG(uint32_t i)
{
S_LSL_REG;
OP_BICS(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_BIC_S_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BIC_S_LSR_IMM(uint32_t i)
{
S_LSR_IMM;
OP_BICS(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_BIC_S_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BIC_S_LSR_REG(uint32_t i)
{
S_LSR_REG;
OP_BICS(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_BIC_S_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BIC_S_ASR_IMM(uint32_t i)
{
S_ASR_IMM;
OP_BICS(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_BIC_S_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BIC_S_ASR_REG(uint32_t i)
{
S_ASR_REG;
OP_BICS(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_BIC_S_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BIC_S_ROR_IMM(uint32_t i)
{
S_ROR_IMM;
OP_BICS(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_BIC_S_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BIC_S_ROR_REG(uint32_t i)
{
S_ROR_REG;
OP_BICS(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_BIC_S_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BIC_S_IMM_VAL(uint32_t i)
{
S_IMM_VALUE;
OP_BICS(1,3);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// MVN / MVNS
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define OP_MVN(a, b) \
- cpu->R[REG_POS(i,12)] = ~shift_op; \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 12)] = ~shift_op; \
+ if (REG_POS(i, 12) == 15) \
{ \
cpu->next_instruction = cpu->R[15]; \
return b; \
@@ -2168,1072 +2156,921 @@
return a;
#define OP_MVNS(a, b) \
- cpu->R[REG_POS(i,12)] = ~shift_op; \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 12)] = ~shift_op; \
+ if (REG_POS(i, 12) == 15) \
{ \
Status_Reg SPSR = cpu->SPSR; \
armcpu_switchMode(cpu, SPSR.bits.mode); \
- cpu->CPSR=SPSR; \
+ cpu->CPSR = SPSR; \
cpu->changeCPSR(); \
- cpu->R[15] &= (0xFFFFFFFC|(((uint32_t)cpu->CPSR.bits.T)<<1)); \
+ cpu->R[15] &= 0xFFFFFFFC | (static_cast<uint32_t>(cpu->CPSR.bits.T) << 1); \
cpu->next_instruction = cpu->R[15]; \
return b; \
} \
cpu->CPSR.bits.C = c; \
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \
- cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i, 12)]); \
+ cpu->CPSR.bits.Z = !cpu->R[REG_POS(i, 12)]; \
return a;
-TEMPLATE static uint32_t FASTCALL OP_MVN_LSL_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MVN_LSL_IMM(uint32_t i)
{
LSL_IMM;
OP_MVN(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_MVN_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MVN_LSL_REG(uint32_t i)
{
LSL_REG;
OP_MVN(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_MVN_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MVN_LSR_IMM(uint32_t i)
{
LSR_IMM;
OP_MVN(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_MVN_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MVN_LSR_REG(uint32_t i)
{
LSR_REG;
OP_MVN(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_MVN_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MVN_ASR_IMM(uint32_t i)
{
ASR_IMM;
OP_MVN(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_MVN_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MVN_ASR_REG(uint32_t i)
{
ASR_REG;
OP_MVN(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_MVN_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MVN_ROR_IMM(uint32_t i)
{
ROR_IMM;
OP_MVN(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_MVN_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MVN_ROR_REG(uint32_t i)
{
ROR_REG;
OP_MVN(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_MVN_IMM_VAL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MVN_IMM_VAL(uint32_t i)
{
IMM_VALUE;
OP_MVN(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_MVN_S_LSL_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MVN_S_LSL_IMM(uint32_t i)
{
S_LSL_IMM;
OP_MVNS(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_MVN_S_LSL_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MVN_S_LSL_REG(uint32_t i)
{
S_LSL_REG;
OP_MVNS(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_MVN_S_LSR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MVN_S_LSR_IMM(uint32_t i)
{
S_LSR_IMM;
OP_MVNS(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_MVN_S_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MVN_S_LSR_REG(uint32_t i)
{
S_LSR_REG;
OP_MVNS(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_MVN_S_ASR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MVN_S_ASR_IMM(uint32_t i)
{
S_ASR_IMM;
OP_MVNS(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_MVN_S_ASR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MVN_S_ASR_REG(uint32_t i)
{
S_ASR_REG;
OP_MVNS(2,4);
}
-TEMPLATE static uint32_t FASTCALL OP_MVN_S_ROR_IMM(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MVN_S_ROR_IMM(uint32_t i)
{
S_ROR_IMM;
OP_MVNS(1,3);
}
-TEMPLATE static uint32_t FASTCALL OP_MVN_S_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MVN_S_ROR_REG(uint32_t i)
{
S_ROR_REG;
OP_MVNS(2,4);
-
-}
-
-TEMPLATE static uint32_t FASTCALL OP_MVN_S_IMM_VAL(const uint32_t i)
+}
+
+TEMPLATE static uint32_t FASTCALL OP_MVN_S_IMM_VAL(uint32_t i)
{
S_IMM_VALUE;
OP_MVNS(1,3);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// MUL / MULS / MLA / MLAS
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define MUL_Mxx_END(c) \
v >>= 8; \
- if((v==0)||(v==0xFFFFFF)) \
- return c+1; \
+ if (!v || v == 0xFFFFFF) \
+ return c + 1; \
v >>= 8; \
- if((v==0)||(v==0xFFFF)) \
- return c+2; \
+ if (!v || v == 0xFFFF) \
+ return c + 2; \
v >>= 8; \
- if((v==0)||(v==0xFF)) \
- return c+3; \
- return c+4; \
-
-
-TEMPLATE static uint32_t FASTCALL OP_MUL(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,8)];
- cpu->R[REG_POS(i,16)] = cpu->R[REG_POS(i,0)] * v;
+ if (!v || v == 0xFF) \
+ return c + 3; \
+ return c + 4;
+
+TEMPLATE static uint32_t FASTCALL OP_MUL(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 8)];
+ cpu->R[REG_POS(i, 16)] = cpu->R[REG_POS(i, 0)] * v;
MUL_Mxx_END(1);
}
-TEMPLATE static uint32_t FASTCALL OP_MLA(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,8)];
- cpu->R[REG_POS(i,16)] = cpu->R[REG_POS(i,0)] * v + cpu->R[REG_POS(i,12)];
+TEMPLATE static uint32_t FASTCALL OP_MLA(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 8)];
+ cpu->R[REG_POS(i, 16)] = cpu->R[REG_POS(i, 0)] * v + cpu->R[REG_POS(i, 12)];
MUL_Mxx_END(2);
}
-TEMPLATE static uint32_t FASTCALL OP_MUL_S(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,8)];
- cpu->R[REG_POS(i,16)] = cpu->R[REG_POS(i,0)] * v;
-
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]);
- cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0);
+TEMPLATE static uint32_t FASTCALL OP_MUL_S(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 8)];
+ cpu->R[REG_POS(i, 16)] = cpu->R[REG_POS(i, 0)] * v;
+
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i, 16)]);
+ cpu->CPSR.bits.Z = !cpu->R[REG_POS(i, 16)];
MUL_Mxx_END(1);
}
-TEMPLATE static uint32_t FASTCALL OP_MLA_S(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,8)];
- cpu->R[REG_POS(i,16)] = cpu->R[REG_POS(i,0)] * v + cpu->R[REG_POS(i,12)];
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]);
- cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0);
+TEMPLATE static uint32_t FASTCALL OP_MLA_S(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 8)];
+ cpu->R[REG_POS(i, 16)] = cpu->R[REG_POS(i, 0)] * v + cpu->R[REG_POS(i, 12)];
+
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i, 16)]);
+ cpu->CPSR.bits.Z = !cpu->R[REG_POS(i, 16)];
MUL_Mxx_END(2);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// UMULL / UMULLS / UMLAL / UMLALS
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define MUL_UMxxL_END(c) \
v >>= 8; \
- if(v==0) \
- return c+1; \
+ if (!v) \
+ return c + 1; \
v >>= 8; \
- if(v==0) \
- return c+2; \
+ if (!v) \
+ return c + 2; \
v >>= 8; \
- if(v==0) \
- return c+3; \
- return c+4; \
-
-
-TEMPLATE static uint32_t FASTCALL OP_UMULL(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,8)];
- uint64_t res = (uint64_t)cpu->R[REG_POS(i,0)] * (uint64_t)v;
-
- cpu->R[REG_POS(i,12)] = (uint32_t)res;
- cpu->R[REG_POS(i,16)] = (uint32_t)(res>>32);
+ if (!v) \
+ return c + 3; \
+ return c + 4;
+
+TEMPLATE static uint32_t FASTCALL OP_UMULL(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 8)];
+ uint64_t res = static_cast<uint64_t>(cpu->R[REG_POS(i, 0)]) * static_cast<uint64_t>(v);
+
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(res);
+ cpu->R[REG_POS(i, 16)] = static_cast<uint32_t>(res >> 32);
MUL_UMxxL_END(2);
}
-TEMPLATE static uint32_t FASTCALL OP_UMLAL(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,8)];
- uint64_t res = (uint64_t)cpu->R[REG_POS(i,0)] * (uint64_t)v;
+TEMPLATE static uint32_t FASTCALL OP_UMLAL(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 8)];
+ uint64_t res = static_cast<uint64_t>(cpu->R[REG_POS(i, 0)]) * static_cast<uint64_t>(v);
// RdLo = (Rm * Rs)[31:0] + RdLo /* Unsigned multiplication */
// RdHi = (Rm * Rs)[63:32] + RdHi + CarryFrom((Rm * Rs)[31:0] + RdLo)
- uint32_t tmp = (uint32_t)res; // low
- cpu->R[REG_POS(i,16)] = (uint32_t)(res>>32) + cpu->R[REG_POS(i,16)] + CarryFrom(tmp, cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,12)] += tmp;
+ uint32_t tmp = static_cast<uint32_t>(res); // low
+ cpu->R[REG_POS(i, 16)] = static_cast<uint32_t>(res >> 32) + cpu->R[REG_POS(i, 16)] + CarryFrom(tmp, cpu->R[REG_POS(i, 12)]);
+ cpu->R[REG_POS(i, 12)] += tmp;
MUL_UMxxL_END(3);
}
-TEMPLATE static uint32_t FASTCALL OP_UMULL_S(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,8)];
- uint64_t res = ((uint64_t)cpu->R[REG_POS(i,0)] * (uint64_t)v);
-
- cpu->R[REG_POS(i,12)] = (uint32_t)res;
- cpu->R[REG_POS(i,16)] = (uint32_t)(res>>32);
-
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]);
- cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) && (cpu->R[REG_POS(i,12)]==0);
+TEMPLATE static uint32_t FASTCALL OP_UMULL_S(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 8)];
+ uint64_t res = static_cast<uint64_t>(cpu->R[REG_POS(i, 0)]) * static_cast<uint64_t>(v);
+
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(res);
+ cpu->R[REG_POS(i, 16)] = static_cast<uint32_t>(res >> 32);
+
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i, 16)]);
+ cpu->CPSR.bits.Z = !cpu->R[REG_POS(i, 16)] && !cpu->R[REG_POS(i, 12)];
MUL_UMxxL_END(2);
}
-TEMPLATE static uint32_t FASTCALL OP_UMLAL_S(const uint32_t i)
-{
- uint32_t v = cpu->R[REG_POS(i,8)];
- uint64_t res = (uint64_t)cpu->R[REG_POS(i,0)] * (uint64_t)v;
+TEMPLATE static uint32_t FASTCALL OP_UMLAL_S(uint32_t i)
+{
+ uint32_t v = cpu->R[REG_POS(i, 8)];
+ uint64_t res = static_cast<uint64_t>(cpu->R[REG_POS(i, 0)]) * static_cast<uint64_t>(v);
// RdLo = (Rm * Rs)[31:0] + RdLo /* Unsigned multiplication */
// RdHi = (Rm * Rs)[63:32] + RdHi + CarryFrom((Rm * Rs)[31:0] + RdLo)
- uint32_t tmp = (uint32_t)res; // low
- cpu->R[REG_POS(i,16)] = (uint32_t)(res>>32) + cpu->R[REG_POS(i,16)] + CarryFrom(tmp, cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,12)] += tmp;
-
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]);
- cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0);
+ uint32_t tmp = static_cast<uint32_t>(res); // low
+ cpu->R[REG_POS(i, 16)] = static_cast<uint32_t>(res >> 32) + cpu->R[REG_POS(i, 16)] + CarryFrom(tmp, cpu->R[REG_POS(i, 12)]);
+ cpu->R[REG_POS(i, 12)] += tmp;
+
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i, 16)]);
+ cpu->CPSR.bits.Z = !cpu->R[REG_POS(i, 16)] & !cpu->R[REG_POS(i, 12)];
MUL_UMxxL_END(3);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// SMULL / SMULLS / SMLAL / SMLALS
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define MUL_SMxxL_END(c) \
v &= 0xFFFFFFFF; \
v >>= 8; \
- if((v==0)||(v==0xFFFFFF)) \
- return c+1; \
+ if (!v || v == 0xFFFFFF) \
+ return c + 1; \
v >>= 8; \
- if((v==0)||(v==0xFFFF)) \
- return c+2; \
+ if (!v || v == 0xFFFF) \
+ return c + 2; \
v >>= 8; \
- if((v==0)||(v==0xFF)) \
- return c+3; \
- return c+4; \
-
-
-TEMPLATE static uint32_t FASTCALL OP_SMULL(const uint32_t i)
-{
- int64_t v = (int32_t)cpu->R[REG_POS(i,8)];
- int64_t res = v * (int64_t)(int32_t)cpu->R[REG_POS(i,0)];
-
- cpu->R[REG_POS(i,12)] = (uint32_t)res;
- cpu->R[REG_POS(i,16)] = (uint32_t)(res>>32);
+ if (!v || v == 0xFF) \
+ return c + 3; \
+ return c + 4;
+
+TEMPLATE static uint32_t FASTCALL OP_SMULL(uint32_t i)
+{
+ int64_t v = static_cast<int32_t>(cpu->R[REG_POS(i, 8)]);
+ int64_t res = v * static_cast<int64_t>(static_cast<int32_t>(cpu->R[REG_POS(i, 0)]));
+
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(res);
+ cpu->R[REG_POS(i, 16)] = static_cast<uint32_t>(res >> 32);
MUL_SMxxL_END(2);
}
-TEMPLATE static uint32_t FASTCALL OP_SMLAL(const uint32_t i)
-{
-
- int64_t v = (int32_t)cpu->R[REG_POS(i,8)];
- int64_t res = v * (int64_t)(int32_t)cpu->R[REG_POS(i,0)];
-
- //LOG("%08X * %08X + %08X%08X\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], cpu->R[REG_POS(i,16)], cpu->R[REG_POS(i,12)]);
-
- uint32_t tmp = (uint32_t)res;
- cpu->R[REG_POS(i,16)] = (uint32_t)(res>>32) + cpu->R[REG_POS(i,16)] + CarryFrom(tmp, cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,12)] += tmp;
-
- //LOG("= %08X%08X %08X%08X\n", cpu->R[REG_POS(i,16)], cpu->R[REG_POS(i,12)], res);
+TEMPLATE static uint32_t FASTCALL OP_SMLAL(uint32_t i)
+{
+ int64_t v = static_cast<int32_t>(cpu->R[REG_POS(i, 8)]);
+ int64_t res = v * static_cast<int64_t>(static_cast<int32_t>(cpu->R[REG_POS(i, 0)]));
+
+ uint32_t tmp = static_cast<uint32_t>(res);
+ cpu->R[REG_POS(i, 16)] = static_cast<uint32_t>(res >> 32) + cpu->R[REG_POS(i, 16)] + CarryFrom(tmp, cpu->R[REG_POS(i, 12)]);
+ cpu->R[REG_POS(i, 12)] += tmp;
MUL_SMxxL_END(3);
}
-TEMPLATE static uint32_t FASTCALL OP_SMULL_S(const uint32_t i)
-{
- int64_t v = (int32_t)cpu->R[REG_POS(i,8)];
- int64_t res = v * (int64_t)(int32_t)cpu->R[REG_POS(i,0)];
-
- cpu->R[REG_POS(i,12)] = (uint32_t)res;
- cpu->R[REG_POS(i,16)] = (uint32_t)(res>>32);
-
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]);
- cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0);
+TEMPLATE static uint32_t FASTCALL OP_SMULL_S(uint32_t i)
+{
+ int64_t v = static_cast<int32_t>(cpu->R[REG_POS(i, 8)]);
+ int64_t res = v * static_cast<int64_t>(static_cast<int32_t>(cpu->R[REG_POS(i, 0)]));
+
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(res);
+ cpu->R[REG_POS(i, 16)] = static_cast<uint32_t>(res >> 32);
+
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i, 16)]);
+ cpu->CPSR.bits.Z = !cpu->R[REG_POS(i, 16)] & !cpu->R[REG_POS(i, 12)];
MUL_SMxxL_END(2);
}
-TEMPLATE static uint32_t FASTCALL OP_SMLAL_S(const uint32_t i)
-{
- int64_t v = (int32_t)cpu->R[REG_POS(i,8)];
- int64_t res = v * (int64_t)(int32_t)cpu->R[REG_POS(i,0)];
-
- uint32_t tmp = (uint32_t)res;
- cpu->R[REG_POS(i,16)] = (uint32_t)(res>>32) + cpu->R[REG_POS(i,16)] + CarryFrom(tmp, cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,12)] += tmp;
-
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]);
- cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0);
+TEMPLATE static uint32_t FASTCALL OP_SMLAL_S(uint32_t i)
+{
+ int64_t v = static_cast<int32_t>(cpu->R[REG_POS(i, 8)]);
+ int64_t res = v * static_cast<int64_t>(static_cast<int32_t>(cpu->R[REG_POS(i, 0)]));
+
+ uint32_t tmp = static_cast<uint32_t>(res);
+ cpu->R[REG_POS(i, 16)] = static_cast<uint32_t>(res >> 32) + cpu->R[REG_POS(i, 16)] + CarryFrom(tmp, cpu->R[REG_POS(i, 12)]);
+ cpu->R[REG_POS(i, 12)] += tmp;
+
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i, 16)]);
+ cpu->CPSR.bits.Z = !cpu->R[REG_POS(i, 16)] & !cpu->R[REG_POS(i, 12)];
MUL_SMxxL_END(3);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// SWP / SWPB
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_SWP(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- uint32_t tmp = ROR(READ32(cpu->mem_if->data, adr), (adr & 3)<<3);
-
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,0)]);
- cpu->R[REG_POS(i,12)] = tmp;
-
- uint32_t c = MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(adr);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(adr);
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_SWP(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ uint32_t tmp = ROR(READ32(cpu->mem_if->data, adr), (adr & 3) << 3);
+
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 0)]);
+ cpu->R[REG_POS(i, 12)] = tmp;
+
+ uint32_t c = MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(adr);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(adr);
return MMU_aluMemCycles<PROCNUM>(4, c);
}
-TEMPLATE static uint32_t FASTCALL OP_SWPB(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_SWPB(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
uint8_t tmp = READ8(cpu->mem_if->data, adr);
- WRITE8(cpu->mem_if->data, adr, (uint8_t)(cpu->R[REG_POS(i,0)]&0xFF));
- cpu->R[REG_POS(i,12)] = tmp;
-
- uint32_t c = MMU_memAccessCycles<PROCNUM,8,MMU_AD_READ>(adr);
- c += MMU_memAccessCycles<PROCNUM,8,MMU_AD_WRITE>(adr);
+
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 0)] & 0xFF));
+ cpu->R[REG_POS(i, 12)] = tmp;
+
+ uint32_t c = MMU_memAccessCycles<PROCNUM, 8, MMU_AD_READ>(adr);
+ c += MMU_memAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(adr);
return MMU_aluMemCycles<PROCNUM>(4, c);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// LDRH
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_LDRH_P_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ16(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRH_M_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ16(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRH_P_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
- cpu->R[REG_POS(i,12)] = (uint32_t)READ16(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRH_M_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
- cpu->R[REG_POS(i,12)] = (uint32_t)READ16(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRH_PRE_INDE_P_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ16(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRH_PRE_INDE_M_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ16(cpu->mem_if->data, adr);
-
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRH_PRE_INDE_P_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] =(uint32_t)READ16(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRH_PRE_INDE_M_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ16(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRH_POS_INDE_P_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] += IMM_OFF;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ16(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRH_POS_INDE_M_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] -= IMM_OFF;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ16(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRH_POS_INDE_P_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)];
- cpu->R[REG_POS(i,12)] = (uint32_t)READ16(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRH_POS_INDE_M_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)];
- cpu->R[REG_POS(i,12)] = (uint32_t)READ16(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_LDRH_P_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + IMM_OFF;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ16(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRH_M_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - IMM_OFF;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ16(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRH_P_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + cpu->R[REG_POS(i, 0)];
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ16(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRH_M_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - cpu->R[REG_POS(i, 0)];
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ16(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRH_PRE_INDE_P_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + IMM_OFF;
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ16(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRH_PRE_INDE_M_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - IMM_OFF;
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ16(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRH_PRE_INDE_P_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + cpu->R[REG_POS(i, 0)];
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ16(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRH_PRE_INDE_M_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - cpu->R[REG_POS(i, 0)];
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ16(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRH_POS_INDE_P_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] += IMM_OFF;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ16(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRH_POS_INDE_M_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] -= IMM_OFF;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ16(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRH_POS_INDE_P_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] += cpu->R[REG_POS(i, 0)];
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ16(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRH_POS_INDE_M_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] -= cpu->R[REG_POS(i, 0)];
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ16(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+// -----------------------------------------------------------------------------
// STRH
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_STRH_P_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
- WRITE16(cpu->mem_if->data, adr, (uint16_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRH_M_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
- WRITE16(cpu->mem_if->data, adr, (uint16_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRH_P_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
- WRITE16(cpu->mem_if->data, adr, (uint16_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRH_M_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
- WRITE16(cpu->mem_if->data, adr, (uint16_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRH_PRE_INDE_P_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE16(cpu->mem_if->data, adr, (uint16_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRH_PRE_INDE_M_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE16(cpu->mem_if->data, adr, (uint16_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRH_PRE_INDE_P_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
- cpu->R[REG_POS(i,16)] = adr;
- WRITE16(cpu->mem_if->data, adr, (uint16_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRH_PRE_INDE_M_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
- cpu->R[REG_POS(i,16)] = adr;
- WRITE16(cpu->mem_if->data, adr, (uint16_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRH_POS_INDE_P_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE16(cpu->mem_if->data, adr, (uint16_t)cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] += IMM_OFF;
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRH_POS_INDE_M_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE16(cpu->mem_if->data, adr, (uint16_t)cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] -= IMM_OFF;
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRH_POS_INDE_P_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE16(cpu->mem_if->data, adr, (uint16_t)cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)];
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRH_POS_INDE_M_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE16(cpu->mem_if->data, adr, (uint16_t)cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)];
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_WRITE>(2,adr);
-}
-
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_STRH_P_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + IMM_OFF;
+ WRITE16(cpu->mem_if->data, adr, static_cast<uint16_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRH_M_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - IMM_OFF;
+ WRITE16(cpu->mem_if->data, adr, static_cast<uint16_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRH_P_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + cpu->R[REG_POS(i, 0)];
+ WRITE16(cpu->mem_if->data, adr, static_cast<uint16_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRH_M_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - cpu->R[REG_POS(i, 0)];
+ WRITE16(cpu->mem_if->data, adr, static_cast<uint16_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRH_PRE_INDE_P_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + IMM_OFF;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE16(cpu->mem_if->data, adr, static_cast<uint16_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRH_PRE_INDE_M_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - IMM_OFF;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE16(cpu->mem_if->data, adr, static_cast<uint16_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRH_PRE_INDE_P_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + cpu->R[REG_POS(i, 0)];
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE16(cpu->mem_if->data, adr, static_cast<uint16_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRH_PRE_INDE_M_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - cpu->R[REG_POS(i, 0)];
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE16(cpu->mem_if->data, adr, static_cast<uint16_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRH_POS_INDE_P_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE16(cpu->mem_if->data, adr, static_cast<uint16_t>(cpu->R[REG_POS(i, 12)]));
+ cpu->R[REG_POS(i, 16)] += IMM_OFF;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRH_POS_INDE_M_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE16(cpu->mem_if->data, adr, static_cast<uint16_t>(cpu->R[REG_POS(i, 12)]));
+ cpu->R[REG_POS(i, 16)] -= IMM_OFF;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRH_POS_INDE_P_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE16(cpu->mem_if->data, adr, static_cast<uint16_t>(cpu->R[REG_POS(i, 12)]));
+ cpu->R[REG_POS(i, 16)] += cpu->R[REG_POS(i, 0)];
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRH_POS_INDE_M_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE16(cpu->mem_if->data, adr, static_cast<uint16_t>(cpu->R[REG_POS(i, 12)]));
+ cpu->R[REG_POS(i, 16)] -= cpu->R[REG_POS(i, 0)];
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_WRITE>(2, adr);
+}
+
+// -----------------------------------------------------------------------------
// LDRSH
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSH_P_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
- cpu->R[REG_POS(i,12)] = (int32_t)((int16_t)READ16(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSH_M_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
- cpu->R[REG_POS(i,12)] = (int32_t)((int16_t)READ16(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSH_P_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
- cpu->R[REG_POS(i,12)] = (int32_t)((int16_t)READ16(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSH_M_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
- cpu->R[REG_POS(i,12)] = (int32_t)((int16_t)READ16(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSH_PRE_INDE_P_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (int32_t)((int16_t)READ16(cpu->mem_if->data, adr));
-
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSH_PRE_INDE_M_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (int32_t)((int16_t)READ16(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSH_PRE_INDE_P_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (int32_t)((int16_t)READ16(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSH_PRE_INDE_M_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (int32_t)((int16_t)READ16(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSH_POS_INDE_P_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] += IMM_OFF;
- cpu->R[REG_POS(i,12)] = (int32_t)((int16_t)READ16(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSH_POS_INDE_M_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] -= IMM_OFF;
- cpu->R[REG_POS(i,12)] = (int32_t)((int16_t)READ16(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSH_POS_INDE_P_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)];
- cpu->R[REG_POS(i,12)] = (int32_t)((int16_t)READ16(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSH_POS_INDE_M_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)];
- cpu->R[REG_POS(i,12)] = (int32_t)((int16_t)READ16(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
-}
-
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSH_P_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + IMM_OFF;
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int16_t>(READ16(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSH_M_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - IMM_OFF;
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int16_t>(READ16(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSH_P_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + cpu->R[REG_POS(i, 0)];
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int16_t>(READ16(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSH_M_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - cpu->R[REG_POS(i, 0)];
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int16_t>(READ16(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSH_PRE_INDE_P_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + IMM_OFF;
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int16_t>(READ16(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSH_PRE_INDE_M_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - IMM_OFF;
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int16_t>(READ16(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSH_PRE_INDE_P_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + cpu->R[REG_POS(i, 0)];
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int16_t>(READ16(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSH_PRE_INDE_M_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - cpu->R[REG_POS(i, 0)];
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int16_t>(READ16(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSH_POS_INDE_P_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] += IMM_OFF;
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int16_t>(READ16(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSH_POS_INDE_M_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] -= IMM_OFF;
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int16_t>(READ16(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSH_POS_INDE_P_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] += cpu->R[REG_POS(i, 0)];
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int16_t>(READ16(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSH_POS_INDE_M_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] -= cpu->R[REG_POS(i, 0)];
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int16_t>(READ16(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+// -----------------------------------------------------------------------------
// LDRSB
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSB_P_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
- cpu->R[REG_POS(i,12)] = (int32_t)((int8_t)READ8(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSB_M_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
- cpu->R[REG_POS(i,12)] = (int32_t)((int8_t)READ8(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSB_P_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
- cpu->R[REG_POS(i,12)] = (int32_t)((int8_t)READ8(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSB_M_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
- cpu->R[REG_POS(i,12)] = (int32_t)((int8_t)READ8(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSB_PRE_INDE_P_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (int32_t)((int8_t)READ8(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSB_PRE_INDE_M_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (int32_t)((int8_t)READ8(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSB_PRE_INDE_P_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (int32_t)((int8_t)READ8(cpu->mem_if->data, adr));
-
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSB_PRE_INDE_M_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (int32_t)((int8_t)READ8(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSB_POS_INDE_P_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] += IMM_OFF;
- cpu->R[REG_POS(i,12)] = (int32_t)((int8_t)READ8(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSB_POS_INDE_M_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] -= IMM_OFF;
- cpu->R[REG_POS(i,12)] = (int32_t)((int8_t)READ8(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSB_POS_INDE_P_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)];
- cpu->R[REG_POS(i,12)] = (int32_t)((int8_t)READ8(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRSB_POS_INDE_M_REG_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)];
- cpu->R[REG_POS(i,12)] = (int32_t)((int8_t)READ8(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSB_P_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + IMM_OFF;
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int8_t>(READ8(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSB_M_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - IMM_OFF;
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int8_t>(READ8(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSB_P_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + cpu->R[REG_POS(i, 0)];
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int8_t>(READ8(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSB_M_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - cpu->R[REG_POS(i, 0)];
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int8_t>(READ8(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSB_PRE_INDE_P_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + IMM_OFF;
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int8_t>(READ8(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSB_PRE_INDE_M_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - IMM_OFF;
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int8_t>(READ8(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSB_PRE_INDE_P_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + cpu->R[REG_POS(i, 0)];
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int8_t>(READ8(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSB_PRE_INDE_M_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - cpu->R[REG_POS(i, 0)];
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int8_t>(READ8(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSB_POS_INDE_P_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] += IMM_OFF;
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int8_t>(READ8(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSB_POS_INDE_M_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] -= IMM_OFF;
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int8_t>(READ8(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSB_POS_INDE_P_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] += cpu->R[REG_POS(i, 0)];
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int8_t>(READ8(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRSB_POS_INDE_M_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] -= cpu->R[REG_POS(i, 0)];
+ cpu->R[REG_POS(i, 12)] = static_cast<int32_t>(static_cast<int8_t>(READ8(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+// -----------------------------------------------------------------------------
// MRS / MSR
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_MRS_CPSR(const uint32_t i)
-{
- cpu->R[REG_POS(i,12)] = cpu->CPSR.val;
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_MRS_CPSR(uint32_t i)
+{
+ cpu->R[REG_POS(i, 12)] = cpu->CPSR.val;
return 1;
}
-TEMPLATE static uint32_t FASTCALL OP_MRS_SPSR(const uint32_t i)
-{
- cpu->R[REG_POS(i,12)] = cpu->SPSR.val;
+TEMPLATE static uint32_t FASTCALL OP_MRS_SPSR(uint32_t i)
+{
+ cpu->R[REG_POS(i, 12)] = cpu->SPSR.val;
return 1;
}
-#define v4_UNALLOC_MASK 0x0FFFFF00
-#define v4_USER_MASK 0xF0000000
-#define v4_PRIV_MASK 0x0000000F
-#define v4_STATE_MASK 0x00000020
-
-#define v5_UNALLOC_MASK 0x07FFFF00
-#define v5_USER_MASK 0xF8000000
-#define v5_PRIV_MASK 0x0000000F
-#define v5_STATE_MASK 0x00000020
-
-TEMPLATE static uint32_t FASTCALL OP_MSR_CPSR(const uint32_t i)
-{
- uint32_t operand = cpu->R[REG_POS(i,0)];
-
-#if 0
- // TODO
+
+#define OP_MSR_CPSR_(operand) \
+ uint32_t byte_mask = cpu->CPSR.bits.mode == USR ? (BIT19(i) ? 0xFF000000 : 0x00000000) : \
+ (BIT16(i) ? 0x000000FF : 0x00000000) | (BIT17(i) ? 0x0000FF00:0x00000000) | (BIT18(i) ? 0x00FF0000 : 0x00000000) | (BIT19(i) ? 0xFF000000 : 0x00000000); \
+ if (cpu->CPSR.bits.mode != USR && BIT16(i)) \
+ armcpu_switchMode(cpu, operand & 0x1F); \
+ cpu->CPSR.val = (cpu->CPSR.val & ~byte_mask) | (operand & byte_mask); \
+ cpu->changeCPSR();
+
+#define OP_MSR_SPSR_(operand) \
+ if (cpu->CPSR.bits.mode == USR || cpu->CPSR.bits.mode == SYS) \
+ return 1; \
+ uint32_t byte_mask = (BIT16(i) ? 0x000000FF : 0x00000000) | (BIT17(i) ? 0x0000FF00 : 0x00000000) | (BIT18(i) ? 0x00FF0000 : 0x00000000) | (BIT19(i) ? 0xFF000000 : 0x00000000); \
+ cpu->SPSR.val = (cpu->SPSR.val & ~byte_mask) | (operand & byte_mask); \
+ cpu->changeCPSR();
+
+//#define __NEW_MSR
+#ifdef __NEW_MSR
+#define v4T_UNALLOC_MASK 0x0FFFFF00
+#define v4T_USER_MASK 0xF0000000
+#define v4T_PRIV_MASK 0x0000000F
+#define v4T_STATE_MASK 0x00000020
+
+#define v5TE_UNALLOC_MASK 0x07FFFF00
+#define v5TE_USER_MASK 0xF8000000
+#define v5TE_PRIV_MASK 0x0000000F
+#define v5TE_STATE_MASK 0x00000020
+#endif
+
+TEMPLATE static uint32_t FASTCALL OP_MSR_CPSR(uint32_t i)
+{
+ uint32_t operand = cpu->R[REG_POS(i, 0)];
+
+#ifdef __NEW_MSR
uint32_t mask = 0;
- uint32_t byte_mask = (BIT16(i)?0x000000FF:0x00000000) |
- (BIT17(i)?0x0000FF00:0x00000000) |
- (BIT18(i)?0x00FF0000:0x00000000) |
- (BIT19(i)?0xFF000000:0x00000000);
-
- if (PROCNUM == 0)
- {
- if ((operand & v5_UNALLOC_MASK) != 0) printf("ARM9: MSR_CPSR_REG UNPREDICTABLE UNALLOC (operand %08X)\n", operand);
- if (cpu->CPSR.bits.mode != USR) // Privileged mode
- {
- if ((operand & v5_STATE_MASK) != 0) printf("ARM9: MSR_CPSR_REG UNPREDICTABLE STATE (operand %08X)\n", operand);
- mask = byte_mask & (v5_USER_MASK | v5_PRIV_MASK);
- }
+ uint32_t byte_mask = (BIT16(i) ? 0x000000FF : 0x00000000) | (BIT17(i) ? 0x0000FF00 : 0x00000000) | (BIT18(i) ? 0x00FF0000 : 0x00000000) | (BIT19(i) ? 0xFF000000 : 0x00000000);
+
+ uint32_t unallocMask = PROCNUM?v4T_UNALLOC_MASK : v5TE_UNALLOC_MASK;
+ uint32_t userMask = PROCNUM?v4T_USER_MASK : v5TE_USER_MASK;
+ uint32_t privMask = PROCNUM?v4T_PRIV_MASK : v5TE_PRIV_MASK;
+ uint32_t stateMask = PROCNUM?v4T_STATE_MASK : v5TE_STATE_MASK;
+
+ if (operand & unallocMask)
+ printf("ARM%c: MSR_CPSR_REG UNPREDICTABLE UNALLOC (operand %08X)\n", PROCNUM ? '7' : '9', operand);
+ if (cpu->CPSR.bits.mode != USR) // Privileged mode
+ {
+ if (BIT16(i))
+ armcpu_switchMode(cpu, operand & 0x1F);
+ if (operand & stateMask)
+ printf("ARM%c: MSR_CPSR_REG UNPREDICTABLE STATE (operand %08X)\n", PROCNUM ? '7' : '9', operand);
else
- mask = byte_mask & v5_USER_MASK;
+ mask = byte_mask & (userMask | privMask);
}
else
- {
- if ((operand & v4_UNALLOC_MASK) != 0) printf("ARM7: MSR_CPSR_REG UNPREDICTABLE UNALLOC (operand %08X)\n", operand);
- if(cpu->CPSR.bits.mode != USR) // Privileged mode
- {
- if ((operand & v4_STATE_MASK) != 0) printf("ARM7: MSR_CPSR_REG UNPREDICTABLE STATE (operand %08X)\n", operand);
- mask = byte_mask & (v4_USER_MASK | v4_PRIV_MASK);
- }
- else
- mask = byte_mask & v4_USER_MASK;
- }
- cpu->CPSR.val = ((cpu->CPSR.val & (~mask)) | (operand & mask));
- if (BIT16(i)) armcpu_switchMode(cpu, cpu->CPSR.bits.mode);
+ mask = byte_mask & userMask;
+
+ u32 new_val = (cpu->CPSR.val & ~mask) | (operand & mask);
+ cpu->CPSR.val = (cpu->CPSR.val & ~mask) | (operand & mask);
cpu->changeCPSR();
#else
- if(cpu->CPSR.bits.mode!=USR)
- {
- if(BIT16(i))
- {
- armcpu_switchMode(cpu, operand & 0x1F);
- cpu->CPSR.val = (cpu->CPSR.val & 0xFFFFFF00) | (operand & 0xFF);
- }
- if(BIT17(i))
- cpu->CPSR.val = (cpu->CPSR.val & 0xFFFF00FF) | (operand & 0xFF00);
- if(BIT18(i))
- cpu->CPSR.val = (cpu->CPSR.val & 0xFF00FFFF) | (operand & 0xFF0000);
- }
- if(BIT19(i))
- cpu->CPSR.val = (cpu->CPSR.val & 0x00FFFFFF) | (operand & 0xFF000000);
-
- cpu->changeCPSR();
+ OP_MSR_CPSR_(operand);
#endif
-
return 1;
}
-TEMPLATE static uint32_t FASTCALL OP_MSR_SPSR(const uint32_t i)
-{
- uint32_t operand = cpu->R[REG_POS(i,0)];
-
-#if 0
- // TODO
- uint32_t mask = 0;
- uint32_t byte_mask = (BIT16(i)?0x000000FF:0x00000000) |
- (BIT17(i)?0x0000FF00:0x00000000) |
- (BIT18(i)?0x00FF0000:0x00000000) |
- (BIT19(i)?0xFF000000:0x00000000);
-
- if (PROCNUM == 0)
- {
- if ((operand & v5_UNALLOC_MASK) != 0) printf("ARM9: MSR_SPSR_REG UNPREDICTABLE UNALLOC (operand %08X)\n", operand);
- // if CurrentModeHasSPSR
- mask = byte_mask & (v5_USER_MASK | v5_PRIV_MASK | v5_STATE_MASK);
- }
- else
- {
- if ((operand & v4_UNALLOC_MASK) != 0) printf("ARM7: MSR_SPSR_REG UNPREDICTABLE UNALLOC (operand %08X)\n", operand);
- // if CurrentModeHasSPSR
- mask = byte_mask & (v4_USER_MASK | v4_PRIV_MASK | v4_STATE_MASK);
- }
- cpu->SPSR.val = ((cpu->SPSR.val & (~mask)) | (operand & mask));
- cpu->changeCPSR();
-#else
- if(cpu->CPSR.bits.mode!=USR)
- {
- if(BIT16(i))
- {
- cpu->SPSR.val = (cpu->SPSR.val & 0xFFFFFF00) | (operand & 0xFF);
- }
- if(BIT17(i))
- cpu->SPSR.val = (cpu->SPSR.val & 0xFFFF00FF) | (operand & 0xFF00);
- if(BIT18(i))
- cpu->SPSR.val = (cpu->SPSR.val & 0xFF00FFFF) | (operand & 0xFF0000);
- }
- if(BIT19(i))
- cpu->SPSR.val = (cpu->SPSR.val & 0x00FFFFFF) | (operand & 0xFF000000);
-#endif
-
+TEMPLATE static uint32_t FASTCALL OP_MSR_SPSR(uint32_t i)
+{
+ //printf("OP_MSR_SPSR\n");
+ uint32_t operand = cpu->R[REG_POS(i, 0)];
+ OP_MSR_SPSR_(operand);
return 1;
}
-TEMPLATE static uint32_t FASTCALL OP_MSR_CPSR_IMM_VAL(const uint32_t i)
-{
+TEMPLATE static uint32_t FASTCALL OP_MSR_CPSR_IMM_VAL(uint32_t i)
+{
+ //printf("OP_MSR_CPSR_IMM_VAL\n");
IMM_VALUE;
-
-#if 0
- // TODO
- uint32_t operand = shift_op;
- uint32_t mask = 0;
- uint32_t byte_mask = (BIT16(i)?0x000000FF:0x00000000) |
- (BIT17(i)?0x0000FF00:0x00000000) |
- (BIT18(i)?0x00FF0000:0x00000000) |
- (BIT19(i)?0xFF000000:0x00000000);
-
- if (PROCNUM == 0)
- {
- if ((operand & v5_UNALLOC_MASK) != 0) printf("ARM9: MSR_CPSR_IMM UNPREDICTABLE UNALLOC (operand %08X)\n", operand);
- if (cpu->CPSR.bits.mode != USR) // Privileged mode
- {
- if ((operand & v5_STATE_MASK) != 0) printf("ARM9: MSR_CPSR_IMM UNPREDICTABLE STATE (operand %08X)\n", operand);
- mask = byte_mask & (v5_USER_MASK | v5_PRIV_MASK);
- }
- else
- mask = byte_mask & v5_USER_MASK;
- }
- else
- {
- if ((operand & v4_UNALLOC_MASK) != 0) printf("ARM7: MSR_CPSR_IMM UNPREDICTABLE UNALLOC (operand %08X)\n", operand);
- if(cpu->CPSR.bits.mode != USR) // Privileged mode
- {
- if ((operand & v4_STATE_MASK) != 0) printf("ARM7: MSR_CPSR_IMM UNPREDICTABLE STATE (operand %08X)\n", operand);
- mask = byte_mask & (v4_USER_MASK | v4_PRIV_MASK);
- }
- else
- mask = byte_mask & v4_USER_MASK;
- }
- cpu->CPSR.val = ((cpu->CPSR.val & (~mask)) | (operand & mask));
- if (BIT16(i)) armcpu_switchMode(cpu, cpu->CPSR.bits.mode);
- cpu->changeCPSR();
-#else
- if(cpu->CPSR.bits.mode!=USR)
- {
- if(BIT16(i))
- {
- armcpu_switchMode(cpu, shift_op & 0x1F);
- cpu->CPSR.val = (cpu->CPSR.val & 0xFFFFFF00) | (shift_op & 0xFF);
- }
- if(BIT17(i))
- cpu->CPSR.val = (cpu->CPSR.val & 0xFFFF00FF) | (shift_op & 0xFF00);
- if(BIT18(i))
- cpu->CPSR.val = (cpu->CPSR.val & 0xFF00FFFF) | (shift_op & 0xFF0000);
- }
- if(BIT19(i))
- {
- //cpu->CPSR.val = (cpu->CPSR.val & 0xFF000000) | (shift_op & 0xFF000000);
- cpu->CPSR.val = (cpu->CPSR.val & 0x00FFFFFF) | (shift_op & 0xFF000000);
- }
- cpu->changeCPSR();
-#endif
-
+ OP_MSR_CPSR_(shift_op);
return 1;
}
-TEMPLATE static uint32_t FASTCALL OP_MSR_SPSR_IMM_VAL(const uint32_t i)
-{
+TEMPLATE static uint32_t FASTCALL OP_MSR_SPSR_IMM_VAL(uint32_t i)
+{
+ //printf("OP_MSR_SPSR_IMM_VAL\n");
IMM_VALUE;
-
-#if 0
- // TODO
- uint32_t operand = shift_op;
- uint32_t mask = 0;
- uint32_t byte_mask = (BIT16(i)?0x000000FF:0x00000000) |
- (BIT17(i)?0x0000FF00:0x00000000) |
- (BIT18(i)?0x00FF0000:0x00000000) |
- (BIT19(i)?0xFF000000:0x00000000);
-
- if (PROCNUM == 0)
- {
- if ((operand & v5_UNALLOC_MASK) != 0) printf("ARM9: MSR_SPSR_IMM UNPREDICTABLE UNALLOC (operand %08X)\n", operand);
- // if CurrentModeHasSPSR
- mask = byte_mask & (v5_USER_MASK | v5_PRIV_MASK | v5_STATE_MASK);
- }
- else
- {
- if ((operand & v4_UNALLOC_MASK) != 0) printf("ARM7: MSR_SPSR_IMM UNPREDICTABLE UNALLOC (operand %08X)\n", operand);
- // if CurrentModeHasSPSR
- mask = byte_mask & (v4_USER_MASK | v4_PRIV_MASK | v4_STATE_MASK);
- }
- cpu->SPSR.val = ((cpu->SPSR.val & (~mask)) | (operand & mask));
-#else
- if(cpu->CPSR.bits.mode!=USR)
- {
- if(BIT16(i))
- {
- cpu->SPSR.val = (cpu->SPSR.val & 0xFFFFFF00) | (shift_op & 0xFF);
- }
- if(BIT17(i))
- cpu->SPSR.val = (cpu->SPSR.val & 0xFFFF00FF) | (shift_op & 0xFF00);
- if(BIT18(i))
- cpu->SPSR.val = (cpu->SPSR.val & 0xFF00FFFF) | (shift_op & 0xFF0000);
- }
- if(BIT19(i))
- {
- cpu->SPSR.val = (cpu->SPSR.val & 0xFF000000) | (shift_op & 0xFF000000);
- }
-
- cpu->changeCPSR();
-#endif
-
+ OP_MSR_SPSR_(shift_op);
return 1;
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// Branch
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_BX(const uint32_t i)
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_BX(uint32_t i)
{
uint32_t tmp = cpu->R[REG_POS(i, 0)];
- if (REG_POS(i, 0) == 15)
- {
- //printf("ARM%c: BX using PC as operand\n", PROCNUM?'7':'9');
- //emu_halt();
- }
cpu->CPSR.bits.T = BIT0(tmp);
- cpu->R[15] = tmp & (0xFFFFFFFC|(cpu->CPSR.bits.T<<1));
+ cpu->R[15] = tmp & (0xFFFFFFFC | (cpu->CPSR.bits.T << 1));
cpu->next_instruction = cpu->R[15];
return 3;
}
-TEMPLATE static uint32_t FASTCALL OP_BLX_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BLX_REG(uint32_t i)
{
uint32_t tmp = cpu->R[REG_POS(i, 0)];
cpu->R[14] = cpu->next_instruction;
cpu->CPSR.bits.T = BIT0(tmp);
- cpu->R[15] = tmp & (0xFFFFFFFC|(cpu->CPSR.bits.T<<1));
+ cpu->R[15] = tmp & (0xFFFFFFFC | (cpu->CPSR.bits.T << 1));
cpu->next_instruction = cpu->R[15];
return 3;
}
-#define SIGNEXTEND_24(i) (((int32_t)i<<8)>>8)
-
-TEMPLATE static uint32_t FASTCALL OP_B(const uint32_t i)
+static inline uint32_t SIGNEXTEND_24(uint32_t i) { return static_cast<uint32_t>((static_cast<int32_t>(i) << 8) >> 8); }
+
+TEMPLATE static uint32_t FASTCALL OP_B(uint32_t i)
{
/*static const uint32_t mov_r12_r12 = 0xE1A0C00C;
const uint32_t last = _MMU_read32<PROCNUM,MMU_AT_DEBUG>(cpu->instruct_adr-4);
@@ -3245,39 +3082,39 @@
}*/
uint32_t off = SIGNEXTEND_24(i);
- if(CONDITION(i)==0xF)
+ if (CONDITION(i) == 0xF)
{
cpu->R[14] = cpu->next_instruction;
cpu->CPSR.bits.T = 1;
}
- cpu->R[15] += (off<<2);
- cpu->R[15] &= (0xFFFFFFFC|(cpu->CPSR.bits.T<<1));
+ cpu->R[15] += off << 2;
+ cpu->R[15] &= 0xFFFFFFFC | (cpu->CPSR.bits.T << 1);
cpu->next_instruction = cpu->R[15];
return 3;
}
-TEMPLATE static uint32_t FASTCALL OP_BL(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BL(uint32_t i)
{
uint32_t off = SIGNEXTEND_24(i);
- if(CONDITION(i)==0xF)
+ if (CONDITION(i) == 0xF)
{
cpu->CPSR.bits.T = 1;
cpu->R[15] += 2;
}
cpu->R[14] = cpu->next_instruction;
- cpu->R[15] += (off<<2);
- cpu->R[15] &= (0xFFFFFFFC|(cpu->CPSR.bits.T<<1));
+ cpu->R[15] += off << 2;
+ cpu->R[15] &= 0xFFFFFFFC | (cpu->CPSR.bits.T << 1);
cpu->next_instruction = cpu->R[15];
return 3;
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// CLZ
-//-----------------------------------------------------------------------------
-
-const uint8_t CLZ_TAB[16]=
+// -----------------------------------------------------------------------------
+
+const uint8_t CLZ_TAB[]=
{
0, // 0000
1, // 0001
@@ -3286,55 +3123,46 @@
4, 4, 4, 4, 4, 4, 4, 4 // 1XXX
};
-TEMPLATE static uint32_t FASTCALL OP_CLZ(const uint32_t i)
-{
- uint32_t Rm = cpu->R[REG_POS(i,0)];
- uint32_t pos;
-
- if(Rm==0)
- {
- cpu->R[REG_POS(i,12)]=32;
+TEMPLATE static uint32_t FASTCALL OP_CLZ(uint32_t i)
+{
+ uint32_t Rm = cpu->R[REG_POS(i, 0)];
+
+ if (!Rm)
+ {
+ cpu->R[REG_POS(i, 12)] = 32;
return 2;
}
- Rm |= (Rm >>1);
- Rm |= (Rm >>2);
- Rm |= (Rm >>4);
- Rm |= (Rm >>8);
- Rm |= (Rm >>16);
-
- pos =
- CLZ_TAB[Rm&0xF] +
- CLZ_TAB[(Rm>>4)&0xF] +
- CLZ_TAB[(Rm>>8)&0xF] +
- CLZ_TAB[(Rm>>12)&0xF] +
- CLZ_TAB[(Rm>>16)&0xF] +
- CLZ_TAB[(Rm>>20)&0xF] +
- CLZ_TAB[(Rm>>24)&0xF] +
- CLZ_TAB[(Rm>>28)&0xF];
-
- cpu->R[REG_POS(i,12)]=32 - pos;
+ Rm |= Rm >> 1;
+ Rm |= Rm >> 2;
+ Rm |= Rm >> 4;
+ Rm |= Rm >> 8;
+ Rm |= Rm >> 16;
+
+ uint32_t pos = CLZ_TAB[Rm & 0xF] + CLZ_TAB[(Rm >> 4) & 0xF] + CLZ_TAB[(Rm >> 8) & 0xF] + CLZ_TAB[(Rm >> 12) & 0xF] +
+ CLZ_TAB[(Rm >> 16) & 0xF] + CLZ_TAB[(Rm >> 20) & 0xF] + CLZ_TAB[(Rm >> 24) & 0xF] + CLZ_TAB[(Rm >> 28) & 0xF];
+
+ cpu->R[REG_POS(i, 12)] = 32 - pos;
return 2;
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// QADD / QDADD / QSUB / QDSUB
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_QADD(const uint32_t i)
-{
- uint32_t res = cpu->R[REG_POS(i,16)]+cpu->R[REG_POS(i,0)];
-
- //LOG("spe add\n");
- if(SIGNED_OVERFLOW(cpu->R[REG_POS(i,16)],cpu->R[REG_POS(i,0)], res))
- {
- cpu->CPSR.bits.Q=1;
- cpu->R[REG_POS(i,12)]=0x80000000-BIT31(res);
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_QADD(uint32_t i)
+{
+ uint32_t res = cpu->R[REG_POS(i, 16)] + cpu->R[REG_POS(i, 0)];
+
+ if (SIGNED_OVERFLOW(cpu->R[REG_POS(i, 16)], cpu->R[REG_POS(i, 0)], res))
+ {
+ cpu->CPSR.bits.Q = 1;
+ cpu->R[REG_POS(i, 12)] = 0x80000000 - BIT31(res);
return 2;
}
- cpu->R[REG_POS(i,12)]=res;
- if(REG_POS(i,12)==15)
+ cpu->R[REG_POS(i, 12)] = res;
+ if (REG_POS(i, 12) == 15)
{
cpu->R[15] &= 0xFFFFFFFC;
cpu->next_instruction = cpu->R[15];
@@ -3343,20 +3171,18 @@
return 2;
}
-TEMPLATE static uint32_t FASTCALL OP_QSUB(const uint32_t i)
-{
- uint32_t res = cpu->R[REG_POS(i,0)]-cpu->R[REG_POS(i,16)];
-
- //LOG("spe add\n");
- if(SIGNED_UNDERFLOW(cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,16)], res))
- {
- cpu->CPSR.bits.Q=1;
- cpu->R[REG_POS(i,12)]=0x80000000-BIT31(res);
+TEMPLATE static uint32_t FASTCALL OP_QSUB(uint32_t i)
+{
+ uint32_t res = cpu->R[REG_POS(i, 0)] - cpu->R[REG_POS(i, 16)];
+
+ if (SIGNED_UNDERFLOW(cpu->R[REG_POS(i, 0)], cpu->R[REG_POS(i, 16)], res))
+ {
+ cpu->CPSR.bits.Q = 1;
+ cpu->R[REG_POS(i, 12)] = 0x80000000 - BIT31(res);
return 2;
}
-
- cpu->R[REG_POS(i,12)]=res;
- if(REG_POS(i,12)==15)
+ cpu->R[REG_POS(i, 12)] = res;
+ if (REG_POS(i, 12) == 15)
{
cpu->R[15] &= 0xFFFFFFFC;
cpu->next_instruction = cpu->R[15];
@@ -3365,28 +3191,25 @@
return 2;
}
-TEMPLATE static uint32_t FASTCALL OP_QDADD(const uint32_t i)
-{
- uint32_t mul = cpu->R[REG_POS(i,16)]<<1;
- uint32_t res;
-
-
- //LOG("spe add\n");
- if(BIT31(cpu->R[REG_POS(i,16)])!=BIT31(mul))
- {
- cpu->CPSR.bits.Q=1;
- mul = 0x80000000-BIT31(mul);
- }
-
- res = mul + cpu->R[REG_POS(i,0)];
- if(SIGNED_OVERFLOW(cpu->R[REG_POS(i,0)],mul, res))
- {
- cpu->CPSR.bits.Q=1;
- cpu->R[REG_POS(i,12)]=0x80000000-BIT31(res);
+TEMPLATE static uint32_t FASTCALL OP_QDADD(uint32_t i)
+{
+ uint32_t mul = cpu->R[REG_POS(i, 16)] << 1;
+
+ if (BIT31(cpu->R[REG_POS(i, 16)]) != BIT31(mul))
+ {
+ cpu->CPSR.bits.Q = 1;
+ mul = 0x80000000 - BIT31(mul);
+ }
+
+ uint32_t res = mul + cpu->R[REG_POS(i, 0)];
+ if (SIGNED_OVERFLOW(cpu->R[REG_POS(i, 0)], mul, res))
+ {
+ cpu->CPSR.bits.Q = 1;
+ cpu->R[REG_POS(i, 12)] = 0x80000000 - BIT31(res);
return 2;
}
- cpu->R[REG_POS(i,12)]=res;
- if(REG_POS(i,12)==15)
+ cpu->R[REG_POS(i, 12)] = res;
+ if (REG_POS(i, 12) == 15)
{
cpu->R[15] &= 0xFFFFFFFC;
cpu->next_instruction = cpu->R[15];
@@ -3395,28 +3218,25 @@
return 2;
}
-TEMPLATE static uint32_t FASTCALL OP_QDSUB(const uint32_t i)
-{
- uint32_t mul = cpu->R[REG_POS(i,16)]<<1;
- uint32_t res;
-
-
- //LOG("spe add\n");
- if(BIT31(cpu->R[REG_POS(i,16)])!=BIT31(mul))
- {
- cpu->CPSR.bits.Q=1;
- mul = 0x80000000-BIT31(mul);
- }
-
- res = cpu->R[REG_POS(i,0)] - mul;
- if(SIGNED_UNDERFLOW(cpu->R[REG_POS(i,0)], mul, res))
- {
- cpu->CPSR.bits.Q=1;
- cpu->R[REG_POS(i,12)]=0x80000000-BIT31(res);
+TEMPLATE static uint32_t FASTCALL OP_QDSUB(uint32_t i)
+{
+ uint32_t mul = cpu->R[REG_POS(i, 16)] << 1;
+
+ if (BIT31(cpu->R[REG_POS(i, 16)]) != BIT31(mul))
+ {
+ cpu->CPSR.bits.Q = 1;
+ mul = 0x80000000 - BIT31(mul);
+ }
+
+ uint32_t res = cpu->R[REG_POS(i, 0)] - mul;
+ if (SIGNED_UNDERFLOW(cpu->R[REG_POS(i, 0)], mul, res))
+ {
+ cpu->CPSR.bits.Q = 1;
+ cpu->R[REG_POS(i, 12)] = 0x80000000 - BIT31(res);
return 2;
}
- cpu->R[REG_POS(i,12)]=res;
- if(REG_POS(i,12)==15)
+ cpu->R[REG_POS(i, 12)] = res;
+ if (REG_POS(i, 12) == 15)
{
cpu->R[15] &= 0xFFFFFFFC;
cpu->next_instruction = cpu->R[15];
@@ -3425,1405 +3245,1387 @@
return 2;
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// SMUL
-//-----------------------------------------------------------------------------
-
-#define HWORD(i) ((int32_t)(((int32_t)(i))>>16))
-#define LWORD(i) (int32_t)(((int32_t)((i)<<16))>>16)
-
-TEMPLATE static uint32_t FASTCALL OP_SMUL_B_B(const uint32_t i)
+// -----------------------------------------------------------------------------
+
+static inline int32_t HWORD(uint32_t i) { return static_cast<int32_t>(static_cast<int32_t>(i) >> 16); }
+static inline int32_t LWORD(uint32_t i) { return static_cast<int32_t>(static_cast<int32_t>(i << 16) >> 16); }
+
+TEMPLATE static uint32_t FASTCALL OP_SMUL_B_B(uint32_t i)
{
// checked
- //INFO("SMUL_B_B\n");
- cpu->R[REG_POS(i,16)] = (uint32_t)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)]));
+ cpu->R[REG_POS(i, 16)] = static_cast<uint32_t>(LWORD(cpu->R[REG_POS(i, 0)]) * LWORD(cpu->R[REG_POS(i, 8)]));
return 2;
}
-TEMPLATE static uint32_t FASTCALL OP_SMUL_B_T(const uint32_t i)
-{
- //INFO("SMUL_B_T\n");
- cpu->R[REG_POS(i,16)] = (uint32_t)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)]));
+TEMPLATE static uint32_t FASTCALL OP_SMUL_B_T(uint32_t i)
+{
+ cpu->R[REG_POS(i, 16)] = static_cast<uint32_t>(LWORD(cpu->R[REG_POS(i, 0)]) * HWORD(cpu->R[REG_POS(i, 8)]));
return 2;
}
-TEMPLATE static uint32_t FASTCALL OP_SMUL_T_B(const uint32_t i)
-{
- //INFO("SMUL_T_B\n");
- cpu->R[REG_POS(i,16)] = (uint32_t)(HWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)]));
+TEMPLATE static uint32_t FASTCALL OP_SMUL_T_B(uint32_t i)
+{
+ cpu->R[REG_POS(i, 16)] = static_cast<uint32_t>(HWORD(cpu->R[REG_POS(i, 0)]) * LWORD(cpu->R[REG_POS(i, 8)]));
return 2;
}
-TEMPLATE static uint32_t FASTCALL OP_SMUL_T_T(const uint32_t i)
-{
- //INFO("SMUL_T_T\n");
- cpu->R[REG_POS(i,16)] = (uint32_t)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)]));
+TEMPLATE static uint32_t FASTCALL OP_SMUL_T_T(uint32_t i)
+{
+ cpu->R[REG_POS(i, 16)] = static_cast<uint32_t>(HWORD(cpu->R[REG_POS(i, 0)]) * HWORD(cpu->R[REG_POS(i, 8)]));
return 2;
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// SMLA
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_SMLA_B_B(const uint32_t i)
-{
- uint32_t tmp = (uint32_t)((int16_t)cpu->R[REG_POS(i,0)]* (int16_t)cpu->R[REG_POS(i,8)]);
-
- cpu->R[REG_POS(i,16)] = tmp + cpu->R[REG_POS(i,12)];
-
- if (OverflowFromADD(cpu->R[REG_POS(i,16)], tmp, cpu->R[REG_POS(i,12)]))
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_SMLA_B_B(uint32_t i)
+{
+ uint32_t tmp = static_cast<uint32_t>(static_cast<int16_t>(cpu->R[REG_POS(i, 0)]) * static_cast<int16_t>(cpu->R[REG_POS(i, 8)]));
+
+ cpu->R[REG_POS(i, 16)] = tmp + cpu->R[REG_POS(i, 12)];
+
+ if (OverflowFromADD(cpu->R[REG_POS(i, 16)], tmp, cpu->R[REG_POS(i, 12)]))
cpu->CPSR.bits.Q = 1;
- //INFO("SMLABB %08X * %08X + %08X = %08X\n", (int16_t)cpu->R[REG_POS(i,0)], (int16_t)cpu->R[REG_POS(i,8)], cpu->R[REG_POS(i,12)], (int32_t)cpu->R[REG_POS(i,16)]);
return 2;
}
-TEMPLATE static uint32_t FASTCALL OP_SMLA_B_T(const uint32_t i)
-{
- uint32_t tmp = (uint32_t)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)]));
- uint32_t a = cpu->R[REG_POS(i,12)];
-
- //INFO("SMLABT %08X * %08X + %08X = %08X\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a);
- cpu->R[REG_POS(i,16)] = tmp + a;
-
- if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)]))
+TEMPLATE static uint32_t FASTCALL OP_SMLA_B_T(uint32_t i)
+{
+ uint32_t tmp = static_cast<uint32_t>(LWORD(cpu->R[REG_POS(i, 0)]) * HWORD(cpu->R[REG_POS(i, 8)]));
+ uint32_t a = cpu->R[REG_POS(i, 12)];
+
+ cpu->R[REG_POS(i, 16)] = tmp + a;
+
+ if (SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i, 16)]))
cpu->CPSR.bits.Q = 1;
return 2;
}
-TEMPLATE static uint32_t FASTCALL OP_SMLA_T_B(const uint32_t i)
-{
- uint32_t tmp = (uint32_t)(HWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)]));
- uint32_t a = cpu->R[REG_POS(i,12)];
-
- //INFO("SMLATB %08X * %08X + %08X = %08X\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a);
- cpu->R[REG_POS(i,16)] = tmp + a;
-
- if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)]))
+TEMPLATE static uint32_t FASTCALL OP_SMLA_T_B(uint32_t i)
+{
+ uint32_t tmp = static_cast<uint32_t>(HWORD(cpu->R[REG_POS(i, 0)]) * LWORD(cpu->R[REG_POS(i, 8)]));
+ uint32_t a = cpu->R[REG_POS(i, 12)];
+
+ cpu->R[REG_POS(i, 16)] = tmp + a;
+
+ if (SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i, 16)]))
cpu->CPSR.bits.Q = 1;
return 2;
}
-TEMPLATE static uint32_t FASTCALL OP_SMLA_T_T(const uint32_t i)
-{
- uint32_t tmp = (uint32_t)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)]));
- uint32_t a = cpu->R[REG_POS(i,12)];
-
- //INFO("SMLATT %08X * %08X + %08X = %08X\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a);
- cpu->R[REG_POS(i,16)] = tmp + a;
-
- if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)]))
+TEMPLATE static uint32_t FASTCALL OP_SMLA_T_T(uint32_t i)
+{
+ uint32_t tmp = static_cast<uint32_t>(HWORD(cpu->R[REG_POS(i, 0)]) * HWORD(cpu->R[REG_POS(i, 8)]));
+ uint32_t a = cpu->R[REG_POS(i, 12)];
+
+ cpu->R[REG_POS(i, 16)] = tmp + a;
+
+ if (SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i, 16)]))
cpu->CPSR.bits.Q = 1;
return 2;
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// SMLAL
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_SMLAL_B_B(const uint32_t i)
-{
- int64_t tmp = (int64_t)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)]));
- uint64_t res = (uint64_t)tmp + cpu->R[REG_POS(i,12)];
-
- //INFO("SMLALBB %08X * %08X + %08X%08X = %08X%08X\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + (res + ((tmp<0)*0xFFFFFFFF))), (int)(uint32_t) res);
-
- cpu->R[REG_POS(i,12)] = (uint32_t) res;
- cpu->R[REG_POS(i,16)] += static_cast<uint32_t>(res + ((tmp<0)*0xFFFFFFFF));
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_SMLAL_B_B(uint32_t i)
+{
+ int64_t tmp = static_cast<int64_t>(LWORD(cpu->R[REG_POS(i, 0)]) * LWORD(cpu->R[REG_POS(i, 8)]));
+ uint64_t res = static_cast<uint64_t>(tmp) + cpu->R[REG_POS(i, 12)];
+
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(res);
+ cpu->R[REG_POS(i, 16)] += static_cast<uint32_t>(res + ((tmp < 0) * 0xFFFFFFFF));
return 2;
}
-TEMPLATE static uint32_t FASTCALL OP_SMLAL_B_T(const uint32_t i)
-{
- int64_t tmp = (int64_t)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)]));
- uint64_t res = (uint64_t)tmp + cpu->R[REG_POS(i,12)];
-
- //INFO("SMLALBT %08X * %08X + %08X%08X = %08X%08X\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(uint32_t) res);
-
- cpu->R[REG_POS(i,12)] = (uint32_t) res;
- cpu->R[REG_POS(i,16)] += static_cast<uint32_t>(res + ((tmp<0)*0xFFFFFFFF));
+TEMPLATE static uint32_t FASTCALL OP_SMLAL_B_T(uint32_t i)
+{
+ int64_t tmp = static_cast<int64_t>(LWORD(cpu->R[REG_POS(i, 0)]) * HWORD(cpu->R[REG_POS(i, 8)]));
+ uint64_t res = static_cast<uint64_t>(tmp) + cpu->R[REG_POS(i, 12)];
+
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(res);
+ cpu->R[REG_POS(i, 16)] += static_cast<uint32_t>(res + ((tmp < 0) * 0xFFFFFFFF));
return 2;
}
-TEMPLATE static uint32_t FASTCALL OP_SMLAL_T_B(const uint32_t i)
-{
- int64_t tmp = (int64_t)(HWORD(cpu->R[REG_POS(i,0)])* (int64_t)LWORD(cpu->R[REG_POS(i,8)]));
- uint64_t res = (uint64_t)tmp + cpu->R[REG_POS(i,12)];
-
- //INFO("SMLALTB %08X * %08X + %08X%08X = %08X%08X\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(uint32_t) res);
-
- cpu->R[REG_POS(i,12)] = (uint32_t) res;
- cpu->R[REG_POS(i,16)] += static_cast<uint32_t>(res + ((tmp<0)*0xFFFFFFFF));
+TEMPLATE static uint32_t FASTCALL OP_SMLAL_T_B(uint32_t i)
+{
+ int64_t tmp = static_cast<int64_t>(HWORD(cpu->R[REG_POS(i, 0)]) * static_cast<int64_t>(LWORD(cpu->R[REG_POS(i, 8)])));
+ uint64_t res = static_cast<uint64_t>(tmp) + cpu->R[REG_POS(i, 12)];
+
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(res);
+ cpu->R[REG_POS(i, 16)] += static_cast<uint32_t>(res + ((tmp < 0) * 0xFFFFFFFF));
return 2;
}
-TEMPLATE static uint32_t FASTCALL OP_SMLAL_T_T(const uint32_t i)
-{
- int64_t tmp = (int64_t)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)]));
- uint64_t res = (uint64_t)tmp + cpu->R[REG_POS(i,12)];
-
- //INFO("SMLALTT %08X * %08X + %08X%08X = %08X%08X\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(uint32_t) res);
-
- cpu->R[REG_POS(i,12)] = (uint32_t) res;
- cpu->R[REG_POS(i,16)] += static_cast<uint32_t>(res + ((tmp<0)*0xFFFFFFFF));
+TEMPLATE static uint32_t FASTCALL OP_SMLAL_T_T(uint32_t i)
+{
+ int64_t tmp = static_cast<int64_t>(HWORD(cpu->R[REG_POS(i, 0)]) * HWORD(cpu->R[REG_POS(i, 8)]));
+ uint64_t res = static_cast<uint64_t>(tmp) + cpu->R[REG_POS(i, 12)];
+
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(res);
+ cpu->R[REG_POS(i, 16)] += static_cast<uint32_t>(res + ((tmp < 0) * 0xFFFFFFFF));
return 2;
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// SMULW
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_SMULW_B(const uint32_t i)
-{
- int64_t tmp = (int64_t)LWORD(cpu->R[REG_POS(i,8)]) * (int64_t)((int32_t)cpu->R[REG_POS(i,0)]);
-
- //INFO("SMULWB %08X * %08X = %08X\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], ((tmp>>16)&0xFFFFFFFF));
-
- cpu->R[REG_POS(i,16)] = ((tmp>>16)&0xFFFFFFFF);
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_SMULW_B(uint32_t i)
+{
+ int64_t tmp = static_cast<int64_t>(LWORD(cpu->R[REG_POS(i, 8)])) * static_cast<int64_t>(static_cast<int32_t>(cpu->R[REG_POS(i, 0)]));
+
+ cpu->R[REG_POS(i, 16)] = (tmp >> 16) & 0xFFFFFFFF;
return 2;
}
-TEMPLATE static uint32_t FASTCALL OP_SMULW_T(const uint32_t i)
-{
- int64_t tmp = (int64_t)HWORD(cpu->R[REG_POS(i,8)]) * (int64_t)((int32_t)cpu->R[REG_POS(i,0)]);
-
- //INFO("SMULWT %08X * %08X = %08X\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], ((tmp>>16)&0xFFFFFFFF));
-
- cpu->R[REG_POS(i,16)] = ((tmp>>16)&0xFFFFFFFF);
+TEMPLATE static uint32_t FASTCALL OP_SMULW_T(uint32_t i)
+{
+ int64_t tmp = static_cast<int64_t>(HWORD(cpu->R[REG_POS(i, 8)])) * static_cast<int64_t>(static_cast<int32_t>(cpu->R[REG_POS(i, 0)]));
+
+ cpu->R[REG_POS(i, 16)] = (tmp >> 16) & 0xFFFFFFFF;
return 2;
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// SMLAW
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_SMLAW_B(const uint32_t i)
-{
- int64_t tmp = (int64_t)LWORD(cpu->R[REG_POS(i,8)]) * (int64_t)((int32_t)cpu->R[REG_POS(i,0)]);
- uint32_t a = cpu->R[REG_POS(i,12)];
-
- //INFO("SMLAWB %08X * %08X + %08X = %08X\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, (tmp>>16) + a);
-
- tmp = (tmp>>16);
-
- cpu->R[REG_POS(i,16)] = static_cast<uint32_t>(tmp + a);
-
- if(SIGNED_OVERFLOW((uint32_t)tmp, a, cpu->R[REG_POS(i,16)]))
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_SMLAW_B(uint32_t i)
+{
+ int64_t tmp = static_cast<int64_t>(LWORD(cpu->R[REG_POS(i, 8)])) * static_cast<int64_t>(static_cast<int32_t>(cpu->R[REG_POS(i, 0)]));
+ uint32_t a = cpu->R[REG_POS(i, 12)];
+
+ tmp >>= 16;
+
+ cpu->R[REG_POS(i, 16)] = static_cast<uint32_t>(tmp + a);
+
+ if (SIGNED_OVERFLOW(static_cast<uint32_t>(tmp), a, cpu->R[REG_POS(i, 16)]))
cpu->CPSR.bits.Q = 1;
return 2;
}
-TEMPLATE static uint32_t FASTCALL OP_SMLAW_T(const uint32_t i)
-{
- int64_t tmp = (int64_t)HWORD(cpu->R[REG_POS(i,8)]) * (int64_t)((int32_t)cpu->R[REG_POS(i,0)]);
- uint32_t a = cpu->R[REG_POS(i,12)];
-
- //INFO("SMLAWT %08X * %08X + %08X = %08X\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, ((tmp>>16)&0xFFFFFFFF) + a);
-
- tmp = ((tmp>>16)&0xFFFFFFFF);
- cpu->R[REG_POS(i,16)] = static_cast<uint32_t>(tmp + a);
-
- if(SIGNED_OVERFLOW((uint32_t)tmp, a, cpu->R[REG_POS(i,16)]))
+TEMPLATE static uint32_t FASTCALL OP_SMLAW_T(uint32_t i)
+{
+ int64_t tmp = static_cast<int64_t>(HWORD(cpu->R[REG_POS(i, 8)])) * static_cast<int64_t>(static_cast<int32_t>(cpu->R[REG_POS(i, 0)]));
+ uint32_t a = cpu->R[REG_POS(i, 12)];
+
+ tmp = (tmp >> 16) & 0xFFFFFFFF;
+ cpu->R[REG_POS(i, 16)] = static_cast<uint32_t>(tmp + a);
+
+ if (SIGNED_OVERFLOW(static_cast<uint32_t>(tmp), a, cpu->R[REG_POS(i, 16)]))
cpu->CPSR.bits.Q = 1;
return 2;
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// LDR
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
#define OP_LDR(a, b) \
- cpu->R[REG_POS(i,12)] = ROR(READ32(cpu->mem_if->data, adr), 8*(adr&3)); \
- \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 12)] = ROR(READ32(cpu->mem_if->data, adr), 8 * (adr & 3)); \
+\
+ if (REG_POS(i, 12) == 15) \
{ \
- if (cpu->LDTBit) \
+ if (!PROCNUM) \
{ \
cpu->CPSR.bits.T = BIT0(cpu->R[15]); \
cpu->R[15] &= 0xFFFFFFFE; \
} \
else \
- { \
cpu->R[15] &= 0xFFFFFFFC; \
- } \
cpu->next_instruction = cpu->R[15]; \
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_READ>(b,adr); \
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_READ>(b, adr); \
} \
- \
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_READ>(a,adr);
+\
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_READ>(a, adr);
// PRE
#define OP_LDR_W(a, b) \
- cpu->R[REG_POS(i,16)] = adr;\
- cpu->R[REG_POS(i,12)] = ROR(READ32(cpu->mem_if->data, adr), 8*(adr&3)); \
- \
- if(REG_POS(i,12)==15) \
+ cpu->R[REG_POS(i, 16)] = adr;\
+ cpu->R[REG_POS(i, 12)] = ROR(READ32(cpu->mem_if->data, adr), 8 * (adr & 3)); \
+\
+ if (REG_POS(i, 12) == 15) \
{ \
- if (cpu->LDTBit) \
+ if (!PROCNUM) \
{ \
cpu->CPSR.bits.T = BIT0(cpu->R[15]); \
cpu->R[15] &= 0xFFFFFFFE; \
} \
else \
- { \
cpu->R[15] &= 0xFFFFFFFC; \
- } \
cpu->next_instruction = cpu->R[15]; \
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_READ>(b,adr); \
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_READ>(b, adr); \
} \
- \
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_READ>(a,adr);
+\
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_READ>(a, adr);
// POST
#define OP_LDR_W2(a, b, c) \
- uint32_t adr = cpu->R[REG_POS(i,16)]; \
- cpu->R[REG_POS(i,16)] = adr + c;\
- cpu->R[REG_POS(i,12)] = ROR(READ32(cpu->mem_if->data, adr), 8*(adr&3)); \
- \
- if(REG_POS(i,12)==15) \
+ uint32_t adr = cpu->R[REG_POS(i, 16)]; \
+ cpu->R[REG_POS(i, 16)] = adr + c;\
+ cpu->R[REG_POS(i, 12)] = ROR(READ32(cpu->mem_if->data, adr), 8 * (adr & 3)); \
+\
+ if (REG_POS(i, 12) == 15) \
{ \
- if (cpu->LDTBit) \
+ if (!PROCNUM) \
{ \
cpu->CPSR.bits.T = BIT0(cpu->R[15]); \
cpu->R[15] &= 0xFFFFFFFE; \
} \
else \
- { \
cpu->R[15] &= 0xFFFFFFFC; \
- } \
cpu->next_instruction = cpu->R[15]; \
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_READ>(b,adr); \
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_READ>(b, adr); \
} \
- \
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_READ>(a,adr);
-
-
-TEMPLATE static uint32_t FASTCALL OP_LDR_P_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
+\
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_READ>(a, adr);
+
+
+TEMPLATE static uint32_t FASTCALL OP_LDR_P_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + IMM_OFF_12;
OP_LDR(3, 5);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_M_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
+TEMPLATE static uint32_t FASTCALL OP_LDR_M_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - IMM_OFF_12;
OP_LDR(3, 5);
}
-TEMPLATE static uint32_t FASTCALL OP_LDREX(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,12)] = ROR(READ32(cpu->mem_if->data, adr), 8*(adr&3));
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDR_P_LSL_IMM_OFF(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_P_LSL_IMM_OFF(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
OP_LDR(3, 5);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_M_LSL_IMM_OFF(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_M_LSL_IMM_OFF(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
OP_LDR(3, 5);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_P_LSR_IMM_OFF(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_P_LSR_IMM_OFF(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
OP_LDR(3, 5);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_M_LSR_IMM_OFF(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_M_LSR_IMM_OFF(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
OP_LDR(3, 5);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_P_ASR_IMM_OFF(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_P_ASR_IMM_OFF(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
OP_LDR(3, 5);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_M_ASR_IMM_OFF(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_M_ASR_IMM_OFF(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
OP_LDR(3, 5);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_P_ROR_IMM_OFF(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_P_ROR_IMM_OFF(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
OP_LDR(3, 5);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_M_ROR_IMM_OFF(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_M_ROR_IMM_OFF(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
OP_LDR(3, 5);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_P_IMM_OFF_PREIND(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
+TEMPLATE static uint32_t FASTCALL OP_LDR_P_IMM_OFF_PREIND(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + IMM_OFF_12;
OP_LDR_W(3, 5);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_M_IMM_OFF_PREIND(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
+TEMPLATE static uint32_t FASTCALL OP_LDR_M_IMM_OFF_PREIND(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - IMM_OFF_12;
OP_LDR_W(3, 5);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_P_LSL_IMM_OFF_PREIND(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_P_LSL_IMM_OFF_PREIND(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
OP_LDR_W(3, 5);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_M_LSL_IMM_OFF_PREIND(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_M_LSL_IMM_OFF_PREIND(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
OP_LDR_W(3, 5);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_P_LSR_IMM_OFF_PREIND(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_P_LSR_IMM_OFF_PREIND(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
OP_LDR_W(3, 5);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_M_LSR_IMM_OFF_PREIND(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_M_LSR_IMM_OFF_PREIND(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
OP_LDR_W(3, 5);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_P_ASR_IMM_OFF_PREIND(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_P_ASR_IMM_OFF_PREIND(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
OP_LDR_W(3, 5);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_M_ASR_IMM_OFF_PREIND(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_M_ASR_IMM_OFF_PREIND(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
OP_LDR_W(3, 5);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_P_ROR_IMM_OFF_PREIND(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_P_ROR_IMM_OFF_PREIND(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
OP_LDR_W(3, 5);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_M_ROR_IMM_OFF_PREIND(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_M_ROR_IMM_OFF_PREIND(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
OP_LDR_W(3, 5);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_P_IMM_OFF_POSTIND(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_P_IMM_OFF_POSTIND(uint32_t i)
{
OP_LDR_W2(3, 5, IMM_OFF_12);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_M_IMM_OFF_POSTIND(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_M_IMM_OFF_POSTIND(uint32_t i)
{
OP_LDR_W2(3, 5, -IMM_OFF_12);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_P_LSL_IMM_OFF_POSTIND(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_P_LSL_IMM_OFF_POSTIND(uint32_t i)
{
LSL_IMM;
OP_LDR_W2(3, 5, shift_op);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_M_LSL_IMM_OFF_POSTIND(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_M_LSL_IMM_OFF_POSTIND(uint32_t i)
{
LSL_IMM;
OP_LDR_W2(3, 5, -shift_op);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_P_LSR_IMM_OFF_POSTIND(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_P_LSR_IMM_OFF_POSTIND(uint32_t i)
{
LSR_IMM;
OP_LDR_W2(3, 5, shift_op);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_M_LSR_IMM_OFF_POSTIND(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_M_LSR_IMM_OFF_POSTIND(uint32_t i)
{
LSR_IMM;
OP_LDR_W2(3, 5, -shift_op);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_P_ASR_IMM_OFF_POSTIND(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_P_ASR_IMM_OFF_POSTIND(uint32_t i)
{
ASR_IMM;
OP_LDR_W2(3, 5, shift_op);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_M_ASR_IMM_OFF_POSTIND(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_M_ASR_IMM_OFF_POSTIND(uint32_t i)
{
ASR_IMM;
OP_LDR_W2(3, 5, -shift_op);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_P_ROR_IMM_OFF_POSTIND(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_P_ROR_IMM_OFF_POSTIND(uint32_t i)
{
ROR_IMM;
OP_LDR_W2(3, 5, shift_op);
}
-TEMPLATE static uint32_t FASTCALL OP_LDR_M_ROR_IMM_OFF_POSTIND(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDR_M_ROR_IMM_OFF_POSTIND(uint32_t i)
{
ROR_IMM;
OP_LDR_W2(3, 5, -shift_op);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
+// LDREX
+// -----------------------------------------------------------------------------
+TEMPLATE static uint32_t FASTCALL OP_LDREX(uint32_t i)
+{
+ printf("LDREX\n");
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 12)] = ROR(READ32(cpu->mem_if->data, adr), 8 * (adr & 3));
+ return MMU_aluMemAccessCycles<PROCNUM,32, MMU_AD_READ>(3, adr);
+}
+
+// -----------------------------------------------------------------------------
// LDRB
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_P_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_M_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_P_LSL_IMM_OFF(const uint32_t i)
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_P_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + IMM_OFF_12;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_M_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - IMM_OFF_12;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_P_LSL_IMM_OFF(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_M_LSL_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_M_LSL_IMM_OFF(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);;
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_P_LSR_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_P_LSR_IMM_OFF(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- cpu->R[REG_POS(i,12)] = READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_M_LSR_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ cpu->R[REG_POS(i, 12)] = READ8(cpu->mem_if->data, adr);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_M_LSR_IMM_OFF(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_P_ASR_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_P_ASR_IMM_OFF(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_M_ASR_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_M_ASR_IMM_OFF(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_P_ROR_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_P_ROR_IMM_OFF(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_M_ROR_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_M_ROR_IMM_OFF(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_P_IMM_OFF_PREIND(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_M_IMM_OFF_PREIND(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);;
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_P_LSL_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_P_IMM_OFF_PREIND(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + IMM_OFF_12;
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_M_IMM_OFF_PREIND(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - IMM_OFF_12;
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_P_LSL_IMM_OFF_PREIND(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_M_LSL_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_M_LSL_IMM_OFF_PREIND(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_P_LSR_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_P_LSR_IMM_OFF_PREIND(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_M_LSR_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_M_LSR_IMM_OFF_PREIND(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_P_ASR_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_P_ASR_IMM_OFF_PREIND(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_M_ASR_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_M_ASR_IMM_OFF_PREIND(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_P_ROR_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_P_ROR_IMM_OFF_PREIND(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_M_ROR_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_M_ROR_IMM_OFF_PREIND(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_P_IMM_OFF_POSTIND(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_M_IMM_OFF_POSTIND(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_P_LSL_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_P_IMM_OFF_POSTIND(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] = adr + IMM_OFF_12;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_M_IMM_OFF_POSTIND(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] = adr - IMM_OFF_12;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_P_LSL_IMM_OFF_POSTIND(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] = adr + shift_op;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_M_LSL_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] = adr + shift_op;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_M_LSL_IMM_OFF_POSTIND(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] = adr - shift_op;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_P_LSR_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] = adr - shift_op;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_P_LSR_IMM_OFF_POSTIND(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] = adr + shift_op;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_M_LSR_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] = adr + shift_op;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_M_LSR_IMM_OFF_POSTIND(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] = adr - shift_op;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_P_ASR_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] = adr - shift_op;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_P_ASR_IMM_OFF_POSTIND(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] = adr + shift_op;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_M_ASR_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] = adr + shift_op;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_M_ASR_IMM_OFF_POSTIND(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] = adr - shift_op;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_P_ROR_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] = adr - shift_op;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_P_ROR_IMM_OFF_POSTIND(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] = adr + shift_op;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_M_ROR_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] = adr + shift_op;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_M_ROR_IMM_OFF_POSTIND(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- cpu->R[REG_POS(i,16)] = adr - shift_op;
- cpu->R[REG_POS(i,12)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
-}
-
-//-----------------------------------------------------------------------------
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ cpu->R[REG_POS(i, 16)] = adr - shift_op;
+ cpu->R[REG_POS(i, 12)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+// -----------------------------------------------------------------------------
// STR
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_STR_P_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_M_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STREX(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,0)]);
- cpu->R[REG_POS(i,12)] = 0;
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_P_LSL_IMM_OFF(const uint32_t i)
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_STR_P_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + IMM_OFF_12;
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_M_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - IMM_OFF_12;
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_P_LSL_IMM_OFF(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_M_LSL_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_M_LSL_IMM_OFF(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_P_LSR_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_P_LSR_IMM_OFF(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_M_LSR_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_M_LSR_IMM_OFF(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_P_ASR_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_P_ASR_IMM_OFF(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_M_ASR_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_M_ASR_IMM_OFF(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_P_ROR_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_P_ROR_IMM_OFF(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_M_ROR_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_M_ROR_IMM_OFF(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_P_IMM_OFF_PREIND(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_M_IMM_OFF_PREIND(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_P_LSL_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_P_IMM_OFF_PREIND(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + IMM_OFF_12;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_M_IMM_OFF_PREIND(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - IMM_OFF_12;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_P_LSL_IMM_OFF_PREIND(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_M_LSL_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_M_LSL_IMM_OFF_PREIND(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_P_LSR_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_P_LSR_IMM_OFF_PREIND(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_M_LSR_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_M_LSR_IMM_OFF_PREIND(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_P_ASR_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_P_ASR_IMM_OFF_PREIND(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_M_ASR_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_M_ASR_IMM_OFF_PREIND(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_P_ROR_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_P_ROR_IMM_OFF_PREIND(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_M_ROR_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_M_ROR_IMM_OFF_PREIND(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_P_IMM_OFF_POSTIND(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12;
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_M_IMM_OFF_POSTIND(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12;
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_P_LSL_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_P_IMM_OFF_POSTIND(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+ cpu->R[REG_POS(i, 16)] = adr + IMM_OFF_12;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_M_IMM_OFF_POSTIND(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+ cpu->R[REG_POS(i, 16)] = adr - IMM_OFF_12;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_P_LSL_IMM_OFF_POSTIND(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] = adr + shift_op;
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_M_LSL_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+ cpu->R[REG_POS(i, 16)] = adr + shift_op;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_M_LSL_IMM_OFF_POSTIND(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] = adr - shift_op;
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_P_LSR_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+ cpu->R[REG_POS(i, 16)] = adr - shift_op;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_P_LSR_IMM_OFF_POSTIND(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] = adr + shift_op;
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_M_LSR_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+ cpu->R[REG_POS(i, 16)] = adr + shift_op;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_M_LSR_IMM_OFF_POSTIND(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] = adr - shift_op;
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_P_ASR_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+ cpu->R[REG_POS(i, 16)] = adr - shift_op;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_P_ASR_IMM_OFF_POSTIND(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] = adr + shift_op;
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_M_ASR_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+ cpu->R[REG_POS(i, 16)] = adr + shift_op;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_M_ASR_IMM_OFF_POSTIND(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] = adr - shift_op;
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_P_ROR_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+ cpu->R[REG_POS(i, 16)] = adr - shift_op;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_P_ROR_IMM_OFF_POSTIND(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] = adr + shift_op;
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_M_ROR_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+ cpu->R[REG_POS(i, 16)] = adr + shift_op;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_M_ROR_IMM_OFF_POSTIND(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] = adr - shift_op;
-
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
-}
-
-//-----------------------------------------------------------------------------
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 12)]);
+ cpu->R[REG_POS(i, 16)] = adr - shift_op;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+// -----------------------------------------------------------------------------
+// STREX
+// -----------------------------------------------------------------------------
+TEMPLATE static uint32_t FASTCALL OP_STREX(uint32_t i)
+{
+ printf("STREX\n");
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i, 0)]);
+ cpu->R[REG_POS(i, 12)] = 0;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+// -----------------------------------------------------------------------------
// STRB
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_P_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_M_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_P_LSL_IMM_OFF(const uint32_t i)
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_P_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + IMM_OFF_12;
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_M_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - IMM_OFF_12;
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_P_LSL_IMM_OFF(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_M_LSL_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_M_LSL_IMM_OFF(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_P_LSR_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_P_LSR_IMM_OFF(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_M_LSR_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_M_LSR_IMM_OFF(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_P_ASR_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_P_ASR_IMM_OFF(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_M_ASR_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_M_ASR_IMM_OFF(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_P_ROR_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_P_ROR_IMM_OFF(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_M_ROR_IMM_OFF(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_M_ROR_IMM_OFF(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_P_IMM_OFF_PREIND(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_M_IMM_OFF_PREIND(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_P_LSL_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_P_IMM_OFF_PREIND(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + IMM_OFF_12;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_M_IMM_OFF_PREIND(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - IMM_OFF_12;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_P_LSL_IMM_OFF_PREIND(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_M_LSL_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_M_LSL_IMM_OFF_PREIND(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_P_LSR_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_P_LSR_IMM_OFF_PREIND(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_M_LSR_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_M_LSR_IMM_OFF_PREIND(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_P_ASR_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_P_ASR_IMM_OFF_PREIND(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_M_ASR_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_M_ASR_IMM_OFF_PREIND(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_P_ROR_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_P_ROR_IMM_OFF_PREIND(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] + shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_M_ROR_IMM_OFF_PREIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] + shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_M_ROR_IMM_OFF_PREIND(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)] - shift_op;
- cpu->R[REG_POS(i,16)] = adr;
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_P_IMM_OFF_POSTIND(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12;
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_M_IMM_OFF_POSTIND(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12;
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_P_LSL_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)] - shift_op;
+ cpu->R[REG_POS(i, 16)] = adr;
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_P_IMM_OFF_POSTIND(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+ cpu->R[REG_POS(i, 16)] = adr + IMM_OFF_12;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_M_IMM_OFF_POSTIND(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+ cpu->R[REG_POS(i, 16)] = adr - IMM_OFF_12;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_P_LSL_IMM_OFF_POSTIND(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] = adr + shift_op;
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_M_LSL_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+ cpu->R[REG_POS(i, 16)] = adr + shift_op;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_M_LSL_IMM_OFF_POSTIND(uint32_t i)
{
LSL_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] = adr - shift_op;
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_P_LSR_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+ cpu->R[REG_POS(i, 16)] = adr - shift_op;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_P_LSR_IMM_OFF_POSTIND(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] = adr + shift_op;
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_M_LSR_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+ cpu->R[REG_POS(i, 16)] = adr + shift_op;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_M_LSR_IMM_OFF_POSTIND(uint32_t i)
{
LSR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] = adr - shift_op;
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_P_ASR_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+ cpu->R[REG_POS(i, 16)] = adr - shift_op;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_P_ASR_IMM_OFF_POSTIND(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] = adr + shift_op;
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_M_ASR_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+ cpu->R[REG_POS(i, 16)] = adr + shift_op;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_M_ASR_IMM_OFF_POSTIND(uint32_t i)
{
ASR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] = adr - shift_op;
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_P_ROR_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+ cpu->R[REG_POS(i, 16)] = adr - shift_op;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_P_ROR_IMM_OFF_POSTIND(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] = adr + shift_op;
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(const uint32_t i)
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+ cpu->R[REG_POS(i, 16)] = adr + shift_op;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(uint32_t i)
{
ROR_IMM;
- uint32_t adr = cpu->R[REG_POS(i,16)];
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_POS(i,12)]);
- cpu->R[REG_POS(i,16)] = adr - shift_op;
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
-}
-
-//-----------------------------------------------------------------------------
+ uint32_t adr = cpu->R[REG_POS(i, 16)];
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_POS(i, 12)]));
+ cpu->R[REG_POS(i, 16)] = adr - shift_op;
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+// -----------------------------------------------------------------------------
// LDMIA / LDMIB / LDMDA / LDMDB
-//-----------------------------------------------------------------------------
-
-#define OP_L_IA(reg, adr) if(BIT##reg(i)) \
+// -----------------------------------------------------------------------------
+
+#define OP_L_IA(reg, adr) \
+ if (BIT##reg(i)) \
{ \
registres[reg] = READ32(cpu->mem_if->data, start); \
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start); \
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(start); \
adr += 4; \
}
-#define OP_L_IB(reg, adr) if(BIT##reg(i)) \
+#define OP_L_IB(reg, adr) \
+ if (BIT##reg(i)) \
{ \
adr += 4; \
registres[reg] = READ32(cpu->mem_if->data, start); \
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start); \
- }
-
-#define OP_L_DA(reg, adr) if(BIT##reg(i)) \
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(start); \
+ }
+
+#define OP_L_DA(reg, adr) \
+ if (BIT##reg(i)) \
{ \
registres[reg] = READ32(cpu->mem_if->data, start); \
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start); \
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(start); \
adr -= 4; \
}
-#define OP_L_DB(reg, adr) if(BIT##reg(i)) \
+#define OP_L_DB(reg, adr) \
+ if (BIT##reg(i)) \
{ \
adr -= 4; \
registres[reg] = READ32(cpu->mem_if->data, start); \
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start); \
- }
-
-TEMPLATE static uint32_t FASTCALL OP_LDMIA(const uint32_t i)
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(start); \
+ }
+
+TEMPLATE static uint32_t FASTCALL OP_LDMIA(uint32_t i)
{
uint32_t c = 0;
- uint32_t start = cpu->R[REG_POS(i,16)];
-
- uint32_t * registres = cpu->R;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+
+ uint32_t *registres = cpu->R;
OP_L_IA(0, start);
OP_L_IA(1, start);
@@ -4841,7 +4643,7 @@
OP_L_IA(13, start);
OP_L_IA(14, start);
- if(BIT15(i))
+ if (BIT15(i))
{
uint32_t tmp = READ32(cpu->mem_if->data, start);
// TODO
@@ -4858,7 +4660,7 @@
// T Bit = value[0]
//else
// pc = value AND 0xFFFFFFFC
- if (cpu->LDTBit)
+ if (!PROCNUM)
{
cpu->CPSR.bits.T = BIT0(tmp);
registres[15] = tmp & 0xFFFFFFFE;
@@ -4868,18 +4670,18 @@
//start += 4;
cpu->next_instruction = registres[15];
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(start);
}
return MMU_aluMemCycles<PROCNUM>(2, c);
}
-TEMPLATE static uint32_t FASTCALL OP_LDMIB(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDMIB(uint32_t i)
{
uint32_t c = 0;
- uint32_t start = cpu->R[REG_POS(i,16)];
-
- uint32_t * registres = cpu->R;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+
+ uint32_t *registres = cpu->R;
OP_L_IB(0, start);
OP_L_IB(1, start);
@@ -4897,12 +4699,12 @@
OP_L_IB(13, start);
OP_L_IB(14, start);
- if(BIT15(i))
+ if (BIT15(i))
{
start += 4;
c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start);
uint32_t tmp = READ32(cpu->mem_if->data, start);
- if (cpu->LDTBit)
+ if (!PROCNUM)
{
cpu->CPSR.bits.T = BIT0(tmp);
registres[15] = tmp & 0xFFFFFFFE;
@@ -4916,24 +4718,24 @@
return MMU_aluMemCycles<PROCNUM>(2, c);
}
-TEMPLATE static uint32_t FASTCALL OP_LDMDA(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDMDA(uint32_t i)
{
uint32_t c = 0;
- uint32_t start = cpu->R[REG_POS(i,16)];
-
- uint32_t * registres = cpu->R;
-
- if(BIT15(i))
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+
+ uint32_t *registres = cpu->R;
+
+ if (BIT15(i))
{
uint32_t tmp = READ32(cpu->mem_if->data, start);
- if (cpu->LDTBit)
+ if (!PROCNUM)
{
cpu->CPSR.bits.T = BIT0(tmp);
registres[15] = tmp & 0xFFFFFFFE;
}
else
registres[15] = tmp & 0xFFFFFFFC;
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(start);
start -= 4;
cpu->next_instruction = registres[15];
}
@@ -4957,18 +4759,18 @@
return MMU_aluMemCycles<PROCNUM>(2, c);
}
-TEMPLATE static uint32_t FASTCALL OP_LDMDB(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDMDB(uint32_t i)
{
uint32_t c = 0;
- uint32_t start = cpu->R[REG_POS(i,16)];
-
- uint32_t * registres = cpu->R;
-
- if(BIT15(i))
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+
+ uint32_t *registres = cpu->R;
+
+ if (BIT15(i))
{
start -= 4;
uint32_t tmp = READ32(cpu->mem_if->data, start);
- if (cpu->LDTBit)
+ if (!PROCNUM)
{
cpu->CPSR.bits.T = BIT0(tmp);
registres[15] = tmp & 0xFFFFFFFE;
@@ -4976,7 +4778,7 @@
else
registres[15] = tmp & 0xFFFFFFFC;
cpu->next_instruction = registres[15];
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(start);
}
OP_L_DB(14, start);
@@ -4998,13 +4800,13 @@
return MMU_aluMemCycles<PROCNUM>(2, c);
}
-TEMPLATE static uint32_t FASTCALL OP_LDMIA_W(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDMIA_W(uint32_t i)
{
uint32_t c = 0;
- uint32_t start = cpu->R[REG_POS(i,16)];
- uint32_t bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF;
-
- uint32_t * registres = cpu->R;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+ uint32_t bitList = (~((2 << REG_POS(i, 16)) - 1)) & 0xFFFF;
+
+ uint32_t *registres = cpu->R;
OP_L_IA(0, start);
OP_L_IA(1, start);
@@ -5022,38 +4824,39 @@
OP_L_IA(13, start);
OP_L_IA(14, start);
- if(BIT15(i))
+ if (BIT15(i))
{
uint32_t tmp = READ32(cpu->mem_if->data, start);
- if (cpu->LDTBit)
+ if (!PROCNUM)
{
cpu->CPSR.bits.T = BIT0(tmp);
registres[15] = tmp & 0xFFFFFFFE;
}
else
registres[15] = tmp & 0xFFFFFFFC;
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(start);
start += 4;
cpu->next_instruction = registres[15];
}
- if(i & (1 << REG_POS(i,16))) {
- if(i & bitList)
- cpu->R[REG_POS(i,16)] = start;
+ if (i & (1 << REG_POS(i, 16)))
+ {
+ if (i & bitList)
+ cpu->R[REG_POS(i, 16)] = start;
}
else
- cpu->R[REG_POS(i,16)] = start;
-
- return MMU_aluMemCycles<PROCNUM>(2, c);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDMIB_W(const uint32_t i)
+ cpu->R[REG_POS(i, 16)] = start;
+
+ return MMU_aluMemCycles<PROCNUM>(BIT15(i) ? 4 : 2, c);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDMIB_W(uint32_t i)
{
uint32_t c = 0;
- uint32_t start = cpu->R[REG_POS(i,16)];
- uint32_t bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF;
-
- uint32_t * registres = cpu->R;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+ uint32_t bitList = (~((2 << REG_POS(i, 16)) - 1)) & 0xFFFF;
+
+ uint32_t *registres = cpu->R;
OP_L_IB(0, start);
OP_L_IB(1, start);
@@ -5071,13 +4874,13 @@
OP_L_IB(13, start);
OP_L_IB(14, start);
- if(BIT15(i))
+ if (BIT15(i))
{
uint32_t tmp;
start += 4;
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(start);
tmp = READ32(cpu->mem_if->data, start);
- if (cpu->LDTBit)
+ if (!PROCNUM)
{
cpu->CPSR.bits.T = BIT0(tmp);
registres[15] = tmp & 0xFFFFFFFE;
@@ -5087,38 +4890,36 @@
cpu->next_instruction = registres[15];
}
- if(i & (1 << REG_POS(i,16))) {
- if(i & bitList)
- cpu->R[REG_POS(i,16)] = start;
+ if (i & (1 << REG_POS(i, 16)))
+ {
+ if (i & bitList)
+ cpu->R[REG_POS(i, 16)] = start;
}
else
- cpu->R[REG_POS(i,16)] = start;
-
- if(BIT15(i))
- return MMU_aluMemCycles<PROCNUM>(4, c);
- else
- return MMU_aluMemCycles<PROCNUM>(2, c);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDMDA_W(const uint32_t i)
+ cpu->R[REG_POS(i, 16)] = start;
+
+ return MMU_aluMemCycles<PROCNUM>(BIT15(i) ? 4 : 2, c);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDMDA_W(uint32_t i)
{
uint32_t c = 0;
- uint32_t start = cpu->R[REG_POS(i,16)];
- uint32_t bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF;
-
- uint32_t * registres = cpu->R;
-
- if(BIT15(i))
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+ uint32_t bitList = (~((2 << REG_POS(i, 16)) - 1)) & 0xFFFF;
+
+ uint32_t *registres = cpu->R;
+
+ if (BIT15(i))
{
uint32_t tmp = READ32(cpu->mem_if->data, start);
- if (cpu->LDTBit)
+ if (!PROCNUM)
{
cpu->CPSR.bits.T = BIT0(tmp);
registres[15] = tmp & 0xFFFFFFFE;
}
else
registres[15] = tmp & 0xFFFFFFFC;
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(start);
start -= 4;
cpu->next_instruction = registres[15];
}
@@ -5139,29 +4940,31 @@
OP_L_DA(1, start);
OP_L_DA(0, start);
- if(i & (1 << REG_POS(i,16))) {
- if(i & bitList)
- cpu->R[REG_POS(i,16)] = start;
+ if (i & (1 << REG_POS(i, 16)))
+ {
+ if (i & bitList)
+ cpu->R[REG_POS(i, 16)] = start;
}
else
- cpu->R[REG_POS(i,16)] = start;
+ cpu->R[REG_POS(i, 16)] = start;
return MMU_aluMemCycles<PROCNUM>(2, c);
}
-TEMPLATE static uint32_t FASTCALL OP_LDMDB_W(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDMDB_W(uint32_t i)
{
uint32_t c = 0;
- uint32_t start = cpu->R[REG_POS(i,16)];
- uint32_t bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF;
- uint32_t * registres = cpu->R;
-
- if(BIT15(i))
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+ uint32_t bitList = (~((2 << REG_POS(i, 16)) - 1)) & 0xFFFF;
+
+ uint32_t *registres = cpu->R;
+
+ if (BIT15(i))
{
uint32_t tmp;
start -= 4;
tmp = READ32(cpu->mem_if->data, start);
- if (cpu->LDTBit)
+ if (!PROCNUM)
{
cpu->CPSR.bits.T = BIT0(tmp);
registres[15] = tmp & 0xFFFFFFFE;
@@ -5169,7 +4972,7 @@
else
registres[15] = tmp & 0xFFFFFFFC;
cpu->next_instruction = registres[15];
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(start);
}
OP_L_DB(14, start);
@@ -5188,32 +4991,34 @@
OP_L_DB(1, start);
OP_L_DB(0, start);
- if(i & (1 << REG_POS(i,16))) {
- if(i & bitList)
- cpu->R[REG_POS(i,16)] = start;
+ if (i & (1 << REG_POS(i, 16)))
+ {
+ if (i & bitList)
+ cpu->R[REG_POS(i, 16)] = start;
}
else
- cpu->R[REG_POS(i,16)] = start;
+ cpu->R[REG_POS(i, 16)] = start;
return MMU_aluMemCycles<PROCNUM>(2, c);
}
-TEMPLATE static uint32_t FASTCALL OP_LDMIA2(const uint32_t i)
-{
+TEMPLATE static uint32_t FASTCALL OP_LDMIA2(uint32_t i)
+{
+ uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+
uint32_t oldmode = 0;
-
- uint32_t c = 0;
-
- uint32_t start = cpu->R[REG_POS(i,16)];
- uint32_t * registres;
-
- if(BIT15(i)==0)
- {
- if((cpu->CPSR.bits.mode==USR)||(cpu->CPSR.bits.mode==SYS)) { printf("ERROR1\n"); return 1; }
+ if (!BIT15(i))
+ {
+ if (cpu->CPSR.bits.mode == USR || cpu->CPSR.bits.mode == SYS)
+ {
+ printf("ERROR1\n");
+ return 1;
+ }
oldmode = armcpu_switchMode(cpu, SYS);
}
- registres = cpu->R;
+ uint32_t *registres = cpu->R;
OP_L_IA(0, start);
OP_L_IA(1, start);
@@ -5231,44 +5036,41 @@
OP_L_IA(13, start);
OP_L_IA(14, start);
- if(BIT15(i) == 0)
- {
+ if (!BIT15(i))
armcpu_switchMode(cpu, static_cast<uint8_t>(oldmode));
- }
else
{
-
uint32_t tmp = READ32(cpu->mem_if->data, start);
Status_Reg SPSR;
- cpu->R[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
+ cpu->R[15] = tmp & (0XFFFFFFFC | (BIT0(tmp) << 1));
SPSR = cpu->SPSR;
armcpu_switchMode(cpu, SPSR.bits.mode);
- cpu->CPSR=SPSR;
+ cpu->CPSR = SPSR;
cpu->changeCPSR();
//start += 4;
cpu->next_instruction = cpu->R[15];
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(start);
}
return MMU_aluMemCycles<PROCNUM>(2, c);
}
-TEMPLATE static uint32_t FASTCALL OP_LDMIB2(const uint32_t i)
-{
+TEMPLATE static uint32_t FASTCALL OP_LDMIB2(uint32_t i)
+{
+ uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+
uint32_t oldmode = 0;
- uint32_t c = 0;
-
- uint32_t start = cpu->R[REG_POS(i,16)];
- uint32_t * registres;
-
- //UNTESTEDOPCODELOG("Untested opcode: OP_LDMIB2 \n");
-
- if(BIT15(i)==0)
- {
- if((cpu->CPSR.bits.mode==USR)||(cpu->CPSR.bits.mode==SYS)) { printf("ERROR1\n"); return 1; }
+ if (!BIT15(i))
+ {
+ if (cpu->CPSR.bits.mode == USR || cpu->CPSR.bits.mode == SYS)
+ {
+ printf("ERROR1\n");
+ return 1;
+ }
oldmode = armcpu_switchMode(cpu, SYS);
}
- registres = cpu->R;
+ uint32_t *registres = cpu->R;
OP_L_IB(0, start);
OP_L_IB(1, start);
@@ -5286,53 +5088,49 @@
OP_L_IB(13, start);
OP_L_IB(14, start);
- if(BIT15(i) == 0)
- {
+ if (!BIT15(i))
armcpu_switchMode(cpu, static_cast<uint8_t>(oldmode));
- }
else
{
- uint32_t tmp;
Status_Reg SPSR;
start += 4;
- tmp = READ32(cpu->mem_if->data, start);
- registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
+ uint32_t tmp = READ32(cpu->mem_if->data, start);
+ registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp) << 1));
SPSR = cpu->SPSR;
armcpu_switchMode(cpu, SPSR.bits.mode);
- cpu->CPSR=SPSR;
+ cpu->CPSR = SPSR;
cpu->changeCPSR();
cpu->next_instruction = registres[15];
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(start);
}
return MMU_aluMemCycles<PROCNUM>(2, c);
}
-TEMPLATE static uint32_t FASTCALL OP_LDMDA2(const uint32_t i)
-{
+TEMPLATE static uint32_t FASTCALL OP_LDMDA2(uint32_t i)
+{
+ uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i,16)];
uint32_t oldmode = 0;
- uint32_t c = 0;
- uint32_t * registres;
-
- uint32_t start = cpu->R[REG_POS(i,16)];
-
- //UNTESTEDOPCODELOG("Untested opcode: OP_LDMDA2 \n");
-
- if(BIT15(i)==0)
- {
- if((cpu->CPSR.bits.mode==USR)||(cpu->CPSR.bits.mode==SYS)) { printf("ERROR1\n"); return 1; }
+ if (!BIT15(i))
+ {
+ if (cpu->CPSR.bits.mode == USR || cpu->CPSR.bits.mode == SYS)
+ {
+ printf("ERROR1\n");
+ return 1;
+ }
oldmode = armcpu_switchMode(cpu, SYS);
}
- registres = cpu->R;
-
- if(BIT15(i))
+ uint32_t *registres = cpu->R;
+
+ if (BIT15(i))
{
uint32_t tmp = READ32(cpu->mem_if->data, start);
- registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
+ registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp) << 1));
cpu->CPSR = cpu->SPSR;
cpu->changeCPSR();
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(start);
start -= 4;
cpu->next_instruction = registres[15];
}
@@ -5353,46 +5151,47 @@
OP_L_DA(1, start);
OP_L_DA(0, start);
- if(BIT15(i)==0)
- {
+ if (!BIT15(i))
armcpu_switchMode(cpu, static_cast<uint8_t>(oldmode));
- }
else
{
Status_Reg SPSR = cpu->SPSR;
armcpu_switchMode(cpu, SPSR.bits.mode);
- cpu->CPSR=SPSR;
+ cpu->CPSR = SPSR;
cpu->changeCPSR();
}
return MMU_aluMemCycles<PROCNUM>(2, c);
}
-TEMPLATE static uint32_t FASTCALL OP_LDMDB2(const uint32_t i)
-{
+TEMPLATE static uint32_t FASTCALL OP_LDMDB2(uint32_t i)
+{
+ uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i,16)];
+
uint32_t oldmode = 0;
- uint32_t c = 0;
- uint32_t * registres;
-
- uint32_t start = cpu->R[REG_POS(i,16)];
- if(BIT15(i)==0)
- {
- if((cpu->CPSR.bits.mode==USR)||(cpu->CPSR.bits.mode==SYS)) { printf("ERROR1\n"); return 1; }
+ if (!BIT15(i))
+ {
+ if (cpu->CPSR.bits.mode == USR || cpu->CPSR.bits.mode == SYS)
+ {
+ printf("ERROR1\n");
+ return 1;
+ }
oldmode = armcpu_switchMode(cpu, SYS);
}
- registres = cpu->R;
-
- if(BIT15(i))
+ uint32_t *registres = cpu->R;
+
+ if (BIT15(i))
{
uint32_t tmp;
start -= 4;
tmp = READ32(cpu->mem_if->data, start);
- registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
+ registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp) << 1));
cpu->CPSR = cpu->SPSR;
cpu->changeCPSR();
cpu->next_instruction = registres[15];
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(start);
}
OP_L_DB(14, start);
@@ -5411,38 +5210,36 @@
OP_L_DB(1, start);
OP_L_DB(0, start);
- if(BIT15(i)==0)
- {
+ if (!BIT15(i))
armcpu_switchMode(cpu, static_cast<uint8_t>(oldmode));
- }
else
{
Status_Reg SPSR = cpu->SPSR;
armcpu_switchMode(cpu, SPSR.bits.mode);
- cpu->CPSR=SPSR;
+ cpu->CPSR = SPSR;
cpu->changeCPSR();
}
return MMU_aluMemCycles<PROCNUM>(2, c);
}
-TEMPLATE static uint32_t FASTCALL OP_LDMIA2_W(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDMIA2_W(uint32_t i)
{
uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i,16)];
uint32_t oldmode = 0;
- uint32_t start = cpu->R[REG_POS(i,16)];
- uint32_t * registres;
- uint32_t tmp;
- Status_Reg SPSR;
-// emu_halt();
- if(BIT15(i)==0)
- {
- if((cpu->CPSR.bits.mode==USR)||(cpu->CPSR.bits.mode==SYS)) { printf("ERROR1\n"); return 1; }
+ if (!BIT15(i))
+ {
+ if (cpu->CPSR.bits.mode == USR || cpu->CPSR.bits.mode == SYS)
+ {
+ printf("ERROR1\n");
+ return 1;
+ }
oldmode = armcpu_switchMode(cpu, SYS);
}
- registres = cpu->R;
+ uint32_t *registres = cpu->R;
OP_L_IA(0, start);
OP_L_IA(1, start);
@@ -5460,45 +5257,45 @@
OP_L_IA(13, start);
OP_L_IA(14, start);
- if(BIT15(i)==0)
- {
- if (!BIT_N(i, REG_POS(i,16)))
- registres[REG_POS(i,16)] = start;
+ if (!BIT15(i))
+ {
+ if (!BIT_N(i, REG_POS(i, 16)))
+ registres[REG_POS(i, 16)] = start;
armcpu_switchMode(cpu, static_cast<uint8_t>(oldmode));
return MMU_aluMemCycles<PROCNUM>(2, c);
}
- if (!BIT_N(i, REG_POS(i,16)))
- registres[REG_POS(i,16)] = start + 4;
- tmp = READ32(cpu->mem_if->data, start);
- registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
- SPSR = cpu->SPSR;
+ if (!BIT_N(i, REG_POS(i, 16)))
+ registres[REG_POS(i, 16)] = start + 4;
+ uint32_t tmp = READ32(cpu->mem_if->data, start);
+ registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp) << 1));
+ Status_Reg SPSR = cpu->SPSR;
armcpu_switchMode(cpu, SPSR.bits.mode);
- cpu->CPSR=SPSR;
+ cpu->CPSR = SPSR;
cpu->changeCPSR();
cpu->next_instruction = registres[15];
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(start);
return MMU_aluMemCycles<PROCNUM>(2, c);
}
-TEMPLATE static uint32_t FASTCALL OP_LDMIB2_W(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDMIB2_W(uint32_t i)
{
uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
uint32_t oldmode = 0;
- uint32_t start = cpu->R[REG_POS(i,16)];
- uint32_t * registres;
- uint32_t tmp;
- Status_Reg SPSR;
-
- if(BIT15(i)==0)
- {
- if((cpu->CPSR.bits.mode==USR)||(cpu->CPSR.bits.mode==SYS)) { printf("ERROR1\n"); return 1; }
+ if (!BIT15(i))
+ {
+ if (cpu->CPSR.bits.mode == USR || cpu->CPSR.bits.mode == SYS)
+ {
+ printf("ERROR1\n");
+ return 1;
+ }
oldmode = armcpu_switchMode(cpu, SYS);
}
- registres = cpu->R;
+ uint32_t *registres = cpu->R;
OP_L_IB(0, start);
OP_L_IB(1, start);
@@ -5516,10 +5313,10 @@
OP_L_IB(13, start);
OP_L_IB(14, start);
- if(BIT15(i)==0)
- {
- if (!BIT_N(i, REG_POS(i,16)))
- registres[REG_POS(i,16)] = start;
+ if (!BIT15(i))
+ {
+ if (!BIT_N(i, REG_POS(i, 16)))
+ registres[REG_POS(i, 16)] = start;
armcpu_switchMode(cpu, static_cast<uint8_t>(oldmode));
return MMU_aluMemCycles<PROCNUM>(2, c);
@@ -5527,43 +5324,45 @@
if (!BIT_N(i, REG_POS(i,16)))
registres[REG_POS(i,16)] = start + 4;
- tmp = READ32(cpu->mem_if->data, start + 4);
- registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
+ uint32_t tmp = READ32(cpu->mem_if->data, start + 4);
+ registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp) << 1));
cpu->CPSR = cpu->SPSR;
cpu->changeCPSR();
cpu->next_instruction = registres[15];
- SPSR = cpu->SPSR;
+ Status_Reg SPSR = cpu->SPSR;
armcpu_switchMode(cpu, SPSR.bits.mode);
- cpu->CPSR=SPSR;
+ cpu->CPSR = SPSR;
cpu->changeCPSR();
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(start);
return MMU_aluMemCycles<PROCNUM>(2, c);
}
-TEMPLATE static uint32_t FASTCALL OP_LDMDA2_W(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDMDA2_W(uint32_t i)
{
uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i,16)];
uint32_t oldmode = 0;
- uint32_t start = cpu->R[REG_POS(i,16)];
- uint32_t * registres;
- Status_Reg SPSR;
-// emu_halt();
- if(BIT15(i)==0)
- {
- if((cpu->CPSR.bits.mode==USR)||(cpu->CPSR.bits.mode==SYS)) { printf("ERROR1\n"); return 1; }
+ if (!BIT15(i))
+ {
+ if (cpu->CPSR.bits.mode == USR || cpu->CPSR.bits.mode == SYS)
+ {
+ printf("ERROR1\n");
+ return 1;
+ }
oldmode = armcpu_switchMode(cpu, SYS);
}
- registres = cpu->R;
-
- if(BIT15(i))
- {
- if (BIT_N(i, REG_POS(i,16))) printf("error1_1\n");
+ uint32_t *registres = cpu->R;
+
+ if (BIT15(i))
+ {
+ if (BIT_N(i, REG_POS(i, 16)))
+ printf("error1_1\n");
uint32_t tmp = READ32(cpu->mem_if->data, start);
- registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start);
+ registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp) << 1));
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(start);
start -= 4;
cpu->next_instruction = registres[15];
}
@@ -5584,47 +5383,48 @@
OP_L_DA(1, start);
OP_L_DA(0, start);
- if (!BIT_N(i, REG_POS(i,16)))
- registres[REG_POS(i,16)] = start;
-
- if(BIT15(i)==0)
+ if (!BIT_N(i, REG_POS(i, 16)))
+ registres[REG_POS(i, 16)] = start;
+
+ if (!BIT15(i))
{
armcpu_switchMode(cpu, static_cast<uint8_t>(oldmode));
return MMU_aluMemCycles<PROCNUM>(2, c);
}
- SPSR = cpu->SPSR;
+ Status_Reg SPSR = cpu->SPSR;
armcpu_switchMode(cpu, SPSR.bits.mode);
- cpu->CPSR=SPSR;
+ cpu->CPSR = SPSR;
cpu->changeCPSR();
return MMU_aluMemCycles<PROCNUM>(2, c);
}
-TEMPLATE static uint32_t FASTCALL OP_LDMDB2_W(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDMDB2_W(uint32_t i)
{
uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
uint32_t oldmode = 0;
- uint32_t start = cpu->R[REG_POS(i,16)];
- uint32_t * registres;
- Status_Reg SPSR;
-// emu_halt();
- if(BIT15(i)==0)
- {
- if((cpu->CPSR.bits.mode==USR)||(cpu->CPSR.bits.mode==SYS)) { printf("ERROR1\n"); return 1; }
+ if (!BIT15(i))
+ {
+ if (cpu->CPSR.bits.mode == USR || cpu->CPSR.bits.mode == SYS)
+ {
+ printf("ERROR1\n");
+ return 1;
+ }
oldmode = armcpu_switchMode(cpu, SYS);
}
- registres = cpu->R;
-
- if(BIT15(i))
- {
- if (BIT_N(i, REG_POS(i,16))) printf("error1_2\n");
- uint32_t tmp;
+ uint32_t *registres = cpu->R;
+
+ if (BIT15(i))
+ {
+ if (BIT_N(i, REG_POS(i, 16)))
+ printf("error1_2\n");
start -= 4;
- tmp = READ32(cpu->mem_if->data, start);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start);
- registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
+ uint32_t tmp = READ32(cpu->mem_if->data, start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(start);
+ registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp) << 1));
cpu->CPSR = cpu->SPSR;
cpu->changeCPSR();
cpu->next_instruction = registres[15];
@@ -5646,190 +5446,184 @@
OP_L_DB(1, start);
OP_L_DB(0, start);
- if (!BIT_N(i, REG_POS(i,16)))
- registres[REG_POS(i,16)] = start;
-
- if(BIT15(i)==0)
+ if (!BIT_N(i, REG_POS(i, 16)))
+ registres[REG_POS(i, 16)] = start;
+
+ if (!BIT15(i))
{
armcpu_switchMode(cpu, static_cast<uint8_t>(oldmode));
return MMU_aluMemCycles<PROCNUM>(2, c);
}
- SPSR = cpu->SPSR;
+ Status_Reg SPSR = cpu->SPSR;
armcpu_switchMode(cpu, SPSR.bits.mode);
- cpu->CPSR=SPSR;
+ cpu->CPSR = SPSR;
cpu->changeCPSR();
return MMU_aluMemCycles<PROCNUM>(2, c);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// STMIA / STMIB / STMDA / STMDB
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_STMIA(const uint32_t i)
-{
- uint32_t c = 0, b;
- uint32_t start = cpu->R[REG_POS(i,16)];
-
- for(b=0; b<16; b++)
- {
- if(BIT_N(i, b))
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_STMIA(uint32_t i)
+{
+ uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+
+ for (uint32_t b = 0; b < 16; ++b)
+ {
+ if (BIT_N(i, b))
{
WRITE32(cpu->mem_if->data, start, cpu->R[b]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(start);
start += 4;
}
}
return MMU_aluMemCycles<PROCNUM>(1, c);
}
-TEMPLATE static uint32_t FASTCALL OP_STMIB(const uint32_t i)
-{
- uint32_t c = 0, b;
- uint32_t start = cpu->R[REG_POS(i,16)];
-
- for(b=0; b<16; b++)
- {
- if(BIT_N(i, b))
+TEMPLATE static uint32_t FASTCALL OP_STMIB(uint32_t i)
+{
+ uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+
+ for (uint32_t b = 0; b < 16; ++b)
+ {
+ if (BIT_N(i, b))
{
start += 4;
WRITE32(cpu->mem_if->data, start, cpu->R[b]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(start);
}
}
return MMU_aluMemCycles<PROCNUM>(1, c);
}
-TEMPLATE static uint32_t FASTCALL OP_STMDA(const uint32_t i)
-{
- uint32_t c = 0, b;
- uint32_t start = cpu->R[REG_POS(i,16)];
-
- for(b=0; b<16; b++)
- {
- if(BIT_N(i, 15-b))
+TEMPLATE static uint32_t FASTCALL OP_STMDA(uint32_t i)
+{
+ uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+
+ for (uint32_t b = 0; b < 16; ++b)
+ {
+ if (BIT_N(i, 15 - b))
{
- WRITE32(cpu->mem_if->data, start, cpu->R[15-b]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(start);
+ WRITE32(cpu->mem_if->data, start, cpu->R[15 - b]);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(start);
start -= 4;
}
}
return MMU_aluMemCycles<PROCNUM>(1, c);
}
-TEMPLATE static uint32_t FASTCALL OP_STMDB(const uint32_t i)
-{
- uint32_t c = 0, b;
- uint32_t start = cpu->R[REG_POS(i,16)];
-
- for(b=0; b<16; b++)
- {
- if(BIT_N(i, 15-b))
+TEMPLATE static uint32_t FASTCALL OP_STMDB(uint32_t i)
+{
+ uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+
+ for (uint32_t b = 0; b < 16; ++b)
+ {
+ if (BIT_N(i, 15 - b))
{
start -= 4;
- WRITE32(cpu->mem_if->data, start, cpu->R[15-b]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(start);
+ WRITE32(cpu->mem_if->data, start, cpu->R[15 - b]);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(start);
}
}
return MMU_aluMemCycles<PROCNUM>(1, c);
}
-TEMPLATE static uint32_t FASTCALL OP_STMIA_W(const uint32_t i)
-{
- uint32_t c = 0, b;
- uint32_t start = cpu->R[REG_POS(i,16)];
-
- for(b=0; b<16; b++)
- {
- if(BIT_N(i, b))
+TEMPLATE static uint32_t FASTCALL OP_STMIA_W(uint32_t i)
+{
+ uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+
+ for (uint32_t b = 0; b < 16; ++b)
+ {
+ if (BIT_N(i, b))
{
WRITE32(cpu->mem_if->data, start, cpu->R[b]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(start);
start += 4;
}
}
- cpu->R[REG_POS(i,16)] = start;
+ cpu->R[REG_POS(i, 16)] = start;
return MMU_aluMemCycles<PROCNUM>(1, c);
}
-TEMPLATE static uint32_t FASTCALL OP_STMIB_W(const uint32_t i)
-{
- uint32_t c = 0, b;
- uint32_t start = cpu->R[REG_POS(i,16)];
-
- for(b=0; b<16; b++)
- {
- if(BIT_N(i, b))
+TEMPLATE static uint32_t FASTCALL OP_STMIB_W(uint32_t i)
+{
+ uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+
+ for (uint32_t b = 0; b < 16; ++b)
+ {
+ if (BIT_N(i, b))
{
start += 4;
WRITE32(cpu->mem_if->data, start, cpu->R[b]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(start);
}
}
- cpu->R[REG_POS(i,16)] = start;
+ cpu->R[REG_POS(i, 16)] = start;
return MMU_aluMemCycles<PROCNUM>(1, c);
}
-TEMPLATE static uint32_t FASTCALL OP_STMDA_W(const uint32_t i)
-{
- uint32_t c = 0, b;
- uint32_t start = cpu->R[REG_POS(i,16)];
-
- for(b=0; b<16; b++)
- {
- if(BIT_N(i, 15-b))
+TEMPLATE static uint32_t FASTCALL OP_STMDA_W(uint32_t i)
+{
+ uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+
+ for (uint32_t b = 0; b < 16; ++b)
+ {
+ if (BIT_N(i, 15 - b))
{
- WRITE32(cpu->mem_if->data, start, cpu->R[15-b]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(start);
+ WRITE32(cpu->mem_if->data, start, cpu->R[15 - b]);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(start);
start -= 4;
}
}
- cpu->R[REG_POS(i,16)] = start;
+ cpu->R[REG_POS(i, 16)] = start;
return MMU_aluMemCycles<PROCNUM>(1, c);
}
-TEMPLATE static uint32_t FASTCALL OP_STMDB_W(const uint32_t i)
-{
- uint32_t c = 0, b;
- uint32_t start = cpu->R[REG_POS(i,16)];
-
- for(b=0; b<16; b++)
- {
- if(BIT_N(i, 15-b))
+TEMPLATE static uint32_t FASTCALL OP_STMDB_W(uint32_t i)
+{
+ uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+
+ for (uint32_t b = 0; b < 16; ++b)
+ {
+ if (BIT_N(i, 15 - b))
{
start -= 4;
- WRITE32(cpu->mem_if->data, start, cpu->R[15-b]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(start);
+ WRITE32(cpu->mem_if->data, start, cpu->R[15 - b]);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(start);
}
}
- cpu->R[REG_POS(i,16)] = start;
+ cpu->R[REG_POS(i, 16)] = start;
return MMU_aluMemCycles<PROCNUM>(1, c);
}
-TEMPLATE static uint32_t FASTCALL OP_STMIA2(const uint32_t i)
-{
- uint32_t c, b;
- uint32_t start;
- uint32_t oldmode;
-
- if(cpu->CPSR.bits.mode==USR)
+TEMPLATE static uint32_t FASTCALL OP_STMIA2(uint32_t i)
+{
+ if (cpu->CPSR.bits.mode == USR)
return 2;
- c = 0;
- start = cpu->R[REG_POS(i,16)];
- oldmode = armcpu_switchMode(cpu, SYS);
-
- //UNTESTEDOPCODELOG("Untested opcode: OP_STMIA2 \n");
-
- for(b=0; b<16; b++)
- {
- if(BIT_N(i, b))
+ uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+ uint32_t oldmode = armcpu_switchMode(cpu, SYS);
+
+ for (uint32_t b = 0; b < 16; ++b)
+ {
+ if (BIT_N(i, b))
{
WRITE32(cpu->mem_if->data, start, cpu->R[b]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(start);
start += 4;
}
}
@@ -5838,28 +5632,22 @@
return MMU_aluMemCycles<PROCNUM>(1, c);
}
-TEMPLATE static uint32_t FASTCALL OP_STMIB2(const uint32_t i)
-{
- uint32_t c, b;
- uint32_t start;
- uint32_t oldmode;
-
- if(cpu->CPSR.bits.mode==USR)
+TEMPLATE static uint32_t FASTCALL OP_STMIB2(uint32_t i)
+{
+ if (cpu->CPSR.bits.mode == USR)
return 2;
- c = 0;
- start = cpu->R[REG_POS(i,16)];
- oldmode = armcpu_switchMode(cpu, SYS);
-
- //UNTESTEDOPCODELOG("Untested opcode: OP_STMIB2 \n");
-
- for(b=0; b<16; b++)
- {
- if(BIT_N(i, b))
+ uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+ uint32_t oldmode = armcpu_switchMode(cpu, SYS);
+
+ for (uint32_t b = 0; b < 16; ++b)
+ {
+ if (BIT_N(i, b))
{
start += 4;
WRITE32(cpu->mem_if->data, start, cpu->R[b]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(start);
}
}
@@ -5867,27 +5655,21 @@
return MMU_aluMemCycles<PROCNUM>(1, c);
}
-TEMPLATE static uint32_t FASTCALL OP_STMDA2(const uint32_t i)
-{
- uint32_t c, b;
- uint32_t start;
- uint32_t oldmode;
-
- if(cpu->CPSR.bits.mode==USR)
+TEMPLATE static uint32_t FASTCALL OP_STMDA2(uint32_t i)
+{
+ if (cpu->CPSR.bits.mode == USR)
return 2;
- c = 0;
- start = cpu->R[REG_POS(i,16)];
- oldmode = armcpu_switchMode(cpu, SYS);
-
- //UNTESTEDOPCODELOG("Untested opcode: OP_STMDA2 \n");
-
- for(b=0; b<16; b++)
- {
- if(BIT_N(i, 15-b))
+ uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+ uint32_t oldmode = armcpu_switchMode(cpu, SYS);
+
+ for (uint32_t b = 0; b < 16; ++b)
+ {
+ if (BIT_N(i, 15 - b))
{
- WRITE32(cpu->mem_if->data, start, cpu->R[15-b]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(start);
+ WRITE32(cpu->mem_if->data, start, cpu->R[15 - b]);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(start);
start -= 4;
}
}
@@ -5896,26 +5678,22 @@
return MMU_aluMemCycles<PROCNUM>(1, c);
}
-TEMPLATE static uint32_t FASTCALL OP_STMDB2(const uint32_t i)
-{
- uint32_t c, b;
- uint32_t start;
- uint32_t oldmode;
-
- if(cpu->CPSR.bits.mode==USR)
+TEMPLATE static uint32_t FASTCALL OP_STMDB2(uint32_t i)
+{
+ if (cpu->CPSR.bits.mode == USR)
return 2;
- c=0;
- start = cpu->R[REG_POS(i,16)];
- oldmode = armcpu_switchMode(cpu, SYS);
-
- for(b=0; b<16; b++)
- {
- if(BIT_N(i, 15-b))
+ uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+ uint32_t oldmode = armcpu_switchMode(cpu, SYS);
+
+ for (uint32_t b = 0; b < 16; ++b)
+ {
+ if (BIT_N(i, 15 - b))
{
start -= 4;
- WRITE32(cpu->mem_if->data, start, cpu->R[15-b]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(start);
+ WRITE32(cpu->mem_if->data, start, cpu->R[15 - b]);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(start);
}
}
@@ -5923,352 +5701,318 @@
return MMU_aluMemCycles<PROCNUM>(1, c);
}
-TEMPLATE static uint32_t FASTCALL OP_STMIA2_W(const uint32_t i)
-{
- uint32_t c, b;
- uint32_t start;
- uint32_t oldmode;
-
- if(cpu->CPSR.bits.mode==USR)
+TEMPLATE static uint32_t FASTCALL OP_STMIA2_W(uint32_t i)
+{
+ if (cpu->CPSR.bits.mode == USR)
return 2;
- c=0;
- start = cpu->R[REG_POS(i,16)];
- oldmode = armcpu_switchMode(cpu, SYS);
-
- //UNTESTEDOPCODELOG("Untested opcode: OP_STMIA2_W \n");
-
- for(b=0; b<16; b++)
- {
- if(BIT_N(i, b))
+ uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+ uint32_t oldmode = armcpu_switchMode(cpu, SYS);
+
+ for (uint32_t b = 0; b < 16; ++b)
+ {
+ if (BIT_N(i, b))
{
WRITE32(cpu->mem_if->data, start, cpu->R[b]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(start);
start += 4;
}
}
- cpu->R[REG_POS(i,16)] = start;
+ cpu->R[REG_POS(i, 16)] = start;
armcpu_switchMode(cpu, static_cast<uint8_t>(oldmode));
return MMU_aluMemCycles<PROCNUM>(1, c);
}
-TEMPLATE static uint32_t FASTCALL OP_STMIB2_W(const uint32_t i)
-{
- uint32_t c, b;
- uint32_t start;
- uint32_t oldmode;
-
- if(cpu->CPSR.bits.mode==USR)
+TEMPLATE static uint32_t FASTCALL OP_STMIB2_W(uint32_t i)
+{
+ if (cpu->CPSR.bits.mode == USR)
return 2;
- c=0;
- start = cpu->R[REG_POS(i,16)];
- oldmode = armcpu_switchMode(cpu, SYS);
-
- for(b=0; b<16; b++)
- {
- if(BIT_N(i, b))
+
+ uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+ uint32_t oldmode = armcpu_switchMode(cpu, SYS);
+
+ for (uint32_t b = 0; b < 16; ++b)
+ {
+ if (BIT_N(i, b))
{
start += 4;
WRITE32(cpu->mem_if->data, start, cpu->R[b]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(start);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(start);
}
}
+
armcpu_switchMode(cpu, static_cast<uint8_t>(oldmode));
- cpu->R[REG_POS(i,16)] = start;
+ cpu->R[REG_POS(i, 16)] = start;
return MMU_aluMemCycles<PROCNUM>(1, c);
}
-TEMPLATE static uint32_t FASTCALL OP_STMDA2_W(const uint32_t i)
-{
- uint32_t c, b;
- uint32_t start;
- uint32_t oldmode;
-
- if(cpu->CPSR.bits.mode==USR)
+TEMPLATE static uint32_t FASTCALL OP_STMDA2_W(uint32_t i)
+{
+ if (cpu->CPSR.bits.mode == USR)
return 2;
- c = 0;
- start = cpu->R[REG_POS(i,16)];
- oldmode = armcpu_switchMode(cpu, SYS);
-
- //UNTESTEDOPCODELOG("Untested opcode: OP_STMDA2_W \n");
-
- for(b=0; b<16; b++)
- {
- if(BIT_N(i, 15-b))
+ uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+ uint32_t oldmode = armcpu_switchMode(cpu, SYS);
+
+ for (uint32_t b = 0; b < 16; ++b)
+ {
+ if (BIT_N(i, 15 - b))
{
- WRITE32(cpu->mem_if->data, start, cpu->R[15-b]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(start);
+ WRITE32(cpu->mem_if->data, start, cpu->R[15 - b]);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(start);
start -= 4;
}
}
- cpu->R[REG_POS(i,16)] = start;
+ cpu->R[REG_POS(i, 16)] = start;
armcpu_switchMode(cpu, static_cast<uint8_t>(oldmode));
return MMU_aluMemCycles<PROCNUM>(1, c);
}
-TEMPLATE static uint32_t FASTCALL OP_STMDB2_W(const uint32_t i)
-{
- uint32_t c, b;
- uint32_t start;
- uint32_t oldmode;
-
- if(cpu->CPSR.bits.mode==USR)
+TEMPLATE static uint32_t FASTCALL OP_STMDB2_W(uint32_t i)
+{
+ if (cpu->CPSR.bits.mode == USR)
return 2;
- c = 0;
-
- start = cpu->R[REG_POS(i,16)];
- oldmode = armcpu_switchMode(cpu, SYS);
-
- //UNTESTEDOPCODELOG("Untested opcode: OP_STMDB2_W \n");
-
- for(b=0; b<16; b++)
- {
- if(BIT_N(i, 15-b))
+ uint32_t c = 0;
+ uint32_t start = cpu->R[REG_POS(i, 16)];
+ uint32_t oldmode = armcpu_switchMode(cpu, SYS);
+
+ for (uint32_t b = 0; b < 16; ++b)
+ {
+ if (BIT_N(i, 15 - b))
{
start -= 4;
- WRITE32(cpu->mem_if->data, start, cpu->R[15-b]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(start);
+ WRITE32(cpu->mem_if->data, start, cpu->R[15 - b]);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(start);
}
}
- cpu->R[REG_POS(i,16)] = start;
+ cpu->R[REG_POS(i, 16)] = start;
armcpu_switchMode(cpu, static_cast<uint8_t>(oldmode));
return MMU_aluMemCycles<PROCNUM>(1, c);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// LDRD / STRD
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_LDRD_STRD_POST_INDEX(const uint32_t i)
-{
- uint32_t Rd_num = REG_POS( i, 12);
- uint32_t addr = cpu->R[REG_POS(i,16)];
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_LDRD_STRD_POST_INDEX(uint32_t i)
+{
+ uint32_t Rd_num = REG_POS(i, 12);
+ uint32_t addr = cpu->R[REG_POS(i, 16)];
uint32_t index;
+
//printf("%s POST\n", BIT5(i)?"STRD":"LDRD");
/* I bit - immediate or register */
- if ( BIT22(i))
+ if (BIT22(i))
index = IMM_OFF;
else
- index = cpu->R[REG_POS(i,0)];
+ index = cpu->R[REG_POS(i, 0)];
// U bit - add or subtract
- if ( BIT23(i))
- cpu->R[REG_POS(i,16)] += index;
+ if (BIT23(i))
+ cpu->R[REG_POS(i, 16)] += index;
else
- cpu->R[REG_POS(i,16)] -= index;
+ cpu->R[REG_POS(i, 16)] -= index;
uint32_t c = 0;
- if ( !(Rd_num & 0x1))
+ if (!(Rd_num & 0x1))
{
// Store/Load
- if ( BIT5(i))
+ if (BIT5(i))
{
WRITE32(cpu->mem_if->data, addr, cpu->R[Rd_num]);
WRITE32(cpu->mem_if->data, addr + 4, cpu->R[Rd_num + 1]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(addr);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(addr + 4);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(addr);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(addr + 4);
}
else
{
cpu->R[Rd_num] = READ32(cpu->mem_if->data, addr);
cpu->R[Rd_num + 1] = READ32(cpu->mem_if->data, addr + 4);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(addr);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(addr + 4);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(addr);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(addr + 4);
}
}
return MMU_aluMemCycles<PROCNUM>(3, c);
}
-TEMPLATE static uint32_t FASTCALL OP_LDRD_STRD_OFFSET_PRE_INDEX(const uint32_t i)
-{
- uint32_t Rd_num = REG_POS( i, 12);
- uint32_t addr = cpu->R[REG_POS(i,16)];
+TEMPLATE static uint32_t FASTCALL OP_LDRD_STRD_OFFSET_PRE_INDEX(uint32_t i)
+{
+ uint32_t Rd_num = REG_POS(i, 12);
+ uint32_t addr = cpu->R[REG_POS(i, 16)];
uint32_t index;
//printf("%s PRE\n", BIT5(i)?"STRD":"LDRD");
// I bit - immediate or register
- if ( BIT22(i))
+ if (BIT22(i))
index = IMM_OFF;
else
- index = cpu->R[REG_POS(i,0)];
+ index = cpu->R[REG_POS(i, 0)];
// U bit - add or subtract
- if ( BIT23(i))
+ if (BIT23(i))
addr += index;
else
addr -= index;
uint32_t c = 0;
- if ( !(Rd_num & 0x1))
+ if (!(Rd_num & 0x1))
{
// Store/Load
- if ( BIT5(i))
+ if (BIT5(i))
{
WRITE32(cpu->mem_if->data, addr, cpu->R[Rd_num]);
WRITE32(cpu->mem_if->data, addr + 4, cpu->R[Rd_num + 1]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(addr);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(addr + 4);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(addr);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(addr + 4);
// W bit - writeback
- if ( BIT21(i))
- cpu->R[REG_POS(i,16)] = addr;
+ if (BIT21(i))
+ cpu->R[REG_POS(i, 16)] = addr;
}
else
{
// W bit - writeback
- if ( BIT21(i))
- cpu->R[REG_POS(i,16)] = addr;
+ if (BIT21(i))
+ cpu->R[REG_POS(i, 16)] = addr;
cpu->R[Rd_num] = READ32(cpu->mem_if->data, addr);
cpu->R[Rd_num + 1] = READ32(cpu->mem_if->data, addr + 4);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(addr);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(addr + 4);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(addr);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(addr + 4);
}
}
return MMU_aluMemCycles<PROCNUM>(3, c);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// STC
// the NDS has no coproc that responses to a STC, no feedback is given to the arm
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_STC_P_IMM_OFF(const uint32_t)
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_STC_P_IMM_OFF(uint32_t)
{
//INFO("OP_STC_P_IMM_OFF\n");
return TRAPUNDEF(cpu);
}
-TEMPLATE static uint32_t FASTCALL OP_STC_M_IMM_OFF(const uint32_t)
+TEMPLATE static uint32_t FASTCALL OP_STC_M_IMM_OFF(uint32_t)
{
//INFO("OP_STC_M_IMM_OFF\n");
return TRAPUNDEF(cpu);
}
-TEMPLATE static uint32_t FASTCALL OP_STC_P_PREIND(const uint32_t)
+TEMPLATE static uint32_t FASTCALL OP_STC_P_PREIND(uint32_t)
{
//INFO("OP_STC_P_PREIND\n");
return TRAPUNDEF(cpu);
}
-TEMPLATE static uint32_t FASTCALL OP_STC_M_PREIND(const uint32_t)
+TEMPLATE static uint32_t FASTCALL OP_STC_M_PREIND(uint32_t)
{
//INFO("OP_STC_M_PREIND\n");
return TRAPUNDEF(cpu);
}
-TEMPLATE static uint32_t FASTCALL OP_STC_P_POSTIND(const uint32_t)
+TEMPLATE static uint32_t FASTCALL OP_STC_P_POSTIND(uint32_t)
{
//INFO("OP_STC_P_POSTIND: cp_num %i\n", (i>>8)&0x0F);
return TRAPUNDEF(cpu);
-
-
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STC_M_POSTIND(const uint32_t)
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STC_M_POSTIND(uint32_t)
{
//INFO("OP_STC_M_POSTIND\n");
return TRAPUNDEF(cpu);
}
-TEMPLATE static uint32_t FASTCALL OP_STC_OPTION(const uint32_t)
+TEMPLATE static uint32_t FASTCALL OP_STC_OPTION(uint32_t)
{
//INFO("OP_STC_OPTION\n");
return TRAPUNDEF(cpu);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// LDC
// the NDS has no coproc that responses to a LDC, no feedback is given to the arm
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_LDC_P_IMM_OFF(const uint32_t)
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_LDC_P_IMM_OFF(uint32_t)
{
//INFO("OP_LDC_P_IMM_OFF\n");
return TRAPUNDEF(cpu);
}
-TEMPLATE static uint32_t FASTCALL OP_LDC_M_IMM_OFF(const uint32_t)
+TEMPLATE static uint32_t FASTCALL OP_LDC_M_IMM_OFF(uint32_t)
{
//INFO("OP_LDC_M_IMM_OFF\n");
return TRAPUNDEF(cpu);
}
-TEMPLATE static uint32_t FASTCALL OP_LDC_P_PREIND(const uint32_t)
+TEMPLATE static uint32_t FASTCALL OP_LDC_P_PREIND(uint32_t)
{
//INFO("OP_LDC_P_PREIND\n");
return TRAPUNDEF(cpu);
}
-TEMPLATE static uint32_t FASTCALL OP_LDC_M_PREIND(const uint32_t)
+TEMPLATE static uint32_t FASTCALL OP_LDC_M_PREIND(uint32_t)
{
//INFO("OP_LDC_M_PREIND\n");
return TRAPUNDEF(cpu);
}
-TEMPLATE static uint32_t FASTCALL OP_LDC_P_POSTIND(const uint32_t)
+TEMPLATE static uint32_t FASTCALL OP_LDC_P_POSTIND(uint32_t)
{
//INFO("OP_LDC_P_POSTIND\n");
return TRAPUNDEF(cpu);
}
-TEMPLATE static uint32_t FASTCALL OP_LDC_M_POSTIND(const uint32_t)
+TEMPLATE static uint32_t FASTCALL OP_LDC_M_POSTIND(uint32_t)
{
//INFO("OP_LDC_M_POSTIND\n");
return TRAPUNDEF(cpu);
}
-TEMPLATE static uint32_t FASTCALL OP_LDC_OPTION(const uint32_t)
+TEMPLATE static uint32_t FASTCALL OP_LDC_OPTION(uint32_t)
{
//INFO("OP_LDC_OPTION\n");
return TRAPUNDEF(cpu);
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// MCR / MRC
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_MCR(const uint32_t i)
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_MCR(uint32_t i)
{
uint32_t cpnum = REG_POS(i, 8);
- if(!cpu->coproc[cpnum])
- {
- //emu_halt();
- //INFO("Stopped (OP_MCR) \n");
- /*INFO("ARM%c: MCR P%i, 0, R%i, C%i, C%i, %i, %i (don't allocated coprocessor)\n",
- PROCNUM?'7':'9', cpnum, REG_POS(i, 12), REG_POS(i, 16), REG_POS(i, 0), (i>>21)&0x7, (i>>5)&0x7);*/
+ if (cpnum != 15)
return 2;
- }
-
- armcp15_moveARM2CP((armcp15_t*)cpu->coproc[cpnum], cpu->R[REG_POS(i, 12)], static_cast<uint8_t>(REG_POS(i, 16)), static_cast<uint8_t>(REG_POS(i, 0)), (i>>21)&0x7, (i>>5)&0x7);
- //cpu->coproc[cpnum]->moveARM2CP(cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7);
+
+ cp15.moveARM2CP(cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i >> 21) & 0x7, (i >> 5) & 0x7);
+
return 2;
}
-TEMPLATE static uint32_t FASTCALL OP_MRC(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_MRC(uint32_t i)
{
//if (PROCNUM != 0) return 1;
uint32_t cpnum = REG_POS(i, 8);
- if(!cpu->coproc[cpnum])
- {
- //emu_halt();
- //INFO("Stopped (OP_MRC) \n");
- /*INFO("ARM%c: MRC P%i, 0, R%i, C%i, C%i, %i, %i (don't allocated coprocessor)\n",
- PROCNUM?'7':'9', cpnum, REG_POS(i, 12), REG_POS(i, 16), REG_POS(i, 0), (i>>21)&0x7, (i>>5)&0x7);*/
+ if (cpnum != 15)
return 2;
- }
// ARM REF:
//data = value from Coprocessor[cp_num]
@@ -6281,7 +6025,7 @@
// Rd = data
uint32_t data = 0;
- armcp15_moveCP2ARM((armcp15_t*)cpu->coproc[cpnum], &data, static_cast<uint8_t>(REG_POS(i, 16)), static_cast<uint8_t>(REG_POS(i, 0)), (i>>21)&0x7, (i>>5)&0x7);
+ cp15.moveCP2ARM(&data, REG_POS(i, 16), REG_POS(i, 0), (i >> 21) & 0x7, (i >> 5) & 0x7);
if (REG_POS(i, 12) == 15)
{
cpu->CPSR.bits.N = BIT31(data);
@@ -6295,29 +6039,24 @@
return 4;
}
-//-----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
// SWI
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_SWI(const uint32_t i)
-{
- uint32_t swinum = (i>>16)&0xFF;
-
- //ideas-style debug prints (execute this SWI with the null terminated string address in R0)
- if(swinum==0xFC)
- {
- //IdeasLog(cpu);
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_SWI(uint32_t i)
+{
+ uint32_t swinum = (i >> 16) & 0xFF;
+
+ // ideas-style debug prints (execute this SWI with the null terminated string address in R0)
+ if (swinum == 0xFC)
return 0;
- }
-
- //if the user has changed the intVector to point away from the nds bioses,
- //then it doesn't really make any sense to use the builtin SWI's since
- //the bios ones aren't getting called anyway
- bool bypassBuiltinSWI =
- (cpu->intVector == 0x00000000 && PROCNUM==0)
- || (cpu->intVector == 0xFFFF0000 && PROCNUM==1);
-
- if(cpu->swi_tab && !bypassBuiltinSWI)
+
+ // if the user has changed the intVector to point away from the nds bioses,
+ // then it doesn't really make any sense to use the builtin SWI's since
+ // the bios ones aren't getting called anyway
+ bool bypassBuiltinSWI = (cpu->intVector == 0x00000000 && !PROCNUM) || (cpu->intVector == 0xFFFF0000 && PROCNUM == 1);
+
+ if (cpu->swi_tab && !bypassBuiltinSWI)
{
swinum &= 0x1F;
//printf("%d ARM SWI %d \n",PROCNUM,swinum);
@@ -6329,24 +6068,41 @@
/* we use an irq thats not in the irq tab, as
it was replaced duie to a changed intVector */
Status_Reg tmp = cpu->CPSR;
- armcpu_switchMode(cpu, SVC); /* enter svc mode */
+ armcpu_switchMode(cpu, SVC); /* enter svc mode */
cpu->R[14] = cpu->next_instruction;
- cpu->SPSR = tmp; /* save old CPSR as new SPSR */
- cpu->CPSR.bits.T = 0; /* handle as ARM32 code */
+ cpu->SPSR = tmp; /* save old CPSR as new SPSR */
+ cpu->CPSR.bits.T = 0; /* handle as ARM32 code */
cpu->CPSR.bits.I = 1;
cpu->changeCPSR();
cpu->R[15] = cpu->intVector + 0x08;
cpu->next_instruction = cpu->R[15];
- return 4;
- }
-}
-
-//-----------------------------------------------------------------------------
+ return 3;
+ }
+}
+
+// -----------------------------------------------------------------------------
// BKPT
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_BKPT(const uint32_t i)
-{
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_BKPT(uint32_t i)
+{
+ /* ARM-ref
+ if (not overridden by debug hardware)
+ R14_abt = address of BKPT instruction + 4
+ SPSR_abt = CPSR
+ CPSR[4:0] = 0b10111 // Enter Abort mode
+ CPSR[5] = 0 // Execute in ARM state
+ // CPSR[6] is unchanged
+ CPSR[7] = 1 // Disable normal interrupts
+ CPSR[8] = 1 // Disable imprecise aborts - v6 only
+ CPSR[9] = CP15_reg1_EEbit
+ if high vectors configured then
+ PC = 0xFFFF000C
+ else
+ PC = 0x0000000C
+ */
+
+ /*
static uint32_t last_bkpt = 0xFFFFFFFF;
if(i != last_bkpt)
printf("ARM OP_BKPT triggered\n");
@@ -6355,13 +6111,26 @@
//this is not 100% correctly emulated, but it does the job
cpu->next_instruction = cpu->instruct_adr;
return 4;
-}
-
-//-----------------------------------------------------------------------------
+ */
+
+ printf("ARM OP_BKPT triggered\n");
+ Status_Reg tmp = cpu->CPSR;
+ armcpu_switchMode(cpu, ABT); // enter abt mode
+ cpu->R[14] = cpu->instruct_adr + 4;
+ cpu->SPSR = tmp; // save old CPSR as new SPSR
+ cpu->CPSR.bits.T = 0; // handle as ARM32 code
+ cpu->CPSR.bits.I = 1;
+ cpu->changeCPSR();
+ cpu->R[15] = cpu->intVector + 0x0C;
+ cpu->next_instruction = cpu->R[15];
+ return 4;
+}
+
+// -----------------------------------------------------------------------------
// CDP
-//-----------------------------------------------------------------------------
-
-TEMPLATE static uint32_t FASTCALL OP_CDP(const uint32_t)
+// -----------------------------------------------------------------------------
+
+TEMPLATE static uint32_t FASTCALL OP_CDP(uint32_t)
{
//INFO("Stopped (OP_CDP) \n");
return TRAPUNDEF(cpu);
@@ -6371,21 +6140,17 @@
// The End
//-----------------------------------------------------------------------------
+const OpFunc arm_instructions_set[2][4096] =
+{
+ {
#define TABDECL(x) x<0>
-const ArmOpFunc arm_instructions_set_0[4096] = {
#include "instruction_tabdef.inc"
+#undef TABDECL
+ },
+ {
+#define TABDECL(x) x<1>
+#include "instruction_tabdef.inc"
+#undef TABDECL
+ }
};
-#undef TABDECL
-
-#define TABDECL(x) x<1>
-const ArmOpFunc arm_instructions_set_1[4096] = {
-#include "instruction_tabdef.inc"
-};
-#undef TABDECL
-
-/*#define TABDECL(x) #x
-const char* arm_instruction_names[4096] = {
-#include "instruction_tabdef.inc"
-};
-#undef TABDECL*/
-
+
--- a/src/in_2sf/desmume/arm_instructions.h
+++ /dev/null
@@ -1,32 +1,1 @@
-/*
- Copyright (C) 2006 yopyop
- Copyright (C) 2006-2009 DeSmuME team
- This file is free software: you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation, either version 2 of the License, or
- (at your option) any later version.
-
- This file is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with the this software. If not, see <http://www.gnu.org/licenses/>.
-*/
-
-#ifndef ARMINSTRUCTION_H
-#define ARMINSTRUCTION_H
-
-#include "armcpu.h"
-
-typedef uint32_t (FASTCALL *ArmOpFunc)(const uint32_t);
-
-extern const ArmOpFunc arm_instructions_set_0[4096];
-extern const ArmOpFunc arm_instructions_set_1[4096];
-
-//extern const char *arm_instruction_names[4096];
-
-#endif
-
--- /dev/null
+++ b/src/in_2sf/desmume/arm_jit.cpp
@@ -1,1 +1,4393 @@
-
+/* Copyright (C) 2006 yopyop
+ Copyright (C) 2011 Loren Merritt
+ Copyright (C) 2012 DeSmuME team
+
+ This file is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This file is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with the this software. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include "types.h"
+#ifdef HAVE_JIT
+#if !defined(__x86_64__) && !defined(__LP64) && !defined(__IA64__) && !defined(_M_X64) && !defined(_WIN64) && !defined(_M_IX86) && !defined(__INTEL__) && !defined(__i386__)
+#error "ERROR: JIT compiler - unsupported target platform"
+#endif
+#ifdef _WINDOWS
+// **** Windows port
+#else
+# include <sys/mman.h>
+# include <errno.h>
+# include <unistd.h>
+# include <stddef.h>
+# define HAVE_STATIC_CODE_BUFFER
+#endif
+#include "instructions.h"
+#include "instruction_attributes.h"
+#include "MMU.h"
+#include "MMU_timing.h"
+#include "utils/AsmJit/AsmJit.h"
+#include "arm_jit.h"
+#include "bios.h"
+
+#define LOG_JIT_LEVEL 0
+#define PROFILER_JIT_LEVEL 0
+
+#if PROFILER_JIT_LEVEL > 0
+#include <algorithm>
+#endif
+
+using namespace AsmJit;
+
+#if LOG_JIT_LEVEL > 0
+#define LOG_JIT 1
+#define JIT_COMMENT(...) c.comment(__VA_ARGS__)
+#else
+#define LOG_JIT 0
+#define JIT_COMMENT(...)
+#endif
+
+#ifdef MAPPED_JIT_FUNCS
+CACHE_ALIGN JIT_struct JIT;
+
+uintptr_t *JIT_struct::JIT_MEM[2][0x4000] = { { 0 }, { 0 } };
+
+static uintptr_t *JIT_MEM[][32] =
+{
+ //arm9
+ {
+ /* 0X*/ DUP2(JIT.ARM9_ITCM),
+ /* 1X*/ DUP2(JIT.ARM9_ITCM), // mirror
+ /* 2X*/ DUP2(JIT.MAIN_MEM),
+ /* 3X*/ DUP2(JIT.SWIRAM),
+ /* 4X*/ DUP2(nullptr),
+ /* 5X*/ DUP2(nullptr),
+ /* 6X*/ nullptr,
+ JIT.ARM9_LCDC, // Plain ARM9-CPU Access (LCDC mode) (max 656KB)
+ /* 7X*/ DUP2(nullptr),
+ /* 8X*/ DUP2(nullptr),
+ /* 9X*/ DUP2(nullptr),
+ /* AX*/ DUP2(nullptr),
+ /* BX*/ DUP2(nullptr),
+ /* CX*/ DUP2(nullptr),
+ /* DX*/ DUP2(nullptr),
+ /* EX*/ DUP2(nullptr),
+ /* FX*/ DUP2(JIT.ARM9_BIOS)
+ },
+ //arm7
+ {
+ /* 0X*/ DUP2(JIT.ARM7_BIOS),
+ /* 1X*/ DUP2(nullptr),
+ /* 2X*/ DUP2(JIT.MAIN_MEM),
+ /* 3X*/ JIT.SWIRAM,
+ JIT.ARM7_ERAM,
+ /* 4X*/ nullptr,
+ JIT.ARM7_WIRAM,
+ /* 5X*/ DUP2(nullptr),
+ /* 6X*/ JIT.ARM7_WRAM, // VRAM allocated as Work RAM to ARM7 (max. 256K)
+ nullptr,
+ /* 7X*/ DUP2(nullptr),
+ /* 8X*/ DUP2(nullptr),
+ /* 9X*/ DUP2(nullptr),
+ /* AX*/ DUP2(nullptr),
+ /* BX*/ DUP2(nullptr),
+ /* CX*/ DUP2(nullptr),
+ /* DX*/ DUP2(nullptr),
+ /* EX*/ DUP2(nullptr),
+ /* FX*/ DUP2(nullptr)
+ }
+};
+
+static uint32_t JIT_MASK[][32] =
+{
+ //arm9
+ {
+ /* 0X*/ DUP2(0x00007FFF),
+ /* 1X*/ DUP2(0x00007FFF),
+ /* 2X*/ DUP2(0x003FFFFF), // FIXME _MMU_MAIN_MEM_MASK
+ /* 3X*/ DUP2(0x00007FFF),
+ /* 4X*/ DUP2(0x00000000),
+ /* 5X*/ DUP2(0x00000000),
+ /* 6X*/ 0x00000000,
+ 0x000FFFFF,
+ /* 7X*/ DUP2(0x00000000),
+ /* 8X*/ DUP2(0x00000000),
+ /* 9X*/ DUP2(0x00000000),
+ /* AX*/ DUP2(0x00000000),
+ /* BX*/ DUP2(0x00000000),
+ /* CX*/ DUP2(0x00000000),
+ /* DX*/ DUP2(0x00000000),
+ /* EX*/ DUP2(0x00000000),
+ /* FX*/ DUP2(0x00007FFF)
+ },
+ //arm7
+ {
+ /* 0X*/ DUP2(0x00003FFF),
+ /* 1X*/ DUP2(0x00000000),
+ /* 2X*/ DUP2(0x003FFFFF),
+ /* 3X*/ 0x00007FFF,
+ 0x0000FFFF,
+ /* 4X*/ 0x00000000,
+ 0x0000FFFF,
+ /* 5X*/ DUP2(0x00000000),
+ /* 6X*/ 0x0003FFFF,
+ 0x00000000,
+ /* 7X*/ DUP2(0x00000000),
+ /* 8X*/ DUP2(0x00000000),
+ /* 9X*/ DUP2(0x00000000),
+ /* AX*/ DUP2(0x00000000),
+ /* BX*/ DUP2(0x00000000),
+ /* CX*/ DUP2(0x00000000),
+ /* DX*/ DUP2(0x00000000),
+ /* EX*/ DUP2(0x00000000),
+ /* FX*/ DUP2(0x00000000)
+ }
+};
+
+static void init_jit_mem()
+{
+ static bool inited = false;
+ if (inited)
+ return;
+ inited = true;
+ for (int proc = 0; proc < 2; ++proc)
+ for (int i = 0; i < 0x4000; ++i)
+ JIT.JIT_MEM[proc][i] = JIT_MEM[proc][i >> 9] + (((i << 14) & JIT_MASK[proc][i >> 9]) >> 1);
+}
+#else
+DS_ALIGN(4096) uintptr_t compiled_funcs[1 << 26] = {0};
+#endif
+
+static uint8_t recompile_counts[(1 << 26) / 16];
+
+#ifdef HAVE_STATIC_CODE_BUFFER
+// On x86_64, allocate jitted code from a static buffer to ensure that it's within 2GB of .text
+// Allows call instructions to use pcrel offsets, as opposed to slower indirect calls.
+// Reduces memory needed for function pointers.
+// FIXME win64 needs this too, x86_32 doesn't
+
+DS_ALIGN(4096) static uint8_t scratchpad[1 << 25];
+static uint8_t *scratchptr;
+
+struct ASMJIT_API StaticCodeGenerator : public Context
+{
+ StaticCodeGenerator()
+ {
+ scratchptr = scratchpad;
+ int align = reinterpret_cast<uintptr_t>(scratchpad) & (sysconf(_SC_PAGESIZE) - 1);
+ int err = mprotect(scratchpad - align, sizeof(scratchpad) + align, PROT_READ | PROT_WRITE | PROT_EXEC);
+ if (err)
+ {
+ fprintf(stderr, "mprotect failed: %s\n", strerror(errno));
+ abort();
+ }
+ }
+
+ uint32_t generate(void **dest, Assembler *assembler)
+ {
+ uintptr_t size = assembler->getCodeSize();
+ if (!size)
+ {
+ *dest = nullptr;
+ return kErrorNoFunction;
+ }
+ if (size > reinterpret_cast<uintptr_t>(scratchpad + sizeof(scratchpad) - scratchptr))
+ {
+ fprintf(stderr, "Out of memory for asmjit. Clearing code cache.\n");
+ arm_jit_reset(true);
+ // If arm_jit_reset didn't involve recompiling op_cmp, we could keep the current function.
+ *dest = nullptr;
+ return kErrorOk;
+ }
+ void *p = scratchptr;
+ size = assembler->relocCode(p);
+ scratchptr += size;
+ *dest = p;
+ return kErrorOk;
+ }
+};
+
+static StaticCodeGenerator codegen;
+static X86Compiler c(&codegen);
+#else
+static X86Compiler c;
+#endif
+
+static void emit_branch(int cond, Label to);
+static void _armlog(uint8_t proc, uint32_t addr, uint32_t opcode);
+
+static FileLogger logger(stderr);
+
+static int PROCNUM;
+static int *PROCNUM_ptr = &PROCNUM;
+static int bb_opcodesize;
+static int bb_adr;
+static bool bb_thumb;
+static GpVar bb_cpu;
+static GpVar bb_cycles;
+static GpVar bb_total_cycles;
+static uint32_t bb_constant_cycles;
+
+#define cpu (&ARMPROC)
+#define bb_next_instruction (bb_adr + bb_opcodesize)
+#define bb_r15 (bb_adr + 2 * bb_opcodesize)
+
+#define cpu_ptr(x) dword_ptr(bb_cpu, offsetof(armcpu_t, x))
+#define cpu_ptr_byte(x, y) byte_ptr(bb_cpu, offsetof(armcpu_t, x) + y)
+#define flags_ptr cpu_ptr_byte(CPSR.val, 3)
+#define reg_ptr(x) dword_ptr(bb_cpu, offsetof(armcpu_t, R) + 4 * (x))
+#define reg_pos_ptr(x) dword_ptr(bb_cpu, offsetof(armcpu_t, R) + 4 * REG_POS(i, (x)))
+#define reg_pos_ptrL(x) word_ptr(bb_cpu, offsetof(armcpu_t, R) + 4 * REG_POS(i, (x)))
+#define reg_pos_ptrH(x) word_ptr(bb_cpu, offsetof(armcpu_t, R) + 4 * REG_POS(i, (x)) + 2)
+#define reg_pos_ptrB(x) byte_ptr(bb_cpu, offsetof(armcpu_t, R) + 4 * REG_POS(i, (x)))
+#define reg_pos_thumb(x) dword_ptr(bb_cpu, offsetof(armcpu_t, R) + 4 * ((i >> (x)) & 0x7))
+#define reg_pos_thumbB(x) byte_ptr(bb_cpu, offsetof(armcpu_t, R) + 4 * ((i >> (x)) & 0x7))
+#define cp15_ptr(x) dword_ptr(bb_cp15, offsetof(armcp15_t, x))
+#define mmu_ptr(x) dword_ptr(bb_mmu, offsetof(MMU_struct, x))
+#define mmu_ptr_byte(x) byte_ptr(bb_mmu, offsetof(MMU_struct, x))
+static inline uint32_t _REG_NUM(uint32_t i, uint32_t n) { return (i >> n) & 0x7; }
+
+#ifndef ASMJIT_X64
+#define r64 r32
+#endif
+
+// sequencer.reschedule = true;
+#define changeCPSR \
+{ \
+ X86CompilerFuncCall *ctxCPSR = c.call(reinterpret_cast<void *>(NDS_Reschedule)); \
+ ctxCPSR->setPrototype(ASMJIT_CALL_CONV, FuncBuilder0<void>()); \
+}
+
+#if PROFILER_JIT_LEVEL > 0
+struct PROFILER_COUNTER_INFO
+{
+ uint64_t count;
+ char name[64];
+};
+
+struct JIT_PROFILER
+{
+ JIT_PROFILER::JIT_PROFILER()
+ {
+ memset(&this->arm_count[0], 0, sizeof(this->arm_count));
+ memset(&this->thumb_count[0], 0, sizeof(this->thumb_count));
+ }
+
+ uint64_t arm_count[4096];
+ uint64_t thumb_count[1024];
+} profiler_counter[2];
+
+static GpVar bb_profiler;
+
+#define profiler_counter_arm(opcode) qword_ptr(bb_profiler, offsetof(JIT_PROFILER, arm_count[INSTRUCTION_INDEX(opcode)]))
+#define profiler_counter_thumb(opcode) qword_ptr(bb_profiler, offsetof(JIT_PROFILER, thumb_count[opcode>>6]))
+
+#if PROFILER_JIT_LEVEL > 1
+struct PROFILER_ENTRY
+{
+ uint32_t addr;
+ uint32_t cycles;
+} profiler_entry[2][1<<26];
+
+static GpVar bb_profiler_entry;
+#endif
+
+#endif
+
+// -----------------------------------------------------------------------------
+// Shifting macros
+// -----------------------------------------------------------------------------
+#define SET_NZCV(sign) \
+{ \
+ JIT_COMMENT("SET_NZCV"); \
+ GpVar x = c.newGpVar(kX86VarTypeGpd); \
+ GpVar y = c.newGpVar(kX86VarTypeGpd); \
+ c.sets(x.r8Lo()); \
+ c.setz(y.r8Lo()); \
+ c.lea(x, ptr(y.r64(), x.r64(), kScale2Times)); \
+ if (sign) \
+ c.setnc(y.r8Lo()); \
+ else \
+ c.setc(y.r8Lo()); \
+ c.lea(x, ptr(y.r64(), x.r64(), kScale2Times)); \
+ c.seto(y.r8Lo()); \
+ c.lea(x, ptr(y.r64(), x.r64(), kScale2Times)); \
+ c.movzx(y, flags_ptr); \
+ c.shl(x, 4); \
+ c.and_(y, 0xF); \
+ c.or_(x, y); \
+ c.mov(flags_ptr, x.r8Lo()); \
+ c.unuse(x); \
+ c.unuse(y); \
+ JIT_COMMENT("end SET_NZCV"); \
+}
+
+#define SET_NZC \
+{ \
+ JIT_COMMENT("SET_NZC"); \
+ GpVar x = c.newGpVar(kX86VarTypeGpd); \
+ GpVar y = c.newGpVar(kX86VarTypeGpd); \
+ c.sets(x.r8Lo()); \
+ c.setz(y.r8Lo()); \
+ c.lea(x, ptr(y.r64(), x.r64(), kScale2Times)); \
+ if (cf_change) \
+ { \
+ c.lea(x, ptr(rcf.r64(), x.r64(), kScale2Times)); \
+ c.unuse(rcf); \
+ } \
+ c.movzx(y, flags_ptr); \
+ c.shl(x, 6 - cf_change); \
+ c.and_(y, cf_change?0x1F:0x3F); \
+ c.or_(x, y); \
+ c.mov(flags_ptr, x.r8Lo()); \
+ JIT_COMMENT("end SET_NZC"); \
+}
+
+#define SET_NZC_SHIFTS_ZERO(cf) \
+{ \
+ JIT_COMMENT("SET_NZC_SHIFTS_ZERO"); \
+ c.and_(flags_ptr, 0x1F); \
+ if (cf) \
+ { \
+ c.shl(rcf, 5); \
+ c.or_(rcf, 1 << 6); \
+ c.or_(flags_ptr, rcf.r8Lo()); \
+ } \
+ else \
+ c.or_(flags_ptr, 1 << 6); \
+ JIT_COMMENT("end SET_NZC_SHIFTS_ZERO"); \
+}
+
+#define SET_NZ(clear_cv) \
+{ \
+ JIT_COMMENT("SET_NZ"); \
+ GpVar x = c.newGpVar(kX86VarTypeGpz); \
+ GpVar y = c.newGpVar(kX86VarTypeGpz); \
+ c.sets(x.r8Lo()); \
+ c.setz(y.r8Lo()); \
+ c.lea(x, ptr(y.r64(), x.r64(), kScale2Times)); \
+ c.movzx(y, flags_ptr); \
+ c.and_(y, clear_cv?0x0F:0x3F); \
+ c.shl(x, 6); \
+ c.or_(x, y); \
+ c.mov(flags_ptr, x.r8Lo()); \
+ JIT_COMMENT("end SET_NZ"); \
+}
+
+#define SET_Q \
+{ \
+ JIT_COMMENT("SET_Q"); \
+ GpVar x = c.newGpVar(kX86VarTypeGpz); \
+ c.seto(x.r8Lo()); \
+ c.shl(x, 3); \
+ c.or_(flags_ptr, x.r8Lo()); \
+ JIT_COMMENT("end SET_Q"); \
+}
+
+#define S_DST_R15 \
+{ \
+ JIT_COMMENT("S_DST_R15"); \
+ GpVar SPSR = c.newGpVar(kX86VarTypeGpd); \
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd); \
+ c.mov(SPSR, cpu_ptr(SPSR.val)); \
+ c.mov(tmp, SPSR); \
+ c.and_(tmp, 0x1F); \
+ X86CompilerFuncCall *ctx = c.call(reinterpret_cast<void *>(armcpu_switchMode)); \
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder2<void, void *, uint8_t>()); \
+ ctx->setArgument(0, bb_cpu); \
+ ctx->setArgument(1, tmp); \
+ c.mov(cpu_ptr(CPSR.val), SPSR); \
+ c.and_(SPSR, 1 << 5); \
+ c.shr(SPSR, 5); \
+ c.lea(tmp, ptr_abs(reinterpret_cast<void *>(0xFFFFFFFC), SPSR.r64(), kScale2Times)); \
+ c.and_(tmp, reg_ptr(15)); \
+ c.mov(cpu_ptr(next_instruction), tmp); \
+ c.unuse(tmp); \
+ JIT_COMMENT("end S_DST_R15"); \
+}
+
+// ============================================================================================= IMM
+#define LSL_IMM \
+ JIT_COMMENT("LSL_IMM"); \
+ bool rhs_is_imm = false; \
+ uint32_t imm = (i >> 7) & 0x1F; \
+ GpVar rhs = c.newGpVar(kX86VarTypeGpd); \
+ c.mov(rhs, reg_pos_ptr(0)); \
+ if (imm) \
+ c.shl(rhs, imm); \
+ uint32_t rhs_first = cpu->R[REG_POS(i, 0)] << imm;
+
+#define S_LSL_IMM \
+ JIT_COMMENT("S_LSL_IMM"); \
+ bool rhs_is_imm = false; \
+ uint8_t cf_change = 0; \
+ GpVar rcf; \
+ GpVar rhs = c.newGpVar(kX86VarTypeGpd); \
+ uint32_t imm = (i >> 7)&0x1F; \
+ c.mov(rhs, reg_pos_ptr(0)); \
+ if (imm) \
+ { \
+ cf_change = 1; \
+ c.shl(rhs, imm); \
+ rcf = c.newGpVar(kX86VarTypeGpd); \
+ c.setc(rcf.r8Lo()); \
+ }
+
+#define LSR_IMM \
+ JIT_COMMENT("LSR_IMM"); \
+ bool rhs_is_imm = false; \
+ uint32_t imm = (i >> 7) & 0x1F; \
+ GpVar rhs = c.newGpVar(kX86VarTypeGpd); \
+ if (imm) \
+ { \
+ c.mov(rhs, reg_pos_ptr(0)); \
+ c.shr(rhs, imm); \
+ } \
+ else \
+ c.mov(rhs, 0); \
+ uint32_t rhs_first = imm ? cpu->R[REG_POS(i, 0)] >> imm : 0;
+
+#define S_LSR_IMM \
+ JIT_COMMENT("S_LSR_IMM"); \
+ bool rhs_is_imm = false; \
+ uint8_t cf_change = 1; \
+ GpVar rcf = c.newGpVar(kX86VarTypeGpd); \
+ GpVar rhs = c.newGpVar(kX86VarTypeGpd); \
+ uint32_t imm = (i >> 7) & 0x1F; \
+ c.mov(rhs, reg_pos_ptr(0)); \
+ if (!imm) \
+ { \
+ c.test(rhs, 1 << 31); \
+ c.setnz(rcf.r8Lo()); \
+ c.xor_(rhs, rhs); \
+ } \
+ else \
+ { \
+ c.shr(rhs, imm); \
+ c.setc(rcf.r8Lo()); \
+ }
+
+#define ASR_IMM \
+ JIT_COMMENT("ASR_IMM"); \
+ bool rhs_is_imm = false; \
+ uint32_t imm = (i >> 7) & 0x1F; \
+ GpVar rhs = c.newGpVar(kX86VarTypeGpd); \
+ c.mov(rhs, reg_pos_ptr(0)); \
+ if (!imm) \
+ imm = 31; \
+ c.sar(rhs, imm); \
+ uint32_t rhs_first = static_cast<int32_t>(cpu->R[REG_POS(i, 0)]) >> imm;
+
+#define S_ASR_IMM \
+ JIT_COMMENT("S_ASR_IMM"); \
+ bool rhs_is_imm = false; \
+ uint8_t cf_change = 1; \
+ GpVar rcf = c.newGpVar(kX86VarTypeGpd); \
+ GpVar rhs = c.newGpVar(kX86VarTypeGpd); \
+ uint32_t imm = (i >> 7) & 0x1F; \
+ c.mov(rhs, reg_pos_ptr(0)); \
+ if (!imm) \
+ imm = 31; \
+ c.sar(rhs, imm); \
+ imm == 31 ? c.sets(rcf.r8Lo()) : c.setc(rcf.r8Lo());
+
+#define ROR_IMM \
+ JIT_COMMENT("ROR_IMM"); \
+ bool rhs_is_imm = false; \
+ uint32_t imm = (i >> 7) & 0x1F; \
+ GpVar rhs = c.newGpVar(kX86VarTypeGpd); \
+ c.mov(rhs, reg_pos_ptr(0)); \
+ if (!imm) \
+ { \
+ c.bt(flags_ptr, 5); \
+ c.rcr(rhs, 1); \
+ } \
+ else \
+ c.ror(rhs, imm); \
+ uint32_t rhs_first = imm ? ROR(cpu->R[REG_POS(i, 0)], imm) : (static_cast<uint32_t>(cpu->CPSR.bits.C) << 31) | (cpu->R[REG_POS(i, 0)] >> 1);
+
+#define S_ROR_IMM \
+ JIT_COMMENT("S_ROR_IMM"); \
+ bool rhs_is_imm = false; \
+ uint8_t cf_change = 1; \
+ GpVar rcf = c.newGpVar(kX86VarTypeGpd); \
+ GpVar rhs = c.newGpVar(kX86VarTypeGpd); \
+ uint32_t imm = (i >> 7) & 0x1F; \
+ c.mov(rhs, reg_pos_ptr(0)); \
+ if (!imm) \
+ { \
+ c.bt(flags_ptr, 5); \
+ c.rcr(rhs, 1); \
+ } \
+ else \
+ c.ror(rhs, imm); \
+ c.setc(rcf.r8Lo());
+
+#define REG_OFF \
+ JIT_COMMENT("REG_OFF"); \
+ bool rhs_is_imm = false; \
+ Mem rhs = reg_pos_ptr(0); \
+ uint32_t rhs_first = cpu->R[REG_POS(i, 0)];
+
+#define IMM_VAL \
+ JIT_COMMENT("IMM_VAL"); \
+ bool rhs_is_imm = true; \
+ uint32_t rhs = ROR(i & 0xFF, (i >> 7) & 0x1E); \
+ uint32_t rhs_first = rhs;
+
+#define S_IMM_VAL \
+ JIT_COMMENT("S_IMM_VAL"); \
+ bool rhs_is_imm = true; \
+ uint8_t cf_change = 0; \
+ GpVar rcf; \
+ uint32_t rhs = ROR(i & 0xFF, (i >> 7) & 0x1E); \
+ if ((i >> 8) & 0xF) \
+ { \
+ cf_change = 1; \
+ rcf = c.newGpVar(kX86VarTypeGpd); \
+ c.mov(rcf, BIT31(rhs)); \
+ } \
+ uint32_t rhs_first = rhs;
+
+#define IMM_OFF \
+ JIT_COMMENT("IMM_OFF"); \
+ bool rhs_is_imm = true; \
+ uint32_t rhs = ((i >> 4) & 0xF0) + (i & 0xF); \
+ uint32_t rhs_first = rhs;
+
+#define IMM_OFF_12 \
+ JIT_COMMENT("IMM_OFF_12"); \
+ bool rhs_is_imm = true; \
+ uint32_t rhs = i & 0xFFF; \
+ uint32_t rhs_first = rhs;
+
+// ============================================================================================= REG
+#define LSX_REG(name, x86inst, sign) \
+ JIT_COMMENT(#name); \
+ bool rhs_is_imm = false; \
+ GpVar rhs = c.newGpVar(kX86VarTypeGpd); \
+ GpVar imm = c.newGpVar(kX86VarTypeGpz); \
+ GpVar tmp = c.newGpVar(kX86VarTypeGpz); \
+ if (sign) \
+ c.mov(tmp, 31); \
+ else \
+ c.mov(tmp, 0); \
+ c.movzx(imm, reg_pos_ptrB(8)); \
+ c.mov(rhs, reg_pos_ptr(0)); \
+ c.cmp(imm, 31); \
+ if (sign) \
+ c.cmovg(imm, tmp); \
+ else \
+ c.cmovg(rhs, tmp); \
+ c.x86inst(rhs, imm); \
+ c.unuse(tmp);
+
+#define S_LSX_REG(name, x86inst, sign) \
+ JIT_COMMENT(#name); \
+ bool rhs_is_imm = false; \
+ uint8_t cf_change = 1; \
+ GpVar rcf = c.newGpVar(kX86VarTypeGpd); \
+ GpVar rhs = c.newGpVar(kX86VarTypeGpd); \
+ GpVar imm = c.newGpVar(kX86VarTypeGpz); \
+ Label __zero = c.newLabel(); \
+ Label __lt32 = c.newLabel(); \
+ Label __done = c.newLabel(); \
+ c.mov(imm, reg_pos_ptr(8)); \
+ c.mov(rhs, reg_pos_ptr(0)); \
+ c.and_(imm, 0xFF); \
+ c.jz(__zero); \
+ c.cmp(imm, 32); \
+ c.jl(__lt32); \
+ if (!sign) \
+ { \
+ Label __eq32 = c.newLabel(); \
+ c.je(__eq32); \
+ /* imm > 32 */ \
+ c.mov(rhs, 0); \
+ c.mov(rcf, 0); \
+ c.jmp(__done); \
+ /* imm == 32 */ \
+ c.bind(__eq32); \
+ } \
+ c.x86inst(rhs, 31); \
+ c.x86inst(rhs, 1); \
+ c.setc(rcf.r8Lo()); \
+ c.jmp(__done); \
+ /* imm == 0 */ \
+ c.bind(__zero); \
+ c.test(flags_ptr, 1 << 5); \
+ c.setnz(rcf.r8Lo()); \
+ c.jmp(__done); \
+ /* imm < 32 */ \
+ c.bind(__lt32); \
+ c.x86inst(rhs, imm); \
+ c.setc(rcf.r8Lo()); \
+ /* done */ \
+ c.bind(__done);
+
+#define LSL_REG LSX_REG(LSL_REG, shl, 0)
+#define LSR_REG LSX_REG(LSR_REG, shr, 0)
+#define ASR_REG LSX_REG(ASR_REG, sar, 1)
+#define S_LSL_REG S_LSX_REG(S_LSL_REG, shl, 0)
+#define S_LSR_REG S_LSX_REG(S_LSR_REG, shr, 0)
+#define S_ASR_REG S_LSX_REG(S_ASR_REG, sar, 1)
+
+#define ROR_REG \
+ JIT_COMMENT("ROR_REG"); \
+ bool rhs_is_imm = false; \
+ GpVar rhs = c.newGpVar(kX86VarTypeGpd); \
+ GpVar imm = c.newGpVar(kX86VarTypeGpz); \
+ c.mov(rhs, reg_pos_ptr(0)); \
+ c.mov(imm, reg_pos_ptrB(8)); \
+ c.ror(rhs, imm.r8Lo());
+
+#define S_ROR_REG \
+ JIT_COMMENT("S_ROR_REG"); \
+ bool rhs_is_imm = false; \
+ bool cf_change = 1; \
+ GpVar rcf = c.newGpVar(kX86VarTypeGpd); \
+ GpVar imm = c.newGpVar(kX86VarTypeGpz); \
+ GpVar rhs = c.newGpVar(kX86VarTypeGpd); \
+ Label __zero = c.newLabel(); \
+ Label __zero_1F = c.newLabel(); \
+ Label __done = c.newLabel(); \
+ c.mov(imm, reg_pos_ptr(8)); \
+ c.mov(rhs, reg_pos_ptr(0)); \
+ c.and_(imm, 0xFF); \
+ c.jz(__zero);\
+ c.and_(imm, 0x1F); \
+ c.jz(__zero_1F);\
+ /* imm&0x1F != 0 */ \
+ c.ror(rhs, imm); \
+ c.setc(rcf.r8Lo()); \
+ c.jmp(__done); \
+ /* imm&0x1F == 0 */ \
+ c.bind(__zero_1F); \
+ c.test(rhs, 1 << 31); \
+ c.setnz(rcf.r8Lo()); \
+ c.jmp(__done); \
+ /* imm == 0 */ \
+ c.bind(__zero); \
+ c.test(flags_ptr, 1 << 5); \
+ c.setnz(rcf.r8Lo()); \
+ /* done */ \
+ c.bind(__done);
+
+// ==================================================================== common funcs
+static void emit_MMU_aluMemCycles(int alu_cycles, GpVar mem_cycles, int population)
+{
+ if (PROCNUM == ARMCPU_ARM9)
+ {
+ if (population < alu_cycles)
+ {
+ GpVar x = c.newGpVar(kX86VarTypeGpd);
+ c.mov(x, alu_cycles);
+ c.cmp(mem_cycles, alu_cycles);
+ c.cmovl(mem_cycles, x);
+ }
+ }
+ else
+ c.add(mem_cycles, alu_cycles);
+}
+
+// -----------------------------------------------------------------------------
+// OPs
+// -----------------------------------------------------------------------------
+#define OP_ARITHMETIC(arg, x86inst, symmetric, flags) \
+ arg; \
+ GpVar lhs = c.newGpVar(kX86VarTypeGpd); \
+ if (REG_POS(i, 12) == REG_POS(i, 16)) \
+ c.x86inst(reg_pos_ptr(12), rhs); \
+ else if (symmetric && !rhs_is_imm) \
+ { \
+ c.x86inst(*reinterpret_cast<GpVar *>(&rhs), reg_pos_ptr(16)); \
+ c.mov(reg_pos_ptr(12), rhs); \
+ } \
+ else \
+ { \
+ c.mov(lhs, reg_pos_ptr(16)); \
+ c.x86inst(lhs, rhs); \
+ c.mov(reg_pos_ptr(12), lhs); \
+ } \
+ if (flags) \
+ { \
+ if (REG_POS(i, 12) == 15) \
+ { \
+ S_DST_R15; \
+ bb_constant_cycles += 2; \
+ return 1; \
+ } \
+ SET_NZCV(!symmetric); \
+ } \
+ else \
+ { \
+ if (REG_POS(i, 12) == 15) \
+ { \
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd); \
+ c.mov(tmp, reg_ptr(15)); \
+ c.mov(cpu_ptr(next_instruction), tmp); \
+ bb_constant_cycles += 2; \
+ } \
+ } \
+ return 1;
+
+#define OP_ARITHMETIC_R(arg, x86inst, flags) \
+ arg; \
+ GpVar lhs = c.newGpVar(kX86VarTypeGpd); \
+ c.mov(lhs, rhs); \
+ c.x86inst(lhs, reg_pos_ptr(16)); \
+ c.mov(reg_pos_ptr(12), lhs); \
+ if (flags) \
+ { \
+ if (REG_POS(i, 12) == 15) \
+ { \
+ S_DST_R15; \
+ bb_constant_cycles += 2; \
+ return 1; \
+ } \
+ SET_NZCV(1); \
+ } \
+ else \
+ { \
+ if (REG_POS(i, 12) == 15) \
+ { \
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd); \
+ c.mov(cpu_ptr(next_instruction), lhs); \
+ bb_constant_cycles += 2; \
+ } \
+ } \
+ return 1;
+
+#define OP_ARITHMETIC_S(arg, x86inst, symmetric) \
+ arg; \
+ if (REG_POS(i, 12) == REG_POS(i, 16)) \
+ c.x86inst(reg_pos_ptr(12), rhs); \
+ else if (symmetric && !rhs_is_imm) \
+ { \
+ c.x86inst(*reinterpret_cast<GpVar *>(&rhs), reg_pos_ptr(16)); \
+ c.mov(reg_pos_ptr(12), rhs); \
+ } \
+ else \
+ { \
+ GpVar lhs = c.newGpVar(kX86VarTypeGpd); \
+ c.mov(lhs, reg_pos_ptr(16)); \
+ c.x86inst(lhs, rhs); \
+ c.mov(reg_pos_ptr(12), lhs); \
+ } \
+ if (REG_POS(i, 12) == 15) \
+ { \
+ S_DST_R15; \
+ bb_constant_cycles += 2; \
+ return 1; \
+ } \
+ SET_NZC; \
+ return 1;
+
+#define GET_CARRY(invert) \
+{ \
+ c.bt(flags_ptr, 5); \
+ if (invert) \
+ c.cmc(); \
+}
+
+static int OP_AND_LSL_IMM(uint32_t i) { OP_ARITHMETIC(LSL_IMM, and_, 1, 0); }
+static int OP_AND_LSL_REG(uint32_t i) { OP_ARITHMETIC(LSL_REG, and_, 1, 0); }
+static int OP_AND_LSR_IMM(uint32_t i) { OP_ARITHMETIC(LSR_IMM, and_, 1, 0); }
+static int OP_AND_LSR_REG(uint32_t i) { OP_ARITHMETIC(LSR_REG, and_, 1, 0); }
+static int OP_AND_ASR_IMM(uint32_t i) { OP_ARITHMETIC(ASR_IMM, and_, 1, 0); }
+static int OP_AND_ASR_REG(uint32_t i) { OP_ARITHMETIC(ASR_REG, and_, 1, 0); }
+static int OP_AND_ROR_IMM(uint32_t i) { OP_ARITHMETIC(ROR_IMM, and_, 1, 0); }
+static int OP_AND_ROR_REG(uint32_t i) { OP_ARITHMETIC(ROR_REG, and_, 1, 0); }
+static int OP_AND_IMM_VAL(uint32_t i) { OP_ARITHMETIC(IMM_VAL, and_, 1, 0); }
+
+static int OP_EOR_LSL_IMM(uint32_t i) { OP_ARITHMETIC(LSL_IMM, xor_, 1, 0); }
+static int OP_EOR_LSL_REG(uint32_t i) { OP_ARITHMETIC(LSL_REG, xor_, 1, 0); }
+static int OP_EOR_LSR_IMM(uint32_t i) { OP_ARITHMETIC(LSR_IMM, xor_, 1, 0); }
+static int OP_EOR_LSR_REG(uint32_t i) { OP_ARITHMETIC(LSR_REG, xor_, 1, 0); }
+static int OP_EOR_ASR_IMM(uint32_t i) { OP_ARITHMETIC(ASR_IMM, xor_, 1, 0); }
+static int OP_EOR_ASR_REG(uint32_t i) { OP_ARITHMETIC(ASR_REG, xor_, 1, 0); }
+static int OP_EOR_ROR_IMM(uint32_t i) { OP_ARITHMETIC(ROR_IMM, xor_, 1, 0); }
+static int OP_EOR_ROR_REG(uint32_t i) { OP_ARITHMETIC(ROR_REG, xor_, 1, 0); }
+static int OP_EOR_IMM_VAL(uint32_t i) { OP_ARITHMETIC(IMM_VAL, xor_, 1, 0); }
+
+static int OP_ORR_LSL_IMM(uint32_t i) { OP_ARITHMETIC(LSL_IMM, or_, 1, 0); }
+static int OP_ORR_LSL_REG(uint32_t i) { OP_ARITHMETIC(LSL_REG, or_, 1, 0); }
+static int OP_ORR_LSR_IMM(uint32_t i) { OP_ARITHMETIC(LSR_IMM, or_, 1, 0); }
+static int OP_ORR_LSR_REG(uint32_t i) { OP_ARITHMETIC(LSR_REG, or_, 1, 0); }
+static int OP_ORR_ASR_IMM(uint32_t i) { OP_ARITHMETIC(ASR_IMM, or_, 1, 0); }
+static int OP_ORR_ASR_REG(uint32_t i) { OP_ARITHMETIC(ASR_REG, or_, 1, 0); }
+static int OP_ORR_ROR_IMM(uint32_t i) { OP_ARITHMETIC(ROR_IMM, or_, 1, 0); }
+static int OP_ORR_ROR_REG(uint32_t i) { OP_ARITHMETIC(ROR_REG, or_, 1, 0); }
+static int OP_ORR_IMM_VAL(uint32_t i) { OP_ARITHMETIC(IMM_VAL, or_, 1, 0); }
+
+static int OP_ADD_LSL_IMM(uint32_t i) { OP_ARITHMETIC(LSL_IMM, add, 1, 0); }
+static int OP_ADD_LSL_REG(uint32_t i) { OP_ARITHMETIC(LSL_REG, add, 1, 0); }
+static int OP_ADD_LSR_IMM(uint32_t i) { OP_ARITHMETIC(LSR_IMM, add, 1, 0); }
+static int OP_ADD_LSR_REG(uint32_t i) { OP_ARITHMETIC(LSR_REG, add, 1, 0); }
+static int OP_ADD_ASR_IMM(uint32_t i) { OP_ARITHMETIC(ASR_IMM, add, 1, 0); }
+static int OP_ADD_ASR_REG(uint32_t i) { OP_ARITHMETIC(ASR_REG, add, 1, 0); }
+static int OP_ADD_ROR_IMM(uint32_t i) { OP_ARITHMETIC(ROR_IMM, add, 1, 0); }
+static int OP_ADD_ROR_REG(uint32_t i) { OP_ARITHMETIC(ROR_REG, add, 1, 0); }
+static int OP_ADD_IMM_VAL(uint32_t i) { OP_ARITHMETIC(IMM_VAL, add, 1, 0); }
+
+static int OP_SUB_LSL_IMM(uint32_t i) { OP_ARITHMETIC(LSL_IMM, sub, 0, 0); }
+static int OP_SUB_LSL_REG(uint32_t i) { OP_ARITHMETIC(LSL_REG, sub, 0, 0); }
+static int OP_SUB_LSR_IMM(uint32_t i) { OP_ARITHMETIC(LSR_IMM, sub, 0, 0); }
+static int OP_SUB_LSR_REG(uint32_t i) { OP_ARITHMETIC(LSR_REG, sub, 0, 0); }
+static int OP_SUB_ASR_IMM(uint32_t i) { OP_ARITHMETIC(ASR_IMM, sub, 0, 0); }
+static int OP_SUB_ASR_REG(uint32_t i) { OP_ARITHMETIC(ASR_REG, sub, 0, 0); }
+static int OP_SUB_ROR_IMM(uint32_t i) { OP_ARITHMETIC(ROR_IMM, sub, 0, 0); }
+static int OP_SUB_ROR_REG(uint32_t i) { OP_ARITHMETIC(ROR_REG, sub, 0, 0); }
+static int OP_SUB_IMM_VAL(uint32_t i) { OP_ARITHMETIC(IMM_VAL, sub, 0, 0); }
+
+static int OP_RSB_LSL_IMM(uint32_t i) { OP_ARITHMETIC_R(LSL_IMM, sub, 0); }
+static int OP_RSB_LSL_REG(uint32_t i) { OP_ARITHMETIC_R(LSL_REG, sub, 0); }
+static int OP_RSB_LSR_IMM(uint32_t i) { OP_ARITHMETIC_R(LSR_IMM, sub, 0); }
+static int OP_RSB_LSR_REG(uint32_t i) { OP_ARITHMETIC_R(LSR_REG, sub, 0); }
+static int OP_RSB_ASR_IMM(uint32_t i) { OP_ARITHMETIC_R(ASR_IMM, sub, 0); }
+static int OP_RSB_ASR_REG(uint32_t i) { OP_ARITHMETIC_R(ASR_REG, sub, 0); }
+static int OP_RSB_ROR_IMM(uint32_t i) { OP_ARITHMETIC_R(ROR_IMM, sub, 0); }
+static int OP_RSB_ROR_REG(uint32_t i) { OP_ARITHMETIC_R(ROR_REG, sub, 0); }
+static int OP_RSB_IMM_VAL(uint32_t i) { OP_ARITHMETIC_R(IMM_VAL, sub, 0); }
+
+// ================================ S instructions
+static int OP_AND_S_LSL_IMM(uint32_t i) { OP_ARITHMETIC_S(S_LSL_IMM, and_, 1); }
+static int OP_AND_S_LSL_REG(uint32_t i) { OP_ARITHMETIC_S(S_LSL_REG, and_, 1); }
+static int OP_AND_S_LSR_IMM(uint32_t i) { OP_ARITHMETIC_S(S_LSR_IMM, and_, 1); }
+static int OP_AND_S_LSR_REG(uint32_t i) { OP_ARITHMETIC_S(S_LSR_REG, and_, 1); }
+static int OP_AND_S_ASR_IMM(uint32_t i) { OP_ARITHMETIC_S(S_ASR_IMM, and_, 1); }
+static int OP_AND_S_ASR_REG(uint32_t i) { OP_ARITHMETIC_S(S_ASR_REG, and_, 1); }
+static int OP_AND_S_ROR_IMM(uint32_t i) { OP_ARITHMETIC_S(S_ROR_IMM, and_, 1); }
+static int OP_AND_S_ROR_REG(uint32_t i) { OP_ARITHMETIC_S(S_ROR_REG, and_, 1); }
+static int OP_AND_S_IMM_VAL(uint32_t i) { OP_ARITHMETIC_S(S_IMM_VAL, and_, 1); }
+
+static int OP_EOR_S_LSL_IMM(uint32_t i) { OP_ARITHMETIC_S(S_LSL_IMM, xor_, 1); }
+static int OP_EOR_S_LSL_REG(uint32_t i) { OP_ARITHMETIC_S(S_LSL_REG, xor_, 1); }
+static int OP_EOR_S_LSR_IMM(uint32_t i) { OP_ARITHMETIC_S(S_LSR_IMM, xor_, 1); }
+static int OP_EOR_S_LSR_REG(uint32_t i) { OP_ARITHMETIC_S(S_LSR_REG, xor_, 1); }
+static int OP_EOR_S_ASR_IMM(uint32_t i) { OP_ARITHMETIC_S(S_ASR_IMM, xor_, 1); }
+static int OP_EOR_S_ASR_REG(uint32_t i) { OP_ARITHMETIC_S(S_ASR_REG, xor_, 1); }
+static int OP_EOR_S_ROR_IMM(uint32_t i) { OP_ARITHMETIC_S(S_ROR_IMM, xor_, 1); }
+static int OP_EOR_S_ROR_REG(uint32_t i) { OP_ARITHMETIC_S(S_ROR_REG, xor_, 1); }
+static int OP_EOR_S_IMM_VAL(uint32_t i) { OP_ARITHMETIC_S(S_IMM_VAL, xor_, 1); }
+
+static int OP_ORR_S_LSL_IMM(uint32_t i) { OP_ARITHMETIC_S(S_LSL_IMM, or_, 1); }
+static int OP_ORR_S_LSL_REG(uint32_t i) { OP_ARITHMETIC_S(S_LSL_REG, or_, 1); }
+static int OP_ORR_S_LSR_IMM(uint32_t i) { OP_ARITHMETIC_S(S_LSR_IMM, or_, 1); }
+static int OP_ORR_S_LSR_REG(uint32_t i) { OP_ARITHMETIC_S(S_LSR_REG, or_, 1); }
+static int OP_ORR_S_ASR_IMM(uint32_t i) { OP_ARITHMETIC_S(S_ASR_IMM, or_, 1); }
+static int OP_ORR_S_ASR_REG(uint32_t i) { OP_ARITHMETIC_S(S_ASR_REG, or_, 1); }
+static int OP_ORR_S_ROR_IMM(uint32_t i) { OP_ARITHMETIC_S(S_ROR_IMM, or_, 1); }
+static int OP_ORR_S_ROR_REG(uint32_t i) { OP_ARITHMETIC_S(S_ROR_REG, or_, 1); }
+static int OP_ORR_S_IMM_VAL(uint32_t i) { OP_ARITHMETIC_S(S_IMM_VAL, or_, 1); }
+
+static int OP_ADD_S_LSL_IMM(uint32_t i) { OP_ARITHMETIC(LSL_IMM, add, 1, 1); }
+static int OP_ADD_S_LSL_REG(uint32_t i) { OP_ARITHMETIC(LSL_REG, add, 1, 1); }
+static int OP_ADD_S_LSR_IMM(uint32_t i) { OP_ARITHMETIC(LSR_IMM, add, 1, 1); }
+static int OP_ADD_S_LSR_REG(uint32_t i) { OP_ARITHMETIC(LSR_REG, add, 1, 1); }
+static int OP_ADD_S_ASR_IMM(uint32_t i) { OP_ARITHMETIC(ASR_IMM, add, 1, 1); }
+static int OP_ADD_S_ASR_REG(uint32_t i) { OP_ARITHMETIC(ASR_REG, add, 1, 1); }
+static int OP_ADD_S_ROR_IMM(uint32_t i) { OP_ARITHMETIC(ROR_IMM, add, 1, 1); }
+static int OP_ADD_S_ROR_REG(uint32_t i) { OP_ARITHMETIC(ROR_REG, add, 1, 1); }
+static int OP_ADD_S_IMM_VAL(uint32_t i) { OP_ARITHMETIC(IMM_VAL, add, 1, 1); }
+
+static int OP_SUB_S_LSL_IMM(uint32_t i) { OP_ARITHMETIC(LSL_IMM, sub, 0, 1); }
+static int OP_SUB_S_LSL_REG(uint32_t i) { OP_ARITHMETIC(LSL_REG, sub, 0, 1); }
+static int OP_SUB_S_LSR_IMM(uint32_t i) { OP_ARITHMETIC(LSR_IMM, sub, 0, 1); }
+static int OP_SUB_S_LSR_REG(uint32_t i) { OP_ARITHMETIC(LSR_REG, sub, 0, 1); }
+static int OP_SUB_S_ASR_IMM(uint32_t i) { OP_ARITHMETIC(ASR_IMM, sub, 0, 1); }
+static int OP_SUB_S_ASR_REG(uint32_t i) { OP_ARITHMETIC(ASR_REG, sub, 0, 1); }
+static int OP_SUB_S_ROR_IMM(uint32_t i) { OP_ARITHMETIC(ROR_IMM, sub, 0, 1); }
+static int OP_SUB_S_ROR_REG(uint32_t i) { OP_ARITHMETIC(ROR_REG, sub, 0, 1); }
+static int OP_SUB_S_IMM_VAL(uint32_t i) { OP_ARITHMETIC(IMM_VAL, sub, 0, 1); }
+
+static int OP_RSB_S_LSL_IMM(uint32_t i) { OP_ARITHMETIC_R(LSL_IMM, sub, 1); }
+static int OP_RSB_S_LSL_REG(uint32_t i) { OP_ARITHMETIC_R(LSL_REG, sub, 1); }
+static int OP_RSB_S_LSR_IMM(uint32_t i) { OP_ARITHMETIC_R(LSR_IMM, sub, 1); }
+static int OP_RSB_S_LSR_REG(uint32_t i) { OP_ARITHMETIC_R(LSR_REG, sub, 1); }
+static int OP_RSB_S_ASR_IMM(uint32_t i) { OP_ARITHMETIC_R(ASR_IMM, sub, 1); }
+static int OP_RSB_S_ASR_REG(uint32_t i) { OP_ARITHMETIC_R(ASR_REG, sub, 1); }
+static int OP_RSB_S_ROR_IMM(uint32_t i) { OP_ARITHMETIC_R(ROR_IMM, sub, 1); }
+static int OP_RSB_S_ROR_REG(uint32_t i) { OP_ARITHMETIC_R(ROR_REG, sub, 1); }
+static int OP_RSB_S_IMM_VAL(uint32_t i) { OP_ARITHMETIC_R(IMM_VAL, sub, 1); }
+
+static int OP_ADC_LSL_IMM(uint32_t i) { OP_ARITHMETIC(LSL_IMM; GET_CARRY(0), adc, 1, 0); }
+static int OP_ADC_LSL_REG(uint32_t i) { OP_ARITHMETIC(LSL_REG; GET_CARRY(0), adc, 1, 0); }
+static int OP_ADC_LSR_IMM(uint32_t i) { OP_ARITHMETIC(LSR_IMM; GET_CARRY(0), adc, 1, 0); }
+static int OP_ADC_LSR_REG(uint32_t i) { OP_ARITHMETIC(LSR_REG; GET_CARRY(0), adc, 1, 0); }
+static int OP_ADC_ASR_IMM(uint32_t i) { OP_ARITHMETIC(ASR_IMM; GET_CARRY(0), adc, 1, 0); }
+static int OP_ADC_ASR_REG(uint32_t i) { OP_ARITHMETIC(ASR_REG; GET_CARRY(0), adc, 1, 0); }
+static int OP_ADC_ROR_IMM(uint32_t i) { OP_ARITHMETIC(ROR_IMM; GET_CARRY(0), adc, 1, 0); }
+static int OP_ADC_ROR_REG(uint32_t i) { OP_ARITHMETIC(ROR_REG; GET_CARRY(0), adc, 1, 0); }
+static int OP_ADC_IMM_VAL(uint32_t i) { OP_ARITHMETIC(IMM_VAL; GET_CARRY(0), adc, 1, 0); }
+
+static int OP_ADC_S_LSL_IMM(uint32_t i) { OP_ARITHMETIC(LSL_IMM; GET_CARRY(0), adc, 1, 1); }
+static int OP_ADC_S_LSL_REG(uint32_t i) { OP_ARITHMETIC(LSL_REG; GET_CARRY(0), adc, 1, 1); }
+static int OP_ADC_S_LSR_IMM(uint32_t i) { OP_ARITHMETIC(LSR_IMM; GET_CARRY(0), adc, 1, 1); }
+static int OP_ADC_S_LSR_REG(uint32_t i) { OP_ARITHMETIC(LSR_REG; GET_CARRY(0), adc, 1, 1); }
+static int OP_ADC_S_ASR_IMM(uint32_t i) { OP_ARITHMETIC(ASR_IMM; GET_CARRY(0), adc, 1, 1); }
+static int OP_ADC_S_ASR_REG(uint32_t i) { OP_ARITHMETIC(ASR_REG; GET_CARRY(0), adc, 1, 1); }
+static int OP_ADC_S_ROR_IMM(uint32_t i) { OP_ARITHMETIC(ROR_IMM; GET_CARRY(0), adc, 1, 1); }
+static int OP_ADC_S_ROR_REG(uint32_t i) { OP_ARITHMETIC(ROR_REG; GET_CARRY(0), adc, 1, 1); }
+static int OP_ADC_S_IMM_VAL(uint32_t i) { OP_ARITHMETIC(IMM_VAL; GET_CARRY(0), adc, 1, 1); }
+
+static int OP_SBC_LSL_IMM(uint32_t i) { OP_ARITHMETIC(LSL_IMM; GET_CARRY(1), sbb, 0, 0); }
+static int OP_SBC_LSL_REG(uint32_t i) { OP_ARITHMETIC(LSL_REG; GET_CARRY(1), sbb, 0, 0); }
+static int OP_SBC_LSR_IMM(uint32_t i) { OP_ARITHMETIC(LSR_IMM; GET_CARRY(1), sbb, 0, 0); }
+static int OP_SBC_LSR_REG(uint32_t i) { OP_ARITHMETIC(LSR_REG; GET_CARRY(1), sbb, 0, 0); }
+static int OP_SBC_ASR_IMM(uint32_t i) { OP_ARITHMETIC(ASR_IMM; GET_CARRY(1), sbb, 0, 0); }
+static int OP_SBC_ASR_REG(uint32_t i) { OP_ARITHMETIC(ASR_REG; GET_CARRY(1), sbb, 0, 0); }
+static int OP_SBC_ROR_IMM(uint32_t i) { OP_ARITHMETIC(ROR_IMM; GET_CARRY(1), sbb, 0, 0); }
+static int OP_SBC_ROR_REG(uint32_t i) { OP_ARITHMETIC(ROR_REG; GET_CARRY(1), sbb, 0, 0); }
+static int OP_SBC_IMM_VAL(uint32_t i) { OP_ARITHMETIC(IMM_VAL; GET_CARRY(1), sbb, 0, 0); }
+
+static int OP_SBC_S_LSL_IMM(uint32_t i) { OP_ARITHMETIC(LSL_IMM; GET_CARRY(1), sbb, 0, 1); }
+static int OP_SBC_S_LSL_REG(uint32_t i) { OP_ARITHMETIC(LSL_REG; GET_CARRY(1), sbb, 0, 1); }
+static int OP_SBC_S_LSR_IMM(uint32_t i) { OP_ARITHMETIC(LSR_IMM; GET_CARRY(1), sbb, 0, 1); }
+static int OP_SBC_S_LSR_REG(uint32_t i) { OP_ARITHMETIC(LSR_REG; GET_CARRY(1), sbb, 0, 1); }
+static int OP_SBC_S_ASR_IMM(uint32_t i) { OP_ARITHMETIC(ASR_IMM; GET_CARRY(1), sbb, 0, 1); }
+static int OP_SBC_S_ASR_REG(uint32_t i) { OP_ARITHMETIC(ASR_REG; GET_CARRY(1), sbb, 0, 1); }
+static int OP_SBC_S_ROR_IMM(uint32_t i) { OP_ARITHMETIC(ROR_IMM; GET_CARRY(1), sbb, 0, 1); }
+static int OP_SBC_S_ROR_REG(uint32_t i) { OP_ARITHMETIC(ROR_REG; GET_CARRY(1), sbb, 0, 1); }
+static int OP_SBC_S_IMM_VAL(uint32_t i) { OP_ARITHMETIC(IMM_VAL; GET_CARRY(1), sbb, 0, 1); }
+
+static int OP_RSC_LSL_IMM(uint32_t i) { OP_ARITHMETIC_R(LSL_IMM; GET_CARRY(1), sbb, 0); }
+static int OP_RSC_LSL_REG(uint32_t i) { OP_ARITHMETIC_R(LSL_REG; GET_CARRY(1), sbb, 0); }
+static int OP_RSC_LSR_IMM(uint32_t i) { OP_ARITHMETIC_R(LSR_IMM; GET_CARRY(1), sbb, 0); }
+static int OP_RSC_LSR_REG(uint32_t i) { OP_ARITHMETIC_R(LSR_REG; GET_CARRY(1), sbb, 0); }
+static int OP_RSC_ASR_IMM(uint32_t i) { OP_ARITHMETIC_R(ASR_IMM; GET_CARRY(1), sbb, 0); }
+static int OP_RSC_ASR_REG(uint32_t i) { OP_ARITHMETIC_R(ASR_REG; GET_CARRY(1), sbb, 0); }
+static int OP_RSC_ROR_IMM(uint32_t i) { OP_ARITHMETIC_R(ROR_IMM; GET_CARRY(1), sbb, 0); }
+static int OP_RSC_ROR_REG(uint32_t i) { OP_ARITHMETIC_R(ROR_REG; GET_CARRY(1), sbb, 0); }
+static int OP_RSC_IMM_VAL(uint32_t i) { OP_ARITHMETIC_R(IMM_VAL; GET_CARRY(1), sbb, 0); }
+
+static int OP_RSC_S_LSL_IMM(uint32_t i) { OP_ARITHMETIC_R(LSL_IMM; GET_CARRY(1), sbb, 1); }
+static int OP_RSC_S_LSL_REG(uint32_t i) { OP_ARITHMETIC_R(LSL_REG; GET_CARRY(1), sbb, 1); }
+static int OP_RSC_S_LSR_IMM(uint32_t i) { OP_ARITHMETIC_R(LSR_IMM; GET_CARRY(1), sbb, 1); }
+static int OP_RSC_S_LSR_REG(uint32_t i) { OP_ARITHMETIC_R(LSR_REG; GET_CARRY(1), sbb, 1); }
+static int OP_RSC_S_ASR_IMM(uint32_t i) { OP_ARITHMETIC_R(ASR_IMM; GET_CARRY(1), sbb, 1); }
+static int OP_RSC_S_ASR_REG(uint32_t i) { OP_ARITHMETIC_R(ASR_REG; GET_CARRY(1), sbb, 1); }
+static int OP_RSC_S_ROR_IMM(uint32_t i) { OP_ARITHMETIC_R(ROR_IMM; GET_CARRY(1), sbb, 1); }
+static int OP_RSC_S_ROR_REG(uint32_t i) { OP_ARITHMETIC_R(ROR_REG; GET_CARRY(1), sbb, 1); }
+static int OP_RSC_S_IMM_VAL(uint32_t i) { OP_ARITHMETIC_R(IMM_VAL; GET_CARRY(1), sbb, 1); }
+
+static int OP_BIC_LSL_IMM(uint32_t i) { OP_ARITHMETIC(LSL_IMM; c.not_(rhs), and_, 1, 0); }
+static int OP_BIC_LSL_REG(uint32_t i) { OP_ARITHMETIC(LSL_REG; c.not_(rhs), and_, 1, 0); }
+static int OP_BIC_LSR_IMM(uint32_t i) { OP_ARITHMETIC(LSR_IMM; c.not_(rhs), and_, 1, 0); }
+static int OP_BIC_LSR_REG(uint32_t i) { OP_ARITHMETIC(LSR_REG; c.not_(rhs), and_, 1, 0); }
+static int OP_BIC_ASR_IMM(uint32_t i) { OP_ARITHMETIC(ASR_IMM; c.not_(rhs), and_, 1, 0); }
+static int OP_BIC_ASR_REG(uint32_t i) { OP_ARITHMETIC(ASR_REG; c.not_(rhs), and_, 1, 0); }
+static int OP_BIC_ROR_IMM(uint32_t i) { OP_ARITHMETIC(ROR_IMM; c.not_(rhs), and_, 1, 0); }
+static int OP_BIC_ROR_REG(uint32_t i) { OP_ARITHMETIC(ROR_REG; c.not_(rhs), and_, 1, 0); }
+static int OP_BIC_IMM_VAL(uint32_t i) { OP_ARITHMETIC(IMM_VAL; rhs = ~rhs, and_, 1, 0); }
+
+static int OP_BIC_S_LSL_IMM(uint32_t i) { OP_ARITHMETIC_S(S_LSL_IMM; c.not_(rhs), and_, 1); }
+static int OP_BIC_S_LSL_REG(uint32_t i) { OP_ARITHMETIC_S(S_LSL_REG; c.not_(rhs), and_, 1); }
+static int OP_BIC_S_LSR_IMM(uint32_t i) { OP_ARITHMETIC_S(S_LSR_IMM; c.not_(rhs), and_, 1); }
+static int OP_BIC_S_LSR_REG(uint32_t i) { OP_ARITHMETIC_S(S_LSR_REG; c.not_(rhs), and_, 1); }
+static int OP_BIC_S_ASR_IMM(uint32_t i) { OP_ARITHMETIC_S(S_ASR_IMM; c.not_(rhs), and_, 1); }
+static int OP_BIC_S_ASR_REG(uint32_t i) { OP_ARITHMETIC_S(S_ASR_REG; c.not_(rhs), and_, 1); }
+static int OP_BIC_S_ROR_IMM(uint32_t i) { OP_ARITHMETIC_S(S_ROR_IMM; c.not_(rhs), and_, 1); }
+static int OP_BIC_S_ROR_REG(uint32_t i) { OP_ARITHMETIC_S(S_ROR_REG; c.not_(rhs), and_, 1); }
+static int OP_BIC_S_IMM_VAL(uint32_t i) { OP_ARITHMETIC_S(S_IMM_VAL; rhs = ~rhs, and_, 1); }
+
+// -----------------------------------------------------------------------------
+// TST
+// -----------------------------------------------------------------------------
+#define OP_TST_(arg) \
+ arg; \
+ c.test(reg_pos_ptr(16), rhs); \
+ SET_NZC; \
+ return 1;
+
+static int OP_TST_LSL_IMM(uint32_t i) { OP_TST_(S_LSL_IMM); }
+static int OP_TST_LSL_REG(uint32_t i) { OP_TST_(S_LSL_REG); }
+static int OP_TST_LSR_IMM(uint32_t i) { OP_TST_(S_LSR_IMM); }
+static int OP_TST_LSR_REG(uint32_t i) { OP_TST_(S_LSR_REG); }
+static int OP_TST_ASR_IMM(uint32_t i) { OP_TST_(S_ASR_IMM); }
+static int OP_TST_ASR_REG(uint32_t i) { OP_TST_(S_ASR_REG); }
+static int OP_TST_ROR_IMM(uint32_t i) { OP_TST_(S_ROR_IMM); }
+static int OP_TST_ROR_REG(uint32_t i) { OP_TST_(S_ROR_REG); }
+static int OP_TST_IMM_VAL(uint32_t i) { OP_TST_(S_IMM_VAL); }
+
+// -----------------------------------------------------------------------------
+// TEQ
+// -----------------------------------------------------------------------------
+#define OP_TEQ_(arg) \
+ arg; \
+ if (!rhs_is_imm) \
+ c.xor_(*reinterpret_cast<GpVar *>(&rhs), reg_pos_ptr(16)); \
+ else \
+ { \
+ GpVar x = c.newGpVar(kX86VarTypeGpd); \
+ c.mov(x, rhs); \
+ c.xor_(x, reg_pos_ptr(16)); \
+ } \
+ SET_NZC; \
+ return 1;
+
+static int OP_TEQ_LSL_IMM(uint32_t i) { OP_TEQ_(S_LSL_IMM); }
+static int OP_TEQ_LSL_REG(uint32_t i) { OP_TEQ_(S_LSL_REG); }
+static int OP_TEQ_LSR_IMM(uint32_t i) { OP_TEQ_(S_LSR_IMM); }
+static int OP_TEQ_LSR_REG(uint32_t i) { OP_TEQ_(S_LSR_REG); }
+static int OP_TEQ_ASR_IMM(uint32_t i) { OP_TEQ_(S_ASR_IMM); }
+static int OP_TEQ_ASR_REG(uint32_t i) { OP_TEQ_(S_ASR_REG); }
+static int OP_TEQ_ROR_IMM(uint32_t i) { OP_TEQ_(S_ROR_IMM); }
+static int OP_TEQ_ROR_REG(uint32_t i) { OP_TEQ_(S_ROR_REG); }
+static int OP_TEQ_IMM_VAL(uint32_t i) { OP_TEQ_(S_IMM_VAL); }
+
+// -----------------------------------------------------------------------------
+// CMP
+// -----------------------------------------------------------------------------
+#define OP_CMP(arg) \
+ arg; \
+ c.cmp(reg_pos_ptr(16), rhs); \
+ SET_NZCV(1); \
+ return 1;
+
+static int OP_CMP_LSL_IMM(uint32_t i) { OP_CMP(LSL_IMM); }
+static int OP_CMP_LSL_REG(uint32_t i) { OP_CMP(LSL_REG); }
+static int OP_CMP_LSR_IMM(uint32_t i) { OP_CMP(LSR_IMM); }
+static int OP_CMP_LSR_REG(uint32_t i) { OP_CMP(LSR_REG); }
+static int OP_CMP_ASR_IMM(uint32_t i) { OP_CMP(ASR_IMM); }
+static int OP_CMP_ASR_REG(uint32_t i) { OP_CMP(ASR_REG); }
+static int OP_CMP_ROR_IMM(uint32_t i) { OP_CMP(ROR_IMM); }
+static int OP_CMP_ROR_REG(uint32_t i) { OP_CMP(ROR_REG); }
+static int OP_CMP_IMM_VAL(uint32_t i) { OP_CMP(IMM_VAL); }
+
+#undef OP_CMP
+
+// -----------------------------------------------------------------------------
+// CMN
+// -----------------------------------------------------------------------------
+#define OP_CMN(arg) \
+ arg; \
+ uint32_t rhs_imm = *reinterpret_cast<uint32_t *>(&rhs); \
+ int sign = rhs_is_imm && (rhs_imm != -rhs_imm); \
+ if (sign) \
+ c.cmp(reg_pos_ptr(16), -rhs_imm); \
+ else \
+ { \
+ GpVar lhs = c.newGpVar(kX86VarTypeGpd); \
+ c.mov(lhs, reg_pos_ptr(16)); \
+ c.add(lhs, rhs); \
+ } \
+ SET_NZCV(sign); \
+ return 1;
+
+static int OP_CMN_LSL_IMM(uint32_t i) { OP_CMN(LSL_IMM); }
+static int OP_CMN_LSL_REG(uint32_t i) { OP_CMN(LSL_REG); }
+static int OP_CMN_LSR_IMM(uint32_t i) { OP_CMN(LSR_IMM); }
+static int OP_CMN_LSR_REG(uint32_t i) { OP_CMN(LSR_REG); }
+static int OP_CMN_ASR_IMM(uint32_t i) { OP_CMN(ASR_IMM); }
+static int OP_CMN_ASR_REG(uint32_t i) { OP_CMN(ASR_REG); }
+static int OP_CMN_ROR_IMM(uint32_t i) { OP_CMN(ROR_IMM); }
+static int OP_CMN_ROR_REG(uint32_t i) { OP_CMN(ROR_REG); }
+static int OP_CMN_IMM_VAL(uint32_t i) { OP_CMN(IMM_VAL); }
+
+#undef OP_CMN
+
+// -----------------------------------------------------------------------------
+// MOV
+// -----------------------------------------------------------------------------
+#define OP_MOV(arg) \
+ arg; \
+ c.mov(reg_pos_ptr(12), rhs); \
+ if (REG_POS(i, 12) == 15) \
+ { \
+ c.mov(cpu_ptr(next_instruction), rhs); \
+ return 1; \
+ } \
+ return 1;
+
+static int OP_MOV_LSL_IMM(uint32_t i) { if (i == 0xE1A00000) { /* nop */ JIT_COMMENT("nop"); return 1; } OP_MOV(LSL_IMM); }
+static int OP_MOV_LSL_REG(uint32_t i) { OP_MOV(LSL_REG; if (REG_POS(i, 0) == 15) c.add(rhs, 4);); }
+static int OP_MOV_LSR_IMM(uint32_t i) { OP_MOV(LSR_IMM); }
+static int OP_MOV_LSR_REG(uint32_t i) { OP_MOV(LSR_REG; if (REG_POS(i, 0) == 15) c.add(rhs, 4);); }
+static int OP_MOV_ASR_IMM(uint32_t i) { OP_MOV(ASR_IMM); }
+static int OP_MOV_ASR_REG(uint32_t i) { OP_MOV(ASR_REG); }
+static int OP_MOV_ROR_IMM(uint32_t i) { OP_MOV(ROR_IMM); }
+static int OP_MOV_ROR_REG(uint32_t i) { OP_MOV(ROR_REG); }
+static int OP_MOV_IMM_VAL(uint32_t i) { OP_MOV(IMM_VAL); }
+
+#define OP_MOV_S(arg) \
+ arg; \
+ c.mov(reg_pos_ptr(12), rhs); \
+ if (REG_POS(i, 12) == 15) \
+ { \
+ S_DST_R15; \
+ bb_constant_cycles += 2; \
+ return 1; \
+ } \
+ if (!rhs_is_imm) \
+ c.cmp(*reinterpret_cast<GpVar *>(&rhs), 0); \
+ else \
+ c.cmp(reg_pos_ptr(12), 0); \
+ SET_NZC; \
+ return 1;
+
+static int OP_MOV_S_LSL_IMM(uint32_t i) { OP_MOV_S(S_LSL_IMM); }
+static int OP_MOV_S_LSL_REG(uint32_t i) { OP_MOV_S(S_LSL_REG; if (REG_POS(i, 0) == 15) c.add(rhs, 4);); }
+static int OP_MOV_S_LSR_IMM(uint32_t i) { OP_MOV_S(S_LSR_IMM); }
+static int OP_MOV_S_LSR_REG(uint32_t i) { OP_MOV_S(S_LSR_REG; if (REG_POS(i, 0) == 15) c.add(rhs, 4);); }
+static int OP_MOV_S_ASR_IMM(uint32_t i) { OP_MOV_S(S_ASR_IMM); }
+static int OP_MOV_S_ASR_REG(uint32_t i) { OP_MOV_S(S_ASR_REG); }
+static int OP_MOV_S_ROR_IMM(uint32_t i) { OP_MOV_S(S_ROR_IMM); }
+static int OP_MOV_S_ROR_REG(uint32_t i) { OP_MOV_S(S_ROR_REG); }
+static int OP_MOV_S_IMM_VAL(uint32_t i) { OP_MOV_S(S_IMM_VAL); }
+
+// -----------------------------------------------------------------------------
+// MVN
+// -----------------------------------------------------------------------------
+static int OP_MVN_LSL_IMM(uint32_t i) { OP_MOV(LSL_IMM; c.not_(rhs)); }
+static int OP_MVN_LSL_REG(uint32_t i) { OP_MOV(LSL_REG; c.not_(rhs)); }
+static int OP_MVN_LSR_IMM(uint32_t i) { OP_MOV(LSR_IMM; c.not_(rhs)); }
+static int OP_MVN_LSR_REG(uint32_t i) { OP_MOV(LSR_REG; c.not_(rhs)); }
+static int OP_MVN_ASR_IMM(uint32_t i) { OP_MOV(ASR_IMM; c.not_(rhs)); }
+static int OP_MVN_ASR_REG(uint32_t i) { OP_MOV(ASR_REG; c.not_(rhs)); }
+static int OP_MVN_ROR_IMM(uint32_t i) { OP_MOV(ROR_IMM; c.not_(rhs)); }
+static int OP_MVN_ROR_REG(uint32_t i) { OP_MOV(ROR_REG; c.not_(rhs)); }
+static int OP_MVN_IMM_VAL(uint32_t i) { OP_MOV(IMM_VAL; rhs = ~rhs); }
+
+static int OP_MVN_S_LSL_IMM(uint32_t i) { OP_MOV_S(S_LSL_IMM; c.not_(rhs)); }
+static int OP_MVN_S_LSL_REG(uint32_t i) { OP_MOV_S(S_LSL_REG; c.not_(rhs)); }
+static int OP_MVN_S_LSR_IMM(uint32_t i) { OP_MOV_S(S_LSR_IMM; c.not_(rhs)); }
+static int OP_MVN_S_LSR_REG(uint32_t i) { OP_MOV_S(S_LSR_REG; c.not_(rhs)); }
+static int OP_MVN_S_ASR_IMM(uint32_t i) { OP_MOV_S(S_ASR_IMM; c.not_(rhs)); }
+static int OP_MVN_S_ASR_REG(uint32_t i) { OP_MOV_S(S_ASR_REG; c.not_(rhs)); }
+static int OP_MVN_S_ROR_IMM(uint32_t i) { OP_MOV_S(S_ROR_IMM; c.not_(rhs)); }
+static int OP_MVN_S_ROR_REG(uint32_t i) { OP_MOV_S(S_ROR_REG; c.not_(rhs)); }
+static int OP_MVN_S_IMM_VAL(uint32_t i) { OP_MOV_S(S_IMM_VAL; rhs = ~rhs); }
+
+//- ----------------------------------------------------------------------------
+// QADD / QDADD / QSUB / QDSUB
+// -----------------------------------------------------------------------------
+// TODO
+static int OP_QADD(uint32_t i) { printf("JIT: unimplemented OP_QADD\n"); return 0; }
+static int OP_QSUB(uint32_t i) { printf("JIT: unimplemented OP_QSUB\n"); return 0; }
+static int OP_QDADD(uint32_t i) { printf("JIT: unimplemented OP_QDADD\n"); return 0; }
+static int OP_QDSUB(uint32_t i) { printf("JIT: unimplemented OP_QDSUB\n"); return 0; }
+
+// -----------------------------------------------------------------------------
+// MUL
+// -----------------------------------------------------------------------------
+static void MUL_Mxx_END(GpVar x, bool sign, int cycles)
+{
+ if (sign)
+ {
+ GpVar y = c.newGpVar(kX86VarTypeGpd);
+ c.mov(y, x);
+ c.sar(x, 31);
+ c.xor_(x, y);
+ }
+ c.or_(x, 1);
+ c.bsr(bb_cycles, x);
+ c.shr(bb_cycles, 3);
+ c.add(bb_cycles, cycles + 1);
+}
+
+#define OP_MUL_(op, width, sign, accum, flags) \
+ GpVar lhs = c.newGpVar(kX86VarTypeGpd); \
+ GpVar rhs = c.newGpVar(kX86VarTypeGpd); \
+ GpVar hi; \
+ if (width) \
+ { \
+ hi = c.newGpVar(kX86VarTypeGpd); \
+ c.xor_(hi, hi); \
+ } \
+ c.mov(lhs, reg_pos_ptr(0)); \
+ c.mov(rhs, reg_pos_ptr(8)); \
+ op; \
+ if (width && accum) \
+ { \
+ if (flags) \
+ { \
+ c.add(lhs, reg_pos_ptr(12)); \
+ c.adc(hi, reg_pos_ptr(16)); \
+ c.mov(reg_pos_ptr(12), lhs); \
+ c.mov(reg_pos_ptr(16), hi); \
+ c.cmp(hi, lhs); \
+ SET_NZ(0); \
+ } \
+ else \
+ { \
+ c.add(reg_pos_ptr(12), lhs); \
+ c.adc(reg_pos_ptr(16), hi); \
+ } \
+ } \
+ else if (width) \
+ { \
+ c.mov(reg_pos_ptr(12), lhs); \
+ c.mov(reg_pos_ptr(16), hi); \
+ if (flags) \
+ { \
+ c.cmp(hi, lhs); \
+ SET_NZ(0); \
+ } \
+ } \
+ else \
+ { \
+ if (accum) \
+ c.add(lhs, reg_pos_ptr(12)); \
+ c.mov(reg_pos_ptr(16), lhs); \
+ if (flags) \
+ { \
+ c.cmp(lhs, 0); \
+ SET_NZ(0); \
+ } \
+ } \
+ MUL_Mxx_END(rhs, sign, 1 + width + accum); \
+ return 1;
+
+static int OP_MUL(uint32_t i) { OP_MUL_(c.imul(lhs,rhs), 0, 1, 0, 0); }
+static int OP_MLA(uint32_t i) { OP_MUL_(c.imul(lhs,rhs), 0, 1, 1, 0); }
+static int OP_UMULL(uint32_t i) { OP_MUL_(c.mul(hi,lhs,rhs), 1, 0, 0, 0); }
+static int OP_UMLAL(uint32_t i) { OP_MUL_(c.mul(hi,lhs,rhs), 1, 0, 1, 0); }
+static int OP_SMULL(uint32_t i) { OP_MUL_(c.imul(hi,lhs,rhs), 1, 1, 0, 0); }
+static int OP_SMLAL(uint32_t i) { OP_MUL_(c.imul(hi,lhs,rhs), 1, 1, 1, 0); }
+
+static int OP_MUL_S(uint32_t i) { OP_MUL_(c.imul(lhs,rhs), 0, 1, 0, 1); }
+static int OP_MLA_S(uint32_t i) { OP_MUL_(c.imul(lhs,rhs), 0, 1, 1, 1); }
+static int OP_UMULL_S(uint32_t i) { OP_MUL_(c.mul(hi,lhs,rhs), 1, 0, 0, 1); }
+static int OP_UMLAL_S(uint32_t i) { OP_MUL_(c.mul(hi,lhs,rhs), 1, 0, 1, 1); }
+static int OP_SMULL_S(uint32_t i) { OP_MUL_(c.imul(hi,lhs,rhs), 1, 1, 0, 1); }
+static int OP_SMLAL_S(uint32_t i) { OP_MUL_(c.imul(hi,lhs,rhs), 1, 1, 1, 1); }
+
+#define OP_MULxy_(op, x, y, width, accum, flags) \
+ GpVar lhs = c.newGpVar(kX86VarTypeGpd); \
+ GpVar rhs = c.newGpVar(kX86VarTypeGpd); \
+ GpVar hi; \
+ c.movsx(lhs, reg_pos_ptr##x(0)); \
+ c.movsx(rhs, reg_pos_ptr##y(8)); \
+ if (width) \
+ hi = c.newGpVar(kX86VarTypeGpd); \
+ op; \
+ if (width && accum) \
+ { \
+ if (flags) \
+ { \
+ c.add(lhs, reg_pos_ptr(12)); \
+ c.adc(hi, reg_pos_ptr(16)); \
+ c.mov(reg_pos_ptr(12), lhs); \
+ c.mov(reg_pos_ptr(16), hi); \
+ SET_Q; \
+ } \
+ else \
+ { \
+ c.add(reg_pos_ptr(12), lhs); \
+ c.adc(reg_pos_ptr(16), hi); \
+ } \
+ } \
+ else if (width) \
+ { \
+ c.mov(reg_pos_ptr(12), lhs); \
+ c.mov(reg_pos_ptr(16), hi); \
+ if (flags) \
+ SET_Q; \
+ } \
+ else \
+ { \
+ if (accum) \
+ c.add(lhs, reg_pos_ptr(12)); \
+ c.mov(reg_pos_ptr(16), lhs); \
+ if (flags) \
+ SET_Q; \
+ } \
+ return 1;
+
+
+// -----------------------------------------------------------------------------
+// SMUL
+// -----------------------------------------------------------------------------
+static int OP_SMUL_B_B(uint32_t i) { OP_MULxy_(c.imul(lhs, rhs), L, L, 0, 0, 0); }
+static int OP_SMUL_B_T(uint32_t i) { OP_MULxy_(c.imul(lhs, rhs), L, H, 0, 0, 0); }
+static int OP_SMUL_T_B(uint32_t i) { OP_MULxy_(c.imul(lhs, rhs), H, L, 0, 0, 0); }
+static int OP_SMUL_T_T(uint32_t i) { OP_MULxy_(c.imul(lhs, rhs), H, H, 0, 0, 0); }
+
+// -----------------------------------------------------------------------------
+// SMLA
+// -----------------------------------------------------------------------------
+static int OP_SMLA_B_B(uint32_t i) { OP_MULxy_(c.imul(lhs, rhs), L, L, 0, 1, 1); }
+static int OP_SMLA_B_T(uint32_t i) { OP_MULxy_(c.imul(lhs, rhs), L, H, 0, 1, 1); }
+static int OP_SMLA_T_B(uint32_t i) { OP_MULxy_(c.imul(lhs, rhs), H, L, 0, 1, 1); }
+static int OP_SMLA_T_T(uint32_t i) { OP_MULxy_(c.imul(lhs, rhs), H, H, 0, 1, 1); }
+
+// -----------------------------------------------------------------------------
+// SMLAL
+// -----------------------------------------------------------------------------
+static int OP_SMLAL_B_B(uint32_t i) { OP_MULxy_(c.imul(hi,lhs,rhs), L, L, 1, 1, 1); }
+static int OP_SMLAL_B_T(uint32_t i) { OP_MULxy_(c.imul(hi,lhs,rhs), L, H, 1, 1, 1); }
+static int OP_SMLAL_T_B(uint32_t i) { OP_MULxy_(c.imul(hi,lhs,rhs), H, L, 1, 1, 1); }
+static int OP_SMLAL_T_T(uint32_t i) { OP_MULxy_(c.imul(hi,lhs,rhs), H, H, 1, 1, 1); }
+
+// -----------------------------------------------------------------------------
+// SMULW / SMLAW
+// -----------------------------------------------------------------------------
+#ifdef ASMJIT_X64
+#define OP_SMxxW_(x, accum, flags) \
+ GpVar lhs = c.newGpVar(kX86VarTypeGpz); \
+ GpVar rhs = c.newGpVar(kX86VarTypeGpz); \
+ c.movsx(lhs, reg_pos_ptr##x(8)); \
+ c.movsxd(rhs, reg_pos_ptr(0)); \
+ c.imul(lhs, rhs); \
+ c.sar(lhs, 16); \
+ if (accum) \
+ c.add(lhs, reg_pos_ptr(12)); \
+ c.mov(reg_pos_ptr(16), lhs.r32()); \
+ if (flags) \
+ SET_Q; \
+ return 1;
+#else
+#define OP_SMxxW_(x, accum, flags) \
+ GpVar lhs = c.newGpVar(kX86VarTypeGpd); \
+ GpVar rhs = c.newGpVar(kX86VarTypeGpd); \
+ GpVar hi = c.newGpVar(kX86VarTypeGpd); \
+ c.movsx(lhs, reg_pos_ptr##x(8)); \
+ c.mov(rhs, reg_pos_ptr(0)); \
+ c.imul(hi, lhs, rhs); \
+ c.shr(lhs, 16); \
+ c.shl(hi, 16); \
+ c.or_(lhs, hi); \
+ if (accum) \
+ c.add(lhs, reg_pos_ptr(12)); \
+ c.mov(reg_pos_ptr(16), lhs); \
+ if (flags) \
+ SET_Q; \
+ return 1;
+#endif
+
+static int OP_SMULW_B(uint32_t i) { OP_SMxxW_(L, 0, 0); }
+static int OP_SMULW_T(uint32_t i) { OP_SMxxW_(H, 0, 0); }
+static int OP_SMLAW_B(uint32_t i) { OP_SMxxW_(L, 1, 1); }
+static int OP_SMLAW_T(uint32_t i) { OP_SMxxW_(H, 1, 1); }
+
+// -----------------------------------------------------------------------------
+// MRS / MSR
+// -----------------------------------------------------------------------------
+static int OP_MRS_CPSR(uint32_t i)
+{
+ GpVar x = c.newGpVar(kX86VarTypeGpd);
+ c.mov(x, cpu_ptr(CPSR));
+ c.mov(reg_pos_ptr(12), x);
+ return 1;
+}
+
+static int OP_MRS_SPSR(uint32_t i)
+{
+ GpVar x = c.newGpVar(kX86VarTypeGpd);
+ c.mov(x, cpu_ptr(SPSR));
+ c.mov(reg_pos_ptr(12), x);
+ return 1;
+}
+
+// TODO: SPSR: if(cpu->CPSR.bits.mode == USR || cpu->CPSR.bits.mode == SYS) return 1;
+#define OP_MSR_(reg, args, sw) \
+ GpVar operand = c.newGpVar(kX86VarTypeGpd); \
+ args; \
+ switch ((i >> 16) & 0xF) \
+ { \
+ case 0x1: /* bit 16 */ \
+ { \
+ GpVar mode = c.newGpVar(kX86VarTypeGpd); \
+ Label __skip = c.newLabel(); \
+ c.mov(mode, cpu_ptr(CPSR)); \
+ c.and_(mode, 0x1F); \
+ c.cmp(mode, USR); \
+ c.je(__skip); \
+ if (sw) \
+ { \
+ c.mov(mode, rhs); \
+ c.and_(mode, 0x1F); \
+ X86CompilerFuncCall* ctx = c.call(reinterpret_cast<void *>(armcpu_switchMode)); \
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder2<void, void *, uint8_t>()); \
+ ctx->setArgument(0, bb_cpu); \
+ ctx->setArgument(1, mode); \
+ } \
+ c.mov(operand, rhs); \
+ Mem xPSR_memB = cpu_ptr_byte(reg, 0); \
+ c.mov(xPSR_memB, operand.r8Lo()); \
+ changeCPSR; \
+ c.bind(__skip); \
+ return 1; \
+ } \
+ case 0x2: /* bit 17 */ \
+ { \
+ GpVar mode = c.newGpVar(kX86VarTypeGpd); \
+ Label __skip = c.newLabel(); \
+ c.mov(mode, cpu_ptr(CPSR)); \
+ c.and_(mode, 0x1F); \
+ c.cmp(mode, USR); \
+ c.je(__skip); \
+ c.mov(operand, rhs); \
+ Mem xPSR_memB = cpu_ptr_byte(reg, 1); \
+ c.shr(operand, 8); \
+ c.mov(xPSR_memB, operand.r8Lo()); \
+ changeCPSR; \
+ c.bind(__skip); \
+ return 1; \
+ } \
+ case 0x4: /* bit 18 */ \
+ { \
+ GpVar mode = c.newGpVar(kX86VarTypeGpd); \
+ Label __skip = c.newLabel(); \
+ c.mov(mode, cpu_ptr(CPSR)); \
+ c.and_(mode, 0x1F); \
+ c.cmp(mode, USR); \
+ c.je(__skip); \
+ c.mov(operand, rhs); \
+ Mem xPSR_memB = cpu_ptr_byte(reg, 2); \
+ c.shr(operand, 16); \
+ c.mov(xPSR_memB, operand.r8Lo()); \
+ changeCPSR; \
+ c.bind(__skip); \
+ return 1; \
+ } \
+ case 0x8: /* bit 19 */ \
+ { \
+ c.mov(operand, rhs); \
+ Mem xPSR_memB = cpu_ptr_byte(reg, 3); \
+ c.shr(operand, 24); \
+ c.mov(xPSR_memB, operand.r8Lo()); \
+ changeCPSR; \
+ return 1; \
+ } \
+ } \
+\
+ static uint32_t byte_mask = (BIT16(i) ? 0x000000FF : 0x00000000) | (BIT17(i) ? 0x0000FF00 : 0x00000000) | (BIT18(i) ? 0x00FF0000 : 0x00000000) | (BIT19(i) ? 0xFF000000 : 0x00000000); \
+ static uint32_t byte_mask_USR = BIT19(i) ? 0xFF000000 : 0x00000000; \
+\
+ Mem xPSR_mem = cpu_ptr(reg.val); \
+ GpVar xPSR = c.newGpVar(kX86VarTypeGpd); \
+ GpVar mode = c.newGpVar(kX86VarTypeGpd); \
+ Label __USR = c.newLabel(); \
+ Label __done = c.newLabel(); \
+ c.mov(mode, cpu_ptr(CPSR.val)); \
+ c.and_(mode, 0x1F); \
+ c.cmp(mode, USR); \
+ c.je(__USR); \
+ /* mode != USR */ \
+ if (sw && BIT16(i)) \
+ { \
+ /* armcpu_switchMode */ \
+ c.mov(mode, rhs); \
+ c.and_(mode, 0x1F); \
+ X86CompilerFuncCall* ctx = c.call(reinterpret_cast<void *>(armcpu_switchMode)); \
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder2<void, void *, uint8_t>()); \
+ ctx->setArgument(0, bb_cpu); \
+ ctx->setArgument(1, mode); \
+ } \
+ /* cpu->CPSR.val = (cpu->CPSR.val & ~byte_mask) | (operand & byte_mask); */ \
+ c.mov(operand, rhs); \
+ c.mov(xPSR, xPSR_mem); \
+ c.and_(operand, byte_mask); \
+ c.and_(xPSR, ~byte_mask); \
+ c.or_(xPSR, operand); \
+ c.mov(xPSR_mem, xPSR); \
+ c.jmp(__done); \
+ /* mode == USR */ \
+ c.bind(__USR); \
+ c.mov(operand, rhs); \
+ c.mov(xPSR, xPSR_mem); \
+ c.and_(operand, byte_mask_USR); \
+ c.and_(xPSR, ~byte_mask_USR); \
+ c.or_(xPSR, operand); \
+ c.mov(xPSR_mem, xPSR); \
+ c.bind(__done); \
+ changeCPSR; \
+ return 1;
+
+static int OP_MSR_CPSR(uint32_t i) { OP_MSR_(CPSR, REG_OFF, 1); }
+static int OP_MSR_SPSR(uint32_t i) { OP_MSR_(SPSR, REG_OFF, 0); }
+static int OP_MSR_CPSR_IMM_VAL(uint32_t i) { OP_MSR_(CPSR, IMM_VAL, 1); }
+static int OP_MSR_SPSR_IMM_VAL(uint32_t i) { OP_MSR_(SPSR, IMM_VAL, 0); }
+
+// -----------------------------------------------------------------------------
+// LDR
+// -----------------------------------------------------------------------------
+typedef uint32_t (FASTCALL *OpLDR)(uint32_t, uint32_t *);
+
+// 98% of all memory accesses land in the same region as the first execution of
+// that instruction, so keep multiple copies with different fastpaths.
+// The copies don't need to differ in any way; the point is merely to cooperate
+// with x86 branch prediction.
+
+enum
+{
+ MEMTYPE_GENERIC, // no assumptions
+ MEMTYPE_MAIN,
+ MEMTYPE_DTCM,
+ MEMTYPE_ERAM,
+ MEMTYPE_SWIRAM,
+ MEMTYPE_OTHER // memory that is known to not be MAIN, DTCM, ERAM, or SWIRAM
+};
+
+static uint32_t classify_adr(uint32_t adr, bool store)
+{
+ if (PROCNUM == ARMCPU_ARM9 && (adr & ~0x3FFF) == MMU.DTCMRegion)
+ return MEMTYPE_DTCM;
+ else if ((adr & 0x0F000000) == 0x02000000)
+ return MEMTYPE_MAIN;
+ else if (PROCNUM == ARMCPU_ARM7 && !store && (adr & 0xFF800000) == 0x03800000)
+ return MEMTYPE_ERAM;
+ else if (PROCNUM == ARMCPU_ARM7 && !store && (adr & 0xFF800000) == 0x03000000)
+ return MEMTYPE_SWIRAM;
+ else
+ return MEMTYPE_GENERIC;
+}
+
+template<int PROCNUM, int memtype> static uint32_t FASTCALL OP_LDR(uint32_t adr, uint32_t *dstreg)
+{
+ uint32_t data = READ32(cpu->mem_if->data, adr);
+ if (adr & 3)
+ data = ROR(data, 8 * (adr & 3));
+ *dstreg = data;
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_READ>(3, adr);
+}
+
+template<int PROCNUM, int memtype> static uint32_t FASTCALL OP_LDRH(uint32_t adr, uint32_t *dstreg)
+{
+ *dstreg = READ16(cpu->mem_if->data, adr);
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+template<int PROCNUM, int memtype> static uint32_t FASTCALL OP_LDRSH(uint32_t adr, uint32_t *dstreg)
+{
+ *dstreg = static_cast<int16_t>(READ16(cpu->mem_if->data, adr));
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+template<int PROCNUM, int memtype> static uint32_t FASTCALL OP_LDRB(uint32_t adr, uint32_t *dstreg)
+{
+ *dstreg = READ8(cpu->mem_if->data, adr);
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+template<int PROCNUM, int memtype> static uint32_t FASTCALL OP_LDRSB(uint32_t adr, uint32_t *dstreg)
+{
+ *dstreg = static_cast<int8_t>(READ8(cpu->mem_if->data, adr));
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+#define T(op) op<0, 0>, op<0, 1>, op<0, 2>, nullptr, nullptr, op<1, 0>, op<1, 1>, nullptr, op<1, 3>, op<1, 4>
+static const OpLDR LDR_tab[2][5] = { T(OP_LDR) };
+static const OpLDR LDRH_tab[2][5] = { T(OP_LDRH) };
+static const OpLDR LDRSH_tab[2][5] = { T(OP_LDRSH) };
+static const OpLDR LDRB_tab[2][5] = { T(OP_LDRB) };
+static const OpLDR LDRSB_tab[2][5] = { T(OP_LDRSB) };
+#undef T
+
+static uint32_t add(uint32_t lhs, uint32_t rhs) { return lhs + rhs; }
+static uint32_t sub(uint32_t lhs, uint32_t rhs) { return lhs - rhs; }
+
+#define OP_LDR_(mem_op, arg, sign_op, writeback) \
+ GpVar adr = c.newGpVar(kX86VarTypeGpd); \
+ GpVar dst = c.newGpVar(kX86VarTypeGpz); \
+ c.mov(adr, reg_pos_ptr(16)); \
+ c.lea(dst, reg_pos_ptr(12)); \
+ arg; \
+ if (!rhs_is_imm || *reinterpret_cast<uint32_t *>(&rhs)) \
+ { \
+ if (!writeback) \
+ c.sign_op(adr, rhs); \
+ else if (writeback < 0) \
+ { \
+ c.sign_op(adr, rhs); \
+ c.mov(reg_pos_ptr(16), adr); \
+ } \
+ else if (writeback > 0) \
+ { \
+ GpVar tmp_reg = c.newGpVar(kX86VarTypeGpd); \
+ c.mov(tmp_reg, adr); \
+ c.sign_op(tmp_reg, rhs); \
+ c.mov(reg_pos_ptr(16), tmp_reg); \
+ } \
+ } \
+ uint32_t adr_first = sign_op(cpu->R[REG_POS(i,16)], rhs_first); \
+ X86CompilerFuncCall *ctx = c.call(reinterpret_cast<void *>(mem_op##_tab[PROCNUM][classify_adr(adr_first, 0)])); \
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder2<uint32_t, uint32_t, uint32_t *>()); \
+ ctx->setArgument(0, adr); \
+ ctx->setArgument(1, dst); \
+ ctx->setReturn(bb_cycles); \
+ if (REG_POS(i, 12) == 15) \
+ { \
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd); \
+ c.mov(tmp, reg_ptr(15)); \
+ if (!PROCNUM) \
+ { \
+ GpVar thumb = c.newGpVar(kX86VarTypeGpz); \
+ c.movzx(thumb, reg_pos_ptrB(16)); \
+ c.and_(thumb, 1); \
+ c.shl(thumb, 5); \
+ c.or_(cpu_ptr(CPSR), thumb.r64()); \
+ c.and_(tmp, 0xFFFFFFFE); \
+ } \
+ else \
+ c.and_(tmp, 0xFFFFFFFC); \
+ c.mov(cpu_ptr(next_instruction), tmp); \
+ } \
+ return 1;
+
+// LDR
+static int OP_LDR_P_IMM_OFF(uint32_t i) { OP_LDR_(LDR, IMM_OFF_12, add, 0); }
+static int OP_LDR_M_IMM_OFF(uint32_t i) { OP_LDR_(LDR, IMM_OFF_12, sub, 0); }
+static int OP_LDR_P_LSL_IMM_OFF(uint32_t i) { OP_LDR_(LDR, LSL_IMM, add, 0); }
+static int OP_LDR_M_LSL_IMM_OFF(uint32_t i) { OP_LDR_(LDR, LSL_IMM, sub, 0); }
+static int OP_LDR_P_LSR_IMM_OFF(uint32_t i) { OP_LDR_(LDR, LSR_IMM, add, 0); }
+static int OP_LDR_M_LSR_IMM_OFF(uint32_t i) { OP_LDR_(LDR, LSR_IMM, sub, 0); }
+static int OP_LDR_P_ASR_IMM_OFF(uint32_t i) { OP_LDR_(LDR, ASR_IMM, add, 0); }
+static int OP_LDR_M_ASR_IMM_OFF(uint32_t i) { OP_LDR_(LDR, ASR_IMM, sub, 0); }
+static int OP_LDR_P_ROR_IMM_OFF(uint32_t i) { OP_LDR_(LDR, ROR_IMM, add, 0); }
+static int OP_LDR_M_ROR_IMM_OFF(uint32_t i) { OP_LDR_(LDR, ROR_IMM, sub, 0); }
+
+static int OP_LDR_P_IMM_OFF_PREIND(uint32_t i) { OP_LDR_(LDR, IMM_OFF_12, add, -1); }
+static int OP_LDR_M_IMM_OFF_PREIND(uint32_t i) { OP_LDR_(LDR, IMM_OFF_12, sub, -1); }
+static int OP_LDR_P_LSL_IMM_OFF_PREIND(uint32_t i) { OP_LDR_(LDR, LSL_IMM, add, -1); }
+static int OP_LDR_M_LSL_IMM_OFF_PREIND(uint32_t i) { OP_LDR_(LDR, LSL_IMM, sub, -1); }
+static int OP_LDR_P_LSR_IMM_OFF_PREIND(uint32_t i) { OP_LDR_(LDR, LSR_IMM, add, -1); }
+static int OP_LDR_M_LSR_IMM_OFF_PREIND(uint32_t i) { OP_LDR_(LDR, LSR_IMM, sub, -1); }
+static int OP_LDR_P_ASR_IMM_OFF_PREIND(uint32_t i) { OP_LDR_(LDR, ASR_IMM, add, -1); }
+static int OP_LDR_M_ASR_IMM_OFF_PREIND(uint32_t i) { OP_LDR_(LDR, ASR_IMM, sub, -1); }
+static int OP_LDR_P_ROR_IMM_OFF_PREIND(uint32_t i) { OP_LDR_(LDR, ROR_IMM, add, -1); }
+static int OP_LDR_M_ROR_IMM_OFF_PREIND(uint32_t i) { OP_LDR_(LDR, ROR_IMM, sub, -1); }
+static int OP_LDR_P_IMM_OFF_POSTIND(uint32_t i) { OP_LDR_(LDR, IMM_OFF_12, add, 1); }
+static int OP_LDR_M_IMM_OFF_POSTIND(uint32_t i) { OP_LDR_(LDR, IMM_OFF_12, sub, 1); }
+static int OP_LDR_P_LSL_IMM_OFF_POSTIND(uint32_t i) { OP_LDR_(LDR, LSL_IMM, add, 1); }
+static int OP_LDR_M_LSL_IMM_OFF_POSTIND(uint32_t i) { OP_LDR_(LDR, LSL_IMM, sub, 1); }
+static int OP_LDR_P_LSR_IMM_OFF_POSTIND(uint32_t i) { OP_LDR_(LDR, LSR_IMM, add, 1); }
+static int OP_LDR_M_LSR_IMM_OFF_POSTIND(uint32_t i) { OP_LDR_(LDR, LSR_IMM, sub, 1); }
+static int OP_LDR_P_ASR_IMM_OFF_POSTIND(uint32_t i) { OP_LDR_(LDR, ASR_IMM, add, 1); }
+static int OP_LDR_M_ASR_IMM_OFF_POSTIND(uint32_t i) { OP_LDR_(LDR, ASR_IMM, sub, 1); }
+static int OP_LDR_P_ROR_IMM_OFF_POSTIND(uint32_t i) { OP_LDR_(LDR, ROR_IMM, add, 1); }
+static int OP_LDR_M_ROR_IMM_OFF_POSTIND(uint32_t i) { OP_LDR_(LDR, ROR_IMM, sub, 1); }
+
+// LDRH
+static int OP_LDRH_P_IMM_OFF(uint32_t i) { OP_LDR_(LDRH, IMM_OFF, add, 0); }
+static int OP_LDRH_M_IMM_OFF(uint32_t i) { OP_LDR_(LDRH, IMM_OFF, sub, 0); }
+static int OP_LDRH_P_REG_OFF(uint32_t i) { OP_LDR_(LDRH, REG_OFF, add, 0); }
+static int OP_LDRH_M_REG_OFF(uint32_t i) { OP_LDR_(LDRH, REG_OFF, sub, 0); }
+
+static int OP_LDRH_PRE_INDE_P_IMM_OFF(uint32_t i) { OP_LDR_(LDRH, IMM_OFF, add, -1); }
+static int OP_LDRH_PRE_INDE_M_IMM_OFF(uint32_t i) { OP_LDR_(LDRH, IMM_OFF, sub, -1); }
+static int OP_LDRH_PRE_INDE_P_REG_OFF(uint32_t i) { OP_LDR_(LDRH, REG_OFF, add, -1); }
+static int OP_LDRH_PRE_INDE_M_REG_OFF(uint32_t i) { OP_LDR_(LDRH, REG_OFF, sub, -1); }
+static int OP_LDRH_POS_INDE_P_IMM_OFF(uint32_t i) { OP_LDR_(LDRH, IMM_OFF, add, 1); }
+static int OP_LDRH_POS_INDE_M_IMM_OFF(uint32_t i) { OP_LDR_(LDRH, IMM_OFF, sub, 1); }
+static int OP_LDRH_POS_INDE_P_REG_OFF(uint32_t i) { OP_LDR_(LDRH, REG_OFF, add, 1); }
+static int OP_LDRH_POS_INDE_M_REG_OFF(uint32_t i) { OP_LDR_(LDRH, REG_OFF, sub, 1); }
+
+// LDRSH
+static int OP_LDRSH_P_IMM_OFF(uint32_t i) { OP_LDR_(LDRSH, IMM_OFF, add, 0); }
+static int OP_LDRSH_M_IMM_OFF(uint32_t i) { OP_LDR_(LDRSH, IMM_OFF, sub, 0); }
+static int OP_LDRSH_P_REG_OFF(uint32_t i) { OP_LDR_(LDRSH, REG_OFF, add, 0); }
+static int OP_LDRSH_M_REG_OFF(uint32_t i) { OP_LDR_(LDRSH, REG_OFF, sub, 0); }
+
+static int OP_LDRSH_PRE_INDE_P_IMM_OFF(uint32_t i) { OP_LDR_(LDRSH, IMM_OFF, add, -1); }
+static int OP_LDRSH_PRE_INDE_M_IMM_OFF(uint32_t i) { OP_LDR_(LDRSH, IMM_OFF, sub, -1); }
+static int OP_LDRSH_PRE_INDE_P_REG_OFF(uint32_t i) { OP_LDR_(LDRSH, REG_OFF, add, -1); }
+static int OP_LDRSH_PRE_INDE_M_REG_OFF(uint32_t i) { OP_LDR_(LDRSH, REG_OFF, sub, -1); }
+static int OP_LDRSH_POS_INDE_P_IMM_OFF(uint32_t i) { OP_LDR_(LDRSH, IMM_OFF, add, 1); }
+static int OP_LDRSH_POS_INDE_M_IMM_OFF(uint32_t i) { OP_LDR_(LDRSH, IMM_OFF, sub, 1); }
+static int OP_LDRSH_POS_INDE_P_REG_OFF(uint32_t i) { OP_LDR_(LDRSH, REG_OFF, add, 1); }
+static int OP_LDRSH_POS_INDE_M_REG_OFF(uint32_t i) { OP_LDR_(LDRSH, REG_OFF, sub, 1); }
+
+// LDRB
+static int OP_LDRB_P_IMM_OFF(uint32_t i) { OP_LDR_(LDRB, IMM_OFF_12, add, 0); }
+static int OP_LDRB_M_IMM_OFF(uint32_t i) { OP_LDR_(LDRB, IMM_OFF_12, sub, 0); }
+static int OP_LDRB_P_LSL_IMM_OFF(uint32_t i) { OP_LDR_(LDRB, LSL_IMM, add, 0); }
+static int OP_LDRB_M_LSL_IMM_OFF(uint32_t i) { OP_LDR_(LDRB, LSL_IMM, sub, 0); }
+static int OP_LDRB_P_LSR_IMM_OFF(uint32_t i) { OP_LDR_(LDRB, LSR_IMM, add, 0); }
+static int OP_LDRB_M_LSR_IMM_OFF(uint32_t i) { OP_LDR_(LDRB, LSR_IMM, sub, 0); }
+static int OP_LDRB_P_ASR_IMM_OFF(uint32_t i) { OP_LDR_(LDRB, ASR_IMM, add, 0); }
+static int OP_LDRB_M_ASR_IMM_OFF(uint32_t i) { OP_LDR_(LDRB, ASR_IMM, sub, 0); }
+static int OP_LDRB_P_ROR_IMM_OFF(uint32_t i) { OP_LDR_(LDRB, ROR_IMM, add, 0); }
+static int OP_LDRB_M_ROR_IMM_OFF(uint32_t i) { OP_LDR_(LDRB, ROR_IMM, sub, 0); }
+
+static int OP_LDRB_P_IMM_OFF_PREIND(uint32_t i) { OP_LDR_(LDRB, IMM_OFF_12, add, -1); }
+static int OP_LDRB_M_IMM_OFF_PREIND(uint32_t i) { OP_LDR_(LDRB, IMM_OFF_12, sub, -1); }
+static int OP_LDRB_P_LSL_IMM_OFF_PREIND(uint32_t i) { OP_LDR_(LDRB, LSL_IMM, add, -1); }
+static int OP_LDRB_M_LSL_IMM_OFF_PREIND(uint32_t i) { OP_LDR_(LDRB, LSL_IMM, sub, -1); }
+static int OP_LDRB_P_LSR_IMM_OFF_PREIND(uint32_t i) { OP_LDR_(LDRB, LSR_IMM, add, -1); }
+static int OP_LDRB_M_LSR_IMM_OFF_PREIND(uint32_t i) { OP_LDR_(LDRB, LSR_IMM, sub, -1); }
+static int OP_LDRB_P_ASR_IMM_OFF_PREIND(uint32_t i) { OP_LDR_(LDRB, ASR_IMM, add, -1); }
+static int OP_LDRB_M_ASR_IMM_OFF_PREIND(uint32_t i) { OP_LDR_(LDRB, ASR_IMM, sub, -1); }
+static int OP_LDRB_P_ROR_IMM_OFF_PREIND(uint32_t i) { OP_LDR_(LDRB, ROR_IMM, add, -1); }
+static int OP_LDRB_M_ROR_IMM_OFF_PREIND(uint32_t i) { OP_LDR_(LDRB, ROR_IMM, sub, -1); }
+static int OP_LDRB_P_IMM_OFF_POSTIND(uint32_t i) { OP_LDR_(LDRB, IMM_OFF_12, add, 1); }
+static int OP_LDRB_M_IMM_OFF_POSTIND(uint32_t i) { OP_LDR_(LDRB, IMM_OFF_12, sub, 1); }
+static int OP_LDRB_P_LSL_IMM_OFF_POSTIND(uint32_t i) { OP_LDR_(LDRB, LSL_IMM, add, 1); }
+static int OP_LDRB_M_LSL_IMM_OFF_POSTIND(uint32_t i) { OP_LDR_(LDRB, LSL_IMM, sub, 1); }
+static int OP_LDRB_P_LSR_IMM_OFF_POSTIND(uint32_t i) { OP_LDR_(LDRB, LSR_IMM, add, 1); }
+static int OP_LDRB_M_LSR_IMM_OFF_POSTIND(uint32_t i) { OP_LDR_(LDRB, LSR_IMM, sub, 1); }
+static int OP_LDRB_P_ASR_IMM_OFF_POSTIND(uint32_t i) { OP_LDR_(LDRB, ASR_IMM, add, 1); }
+static int OP_LDRB_M_ASR_IMM_OFF_POSTIND(uint32_t i) { OP_LDR_(LDRB, ASR_IMM, sub, 1); }
+static int OP_LDRB_P_ROR_IMM_OFF_POSTIND(uint32_t i) { OP_LDR_(LDRB, ROR_IMM, add, 1); }
+static int OP_LDRB_M_ROR_IMM_OFF_POSTIND(uint32_t i) { OP_LDR_(LDRB, ROR_IMM, sub, 1); }
+
+// LDRSB
+static int OP_LDRSB_P_IMM_OFF(uint32_t i) { OP_LDR_(LDRSB, IMM_OFF, add, 0); }
+static int OP_LDRSB_M_IMM_OFF(uint32_t i) { OP_LDR_(LDRSB, IMM_OFF, sub, 0); }
+static int OP_LDRSB_P_REG_OFF(uint32_t i) { OP_LDR_(LDRSB, REG_OFF, add, 0); }
+static int OP_LDRSB_M_REG_OFF(uint32_t i) { OP_LDR_(LDRSB, REG_OFF, sub, 0); }
+
+static int OP_LDRSB_PRE_INDE_P_IMM_OFF(uint32_t i) { OP_LDR_(LDRSB, IMM_OFF, add, -1); }
+static int OP_LDRSB_PRE_INDE_M_IMM_OFF(uint32_t i) { OP_LDR_(LDRSB, IMM_OFF, sub, -1); }
+static int OP_LDRSB_PRE_INDE_P_REG_OFF(uint32_t i) { OP_LDR_(LDRSB, REG_OFF, add, -1); }
+static int OP_LDRSB_PRE_INDE_M_REG_OFF(uint32_t i) { OP_LDR_(LDRSB, REG_OFF, sub, -1); }
+static int OP_LDRSB_POS_INDE_P_IMM_OFF(uint32_t i) { OP_LDR_(LDRSB, IMM_OFF, add, 1); }
+static int OP_LDRSB_POS_INDE_M_IMM_OFF(uint32_t i) { OP_LDR_(LDRSB, IMM_OFF, sub, 1); }
+static int OP_LDRSB_POS_INDE_P_REG_OFF(uint32_t i) { OP_LDR_(LDRSB, REG_OFF, add, 1); }
+static int OP_LDRSB_POS_INDE_M_REG_OFF(uint32_t i) { OP_LDR_(LDRSB, REG_OFF, sub, 1); }
+
+// -----------------------------------------------------------------------------
+// STR
+// -----------------------------------------------------------------------------
+template<int PROCNUM, int memtype> static uint32_t FASTCALL OP_STR(uint32_t adr, uint32_t data)
+{
+ WRITE32(cpu->mem_if->data, adr, data);
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+template<int PROCNUM, int memtype> static uint32_t FASTCALL OP_STRH(uint32_t adr, uint32_t data)
+{
+ WRITE16(cpu->mem_if->data, adr, data);
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_WRITE>(2, adr);
+}
+
+template<int PROCNUM, int memtype> static uint32_t FASTCALL OP_STRB(uint32_t adr, uint32_t data)
+{
+ WRITE8(cpu->mem_if->data, adr, data);
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+typedef uint32_t (FASTCALL *OpSTR)(uint32_t, uint32_t);
+#define T(op) op<0, 0>, op<0, 1>, op<0, 2>, op<1, 0>, op<1, 1>, nullptr
+static const OpSTR STR_tab[2][3] = { T(OP_STR) };
+static const OpSTR STRH_tab[2][3] = { T(OP_STRH) };
+static const OpSTR STRB_tab[2][3] = { T(OP_STRB) };
+#undef T
+
+#define OP_STR_(mem_op, arg, sign_op, writeback) \
+ GpVar adr = c.newGpVar(kX86VarTypeGpd); \
+ GpVar data = c.newGpVar(kX86VarTypeGpd); \
+ c.mov(adr, reg_pos_ptr(16)); \
+ c.mov(data, reg_pos_ptr(12)); \
+ arg; \
+ if (!rhs_is_imm || *reinterpret_cast<uint32_t *>(&rhs)) \
+ { \
+ if (!writeback) \
+ c.sign_op(adr, rhs); \
+ else if (writeback < 0) \
+ { \
+ c.sign_op(adr, rhs); \
+ c.mov(reg_pos_ptr(16), adr); \
+ } \
+ else if (writeback > 0) \
+ { \
+ GpVar tmp_reg = c.newGpVar(kX86VarTypeGpd); \
+ c.mov(tmp_reg, adr); \
+ c.sign_op(tmp_reg, rhs); \
+ c.mov(reg_pos_ptr(16), tmp_reg); \
+ } \
+ } \
+ uint32_t adr_first = sign_op(cpu->R[REG_POS(i,16)], rhs_first); \
+ X86CompilerFuncCall *ctx = c.call(reinterpret_cast<void *>(mem_op##_tab[PROCNUM][classify_adr(adr_first, 1)])); \
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder2<uint32_t, uint32_t, uint32_t>()); \
+ ctx->setArgument(0, adr); \
+ ctx->setArgument(1, data); \
+ ctx->setReturn(bb_cycles); \
+ return 1;
+
+static int OP_STR_P_IMM_OFF(uint32_t i) { OP_STR_(STR, IMM_OFF_12, add, 0); }
+static int OP_STR_M_IMM_OFF(uint32_t i) { OP_STR_(STR, IMM_OFF_12, sub, 0); }
+static int OP_STR_P_LSL_IMM_OFF(uint32_t i) { OP_STR_(STR, LSL_IMM, add, 0); }
+static int OP_STR_M_LSL_IMM_OFF(uint32_t i) { OP_STR_(STR, LSL_IMM, sub, 0); }
+static int OP_STR_P_LSR_IMM_OFF(uint32_t i) { OP_STR_(STR, LSR_IMM, add, 0); }
+static int OP_STR_M_LSR_IMM_OFF(uint32_t i) { OP_STR_(STR, LSR_IMM, sub, 0); }
+static int OP_STR_P_ASR_IMM_OFF(uint32_t i) { OP_STR_(STR, ASR_IMM, add, 0); }
+static int OP_STR_M_ASR_IMM_OFF(uint32_t i) { OP_STR_(STR, ASR_IMM, sub, 0); }
+static int OP_STR_P_ROR_IMM_OFF(uint32_t i) { OP_STR_(STR, ROR_IMM, add, 0); }
+static int OP_STR_M_ROR_IMM_OFF(uint32_t i) { OP_STR_(STR, ROR_IMM, sub, 0); }
+
+static int OP_STR_P_IMM_OFF_PREIND(uint32_t i) { OP_STR_(STR, IMM_OFF_12, add, -1); }
+static int OP_STR_M_IMM_OFF_PREIND(uint32_t i) { OP_STR_(STR, IMM_OFF_12, sub, -1); }
+static int OP_STR_P_LSL_IMM_OFF_PREIND(uint32_t i) { OP_STR_(STR, LSL_IMM, add, -1); }
+static int OP_STR_M_LSL_IMM_OFF_PREIND(uint32_t i) { OP_STR_(STR, LSL_IMM, sub, -1); }
+static int OP_STR_P_LSR_IMM_OFF_PREIND(uint32_t i) { OP_STR_(STR, LSR_IMM, add, -1); }
+static int OP_STR_M_LSR_IMM_OFF_PREIND(uint32_t i) { OP_STR_(STR, LSR_IMM, sub, -1); }
+static int OP_STR_P_ASR_IMM_OFF_PREIND(uint32_t i) { OP_STR_(STR, ASR_IMM, add, -1); }
+static int OP_STR_M_ASR_IMM_OFF_PREIND(uint32_t i) { OP_STR_(STR, ASR_IMM, sub, -1); }
+static int OP_STR_P_ROR_IMM_OFF_PREIND(uint32_t i) { OP_STR_(STR, ROR_IMM, add, -1); }
+static int OP_STR_M_ROR_IMM_OFF_PREIND(uint32_t i) { OP_STR_(STR, ROR_IMM, sub, -1); }
+static int OP_STR_P_IMM_OFF_POSTIND(uint32_t i) { OP_STR_(STR, IMM_OFF_12, add, 1); }
+static int OP_STR_M_IMM_OFF_POSTIND(uint32_t i) { OP_STR_(STR, IMM_OFF_12, sub, 1); }
+static int OP_STR_P_LSL_IMM_OFF_POSTIND(uint32_t i) { OP_STR_(STR, LSL_IMM, add, 1); }
+static int OP_STR_M_LSL_IMM_OFF_POSTIND(uint32_t i) { OP_STR_(STR, LSL_IMM, sub, 1); }
+static int OP_STR_P_LSR_IMM_OFF_POSTIND(uint32_t i) { OP_STR_(STR, LSR_IMM, add, 1); }
+static int OP_STR_M_LSR_IMM_OFF_POSTIND(uint32_t i) { OP_STR_(STR, LSR_IMM, sub, 1); }
+static int OP_STR_P_ASR_IMM_OFF_POSTIND(uint32_t i) { OP_STR_(STR, ASR_IMM, add, 1); }
+static int OP_STR_M_ASR_IMM_OFF_POSTIND(uint32_t i) { OP_STR_(STR, ASR_IMM, sub, 1); }
+static int OP_STR_P_ROR_IMM_OFF_POSTIND(uint32_t i) { OP_STR_(STR, ROR_IMM, add, 1); }
+static int OP_STR_M_ROR_IMM_OFF_POSTIND(uint32_t i) { OP_STR_(STR, ROR_IMM, sub, 1); }
+
+static int OP_STRH_P_IMM_OFF(uint32_t i) { OP_STR_(STRH, IMM_OFF, add, 0); }
+static int OP_STRH_M_IMM_OFF(uint32_t i) { OP_STR_(STRH, IMM_OFF, sub, 0); }
+static int OP_STRH_P_REG_OFF(uint32_t i) { OP_STR_(STRH, REG_OFF, add, 0); }
+static int OP_STRH_M_REG_OFF(uint32_t i) { OP_STR_(STRH, REG_OFF, sub, 0); }
+
+static int OP_STRH_PRE_INDE_P_IMM_OFF(uint32_t i) { OP_STR_(STRH, IMM_OFF, add, -1); }
+static int OP_STRH_PRE_INDE_M_IMM_OFF(uint32_t i) { OP_STR_(STRH, IMM_OFF, sub, -1); }
+static int OP_STRH_PRE_INDE_P_REG_OFF(uint32_t i) { OP_STR_(STRH, REG_OFF, add, -1); }
+static int OP_STRH_PRE_INDE_M_REG_OFF(uint32_t i) { OP_STR_(STRH, REG_OFF, sub, -1); }
+static int OP_STRH_POS_INDE_P_IMM_OFF(uint32_t i) { OP_STR_(STRH, IMM_OFF, add, 1); }
+static int OP_STRH_POS_INDE_M_IMM_OFF(uint32_t i) { OP_STR_(STRH, IMM_OFF, sub, 1); }
+static int OP_STRH_POS_INDE_P_REG_OFF(uint32_t i) { OP_STR_(STRH, REG_OFF, add, 1); }
+static int OP_STRH_POS_INDE_M_REG_OFF(uint32_t i) { OP_STR_(STRH, REG_OFF, sub, 1); }
+
+static int OP_STRB_P_IMM_OFF(uint32_t i) { OP_STR_(STRB, IMM_OFF_12, add, 0); }
+static int OP_STRB_M_IMM_OFF(uint32_t i) { OP_STR_(STRB, IMM_OFF_12, sub, 0); }
+static int OP_STRB_P_LSL_IMM_OFF(uint32_t i) { OP_STR_(STRB, LSL_IMM, add, 0); }
+static int OP_STRB_M_LSL_IMM_OFF(uint32_t i) { OP_STR_(STRB, LSL_IMM, sub, 0); }
+static int OP_STRB_P_LSR_IMM_OFF(uint32_t i) { OP_STR_(STRB, LSR_IMM, add, 0); }
+static int OP_STRB_M_LSR_IMM_OFF(uint32_t i) { OP_STR_(STRB, LSR_IMM, sub, 0); }
+static int OP_STRB_P_ASR_IMM_OFF(uint32_t i) { OP_STR_(STRB, ASR_IMM, add, 0); }
+static int OP_STRB_M_ASR_IMM_OFF(uint32_t i) { OP_STR_(STRB, ASR_IMM, sub, 0); }
+static int OP_STRB_P_ROR_IMM_OFF(uint32_t i) { OP_STR_(STRB, ROR_IMM, add, 0); }
+static int OP_STRB_M_ROR_IMM_OFF(uint32_t i) { OP_STR_(STRB, ROR_IMM, sub, 0); }
+
+static int OP_STRB_P_IMM_OFF_PREIND(uint32_t i) { OP_STR_(STRB, IMM_OFF_12, add, -1); }
+static int OP_STRB_M_IMM_OFF_PREIND(uint32_t i) { OP_STR_(STRB, IMM_OFF_12, sub, -1); }
+static int OP_STRB_P_LSL_IMM_OFF_PREIND(uint32_t i) { OP_STR_(STRB, LSL_IMM, add, -1); }
+static int OP_STRB_M_LSL_IMM_OFF_PREIND(uint32_t i) { OP_STR_(STRB, LSL_IMM, sub, -1); }
+static int OP_STRB_P_LSR_IMM_OFF_PREIND(uint32_t i) { OP_STR_(STRB, LSR_IMM, add, -1); }
+static int OP_STRB_M_LSR_IMM_OFF_PREIND(uint32_t i) { OP_STR_(STRB, LSR_IMM, sub, -1); }
+static int OP_STRB_P_ASR_IMM_OFF_PREIND(uint32_t i) { OP_STR_(STRB, ASR_IMM, add, -1); }
+static int OP_STRB_M_ASR_IMM_OFF_PREIND(uint32_t i) { OP_STR_(STRB, ASR_IMM, sub, -1); }
+static int OP_STRB_P_ROR_IMM_OFF_PREIND(uint32_t i) { OP_STR_(STRB, ROR_IMM, add, -1); }
+static int OP_STRB_M_ROR_IMM_OFF_PREIND(uint32_t i) { OP_STR_(STRB, ROR_IMM, sub, -1); }
+static int OP_STRB_P_IMM_OFF_POSTIND(uint32_t i) { OP_STR_(STRB, IMM_OFF_12, add, 1); }
+static int OP_STRB_M_IMM_OFF_POSTIND(uint32_t i) { OP_STR_(STRB, IMM_OFF_12, sub, 1); }
+static int OP_STRB_P_LSL_IMM_OFF_POSTIND(uint32_t i) { OP_STR_(STRB, LSL_IMM, add, 1); }
+static int OP_STRB_M_LSL_IMM_OFF_POSTIND(uint32_t i) { OP_STR_(STRB, LSL_IMM, sub, 1); }
+static int OP_STRB_P_LSR_IMM_OFF_POSTIND(uint32_t i) { OP_STR_(STRB, LSR_IMM, add, 1); }
+static int OP_STRB_M_LSR_IMM_OFF_POSTIND(uint32_t i) { OP_STR_(STRB, LSR_IMM, sub, 1); }
+static int OP_STRB_P_ASR_IMM_OFF_POSTIND(uint32_t i) { OP_STR_(STRB, ASR_IMM, add, 1); }
+static int OP_STRB_M_ASR_IMM_OFF_POSTIND(uint32_t i) { OP_STR_(STRB, ASR_IMM, sub, 1); }
+static int OP_STRB_P_ROR_IMM_OFF_POSTIND(uint32_t i) { OP_STR_(STRB, ROR_IMM, add, 1); }
+static int OP_STRB_M_ROR_IMM_OFF_POSTIND(uint32_t i) { OP_STR_(STRB, ROR_IMM, sub, 1); }
+
+// -----------------------------------------------------------------------------
+// LDRD / STRD
+// -----------------------------------------------------------------------------
+typedef uint32_t FASTCALL (*LDRD_STRD_REG)(uint32_t);
+
+template<int PROCNUM, uint8_t Rnum> static uint32_t FASTCALL OP_LDRD_REG(uint32_t adr)
+{
+ cpu->R[Rnum] = READ32(cpu->mem_if->data, adr);
+ cpu->R[Rnum + 1] = READ32(cpu->mem_if->data, adr + 4);
+ return MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(adr) + MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(adr + 4);
+}
+
+template<int PROCNUM, uint8_t Rnum> static uint32_t FASTCALL OP_STRD_REG(uint32_t adr)
+{
+ WRITE32(cpu->mem_if->data, adr, cpu->R[Rnum]);
+ WRITE32(cpu->mem_if->data, adr + 4, cpu->R[Rnum + 1]);
+ return MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(adr) + MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(adr + 4);
+}
+
+#define T(op, proc) op<proc, 0>, op<proc, 1>, op<proc, 2>, op<proc, 3>, op<proc, 4>, op<proc, 5>, op<proc, 6>, op<proc, 7>, \
+ op<proc, 8>, op<proc, 9>, op<proc, 10>, op<proc, 11>, op<proc, 12>, op<proc, 13>, op<proc, 14>, op<proc, 15>
+static const LDRD_STRD_REG op_ldrd_tab[2][16] = { { T(OP_LDRD_REG, 0) }, { T(OP_LDRD_REG, 1) } };
+static const LDRD_STRD_REG op_strd_tab[2][16] = { { T(OP_STRD_REG, 0) }, { T(OP_STRD_REG, 1) } };
+#undef T
+
+static int OP_LDRD_STRD_POST_INDEX(uint32_t i)
+{
+ uint8_t Rd_num = REG_POS(i, 12);
+
+ if (Rd_num == 14)
+ {
+ printf("OP_LDRD_STRD_POST_INDEX: use R14!!!!\n");
+ return 0; // TODO: exception
+ }
+ if (Rd_num & 0x1)
+ {
+ printf("OP_LDRD_STRD_POST_INDEX: ERROR!!!!\n");
+ return 0; // TODO: exception
+ }
+ GpVar Rd = c.newGpVar(kX86VarTypeGpd);
+ GpVar addr = c.newGpVar(kX86VarTypeGpd);
+
+ c.mov(Rd, reg_pos_ptr(16));
+ c.mov(addr, reg_pos_ptr(16));
+
+ // I bit - immediate or register
+ if (BIT22(i))
+ {
+ IMM_OFF;
+ BIT23(i) ? c.add(reg_pos_ptr(16), rhs) : c.sub(reg_pos_ptr(16), rhs);
+ }
+ else
+ {
+ GpVar idx = c.newGpVar(kX86VarTypeGpd);
+ c.mov(idx, reg_pos_ptr(0));
+ BIT23(i) ? c.add(reg_pos_ptr(16), idx) : c.sub(reg_pos_ptr(16), idx);
+ }
+
+ X86CompilerFuncCall *ctx = c.call(reinterpret_cast<void *>(BIT5(i) ? op_strd_tab[PROCNUM][Rd_num] : op_ldrd_tab[PROCNUM][Rd_num]));
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder1<uint32_t, uint32_t>());
+ ctx->setArgument(0, addr);
+ ctx->setReturn(bb_cycles);
+ emit_MMU_aluMemCycles(3, bb_cycles, 0);
+ return 1;
+}
+
+static int OP_LDRD_STRD_OFFSET_PRE_INDEX(uint32_t i)
+{
+ uint8_t Rd_num = REG_POS(i, 12);
+
+ if (Rd_num == 14)
+ {
+ printf("OP_LDRD_STRD_OFFSET_PRE_INDEX: use R14!!!!\n");
+ return 0; // TODO: exception
+ }
+ if (Rd_num & 0x1)
+ {
+ printf("OP_LDRD_STRD_OFFSET_PRE_INDEX: ERROR!!!!\n");
+ return 0; // TODO: exception
+ }
+ GpVar Rd = c.newGpVar(kX86VarTypeGpd);
+ GpVar addr = c.newGpVar(kX86VarTypeGpd);
+
+ c.mov(Rd, reg_pos_ptr(16));
+ c.mov(addr, reg_pos_ptr(16));
+
+ // I bit - immediate or register
+ if (BIT22(i))
+ {
+ IMM_OFF;
+ BIT23(i) ? c.add(addr, rhs) : c.sub(addr, rhs);
+ }
+ else
+ BIT23(i) ? c.add(addr, reg_pos_ptr(0)) : c.sub(addr, reg_pos_ptr(0));
+
+ if (BIT5(i)) // Store
+ {
+ X86CompilerFuncCall *ctx = c.call(reinterpret_cast<void *>(op_strd_tab[PROCNUM][Rd_num]));
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder1<uint32_t, uint32_t>());
+ ctx->setArgument(0, addr);
+ ctx->setReturn(bb_cycles);
+ if (BIT21(i)) // W bit - writeback
+ c.mov(reg_pos_ptr(16), addr);
+ emit_MMU_aluMemCycles(3, bb_cycles, 0);
+ }
+ else // Load
+ {
+ if (BIT21(i)) // W bit - writeback
+ c.mov(reg_pos_ptr(16), addr);
+ X86CompilerFuncCall *ctx = c.call(reinterpret_cast<void *>(op_ldrd_tab[PROCNUM][Rd_num]));
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder1<uint32_t, uint32_t>());
+ ctx->setArgument(0, addr);
+ ctx->setReturn(bb_cycles);
+ emit_MMU_aluMemCycles(3, bb_cycles, 0);
+ }
+ return 1;
+}
+
+// -----------------------------------------------------------------------------
+// SWP/SWPB
+// -----------------------------------------------------------------------------
+template<int PROCNUM> static uint32_t FASTCALL op_swp(uint32_t adr, uint32_t *Rd, uint32_t Rs)
+{
+ uint32_t tmp = ROR(READ32(cpu->mem_if->data, adr), (adr & 3) << 3);
+ WRITE32(cpu->mem_if->data, adr, Rs);
+ *Rd = tmp;
+ return MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(adr) + MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(adr);
+}
+
+template<int PROCNUM> static uint32_t FASTCALL op_swpb(uint32_t adr, uint32_t *Rd, uint32_t Rs)
+{
+ uint32_t tmp = READ8(cpu->mem_if->data, adr);
+ WRITE8(cpu->mem_if->data, adr, Rs);
+ *Rd = tmp;
+ return MMU_memAccessCycles<PROCNUM, 8, MMU_AD_READ>(adr) + MMU_memAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(adr);
+}
+
+typedef uint32_t FASTCALL (*OP_SWP_SWPB)(uint32_t, uint32_t *, uint32_t);
+static const OP_SWP_SWPB op_swp_tab[2][2] = { { op_swp<0>, op_swp<1> }, { op_swpb<0>, op_swpb<1> } };
+
+static int op_swp_(uint32_t i, int b)
+{
+ GpVar addr = c.newGpVar(kX86VarTypeGpd);
+ GpVar Rd = c.newGpVar(kX86VarTypeGpz);
+ GpVar Rs = c.newGpVar(kX86VarTypeGpd);
+ c.mov(addr, reg_pos_ptr(16));
+ c.lea(Rd, reg_pos_ptr(12));
+ if (b)
+ c.movzx(Rs, reg_pos_ptrB(0));
+ else
+ c.mov(Rs, reg_pos_ptr(0));
+ X86CompilerFuncCall *ctx = c.call(reinterpret_cast<void *>(op_swp_tab[b][PROCNUM]));
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder3<uint32_t, uint32_t, uint32_t *, uint32_t>());
+ ctx->setArgument(0, addr);
+ ctx->setArgument(1, Rd);
+ ctx->setArgument(2, Rs);
+ ctx->setReturn(bb_cycles);
+ emit_MMU_aluMemCycles(4, bb_cycles, 0);
+ return 1;
+}
+
+static int OP_SWP(uint32_t i) { return op_swp_(i, 0); }
+static int OP_SWPB(uint32_t i) { return op_swp_(i, 1); }
+
+// -----------------------------------------------------------------------------
+// LDMIA / LDMIB / LDMDA / LDMDB / STMIA / STMIB / STMDA / STMDB
+// -----------------------------------------------------------------------------
+static uint32_t popcount(uint32_t x)
+{
+ uint32_t pop = 0;
+ for (; x; x >>= 1)
+ pop += x & 1;
+ return pop;
+}
+
+static uint64_t get_reg_list(uint32_t reg_mask, int dir)
+{
+ uint64_t regs = 0;
+ for (int j = 0; j < 16; ++j)
+ {
+ int k = dir < 0 ? j : 15 - j;
+ if (BIT_N(reg_mask, k))
+ regs = (regs << 4) | k;
+ }
+ return regs;
+}
+
+#ifdef ASMJIT_X64
+// generic needs to spill regs and main doesn't; if it's inlined gcc isn't smart enough to keep the spills out of the common case.
+#define LDM_INLINE
+#else
+// spills either way, and we might as well save codesize by not having separate functions
+#define LDM_INLINE inline
+#endif
+
+template<int PROCNUM, bool store, int dir> static LDM_INLINE FASTCALL uint32_t OP_LDM_STM_generic(uint32_t adr, uint64_t regs, int n)
+{
+ uint32_t cycles = 0;
+ adr &= ~3;
+ do
+ {
+ if (store)
+ _MMU_write32<PROCNUM>(adr, cpu->R[regs & 0xF]);
+ else
+ cpu->R[regs & 0xF] = _MMU_read32<PROCNUM>(adr);
+ cycles += MMU_memAccessCycles<PROCNUM, 32, store ? MMU_AD_WRITE : MMU_AD_READ>(adr);
+ adr += 4 * dir;
+ regs >>= 4;
+ } while (--n > 0);
+ return cycles;
+}
+
+#ifdef ENABLE_ADVANCED_TIMING
+#define ADV_CYCLES cycles += MMU_memAccessCycles<PROCNUM, 32, store ? MMU_AD_WRITE : MMU_AD_READ>(adr);
+#else
+#define ADV_CYCLES
+#endif
+
+template<int PROCNUM, bool store, int dir> static LDM_INLINE FASTCALL uint32_t OP_LDM_STM_other(uint32_t adr, uint64_t regs, int n)
+{
+ uint32_t cycles = 0;
+ adr &= ~3;
+#ifndef ENABLE_ADVANCED_TIMING
+ cycles = n * MMU_memAccessCycles<PROCNUM, 32, store ? MMU_AD_WRITE : MMU_AD_READ>(adr);
+#endif
+ do
+ {
+ if (PROCNUM == ARMCPU_ARM9)
+ {
+ if (store)
+ _MMU_ARM9_write32(adr, cpu->R[regs & 0xF]);
+ else
+ cpu->R[regs & 0xF] = _MMU_ARM9_read32(adr);
+ }
+ else
+ {
+ if (store)
+ _MMU_ARM7_write32(adr, cpu->R[regs & 0xF]);
+ else
+ cpu->R[regs & 0xF] = _MMU_ARM7_read32(adr);
+ }
+ ADV_CYCLES;
+ adr += 4 * dir;
+ regs >>= 4;
+ } while (--n > 0);
+ return cycles;
+}
+
+template<int PROCNUM, bool store, int dir, bool null_compiled> static FORCEINLINE FASTCALL uint32_t OP_LDM_STM_main(uint32_t adr, uint64_t regs, int n, uint8_t *ptr, uint32_t cycles)
+{
+#ifdef ENABLE_ADVANCED_TIMING
+ cycles = 0;
+#endif
+ uintptr_t *func = reinterpret_cast<uintptr_t *>(&JIT_COMPILED_FUNC(adr, PROCNUM));
+
+#define OP(j) \
+{ \
+ /* no need to zero functions in DTCM, since we can't execute from it */ \
+ if (null_compiled && store) \
+ { \
+ *func = 0; \
+ *(func + 1) = 0; \
+ } \
+ int Rd = (static_cast<uintptr_t>(regs) >> (j * 4)) & 0xF; \
+ if (store) \
+ *reinterpret_cast<uint32_t *>(ptr) = cpu->R[Rd]; \
+ else \
+ cpu->R[Rd] = *reinterpret_cast<uint32_t *>(ptr); \
+ ADV_CYCLES; \
+ func += 2 * dir; \
+ adr += 4 * dir; \
+ ptr += 4 * dir; \
+}
+
+ do
+ {
+ OP(0);
+ if (n == 1)
+ break;
+ OP(1);
+ if (n == 2)
+ break;
+ OP(2);
+ if (n == 3)
+ break;
+ OP(3);
+ regs >>= 16;
+ n -= 4;
+ } while (n > 0);
+ return cycles;
+#undef OP
+#undef ADV_CYCLES
+}
+
+template<int PROCNUM, bool store, int dir> static uint32_t FASTCALL OP_LDM_STM(uint32_t adr, uint64_t regs, int n)
+{
+ // TODO use classify_adr?
+ uint32_t cycles;
+ uint8_t *ptr;
+
+ if ((adr ^ (adr + (dir > 0 ? (n - 1) * 4 : -15 * 4))) & ~0x3FFF) // a little conservative, but we don't want to run too many comparisons
+ // the memory region spans a page boundary, so we can't factor the address translation out of the loop
+ return OP_LDM_STM_generic<PROCNUM, store, dir>(adr, regs, n);
+ else if (PROCNUM == ARMCPU_ARM9 && (adr & ~0x3FFF) == MMU.DTCMRegion)
+ {
+ // don't special-case DTCM cycles, even though that would be both faster and more accurate,
+ // because that wouldn't match the non-jitted version with !ACCOUNT_FOR_DATA_TCM_SPEED
+ ptr = MMU.ARM9_DTCM + (adr & 0x3FFC);
+ cycles = n * MMU_memAccessCycles<PROCNUM, 32, store ? MMU_AD_WRITE : MMU_AD_READ>(adr);
+ if (store)
+ return OP_LDM_STM_main<PROCNUM, store, dir, 0>(adr, regs, n, ptr, cycles);
+ }
+ else if ((adr & 0x0F000000) == 0x02000000)
+ {
+ ptr = MMU.MAIN_MEM + (adr & _MMU_MAIN_MEM_MASK32);
+ cycles = n * (PROCNUM == ARMCPU_ARM9 ? 4 : 2);
+ }
+ else if (PROCNUM == ARMCPU_ARM7 && !store && (adr & 0xFF800000) == 0x03800000)
+ {
+ ptr = MMU.ARM7_ERAM + (adr & 0xFFFC);
+ cycles = n;
+ }
+ else if (PROCNUM == ARMCPU_ARM7 && !store && (adr & 0xFF800000) == 0x03000000)
+ {
+ ptr = MMU.SWIRAM + (adr & 0x7FFC);
+ cycles = n;
+ }
+ else
+ return OP_LDM_STM_other<PROCNUM, store, dir>(adr, regs, n);
+
+ return OP_LDM_STM_main<PROCNUM, store, dir, store>(adr, regs, n, ptr, cycles);
+}
+
+typedef uint32_t FASTCALL (*LDMOpFunc)(uint32_t, uint64_t, int);
+static const LDMOpFunc op_ldm_stm_tab[2][2][2] =
+{
+ {
+ { OP_LDM_STM<0, 0, -1>, OP_LDM_STM<0, 0, 1> },
+ { OP_LDM_STM<0, 1, -1>, OP_LDM_STM<0, 1, 1> },
+ },
+ {
+ { OP_LDM_STM<1, 0, -1>, OP_LDM_STM<1, 0, 1> },
+ { OP_LDM_STM<1, 1, -1>, OP_LDM_STM<1, 1, 1> },
+ }
+};
+
+static void call_ldm_stm(GpVar adr, uint32_t bitmask, bool store, int dir)
+{
+ if (bitmask)
+ {
+ GpVar n = c.newGpVar(kX86VarTypeGpd);
+ c.mov(n, popcount(bitmask));
+#ifdef ASMJIT_X64
+ GpVar regs = c.newGpVar(kX86VarTypeGpz);
+ c.mov(regs, get_reg_list(bitmask, dir));
+ X86CompilerFuncCall *ctx = c.call(reinterpret_cast<void *>(op_ldm_stm_tab[PROCNUM][store][dir > 0]));
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder3<uint32_t, uint32_t, uint64_t, int>());
+ ctx->setArgument(0, adr);
+ ctx->setArgument(1, regs);
+ ctx->setArgument(2, n);
+#else
+ // same prototype, but we have to handle splitting of a u64 arg manually
+ GpVar regs_lo = c.newGpVar(kX86VarTypeGpd);
+ GpVar regs_hi = c.newGpVar(kX86VarTypeGpd);
+ c.mov(regs_lo, static_cast<uint32_t>(get_reg_list(bitmask, dir)));
+ c.mov(regs_hi, get_reg_list(bitmask, dir) >> 32);
+ X86CompilerFuncCall *ctx = c.call(reinterpret_cast<void *>(op_ldm_stm_tab[PROCNUM][store][dir > 0]));
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder4<uint32_t, uint32_t, uint32_t, uint32_t, int>());
+ ctx->setArgument(0, adr);
+ ctx->setArgument(1, regs_lo);
+ ctx->setArgument(2, regs_hi);
+ ctx->setArgument(3, n);
+#endif
+ ctx->setReturn(bb_cycles);
+ }
+ else
+ ++bb_constant_cycles;
+}
+
+static int op_bx(Mem srcreg, bool blx, bool test_thumb);
+static int op_bx_thumb(Mem srcreg, bool blx, bool test_thumb);
+
+static int op_ldm_stm(uint32_t i, bool store, int dir, bool before, bool writeback)
+{
+ uint32_t bitmask = i & 0xFFFF;
+ uint32_t pop = popcount(bitmask);
+
+ GpVar adr = c.newGpVar(kX86VarTypeGpd);
+ c.mov(adr, reg_pos_ptr(16));
+ if (before)
+ c.add(adr, 4*dir);
+
+ call_ldm_stm(adr, bitmask, store, dir);
+
+ if (BIT15(i) && !store)
+ op_bx(reg_ptr(15), 0, PROCNUM == ARMCPU_ARM9);
+
+ if (writeback)
+ {
+
+ if (store || !(i & (1 << REG_POS(i, 16))))
+ {
+ JIT_COMMENT("--- writeback");
+ c.add(reg_pos_ptr(16), 4 * dir * pop);
+ }
+ else
+ {
+ uint32_t bitlist = (~((2 << REG_POS(i, 16)) - 1)) & 0xFFFF;
+ if (i & bitlist)
+ {
+ JIT_COMMENT("--- writeback");
+ c.add(adr, 4 * dir * (pop - before));
+ c.mov(reg_pos_ptr(16), adr);
+ }
+ }
+ }
+
+ emit_MMU_aluMemCycles(store ? 1 : 2, bb_cycles, pop);
+ return 1;
+}
+
+static int OP_LDMIA(uint32_t i) { return op_ldm_stm(i, 0, +1, 0, 0); }
+static int OP_LDMIB(uint32_t i) { return op_ldm_stm(i, 0, +1, 1, 0); }
+static int OP_LDMDA(uint32_t i) { return op_ldm_stm(i, 0, -1, 0, 0); }
+static int OP_LDMDB(uint32_t i) { return op_ldm_stm(i, 0, -1, 1, 0); }
+static int OP_LDMIA_W(uint32_t i) { return op_ldm_stm(i, 0, +1, 0, 1); }
+static int OP_LDMIB_W(uint32_t i) { return op_ldm_stm(i, 0, +1, 1, 1); }
+static int OP_LDMDA_W(uint32_t i) { return op_ldm_stm(i, 0, -1, 0, 1); }
+static int OP_LDMDB_W(uint32_t i) { return op_ldm_stm(i, 0, -1, 1, 1); }
+
+static int OP_STMIA(uint32_t i) { return op_ldm_stm(i, 1, +1, 0, 0); }
+static int OP_STMIB(uint32_t i) { return op_ldm_stm(i, 1, +1, 1, 0); }
+static int OP_STMDA(uint32_t i) { return op_ldm_stm(i, 1, -1, 0, 0); }
+static int OP_STMDB(uint32_t i) { return op_ldm_stm(i, 1, -1, 1, 0); }
+static int OP_STMIA_W(uint32_t i) { return op_ldm_stm(i, 1, +1, 0, 1); }
+static int OP_STMIB_W(uint32_t i) { return op_ldm_stm(i, 1, +1, 1, 1); }
+static int OP_STMDA_W(uint32_t i) { return op_ldm_stm(i, 1, -1, 0, 1); }
+static int OP_STMDB_W(uint32_t i) { return op_ldm_stm(i, 1, -1, 1, 1); }
+
+static int op_ldm_stm2(uint32_t i, bool store, int dir, bool before, bool writeback)
+{
+ uint32_t bitmask = i & 0xFFFF;
+ uint32_t pop = popcount(bitmask);
+ bool bit15 = !!BIT15(i);
+
+ //printf("ARM%c: %s R%d:%08X, bitmask %02X\n", PROCNUM?'7':'9', (store?"STM":"LDM"), REG_POS(i, 16), cpu->R[REG_POS(i, 16)], bitmask);
+ uint32_t adr_first = cpu->R[REG_POS(i, 16)];
+
+ GpVar adr = c.newGpVar(kX86VarTypeGpd);
+ GpVar oldmode = c.newGpVar(kX86VarTypeGpd);
+
+ c.mov(adr, reg_pos_ptr(16));
+ if (before)
+ c.add(adr, 4*dir);
+
+ if (!bit15 || store)
+ {
+ //if((cpu->CPSR.bits.mode==USR)||(cpu->CPSR.bits.mode==SYS)) { printf("ERROR1\n"); return 1; }
+ //oldmode = armcpu_switchMode(cpu, SYS);
+ c.mov(oldmode, SYS);
+ X86CompilerFuncCall *ctx = c.call(reinterpret_cast<void *>(armcpu_switchMode));
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder2<uint32_t, uint8_t *, uint8_t>());
+ ctx->setArgument(0, bb_cpu);
+ ctx->setArgument(1, oldmode);
+ ctx->setReturn(oldmode);
+ }
+
+ call_ldm_stm(adr, bitmask, store, dir);
+
+ if (!bit15 || store)
+ {
+ //armcpu_switchMode(cpu, oldmode);
+ X86CompilerFuncCall *ctx = c.call(reinterpret_cast<void *>(armcpu_switchMode));
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder2<void, uint8_t *, uint8_t>());
+ ctx->setArgument(0, bb_cpu);
+ ctx->setArgument(1, oldmode);
+ }
+ else
+ S_DST_R15;
+
+ // FIXME
+ if (writeback)
+ {
+ if (store || !(i & (1 << REG_POS(i, 16))))
+ c.add(reg_pos_ptr(16), 4 * dir * pop);
+ else
+ {
+ uint32_t bitlist = (~((2 << REG_POS(i, 16)) - 1)) & 0xFFFF;
+ if (i & bitlist)
+ {
+ c.add(adr, 4 * dir * (pop - before));
+ c.mov(reg_pos_ptr(16), adr);
+ }
+ }
+ }
+
+ emit_MMU_aluMemCycles(store ? 1 : 2, bb_cycles, pop);
+ return 1;
+}
+
+static int OP_LDMIA2(uint32_t i) { return op_ldm_stm2(i, 0, +1, 0, 0); }
+static int OP_LDMIB2(uint32_t i) { return op_ldm_stm2(i, 0, +1, 1, 0); }
+static int OP_LDMDA2(uint32_t i) { return op_ldm_stm2(i, 0, -1, 0, 0); }
+static int OP_LDMDB2(uint32_t i) { return op_ldm_stm2(i, 0, -1, 1, 0); }
+static int OP_LDMIA2_W(uint32_t i) { return op_ldm_stm2(i, 0, +1, 0, 1); }
+static int OP_LDMIB2_W(uint32_t i) { return op_ldm_stm2(i, 0, +1, 1, 1); }
+static int OP_LDMDA2_W(uint32_t i) { return op_ldm_stm2(i, 0, -1, 0, 1); }
+static int OP_LDMDB2_W(uint32_t i) { return op_ldm_stm2(i, 0, -1, 1, 1); }
+
+static int OP_STMIA2(uint32_t i) { return op_ldm_stm2(i, 1, +1, 0, 0); }
+static int OP_STMIB2(uint32_t i) { return op_ldm_stm2(i, 1, +1, 1, 0); }
+static int OP_STMDA2(uint32_t i) { return op_ldm_stm2(i, 1, -1, 0, 0); }
+static int OP_STMDB2(uint32_t i) { return op_ldm_stm2(i, 1, -1, 1, 0); }
+static int OP_STMIA2_W(uint32_t i) { return op_ldm_stm2(i, 1, +1, 0, 1); }
+static int OP_STMIB2_W(uint32_t i) { return op_ldm_stm2(i, 1, +1, 1, 1); }
+static int OP_STMDA2_W(uint32_t i) { return op_ldm_stm2(i, 1, -1, 0, 1); }
+static int OP_STMDB2_W(uint32_t i) { return op_ldm_stm2(i, 1, -1, 1, 1); }
+
+// -----------------------------------------------------------------------------
+// Branch
+// -----------------------------------------------------------------------------
+
+static inline uint32_t SIGNEXTEND_11(uint32_t i) { return static_cast<uint32_t>((static_cast<int32_t>(i) << 21) >> 21); }
+static inline uint32_t SIGNEXTEND_24(uint32_t i) { return static_cast<uint32_t>((static_cast<int32_t>(i) << 8) >> 8); }
+
+static int op_b(uint32_t i, bool bl)
+{
+ uint32_t dst = bb_r15 + (SIGNEXTEND_24(i) << 2);
+ if (CONDITION(i) == 0xF)
+ {
+ if (bl)
+ dst += 2;
+ c.or_(cpu_ptr_byte(CPSR, 0), 1 << 5);
+ }
+ if (bl || CONDITION(i) == 0xF)
+ c.mov(reg_ptr(14), bb_next_instruction);
+
+ c.mov(cpu_ptr(instruct_adr), dst);
+ return 1;
+}
+
+static int OP_B(uint32_t i) { return op_b(i, 0); }
+static int OP_BL(uint32_t i) { return op_b(i, 1); }
+
+static int op_bx(Mem srcreg, bool blx, bool test_thumb)
+{
+ GpVar dst = c.newGpVar(kX86VarTypeGpd);
+ c.mov(dst, srcreg);
+
+ if (test_thumb)
+ {
+ GpVar mask = c.newGpVar(kX86VarTypeGpd);
+ GpVar thumb = dst;
+ dst = c.newGpVar(kX86VarTypeGpd);
+ c.mov(dst, thumb);
+ c.and_(thumb, 1);
+ c.lea(mask, ptr_abs(reinterpret_cast<void *>(0xFFFFFFFC), thumb.r64(), kScale2Times));
+ c.shl(thumb, 5);
+ c.or_(cpu_ptr_byte(CPSR, 0), thumb.r8Lo());
+ c.and_(dst, mask);
+ }
+ else
+ c.and_(dst, 0xFFFFFFFC);
+
+ if (blx)
+ c.mov(reg_ptr(14), bb_next_instruction);
+ c.mov(cpu_ptr(instruct_adr), dst);
+ return 1;
+}
+
+// TODO: exeption when Rm=PC
+static int OP_BX(uint32_t i) { return op_bx(reg_pos_ptr(0), 0, 1); }
+static int OP_BLX_REG(uint32_t i) { return op_bx(reg_pos_ptr(0), 1, 1); }
+
+// -----------------------------------------------------------------------------
+// CLZ
+// -----------------------------------------------------------------------------
+static int OP_CLZ(uint32_t i)
+{
+ GpVar res = c.newGpVar(kX86VarTypeGpd);
+ c.mov(res, 0x3F);
+ c.bsr(res, reg_pos_ptr(0));
+ c.xor_(res, 0x1F);
+ c.mov(reg_pos_ptr(12), res);
+
+ return 1;
+}
+
+// -----------------------------------------------------------------------------
+// MCR / MRC
+// -----------------------------------------------------------------------------
+#define maskPrecalc \
+{ \
+ X86CompilerFuncCall *ctxM = c.call(reinterpret_cast<void *>(maskPrecalc)); \
+ ctxM->setPrototype(ASMJIT_CALL_CONV, FuncBuilder0<void>()); \
+}
+static int OP_MCR(uint32_t i)
+{
+ if (PROCNUM == ARMCPU_ARM7)
+ return 0;
+
+ uint32_t cpnum = REG_POS(i, 8);
+ if (cpnum != 15)
+ {
+ // TODO - exception?
+ printf("JIT: MCR P%i, 0, R%i, C%i, C%i, %i, %i (don't allocated coprocessor)\n", cpnum, REG_POS(i, 12), REG_POS(i, 16), REG_POS(i, 0), (i >> 21) & 0x7, (i >> 5) & 0x7);
+ return 2;
+ }
+ if (REG_POS(i, 12) == 15)
+ {
+ printf("JIT: MCR Rd=R15\n");
+ return 2;
+ }
+
+ uint8_t CRn = REG_POS(i, 16); // Cn
+ uint8_t CRm = REG_POS(i, 0); // Cm
+ uint8_t opcode1 = (i >> 21) & 0x7; // opcode1
+ uint8_t opcode2 = (i >> 5) & 0x7; // opcode2
+
+ GpVar bb_cp15 = c.newGpVar(kX86VarTypeGpz);
+ GpVar data = c.newGpVar(kX86VarTypeGpd);
+ c.mov(data, reg_pos_ptr(12));
+ c.mov(bb_cp15, reinterpret_cast<uintptr_t>(&cp15));
+
+ bool bUnknown = false;
+ switch (CRn)
+ {
+ case 1:
+ if (!opcode1 && !opcode2 && !CRm)
+ {
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd);
+ // On the NDS bit0,2,7,12..19 are R/W, Bit3..6 are always set, all other bits are always zero.
+ //MMU.ARM9_RW_MODE = BIT7(val);
+ GpVar bb_mmu = c.newGpVar(kX86VarTypeGpz);
+ c.mov(bb_mmu, reinterpret_cast<uintptr_t>(&MMU));
+ Mem rwmode = mmu_ptr_byte(ARM9_RW_MODE);
+ Mem ldtbit = cpu_ptr_byte(LDTBit, 0);
+ c.test(data, 1 << 7);
+ c.setnz(rwmode);
+ //cpu->intVector = 0xFFFF0000 * (BIT13(val));
+ GpVar vec = c.newGpVar(kX86VarTypeGpd);
+ c.mov(tmp, 0xFFFF0000);
+ c.xor_(vec, vec);
+ c.test(data, 1 << 13);
+ c.cmovnz(vec, tmp);
+ c.mov(cpu_ptr(intVector), vec);
+ //cpu->LDTBit = !BIT15(val); //TBit
+ c.test(data, 1 << 15);
+ c.setz(ldtbit);
+ //ctrl = (val & 0x000FF085) | 0x00000078;
+ c.and_(data, 0x000FF085);
+ c.or_(data, 0x00000078);
+ c.mov(cp15_ptr(ctrl), data);
+ break;
+ }
+ bUnknown = true;
+ break;
+ case 2:
+ if (!opcode1 && !CRm)
+ {
+ switch (opcode2)
+ {
+ case 0:
+ // DCConfig = val;
+ c.mov(cp15_ptr(DCConfig), data);
+ break;
+ case 1:
+ // ICConfig = val;
+ c.mov(cp15_ptr(ICConfig), data);
+ break;
+ default:
+ bUnknown = true;
+ break;
+ }
+ break;
+ }
+ bUnknown = true;
+ break;
+ case 3:
+ if (!opcode1 && !opcode2 && !CRm)
+ {
+ //writeBuffCtrl = val;
+ c.mov(cp15_ptr(writeBuffCtrl), data);
+ break;
+ }
+ bUnknown = true;
+ break;
+ case 5:
+ if (!opcode1 && !CRm)
+ {
+ switch (opcode2)
+ {
+ case 2:
+ //DaccessPerm = val;
+ c.mov(cp15_ptr(DaccessPerm), data);
+ maskPrecalc;
+ break;
+ case 3:
+ //IaccessPerm = val;
+ c.mov(cp15_ptr(IaccessPerm), data);
+ maskPrecalc;
+ break;
+ default:
+ bUnknown = true;
+ break;
+ }
+ }
+ bUnknown = true;
+ break;
+ case 6:
+ if (!opcode1 && !opcode2)
+ {
+ switch (CRm)
+ {
+ case 0:
+ //protectBaseSize0 = val;
+ c.mov(cp15_ptr(protectBaseSize0), data);
+ maskPrecalc;
+ break;
+ case 1:
+ //protectBaseSize1 = val;
+ c.mov(cp15_ptr(protectBaseSize1), data);
+ maskPrecalc;
+ break;
+ case 2:
+ //protectBaseSize2 = val;
+ c.mov(cp15_ptr(protectBaseSize2), data);
+ maskPrecalc;
+ break;
+ case 3:
+ //protectBaseSize3 = val;
+ c.mov(cp15_ptr(protectBaseSize3), data);
+ maskPrecalc;
+ break;
+ case 4:
+ //protectBaseSize4 = val;
+ c.mov(cp15_ptr(protectBaseSize4), data);
+ maskPrecalc;
+ break;
+ case 5:
+ //protectBaseSize5 = val;
+ c.mov(cp15_ptr(protectBaseSize5), data);
+ maskPrecalc;
+ break;
+ case 6:
+ //protectBaseSize6 = val;
+ c.mov(cp15_ptr(protectBaseSize6), data);
+ maskPrecalc;
+ break;
+ case 7:
+ //protectBaseSize7 = val;
+ c.mov(cp15_ptr(protectBaseSize7), data);
+ maskPrecalc;
+ break;
+ default:
+ bUnknown = true;
+ break;
+ }
+ }
+ bUnknown = true;
+ break;
+ case 7:
+ if (!CRm && !opcode1 && opcode2 == 4)
+ {
+ //CP15wait4IRQ;
+ c.mov(cpu_ptr(waitIRQ), true);
+ c.mov(cpu_ptr(halt_IE_and_IF), true);
+ //IME set deliberately omitted: only SWI sets IME to 1
+ break;
+ }
+ bUnknown = true;
+ break;
+ case 9:
+ if (!opcode1)
+ {
+ switch (CRm)
+ {
+ case 0:
+ switch (opcode2)
+ {
+ case 0:
+ //DcacheLock = val;
+ c.mov(cp15_ptr(DcacheLock), data);
+ break;
+ case 1:
+ //IcacheLock = val;
+ c.mov(cp15_ptr(IcacheLock), data);
+ break;
+ default:
+ bUnknown = true;
+ break;
+ }
+ case 1:
+ switch (opcode2)
+ {
+ case 0:
+ {
+ //MMU.DTCMRegion = DTCMRegion = val & 0x0FFFF000;
+ c.and_(data, 0x0FFFF000);
+ GpVar bb_mmu = c.newGpVar(kX86VarTypeGpz);
+ c.mov(bb_mmu, reinterpret_cast<uintptr_t>(&MMU));
+ c.mov(mmu_ptr(DTCMRegion), data);
+ c.mov(cp15_ptr(DTCMRegion), data);
+ break;
+ }
+ case 1:
+ {
+ //ITCMRegion = val;
+ //ITCM base is not writeable!
+ GpVar bb_mmu = c.newGpVar(kX86VarTypeGpz);
+ c.mov(bb_mmu, reinterpret_cast<uintptr_t>(&MMU));
+ c.mov(mmu_ptr(ITCMRegion), 0);
+ c.mov(cp15_ptr(ITCMRegion), data);
+ break;
+ }
+ default:
+ bUnknown = true;
+ break;
+ }
+ }
+ break;
+ }
+ bUnknown = true;
+ break;
+ default:
+ bUnknown = true;
+ }
+
+ if (bUnknown)
+ {
+ //printf("Unknown MCR command: MRC P15, 0, R%i, C%i, C%i, %i, %i\n", REG_POS(i, 12), CRn, CRm, opcode1, opcode2);
+ return 1;
+ }
+
+ return 1;
+}
+
+static int OP_MRC(uint32_t i)
+{
+ if (PROCNUM == ARMCPU_ARM7)
+ return 0;
+
+ uint32_t cpnum = REG_POS(i, 8);
+ if (cpnum != 15)
+ {
+ printf("MRC P%i, 0, R%i, C%i, C%i, %i, %i (don't allocated coprocessor)\n", cpnum, REG_POS(i, 12), REG_POS(i, 16), REG_POS(i, 0), (i>>21)&0x7, (i>>5)&0x7);
+ return 2;
+ }
+
+ uint8_t CRn = REG_POS(i, 16); // Cn
+ uint8_t CRm = REG_POS(i, 0); // Cm
+ uint8_t opcode1 = (i >> 21) & 0x7; // opcode1
+ uint8_t opcode2 = (i >> 5) & 0x7; // opcode2
+
+ GpVar bb_cp15 = c.newGpVar(kX86VarTypeGpz);
+ GpVar data = c.newGpVar(kX86VarTypeGpd);
+
+ c.mov(bb_cp15, (uintptr_t)&cp15);
+
+ bool bUnknown = false;
+ switch (CRn)
+ {
+ case 0:
+ if (!opcode1 && !CRm)
+ {
+ switch (opcode2)
+ {
+ case 1:
+ // *R = cacheType;
+ c.mov(data, cp15_ptr(cacheType));
+ break;
+ case 2:
+ // *R = TCMSize;
+ c.mov(data, cp15_ptr(TCMSize));
+ break;
+ default: // FIXME
+ // *R = IDCode;
+ c.mov(data, cp15_ptr(IDCode));
+ break;
+ }
+ break;
+ }
+ bUnknown = true;
+ break;
+ case 1:
+ if (!opcode1 && !opcode2 && !CRm)
+ {
+ // *R = ctrl;
+ c.mov(data, cp15_ptr(ctrl));
+ break;
+ }
+ bUnknown = true;
+ break;
+ case 2:
+ if (!opcode1 && !CRm)
+ {
+ switch (opcode2)
+ {
+ case 0:
+ // *R = DCConfig;
+ c.mov(data, cp15_ptr(DCConfig));
+ break;
+ case 1:
+ // *R = ICConfig;
+ c.mov(data, cp15_ptr(ICConfig));
+ break;
+ default:
+ bUnknown = true;
+ break;
+ }
+ break;
+ }
+ bUnknown = true;
+ break;
+ case 3:
+ if (!opcode1 && !opcode2 && !CRm)
+ {
+ // *R = writeBuffCtrl;
+ c.mov(data, cp15_ptr(writeBuffCtrl));
+ break;
+ }
+ bUnknown = true;
+ break;
+ case 5:
+ if (!opcode1 && !CRm)
+ {
+ switch (opcode2)
+ {
+ case 2:
+ // *R = DaccessPerm;
+ c.mov(data, cp15_ptr(DaccessPerm));
+ break;
+ case 3:
+ // *R = IaccessPerm;
+ c.mov(data, cp15_ptr(IaccessPerm));
+ break;
+ default:
+ bUnknown = true;
+ break;
+ }
+ break;
+ }
+ bUnknown = true;
+ break;
+ case 6:
+ if (!opcode1 && !opcode2)
+ {
+ switch(CRm)
+ {
+ case 0:
+ // *R = protectBaseSize0;
+ c.mov(data, cp15_ptr(protectBaseSize0));
+ break;
+ case 1:
+ // *R = protectBaseSize1;
+ c.mov(data, cp15_ptr(protectBaseSize1));
+ break;
+ case 2:
+ // *R = protectBaseSize2;
+ c.mov(data, cp15_ptr(protectBaseSize2));
+ break;
+ case 3:
+ // *R = protectBaseSize3;
+ c.mov(data, cp15_ptr(protectBaseSize3));
+ break;
+ case 4:
+ // *R = protectBaseSize4;
+ c.mov(data, cp15_ptr(protectBaseSize4));
+ break;
+ case 5:
+ // *R = protectBaseSize5;
+ c.mov(data, cp15_ptr(protectBaseSize5));
+ break;
+ case 6:
+ // *R = protectBaseSize6;
+ c.mov(data, cp15_ptr(protectBaseSize6));
+ break;
+ case 7:
+ // *R = protectBaseSize7;
+ c.mov(data, cp15_ptr(protectBaseSize7));
+ break;
+ default:
+ bUnknown = true;
+ break;
+ }
+ break;
+ }
+ bUnknown = true;
+ break;
+ case 9:
+ if (!opcode1)
+ {
+ switch (CRm)
+ {
+ case 0:
+ switch (opcode2)
+ {
+ case 0:
+ //*R = DcacheLock;
+ c.mov(data, cp15_ptr(DcacheLock));
+ break;
+ case 1:
+ //*R = IcacheLock;
+ c.mov(data, cp15_ptr(IcacheLock));
+ break;
+ default:
+ bUnknown = true;
+ break;
+ }
+ case 1:
+ switch (opcode2)
+ {
+ case 0:
+ //*R = DTCMRegion;
+ c.mov(data, cp15_ptr(DTCMRegion));
+ break;
+ case 1:
+ //*R = ITCMRegion;
+ c.mov(data, cp15_ptr(ITCMRegion));
+ break;
+ default:
+ bUnknown = true;
+ break;
+ }
+ }
+ break;
+ }
+ bUnknown = true;
+ break;
+ default:
+ bUnknown = true;
+ }
+
+ if (bUnknown)
+ {
+ //printf("Unknown MRC command: MRC P15, 0, R%i, C%i, C%i, %i, %i\n", REG_POS(i, 12), CRn, CRm, opcode1, opcode2);
+ return 1;
+ }
+
+ if (REG_POS(i, 12) == 15) // set NZCV
+ {
+ //CPSR.bits.N = BIT31(data);
+ //CPSR.bits.Z = BIT30(data);
+ //CPSR.bits.C = BIT29(data);
+ //CPSR.bits.V = BIT28(data);
+ c.and_(data, 0xF0000000);
+ c.and_(cpu_ptr(CPSR), 0x0FFFFFFF);
+ c.or_(cpu_ptr(CPSR), data);
+ }
+ else
+ c.mov(reg_pos_ptr(12), data);
+
+ return 1;
+}
+
+uint32_t op_swi(uint8_t swinum)
+{
+ if (cpu->swi_tab)
+ {
+#if defined(_M_X64) || defined(__x86_64__)
+ // TODO:
+ return 0;
+#else
+ X86CompilerFuncCall *ctx = c.call(reinterpret_cast<void *>(ARM_swi_tab[PROCNUM][swinum]));
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder0<uint32_t>());
+ ctx->setReturn(bb_cycles);
+ c.add(bb_cycles, 3);
+ return 1;
+#endif
+ }
+
+ GpVar oldCPSR = c.newGpVar(kX86VarTypeGpd);
+ GpVar mode = c.newGpVar(kX86VarTypeGpd);
+ Mem CPSR = cpu_ptr(CPSR.val);
+ JIT_COMMENT("store CPSR to x86 stack");
+ c.mov(oldCPSR, CPSR);
+ JIT_COMMENT("enter SVC mode");
+ c.mov(mode, imm(SVC));
+ X86CompilerFuncCall* ctx = c.call(reinterpret_cast<void *>(armcpu_switchMode));
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder2<void, void *, uint8_t>());
+ ctx->setArgument(0, bb_cpu);
+ ctx->setArgument(1, mode);
+ c.unuse(mode);
+ JIT_COMMENT("store next instruction address to R14");
+ c.mov(reg_ptr(14), bb_next_instruction);
+ JIT_COMMENT("save old CPSR as new SPSR");
+ c.mov(cpu_ptr(SPSR.val), oldCPSR);
+ JIT_COMMENT("CPSR: clear T, set I");
+ GpVar _cpsr = c.newGpVar(kX86VarTypeGpd);
+ c.mov(_cpsr, CPSR);
+ c.and_(_cpsr, ~(1 << 5)); /* clear T */
+ c.or_(_cpsr, 1 << 7); /* set I */
+ c.mov(CPSR, _cpsr);
+ c.unuse(_cpsr);
+ JIT_COMMENT("set next instruction");
+ c.mov(cpu_ptr(next_instruction), imm(cpu->intVector + 0x08));
+
+ return 1;
+}
+
+static int OP_SWI(uint32_t i) { return op_swi((i >> 16) & 0x1F); }
+
+// -----------------------------------------------------------------------------
+// BKPT
+// -----------------------------------------------------------------------------
+static int OP_BKPT(uint32_t i) { printf("JIT: unimplemented OP_BKPT\n"); return 0; }
+
+// -----------------------------------------------------------------------------
+// THUMB
+// -----------------------------------------------------------------------------
+#define OP_SHIFTS_IMM(x86inst) \
+ GpVar rcf = c.newGpVar(kX86VarTypeGpd); \
+ uint8_t cf_change = 1; \
+ uint32_t rhs = (i >> 6) & 0x1F; \
+ if (_REG_NUM(i, 0) == _REG_NUM(i, 3)) \
+ c.x86inst(reg_pos_thumb(0), rhs); \
+ else \
+ { \
+ GpVar lhs = c.newGpVar(kX86VarTypeGpd); \
+ c.mov(lhs, reg_pos_thumb(3)); \
+ c.x86inst(lhs, rhs); \
+ c.mov(reg_pos_thumb(0), lhs); \
+ c.unuse(lhs); \
+ } \
+ c.setc(rcf.r8Lo()); \
+ SET_NZC; \
+ return 1;
+
+#define OP_SHIFTS_REG(x86inst, bit) \
+ uint8_t cf_change = 1; \
+ GpVar imm = c.newGpVar(kX86VarTypeGpz); \
+ GpVar rcf = c.newGpVar(kX86VarTypeGpd); \
+ Label __eq32 = c.newLabel(); \
+ Label __ls32 = c.newLabel(); \
+ Label __zero = c.newLabel(); \
+ Label __done = c.newLabel(); \
+\
+ c.mov(imm, reg_pos_thumb(3)); \
+ c.and_(imm, 0xFF); \
+ c.jz(__zero); \
+ c.cmp(imm, 32); \
+ c.jl(__ls32); \
+ c.je(__eq32); \
+ /* imm > 32 */ \
+ c.mov(reg_pos_thumb(0), 0); \
+ SET_NZC_SHIFTS_ZERO(0); \
+ c.jmp(__done); \
+ /* imm == 32 */ \
+ c.bind(__eq32); \
+ c.test(reg_pos_thumb(0), 1 << bit); \
+ c.setnz(rcf.r8Lo()); \
+ c.mov(reg_pos_thumb(0), 0); \
+ SET_NZC_SHIFTS_ZERO(1); \
+ c.jmp(__done); \
+ /* imm == 0 */ \
+ c.bind(__zero); \
+ c.cmp(reg_pos_thumb(0), 0); \
+ SET_NZ(0); \
+ c.jmp(__done); \
+ /* imm < 32 */ \
+ c.bind(__ls32); \
+ c.x86inst(reg_pos_thumb(0), imm); \
+ c.setc(rcf.r8Lo()); \
+ SET_NZC; \
+ c.bind(__done); \
+ return 1;
+
+#define OP_LOGIC(x86inst, _conv) \
+ GpVar rhs = c.newGpVar(kX86VarTypeGpd); \
+ c.mov(rhs, reg_pos_thumb(3)); \
+ if (_conv == 1) \
+ c.not_(rhs); \
+ c.x86inst(reg_pos_thumb(0), rhs); \
+ SET_NZ(0); \
+ return 1;
+
+// -----------------------------------------------------------------------------
+// LSL / LSR / ASR / ROR
+// -----------------------------------------------------------------------------
+static int OP_LSL_0(uint32_t i)
+{
+ if (_REG_NUM(i, 0) == _REG_NUM(i, 3))
+ c.cmp(reg_pos_thumb(0), 0);
+ else
+ {
+ GpVar rhs = c.newGpVar(kX86VarTypeGpd);
+ c.mov(rhs, reg_pos_thumb(3));
+ c.mov(reg_pos_thumb(0), rhs);
+ c.cmp(rhs, 0);
+ }
+ SET_NZ(0);
+ return 1;
+}
+static int OP_LSL(uint32_t i) { OP_SHIFTS_IMM(shl); }
+static int OP_LSL_REG(uint32_t i) { OP_SHIFTS_REG(shl, 0); }
+static int OP_LSR_0(uint32_t i)
+{
+ GpVar rcf = c.newGpVar(kX86VarTypeGpd);
+ c.test(reg_pos_thumb(3), 1 << 31);
+ c.setnz(rcf.r8Lo());
+ SET_NZC_SHIFTS_ZERO(1);
+ c.mov(reg_pos_thumb(0), 0);
+ return 1;
+}
+static int OP_LSR(uint32_t i) { OP_SHIFTS_IMM(shr); }
+static int OP_LSR_REG(uint32_t i) { OP_SHIFTS_REG(shr, 31); }
+static int OP_ASR_0(uint32_t i)
+{
+ uint8_t cf_change = 1;
+ GpVar rcf = c.newGpVar(kX86VarTypeGpd);
+ GpVar rhs = c.newGpVar(kX86VarTypeGpd);
+ if (_REG_NUM(i, 0) == _REG_NUM(i, 3))
+ c.sar(reg_pos_thumb(0), 31);
+ else
+ {
+ c.mov(rhs, reg_pos_thumb(3));
+ c.sar(rhs, 31);
+ c.mov(reg_pos_thumb(0), rhs);
+ }
+ c.sets(rcf.r8Lo());
+ SET_NZC;
+ return 1;
+}
+static int OP_ASR(uint32_t i) { OP_SHIFTS_IMM(sar); }
+static int OP_ASR_REG(uint32_t i)
+{
+ uint8_t cf_change = 1;
+ Label __gr0 = c.newLabel();
+ Label __lt32 = c.newLabel();
+ Label __done = c.newLabel();
+ Label __setFlags = c.newLabel();
+ GpVar imm = c.newGpVar(kX86VarTypeGpz);
+ GpVar rcf = c.newGpVar(kX86VarTypeGpd);
+ c.mov(imm, reg_pos_thumb(3));
+ c.and_(imm, 0xFF);
+ c.jnz(__gr0);
+ /* imm == 0 */
+ c.cmp(reg_pos_thumb(0), 0);
+ SET_NZ(0);
+ c.jmp(__done);
+ /* imm > 0 */
+ c.bind(__gr0);
+ c.cmp(imm, 32);
+ c.jl(__lt32);
+ /* imm > 31 */
+ c.sar(reg_pos_thumb(0), 31);
+ c.sets(rcf.r8Lo());
+ c.jmp(__setFlags);
+ /* imm < 32 */
+ c.bind(__lt32);
+ c.sar(reg_pos_thumb(0), imm);
+ c.setc(rcf.r8Lo());
+ c.bind(__setFlags);
+ SET_NZC;
+ c.bind(__done);
+ return 1;
+}
+
+// -----------------------------------------------------------------------------
+// ROR
+// -----------------------------------------------------------------------------
+static int OP_ROR_REG(uint32_t i)
+{
+ uint8_t cf_change = 1;
+ GpVar imm = c.newGpVar(kX86VarTypeGpz);
+ GpVar rcf = c.newGpVar(kX86VarTypeGpd);
+ Label __zero = c.newLabel();
+ Label __zero_1F = c.newLabel();
+ Label __done = c.newLabel();
+
+ c.mov(imm, reg_pos_thumb(3));
+ c.and_(imm, 0xFF);
+ c.jz(__zero);
+ c.and_(imm, 0x1F);
+ c.jz(__zero_1F);
+ c.ror(reg_pos_thumb(0), imm);
+ c.setc(rcf.r8Lo());
+ SET_NZC;
+ c.jmp(__done);
+ /* imm & 0x1F == 0 */
+ c.bind(__zero_1F);
+ c.cmp(reg_pos_thumb(0), 0);
+ c.sets(rcf.r8Lo());
+ SET_NZC;
+ c.jmp(__done);
+ /* imm == 0 */
+ c.bind(__zero);
+ c.cmp(reg_pos_thumb(0), 0);
+ SET_NZ(0);
+ c.bind(__done);
+
+ return 1;
+}
+
+// -----------------------------------------------------------------------------
+// AND / ORR / EOR / BIC
+// -----------------------------------------------------------------------------
+static int OP_AND(uint32_t i) { OP_LOGIC(and_, 0); }
+static int OP_ORR(uint32_t i) { OP_LOGIC(or_, 0); }
+static int OP_EOR(uint32_t i) { OP_LOGIC(xor_, 0); }
+static int OP_BIC(uint32_t i) { OP_LOGIC(and_, 1); }
+
+// -----------------------------------------------------------------------------
+// NEG
+// -----------------------------------------------------------------------------
+static int OP_NEG(uint32_t i)
+{
+ if (_REG_NUM(i, 0) == _REG_NUM(i, 3))
+ c.neg(reg_pos_thumb(0));
+ else
+ {
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd);
+ c.mov(tmp, reg_pos_thumb(3));
+ c.neg(tmp);
+ c.mov(reg_pos_thumb(0), tmp);
+ }
+ SET_NZCV(1);
+ return 1;
+}
+
+//-----------------------------------------------------------------------------
+// ADD
+//-----------------------------------------------------------------------------
+static int OP_ADD_IMM3(uint32_t i)
+{
+ uint32_t imm3 = (i >> 6) & 0x07;
+
+ if (!imm3) // mov 2
+ {
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd);
+ c.mov(tmp, reg_pos_thumb(3));
+ c.mov(reg_pos_thumb(0), tmp);
+ c.cmp(tmp, 0);
+ SET_NZ(1);
+ return 1;
+ }
+ if (_REG_NUM(i, 0) == _REG_NUM(i, 3))
+ c.add(reg_pos_thumb(0), imm3);
+ else
+ {
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd);
+ c.mov(tmp, reg_pos_thumb(3));
+ c.add(tmp, imm3);
+ c.mov(reg_pos_thumb(0), tmp);
+ }
+ SET_NZCV(0);
+ return 1;
+}
+static int OP_ADD_IMM8(uint32_t i)
+{
+ c.add(reg_pos_thumb(8), (i & 0xFF));
+ SET_NZCV(0);
+
+ return 1;
+}
+static int OP_ADD_REG(uint32_t i)
+{
+ //cpu->R[REG_NUM(i, 0)] = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
+ if (_REG_NUM(i, 0) == _REG_NUM(i, 3))
+ {
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd);
+ c.mov(tmp, reg_pos_thumb(6));
+ c.add(reg_pos_thumb(0), tmp);
+ }
+ else
+ {
+ if (_REG_NUM(i, 0) == _REG_NUM(i, 6))
+ {
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd);
+ c.mov(tmp, reg_pos_thumb(3));
+ c.add(reg_pos_thumb(0), tmp);
+ }
+ else
+ {
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd);
+ c.mov(tmp, reg_pos_thumb(3));
+ c.add(tmp, reg_pos_thumb(6));
+ c.mov(reg_pos_thumb(0), tmp);
+ }
+ }
+ SET_NZCV(0);
+ return 1;
+}
+static int OP_ADD_SPE(uint32_t i)
+{
+ uint32_t Rd = _REG_NUM(i, 0) | ((i >> 4) & 8);
+ //cpu->R[Rd] += cpu->R[REG_POS(i, 3)];
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd);
+ c.mov(tmp, reg_ptr(Rd));
+ c.add(tmp, reg_pos_ptr(3));
+ c.mov(reg_ptr(Rd), tmp);
+
+ if (Rd == 15)
+ c.mov(cpu_ptr(next_instruction), tmp);
+
+ return 1;
+}
+
+static int OP_ADD_2PC(uint32_t i)
+{
+ uint32_t imm = (i & 0xFF) << 2;
+ c.mov(reg_pos_thumb(8), (bb_r15 & 0xFFFFFFFC) + imm);
+ return 1;
+}
+
+static int OP_ADD_2SP(uint32_t i)
+{
+ uint32_t imm = (i & 0xFF) << 2;
+ //cpu->R[REG_NUM(i, 8)] = cpu->R[13] + ((i&0xFF)<<2);
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd);
+ c.mov(tmp, reg_ptr(13));
+ if (imm)
+ c.add(tmp, imm);
+ c.mov(reg_pos_thumb(8), tmp);
+
+ return 1;
+}
+
+// -----------------------------------------------------------------------------
+// SUB
+// -----------------------------------------------------------------------------
+static int OP_SUB_IMM3(uint32_t i)
+{
+ uint32_t imm3 = (i >> 6) & 0x07;
+
+ // cpu->R[REG_NUM(i, 0)] = cpu->R[REG_NUM(i, 3)] - imm3;
+ if (_REG_NUM(i, 0) == _REG_NUM(i, 3))
+ c.sub(reg_pos_thumb(0), imm3);
+ else
+ {
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd);
+ c.mov(tmp, reg_pos_thumb(3));
+ c.sub(tmp, imm3);
+ c.mov(reg_pos_thumb(0), tmp);
+ }
+ SET_NZCV(1);
+ return 1;
+}
+static int OP_SUB_IMM8(uint32_t i)
+{
+ //cpu->R[REG_NUM(i, 8)] -= imm8;
+ c.sub(reg_pos_thumb(8), i & 0xFF);
+ SET_NZCV(1);
+ return 1;
+}
+static int OP_SUB_REG(uint32_t i)
+{
+ // cpu->R[REG_NUM(i, 0)] = cpu->R[REG_NUM(i, 3)] - cpu->R[REG_NUM(i, 6)];
+ if (_REG_NUM(i, 0) == _REG_NUM(i, 3))
+ {
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd);
+ c.mov(tmp, reg_pos_thumb(6));
+ c.sub(reg_pos_thumb(0), tmp);
+ }
+ else
+ {
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd);
+ c.mov(tmp, reg_pos_thumb(3));
+ c.sub(tmp, reg_pos_thumb(6));
+ c.mov(reg_pos_thumb(0), tmp);
+ }
+ SET_NZCV(1);
+ return 1;
+}
+
+// -----------------------------------------------------------------------------
+// ADC
+// -----------------------------------------------------------------------------
+static int OP_ADC_REG(uint32_t i)
+{
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd);
+ c.mov(tmp, reg_pos_thumb(3));
+ GET_CARRY(0);
+ c.adc(reg_pos_thumb(0), tmp);
+ SET_NZCV(0);
+ return 1;
+}
+
+// -----------------------------------------------------------------------------
+// SBC
+// -----------------------------------------------------------------------------
+static int OP_SBC_REG(uint32_t i)
+{
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd);
+ c.mov(tmp, reg_pos_thumb(3));
+ GET_CARRY(1);
+ c.sbb(reg_pos_thumb(0), tmp);
+ SET_NZCV(1);
+ return 1;
+}
+
+// -----------------------------------------------------------------------------
+// MOV / MVN
+// -----------------------------------------------------------------------------
+static int OP_MOV_IMM8(uint32_t i)
+{
+ c.mov(reg_pos_thumb(8), i & 0xFF);
+ c.cmp(reg_pos_thumb(8), 0);
+ SET_NZ(0);
+ return 1;
+}
+
+static int OP_MOV_SPE(uint32_t i)
+{
+ uint32_t Rd = _REG_NUM(i, 0) | ((i >> 4) & 8);
+ //cpu->R[Rd] = cpu->R[REG_POS(i, 3)];
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd);
+ c.mov(tmp, reg_pos_ptr(3));
+ c.mov(reg_ptr(Rd), tmp);
+ if (Rd == 15)
+ {
+ c.mov(cpu_ptr(next_instruction), tmp);
+ bb_constant_cycles += 2;
+ }
+
+ return 1;
+}
+
+static int OP_MVN(uint32_t i)
+{
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd);
+ c.mov(tmp, reg_pos_thumb(3));
+ c.not_(tmp);
+ c.cmp(tmp, 0);
+ c.mov(reg_pos_thumb(0), tmp);
+ SET_NZ(0);
+ return 1;
+}
+
+// -----------------------------------------------------------------------------
+// MUL
+// -----------------------------------------------------------------------------
+static int OP_MUL_REG(uint32_t i)
+{
+ GpVar lhs = c.newGpVar(kX86VarTypeGpd);
+ c.mov(lhs, reg_pos_thumb(0));
+ c.imul(lhs, reg_pos_thumb(3));
+ c.cmp(lhs, 0);
+ c.mov(reg_pos_thumb(0), lhs);
+ SET_NZ(0);
+ if (PROCNUM == ARMCPU_ARM7)
+ c.mov(bb_cycles, 4);
+ else
+ MUL_Mxx_END(lhs, 0, 1);
+ return 1;
+}
+
+// -----------------------------------------------------------------------------
+// CMP / CMN
+// -----------------------------------------------------------------------------
+static int OP_CMP_IMM8(uint32_t i)
+{
+ c.cmp(reg_pos_thumb(8), i & 0xFF);
+ SET_NZCV(1);
+ return 1;
+}
+
+static int OP_CMP(uint32_t i)
+{
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd);
+ c.mov(tmp, reg_pos_thumb(3));
+ c.cmp(reg_pos_thumb(0), tmp);
+ SET_NZCV(1);
+ return 1;
+}
+
+static int OP_CMP_SPE(uint32_t i)
+{
+ uint32_t Rn = (i & 7) | ((i >> 4) & 8);
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd);
+ c.mov(tmp, reg_pos_ptr(3));
+ c.cmp(reg_ptr(Rn), tmp);
+ SET_NZCV(1);
+ return 1;
+}
+
+static int OP_CMN(uint32_t i)
+{
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd);
+ c.mov(tmp, reg_pos_thumb(0));
+ c.add(tmp, reg_pos_thumb(3));
+ SET_NZCV(0);
+ return 1;
+}
+
+// -----------------------------------------------------------------------------
+// TST
+// -----------------------------------------------------------------------------
+static int OP_TST(uint32_t i)
+{
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd);
+ c.mov(tmp, reg_pos_thumb(3));
+ c.test(reg_pos_thumb(0), tmp);
+ SET_NZ(0);
+ return 1;
+}
+
+// -----------------------------------------------------------------------------
+// STR / LDR / STRB / LDRB
+// -----------------------------------------------------------------------------
+#define STR_THUMB(mem_op, offset) \
+ GpVar addr = c.newGpVar(kX86VarTypeGpd); \
+ GpVar data = c.newGpVar(kX86VarTypeGpd); \
+ uint32_t adr_first = cpu->R[_REG_NUM(i, 3)]; \
+\
+ c.mov(addr, reg_pos_thumb(3)); \
+ if ((offset) != -1) \
+ { \
+ if ((offset)) \
+ { \
+ c.add(addr, static_cast<uint32_t>((offset))); \
+ adr_first += static_cast<uint32_t>((offset)); \
+ } \
+ } \
+ else \
+ { \
+ c.add(addr, reg_pos_thumb(6)); \
+ adr_first += cpu->R[_REG_NUM(i, 6)]; \
+ } \
+ c.mov(data, reg_pos_thumb(0)); \
+ X86CompilerFuncCall *ctx = c.call(reinterpret_cast<void *>(mem_op##_tab[PROCNUM][classify_adr(adr_first, 1)])); \
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder2<void, uint32_t, uint32_t>()); \
+ ctx->setArgument(0, addr); \
+ ctx->setArgument(1, data); \
+ ctx->setReturn(bb_cycles); \
+ return 1;
+
+#define LDR_THUMB(mem_op, offset) \
+ GpVar addr = c.newGpVar(kX86VarTypeGpd); \
+ GpVar data = c.newGpVar(kX86VarTypeGpz); \
+ uint32_t adr_first = cpu->R[_REG_NUM(i, 3)]; \
+\
+ c.mov(addr, reg_pos_thumb(3)); \
+ if ((offset) != -1) \
+ { \
+ if ((offset)) \
+ { \
+ c.add(addr, static_cast<uint32_t>((offset))); \
+ adr_first += static_cast<uint32_t>((offset)); \
+ } \
+ } \
+ else \
+ { \
+ c.add(addr, reg_pos_thumb(6)); \
+ adr_first += cpu->R[_REG_NUM(i, 6)]; \
+ } \
+ c.lea(data, reg_pos_thumb(0)); \
+ X86CompilerFuncCall *ctx = c.call(reinterpret_cast<void *>(mem_op##_tab[PROCNUM][classify_adr(adr_first, 0)])); \
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder2<void, uint32_t, uint32_t *>()); \
+ ctx->setArgument(0, addr); \
+ ctx->setArgument(1, data); \
+ ctx->setReturn(bb_cycles); \
+ return 1;
+
+static int OP_STRB_IMM_OFF(uint32_t i) { STR_THUMB(STRB, (i >> 6) & 0x1F); }
+static int OP_LDRB_IMM_OFF(uint32_t i) { LDR_THUMB(LDRB, (i >> 6) & 0x1F); }
+static int OP_STRB_REG_OFF(uint32_t i) { STR_THUMB(STRB, -1); }
+static int OP_LDRB_REG_OFF(uint32_t i) { LDR_THUMB(LDRB, -1); }
+static int OP_LDRSB_REG_OFF(uint32_t i) { LDR_THUMB(LDRSB, -1); }
+
+static int OP_STRH_IMM_OFF(uint32_t i) { STR_THUMB(STRH, (i >> 5) & 0x3E); }
+static int OP_LDRH_IMM_OFF(uint32_t i) { LDR_THUMB(LDRH, (i >> 5) & 0x3E); }
+static int OP_STRH_REG_OFF(uint32_t i) { STR_THUMB(STRH, -1); }
+static int OP_LDRH_REG_OFF(uint32_t i) { LDR_THUMB(LDRH, -1); }
+static int OP_LDRSH_REG_OFF(uint32_t i) { LDR_THUMB(LDRSH, -1); }
+
+static int OP_STR_IMM_OFF(uint32_t i) { STR_THUMB(STR, (i >> 4) & 0x7C); }
+static int OP_LDR_IMM_OFF(uint32_t i) { LDR_THUMB(LDR, (i >> 4) & 0x7C); } // FIXME: tempValue = (tempValue>>adr) | (tempValue<<(32-adr));
+static int OP_STR_REG_OFF(uint32_t i) { STR_THUMB(STR, -1); }
+static int OP_LDR_REG_OFF(uint32_t i) { LDR_THUMB(LDR, -1); }
+
+static int OP_STR_SPREL(uint32_t i)
+{
+ uint32_t imm = (i & 0xFF) << 2;
+ uint32_t adr_first = cpu->R[13] + imm;
+
+ GpVar addr = c.newGpVar(kX86VarTypeGpd);
+ c.mov(addr, reg_ptr(13));
+ if (imm)
+ c.add(addr, imm);
+ GpVar data = c.newGpVar(kX86VarTypeGpd);
+ c.mov(data, reg_pos_thumb(8));
+ X86CompilerFuncCall *ctx = c.call(reinterpret_cast<void *>(STR_tab[PROCNUM][classify_adr(adr_first, 1)]));
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder2<void, uint32_t, uint32_t>());
+ ctx->setArgument(0, addr);
+ ctx->setArgument(1, data);
+ ctx->setReturn(bb_cycles);
+ return 1;
+}
+
+static int OP_LDR_SPREL(uint32_t i)
+{
+ uint32_t imm = (i & 0xFF) << 2;
+ uint32_t adr_first = cpu->R[13] + imm;
+
+ GpVar addr = c.newGpVar(kX86VarTypeGpd);
+ c.mov(addr, reg_ptr(13));
+ if (imm)
+ c.add(addr, imm);
+ GpVar data = c.newGpVar(kX86VarTypeGpz);
+ c.lea(data, reg_pos_thumb(8));
+ X86CompilerFuncCall *ctx = c.call(reinterpret_cast<void *>(LDR_tab[PROCNUM][classify_adr(adr_first, 0)]));
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder2<void, uint32_t, uint32_t *>());
+ ctx->setArgument(0, addr);
+ ctx->setArgument(1, data);
+ ctx->setReturn(bb_cycles);
+ return 1;
+}
+
+static int OP_LDR_PCREL(uint32_t i)
+{
+ uint32_t imm = (i & 0xFF) << 2;
+ uint32_t adr_first = (bb_r15 & 0xFFFFFFFC) + imm;
+ GpVar addr = c.newGpVar(kX86VarTypeGpd);
+ GpVar data = c.newGpVar(kX86VarTypeGpz);
+ c.mov(addr, adr_first);
+ c.lea(data, reg_pos_thumb(8));
+ X86CompilerFuncCall *ctx = c.call(reinterpret_cast<void *>(LDR_tab[PROCNUM][classify_adr(adr_first, 0)]));
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder2<void, uint32_t, uint32_t *>());
+ ctx->setArgument(0, addr);
+ ctx->setArgument(1, data);
+ ctx->setReturn(bb_cycles);
+ return 1;
+}
+
+// -----------------------------------------------------------------------------
+// STMIA / LDMIA
+// -----------------------------------------------------------------------------
+static int op_ldm_stm_thumb(uint32_t i, bool store)
+{
+ uint32_t bitmask = i & 0xFF;
+ uint32_t pop = popcount(bitmask);
+
+ //if (BIT_N(i, _REG_NUM(i, 8)))
+ // printf("WARNING - %sIA with Rb in Rlist (THUMB)\n", store?"STM":"LDM");
+
+ GpVar adr = c.newGpVar(kX86VarTypeGpd);
+ c.mov(adr, reg_pos_thumb(8));
+
+ call_ldm_stm(adr, bitmask, store, 1);
+
+ // ARM_REF: THUMB: Causes base register write-back, and is not optional
+ // ARM_REF: If the base register <Rn> is specified in <registers>, the final value of <Rn> is the loaded value
+ // (not the written-back value).
+ if (store)
+ c.add(reg_pos_thumb(8), 4 * pop);
+ else
+ {
+ if (!BIT_N(i, _REG_NUM(i, 8)))
+ c.add(reg_pos_thumb(8), 4 * pop);
+ }
+
+ emit_MMU_aluMemCycles(store ? 2 : 3, bb_cycles, pop);
+ return 1;
+}
+
+static int OP_LDMIA_THUMB(uint32_t i) { return op_ldm_stm_thumb(i, 0); }
+static int OP_STMIA_THUMB(uint32_t i) { return op_ldm_stm_thumb(i, 1); }
+
+// -----------------------------------------------------------------------------
+// Adjust SP
+// -----------------------------------------------------------------------------
+static int OP_ADJUST_P_SP(uint32_t i) { c.add(reg_ptr(13), (i & 0x7F) << 2); return 1; }
+static int OP_ADJUST_M_SP(uint32_t i) { c.sub(reg_ptr(13), (i & 0x7F) << 2); return 1; }
+
+// -----------------------------------------------------------------------------
+// PUSH / POP
+// -----------------------------------------------------------------------------
+static int op_push_pop(uint32_t i, bool store, bool pc_lr)
+{
+ uint32_t bitmask = i & 0xFF;
+ bitmask |= pc_lr << (store ? 14 : 15);
+ uint32_t pop = popcount(bitmask);
+ int dir = store ? -1 : 1;
+
+ GpVar adr = c.newGpVar(kX86VarTypeGpd);
+ c.mov(adr, reg_ptr(13));
+ if (store)
+ c.sub(adr, 4);
+
+ call_ldm_stm(adr, bitmask, store, dir);
+
+ if (pc_lr && !store)
+ op_bx_thumb(reg_ptr(15), 0, PROCNUM == ARMCPU_ARM9);
+ c.add(reg_ptr(13), 4 * dir * pop);
+
+ emit_MMU_aluMemCycles(store ? (pc_lr ? 4 : 3) : (pc_lr ? 5 : 2), bb_cycles, pop);
+ return 1;
+}
+
+static int OP_PUSH(uint32_t i) { return op_push_pop(i, 1, 0); }
+static int OP_PUSH_LR(uint32_t i) { return op_push_pop(i, 1, 1); }
+static int OP_POP(uint32_t i) { return op_push_pop(i, 0, 0); }
+static int OP_POP_PC(uint32_t i) { return op_push_pop(i, 0, 1); }
+
+// -----------------------------------------------------------------------------
+// Branch
+// -----------------------------------------------------------------------------
+static int OP_B_COND(uint32_t i)
+{
+ Label skip = c.newLabel();
+
+ uint32_t dst = bb_r15 + (static_cast<uint32_t>(static_cast<int8_t>(i & 0xFF)) << 1);
+
+ c.mov(cpu_ptr(instruct_adr), bb_next_instruction);
+
+ emit_branch((i >> 8) & 0xF, skip);
+ c.mov(cpu_ptr(instruct_adr), dst);
+ c.add(bb_total_cycles, 2);
+ c.bind(skip);
+
+ return 1;
+}
+
+static int OP_B_UNCOND(uint32_t i)
+{
+ uint32_t dst = bb_r15 + (SIGNEXTEND_11(i) << 1);
+ c.mov(cpu_ptr(instruct_adr), dst);
+ return 1;
+}
+
+static int OP_BLX(uint32_t i)
+{
+ GpVar dst = c.newGpVar(kX86VarTypeGpd);
+ c.mov(dst, reg_ptr(14));
+ c.add(dst, (i & 0x7FF) << 1);
+ c.and_(dst, 0xFFFFFFFC);
+ c.mov(cpu_ptr(instruct_adr), dst);
+ c.mov(reg_ptr(14), bb_next_instruction | 1);
+ // reset T bit
+ c.and_(cpu_ptr_byte(CPSR, 0), ~(1 << 5));
+ return 1;
+}
+
+static int OP_BL_10( uint32_t i)
+{
+ uint32_t dst = bb_r15 + (SIGNEXTEND_11(i) << 12);
+ c.mov(reg_ptr(14), dst);
+ return 1;
+}
+
+static int OP_BL_11(uint32_t i)
+{
+ GpVar dst = c.newGpVar(kX86VarTypeGpd);
+ c.mov(dst, reg_ptr(14));
+ c.add(dst, (i & 0x7FF) << 1);
+ c.mov(cpu_ptr(instruct_adr), dst);
+ c.mov(reg_ptr(14), bb_next_instruction | 1);
+ return 1;
+}
+
+static int op_bx_thumb(Mem srcreg, bool blx, bool test_thumb)
+{
+ GpVar dst = c.newGpVar(kX86VarTypeGpd);
+ GpVar thumb = c.newGpVar(kX86VarTypeGpd);
+ c.mov(dst, srcreg);
+ c.mov(thumb, dst); // * cpu->CPSR.bits.T = BIT0(Rm);
+ c.and_(thumb, 1); // *
+ if (blx)
+ c.mov(reg_ptr(14), bb_next_instruction | 1);
+ if (test_thumb)
+ {
+ GpVar mask = c.newGpVar(kX86VarTypeGpd);
+ c.lea(mask, ptr_abs(reinterpret_cast<void *>(0xFFFFFFFC), thumb.r64(), kScale2Times));
+ c.and_(dst, mask);
+ }
+ else
+ c.and_(dst, 0xFFFFFFFE);
+
+ GpVar tmp = c.newGpVar(kX86VarTypeGpd); // *
+ c.mov(tmp, cpu_ptr_byte(CPSR, 0)); // *
+ c.and_(tmp, ~(1 << 5)); // *
+ c.shl(thumb, 5); // *
+ c.or_(tmp, thumb); // *
+ c.mov(cpu_ptr_byte(CPSR, 0), tmp.r8Lo()); // ******************************
+
+ c.mov(cpu_ptr(instruct_adr), dst);
+ return 1;
+}
+
+static int OP_BX_THUMB(uint32_t i) { if (REG_POS(i, 3) == 15) c.mov(reg_ptr(15), bb_r15); return op_bx_thumb(reg_pos_ptr(3), 0, 0); }
+static int OP_BLX_THUMB(uint32_t i) { return op_bx_thumb(reg_pos_ptr(3), 1, 1); }
+
+static int OP_SWI_THUMB(uint32_t i) { return op_swi(i & 0x1F); }
+
+// -----------------------------------------------------------------------------
+// Unimplemented; fall back to the C versions
+// -----------------------------------------------------------------------------
+
+#define OP_UND nullptr
+#define OP_LDREX nullptr
+#define OP_STREX nullptr
+#define OP_LDC_P_IMM_OFF nullptr
+#define OP_LDC_M_IMM_OFF nullptr
+#define OP_LDC_P_PREIND nullptr
+#define OP_LDC_M_PREIND nullptr
+#define OP_LDC_P_POSTIND nullptr
+#define OP_LDC_M_POSTIND nullptr
+#define OP_LDC_OPTION nullptr
+#define OP_STC_P_IMM_OFF nullptr
+#define OP_STC_M_IMM_OFF nullptr
+#define OP_STC_P_PREIND nullptr
+#define OP_STC_M_PREIND nullptr
+#define OP_STC_P_POSTIND nullptr
+#define OP_STC_M_POSTIND nullptr
+#define OP_STC_OPTION nullptr
+#define OP_CDP nullptr
+
+#define OP_UND_THUMB nullptr
+#define OP_BKPT_THUMB nullptr
+
+// -----------------------------------------------------------------------------
+// Dispatch table
+// -----------------------------------------------------------------------------
+
+typedef int (*ArmOpCompiler)(uint32_t);
+static const ArmOpCompiler arm_instruction_compilers[4096] =
+{
+#define TABDECL(x) x
+#include "instruction_tabdef.inc"
+#undef TABDECL
+};
+
+static const ArmOpCompiler thumb_instruction_compilers[1024] =
+{
+#define TABDECL(x) x
+#include "thumb_tabdef.inc"
+#undef TABDECL
+};
+
+//-----------------------------------------------------------------------------
+// Generic instruction wrapper
+//-----------------------------------------------------------------------------
+
+template<int PROCNUM, int thumb> static uint32_t FASTCALL OP_DECODE()
+{
+ uint32_t cycles;
+ uint32_t adr = cpu->instruct_adr;
+ if (thumb)
+ {
+ cpu->next_instruction = adr + 2;
+ cpu->R[15] = adr + 4;
+ uint32_t opcode = _MMU_read16<PROCNUM, MMU_AT_CODE>(adr);
+ _armlog(PROCNUM, adr, opcode);
+ cycles = thumb_instructions_set[PROCNUM][opcode >> 6](opcode);
+ }
+ else
+ {
+ cpu->next_instruction = adr + 4;
+ cpu->R[15] = adr + 8;
+ uint32_t opcode = _MMU_read32<PROCNUM, MMU_AT_CODE>(adr);
+ _armlog(PROCNUM, adr, opcode);
+ if (CONDITION(opcode) == 0xE || TEST_COND(CONDITION(opcode), CODE(opcode), cpu->CPSR))
+ cycles = arm_instructions_set[PROCNUM][INSTRUCTION_INDEX(opcode)](opcode);
+ else
+ cycles = 1;
+ }
+ cpu->instruct_adr = cpu->next_instruction;
+ return cycles;
+}
+
+static const ArmOpCompiled op_decode[][2] = { { OP_DECODE<0, 0>, OP_DECODE<0, 1> }, { OP_DECODE<1, 0>, OP_DECODE<1, 1> } };
+
+// -----------------------------------------------------------------------------
+// Compiler
+// -----------------------------------------------------------------------------
+
+static uint32_t instr_attributes(uint32_t opcode)
+{
+ return bb_thumb ? thumb_attributes[opcode >> 6] : instruction_attributes[INSTRUCTION_INDEX(opcode)];
+}
+
+static bool instr_is_branch(uint32_t opcode)
+{
+ uint32_t x = instr_attributes(opcode);
+ if (bb_thumb)
+ return (x & BRANCH_ALWAYS) || ((x & BRANCH_POS0) && ((opcode & 7) | ((opcode >> 4) & 8)) == 15) || (x & BRANCH_SWI) || (x & JIT_BYPASS);
+ else
+ return (x & BRANCH_ALWAYS) || ((x & BRANCH_POS12) && REG_POS(opcode, 12) == 15) || ((x & BRANCH_LDM) && BIT15(opcode)) || (x & BRANCH_SWI) || (x & JIT_BYPASS);
+}
+
+static bool instr_uses_r15(uint32_t opcode)
+{
+ uint32_t x = instr_attributes(opcode);
+ if (bb_thumb)
+ return ((x & SRCREG_POS0) && ((opcode & 7) | ((opcode >> 4) & 8)) == 15) || ((x & SRCREG_POS3) && REG_POS(opcode, 3) == 15) || (x & JIT_BYPASS);
+ else
+ return ((x & SRCREG_POS0) && REG_POS(opcode, 0) == 15) || ((x & SRCREG_POS8) && REG_POS(opcode, 8) == 15) || ((x & SRCREG_POS12) && REG_POS(opcode, 12) == 15) ||
+ ((x & SRCREG_POS16) && REG_POS(opcode, 16) == 15) || ((x & SRCREG_STM) && BIT15(opcode)) || (x & JIT_BYPASS);
+}
+
+static bool instr_is_conditional(uint32_t opcode)
+{
+ if (bb_thumb)
+ return false;
+
+ return !(CONDITION(opcode) == 0xE || (CONDITION(opcode) == 0xF && CODE(opcode) == 5));
+}
+
+static int instr_cycles(uint32_t opcode)
+{
+ uint32_t x = instr_attributes(opcode);
+ uint32_t c = x & INSTR_CYCLES_MASK;
+ if (c == INSTR_CYCLES_VARIABLE)
+ {
+ if ((x & BRANCH_SWI) && !cpu->swi_tab)
+ return 3;
+
+ return 0;
+ }
+ if (instr_is_branch(opcode) && !(instr_attributes(opcode) & (BRANCH_ALWAYS | BRANCH_LDM)))
+ c += 2;
+ return c;
+}
+
+static bool instr_does_prefetch(uint32_t opcode)
+{
+ uint32_t x = instr_attributes(opcode);
+ if(bb_thumb)
+ return thumb_instruction_compilers[opcode >> 6] && (x & BRANCH_ALWAYS);
+ else
+ return instr_is_branch(opcode) && arm_instruction_compilers[INSTRUCTION_INDEX(opcode)] && ((x & BRANCH_ALWAYS) || (x & BRANCH_LDM));
+}
+
+static void sync_r15(uint32_t opcode, bool is_last, bool force)
+{
+ if (instr_does_prefetch(opcode))
+ {
+ assert(!instr_uses_r15(opcode));
+ if (force)
+ {
+ JIT_COMMENT("sync_r15: force instruct_adr %08Xh (PREFETCH)", bb_adr);
+ c.mov(cpu_ptr(instruct_adr), bb_next_instruction);
+ }
+ }
+ else
+ {
+ if (force || (instr_attributes(opcode) & JIT_BYPASS) || (instr_attributes(opcode) & BRANCH_SWI) || (is_last && !instr_is_branch(opcode)))
+ {
+ JIT_COMMENT("sync_r15: next_instruction %08Xh - %s%s%s%s", bb_next_instruction,
+ force ? " FORCE" : "",
+ (instr_attributes(opcode) & JIT_BYPASS) ? " BYPASS" : "",
+ (instr_attributes(opcode) & BRANCH_SWI) ? " SWI" : "",
+ is_last && !instr_is_branch(opcode) ? " LAST" : ""
+ );
+ c.mov(cpu_ptr(next_instruction), bb_next_instruction);
+ }
+ if (instr_uses_r15(opcode))
+ {
+ JIT_COMMENT("sync_r15: R15 %08Xh (USES R15)", bb_r15);
+ c.mov(reg_ptr(15), bb_r15);
+ }
+ if (instr_attributes(opcode) & JIT_BYPASS)
+ {
+ JIT_COMMENT("sync_r15: instruct_adr %08Xh (JIT_BYPASS)", bb_adr);
+ c.mov(cpu_ptr(instruct_adr), bb_adr);
+ }
+ }
+}
+
+static void emit_branch(int cond, Label to)
+{
+ JIT_COMMENT("emit_branch cond %02X", cond);
+ static const uint8_t cond_bit[] = { 0x40, 0x40, 0x20, 0x20, 0x80, 0x80, 0x10, 0x10 };
+ if (cond < 8)
+ {
+ c.test(flags_ptr, cond_bit[cond]);
+ (cond & 1) ? c.jnz(to) : c.jz(to);
+ }
+ else
+ {
+ GpVar x = c.newGpVar(kX86VarTypeGpz);
+ c.movzx(x, flags_ptr);
+ c.and_(x, 0xF0);
+#if defined(_M_X64) || defined(__x86_64__)
+ c.add(x, offsetof(armcpu_t,cond_table) + cond);
+ c.test(byte_ptr(bb_cpu, x), 1);
+#else
+ c.test(byte_ptr_abs((void *)(arm_cond_table + cond), x, kScaleNone), 1);
+#endif
+ c.unuse(x);
+ c.jz(to);
+ }
+}
+
+static void emit_armop_call(uint32_t opcode)
+{
+ ArmOpCompiler fc = bb_thumb ? thumb_instruction_compilers[opcode >> 6] : arm_instruction_compilers[INSTRUCTION_INDEX(opcode)];
+ if (fc && fc(opcode))
+ return;
+
+ JIT_COMMENT("call interpreter");
+ GpVar arg = c.newGpVar(kX86VarTypeGpd);
+ c.mov(arg, opcode);
+ OpFunc f = bb_thumb ? thumb_instructions_set[PROCNUM][opcode >> 6] : arm_instructions_set[PROCNUM][INSTRUCTION_INDEX(opcode)];
+ X86CompilerFuncCall *ctx = c.call(reinterpret_cast<void *>(f));
+ ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder1<uint32_t, uint32_t>());
+ ctx->setArgument(0, arg);
+ ctx->setReturn(bb_cycles);
+}
+
+static void _armlog(uint8_t proc, uint32_t addr, uint32_t opcode)
+{
+#if 0
+#if 0
+ fprintf(stderr, "\t\t;R0:%08X R1:%08X R2:%08X R3:%08X R4:%08X R5:%08X R6:%08X R7:%08X R8:%08X R9:%08X\n\t\t;R10:%08X R11:%08X R12:%08X R13:%08X R14:%08X R15:%08X| next %08X, N:%i Z:%i C:%i V:%i\n",
+ cpu->R[0], cpu->R[1], cpu->R[2], cpu->R[3], cpu->R[4], cpu->R[5], cpu->R[6], cpu->R[7],
+ cpu->R[8], cpu->R[9], cpu->R[10], cpu->R[11], cpu->R[12], cpu->R[13], cpu->R[14], cpu->R[15],
+ cpu->next_instruction, cpu->CPSR.bits.N, cpu->CPSR.bits.Z, cpu->CPSR.bits.C, cpu->CPSR.bits.V);
+#endif
+ #define INDEX22(i) ((((i)>>16)&0xFF0)|(((i)>>4)&0xF))
+ char dasmbuf[4096];
+ if(cpu->CPSR.bits.T)
+ des_thumb_instructions_set[((opcode)>>6)&1023](addr, opcode, dasmbuf);
+ else
+ des_arm_instructions_set[INDEX22(opcode)](addr, opcode, dasmbuf);
+ #undef INDEX22
+ fprintf(stderr, "%s%c %08X\t%08X \t%s\n", cpu->CPSR.bits.T?"THUMB":"ARM", proc?'7':'9', addr, opcode, dasmbuf);
+#endif
+}
+
+template<int PROCNUM> static uint32_t compile_basicblock()
+{
+#if LOG_JIT
+ bool has_variable_cycles = false;
+#endif
+ uint32_t interpreted_cycles = 0;
+ uint32_t start_adr = cpu->instruct_adr;
+ uint32_t opcode = 0;
+
+ bb_thumb = cpu->CPSR.bits.T;
+ bb_opcodesize = bb_thumb ? 2 : 4;
+
+ if (!JIT_MAPPED(start_adr & 0x0FFFFFFF, PROCNUM))
+ {
+ printf("JIT: use unmapped memory address %08X\n", start_adr);
+ execute = false;
+ return 1;
+ }
+
+#if LOG_JIT
+ fprintf(stderr, "adr %08Xh %s%c\n", start_adr, ARMPROC.CPSR.bits.T ? "THUMB":"ARM", PROCNUM?'7':'9');
+#endif
+
+ c.clear();
+ c.newFunc(ASMJIT_CALL_CONV, FuncBuilder0<int>());
+ c.getFunc()->setHint(kFuncHintNaked, true);
+ c.getFunc()->setHint(kX86FuncHintPushPop, true);
+
+ JIT_COMMENT("CPU ptr");
+ bb_cpu = c.newGpVar(kX86VarTypeGpz);
+ c.mov(bb_cpu, (uintptr_t)&ARMPROC);
+
+ JIT_COMMENT("reset bb_total_cycles");
+ bb_total_cycles = c.newGpVar(kX86VarTypeGpz);
+ c.mov(bb_total_cycles, 0);
+
+#if (PROFILER_JIT_LEVEL > 0)
+ JIT_COMMENT("Profiler ptr");
+ bb_profiler = c.newGpVar(kX86VarTypeGpz);
+ c.mov(bb_profiler, reinterpret_cast<uintptr_t>(&profiler_counter[PROCNUM]));
+#endif
+
+ bb_constant_cycles = 0;
+ for (uint32_t i = 0, bEndBlock = 0; !bEndBlock; ++i)
+ {
+ bb_adr = start_adr + (i * bb_opcodesize);
+ if (bb_thumb)
+ opcode = _MMU_read16<PROCNUM, MMU_AT_CODE>(bb_adr);
+ else
+ opcode = _MMU_read32<PROCNUM, MMU_AT_CODE>(bb_adr);
+
+#if LOG_JIT
+ char dasmbuf[1024] = {0};
+ if (bb_thumb)
+ des_thumb_instructions_set[opcode >> 6](bb_adr, opcode, dasmbuf);
+ else
+ des_arm_instructions_set[INSTRUCTION_INDEX(opcode)](bb_adr, opcode, dasmbuf);
+ fprintf(stderr, "%08X\t%s\t\t; %s \n", bb_adr, dasmbuf, disassemble(opcode));
+#endif
+
+ uint32_t cycles = instr_cycles(opcode);
+
+ bEndBlock = i >= CommonSettings.jit_max_block_size - 1 || instr_is_branch(opcode);
+
+#if LOG_JIT
+ if (instr_is_conditional(opcode) && cycles > 1 || !cycles)
+ has_variable_cycles = true;
+#endif
+ bb_cycles = c.newGpVar(kX86VarTypeGpz);
+
+ bb_constant_cycles += instr_is_conditional(opcode) ? 1 : cycles;
+
+ JIT_COMMENT("%s (PC:%08X)", disassemble(opcode), bb_adr);
+
+#if PROFILER_JIT_LEVEL > 0
+ JIT_COMMENT("*** profiler - counter");
+ if (bb_thumb)
+ c.add(profiler_counter_thumb(opcode), 1);
+ else
+ c.add(profiler_counter_arm(opcode), 1);
+#endif
+ if (instr_is_conditional(opcode))
+ {
+ // 25% of conditional instructions are immediately followed by
+ // another with the same condition, but merging them into a
+ // single branch has negligible effect on speed.
+ if (bEndBlock)
+ sync_r15(opcode, 1, 1);
+ Label skip = c.newLabel();
+ emit_branch(CONDITION(opcode), skip);
+ if (!bEndBlock)
+ sync_r15(opcode, 0, 0);
+ emit_armop_call(opcode);
+
+ if (!cycles)
+ {
+ JIT_COMMENT("variable cycles");
+ c.lea(bb_total_cycles, ptr(bb_total_cycles.r64(), bb_cycles.r64(), kScaleNone));
+ }
+ c.bind(skip);
+ }
+ else
+ {
+ sync_r15(opcode, !!bEndBlock, false);
+ emit_armop_call(opcode);
+ if (!cycles)
+ {
+ JIT_COMMENT("variable cycles");
+ c.lea(bb_total_cycles, ptr(bb_total_cycles.r64(), bb_cycles.r64(), kScaleNone));
+ }
+ }
+ interpreted_cycles += op_decode[PROCNUM][bb_thumb]();
+ }
+
+ if (!instr_does_prefetch(opcode))
+ {
+ JIT_COMMENT("!instr_does_prefetch: copy next_instruction (%08X) to instruct_adr (%08X)", cpu->next_instruction, cpu->instruct_adr);
+ GpVar x = c.newGpVar(kX86VarTypeGpd);
+ c.mov(x, cpu_ptr(next_instruction));
+ c.mov(cpu_ptr(instruct_adr), x);
+ c.unuse(x);
+ //c.mov(cpu_ptr(instruct_adr), bb_adr);
+ //c.mov(cpu_ptr(instruct_adr), bb_next_instruction);
+ }
+
+ JIT_COMMENT("total cycles (block)");
+
+ if (bb_constant_cycles > 0)
+ c.add(bb_total_cycles, bb_constant_cycles);
+
+#if PROFILER_JIT_LEVEL > 1
+ JIT_COMMENT("*** profiler - cycles");
+ uint32_t padr = (start_adr & 0x07FFFFFE) >> 1;
+ bb_profiler_entry = c.newGpVar(kX86VarTypeGpz);
+ c.mov(bb_profiler_entry, reinterpret_cast<uintptr_t>(&profiler_entry[PROCNUM][padr]));
+ c.add(dword_ptr(bb_profiler_entry, offsetof(PROFILER_ENTRY, cycles)), bb_total_cycles);
+ profiler_entry[PROCNUM][padr].addr = start_adr;
+#endif
+
+ c.ret(bb_total_cycles);
+#if LOG_JIT
+ fprintf(stderr, "cycles %d%s\n", bb_constant_cycles, has_variable_cycles ? " + variable" : "");
+#endif
+ c.endFunc();
+
+ ArmOpCompiled f = reinterpret_cast<ArmOpCompiled>(c.make());
+ if(c.getError())
+ {
+ fprintf(stderr, "JIT error: %s\n", getErrorString(c.getError()));
+ f = op_decode[PROCNUM][bb_thumb];
+ }
+#if LOG_JIT
+ uintptr_t baddr = reinterpret_cast<uintptr_t>(f);
+ fprintf(stderr, "Block address %08lX\n\n", baddr);
+ fflush(stderr);
+#endif
+
+ JIT_COMPILED_FUNC(start_adr, PROCNUM) = reinterpret_cast<uintptr_t>(f);
+ return interpreted_cycles;
+}
+
+template<int PROCNUM> uint32_t arm_jit_compile()
+{
+ *PROCNUM_ptr = PROCNUM;
+
+ // prevent endless recompilation of self-modifying code, which would be a memleak since we only free code all at once.
+ // also allows us to clear compiled_funcs[] while leaving it sparsely allocated, if the OS does memory overcommit.
+ uint32_t adr = cpu->instruct_adr;
+ uint32_t mask_adr = (adr & 0x07FFFFFE) >> 4;
+ if (((recompile_counts[mask_adr >> 1] >> 4 * (mask_adr & 1)) & 0xF) > 8)
+ {
+ ArmOpCompiled f = op_decode[PROCNUM][cpu->CPSR.bits.T];
+ JIT_COMPILED_FUNC(adr, PROCNUM) = reinterpret_cast<uintptr_t>(f);
+ return f();
+ }
+ recompile_counts[mask_adr >> 1] += 1 << 4 * (mask_adr & 1);
+
+ return compile_basicblock<PROCNUM>();
+}
+
+template uint32_t arm_jit_compile<0>();
+template uint32_t arm_jit_compile<1>();
+
+void arm_jit_reset(bool enable)
+{
+#if LOG_JIT
+ c.setLogger(&logger);
+#ifdef _WINDOWS
+ freopen("\\desmume_jit.log", "w", stderr);
+#endif
+#endif
+#ifdef HAVE_STATIC_CODE_BUFFER
+ scratchptr = scratchpad;
+#endif
+ printf("CPU mode: %s\n", enable ? "JIT" : "Interpreter");
+ printf("JIT max block size %d instruction(s)\n", CommonSettings.jit_max_block_size);
+
+ if (enable)
+ {
+#ifdef MAPPED_JIT_FUNCS
+ // these pointers are allocated by asmjit and need freeing
+ #define JITFREE(x) for (size_t iii = 0; iii < ARRAY_SIZE((x)); ++iii) if ((x)[iii]) AsmJit::MemoryManager::getGlobal()->free(reinterpret_cast<void *>((x)[iii])); memset((x), 0, sizeof((x)));
+ JITFREE(JIT.MAIN_MEM);
+ JITFREE(JIT.SWIRAM);
+ JITFREE(JIT.ARM9_ITCM);
+ JITFREE(JIT.ARM9_LCDC);
+ JITFREE(JIT.ARM9_BIOS);
+ JITFREE(JIT.ARM7_BIOS);
+ JITFREE(JIT.ARM7_ERAM);
+ JITFREE(JIT.ARM7_WIRAM);
+ JITFREE(JIT.ARM7_WRAM);
+ #undef JITFREE
+
+ memset(recompile_counts, 0, sizeof(recompile_counts));
+ init_jit_mem();
+#else
+ for (int i = 0; i < sizeof(recompile_counts) / 8; ++i)
+ if (reinterpret_cast<uint64_t *>(recompile_counts)[i])
+ {
+ reinterpret_cast<uint64_t *>(recompile_counts)[i] = nullptr;
+ memset(compiled_funcs + 128 * i, 0, 128 * sizeof(*compiled_funcs));
+ }
+#endif
+ }
+
+ c.clear();
+
+#if PROFILER_JIT_LEVEL > 0
+ reconstruct(&profiler_counter[0]);
+ reconstruct(&profiler_counter[1]);
+#if PROFILER_JIT_LEVEL > 1
+ for (uint8_t t = 0; t < 2; ++t)
+ {
+ for (uint32_t i = 0; i < (1 << 26); ++i)
+ memset(&profiler_entry[t][i], 0, sizeof(PROFILER_ENTRY));
+ }
+#endif
+#endif
+}
+
+#if PROFILER_JIT_LEVEL > 0
+static int pcmp(PROFILER_COUNTER_INFO *info1, PROFILER_COUNTER_INFO *info2)
+{
+ return static_cast<int>(info2->count - info1->count);
+}
+
+#if PROFILER_JIT_LEVEL > 1
+static int pcmp_entry(PROFILER_ENTRY *info1, PROFILER_ENTRY *info2)
+{
+ return static_cast<int>(info1->cycles - info2->cycles);
+}
+#endif
+#endif
+
+void arm_jit_close()
+{
+#if PROFILER_JIT_LEVEL > 0
+ printf("Generating profile report...");
+
+ for (uint8_t proc = 0; proc < 2; ++proc)
+ {
+ extern GameInfo gameInfo;
+ uint16_t last[2] = { 0 };
+
+ auto arm_info = std::unique_ptr<PROFILER_COUNTER_INFO[]>(new PROFILER_COUNTER_INFO[4096]);
+ auto thumb_info = std::unique_ptr<PROFILER_COUNTER_INFO[]>(new PROFILER_COUNTER_INFO[1024]);
+ memset(arm_info, 0, sizeof(PROFILER_COUNTER_INFO) * 4096);
+ memset(thumb_info, 0, sizeof(PROFILER_COUNTER_INFO) * 1024);
+
+ // ARM
+ last[0] = 0;
+ for (uint16_t i = 0; i < 4096; ++i)
+ {
+ uint16_t t = 0;
+ if (!profiler_counter[proc].arm_count[i])
+ continue;
+
+ for (t = 0; t < last[0]; ++t)
+ {
+ if (!strcmp(arm_instruction_names[i], arm_info[t].name))
+ {
+ arm_info[t].count += profiler_counter[proc].arm_count[i];
+ break;
+ }
+ }
+ if (t == last[0])
+ {
+ strcpy(arm_info[last[0]++].name, arm_instruction_names[i]);
+ arm_info[t].count = profiler_counter[proc].arm_count[i];
+ }
+ }
+
+ // THUMB
+ last[1] = 0;
+ for (uint16_t i = 0; i < 1024; ++i)
+ {
+ uint16_t t = 0;
+ if (!profiler_counter[proc].thumb_count[i])
+ continue;
+
+ for (t = 0; t < last[1]; ++t)
+ if (!strcmp(thumb_instruction_names[i], thumb_info[t].name))
+ {
+ thumb_info[t].count += profiler_counter[proc].thumb_count[i];
+ break;
+ }
+ if (t == last[1])
+ {
+ strcpy(thumb_info[last[1]++].name, thumb_instruction_names[i]);
+ thumb_info[t].count = profiler_counter[proc].thumb_count[i];
+ }
+ }
+
+ std::qsort(arm_info, last[0], sizeof(PROFILER_COUNTER_INFO), (int (*)(const void *, const void *))pcmp);
+ std::qsort(thumb_info, last[1], sizeof(PROFILER_COUNTER_INFO), (int (*)(const void *, const void *))pcmp);
+
+ char buf[MAX_PATH] = { 0 };
+ sprintf(buf, "\\desmume_jit%c_counter.profiler", !proc ? '9' : '7');
+ FILE *fp = fopen(buf, "w");
+ if (fp)
+ {
+ if (!gameInfo.isHomebrew)
+ {
+ fprintf(fp, "Name: %s\n", gameInfo.ROMname);
+ fprintf(fp, "Serial: %s\n", gameInfo.ROMserial);
+ }
+ else
+ fprintf(fp, "Homebrew\n");
+ fprintf(fp, "CPU: ARM%c\n\n", !proc ? '9' : '7');
+
+ if (last[0])
+ {
+ fprintf(fp, "========================================== ARM ==========================================\n");
+ for (int i = 0; i < last[0]; ++i)
+ fprintf(fp, "%30s: %20ld\n", arm_info[i].name, arm_info[i].count);
+ fprintf(fp, "\n");
+ }
+
+ if (last[1])
+ {
+ fprintf(fp, "========================================== THUMB ==========================================\n");
+ for (int i = 0; i < last[1]; ++i)
+ fprintf(fp, "%30s: %20ld\n", thumb_info[i].name, thumb_info[i].count);
+ fprintf(fp, "\n");
+ }
+
+ fclose(fp);
+ }
+
+#if PROFILER_JIT_LEVEL > 1
+ sprintf(buf, "\\desmume_jit%c_entry.profiler", !proc ? '9' : '7');
+ fp = fopen(buf, "w");
+ if (fp)
+ {
+ uint32_t count = 0;
+
+ fprintf(fp, "Entrypoints (cycles):\n");
+ auto tmp = std::unique_ptr<PROFILER_ENTRY[]>(new PROFILER_ENTRY[1 << 26]);
+ memset(tmp, 0, sizeof(PROFILER_ENTRY) * (1 << 26));
+ for (uint32_t i = 0; i < (1 << 26); ++i)
+ {
+ if (!profiler_entry[proc][i].cycles)
+ continue;
+ memcpy(&tmp[count++], &profiler_entry[proc][i], sizeof(PROFILER_ENTRY));
+ }
+ std::qsort(tmp, count, sizeof(PROFILER_ENTRY), (int (*)(const void *, const void *))pcmp_entry);
+ if (!gameInfo.isHomebrew)
+ {
+ fprintf(fp, "Name: %s\n", gameInfo.ROMname);
+ fprintf(fp, "Serial: %s\n", gameInfo.ROMserial);
+ }
+ else
+ fprintf(fp, "Homebrew\n");
+ fprintf(fp, "CPU: ARM%c\n\n", !proc ? '9' : '7');
+
+ while (count-- > 0)
+ fprintf(fp, "%08X: %20ld\n", tmp[count].addr, tmp[count].cycles);
+
+ fclose(fp);
+ }
+#endif
+ }
+ printf(" done.\n");
+#endif
+}
+#endif // HAVE_JIT
+
--- /dev/null
+++ b/src/in_2sf/desmume/arm_jit.h
@@ -1,1 +1,68 @@
+/* Copyright (C) 2006 yopyop
+ Copyright (C) 2011 Loren Merritt
+ Copyright (C) 2012 DeSmuME team
+ This file is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This file is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with the this software. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef ARM_JIT
+#define ARM_JIT
+
+#include "types.h"
+
+typedef uint32_t (FASTCALL *ArmOpCompiled)();
+
+void arm_jit_reset(bool enable);
+void arm_jit_close();
+void arm_jit_sync();
+template<int PROCNUM> uint32_t arm_jit_compile();
+
+#ifdef _WINDOWS
+# define MAPPED_JIT_FUNCS
+#endif
+
+#ifdef MAPPED_JIT_FUNCS
+struct JIT_struct
+{
+ // only include the memory types that code can execute from
+ uintptr_t MAIN_MEM[0x800000];
+ uintptr_t SWIRAM[0x4000];
+ uintptr_t ARM9_ITCM[0x4000];
+ uintptr_t ARM9_LCDC[0x52000];
+ uintptr_t ARM9_BIOS[0x4000];
+ uintptr_t ARM7_BIOS[0x2000];
+ uintptr_t ARM7_ERAM[0x8000];
+ uintptr_t ARM7_WIRAM[0x8000];
+ uintptr_t ARM7_WRAM[0x20000];
+
+ static uintptr_t *JIT_MEM[2][0x4000];
+};
+extern CACHE_ALIGN JIT_struct JIT;
+inline uintptr_t &JIT_COMPILED_FUNC(uint32_t adr, uint32_t PROCNUM) { return JIT.JIT_MEM[PROCNUM][(adr & 0x0FFFC000) >> 14][(adr & 0x00003FFE) >> 1]; }
+inline uintptr_t &JIT_COMPILED_FUNC_PREMASKED(uint32_t adr, uint32_t PROCNUM, uint32_t ofs) { return JIT.JIT_MEM[PROCNUM][adr >> 14][((adr & 0x00003FFE) >> 1) + ofs]; }
+#define JIT_COMPILED_FUNC_KNOWNBANK(adr, bank, mask, ofs) JIT.bank[(((adr) & (mask)) >> 1) + ofs]
+inline bool JIT_MAPPED(uint32_t adr, uint32_t PROCNUM) { return !!JIT.JIT_MEM[PROCNUM][adr >> 14]; }
+#else
+// actually an array of function pointers, but they fit in 32bit address space, so might as well save memory
+extern uintptr_t compiled_funcs[];
+// there isn't anything mapped between 07000000 and 0EFFFFFF, so we can mask off bit 27 and get away with a smaller array
+inline uintptr_r &JIT_COMPILED_FUNC(uint32_t adr, uint32_t PROCNUM) { compiled_funcs[(adr & 0x07FFFFFE) >> 1]; }
+inline uintptr_t &JIT_COMPILED_FUNC_PREMASKED(uint32_t adr, uint32_t PROCNUM, uint32_t ofs) { return JIT_COMPILED_FUNC(adr, PROCNUM); }
+#define JIT_COMPILED_FUNC_KNOWNBANK(adr, bank, mask, ofs) JIT_COMPILED_FUNC(adr, PROCNUM)
+inline bool JIT_MAPPED(uint32_t adr, uint32_t PROCNUM) { return true; }
+#endif
+
+
+#endif
+
--- a/src/in_2sf/desmume/armcpu.cpp
+++ b/src/in_2sf/desmume/armcpu.cpp
@@ -16,196 +16,40 @@
along with the this software. If not, see <http://www.gnu.org/licenses/>.
*/
+#include <algorithm>
#include <cstdlib>
#include <cstdio>
#include <cassert>
-#include <algorithm>
-
#include "types.h"
-#include "arm_instructions.h"
-#include "thumb_instructions.h"
+#include "instructions.h"
#include "cp15.h"
#include "bios.h"
-//#include "debug.h"
-//#include "Disassembler.h"
#include "NDSSystem.h"
#include "MMU_timing.h"
#ifdef HAVE_LUA
#include "lua-engine.h"
#endif
+#ifdef HAVE_JIT
+#include "arm_jit.h"
+#endif
template<uint32_t> static uint32_t armcpu_prefetch();
-inline uint32_t armcpu_prefetch(armcpu_t *armcpu) {
- if(armcpu->proc_ID==0) return armcpu_prefetch<0>();
- else return armcpu_prefetch<1>();
-}
-
-const unsigned char arm_cond_table[16*16] = {
- /* N=0, Z=0, C=0, V=0 */
- 0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,
- 0x00,0xFF,0xFF,0x00,0xFF,0x00,0xFF,0x20,
- /* N=0, Z=0, C=0, V=1 */
- 0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x00,
- 0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x20,
- /* N=0, Z=0, C=1, V=0 */
- 0x00,0xFF,0xFF,0x00,0x00,0xFF,0x00,0xFF,
- 0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x20,
- /* N=0, Z=0, C=1, V=1 */
- 0x00,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x00,
- 0xFF,0x00,0x00,0xFF,0x00,0xFF,0xFF,0x20,
- /* N=0, Z=1, C=0, V=0 */
- 0xFF,0x00,0x00,0xFF,0x00,0xFF,0x00,0xFF,
- 0x00,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x20,
- /* N=0, Z=1, C=0, V=1 */
- 0xFF,0x00,0x00,0xFF,0x00,0xFF,0xFF,0x00,
- 0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x20,
- /* N=0, Z=1, C=1, V=0 */
- 0xFF,0x00,0xFF,0x00,0x00,0xFF,0x00,0xFF,
- 0x00,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x20,
- /* N=0, Z=1, C=1, V=1 */
- 0xFF,0x00,0xFF,0x00,0x00,0xFF,0xFF,0x00,
- 0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x20,
- /* N=1, Z=0, C=0, V=0 */
- 0x00,0xFF,0x00,0xFF,0xFF,0x00,0x00,0xFF,
- 0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x20,
- /* N=1, Z=0, C=0, V=1 */
- 0x00,0xFF,0x00,0xFF,0xFF,0x00,0xFF,0x00,
- 0x00,0xFF,0xFF,0x00,0xFF,0x00,0xFF,0x20,
- /* N=1, Z=0, C=1, V=0 */
- 0x00,0xFF,0xFF,0x00,0xFF,0x00,0x00,0xFF,
- 0xFF,0x00,0x00,0xFF,0x00,0xFF,0xFF,0x20,
- /* N=1, Z=0, C=1, V=1 */
- 0x00,0xFF,0xFF,0x00,0xFF,0x00,0xFF,0x00,
- 0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x20,
- /* N=1, Z=1, C=0, V=0 */
- 0xFF,0x00,0x00,0xFF,0xFF,0x00,0x00,0xFF,
- 0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x20,
- /* N=1, Z=1, C=0, V=1 */
- 0xFF,0x00,0x00,0xFF,0xFF,0x00,0xFF,0x00,
- 0x00,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x20,
- /* N=1, Z=1, C=1, V=0 */
- 0xFF,0x00,0xFF,0x00,0xFF,0x00,0x00,0xFF,
- 0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x20,
- /* N=1, Z=1, C=1, V=1 */
- 0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,
- 0x00,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x20,
-};
+static inline uint32_t armcpu_prefetch(armcpu_t *armcpu)
+{
+ if (!armcpu->proc_ID)
+ return armcpu_prefetch<0>();
+ else
+ return armcpu_prefetch<1>();
+}
armcpu_t NDS_ARM7;
armcpu_t NDS_ARM9;
-/*#define SWAP(a, b, c) do \
- { \
- c=a; \
- a=b; \
- b=c; \
- } \
- while(0)*/
-template<typename T> static inline void SWAP(T &a, T &b)
-{
- T c = a;
- a = b;
- b = c;
-}
-
-#ifdef GDB_STUB
-
-#define STALLED_CYCLE_COUNT 10
-
-static void
-stall_cpu( void *instance) {
- armcpu_t *armcpu = (armcpu_t *)instance;
- printf("UNSTALL\n");
- armcpu->stalled = 1;
-}
-
-static void
-unstall_cpu( void *instance) {
- armcpu_t *armcpu = (armcpu_t *)instance;
- printf("UNSTALL\n");
- armcpu->stalled = 0;
-}
-
-static void
-install_post_exec_fn( void *instance,
- void (*ex_fn)( void *, uint32_t adr, int thumb),
- void *fn_data) {
- armcpu_t *armcpu = (armcpu_t *)instance;
-
-
- armcpu->post_ex_fn = ex_fn;
- armcpu->post_ex_fn_data = fn_data;
-}
-
-static void
-remove_post_exec_fn( void *instance) {
- armcpu_t *armcpu = (armcpu_t *)instance;
-
- armcpu->post_ex_fn = NULL;
-}
-#endif
-
-#ifdef GDB_STUB
-static uint32_t read_cpu_reg( void *instance, uint32_t reg_num)
-{
- armcpu_t *armcpu = (armcpu_t *)instance;
-
- if ( reg_num <= 14) {
- return armcpu->R[reg_num];
- }
- else if ( reg_num == 15) {
- return armcpu->instruct_adr;
- }
- else if ( reg_num == 16) {
- //CPSR
- return armcpu->CPSR.val;
- }
-}
-
-static void
-set_cpu_reg( void *instance, uint32_t reg_num, uint32_t value) {
- armcpu_t *armcpu = (armcpu_t *)instance;
-
- if ( reg_num <= 14) {
- armcpu->R[reg_num] = value;
- }
- else if ( reg_num == 15) {
- armcpu->next_instruction = value;
- }
- else if ( reg_num == 16) {
- /* FIXME: setting the CPSR */
- }
-}
-#endif
-
-#ifdef GDB_STUB
-int armcpu_new( armcpu_t *armcpu, uint32_t id,
- struct armcpu_memory_iface *mem_if,
- struct armcpu_ctrl_iface **ctrl_iface_ret)
-#else
-int armcpu_new( armcpu_t *armcpu, uint32_t id)
-#endif
+int armcpu_new(armcpu_t *armcpu, uint32_t id)
{
armcpu->proc_ID = id;
-#ifdef GDB_STUB
- armcpu->mem_if = mem_if;
-
- /* populate the control interface */
- armcpu->ctrl_iface.stall = stall_cpu;
- armcpu->ctrl_iface.unstall = unstall_cpu;
- armcpu->ctrl_iface.read_reg = read_cpu_reg;
- armcpu->ctrl_iface.set_reg = set_cpu_reg;
- armcpu->ctrl_iface.install_post_ex_fn = install_post_exec_fn;
- armcpu->ctrl_iface.remove_post_ex_fn = remove_post_exec_fn;
- armcpu->ctrl_iface.data = armcpu;
-
- *ctrl_iface_ret = &armcpu->ctrl_iface;
-
- armcpu->post_ex_fn = NULL;
-#endif
-
armcpu->stalled = 0;
armcpu_init(armcpu, 0);
@@ -213,33 +57,29 @@
return 0;
}
-//call this whenever CPSR is changed (other than CNVZQ or T flags); interrupts may need to be unleashed
+// call this whenever CPSR is changed (other than CNVZQ or T flags); interrupts may need to be unleashed
void armcpu_t::changeCPSR()
{
- //but all it does is give them a chance to unleash by forcing an immediate reschedule
- //TODO - we could actually set CPSR through here and look for a change in the I bit
- //that would be a little optimization as well as a safety measure if we prevented setting CPSR directly
+ // but all it does is give them a chance to unleash by forcing an immediate reschedule
+ // TODO - we could actually set CPSR through here and look for a change in the I bit
+ // that would be a little optimization as well as a safety measure if we prevented setting CPSR directly
NDS_Reschedule();
}
void armcpu_init(armcpu_t *armcpu, uint32_t adr)
{
- armcpu->LDTBit = (armcpu->proc_ID==0); //Si ARM9 utiliser le syte v5 pour le load
- armcpu->intVector = 0xFFFF0000 * (armcpu->proc_ID==0);
+#if defined(_M_X64) || defined(__x86_64__)
+ memcpy(&armcpu->cond_table[0], &arm_cond_table[0], sizeof(arm_cond_table));
+#endif
+
+ armcpu->LDTBit = !armcpu->proc_ID; // Si ARM9 utiliser le syte v5 pour le load
+ armcpu->intVector = 0xFFFF0000 * !armcpu->proc_ID;
armcpu->waitIRQ = false;
armcpu->halt_IE_and_IF = false;
armcpu->intrWaitARM_state = 0;
-//#ifdef GDB_STUB
-// armcpu->irq_flag = 0;
-//#endif
-
- for(int i = 0; i < 16; ++i)
- {
+ for (int i = 0; i < 16; ++i)
armcpu->R[i] = 0;
- if(armcpu->coproc[i]) free(armcpu->coproc[i]);
- armcpu->coproc[i] = NULL;
- }
armcpu->CPSR.val = armcpu->SPSR.val = SYS;
@@ -252,125 +92,96 @@
armcpu->SPSR_svc.val = armcpu->SPSR_abt.val = armcpu->SPSR_und.val = armcpu->SPSR_irq.val = armcpu->SPSR_fiq.val = 0;
-//#ifdef GDB_STUB
-// armcpu->instruct_adr = adr;
-// armcpu->R[15] = adr + 8;
-//#else
- //armcpu->R[15] = adr;
-//#endif
-
armcpu->next_instruction = adr;
- // only ARM9 have co-processor
- if (armcpu->proc_ID==0)
- armcpu->coproc[15] = (armcp_t*)armcp15_new(armcpu);
-
-//#ifndef GDB_STUB
armcpu_prefetch(armcpu);
-//#endif
}
uint32_t armcpu_switchMode(armcpu_t *armcpu, uint8_t mode)
{
uint32_t oldmode = armcpu->CPSR.bits.mode;
- switch(oldmode)
- {
- case USR :
- case SYS :
+ switch (oldmode)
+ {
+ case USR:
+ case SYS:
armcpu->R13_usr = armcpu->R[13];
armcpu->R14_usr = armcpu->R[14];
break;
-
- case FIQ :
- {
- //uint32_t tmp;
- SWAP(armcpu->R[8], armcpu->R8_fiq/*, tmp*/);
- SWAP(armcpu->R[9], armcpu->R9_fiq/*, tmp*/);
- SWAP(armcpu->R[10], armcpu->R10_fiq/*, tmp*/);
- SWAP(armcpu->R[11], armcpu->R11_fiq/*, tmp*/);
- SWAP(armcpu->R[12], armcpu->R12_fiq/*, tmp*/);
- armcpu->R13_fiq = armcpu->R[13];
- armcpu->R14_fiq = armcpu->R[14];
- armcpu->SPSR_fiq = armcpu->SPSR;
- break;
- }
- case IRQ :
+ case FIQ:
+ std::swap(armcpu->R[8], armcpu->R8_fiq);
+ std::swap(armcpu->R[9], armcpu->R9_fiq);
+ std::swap(armcpu->R[10], armcpu->R10_fiq);
+ std::swap(armcpu->R[11], armcpu->R11_fiq);
+ std::swap(armcpu->R[12], armcpu->R12_fiq);
+ armcpu->R13_fiq = armcpu->R[13];
+ armcpu->R14_fiq = armcpu->R[14];
+ armcpu->SPSR_fiq = armcpu->SPSR;
+ break;
+ case IRQ:
armcpu->R13_irq = armcpu->R[13];
armcpu->R14_irq = armcpu->R[14];
armcpu->SPSR_irq = armcpu->SPSR;
break;
-
- case SVC :
+ case SVC:
armcpu->R13_svc = armcpu->R[13];
armcpu->R14_svc = armcpu->R[14];
armcpu->SPSR_svc = armcpu->SPSR;
break;
-
- case ABT :
+ case ABT:
armcpu->R13_abt = armcpu->R[13];
armcpu->R14_abt = armcpu->R[14];
armcpu->SPSR_abt = armcpu->SPSR;
break;
-
- case UND :
+ case UND:
armcpu->R13_und = armcpu->R[13];
armcpu->R14_und = armcpu->R[14];
armcpu->SPSR_und = armcpu->SPSR;
break;
- default :
- break;
- }
-
- switch(mode)
- {
- case USR :
- case SYS :
- armcpu->R[13] = armcpu->R13_usr;
- armcpu->R[14] = armcpu->R14_usr;
- //SPSR = CPSR;
- break;
-
- case FIQ :
- {
- //uint32_t tmp;
- SWAP(armcpu->R[8], armcpu->R8_fiq/*, tmp*/);
- SWAP(armcpu->R[9], armcpu->R9_fiq/*, tmp*/);
- SWAP(armcpu->R[10], armcpu->R10_fiq/*, tmp*/);
- SWAP(armcpu->R[11], armcpu->R11_fiq/*, tmp*/);
- SWAP(armcpu->R[12], armcpu->R12_fiq/*, tmp*/);
- armcpu->R[13] = armcpu->R13_fiq;
- armcpu->R[14] = armcpu->R14_fiq;
- armcpu->SPSR = armcpu->SPSR_fiq;
- break;
- }
-
- case IRQ :
- armcpu->R[13] = armcpu->R13_irq;
- armcpu->R[14] = armcpu->R14_irq;
- armcpu->SPSR = armcpu->SPSR_irq;
- break;
-
- case SVC :
- armcpu->R[13] = armcpu->R13_svc;
- armcpu->R[14] = armcpu->R14_svc;
- armcpu->SPSR = armcpu->SPSR_svc;
- break;
-
- case ABT :
- armcpu->R[13] = armcpu->R13_abt;
- armcpu->R[14] = armcpu->R14_abt;
- armcpu->SPSR = armcpu->SPSR_abt;
- break;
-
- case UND :
- armcpu->R[13] = armcpu->R13_und;
- armcpu->R[14] = armcpu->R14_und;
- armcpu->SPSR = armcpu->SPSR_und;
- break;
-
- default :
- break;
+ default:
+ printf("switchMode: WRONG mode %02X\n",mode);
+ }
+
+ switch (mode)
+ {
+ case USR:
+ case SYS:
+ armcpu->R[13] = armcpu->R13_usr;
+ armcpu->R[14] = armcpu->R14_usr;
+ //SPSR = CPSR;
+ break;
+ case FIQ:
+ std::swap(armcpu->R[8], armcpu->R8_fiq);
+ std::swap(armcpu->R[9], armcpu->R9_fiq);
+ std::swap(armcpu->R[10], armcpu->R10_fiq);
+ std::swap(armcpu->R[11], armcpu->R11_fiq);
+ std::swap(armcpu->R[12], armcpu->R12_fiq);
+ armcpu->R[13] = armcpu->R13_fiq;
+ armcpu->R[14] = armcpu->R14_fiq;
+ armcpu->SPSR = armcpu->SPSR_fiq;
+ break;
+ case IRQ:
+ armcpu->R[13] = armcpu->R13_irq;
+ armcpu->R[14] = armcpu->R14_irq;
+ armcpu->SPSR = armcpu->SPSR_irq;
+ break;
+ case SVC:
+ armcpu->R[13] = armcpu->R13_svc;
+ armcpu->R[14] = armcpu->R14_svc;
+ armcpu->SPSR = armcpu->SPSR_svc;
+ break;
+ case ABT:
+ armcpu->R[13] = armcpu->R13_abt;
+ armcpu->R[14] = armcpu->R14_abt;
+ armcpu->SPSR = armcpu->SPSR_abt;
+ break;
+ case UND:
+ armcpu->R[13] = armcpu->R13_und;
+ armcpu->R[14] = armcpu->R14_und;
+ armcpu->SPSR = armcpu->SPSR_und;
+ break;
+ default:
+ break;
}
armcpu->CPSR.bits.mode = mode & 0x1F;
@@ -385,217 +196,127 @@
return 1;
}
-template<uint32_t PROCNUM>
-inline static uint32_t armcpu_prefetch()
-{
- armcpu_t* const armcpu = &ARMPROC;
-//#ifdef GDB_STUB
-// uint32_t temp_instruction;
-//#endif
+template<uint32_t PROCNUM> static inline uint32_t armcpu_prefetch()
+{
+ armcpu_t *const armcpu = &ARMPROC;
uint32_t curInstruction = armcpu->next_instruction;
- if(armcpu->CPSR.bits.T == 0)
- {
-//#ifdef GDB_STUB
-// temp_instruction =
-// armcpu->mem_if->prefetch32( armcpu->mem_if->data,
-// armcpu->next_instruction);
-//
-// if ( !armcpu->stalled) {
-// armcpu->instruction = temp_instruction;
-// armcpu->instruct_adr = armcpu->next_instruction;
-// armcpu->next_instruction += 4;
-// armcpu->R[15] = armcpu->next_instruction + 4;
-// }
-//#else
- curInstruction &= 0xFFFFFFFC; //please don't change this to 0x0FFFFFFC -- the NDS will happily run on 0xF******* addresses all day long
- //please note that we must setup R[15] before reading the instruction since there is a protection
- //which prevents PC > 0x3FFF from reading the bios region
+ if (!armcpu->CPSR.bits.T)
+ {
+ curInstruction &= 0xFFFFFFFC; // please don't change this to 0x0FFFFFFC -- the NDS will happily run on 0xF******* addresses all day long
+ // please note that we must setup R[15] before reading the instruction since there is a protection
+ // which prevents PC > 0x3FFF from reading the bios region
armcpu->instruct_adr = curInstruction;
armcpu->next_instruction = curInstruction + 4;
armcpu->R[15] = curInstruction + 8;
armcpu->instruction = _MMU_read32<PROCNUM, MMU_AT_CODE>(curInstruction);
-//#endif
-
- return MMU_codeFetchCycles<PROCNUM,32>(curInstruction);
- }
-
-//#ifdef GDB_STUB
-// temp_instruction =
-// armcpu->mem_if->prefetch16( armcpu->mem_if->data,
-// armcpu->next_instruction);
-//
-// if ( !armcpu->stalled) {
-// armcpu->instruction = temp_instruction;
-// armcpu->instruct_adr = armcpu->next_instruction;
-// armcpu->next_instruction = armcpu->next_instruction + 2;
-// armcpu->R[15] = armcpu->next_instruction + 2;
-// }
-//#else
- curInstruction &= 0xFFFFFFFE; //please don't change this to 0x0FFFFFFE -- the NDS will happily run on 0xF******* addresses all day long
- //please note that we must setup R[15] before reading the instruction since there is a protection
- //which prevents PC > 0x3FFF from reading the bios region
+
+ return MMU_codeFetchCycles<PROCNUM, 32>(curInstruction);
+ }
+ curInstruction &= 0xFFFFFFFE; // please don't change this to 0x0FFFFFFE -- the NDS will happily run on 0xF******* addresses all day long
+ // please note that we must setup R[15] before reading the instruction since there is a protection
+ // which prevents PC > 0x3FFF from reading the bios region
armcpu->instruct_adr = curInstruction;
armcpu->next_instruction = curInstruction + 2;
armcpu->R[15] = curInstruction + 4;
armcpu->instruction = _MMU_read16<PROCNUM, MMU_AT_CODE>(curInstruction);
-//#endif
-
- if(PROCNUM==0)
+
+ if (!PROCNUM)
{
// arm9 fetches 2 instructions at a time in thumb mode
- if(!(curInstruction == armcpu->instruct_adr + 2 && (curInstruction & 2)))
- return MMU_codeFetchCycles<PROCNUM,32>(curInstruction);
+ if (!(curInstruction == armcpu->instruct_adr + 2 && (curInstruction & 2)))
+ return MMU_codeFetchCycles<PROCNUM, 32>(curInstruction);
else
return 0;
}
- return MMU_codeFetchCycles<PROCNUM,16>(curInstruction);
-}
-
-#if 0 /* not used */
-static bool FASTCALL test_EQ(Status_Reg CPSR) { return CPSR.bits.Z; }
-static bool FASTCALL test_NE(Status_Reg CPSR) { return !CPSR.bits.Z; }
-static bool FASTCALL test_CS(Status_Reg CPSR) { return CPSR.bits.C; }
-static bool FASTCALL test_CC(Status_Reg CPSR) { return !CPSR.bits.C; }
-static bool FASTCALL test_MI(Status_Reg CPSR) { return CPSR.bits.N; }
-static bool FASTCALL test_PL(Status_Reg CPSR) { return !CPSR.bits.N; }
-static bool FASTCALL test_VS(Status_Reg CPSR) { return CPSR.bits.V; }
-static bool FASTCALL test_VC(Status_Reg CPSR) { return !CPSR.bits.V; }
-static bool FASTCALL test_HI(Status_Reg CPSR) { return CPSR.bits.C && !CPSR.bits.Z; }
-static bool FASTCALL test_LS(Status_Reg CPSR) { return CPSR.bits.Z || !CPSR.bits.C; }
-static bool FASTCALL test_GE(Status_Reg CPSR) { return CPSR.bits.N==CPSR.bits.V; }
-static bool FASTCALL test_LT(Status_Reg CPSR) { return CPSR.bits.N!=CPSR.bits.V; }
-static bool FASTCALL test_GT(Status_Reg CPSR) { return !CPSR.bits.Z && CPSR.bits.N==CPSR.bits.V; }
-static bool FASTCALL test_LE(Status_Reg CPSR) { return CPSR.bits.Z || CPSR.bits.N!=CPSR.bits.V; }
-static bool FASTCALL test_AL(Status_Reg CPSR) { return 1; }
-
-static bool (FASTCALL* test_conditions[])(Status_Reg CPSR)= {
- test_EQ , test_NE ,
- test_CS , test_CC ,
- test_MI , test_PL ,
- test_VS , test_VC ,
- test_HI , test_LS ,
- test_GE , test_LT ,
- test_GT , test_LE ,
- test_AL
-};
-#define TEST_COND2(cond, CPSR) \
- (cond<15&&test_conditions[cond](CPSR))
-#endif
-
-//TODO - merge with armcpu_irqException?
-//http://www.ethernut.de/en/documents/arm-exceptions.html
-//http://docs.google.com/viewer?a=v&q=cache:V4ht1YkxprMJ:www.cs.nctu.edu.tw/~wjtsai/EmbeddedSystemDesign/Ch3-1.pdf+arm+exception+handling&hl=en&gl=us&pid=bl&srcid=ADGEEShx9VTHbUhWdDOrTVRzLkcCsVfJiijncNDkkgkrlJkLa7D0LCpO8fQ_hhU3DTcgZh9rcZWWQq4TYhhCovJ625h41M0ZUX3WGasyzWQFxYzDCB-VS6bsUmpoJnRxAc-bdkD0qmsu&sig=AHIEtbR9VHvDOCRmZFQDUVwy53iJDjoSPQ
+ return MMU_codeFetchCycles<PROCNUM, 16>(curInstruction);
+}
+
+// TODO - merge with armcpu_irqException?
+// http://www.ethernut.de/en/documents/arm-exceptions.html
+// http://docs.google.com/viewer?a=v&q=cache:V4ht1YkxprMJ:www.cs.nctu.edu.tw/~wjtsai/EmbeddedSystemDesign/Ch3-1.pdf+arm+exception+handling&hl=en&gl=us&pid=bl&srcid=ADGEEShx9VTHbUhWdDOrTVRzLkcCsVfJiijncNDkkgkrlJkLa7D0LCpO8fQ_hhU3DTcgZh9rcZWWQq4TYhhCovJ625h41M0ZUX3WGasyzWQFxYzDCB-VS6bsUmpoJnRxAc-bdkD0qmsu&sig=AHIEtbR9VHvDOCRmZFQDUVwy53iJDjoSPQ
void armcpu_exception(armcpu_t *cpu, uint32_t number)
{
Mode cpumode = USR;
- switch(number)
- {
- case EXCEPTION_RESET: cpumode = SVC; break;
- case EXCEPTION_UNDEFINED_INSTRUCTION: cpumode = UND; break;
- case EXCEPTION_SWI: cpumode = SVC; break;
- case EXCEPTION_PREFETCH_ABORT: cpumode = ABT; break;
- case EXCEPTION_DATA_ABORT: cpumode = ABT; break;
- case EXCEPTION_RESERVED_0x14: execute = false;/*emu_halt();*/ break;
- case EXCEPTION_IRQ: cpumode = IRQ; break;
- case EXCEPTION_FAST_IRQ: cpumode = FIQ; break;
+ switch (number)
+ {
+ case EXCEPTION_RESET:
+ cpumode = SVC;
+ break;
+ case EXCEPTION_UNDEFINED_INSTRUCTION:
+ cpumode = UND;
+ break;
+ case EXCEPTION_SWI:
+ cpumode = SVC;
+ break;
+ case EXCEPTION_PREFETCH_ABORT:
+ cpumode = ABT;
+ break;
+ case EXCEPTION_DATA_ABORT:
+ cpumode = ABT;
+ break;
+ case EXCEPTION_RESERVED_0x14:
+ execute = false;
+ break;
+ case EXCEPTION_IRQ:
+ cpumode = IRQ;
+ break;
+ case EXCEPTION_FAST_IRQ:
+ cpumode = FIQ;
}
Status_Reg tmp = cpu->CPSR;
- armcpu_switchMode(cpu, cpumode); //enter new mode
+ armcpu_switchMode(cpu, cpumode); // enter new mode
cpu->R[14] = cpu->next_instruction;
- cpu->SPSR = tmp; //save old CPSR as new SPSR
- cpu->CPSR.bits.T = 0; //handle as ARM32 code
+ cpu->SPSR = tmp; // save old CPSR as new SPSR
+ cpu->CPSR.bits.T = 0; // handle as ARM32 code
cpu->CPSR.bits.I = 1;
cpu->changeCPSR();
cpu->R[15] = cpu->intVector + number;
cpu->next_instruction = cpu->R[15];
printf("armcpu_exception!\n");
- //extern bool dolog;
- //dolog=true;
-
- //HOW DOES THIS WORTK WITHOUT A PREFETCH, LIKE IRQ BELOW?
- //I REALLY WISH WE DIDNT PREFETCH BEFORE EXECUTING
+
+ // HOW DOES THIS WORTK WITHOUT A PREFETCH, LIKE IRQ BELOW?
+ // I REALLY WISH WE DIDNT PREFETCH BEFORE EXECUTING
}
bool armcpu_irqException(armcpu_t *armcpu)
{
- Status_Reg tmp;
-
- //TODO - remove GDB specific code
-//#ifdef GDB_STUB
-// armcpu->irq_flag = 0;
-//#endif
+ Status_Reg tmp;
tmp = armcpu->CPSR;
armcpu_switchMode(armcpu, IRQ);
- //TODO - remove GDB specific code
-//#ifdef GDB_STUB
-// armcpu->R[14] = armcpu->next_instruction + 4;
-//#else
armcpu->R[14] = armcpu->instruct_adr + 4;
-//#endif
armcpu->SPSR = tmp;
armcpu->CPSR.bits.T = 0;
armcpu->CPSR.bits.I = 1;
armcpu->next_instruction = armcpu->intVector + 0x18;
armcpu->waitIRQ = 0;
- //must retain invariant of having next instruction to be executed prefetched
- //(yucky)
+ // must retain invariant of having next instruction to be executed prefetched
+ // (yucky)
armcpu_prefetch(armcpu);
return true;
}
-//TODO - remove GDB specific code
-//bool
-//armcpu_flagIrq( armcpu_t *armcpu) {
-// if(armcpu->CPSR.bits.I) return false;
-//
-// armcpu->waitIRQ = 0;
-//
-//#ifdef GDB_STUB
-// armcpu->irq_flag = 1;
-//#endif
-//
-// return true;
-//}
-
-uint32_t TRAPUNDEF(armcpu_t* cpu)
-{
- //INFO("ARM%c: Undefined instruction: 0x%08X (%s) PC=0x%08X\n", cpu->proc_ID?'7':'9', cpu->instruction, decodeIntruction(false, cpu->instruction), cpu->instruct_adr);
-
- if (((cpu->intVector != 0) ^ (cpu->proc_ID == ARMCPU_ARM9)))
- {
- armcpu_exception(&NDS_ARM9,EXCEPTION_UNDEFINED_INSTRUCTION);
+uint32_t TRAPUNDEF(armcpu_t *cpu)
+{
+ if (!!cpu->intVector ^ (cpu->proc_ID == ARMCPU_ARM9))
+ {
+ armcpu_exception(&NDS_ARM9, EXCEPTION_UNDEFINED_INSTRUCTION);
return 4;
}
else
{
- //emu_halt();
execute = false;
return 4;
}
}
-//bool
-//armcpu_flagIrq( armcpu_t *armcpu) {
-// if(armcpu->CPSR.bits.I) return false;
-//
-// armcpu->waitIRQ = 0;
-//
-//#ifdef GDB_STUB
-// armcpu->irq_flag = 1;
-//#endif
-//
-// return true;
-//}
-
-template<int PROCNUM>
-uint32_t armcpu_exec()
+template<int PROCNUM> uint32_t armcpu_exec()
{
// Usually, fetching and executing are processed parallelly.
// So this function stores the cycles of each process to
@@ -603,100 +324,27 @@
uint32_t cFetch = 0;
uint32_t cExecute = 0;
- //this assert is annoying. but sometimes it is handy.
+ // this assert is annoying. but sometimes it is handy.
//assert(ARMPROC.instruct_adr!=0x00000000);
-//#ifdef DEVELOPER
-#if 0
- if ((((ARMPROC.instruct_adr & 0x0F000000) == 0x0F000000) && (PROCNUM == 0)) ||
- (((ARMPROC.instruct_adr & 0x0F000000) == 0x00000000) && (PROCNUM == 1)))
- {
- switch (ARMPROC.instruct_adr & 0xFFFF)
- {
- case 0x00000000:
- printf("BIOS%c: Reset!!!\n", PROCNUM?'7':'9');
- emu_halt();
- break;
- case 0x00000004:
- printf("BIOS%c: Undefined instruction\n", PROCNUM?'7':'9');
- //emu_halt();
- break;
- case 0x00000008:
- //printf("BIOS%c: SWI\n", PROCNUM?'7':'9');
- break;
- case 0x0000000C:
- printf("BIOS%c: Prefetch Abort!!!\n", PROCNUM?'7':'9');
- //emu_halt();
- break;
- case 0x00000010:
- //printf("BIOS%c: Data Abort!!!\n", PROCNUM?'7':'9');
- //emu_halt();
- break;
- case 0x00000014:
- printf("BIOS%c: Reserved!!!\n", PROCNUM?'7':'9');
- break;
- case 0x00000018:
- //printf("BIOS%c: IRQ\n", PROCNUM?'7':'9');
- break;
- case 0x0000001C:
- printf("BIOS%c: Fast IRQ\n", PROCNUM?'7':'9');
- break;
- }
- }
-#endif
-
-#if 0 //#ifdef GDB_STUB
- if (ARMPROC.stalled) {
- return STALLED_CYCLE_COUNT;
- }
-
- /* check for interrupts */
- if (ARMPROC.irq_flag) {
- armcpu_irqException(&ARMPROC);
- }
-
- cFetch = armcpu_prefetch(&ARMPROC);
-
- if (ARMPROC.stalled) {
- return MMU_fetchExecuteCycles<PROCNUM>(cExecute, cFetch);
- }
-#endif
//cFetch = armcpu_prefetch(&ARMPROC);
//printf("%d: %08X\n",PROCNUM,ARMPROC.instruct_adr);
- if(ARMPROC.CPSR.bits.T == 0)
- {
- if(
- CONDITION(ARMPROC.instruction) == 0x0E //fast path for unconditional instructions
- || (TEST_COND(CONDITION(ARMPROC.instruction), CODE(ARMPROC.instruction), ARMPROC.CPSR)) //handles any condition
- )
+ if (!ARMPROC.CPSR.bits.T)
+ {
+ if (
+ CONDITION(ARMPROC.instruction) == 0x0E // fast path for unconditional instructions
+ || (TEST_COND(CONDITION(ARMPROC.instruction), CODE(ARMPROC.instruction), ARMPROC.CPSR)) // handles any condition
+ )
{
#ifdef HAVE_LUA
CallRegisteredLuaMemHook(ARMPROC.instruct_adr, 4, ARMPROC.instruction, LUAMEMHOOK_EXEC); // should report even if condition=false?
#endif
- if(PROCNUM==0) {
- #ifdef DEVELOPER
- DEBUG_statistics.instructionHits[0].arm[INSTRUCTION_INDEX(ARMPROC.instruction)]++;
- #endif
- cExecute = arm_instructions_set_0[INSTRUCTION_INDEX(ARMPROC.instruction)](ARMPROC.instruction);
- }
- else {
- #ifdef DEVELOPER
- DEBUG_statistics.instructionHits[1].arm[INSTRUCTION_INDEX(ARMPROC.instruction)]++;
- #endif
- cExecute = arm_instructions_set_1[INSTRUCTION_INDEX(ARMPROC.instruction)](ARMPROC.instruction);
- }
+ cExecute = arm_instructions_set[PROCNUM][INSTRUCTION_INDEX(ARMPROC.instruction)](ARMPROC.instruction);
}
else
cExecute = 1; // If condition=false: 1S cycle
-#ifdef GDB_STUB
- if ( ARMPROC.post_ex_fn != NULL) {
- /* call the external post execute function */
- ARMPROC.post_ex_fn(ARMPROC.post_ex_fn_data, ARMPROC.instruct_adr, 0);
- }
- ARMPROC.mem_if->prefetch32( ARMPROC.mem_if->data, ARMPROC.next_instruction);
-#endif
cFetch = armcpu_prefetch<PROCNUM>();
return MMU_fetchExecuteCycles<PROCNUM>(cExecute, cFetch);
}
@@ -704,32 +352,39 @@
#ifdef HAVE_LUA
CallRegisteredLuaMemHook(ARMPROC.instruct_adr, 2, ARMPROC.instruction, LUAMEMHOOK_EXEC);
#endif
- if(PROCNUM==0)
- {
- #ifdef DEVELOPER
- DEBUG_statistics.instructionHits[0].thumb[ARMPROC.instruction>>6]++;
- #endif
- cExecute = thumb_instructions_set_0[ARMPROC.instruction>>6](ARMPROC.instruction);
- }
- else {
- #ifdef DEVELOPER
- DEBUG_statistics.instructionHits[1].thumb[ARMPROC.instruction>>6]++;
- #endif
- cExecute = thumb_instructions_set_1[ARMPROC.instruction>>6](ARMPROC.instruction);
- }
-
-#ifdef GDB_STUB
- if ( ARMPROC.post_ex_fn != NULL) {
- /* call the external post execute function */
- ARMPROC.post_ex_fn( ARMPROC.post_ex_fn_data, ARMPROC.instruct_adr, 1);
- }
- ARMPROC.mem_if->prefetch32( ARMPROC.mem_if->data, ARMPROC.next_instruction);
-#endif
+ cExecute = thumb_instructions_set[PROCNUM][ARMPROC.instruction>>6](ARMPROC.instruction);
+
cFetch = armcpu_prefetch<PROCNUM>();
return MMU_fetchExecuteCycles<PROCNUM>(cExecute, cFetch);
}
-//these templates needed to be instantiated manually
+// these templates needed to be instantiated manually
template uint32_t armcpu_exec<0>();
template uint32_t armcpu_exec<1>();
+#ifdef HAVE_JIT
+void arm_jit_sync()
+{
+ NDS_ARM7.next_instruction = NDS_ARM7.instruct_adr;
+ NDS_ARM9.next_instruction = NDS_ARM9.instruct_adr;
+ armcpu_prefetch<0>();
+ armcpu_prefetch<1>();
+}
+
+template<int PROCNUM, bool jit> uint32_t armcpu_exec()
+{
+ if (jit)
+ {
+ ArmOpCompiled f = reinterpret_cast<ArmOpCompiled>(JIT_COMPILED_FUNC(ARMPROC.instruct_adr, PROCNUM));
+ return f ? f() : arm_jit_compile<PROCNUM>();
+ }
+
+ return armcpu_exec<PROCNUM>();
+}
+
+template uint32_t armcpu_exec<0, false>();
+template uint32_t armcpu_exec<0, true>();
+template uint32_t armcpu_exec<1, false>();
+template uint32_t armcpu_exec<1, true>();
+#endif
+
--- a/src/in_2sf/desmume/armcpu.h
+++ b/src/in_2sf/desmume/armcpu.h
@@ -22,45 +22,45 @@
#include "types.h"
#include "bits.h"
#include "MMU.h"
-#include "common.h"
-
-static inline uint32_t CODE(uint32_t i) { return (i >> 25) & 0x7; }
-
-static const uint32_t EXCEPTION_RESET = 0x00;
-static const uint32_t EXCEPTION_UNDEFINED_INSTRUCTION = 0x04;
-static const uint32_t EXCEPTION_SWI = 0x08;
-static const uint32_t EXCEPTION_PREFETCH_ABORT = 0x0C;
-static const uint32_t EXCEPTION_DATA_ABORT = 0x10;
-static const uint32_t EXCEPTION_RESERVED_0x14 = 0x14;
-static const uint32_t EXCEPTION_IRQ = 0x18;
-static const uint32_t EXCEPTION_FAST_IRQ = 0x1C;
-
-static inline uint32_t INSTRUCTION_INDEX(uint32_t i) { return ((i >> 16) & 0xFF0) | ((i >> 4) & 0xF); }
-
-static inline uint32_t ROR(uint32_t i, uint32_t j) { return (i >> j) | (i << (32 - j)); }
-
-template<typename T> static inline T UNSIGNED_OVERFLOW(T a, T b, T c) { return BIT31((a & b) | ((a | b) & ~c)); }
-
-template<typename T> static inline T UNSIGNED_UNDERFLOW(T a, T b, T c) { return BIT31((~a & b) | ((~a | b) & c)); }
-
-template<typename T> static inline T SIGNED_OVERFLOW(T a, T b, T c) { return BIT31((a & b & ~c) | (~a & ~b & c)); }
-
-template<typename T> static inline T SIGNED_UNDERFLOW(T a, T b, T c) { return BIT31((a & ~b & ~c) | (~a & b & c)); }
+#include "instructions.h"
+
+inline uint32_t CODE(uint32_t i) { return (i >> 25) & 0x7; }
+
+const uint32_t EXCEPTION_RESET = 0x00;
+const uint32_t EXCEPTION_UNDEFINED_INSTRUCTION = 0x04;
+const uint32_t EXCEPTION_SWI = 0x08;
+const uint32_t EXCEPTION_PREFETCH_ABORT = 0x0C;
+const uint32_t EXCEPTION_DATA_ABORT = 0x10;
+const uint32_t EXCEPTION_RESERVED_0x14 = 0x14;
+const uint32_t EXCEPTION_IRQ = 0x18;
+const uint32_t EXCEPTION_FAST_IRQ = 0x1C;
+
+inline uint32_t INSTRUCTION_INDEX(uint32_t i) { return ((i >> 16) & 0xFF0) | ((i >> 4) & 0xF); }
+
+inline uint32_t ROR(uint32_t i, uint32_t j) { return (i >> j) | (i << (32 - j)); }
+
+template<typename T> inline T UNSIGNED_OVERFLOW(T a, T b, T c) { return BIT31((a & b) | ((a | b) & ~c)); }
+
+template<typename T> inline T UNSIGNED_UNDERFLOW(T a, T b, T c) { return BIT31((~a & b) | ((~a | b) & c)); }
+
+template<typename T> inline T SIGNED_OVERFLOW(T a, T b, T c) { return BIT31((a & b & ~c) | (~a & ~b & c)); }
+
+template<typename T> inline T SIGNED_UNDERFLOW(T a, T b, T c) { return BIT31((a & ~b & ~c) | (~a & b & c)); }
// ============================= CPRS flags funcs
-static inline bool CarryFrom(int32_t left, int32_t right)
+inline bool CarryFrom(int32_t left, int32_t right)
{
uint32_t res = 0xFFFFFFFFU - static_cast<uint32_t>(left);
return static_cast<uint32_t>(right) > res;
}
-static inline bool BorrowFrom(int32_t left, int32_t right)
+inline bool BorrowFrom(int32_t left, int32_t right)
{
return static_cast<uint32_t>(right) > static_cast<uint32_t>(left);
}
-static inline bool OverflowFromADD(int32_t alu_out, int32_t left, int32_t right)
+inline bool OverflowFromADD(int32_t alu_out, int32_t left, int32_t right)
{
return ((left >= 0 && right >= 0) || (left < 0 && right < 0)) && ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0));
}
@@ -70,24 +70,57 @@
return ((left < 0 && right >= 0) || (left >= 0 && right < 0)) && ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0));
}
-//zero 15-feb-2009 - these werent getting used and they were getting in my way
-//#define EQ 0x0
-//#define NE 0x1
-//#define CS 0x2
-//#define CC 0x3
-//#define MI 0x4
-//#define PL 0x5
-//#define VS 0x6
-//#define VC 0x7
-//#define HI 0x8
-//#define LS 0x9
-//#define GE 0xA
-//#define LT 0xB
-//#define GT 0xC
-//#define LE 0xD
-//#define AL 0xE
-
-extern const uint8_t arm_cond_table[16 * 16];
+const uint8_t arm_cond_table[] =
+{
+ // N=0, Z=0, C=0, V=0
+ 0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF, // 0x00
+ 0x00,0xFF,0xFF,0x00,0xFF,0x00,0xFF,0x20, // 0x00
+ // N=0, Z=0, C=0, V=1
+ 0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x00, // 0x10
+ 0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x20,
+ // N=0, Z=0, C=1, V=0
+ 0x00,0xFF,0xFF,0x00,0x00,0xFF,0x00,0xFF, // 0x20
+ 0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x20,
+ // N=0, Z=0, C=1, V=1
+ 0x00,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x00, // 0x30
+ 0xFF,0x00,0x00,0xFF,0x00,0xFF,0xFF,0x20,
+ // N=0, Z=1, C=0, V=0
+ 0xFF,0x00,0x00,0xFF,0x00,0xFF,0x00,0xFF, // 0x40
+ 0x00,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x20,
+ // N=0, Z=1, C=0, V=1
+ 0xFF,0x00,0x00,0xFF,0x00,0xFF,0xFF,0x00, // 0x50
+ 0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x20,
+ // N=0, Z=1, C=1, V=0
+ 0xFF,0x00,0xFF,0x00,0x00,0xFF,0x00,0xFF, // 0x60
+ 0x00,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x20,
+ // N=0, Z=1, C=1, V=1
+ 0xFF,0x00,0xFF,0x00,0x00,0xFF,0xFF,0x00, // 0x70
+ 0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x20,
+ // N=1, Z=0, C=0, V=0
+ 0x00,0xFF,0x00,0xFF,0xFF,0x00,0x00,0xFF, // 0x80
+ 0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x20,
+ // N=1, Z=0, C=0, V=1
+ 0x00,0xFF,0x00,0xFF,0xFF,0x00,0xFF,0x00, // 0x90
+ 0x00,0xFF,0xFF,0x00,0xFF,0x00,0xFF,0x20,
+ // N=1, Z=0, C=1, V=0
+ 0x00,0xFF,0xFF,0x00,0xFF,0x00,0x00,0xFF, // 0xA0
+ 0xFF,0x00,0x00,0xFF,0x00,0xFF,0xFF,0x20,
+ // N=1, Z=0, C=1, V=1
+ 0x00,0xFF,0xFF,0x00,0xFF,0x00,0xFF,0x00, // 0xB0
+ 0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x20,
+ // N=1, Z=1, C=0, V=0
+ 0xFF,0x00,0x00,0xFF,0xFF,0x00,0x00,0xFF, // 0xC0
+ 0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x20,
+ // N=1, Z=1, C=0, V=1
+ 0xFF,0x00,0x00,0xFF,0xFF,0x00,0xFF,0x00, // 0xD0
+ 0x00,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x20,
+ // N=1, Z=1, C=1, V=0
+ 0xFF,0x00,0xFF,0x00,0xFF,0x00,0x00,0xFF, // 0xE0
+ 0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x20,
+ // N=1, Z=1, C=1, V=1
+ 0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00, // 0xF0
+ 0x00,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x20
+};
enum Mode
{
@@ -138,34 +171,7 @@
} Status_Reg;
#endif
-static inline uint8_t TEST_COND(uint32_t cond, uint32_t inst, Status_Reg CPSR) { return arm_cond_table[((CPSR.val >> 24) & 0xf0) | cond] & (1 << inst); }
-
-/**
- * The control interface to a CPU
- */
-/*struct armcpu_ctrl_iface
-{*/
- /** stall the processor */
- //void (*stall)(void *instance);
-
- /** unstall the processor */
- //void (*unstall)(void *instance);
-
- /** read a register value */
- //uint32_t (*read_reg)(void *instance, uint32_t reg_num);
-
- /** set a register value */
- //void (*set_reg)(void *instance, uint32_t reg_num, uint32_t value);
-
- /** install the post execute function */
- //void (*install_post_ex_fn)( void *instance, void (*fn)(void *, uint32_t, int), void *fn_data);
-
- /** remove the post execute function */
- //void (*remove_post_ex_fn)(void *instance);
-
- /** the private data passed to all interface functions */
- /*void *data;
-};*/
+inline uint8_t TEST_COND(uint32_t cond, uint32_t inst, Status_Reg CPSR) { return arm_cond_table[((CPSR.val >> 24) & 0xf0) | cond] & (1 << inst); }
typedef void *armcp_t;
@@ -190,8 +196,6 @@
uint32_t R8_fiq, R9_fiq, R10_fiq, R11_fiq, R12_fiq, R13_fiq, R14_fiq;
Status_Reg SPSR_svc, SPSR_abt, SPSR_und, SPSR_irq, SPSR_fiq;
- armcp_t *coproc[16];
-
uint32_t intVector;
uint8_t LDTBit; // 1 : ARMv5 style 0 : non ARMv5
bool waitIRQ;
@@ -205,43 +209,28 @@
// flag indicating if the processor is stalled (for debugging)
int stalled;
-#ifdef GDB_STUB
- /** there is a pending irq for the cpu */
- int irq_flag;
-
- /** the post executed function (if installed) */
- void (*post_ex_fn)(void *, uint32_t adr, int thumb);
-
- /** data for the post executed function */
- void *post_ex_fn_data;
-
- /** the memory interface */
- armcpu_memory_iface *mem_if;
-
- /** the ctrl interface */
- armcpu_ctrl_iface ctrl_iface;
+#if defined(_M_X64) || defined(__x86_64__)
+ u8 cond_table[16 * 16];
#endif
};
-#ifdef GDB_STUB
-int armcpu_new(armcpu_t *armcpu, uint32_t id, armcpu_memory_iface *mem_if, armcpu_ctrl_iface **ctrl_iface_ret);
-#else
int armcpu_new(armcpu_t *armcpu, uint32_t id);
-#endif
void armcpu_init(armcpu_t *armcpu, uint32_t adr);
uint32_t armcpu_switchMode(armcpu_t *armcpu, uint8_t mode);
-template<int PROCNUM> uint32_t armcpu_exec();
-
bool armcpu_irqException(armcpu_t *armcpu);
-//bool armcpu_flagIrq( armcpu_t *armcpu);
void armcpu_exception(armcpu_t *cpu, uint32_t number);
uint32_t TRAPUNDEF(armcpu_t* cpu);
uint32_t armcpu_Wait4IRQ(armcpu_t *cpu);
extern armcpu_t NDS_ARM7, NDS_ARM9;
-static inline void setIF(int PROCNUM, uint32_t flag)
+template<int PROCNUM> uint32_t armcpu_exec();
+#ifdef HAVE_JIT
+template<int PROCNUM, bool jit> uint32_t armcpu_exec();
+#endif
+
+inline void setIF(int PROCNUM, uint32_t flag)
{
// don't set generated bits!!!
assert(!(flag&0x00200000));
@@ -252,27 +241,10 @@
NDS_Reschedule();
}
-static inline void NDS_makeIrq(int PROCNUM, uint32_t num)
-{
- setIF(PROCNUM, 1<<num);
-}
-
-/*static inline char *decodeIntruction(bool thumb_mode, uint32_t instr)
-{
- char txt[20] = "";
- uint32_t tmp = 0;
- if (thumb_mode)
- {
- tmp = instr >> 6;
- strcpy(txt, intToBin(static_cast<uint16_t>(tmp)) + 6);
- }
- else
- {
- tmp = ((instr >> 16) & 0x0FF0) | ((instr >> 4) & 0x0F);
- strcpy(txt, intToBin(tmp) + 20);
- }
- return _strdup(txt);
-}*/
-
-#endif
-
+inline void NDS_makeIrq(int PROCNUM, uint32_t num)
+{
+ setIF(PROCNUM, 1 << num);
+}
+
+#endif
+
--- a/src/in_2sf/desmume/bios.cpp
+++ b/src/in_2sf/desmume/bios.cpp
@@ -17,178 +17,177 @@
*/
#include <cmath>
-
#include "cp15.h"
#include "MMU.h"
-//#include "debug.h"
#include "NDSSystem.h"
#define cpu (&ARMPROC)
#define TEMPLATE template<int PROCNUM>
-static const uint16_t getsinetbl[] = {
-0x0000, 0x0324, 0x0648, 0x096A, 0x0C8C, 0x0FAB, 0x12C8, 0x15E2,
-0x18F9, 0x1C0B, 0x1F1A, 0x2223, 0x2528, 0x2826, 0x2B1F, 0x2E11,
-0x30FB, 0x33DF, 0x36BA, 0x398C, 0x3C56, 0x3F17, 0x41CE, 0x447A,
-0x471C, 0x49B4, 0x4C3F, 0x4EBF, 0x5133, 0x539B, 0x55F5, 0x5842,
-0x5A82, 0x5CB3, 0x5ED7, 0x60EB, 0x62F1, 0x64E8, 0x66CF, 0x68A6,
-0x6A6D, 0x6C23, 0x6DC9, 0x6F5E, 0x70E2, 0x7254, 0x73B5, 0x7504,
-0x7641, 0x776B, 0x7884, 0x7989, 0x7A7C, 0x7B5C, 0x7C29, 0x7CE3,
-0x7D89, 0x7E1D, 0x7E9C, 0x7F09, 0x7F61, 0x7FA6, 0x7FD8, 0x7FF5
+static const uint16_t getsinetbl[] =
+{
+ 0x0000, 0x0324, 0x0648, 0x096A, 0x0C8C, 0x0FAB, 0x12C8, 0x15E2,
+ 0x18F9, 0x1C0B, 0x1F1A, 0x2223, 0x2528, 0x2826, 0x2B1F, 0x2E11,
+ 0x30FB, 0x33DF, 0x36BA, 0x398C, 0x3C56, 0x3F17, 0x41CE, 0x447A,
+ 0x471C, 0x49B4, 0x4C3F, 0x4EBF, 0x5133, 0x539B, 0x55F5, 0x5842,
+ 0x5A82, 0x5CB3, 0x5ED7, 0x60EB, 0x62F1, 0x64E8, 0x66CF, 0x68A6,
+ 0x6A6D, 0x6C23, 0x6DC9, 0x6F5E, 0x70E2, 0x7254, 0x73B5, 0x7504,
+ 0x7641, 0x776B, 0x7884, 0x7989, 0x7A7C, 0x7B5C, 0x7C29, 0x7CE3,
+ 0x7D89, 0x7E1D, 0x7E9C, 0x7F09, 0x7F61, 0x7FA6, 0x7FD8, 0x7FF5
};
-static const uint16_t getpitchtbl[] = {
-0x0000, 0x003B, 0x0076, 0x00B2, 0x00ED, 0x0128, 0x0164, 0x019F,
-0x01DB, 0x0217, 0x0252, 0x028E, 0x02CA, 0x0305, 0x0341, 0x037D,
-0x03B9, 0x03F5, 0x0431, 0x046E, 0x04AA, 0x04E6, 0x0522, 0x055F,
-0x059B, 0x05D8, 0x0614, 0x0651, 0x068D, 0x06CA, 0x0707, 0x0743,
-0x0780, 0x07BD, 0x07FA, 0x0837, 0x0874, 0x08B1, 0x08EF, 0x092C,
-0x0969, 0x09A7, 0x09E4, 0x0A21, 0x0A5F, 0x0A9C, 0x0ADA, 0x0B18,
-0x0B56, 0x0B93, 0x0BD1, 0x0C0F, 0x0C4D, 0x0C8B, 0x0CC9, 0x0D07,
-0x0D45, 0x0D84, 0x0DC2, 0x0E00, 0x0E3F, 0x0E7D, 0x0EBC, 0x0EFA,
-0x0F39, 0x0F78, 0x0FB6, 0x0FF5, 0x1034, 0x1073, 0x10B2, 0x10F1,
-0x1130, 0x116F, 0x11AE, 0x11EE, 0x122D, 0x126C, 0x12AC, 0x12EB,
-0x132B, 0x136B, 0x13AA, 0x13EA, 0x142A, 0x146A, 0x14A9, 0x14E9,
-0x1529, 0x1569, 0x15AA, 0x15EA, 0x162A, 0x166A, 0x16AB, 0x16EB,
-0x172C, 0x176C, 0x17AD, 0x17ED, 0x182E, 0x186F, 0x18B0, 0x18F0,
-0x1931, 0x1972, 0x19B3, 0x19F5, 0x1A36, 0x1A77, 0x1AB8, 0x1AFA,
-0x1B3B, 0x1B7D, 0x1BBE, 0x1C00, 0x1C41, 0x1C83, 0x1CC5, 0x1D07,
-0x1D48, 0x1D8A, 0x1DCC, 0x1E0E, 0x1E51, 0x1E93, 0x1ED5, 0x1F17,
-0x1F5A, 0x1F9C, 0x1FDF, 0x2021, 0x2064, 0x20A6, 0x20E9, 0x212C,
-0x216F, 0x21B2, 0x21F5, 0x2238, 0x227B, 0x22BE, 0x2301, 0x2344,
-0x2388, 0x23CB, 0x240E, 0x2452, 0x2496, 0x24D9, 0x251D, 0x2561,
-0x25A4, 0x25E8, 0x262C, 0x2670, 0x26B4, 0x26F8, 0x273D, 0x2781,
-0x27C5, 0x280A, 0x284E, 0x2892, 0x28D7, 0x291C, 0x2960, 0x29A5,
-0x29EA, 0x2A2F, 0x2A74, 0x2AB9, 0x2AFE, 0x2B43, 0x2B88, 0x2BCD,
-0x2C13, 0x2C58, 0x2C9D, 0x2CE3, 0x2D28, 0x2D6E, 0x2DB4, 0x2DF9,
-0x2E3F, 0x2E85, 0x2ECB, 0x2F11, 0x2F57, 0x2F9D, 0x2FE3, 0x302A,
-0x3070, 0x30B6, 0x30FD, 0x3143, 0x318A, 0x31D0, 0x3217, 0x325E,
-0x32A5, 0x32EC, 0x3332, 0x3379, 0x33C1, 0x3408, 0x344F, 0x3496,
-0x34DD, 0x3525, 0x356C, 0x35B4, 0x35FB, 0x3643, 0x368B, 0x36D3,
-0x371A, 0x3762, 0x37AA, 0x37F2, 0x383A, 0x3883, 0x38CB, 0x3913,
-0x395C, 0x39A4, 0x39ED, 0x3A35, 0x3A7E, 0x3AC6, 0x3B0F, 0x3B58,
-0x3BA1, 0x3BEA, 0x3C33, 0x3C7C, 0x3CC5, 0x3D0E, 0x3D58, 0x3DA1,
-0x3DEA, 0x3E34, 0x3E7D, 0x3EC7, 0x3F11, 0x3F5A, 0x3FA4, 0x3FEE,
-0x4038, 0x4082, 0x40CC, 0x4116, 0x4161, 0x41AB, 0x41F5, 0x4240,
-0x428A, 0x42D5, 0x431F, 0x436A, 0x43B5, 0x4400, 0x444B, 0x4495,
-0x44E1, 0x452C, 0x4577, 0x45C2, 0x460D, 0x4659, 0x46A4, 0x46F0,
-0x473B, 0x4787, 0x47D3, 0x481E, 0x486A, 0x48B6, 0x4902, 0x494E,
-0x499A, 0x49E6, 0x4A33, 0x4A7F, 0x4ACB, 0x4B18, 0x4B64, 0x4BB1,
-0x4BFE, 0x4C4A, 0x4C97, 0x4CE4, 0x4D31, 0x4D7E, 0x4DCB, 0x4E18,
-0x4E66, 0x4EB3, 0x4F00, 0x4F4E, 0x4F9B, 0x4FE9, 0x5036, 0x5084,
-0x50D2, 0x5120, 0x516E, 0x51BC, 0x520A, 0x5258, 0x52A6, 0x52F4,
-0x5343, 0x5391, 0x53E0, 0x542E, 0x547D, 0x54CC, 0x551A, 0x5569,
-0x55B8, 0x5607, 0x5656, 0x56A5, 0x56F4, 0x5744, 0x5793, 0x57E2,
-0x5832, 0x5882, 0x58D1, 0x5921, 0x5971, 0x59C1, 0x5A10, 0x5A60,
-0x5AB0, 0x5B01, 0x5B51, 0x5BA1, 0x5BF1, 0x5C42, 0x5C92, 0x5CE3,
-0x5D34, 0x5D84, 0x5DD5, 0x5E26, 0x5E77, 0x5EC8, 0x5F19, 0x5F6A,
-0x5FBB, 0x600D, 0x605E, 0x60B0, 0x6101, 0x6153, 0x61A4, 0x61F6,
-0x6248, 0x629A, 0x62EC, 0x633E, 0x6390, 0x63E2, 0x6434, 0x6487,
-0x64D9, 0x652C, 0x657E, 0x65D1, 0x6624, 0x6676, 0x66C9, 0x671C,
-0x676F, 0x67C2, 0x6815, 0x6869, 0x68BC, 0x690F, 0x6963, 0x69B6,
-0x6A0A, 0x6A5E, 0x6AB1, 0x6B05, 0x6B59, 0x6BAD, 0x6C01, 0x6C55,
-0x6CAA, 0x6CFE, 0x6D52, 0x6DA7, 0x6DFB, 0x6E50, 0x6EA4, 0x6EF9,
-0x6F4E, 0x6FA3, 0x6FF8, 0x704D, 0x70A2, 0x70F7, 0x714D, 0x71A2,
-0x71F7, 0x724D, 0x72A2, 0x72F8, 0x734E, 0x73A4, 0x73FA, 0x7450,
-0x74A6, 0x74FC, 0x7552, 0x75A8, 0x75FF, 0x7655, 0x76AC, 0x7702,
-0x7759, 0x77B0, 0x7807, 0x785E, 0x78B4, 0x790C, 0x7963, 0x79BA,
-0x7A11, 0x7A69, 0x7AC0, 0x7B18, 0x7B6F, 0x7BC7, 0x7C1F, 0x7C77,
-0x7CCF, 0x7D27, 0x7D7F, 0x7DD7, 0x7E2F, 0x7E88, 0x7EE0, 0x7F38,
-0x7F91, 0x7FEA, 0x8042, 0x809B, 0x80F4, 0x814D, 0x81A6, 0x81FF,
-0x8259, 0x82B2, 0x830B, 0x8365, 0x83BE, 0x8418, 0x8472, 0x84CB,
-0x8525, 0x857F, 0x85D9, 0x8633, 0x868E, 0x86E8, 0x8742, 0x879D,
-0x87F7, 0x8852, 0x88AC, 0x8907, 0x8962, 0x89BD, 0x8A18, 0x8A73,
-0x8ACE, 0x8B2A, 0x8B85, 0x8BE0, 0x8C3C, 0x8C97, 0x8CF3, 0x8D4F,
-0x8DAB, 0x8E07, 0x8E63, 0x8EBF, 0x8F1B, 0x8F77, 0x8FD4, 0x9030,
-0x908C, 0x90E9, 0x9146, 0x91A2, 0x91FF, 0x925C, 0x92B9, 0x9316,
-0x9373, 0x93D1, 0x942E, 0x948C, 0x94E9, 0x9547, 0x95A4, 0x9602,
-0x9660, 0x96BE, 0x971C, 0x977A, 0x97D8, 0x9836, 0x9895, 0x98F3,
-0x9952, 0x99B0, 0x9A0F, 0x9A6E, 0x9ACD, 0x9B2C, 0x9B8B, 0x9BEA,
-0x9C49, 0x9CA8, 0x9D08, 0x9D67, 0x9DC7, 0x9E26, 0x9E86, 0x9EE6,
-0x9F46, 0x9FA6, 0xA006, 0xA066, 0xA0C6, 0xA127, 0xA187, 0xA1E8,
-0xA248, 0xA2A9, 0xA30A, 0xA36B, 0xA3CC, 0xA42D, 0xA48E, 0xA4EF,
-0xA550, 0xA5B2, 0xA613, 0xA675, 0xA6D6, 0xA738, 0xA79A, 0xA7FC,
-0xA85E, 0xA8C0, 0xA922, 0xA984, 0xA9E7, 0xAA49, 0xAAAC, 0xAB0E,
-0xAB71, 0xABD4, 0xAC37, 0xAC9A, 0xACFD, 0xAD60, 0xADC3, 0xAE27,
-0xAE8A, 0xAEED, 0xAF51, 0xAFB5, 0xB019, 0xB07C, 0xB0E0, 0xB145,
-0xB1A9, 0xB20D, 0xB271, 0xB2D6, 0xB33A, 0xB39F, 0xB403, 0xB468,
-0xB4CD, 0xB532, 0xB597, 0xB5FC, 0xB662, 0xB6C7, 0xB72C, 0xB792,
-0xB7F7, 0xB85D, 0xB8C3, 0xB929, 0xB98F, 0xB9F5, 0xBA5B, 0xBAC1,
-0xBB28, 0xBB8E, 0xBBF5, 0xBC5B, 0xBCC2, 0xBD29, 0xBD90, 0xBDF7,
-0xBE5E, 0xBEC5, 0xBF2C, 0xBF94, 0xBFFB, 0xC063, 0xC0CA, 0xC132,
-0xC19A, 0xC202, 0xC26A, 0xC2D2, 0xC33A, 0xC3A2, 0xC40B, 0xC473,
-0xC4DC, 0xC544, 0xC5AD, 0xC616, 0xC67F, 0xC6E8, 0xC751, 0xC7BB,
-0xC824, 0xC88D, 0xC8F7, 0xC960, 0xC9CA, 0xCA34, 0xCA9E, 0xCB08,
-0xCB72, 0xCBDC, 0xCC47, 0xCCB1, 0xCD1B, 0xCD86, 0xCDF1, 0xCE5B,
-0xCEC6, 0xCF31, 0xCF9C, 0xD008, 0xD073, 0xD0DE, 0xD14A, 0xD1B5,
-0xD221, 0xD28D, 0xD2F8, 0xD364, 0xD3D0, 0xD43D, 0xD4A9, 0xD515,
-0xD582, 0xD5EE, 0xD65B, 0xD6C7, 0xD734, 0xD7A1, 0xD80E, 0xD87B,
-0xD8E9, 0xD956, 0xD9C3, 0xDA31, 0xDA9E, 0xDB0C, 0xDB7A, 0xDBE8,
-0xDC56, 0xDCC4, 0xDD32, 0xDDA0, 0xDE0F, 0xDE7D, 0xDEEC, 0xDF5B,
-0xDFC9, 0xE038, 0xE0A7, 0xE116, 0xE186, 0xE1F5, 0xE264, 0xE2D4,
-0xE343, 0xE3B3, 0xE423, 0xE493, 0xE503, 0xE573, 0xE5E3, 0xE654,
-0xE6C4, 0xE735, 0xE7A5, 0xE816, 0xE887, 0xE8F8, 0xE969, 0xE9DA,
-0xEA4B, 0xEABC, 0xEB2E, 0xEB9F, 0xEC11, 0xEC83, 0xECF5, 0xED66,
-0xEDD9, 0xEE4B, 0xEEBD, 0xEF2F, 0xEFA2, 0xF014, 0xF087, 0xF0FA,
-0xF16D, 0xF1E0, 0xF253, 0xF2C6, 0xF339, 0xF3AD, 0xF420, 0xF494,
-0xF507, 0xF57B, 0xF5EF, 0xF663, 0xF6D7, 0xF74C, 0xF7C0, 0xF834,
-0xF8A9, 0xF91E, 0xF992, 0xFA07, 0xFA7C, 0xFAF1, 0xFB66, 0xFBDC,
-0xFC51, 0xFCC7, 0xFD3C, 0xFDB2, 0xFE28, 0xFE9E, 0xFF14, 0xFF8A
+static const uint16_t getpitchtbl[] =
+{
+ 0x0000, 0x003B, 0x0076, 0x00B2, 0x00ED, 0x0128, 0x0164, 0x019F,
+ 0x01DB, 0x0217, 0x0252, 0x028E, 0x02CA, 0x0305, 0x0341, 0x037D,
+ 0x03B9, 0x03F5, 0x0431, 0x046E, 0x04AA, 0x04E6, 0x0522, 0x055F,
+ 0x059B, 0x05D8, 0x0614, 0x0651, 0x068D, 0x06CA, 0x0707, 0x0743,
+ 0x0780, 0x07BD, 0x07FA, 0x0837, 0x0874, 0x08B1, 0x08EF, 0x092C,
+ 0x0969, 0x09A7, 0x09E4, 0x0A21, 0x0A5F, 0x0A9C, 0x0ADA, 0x0B18,
+ 0x0B56, 0x0B93, 0x0BD1, 0x0C0F, 0x0C4D, 0x0C8B, 0x0CC9, 0x0D07,
+ 0x0D45, 0x0D84, 0x0DC2, 0x0E00, 0x0E3F, 0x0E7D, 0x0EBC, 0x0EFA,
+ 0x0F39, 0x0F78, 0x0FB6, 0x0FF5, 0x1034, 0x1073, 0x10B2, 0x10F1,
+ 0x1130, 0x116F, 0x11AE, 0x11EE, 0x122D, 0x126C, 0x12AC, 0x12EB,
+ 0x132B, 0x136B, 0x13AA, 0x13EA, 0x142A, 0x146A, 0x14A9, 0x14E9,
+ 0x1529, 0x1569, 0x15AA, 0x15EA, 0x162A, 0x166A, 0x16AB, 0x16EB,
+ 0x172C, 0x176C, 0x17AD, 0x17ED, 0x182E, 0x186F, 0x18B0, 0x18F0,
+ 0x1931, 0x1972, 0x19B3, 0x19F5, 0x1A36, 0x1A77, 0x1AB8, 0x1AFA,
+ 0x1B3B, 0x1B7D, 0x1BBE, 0x1C00, 0x1C41, 0x1C83, 0x1CC5, 0x1D07,
+ 0x1D48, 0x1D8A, 0x1DCC, 0x1E0E, 0x1E51, 0x1E93, 0x1ED5, 0x1F17,
+ 0x1F5A, 0x1F9C, 0x1FDF, 0x2021, 0x2064, 0x20A6, 0x20E9, 0x212C,
+ 0x216F, 0x21B2, 0x21F5, 0x2238, 0x227B, 0x22BE, 0x2301, 0x2344,
+ 0x2388, 0x23CB, 0x240E, 0x2452, 0x2496, 0x24D9, 0x251D, 0x2561,
+ 0x25A4, 0x25E8, 0x262C, 0x2670, 0x26B4, 0x26F8, 0x273D, 0x2781,
+ 0x27C5, 0x280A, 0x284E, 0x2892, 0x28D7, 0x291C, 0x2960, 0x29A5,
+ 0x29EA, 0x2A2F, 0x2A74, 0x2AB9, 0x2AFE, 0x2B43, 0x2B88, 0x2BCD,
+ 0x2C13, 0x2C58, 0x2C9D, 0x2CE3, 0x2D28, 0x2D6E, 0x2DB4, 0x2DF9,
+ 0x2E3F, 0x2E85, 0x2ECB, 0x2F11, 0x2F57, 0x2F9D, 0x2FE3, 0x302A,
+ 0x3070, 0x30B6, 0x30FD, 0x3143, 0x318A, 0x31D0, 0x3217, 0x325E,
+ 0x32A5, 0x32EC, 0x3332, 0x3379, 0x33C1, 0x3408, 0x344F, 0x3496,
+ 0x34DD, 0x3525, 0x356C, 0x35B4, 0x35FB, 0x3643, 0x368B, 0x36D3,
+ 0x371A, 0x3762, 0x37AA, 0x37F2, 0x383A, 0x3883, 0x38CB, 0x3913,
+ 0x395C, 0x39A4, 0x39ED, 0x3A35, 0x3A7E, 0x3AC6, 0x3B0F, 0x3B58,
+ 0x3BA1, 0x3BEA, 0x3C33, 0x3C7C, 0x3CC5, 0x3D0E, 0x3D58, 0x3DA1,
+ 0x3DEA, 0x3E34, 0x3E7D, 0x3EC7, 0x3F11, 0x3F5A, 0x3FA4, 0x3FEE,
+ 0x4038, 0x4082, 0x40CC, 0x4116, 0x4161, 0x41AB, 0x41F5, 0x4240,
+ 0x428A, 0x42D5, 0x431F, 0x436A, 0x43B5, 0x4400, 0x444B, 0x4495,
+ 0x44E1, 0x452C, 0x4577, 0x45C2, 0x460D, 0x4659, 0x46A4, 0x46F0,
+ 0x473B, 0x4787, 0x47D3, 0x481E, 0x486A, 0x48B6, 0x4902, 0x494E,
+ 0x499A, 0x49E6, 0x4A33, 0x4A7F, 0x4ACB, 0x4B18, 0x4B64, 0x4BB1,
+ 0x4BFE, 0x4C4A, 0x4C97, 0x4CE4, 0x4D31, 0x4D7E, 0x4DCB, 0x4E18,
+ 0x4E66, 0x4EB3, 0x4F00, 0x4F4E, 0x4F9B, 0x4FE9, 0x5036, 0x5084,
+ 0x50D2, 0x5120, 0x516E, 0x51BC, 0x520A, 0x5258, 0x52A6, 0x52F4,
+ 0x5343, 0x5391, 0x53E0, 0x542E, 0x547D, 0x54CC, 0x551A, 0x5569,
+ 0x55B8, 0x5607, 0x5656, 0x56A5, 0x56F4, 0x5744, 0x5793, 0x57E2,
+ 0x5832, 0x5882, 0x58D1, 0x5921, 0x5971, 0x59C1, 0x5A10, 0x5A60,
+ 0x5AB0, 0x5B01, 0x5B51, 0x5BA1, 0x5BF1, 0x5C42, 0x5C92, 0x5CE3,
+ 0x5D34, 0x5D84, 0x5DD5, 0x5E26, 0x5E77, 0x5EC8, 0x5F19, 0x5F6A,
+ 0x5FBB, 0x600D, 0x605E, 0x60B0, 0x6101, 0x6153, 0x61A4, 0x61F6,
+ 0x6248, 0x629A, 0x62EC, 0x633E, 0x6390, 0x63E2, 0x6434, 0x6487,
+ 0x64D9, 0x652C, 0x657E, 0x65D1, 0x6624, 0x6676, 0x66C9, 0x671C,
+ 0x676F, 0x67C2, 0x6815, 0x6869, 0x68BC, 0x690F, 0x6963, 0x69B6,
+ 0x6A0A, 0x6A5E, 0x6AB1, 0x6B05, 0x6B59, 0x6BAD, 0x6C01, 0x6C55,
+ 0x6CAA, 0x6CFE, 0x6D52, 0x6DA7, 0x6DFB, 0x6E50, 0x6EA4, 0x6EF9,
+ 0x6F4E, 0x6FA3, 0x6FF8, 0x704D, 0x70A2, 0x70F7, 0x714D, 0x71A2,
+ 0x71F7, 0x724D, 0x72A2, 0x72F8, 0x734E, 0x73A4, 0x73FA, 0x7450,
+ 0x74A6, 0x74FC, 0x7552, 0x75A8, 0x75FF, 0x7655, 0x76AC, 0x7702,
+ 0x7759, 0x77B0, 0x7807, 0x785E, 0x78B4, 0x790C, 0x7963, 0x79BA,
+ 0x7A11, 0x7A69, 0x7AC0, 0x7B18, 0x7B6F, 0x7BC7, 0x7C1F, 0x7C77,
+ 0x7CCF, 0x7D27, 0x7D7F, 0x7DD7, 0x7E2F, 0x7E88, 0x7EE0, 0x7F38,
+ 0x7F91, 0x7FEA, 0x8042, 0x809B, 0x80F4, 0x814D, 0x81A6, 0x81FF,
+ 0x8259, 0x82B2, 0x830B, 0x8365, 0x83BE, 0x8418, 0x8472, 0x84CB,
+ 0x8525, 0x857F, 0x85D9, 0x8633, 0x868E, 0x86E8, 0x8742, 0x879D,
+ 0x87F7, 0x8852, 0x88AC, 0x8907, 0x8962, 0x89BD, 0x8A18, 0x8A73,
+ 0x8ACE, 0x8B2A, 0x8B85, 0x8BE0, 0x8C3C, 0x8C97, 0x8CF3, 0x8D4F,
+ 0x8DAB, 0x8E07, 0x8E63, 0x8EBF, 0x8F1B, 0x8F77, 0x8FD4, 0x9030,
+ 0x908C, 0x90E9, 0x9146, 0x91A2, 0x91FF, 0x925C, 0x92B9, 0x9316,
+ 0x9373, 0x93D1, 0x942E, 0x948C, 0x94E9, 0x9547, 0x95A4, 0x9602,
+ 0x9660, 0x96BE, 0x971C, 0x977A, 0x97D8, 0x9836, 0x9895, 0x98F3,
+ 0x9952, 0x99B0, 0x9A0F, 0x9A6E, 0x9ACD, 0x9B2C, 0x9B8B, 0x9BEA,
+ 0x9C49, 0x9CA8, 0x9D08, 0x9D67, 0x9DC7, 0x9E26, 0x9E86, 0x9EE6,
+ 0x9F46, 0x9FA6, 0xA006, 0xA066, 0xA0C6, 0xA127, 0xA187, 0xA1E8,
+ 0xA248, 0xA2A9, 0xA30A, 0xA36B, 0xA3CC, 0xA42D, 0xA48E, 0xA4EF,
+ 0xA550, 0xA5B2, 0xA613, 0xA675, 0xA6D6, 0xA738, 0xA79A, 0xA7FC,
+ 0xA85E, 0xA8C0, 0xA922, 0xA984, 0xA9E7, 0xAA49, 0xAAAC, 0xAB0E,
+ 0xAB71, 0xABD4, 0xAC37, 0xAC9A, 0xACFD, 0xAD60, 0xADC3, 0xAE27,
+ 0xAE8A, 0xAEED, 0xAF51, 0xAFB5, 0xB019, 0xB07C, 0xB0E0, 0xB145,
+ 0xB1A9, 0xB20D, 0xB271, 0xB2D6, 0xB33A, 0xB39F, 0xB403, 0xB468,
+ 0xB4CD, 0xB532, 0xB597, 0xB5FC, 0xB662, 0xB6C7, 0xB72C, 0xB792,
+ 0xB7F7, 0xB85D, 0xB8C3, 0xB929, 0xB98F, 0xB9F5, 0xBA5B, 0xBAC1,
+ 0xBB28, 0xBB8E, 0xBBF5, 0xBC5B, 0xBCC2, 0xBD29, 0xBD90, 0xBDF7,
+ 0xBE5E, 0xBEC5, 0xBF2C, 0xBF94, 0xBFFB, 0xC063, 0xC0CA, 0xC132,
+ 0xC19A, 0xC202, 0xC26A, 0xC2D2, 0xC33A, 0xC3A2, 0xC40B, 0xC473,
+ 0xC4DC, 0xC544, 0xC5AD, 0xC616, 0xC67F, 0xC6E8, 0xC751, 0xC7BB,
+ 0xC824, 0xC88D, 0xC8F7, 0xC960, 0xC9CA, 0xCA34, 0xCA9E, 0xCB08,
+ 0xCB72, 0xCBDC, 0xCC47, 0xCCB1, 0xCD1B, 0xCD86, 0xCDF1, 0xCE5B,
+ 0xCEC6, 0xCF31, 0xCF9C, 0xD008, 0xD073, 0xD0DE, 0xD14A, 0xD1B5,
+ 0xD221, 0xD28D, 0xD2F8, 0xD364, 0xD3D0, 0xD43D, 0xD4A9, 0xD515,
+ 0xD582, 0xD5EE, 0xD65B, 0xD6C7, 0xD734, 0xD7A1, 0xD80E, 0xD87B,
+ 0xD8E9, 0xD956, 0xD9C3, 0xDA31, 0xDA9E, 0xDB0C, 0xDB7A, 0xDBE8,
+ 0xDC56, 0xDCC4, 0xDD32, 0xDDA0, 0xDE0F, 0xDE7D, 0xDEEC, 0xDF5B,
+ 0xDFC9, 0xE038, 0xE0A7, 0xE116, 0xE186, 0xE1F5, 0xE264, 0xE2D4,
+ 0xE343, 0xE3B3, 0xE423, 0xE493, 0xE503, 0xE573, 0xE5E3, 0xE654,
+ 0xE6C4, 0xE735, 0xE7A5, 0xE816, 0xE887, 0xE8F8, 0xE969, 0xE9DA,
+ 0xEA4B, 0xEABC, 0xEB2E, 0xEB9F, 0xEC11, 0xEC83, 0xECF5, 0xED66,
+ 0xEDD9, 0xEE4B, 0xEEBD, 0xEF2F, 0xEFA2, 0xF014, 0xF087, 0xF0FA,
+ 0xF16D, 0xF1E0, 0xF253, 0xF2C6, 0xF339, 0xF3AD, 0xF420, 0xF494,
+ 0xF507, 0xF57B, 0xF5EF, 0xF663, 0xF6D7, 0xF74C, 0xF7C0, 0xF834,
+ 0xF8A9, 0xF91E, 0xF992, 0xFA07, 0xFA7C, 0xFAF1, 0xFB66, 0xFBDC,
+ 0xFC51, 0xFCC7, 0xFD3C, 0xFDB2, 0xFE28, 0xFE9E, 0xFF14, 0xFF8A
};
-static const uint8_t getvoltbl[] = {
-0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
-0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
-0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03,
-0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
-0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
-0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
-0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05,
-0x05, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06,
-0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x08, 0x08, 0x08, 0x08,
-0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B,
-0x0B, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0D, 0x0D, 0x0D, 0x0D, 0x0D, 0x0D, 0x0E,
-0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x10, 0x10, 0x10, 0x10, 0x10,
-0x10, 0x11, 0x11, 0x11, 0x11, 0x11, 0x12, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13, 0x14,
-0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x17, 0x17, 0x17, 0x18,
-0x18, 0x18, 0x18, 0x19, 0x19, 0x19, 0x19, 0x1A, 0x1A, 0x1A, 0x1B, 0x1B, 0x1B, 0x1C, 0x1C, 0x1C,
-0x1D, 0x1D, 0x1D, 0x1E, 0x1E, 0x1E, 0x1F, 0x1F, 0x1F, 0x20, 0x20, 0x20, 0x21, 0x21, 0x22, 0x22,
-0x22, 0x23, 0x23, 0x24, 0x24, 0x24, 0x25, 0x25, 0x26, 0x26, 0x27, 0x27, 0x27, 0x28, 0x28, 0x29,
-0x29, 0x2A, 0x2A, 0x2B, 0x2B, 0x2C, 0x2C, 0x2D, 0x2D, 0x2E, 0x2E, 0x2F, 0x2F, 0x30, 0x31, 0x31,
-0x32, 0x32, 0x33, 0x33, 0x34, 0x35, 0x35, 0x36, 0x36, 0x37, 0x38, 0x38, 0x39, 0x3A, 0x3A, 0x3B,
-0x3C, 0x3C, 0x3D, 0x3E, 0x3F, 0x3F, 0x40, 0x41, 0x42, 0x42, 0x43, 0x44, 0x45, 0x45, 0x46, 0x47,
-0x48, 0x49, 0x4A, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x52, 0x53, 0x54, 0x55,
-0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
-0x68, 0x69, 0x6A, 0x6B, 0x6D, 0x6E, 0x6F, 0x71, 0x72, 0x73, 0x75, 0x76, 0x77, 0x79, 0x7A, 0x7B,
-0x7D, 0x7E, 0x7F, 0x20, 0x21, 0x21, 0x21, 0x22, 0x22, 0x23, 0x23, 0x23, 0x24, 0x24, 0x25, 0x25,
-0x26, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x29, 0x2A, 0x2A, 0x2B, 0x2B, 0x2C, 0x2C, 0x2D,
-0x2D, 0x2E, 0x2E, 0x2F, 0x2F, 0x30, 0x30, 0x31, 0x31, 0x32, 0x33, 0x33, 0x34, 0x34, 0x35, 0x36,
-0x36, 0x37, 0x37, 0x38, 0x39, 0x39, 0x3A, 0x3B, 0x3B, 0x3C, 0x3D, 0x3E, 0x3E, 0x3F, 0x40, 0x40,
-0x41, 0x42, 0x43, 0x43, 0x44, 0x45, 0x46, 0x47, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4D,
-0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D,
-0x5E, 0x5F, 0x60, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6F, 0x70,
-0x71, 0x73, 0x74, 0x75, 0x77, 0x78, 0x79, 0x7B, 0x7C, 0x7E, 0x7E, 0x40, 0x41, 0x42, 0x43, 0x43,
-0x44, 0x45, 0x46, 0x47, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51,
-0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61,
-0x62, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6B, 0x6C, 0x6D, 0x6E, 0x70, 0x71, 0x72, 0x74, 0x75,
-0x76, 0x78, 0x79, 0x7B, 0x7C, 0x7D, 0x7E, 0x40, 0x41, 0x42, 0x42, 0x43, 0x44, 0x45, 0x46, 0x46,
-0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55,
-0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x65, 0x66,
-0x67, 0x68, 0x69, 0x6A, 0x6C, 0x6D, 0x6E, 0x6F, 0x71, 0x72, 0x73, 0x75, 0x76, 0x77, 0x79, 0x7A,
-0x7C, 0x7D, 0x7E, 0x7F
+static const uint8_t getvoltbl[] =
+{
+ 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03,
+ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
+ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
+ 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
+ 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05,
+ 0x05, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06,
+ 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x08, 0x08, 0x08, 0x08,
+ 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
+ 0x09, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B,
+ 0x0B, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0D, 0x0D, 0x0D, 0x0D, 0x0D, 0x0D, 0x0E,
+ 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x10, 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x11, 0x11, 0x11, 0x11, 0x11, 0x12, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13, 0x14,
+ 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x17, 0x17, 0x17, 0x18,
+ 0x18, 0x18, 0x18, 0x19, 0x19, 0x19, 0x19, 0x1A, 0x1A, 0x1A, 0x1B, 0x1B, 0x1B, 0x1C, 0x1C, 0x1C,
+ 0x1D, 0x1D, 0x1D, 0x1E, 0x1E, 0x1E, 0x1F, 0x1F, 0x1F, 0x20, 0x20, 0x20, 0x21, 0x21, 0x22, 0x22,
+ 0x22, 0x23, 0x23, 0x24, 0x24, 0x24, 0x25, 0x25, 0x26, 0x26, 0x27, 0x27, 0x27, 0x28, 0x28, 0x29,
+ 0x29, 0x2A, 0x2A, 0x2B, 0x2B, 0x2C, 0x2C, 0x2D, 0x2D, 0x2E, 0x2E, 0x2F, 0x2F, 0x30, 0x31, 0x31,
+ 0x32, 0x32, 0x33, 0x33, 0x34, 0x35, 0x35, 0x36, 0x36, 0x37, 0x38, 0x38, 0x39, 0x3A, 0x3A, 0x3B,
+ 0x3C, 0x3C, 0x3D, 0x3E, 0x3F, 0x3F, 0x40, 0x41, 0x42, 0x42, 0x43, 0x44, 0x45, 0x45, 0x46, 0x47,
+ 0x48, 0x49, 0x4A, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x52, 0x53, 0x54, 0x55,
+ 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
+ 0x68, 0x69, 0x6A, 0x6B, 0x6D, 0x6E, 0x6F, 0x71, 0x72, 0x73, 0x75, 0x76, 0x77, 0x79, 0x7A, 0x7B,
+ 0x7D, 0x7E, 0x7F, 0x20, 0x21, 0x21, 0x21, 0x22, 0x22, 0x23, 0x23, 0x23, 0x24, 0x24, 0x25, 0x25,
+ 0x26, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x29, 0x2A, 0x2A, 0x2B, 0x2B, 0x2C, 0x2C, 0x2D,
+ 0x2D, 0x2E, 0x2E, 0x2F, 0x2F, 0x30, 0x30, 0x31, 0x31, 0x32, 0x33, 0x33, 0x34, 0x34, 0x35, 0x36,
+ 0x36, 0x37, 0x37, 0x38, 0x39, 0x39, 0x3A, 0x3B, 0x3B, 0x3C, 0x3D, 0x3E, 0x3E, 0x3F, 0x40, 0x40,
+ 0x41, 0x42, 0x43, 0x43, 0x44, 0x45, 0x46, 0x47, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4D,
+ 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D,
+ 0x5E, 0x5F, 0x60, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6F, 0x70,
+ 0x71, 0x73, 0x74, 0x75, 0x77, 0x78, 0x79, 0x7B, 0x7C, 0x7E, 0x7E, 0x40, 0x41, 0x42, 0x43, 0x43,
+ 0x44, 0x45, 0x46, 0x47, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51,
+ 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61,
+ 0x62, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6B, 0x6C, 0x6D, 0x6E, 0x70, 0x71, 0x72, 0x74, 0x75,
+ 0x76, 0x78, 0x79, 0x7B, 0x7C, 0x7D, 0x7E, 0x40, 0x41, 0x42, 0x42, 0x43, 0x44, 0x45, 0x46, 0x46,
+ 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55,
+ 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x65, 0x66,
+ 0x67, 0x68, 0x69, 0x6A, 0x6C, 0x6D, 0x6E, 0x6F, 0x71, 0x72, 0x73, 0x75, 0x76, 0x77, 0x79, 0x7A,
+ 0x7C, 0x7D, 0x7E, 0x7F
};
TEMPLATE static uint32_t bios_nop()
{
- /*LOG("SWI: ARM%c Unimplemented BIOS function %02X was used. R0:%08X, R1:%08X, R2:%08X\n", PROCNUM?'7':'9',
- (cpu->instruction)&0x1F, cpu->R[0], cpu->R[1], cpu->R[2]);*/
return 3;
}
@@ -196,13 +195,9 @@
{
uint32_t elapsed;
- //printf("%lld waitbyloop\n",nds_timer);
- //INFO("ARM%c: SWI 0x03 (WaitByLoop)\n", PROCNUM?'7':'9');
if (PROCNUM == ARMCPU_ARM9)
{
- armcp15_t *cp = (armcp15_t*)(cpu->coproc[15]);
-
- if (cp->ctrl & ((1<<16)|(1<<18))) // DTCM or ITCM is on (cache)
+ if (cp15.ctrl & ((1 << 16) | (1 << 18))) // DTCM or ITCM is on (cache)
elapsed = cpu->R[0] * 2;
else
elapsed = cpu->R[0] * 8;
@@ -215,45 +210,43 @@
TEMPLATE static uint32_t wait4IRQ()
{
- cpu->waitIRQ = true;
+ cpu->waitIRQ = true;
cpu->halt_IE_and_IF = true;
return 1;
}
-TEMPLATE uint32_t intrWaitARM()
-{
- //TODO - account for differences between arm7 and arm9 (according to gbatek, the "bug doesn't work")
-
- const uint32_t intrFlagAdr = (PROCNUM == ARMCPU_ARM7)
- ? 0x380FFF8
- : (((armcp15_t *)(cpu->coproc[15]))->DTCMRegion&0xFFFFF000)+0x3FF8;
-
- //set IME=1
- //without this, no irq handlers can happen (even though IF&IE waits can happily happen)
- //and so no bits in the OS irq flag variable can get set by the handlers
+TEMPLATE static uint32_t intrWaitARM()
+{
+ // TODO - account for differences between arm7 and arm9 (according to gbatek, the "bug doesn't work")
+
+ const uint32_t intrFlagAdr = PROCNUM == ARMCPU_ARM7 ? 0x380FFF8 : (cp15.DTCMRegion & 0xFFFFF000) + 0x3FF8;
+
+ // set IME=1
+ // without this, no irq handlers can happen (even though IF&IE waits can happily happen)
+ // and so no bits in the OS irq flag variable can get set by the handlers
_MMU_write32<PROCNUM>(0x04000208, 1);
- //analyze the OS irq flag variable
+ // analyze the OS irq flag variable
uint32_t intr = _MMU_read32<PROCNUM>(intrFlagAdr);
- uint32_t intrFlag = (cpu->R[1] & intr);
-
- //if the user requested us to discard flags, then clear the flag(s) we're going to be waiting on.
- //(be sure to only do this only on the first run through. use a little state machine to control that)
- if(cpu->intrWaitARM_state==0 && cpu->R[0]==1)
+ uint32_t intrFlag = cpu->R[1] & intr;
+
+ // if the user requested us to discard flags, then clear the flag(s) we're going to be waiting on.
+ // (be sure to only do this only on the first run through. use a little state machine to control that)
+ if (!cpu->intrWaitARM_state && cpu->R[0] == 1)
{
intr ^= intrFlag;
_MMU_write32<PROCNUM>(intrFlagAdr, intr);
- //we want to make sure we wait at least once below
+ // we want to make sure we wait at least once below
intrFlag = 0;
}
cpu->intrWaitARM_state = 1;
- //now, if the condition is satisfied (and it won't be the first time through, no matter what, due to cares taken above)
- if(intrFlag)
- {
- //write back the OS irq flags with the ones we were waiting for cleared
+ // now, if the condition is satisfied (and it won't be the first time through, no matter what, due to cares taken above)
+ if (intrFlag)
+ {
+ // write back the OS irq flags with the ones we were waiting for cleared
intr ^= intrFlag;
_MMU_write32<PROCNUM>(intrFlagAdr, intr);
@@ -261,12 +254,12 @@
return 1;
}
- //the condition wasn't satisfied. this means that we need to halt, wait for some enabled interrupt,
- //and then ensure that we return to this opcode again to check the condition again
+ // the condition wasn't satisfied. this means that we need to halt, wait for some enabled interrupt,
+ // and then ensure that we return to this opcode again to check the condition again
cpu->waitIRQ = true;
cpu->halt_IE_and_IF = true;
- //(rewire PC to jump back to this opcode)
+ // (rewire PC to jump back to this opcode)
uint32_t instructAddr = cpu->instruct_adr;
cpu->R[15] = instructAddr;
cpu->next_instruction = instructAddr;
@@ -288,713 +281,707 @@
TEMPLATE static uint32_t divide()
{
- int32_t num = (int32_t)cpu->R[0];
- int32_t dnum = (int32_t)cpu->R[1];
-
- if(dnum==0) return 0;
-
- int32_t res = num / dnum;
- cpu->R[0] = (uint32_t)res;
- cpu->R[1] = (uint32_t)(num % dnum);
- cpu->R[3] = (uint32_t)abs(res);
-
- //INFO("ARM%c: SWI 0x09 (divide): in num %i, dnum %i, out R0:%i, R1:%i, R3:%i\n", PROCNUM?'7':'9', num, dnum, cpu->R[0], cpu->R[1], cpu->R[3]);
-
- return 6;
+ int32_t num = static_cast<int32_t>(cpu->R[0]);
+ int32_t dnum = static_cast<int32_t>(cpu->R[1]);
+
+ if (!dnum)
+ return 0;
+
+ int32_t res = num / dnum;
+ cpu->R[0] = static_cast<uint32_t>(res);
+ cpu->R[1] = static_cast<uint32_t>(num % dnum);
+ cpu->R[3] = static_cast<uint32_t>(std::abs(res));
+
+ return 6;
}
TEMPLATE static uint32_t copy()
{
- uint32_t src = cpu->R[0];
- uint32_t dst = cpu->R[1];
- uint32_t cnt = cpu->R[2];
-
- //INFO("swi copy from %08X to %08X, cnt=%08X\n", src, dst, cnt);
-
- switch(BIT26(cnt))
- {
- case 0:
- src &= 0xFFFFFFFE;
- dst &= 0xFFFFFFFE;
- switch(BIT24(cnt))
- {
- case 0:
- cnt &= 0x1FFFFF;
- while(cnt)
- {
- _MMU_write16<PROCNUM>(dst, _MMU_read16<PROCNUM>(src));
- cnt--;
- dst+=2;
- src+=2;
- }
- break;
- case 1:
- {
- uint32_t val = _MMU_read16<PROCNUM>(src);
- cnt &= 0x1FFFFF;
- while(cnt)
- {
- _MMU_write16<PROCNUM>(dst, static_cast<uint16_t>(val));
- cnt--;
- dst+=2;
- }
- }
- break;
- }
- break;
- case 1:
- src &= 0xFFFFFFFC;
- dst &= 0xFFFFFFFC;
- switch(BIT24(cnt))
- {
- case 0:
- cnt &= 0x1FFFFF;
- while(cnt)
- {
- _MMU_write32<PROCNUM>(dst, _MMU_read32<PROCNUM>(src));
- cnt--;
- dst+=4;
- src+=4;
- }
- break;
- case 1:
- {
- uint32_t val = _MMU_read32<PROCNUM>(src);
- cnt &= 0x1FFFFF;
- while(cnt)
- {
- _MMU_write32<PROCNUM>(dst, val);
- cnt--;
- dst+=4;
- }
- }
- break;
- }
- break;
- }
- return 1;
+ uint32_t src = cpu->R[0];
+ uint32_t dst = cpu->R[1];
+ uint32_t cnt = cpu->R[2];
+
+ switch (BIT26(cnt))
+ {
+ case 0:
+ src &= 0xFFFFFFFE;
+ dst &= 0xFFFFFFFE;
+ switch (BIT24(cnt))
+ {
+ case 0:
+ cnt &= 0x1FFFFF;
+ while (cnt)
+ {
+ _MMU_write16<PROCNUM>(dst, _MMU_read16<PROCNUM>(src));
+ --cnt;
+ dst += 2;
+ src += 2;
+ }
+ break;
+ case 1:
+ {
+ uint16_t val = _MMU_read16<PROCNUM>(src);
+ cnt &= 0x1FFFFF;
+ while (cnt)
+ {
+ _MMU_write16<PROCNUM>(dst, static_cast<uint16_t>(val));
+ --cnt;
+ dst += 2;
+ }
+ break;
+ }
+ }
+ break;
+ case 1:
+ src &= 0xFFFFFFFC;
+ dst &= 0xFFFFFFFC;
+ switch (BIT24(cnt))
+ {
+ case 0:
+ cnt &= 0x1FFFFF;
+ while (cnt)
+ {
+ _MMU_write32<PROCNUM>(dst, _MMU_read32<PROCNUM>(src));
+ --cnt;
+ dst += 4;
+ src += 4;
+ }
+ break;
+ case 1:
+ {
+ uint32_t val = _MMU_read32<PROCNUM>(src);
+ cnt &= 0x1FFFFF;
+ while (cnt)
+ {
+ _MMU_write32<PROCNUM>(dst, val);
+ --cnt;
+ dst += 4;
+ }
+ break;
+ }
+ }
+ break;
+ }
+ return 1;
}
TEMPLATE static uint32_t fastCopy()
{
- uint32_t src = cpu->R[0] & 0xFFFFFFFC;
- uint32_t dst = cpu->R[1] & 0xFFFFFFFC;
- uint32_t cnt = cpu->R[2];
-
- //INFO("swi fastcopy from %08X to %08X, cnt=%08X\n", src, dst, cnt);
-
- switch(BIT24(cnt))
- {
- case 0:
- cnt &= 0x1FFFFF;
- while(cnt)
- {
- _MMU_write32<PROCNUM>(dst, _MMU_read32<PROCNUM>(src));
- cnt--;
- dst+=4;
- src+=4;
- }
- break;
- case 1:
- {
- uint32_t val = _MMU_read32<PROCNUM>(src);
- cnt &= 0x1FFFFF;
- while(cnt)
- {
- _MMU_write32<PROCNUM>(dst, val);
- cnt--;
- dst+=4;
- }
- }
- break;
- }
- return 1;
+ uint32_t src = cpu->R[0] & 0xFFFFFFFC;
+ uint32_t dst = cpu->R[1] & 0xFFFFFFFC;
+ uint32_t cnt = cpu->R[2];
+
+ switch (BIT24(cnt))
+ {
+ case 0:
+ cnt &= 0x1FFFFF;
+ while (cnt)
+ {
+ _MMU_write32<PROCNUM>(dst, _MMU_read32<PROCNUM>(src));
+ --cnt;
+ dst += 4;
+ src += 4;
+ }
+ break;
+ case 1:
+ {
+ uint32_t val = _MMU_read32<PROCNUM>(src);
+ cnt &= 0x1FFFFF;
+ while (cnt)
+ {
+ _MMU_write32<PROCNUM>(dst, val);
+ --cnt;
+ dst += 4;
+ }
+ break;
+ }
+ }
+ return 1;
}
TEMPLATE static uint32_t LZ77UnCompVram()
{
- int i1, i2;
- int byteCount;
- int byteShift;
- uint32_t writeValue;
- int len;
- uint32_t source = cpu->R[0];
- uint32_t dest = cpu->R[1];
- uint32_t header = _MMU_read32<PROCNUM>(source);
- source += 4;
-
- //INFO("swi lz77uncompvram\n");
-
- if(((source & 0xe000000) == 0) ||
- ((source + ((header >> 8) & 0x1fffff)) & 0xe000000) == 0)
- return 0;
-
- byteCount = 0;
- byteShift = 0;
- writeValue = 0;
-
- len = header >> 8;
-
- while(len > 0) {
- uint8_t d = _MMU_read08<PROCNUM>(source++);
-
- if(d) {
- for(i1 = 0; i1 < 8; i1++) {
- if(d & 0x80) {
- int length;
- int offset;
- uint32_t windowOffset;
- uint16_t data = _MMU_read08<PROCNUM>(source++) << 8;
- data |= _MMU_read08<PROCNUM>(source++);
- length = (data >> 12) + 3;
- offset = (data & 0x0FFF);
- windowOffset = dest + byteCount - offset - 1;
- for(i2 = 0; i2 < length; i2++) {
- writeValue |= (_MMU_read08<PROCNUM>(windowOffset++) << byteShift);
- byteShift += 8;
- byteCount++;
-
- if(byteCount == 2) {
- _MMU_write16<PROCNUM>(dest, static_cast<uint16_t>(writeValue));
- dest += 2;
- byteCount = 0;
- byteShift = 0;
- writeValue = 0;
- }
- len--;
- if(len == 0)
- return 0;
- }
- } else {
- writeValue |= (_MMU_read08<PROCNUM>(source++) << byteShift);
- byteShift += 8;
- byteCount++;
- if(byteCount == 2) {
- _MMU_write16<PROCNUM>(dest, static_cast<uint16_t>(writeValue));
- dest += 2;
- byteCount = 0;
- byteShift = 0;
- writeValue = 0;
- }
- len--;
- if(len == 0)
- return 0;
- }
- d <<= 1;
- }
- } else {
- for(i1 = 0; i1 < 8; i1++) {
- writeValue |= (_MMU_read08<PROCNUM>(source++) << byteShift);
- byteShift += 8;
- byteCount++;
- if(byteCount == 2) {
- _MMU_write16<PROCNUM>(dest, static_cast<uint16_t>(writeValue));
- dest += 2;
- byteShift = 0;
- byteCount = 0;
- writeValue = 0;
- }
- len--;
- if(len == 0)
- return 0;
- }
- }
- }
- return 1;
+ uint32_t source = cpu->R[0];
+ uint32_t dest = cpu->R[1];
+ uint32_t header = _MMU_read32<PROCNUM>(source);
+ source += 4;
+
+ if (!(source & 0xe000000) || !((source + ((header >> 8) & 0x1fffff)) & 0xe000000))
+ return 0;
+
+ int byteCount = 0;
+ int byteShift = 0;
+ uint32_t writeValue = 0;
+
+ int len = header >> 8;
+
+ while (len > 0)
+ {
+ uint8_t d = _MMU_read08<PROCNUM>(source++);
+
+ int i1, i2;
+ if (d)
+ {
+ for (i1 = 0; i1 < 8; ++i1)
+ {
+ if (d & 0x80)
+ {
+ uint16_t data = _MMU_read08<PROCNUM>(source++) << 8;
+ data |= _MMU_read08<PROCNUM>(source++);
+ int length = (data >> 12) + 3;
+ int offset = data & 0x0FFF;
+ uint32_t windowOffset = dest + byteCount - offset - 1;
+ for (i2 = 0; i2 < length; ++i2)
+ {
+ writeValue |= _MMU_read08<PROCNUM>(windowOffset++) << byteShift;
+ byteShift += 8;
+ ++byteCount;
+
+ if (byteCount == 2)
+ {
+ _MMU_write16<PROCNUM>(dest, static_cast<uint16_t>(writeValue));
+ dest += 2;
+ byteCount = 0;
+ byteShift = 0;
+ writeValue = 0;
+ }
+ --len;
+ if (!len)
+ return 0;
+ }
+ }
+ else
+ {
+ writeValue |= _MMU_read08<PROCNUM>(source++) << byteShift;
+ byteShift += 8;
+ ++byteCount;
+ if (byteCount == 2)
+ {
+ _MMU_write16<PROCNUM>(dest, static_cast<uint16_t>(writeValue));
+ dest += 2;
+ byteCount = 0;
+ byteShift = 0;
+ writeValue = 0;
+ }
+ --len;
+ if (!len)
+ return 0;
+ }
+ d <<= 1;
+ }
+ }
+ else
+ {
+ for (i1 = 0; i1 < 8; ++i1)
+ {
+ writeValue |= _MMU_read08<PROCNUM>(source++) << byteShift;
+ byteShift += 8;
+ ++byteCount;
+ if (byteCount == 2)
+ {
+ _MMU_write16<PROCNUM>(dest, static_cast<uint16_t>(writeValue));
+ dest += 2;
+ byteShift = 0;
+ byteCount = 0;
+ writeValue = 0;
+ }
+ --len;
+ if (!len)
+ return 0;
+ }
+ }
+ }
+ return 1;
}
TEMPLATE static uint32_t LZ77UnCompWram()
{
- int i1, i2;
- int len;
- uint32_t source = cpu->R[0];
- uint32_t dest = cpu->R[1];
-
- uint32_t header = _MMU_read32<PROCNUM>(source);
- source += 4;
-
- //INFO("swi lz77uncompwram\n");
-
- if(((source & 0xe000000) == 0) ||
- ((source + ((header >> 8) & 0x1fffff)) & 0xe000000) == 0)
- return 0;
-
- len = header >> 8;
-
- while(len > 0) {
- uint8_t d = _MMU_read08<PROCNUM>(source++);
-
- if(d) {
- for(i1 = 0; i1 < 8; i1++) {
- if(d & 0x80) {
- int length;
- int offset;
- uint32_t windowOffset;
- uint16_t data = _MMU_read08<PROCNUM>(source++) << 8;
- data |= _MMU_read08<PROCNUM>(source++);
- length = (data >> 12) + 3;
- offset = (data & 0x0FFF);
- windowOffset = dest - offset - 1;
- for(i2 = 0; i2 < length; i2++) {
- _MMU_write08<PROCNUM>(dest++, _MMU_read08<PROCNUM>(windowOffset++));
- len--;
- if(len == 0)
- return 0;
- }
- } else {
- _MMU_write08<PROCNUM>(dest++, _MMU_read08<PROCNUM>(source++));
- len--;
- if(len == 0)
- return 0;
- }
- d <<= 1;
- }
- } else {
- for(i1 = 0; i1 < 8; i1++) {
- _MMU_write08<PROCNUM>(dest++, _MMU_read08<PROCNUM>(source++));
- len--;
- if(len == 0)
- return 0;
- }
- }
- }
- return 1;
+ uint32_t source = cpu->R[0];
+ uint32_t dest = cpu->R[1];
+ uint32_t header = _MMU_read32<PROCNUM>(source);
+ source += 4;
+
+ if (!(source & 0xe000000) || !((source + ((header >> 8) & 0x1fffff)) & 0xe000000))
+ return 0;
+
+ int len = header >> 8;
+
+ while (len > 0)
+ {
+ uint8_t d = _MMU_read08<PROCNUM>(source++);
+
+ int i1, i2;
+ if (d)
+ {
+ for (i1 = 0; i1 < 8; ++i1)
+ {
+ if (d & 0x80)
+ {
+ uint16_t data = _MMU_read08<PROCNUM>(source++) << 8;
+ data |= _MMU_read08<PROCNUM>(source++);
+ int length = (data >> 12) + 3;
+ int offset = data & 0x0FFF;
+ uint32_t windowOffset = dest - offset - 1;
+ for (i2 = 0; i2 < length; ++i2)
+ {
+ _MMU_write08<PROCNUM>(dest++, _MMU_read08<PROCNUM>(windowOffset++));
+ --len;
+ if (!len)
+ return 0;
+ }
+ }
+ else
+ {
+ _MMU_write08<PROCNUM>(dest++, _MMU_read08<PROCNUM>(source++));
+ --len;
+ if (!len)
+ return 0;
+ }
+ d <<= 1;
+ }
+ }
+ else
+ {
+ for (i1 = 0; i1 < 8; ++i1)
+ {
+ _MMU_write08<PROCNUM>(dest++, _MMU_read08<PROCNUM>(source++));
+ --len;
+ if (!len)
+ return 0;
+ }
+ }
+ }
+ return 1;
}
TEMPLATE static uint32_t RLUnCompVram()
{
- int i;
- int len;
- int byteCount;
- int byteShift;
- uint32_t writeValue;
- uint32_t source = cpu->R[0];
- uint32_t dest = cpu->R[1];
-
- uint32_t header = _MMU_read32<PROCNUM>(source);
- source += 4;
-
- //INFO("swi rluncompvram\n");
-
- if(((source & 0xe000000) == 0) ||
- ((source + ((header >> 8) & 0x1fffff)) & 0xe000000) == 0)
- return 0;
-
- len = header >> 8;
- byteCount = 0;
- byteShift = 0;
- writeValue = 0;
-
- while(len > 0) {
- uint8_t d = _MMU_read08<PROCNUM>(source++);
- int l = d & 0x7F;
- if(d & 0x80) {
- uint8_t data = _MMU_read08<PROCNUM>(source++);
- l += 3;
- for(i = 0;i < l; i++) {
- writeValue |= (data << byteShift);
- byteShift += 8;
- byteCount++;
-
- if(byteCount == 2) {
- _MMU_write16<PROCNUM>(dest, static_cast<uint16_t>(writeValue));
- dest += 2;
- byteCount = 0;
- byteShift = 0;
- writeValue = 0;
- }
- len--;
- if(len == 0)
- return 0;
- }
- } else {
- l++;
- for(i = 0; i < l; i++) {
- writeValue |= (_MMU_read08<PROCNUM>(source++) << byteShift);
- byteShift += 8;
- byteCount++;
- if(byteCount == 2) {
- _MMU_write16<PROCNUM>(dest, static_cast<uint16_t>(writeValue));
- dest += 2;
- byteCount = 0;
- byteShift = 0;
- writeValue = 0;
- }
- len--;
- if(len == 0)
- return 0;
- }
- }
- }
- return 1;
+ uint32_t source = cpu->R[0];
+ uint32_t dest = cpu->R[1];
+ uint32_t header = _MMU_read32<PROCNUM>(source);
+ source += 4;
+
+ if (!(source & 0xe000000) || !((source + ((header >> 8) & 0x1fffff)) & 0xe000000))
+ return 0;
+
+ int len = header >> 8;
+ int byteCount = 0;
+ int byteShift = 0;
+ uint32_t writeValue = 0;
+
+ while (len > 0)
+ {
+ uint8_t d = _MMU_read08<PROCNUM>(source++);
+ int l = d & 0x7F;
+
+ int i;
+ if (d & 0x80)
+ {
+ uint8_t data = _MMU_read08<PROCNUM>(source++);
+ l += 3;
+ for (i = 0; i < l; ++i)
+ {
+ writeValue |= data << byteShift;
+ byteShift += 8;
+ ++byteCount;
+
+ if (byteCount == 2)
+ {
+ _MMU_write16<PROCNUM>(dest, static_cast<uint16_t>(writeValue));
+ dest += 2;
+ byteCount = 0;
+ byteShift = 0;
+ writeValue = 0;
+ }
+ --len;
+ if (!len)
+ return 0;
+ }
+ }
+ else
+ {
+ ++l;
+ for (i = 0; i < l; ++i)
+ {
+ writeValue |= _MMU_read08<PROCNUM>(source++) << byteShift;
+ byteShift += 8;
+ ++byteCount;
+
+ if (byteCount == 2)
+ {
+ _MMU_write16<PROCNUM>(dest, static_cast<uint16_t>(writeValue));
+ dest += 2;
+ byteCount = 0;
+ byteShift = 0;
+ writeValue = 0;
+ }
+ --len;
+ if (!len)
+ return 0;
+ }
+ }
+ }
+ return 1;
}
TEMPLATE static uint32_t RLUnCompWram()
{
- int i;
- int len;
- uint32_t source = cpu->R[0];
- uint32_t dest = cpu->R[1];
-
- uint32_t header = _MMU_read32<PROCNUM>(source);
- source += 4;
-
- //INFO("swi rluncompwram\n");
-
- if(((source & 0xe000000) == 0) ||
- ((source + ((header >> 8) & 0x1fffff)) & 0xe000000) == 0)
- return 0;
-
- len = header >> 8;
-
- while(len > 0) {
- uint8_t d = _MMU_read08<PROCNUM>(source++);
- int l = d & 0x7F;
- if(d & 0x80) {
- uint8_t data = _MMU_read08<PROCNUM>(source++);
- l += 3;
- for(i = 0;i < l; i++) {
- _MMU_write08<PROCNUM>(dest++, data);
- len--;
- if(len == 0)
- return 0;
- }
- } else {
- l++;
- for(i = 0; i < l; i++) {
- _MMU_write08<PROCNUM>(dest++, _MMU_read08<PROCNUM>(source++));
- len--;
- if(len == 0)
- return 0;
- }
- }
- }
- return 1;
+ uint32_t source = cpu->R[0];
+ uint32_t dest = cpu->R[1];
+ uint32_t header = _MMU_read32<PROCNUM>(source);
+ source += 4;
+
+ if (!(source & 0xe000000) || !((source + ((header >> 8) & 0x1fffff)) & 0xe000000))
+ return 0;
+
+ int len = header >> 8;
+
+ while (len > 0)
+ {
+ uint8_t d = _MMU_read08<PROCNUM>(source++);
+ int l = d & 0x7F;
+
+ int i;
+ if (d & 0x80)
+ {
+ uint8_t data = _MMU_read08<PROCNUM>(source++);
+ l += 3;
+ for (i = 0; i < l; ++i)
+ {
+ _MMU_write08<PROCNUM>(dest++, data);
+ --len;
+ if (!len)
+ return 0;
+ }
+ }
+ else
+ {
+ ++l;
+ for (i = 0; i < l; ++i)
+ {
+ _MMU_write08<PROCNUM>(dest++, _MMU_read08<PROCNUM>(source++));
+ --len;
+ if (!len)
+ return 0;
+ }
+ }
+ }
+ return 1;
}
TEMPLATE static uint32_t UnCompHuffman()
{
- uint32_t source, dest, writeValue, header, treeStart, mask;
- uint32_t data;
- uint8_t treeSize, currentNode, rootNode;
- int byteCount, byteShift, len, pos;
- int writeData;
-
- source = cpu->R[0];
- dest = cpu->R[1];
-
- header = _MMU_read08<PROCNUM>(source);
- source += 4;
-
- //INFO("swi uncomphuffman\n");
-
- if(((source & 0xe000000) == 0) ||
- ((source + ((header >> 8) & 0x1fffff)) & 0xe000000) == 0)
- return 0;
-
- treeSize = _MMU_read08<PROCNUM>(source++);
-
- treeStart = source;
-
- source += ((treeSize+1)<<1)-1; // minus because we already skipped one byte
-
- len = header >> 8;
-
- mask = 0x80000000;
- data = _MMU_read08<PROCNUM>(source);
- source += 4;
-
- pos = 0;
- rootNode = _MMU_read08<PROCNUM>(treeStart);
- currentNode = rootNode;
- writeData = 0;
- byteShift = 0;
- byteCount = 0;
- writeValue = 0;
-
- if((header & 0x0F) == 8) {
- while(len > 0) {
- // take left
- if(pos == 0)
- pos++;
- else
- pos += (((currentNode & 0x3F)+1)<<1);
-
- if(data & mask) {
- // right
- if(currentNode & 0x40)
- writeData = 1;
- currentNode = _MMU_read08<PROCNUM>(treeStart+pos+1);
- } else {
- // left
- if(currentNode & 0x80)
- writeData = 1;
- currentNode = _MMU_read08<PROCNUM>(treeStart+pos);
- }
-
- if(writeData) {
- writeValue |= (currentNode << byteShift);
- byteCount++;
- byteShift += 8;
-
- pos = 0;
- currentNode = rootNode;
- writeData = 0;
-
- if(byteCount == 4) {
- byteCount = 0;
- byteShift = 0;
- _MMU_write08<PROCNUM>(dest, static_cast<uint8_t>(writeValue));
- writeValue = 0;
- dest += 4;
- len -= 4;
- }
- }
- mask >>= 1;
- if(mask == 0) {
- mask = 0x80000000;
- data = _MMU_read08<PROCNUM>(source);
- source += 4;
- }
- }
- } else {
- int halfLen = 0;
- int value = 0;
- while(len > 0) {
- // take left
- if(pos == 0)
- pos++;
- else
- pos += (((currentNode & 0x3F)+1)<<1);
-
- if((data & mask)) {
- // right
- if(currentNode & 0x40)
- writeData = 1;
- currentNode = _MMU_read08<PROCNUM>(treeStart+pos+1);
- } else {
- // left
- if(currentNode & 0x80)
- writeData = 1;
- currentNode = _MMU_read08<PROCNUM>(treeStart+pos);
- }
-
- if(writeData) {
- if(halfLen == 0)
- value |= currentNode;
- else
- value |= (currentNode<<4);
-
- halfLen += 4;
- if(halfLen == 8) {
- writeValue |= (value << byteShift);
- byteCount++;
- byteShift += 8;
-
- halfLen = 0;
- value = 0;
-
- if(byteCount == 4) {
- byteCount = 0;
- byteShift = 0;
- _MMU_write08<PROCNUM>(dest, static_cast<uint8_t>(writeValue));
- dest += 4;
- writeValue = 0;
- len -= 4;
- }
- }
- pos = 0;
- currentNode = rootNode;
- writeData = 0;
- }
- mask >>= 1;
- if(mask == 0) {
- mask = 0x80000000;
- data = _MMU_read08<PROCNUM>(source);
- source += 4;
- }
- }
- }
- return 1;
+ uint32_t source = cpu->R[0];
+ uint32_t dest = cpu->R[1];
+ uint32_t header = _MMU_read08<PROCNUM>(source);
+ source += 4;
+
+ if (!(source & 0xe000000) || !((source + ((header >> 8) & 0x1fffff)) & 0xe000000))
+ return 0;
+
+ uint8_t treeSize = _MMU_read08<PROCNUM>(source++);
+
+ uint32_t treeStart = source;
+
+ source += ((treeSize + 1) << 1) - 1; // minus because we already skipped one byte
+
+ int len = header >> 8;
+
+ uint32_t mask = 0x80000000;
+ uint32_t data = _MMU_read08<PROCNUM>(source);
+ source += 4;
+
+ int pos = 0;
+ uint8_t rootNode = _MMU_read08<PROCNUM>(treeStart);
+ uint8_t currentNode = rootNode;
+ int writeData = 0;
+ int byteShift = 0;
+ int byteCount = 0;
+ uint32_t writeValue = 0;
+
+ if ((header & 0x0F) == 8)
+ {
+ while (len > 0)
+ {
+ // take left
+ if (!pos)
+ ++pos;
+ else
+ pos += ((currentNode & 0x3F) + 1) << 1;
+
+ if (data & mask)
+ {
+ // right
+ if (currentNode & 0x40)
+ writeData = 1;
+ currentNode = _MMU_read08<PROCNUM>(treeStart + pos + 1);
+ }
+ else
+ {
+ // left
+ if (currentNode & 0x80)
+ writeData = 1;
+ currentNode = _MMU_read08<PROCNUM>(treeStart + pos);
+ }
+
+ if (writeData)
+ {
+ writeValue |= currentNode << byteShift;
+ ++byteCount;
+ byteShift += 8;
+
+ pos = 0;
+ currentNode = rootNode;
+ writeData = 0;
+
+ if (byteCount == 4)
+ {
+ byteCount = 0;
+ byteShift = 0;
+ _MMU_write08<PROCNUM>(dest, static_cast<uint8_t>(writeValue));
+ writeValue = 0;
+ dest += 4;
+ len -= 4;
+ }
+ }
+ mask >>= 1;
+ if (!mask)
+ {
+ mask = 0x80000000;
+ data = _MMU_read08<PROCNUM>(source);
+ source += 4;
+ }
+ }
+ }
+ else
+ {
+ int halfLen = 0;
+ int value = 0;
+ while (len > 0)
+ {
+ // take left
+ if (!pos)
+ ++pos;
+ else
+ pos += ((currentNode & 0x3F) + 1) << 1;
+
+ if (data & mask)
+ {
+ // right
+ if (currentNode & 0x40)
+ writeData = 1;
+ currentNode = _MMU_read08<PROCNUM>(treeStart + pos + 1);
+ }
+ else
+ {
+ // left
+ if (currentNode & 0x80)
+ writeData = 1;
+ currentNode = _MMU_read08<PROCNUM>(treeStart + pos);
+ }
+
+ if (writeData)
+ {
+ if (!halfLen)
+ value |= currentNode;
+ else
+ value |= currentNode << 4;
+
+ halfLen += 4;
+ if (halfLen == 8)
+ {
+ writeValue |= value << byteShift;
+ ++byteCount;
+ byteShift += 8;
+
+ halfLen = 0;
+ value = 0;
+
+ if (byteCount == 4)
+ {
+ byteCount = 0;
+ byteShift = 0;
+ _MMU_write08<PROCNUM>(dest, static_cast<uint8_t>(writeValue));
+ dest += 4;
+ writeValue = 0;
+ len -= 4;
+ }
+ }
+ pos = 0;
+ currentNode = rootNode;
+ writeData = 0;
+ }
+ mask >>= 1;
+ if (!mask)
+ {
+ mask = 0x80000000;
+ data = _MMU_read08<PROCNUM>(source);
+ source += 4;
+ }
+ }
+ }
+ return 1;
}
TEMPLATE static uint32_t BitUnPack()
{
- uint32_t source,dest,header,base,d,temp;
- int len,bits,revbits,dataSize,data,bitwritecount,mask,bitcount,addBase;
- uint8_t b;
-
- source = cpu->R[0];
- dest = cpu->R[1];
- header = cpu->R[2];
-
- len = _MMU_read16<PROCNUM>(header);
- bits = _MMU_read08<PROCNUM>(header+2);
- switch (bits)
- {
- case 1:
- case 2:
- case 4:
- case 8:
- break;
- default: return 0; // error
- }
- dataSize = _MMU_read08<PROCNUM>(header+3);
- switch (dataSize)
- {
- case 1:
- case 2:
- case 4:
- case 8:
- case 16:
- case 32:
- break;
- default: return 0; // error
- }
-
- revbits = 8 - bits;
- // uint32_t value = 0;
- base = _MMU_read08<PROCNUM>(header+4);
- addBase = (base & 0x80000000) ? 1 : 0;
- base &= 0x7fffffff;
-
- //INFO("SWI10: bitunpack src 0x%08X dst 0x%08X hdr 0x%08X (src len %05i src bits %02i dst bits %02i)\n\n", source, dest, header, len, bits, dataSize);
-
- data = 0;
- bitwritecount = 0;
- while(1) {
- len -= 1;
- if(len < 0)
- break;
- mask = 0xff >> revbits;
- b = _MMU_read08<PROCNUM>(source);
- source++;
- bitcount = 0;
- while(1) {
- if(bitcount >= 8)
- break;
- d = b & mask;
- temp = d >> bitcount;
- if(!temp && addBase) {
- temp += base;
- }
- data |= temp << bitwritecount;
- bitwritecount += dataSize;
- if(bitwritecount >= 32) {
- _MMU_write08<PROCNUM>(dest, data);
- dest += 4;
- data = 0;
- bitwritecount = 0;
- }
- mask <<= bits;
- bitcount += bits;
- }
- }
- return 1;
+ uint32_t source = cpu->R[0];
+ uint32_t dest = cpu->R[1];
+ uint32_t header = cpu->R[2];
+
+ int len = _MMU_read16<PROCNUM>(header);
+ int bits = _MMU_read08<PROCNUM>(header + 2);
+ switch (bits)
+ {
+ case 1:
+ case 2:
+ case 4:
+ case 8:
+ break;
+ default:
+ return 0; // error
+ }
+ int dataSize = _MMU_read08<PROCNUM>(header + 3);
+ switch (dataSize)
+ {
+ case 1:
+ case 2:
+ case 4:
+ case 8:
+ case 16:
+ case 32:
+ break;
+ default:
+ return 0; // error
+ }
+
+ int revbits = 8 - bits;
+ uint32_t base = _MMU_read08<PROCNUM>(header + 4);
+ int addBase = base & 0x80000000 ? 1 : 0;
+ base &= 0x7fffffff;
+
+ int data = 0;
+ int bitwritecount = 0;
+ while (1)
+ {
+ len -= 1;
+ if (len < 0)
+ break;
+ int mask = 0xff >> revbits;
+ uint8_t b = _MMU_read08<PROCNUM>(source);
+ ++source;
+ int bitcount = 0;
+ while (1)
+ {
+ if (bitcount >= 8)
+ break;
+ uint32_t d = b & mask;
+ uint32_t temp = d >> bitcount;
+ if (!temp && addBase)
+ temp += base;
+ data |= temp << bitwritecount;
+ bitwritecount += dataSize;
+ if (bitwritecount >= 32)
+ {
+ _MMU_write08<PROCNUM>(dest, data);
+ dest += 4;
+ data = 0;
+ bitwritecount = 0;
+ }
+ mask <<= bits;
+ bitcount += bits;
+ }
+ }
+ return 1;
}
TEMPLATE static uint32_t Diff8bitUnFilterWram()
{
- uint32_t source,dest,header;
- uint8_t data,diff;
- int len;
-
- source = cpu->R[0];
- dest = cpu->R[1];
-
- header = _MMU_read08<PROCNUM>(source);
- source += 4;
-
- //INFO("swi diff8bitunfilterwram\n");
-
- if(((source & 0xe000000) == 0) ||
- (( (source + ((header >> 8) & 0x1fffff)) & 0xe000000) == 0))
- return 0;
-
- len = header >> 8;
-
- data = _MMU_read08<PROCNUM>(source++);
- _MMU_write08<PROCNUM>(dest++, data);
- len--;
-
- while(len > 0) {
- diff = _MMU_read08<PROCNUM>(source++);
- data += diff;
- _MMU_write08<PROCNUM>(dest++, data);
- len--;
- }
- return 1;
+ uint32_t source = cpu->R[0];
+ uint32_t dest = cpu->R[1];
+ uint32_t header = _MMU_read08<PROCNUM>(source);
+ source += 4;
+
+ if (!(source & 0xe000000) || !((source + ((header >> 8) & 0x1fffff)) & 0xe000000))
+ return 0;
+
+ int len = header >> 8;
+
+ uint8_t data = _MMU_read08<PROCNUM>(source++);
+ _MMU_write08<PROCNUM>(dest++, data);
+ --len;
+
+ while (len > 0)
+ {
+ uint8_t diff = _MMU_read08<PROCNUM>(source++);
+ data += diff;
+ _MMU_write08<PROCNUM>(dest++, data);
+ --len;
+ }
+ return 1;
}
TEMPLATE static uint32_t Diff16bitUnFilter()
{
- uint32_t source,dest,header;
- uint16_t data;
- int len;
-
- source = cpu->R[0];
- dest = cpu->R[1];
-
- //INFO("swi diff16bitunfilter\n");
-
- header = _MMU_read08<PROCNUM>(source);
- source += 4;
-
- if(((source & 0xe000000) == 0) ||
- ((source + ((header >> 8) & 0x1fffff)) & 0xe000000) == 0)
- return 0;
-
- len = header >> 8;
-
- data = _MMU_read16<PROCNUM>(source);
- source += 2;
- _MMU_write16<PROCNUM>(dest, data);
- dest += 2;
- len -= 2;
-
- while(len >= 2) {
- uint16_t diff = _MMU_read16<PROCNUM>(source);
- source += 2;
- data += diff;
- _MMU_write16<PROCNUM>(dest, data);
- dest += 2;
- len -= 2;
- }
- return 1;
+ uint32_t source = cpu->R[0];
+ uint32_t dest = cpu->R[1];
+ uint32_t header = _MMU_read08<PROCNUM>(source);
+ source += 4;
+
+ if (!(source & 0xe000000) || !((source + ((header >> 8) & 0x1fffff)) & 0xe000000))
+ return 0;
+
+ int len = header >> 8;
+
+ uint16_t data = _MMU_read16<PROCNUM>(source);
+ source += 2;
+ _MMU_write16<PROCNUM>(dest, data);
+ dest += 2;
+ len -= 2;
+
+ while (len >= 2)
+ {
+ uint16_t diff = _MMU_read16<PROCNUM>(source);
+ source += 2;
+ data += diff;
+ _MMU_write16<PROCNUM>(dest, data);
+ dest += 2;
+ len -= 2;
+ }
+ return 1;
}
TEMPLATE static uint32_t bios_sqrt()
{
- cpu->R[0] = (uint32_t)sqrt((double)(cpu->R[0]));
- return 1;
+ cpu->R[0] = static_cast<uint32_t>(std::sqrt(static_cast<double>(cpu->R[0])));
+ return 1;
}
TEMPLATE static uint32_t setHaltCR()
{
- _MMU_write08<PROCNUM>(0x4000300+cpu->proc_ID, static_cast<uint8_t>(cpu->R[0]));
- return 1;
+ _MMU_write08<PROCNUM>(0x4000300+cpu->proc_ID, static_cast<uint8_t>(cpu->R[0]));
+ return 1;
}
TEMPLATE static uint32_t getSineTab()
{
- //ds returns garbage according to gbatek, but we must protect ourselves
- if(cpu->R[0] >= ARRAY_SIZE(getsinetbl))
- {
- printf("Invalid SWI getSineTab: %08X\n",cpu->R[0]);
+ // ds returns garbage according to gbatek, but we must protect ourselves
+ if (cpu->R[0] >= ARRAY_SIZE(getsinetbl))
+ {
+ printf("Invalid SWI getSineTab: %08X\n", cpu->R[0]);
return 1;
}
-
cpu->R[0] = getsinetbl[cpu->R[0]];
return 1;
}
TEMPLATE static uint32_t getPitchTab()
{
- //ds returns garbage according to gbatek, but we must protect ourselves
- if(cpu->R[0] >= ARRAY_SIZE(getpitchtbl))
- {
- printf("Invalid SWI getPitchTab: %08X\n",cpu->R[0]);
+ // ds returns garbage according to gbatek, but we must protect ourselves
+ if (cpu->R[0] >= ARRAY_SIZE(getpitchtbl))
+ {
+ printf("Invalid SWI getPitchTab: %08X\n", cpu->R[0]);
return 1;
}
@@ -1004,73 +991,44 @@
TEMPLATE static uint32_t getVolumeTab()
{
- //ds returns garbage according to gbatek, but we must protect ourselves
- if(cpu->R[0] >= ARRAY_SIZE(getvoltbl))
- {
- printf("Invalid SWI getVolumeTab: %08X\n",cpu->R[0]);
+ // ds returns garbage according to gbatek, but we must protect ourselves
+ if (cpu->R[0] >= ARRAY_SIZE(getvoltbl))
+ {
+ printf("Invalid SWI getVolumeTab: %08X\n", cpu->R[0]);
return 1;
}
-
- cpu->R[0] = getvoltbl[cpu->R[0]];
- return 1;
-}
-
-
-//TEMPLATE static uint32_t getCRC16_old(uint32_t crc, uint32_t datap, uint32_t size)
-//{
-// unsigned int i,j;
-//
-// const uint16_t val[] = { 0xC0C1,0xC181,0xC301,0xC601,0xCC01,0xD801,0xF001,0xA001 };
-// for(i = 0; i < size; i++)
-// {
-// crc = crc ^ _MMU_read08<PROCNUM>(datap + i);
-//
-// for(j = 0; j < 8; j++) {
-// int do_bit = 0;
-//
-// if ( crc & 0x1)
-// do_bit = 1;
-//
-// crc = crc >> 1;
-//
-// if ( do_bit) {
-// crc = crc ^ (val[j] << (7-j));
-// }
-// }
-// }
-// return crc;
-//}
+ cpu->R[0] = getvoltbl[cpu->R[0]];
+ return 1;
+}
TEMPLATE static uint32_t getCRC16()
{
- //gbatek is wrong.
-
- //dawn of sorrow uses this to checksum its save data;
- //if this implementation is wrong, then it won't match what the real bios returns,
- //and savefiles created with a bios will be invalid when loaded with non-bios (and vice-versa)
-
- //uint32_t old = getCRC16_old<PROCNUM>(cpu->R[0],cpu->R[1],cpu->R[2]);
-
- uint16_t crc = (uint16_t)cpu->R[0];
+ // gbatek is wrong.
+
+ // dawn of sorrow uses this to checksum its save data;
+ // if this implementation is wrong, then it won't match what the real bios returns,
+ // and savefiles created with a bios will be invalid when loaded with non-bios (and vice-versa)
+
+ uint16_t crc = static_cast<uint16_t>(cpu->R[0]);
uint32_t datap = cpu->R[1];
- uint32_t size = cpu->R[2]>>1;
+ uint32_t size = cpu->R[2] >> 1;
uint16_t currVal = 0;
- const uint16_t val[] = { 0x0000,0xCC01,0xD801,0x1400,0xF001,0x3C00,0x2800,0xE401,0xA001,0x6C00,0x7800,0xB401,0x5000,0x9C01,0x8801,0x4400};
-
- for(uint32_t i = 0; i < size; i++)
- {
- currVal = _MMU_read16<PROCNUM>(datap + i*2);
-
- for(int j=0;j<4;j++)
- {
- uint16_t tabVal = val[crc&0xF];
+ const uint16_t val[] = { 0x0000, 0xCC01, 0xD801, 0x1400, 0xF001, 0x3C00, 0x2800, 0xE401, 0xA001, 0x6C00, 0x7800, 0xB401, 0x5000, 0x9C01, 0x8801, 0x4400 };
+
+ for (uint32_t i = 0; i < size; ++i)
+ {
+ currVal = _MMU_read16<PROCNUM>(datap + i * 2);
+
+ for (int j = 0; j < 4; ++j)
+ {
+ uint16_t tabVal = val[crc & 0xF];
crc >>= 4;
crc ^= tabVal;
- uint16_t tempVal = currVal >> (4*j);
- tabVal = val[tempVal&0xF];
+ uint16_t tempVal = currVal >> (4 * j);
+ tabVal = val[tempVal & 0xF];
crc ^= tabVal;
}
}
@@ -1082,23 +1040,19 @@
TEMPLATE static uint32_t isDebugger()
{
- //gbatek has additional specifications which are not emulated here
-/*#ifdef DEVELOPER
- cpu->R[0] = 1;
-#else*/
+ // gbatek has additional specifications which are not emulated here
cpu->R[0] = 0;
-//#endif
return 1;
}
TEMPLATE static uint32_t SoundBias()
{
- uint32_t curBias = _MMU_read32<ARMCPU_ARM7>(0x04000504);
- uint32_t newBias = (curBias == 0) ? 0x000:0x200;
- uint32_t delay = (newBias > curBias) ? (newBias-curBias) : (curBias-newBias);
-
- _MMU_write32<ARMCPU_ARM7>(0x04000504, newBias);
- return cpu->R[1] * delay;
+ uint32_t curBias = _MMU_read32<ARMCPU_ARM7>(0x04000504);
+ uint32_t newBias = !curBias ? 0x000:0x200;
+ uint32_t delay = newBias > curBias ? newBias - curBias : curBias - newBias;
+
+ _MMU_write32<ARMCPU_ARM7>(0x04000504, newBias);
+ return cpu->R[1] * delay;
}
TEMPLATE static uint32_t getBootProcs()
@@ -1109,73 +1063,75 @@
return 1;
}
-uint32_t (* ARM9_swi_tab[32])()={
- bios_nop<ARMCPU_ARM9>, // 0x00
- bios_nop<ARMCPU_ARM9>, // 0x01
- bios_nop<ARMCPU_ARM9>, // 0x02
- WaitByLoop<ARMCPU_ARM9>, // 0x03
- intrWaitARM<ARMCPU_ARM9>, // 0x04
- waitVBlankARM<ARMCPU_ARM9>, // 0x05
- wait4IRQ<ARMCPU_ARM9>, // 0x06
- bios_nop<ARMCPU_ARM9>, // 0x07
- bios_nop<ARMCPU_ARM9>, // 0x08
- divide<ARMCPU_ARM9>, // 0x09
- bios_nop<ARMCPU_ARM9>, // 0x0A
- copy<ARMCPU_ARM9>, // 0x0B
- fastCopy<ARMCPU_ARM9>, // 0x0C
- bios_sqrt<ARMCPU_ARM9>, // 0x0D
- getCRC16<ARMCPU_ARM9>, // 0x0E
- isDebugger<ARMCPU_ARM9>, // 0x0F
- BitUnPack<ARMCPU_ARM9>, // 0x10
- LZ77UnCompWram<ARMCPU_ARM9>, // 0x11
- LZ77UnCompVram<ARMCPU_ARM9>, // 0x12
- UnCompHuffman<ARMCPU_ARM9>, // 0x13
- RLUnCompWram<ARMCPU_ARM9>, // 0x14
- RLUnCompVram<ARMCPU_ARM9>, // 0x15
- Diff8bitUnFilterWram<ARMCPU_ARM9>, // 0x16
- bios_nop<ARMCPU_ARM9>, // 0x17
- Diff16bitUnFilter<ARMCPU_ARM9>, // 0x18
- bios_nop<ARMCPU_ARM9>, // 0x19
- bios_nop<ARMCPU_ARM9>, // 0x1A
- bios_nop<ARMCPU_ARM9>, // 0x1B
- bios_nop<ARMCPU_ARM9>, // 0x1C
- bios_nop<ARMCPU_ARM9>, // 0x1D
- bios_nop<ARMCPU_ARM9>, // 0x1E
- setHaltCR<ARMCPU_ARM9>, // 0x1F
+uint32_t (*ARM_swi_tab[][32])() =
+{
+ {
+ bios_nop<ARMCPU_ARM9>, // 0x00
+ bios_nop<ARMCPU_ARM9>, // 0x01
+ bios_nop<ARMCPU_ARM9>, // 0x02
+ WaitByLoop<ARMCPU_ARM9>, // 0x03
+ intrWaitARM<ARMCPU_ARM9>, // 0x04
+ waitVBlankARM<ARMCPU_ARM9>, // 0x05
+ wait4IRQ<ARMCPU_ARM9>, // 0x06
+ bios_nop<ARMCPU_ARM9>, // 0x07
+ bios_nop<ARMCPU_ARM9>, // 0x08
+ divide<ARMCPU_ARM9>, // 0x09
+ bios_nop<ARMCPU_ARM9>, // 0x0A
+ copy<ARMCPU_ARM9>, // 0x0B
+ fastCopy<ARMCPU_ARM9>, // 0x0C
+ bios_sqrt<ARMCPU_ARM9>, // 0x0D
+ getCRC16<ARMCPU_ARM9>, // 0x0E
+ isDebugger<ARMCPU_ARM9>, // 0x0F
+ BitUnPack<ARMCPU_ARM9>, // 0x10
+ LZ77UnCompWram<ARMCPU_ARM9>, // 0x11
+ LZ77UnCompVram<ARMCPU_ARM9>, // 0x12
+ UnCompHuffman<ARMCPU_ARM9>, // 0x13
+ RLUnCompWram<ARMCPU_ARM9>, // 0x14
+ RLUnCompVram<ARMCPU_ARM9>, // 0x15
+ Diff8bitUnFilterWram<ARMCPU_ARM9>, // 0x16
+ bios_nop<ARMCPU_ARM9>, // 0x17
+ Diff16bitUnFilter<ARMCPU_ARM9>, // 0x18
+ bios_nop<ARMCPU_ARM9>, // 0x19
+ bios_nop<ARMCPU_ARM9>, // 0x1A
+ bios_nop<ARMCPU_ARM9>, // 0x1B
+ bios_nop<ARMCPU_ARM9>, // 0x1C
+ bios_nop<ARMCPU_ARM9>, // 0x1D
+ bios_nop<ARMCPU_ARM9>, // 0x1E
+ setHaltCR<ARMCPU_ARM9>, // 0x1F
+ },
+ {
+ bios_nop<ARMCPU_ARM7>, // 0x00
+ bios_nop<ARMCPU_ARM7>, // 0x01
+ bios_nop<ARMCPU_ARM7>, // 0x02
+ WaitByLoop<ARMCPU_ARM7>, // 0x03
+ intrWaitARM<ARMCPU_ARM7>, // 0x04
+ waitVBlankARM<ARMCPU_ARM7>, // 0x05
+ wait4IRQ<ARMCPU_ARM7>, // 0x06
+ sleep<ARMCPU_ARM7>, // 0x07
+ SoundBias<ARMCPU_ARM7>, // 0x08
+ divide<ARMCPU_ARM7>, // 0x09
+ bios_nop<ARMCPU_ARM7>, // 0x0A
+ copy<ARMCPU_ARM7>, // 0x0B
+ fastCopy<ARMCPU_ARM7>, // 0x0C
+ bios_sqrt<ARMCPU_ARM7>, // 0x0D
+ getCRC16<ARMCPU_ARM7>, // 0x0E
+ isDebugger<ARMCPU_ARM7>, // 0x0F
+ BitUnPack<ARMCPU_ARM7>, // 0x10
+ LZ77UnCompWram<ARMCPU_ARM7>, // 0x11
+ LZ77UnCompVram<ARMCPU_ARM7>, // 0x12
+ UnCompHuffman<ARMCPU_ARM7>, // 0x13
+ RLUnCompWram<ARMCPU_ARM7>, // 0x14
+ RLUnCompVram<ARMCPU_ARM7>, // 0x15
+ Diff8bitUnFilterWram<ARMCPU_ARM7>, // 0x16
+ bios_nop<ARMCPU_ARM7>, // 0x17
+ bios_nop<ARMCPU_ARM7>, // 0x18
+ bios_nop<ARMCPU_ARM7>, // 0x19
+ getSineTab<ARMCPU_ARM7>, // 0x1A
+ getPitchTab<ARMCPU_ARM7>, // 0x1B
+ getVolumeTab<ARMCPU_ARM7>, // 0x1C
+ getBootProcs<ARMCPU_ARM7>, // 0x1D
+ bios_nop<ARMCPU_ARM7>, // 0x1E
+ setHaltCR<ARMCPU_ARM7>, // 0x1F
+ }
};
-uint32_t (* ARM7_swi_tab[32])()={
- bios_nop<ARMCPU_ARM7>, // 0x00
- bios_nop<ARMCPU_ARM7>, // 0x01
- bios_nop<ARMCPU_ARM7>, // 0x02
- WaitByLoop<ARMCPU_ARM7>, // 0x03
- intrWaitARM<ARMCPU_ARM7>, // 0x04
- waitVBlankARM<ARMCPU_ARM7>, // 0x05
- wait4IRQ<ARMCPU_ARM7>, // 0x06
- sleep<ARMCPU_ARM7>, // 0x07
- SoundBias<ARMCPU_ARM7>, // 0x08
- divide<ARMCPU_ARM7>, // 0x09
- bios_nop<ARMCPU_ARM7>, // 0x0A
- copy<ARMCPU_ARM7>, // 0x0B
- fastCopy<ARMCPU_ARM7>, // 0x0C
- bios_sqrt<ARMCPU_ARM7>, // 0x0D
- getCRC16<ARMCPU_ARM7>, // 0x0E
- isDebugger<ARMCPU_ARM7>, // 0x0F
- BitUnPack<ARMCPU_ARM7>, // 0x10
- LZ77UnCompWram<ARMCPU_ARM7>, // 0x11
- LZ77UnCompVram<ARMCPU_ARM7>, // 0x12
- UnCompHuffman<ARMCPU_ARM7>, // 0x13
- RLUnCompWram<ARMCPU_ARM7>, // 0x14
- RLUnCompVram<ARMCPU_ARM7>, // 0x15
- Diff8bitUnFilterWram<ARMCPU_ARM7>, // 0x16
- bios_nop<ARMCPU_ARM7>, // 0x17
- bios_nop<ARMCPU_ARM7>, // 0x18
- bios_nop<ARMCPU_ARM7>, // 0x19
- getSineTab<ARMCPU_ARM7>, // 0x1A
- getPitchTab<ARMCPU_ARM7>, // 0x1B
- getVolumeTab<ARMCPU_ARM7>, // 0x1C
- getBootProcs<ARMCPU_ARM7>, // 0x1D
- bios_nop<ARMCPU_ARM7>, // 0x1E
- setHaltCR<ARMCPU_ARM7>, // 0x1F
-};
-
--- a/src/in_2sf/desmume/bios.h
+++ b/src/in_2sf/desmume/bios.h
@@ -1,6 +1,6 @@
/*
Copyright (C) 2006 yopyop
- Copyright (C) 2006-2009 DeSmuME team
+ Copyright (C) 2006-2012 DeSmuME team
This file is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -21,8 +21,7 @@
#include "armcpu.h"
-extern uint32_t (*ARM9_swi_tab[32])();
-extern uint32_t (*ARM7_swi_tab[32])();
+extern uint32_t (*ARM_swi_tab[2][32])();
#endif
--- a/src/in_2sf/desmume/bits.h
+++ b/src/in_2sf/desmume/bits.h
@@ -1,45 +1,45 @@
#ifndef BITS_H
#define BITS_H
-static inline uint32_t BIT(uint32_t n) { return 1 << n; }
+inline uint32_t BIT(uint32_t n) { return 1 << n; }
-static inline uint32_t BIT_N(uint32_t i, uint32_t n) { return (i >> n) & 1; }
-static inline uint32_t BIT0(uint32_t i) { return i & 1; }
-static inline uint32_t BIT1(uint32_t i) { return BIT_N(i, 1); }
-static inline uint32_t BIT2(uint32_t i) { return BIT_N(i, 2); }
-static inline uint32_t BIT3(uint32_t i) { return BIT_N(i, 3); }
-static inline uint32_t BIT4(uint32_t i) { return BIT_N(i, 4); }
-static inline uint32_t BIT5(uint32_t i) { return BIT_N(i, 5); }
-static inline uint32_t BIT6(uint32_t i) { return BIT_N(i, 6); }
-static inline uint32_t BIT7(uint32_t i) { return BIT_N(i, 7); }
-static inline uint32_t BIT8(uint32_t i) { return BIT_N(i, 8); }
-static inline uint32_t BIT9(uint32_t i) { return BIT_N(i, 9); }
-static inline uint32_t BIT10(uint32_t i) { return BIT_N(i, 10); }
-static inline uint32_t BIT11(uint32_t i) { return BIT_N(i, 11); }
-static inline uint32_t BIT12(uint32_t i) { return BIT_N(i, 12); }
-static inline uint32_t BIT13(uint32_t i) { return BIT_N(i, 13); }
-static inline uint32_t BIT14(uint32_t i) { return BIT_N(i, 14); }
-static inline uint32_t BIT15(uint32_t i) { return BIT_N(i, 15); }
-static inline uint32_t BIT16(uint32_t i) { return BIT_N(i, 16); }
-static inline uint32_t BIT17(uint32_t i) { return BIT_N(i, 17); }
-static inline uint32_t BIT18(uint32_t i) { return BIT_N(i, 18); }
-static inline uint32_t BIT19(uint32_t i) { return BIT_N(i, 19); }
-static inline uint32_t BIT20(uint32_t i) { return BIT_N(i, 20); }
-static inline uint32_t BIT21(uint32_t i) { return BIT_N(i, 21); }
-static inline uint32_t BIT22(uint32_t i) { return BIT_N(i, 22); }
-static inline uint32_t BIT23(uint32_t i) { return BIT_N(i, 23); }
-static inline uint32_t BIT24(uint32_t i) { return BIT_N(i, 24); }
-static inline uint32_t BIT25(uint32_t i) { return BIT_N(i, 25); }
-static inline uint32_t BIT26(uint32_t i) { return BIT_N(i, 26); }
-static inline uint32_t BIT27(uint32_t i) { return BIT_N(i, 27); }
-static inline uint32_t BIT28(uint32_t i) { return BIT_N(i, 28); }
-static inline uint32_t BIT29(uint32_t i) { return BIT_N(i, 29); }
-static inline uint32_t BIT30(uint32_t i) { return BIT_N(i, 30); }
-static inline uint32_t BIT31(uint32_t i) { return i >> 31; }
+inline uint32_t BIT_N(uint32_t i, uint32_t n) { return (i >> n) & 1; }
+inline uint32_t BIT0(uint32_t i) { return i & 1; }
+inline uint32_t BIT1(uint32_t i) { return BIT_N(i, 1); }
+inline uint32_t BIT2(uint32_t i) { return BIT_N(i, 2); }
+inline uint32_t BIT3(uint32_t i) { return BIT_N(i, 3); }
+inline uint32_t BIT4(uint32_t i) { return BIT_N(i, 4); }
+inline uint32_t BIT5(uint32_t i) { return BIT_N(i, 5); }
+inline uint32_t BIT6(uint32_t i) { return BIT_N(i, 6); }
+inline uint32_t BIT7(uint32_t i) { return BIT_N(i, 7); }
+inline uint32_t BIT8(uint32_t i) { return BIT_N(i, 8); }
+inline uint32_t BIT9(uint32_t i) { return BIT_N(i, 9); }
+inline uint32_t BIT10(uint32_t i) { return BIT_N(i, 10); }
+inline uint32_t BIT11(uint32_t i) { return BIT_N(i, 11); }
+inline uint32_t BIT12(uint32_t i) { return BIT_N(i, 12); }
+inline uint32_t BIT13(uint32_t i) { return BIT_N(i, 13); }
+inline uint32_t BIT14(uint32_t i) { return BIT_N(i, 14); }
+inline uint32_t BIT15(uint32_t i) { return BIT_N(i, 15); }
+inline uint32_t BIT16(uint32_t i) { return BIT_N(i, 16); }
+inline uint32_t BIT17(uint32_t i) { return BIT_N(i, 17); }
+inline uint32_t BIT18(uint32_t i) { return BIT_N(i, 18); }
+inline uint32_t BIT19(uint32_t i) { return BIT_N(i, 19); }
+inline uint32_t BIT20(uint32_t i) { return BIT_N(i, 20); }
+inline uint32_t BIT21(uint32_t i) { return BIT_N(i, 21); }
+inline uint32_t BIT22(uint32_t i) { return BIT_N(i, 22); }
+inline uint32_t BIT23(uint32_t i) { return BIT_N(i, 23); }
+inline uint32_t BIT24(uint32_t i) { return BIT_N(i, 24); }
+inline uint32_t BIT25(uint32_t i) { return BIT_N(i, 25); }
+inline uint32_t BIT26(uint32_t i) { return BIT_N(i, 26); }
+inline uint32_t BIT27(uint32_t i) { return BIT_N(i, 27); }
+inline uint32_t BIT28(uint32_t i) { return BIT_N(i, 28); }
+inline uint32_t BIT29(uint32_t i) { return BIT_N(i, 29); }
+inline uint32_t BIT30(uint32_t i) { return BIT_N(i, 30); }
+inline uint32_t BIT31(uint32_t i) { return i >> 31; }
-static inline uint32_t CONDITION(uint32_t i) { return i >> 28; }
+inline uint32_t CONDITION(uint32_t i) { return i >> 28; }
-static inline uint32_t REG_POS(uint32_t i, uint32_t n) { return (i >> n) & 0xF; }
+inline uint32_t REG_POS(uint32_t i, uint32_t n) { return (i >> n) & 0xF; }
#endif
--- a/src/in_2sf/desmume/common.cpp
+++ /dev/null
@@ -1,68 +1,1 @@
-/*
- Copyright (C) 2008-2010 DeSmuME team
- This file is free software: you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation, either version 2 of the License, or
- (at your option) any later version.
-
- This file is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with the this software. If not, see <http://www.gnu.org/licenses/>.
-*/
-
-//TODO - move this into ndssystem where it belongs probably
-
-#include <string>
-#include <cstring>
-
-#include "common.h"
-
-const uint8_t logo_data[156] = {
- 0x24,0xFF,0xAE,0x51,0x69,0x9A,0xA2,0x21,0x3D,0x84,0x82,0x0A,0x84,0xE4,0x09,0xAD,
- 0x11,0x24,0x8B,0x98,0xC0,0x81,0x7F,0x21,0xA3,0x52,0xBE,0x19,0x93,0x09,0xCE,0x20,
- 0x10,0x46,0x4A,0x4A,0xF8,0x27,0x31,0xEC,0x58,0xC7,0xE8,0x33,0x82,0xE3,0xCE,0xBF,
- 0x85,0xF4,0xDF,0x94,0xCE,0x4B,0x09,0xC1,0x94,0x56,0x8A,0xC0,0x13,0x72,0xA7,0xFC,
- 0x9F,0x84,0x4D,0x73,0xA3,0xCA,0x9A,0x61,0x58,0x97,0xA3,0x27,0xFC,0x03,0x98,0x76,
- 0x23,0x1D,0xC7,0x61,0x03,0x04,0xAE,0x56,0xBF,0x38,0x84,0x00,0x40,0xA7,0x0E,0xFD,
- 0xFF,0x52,0xFE,0x03,0x6F,0x95,0x30,0xF1,0x97,0xFB,0xC0,0x85,0x60,0xD6,0x80,0x25,
- 0xA9,0x63,0xBE,0x03,0x01,0x4E,0x38,0xE2,0xF9,0xA2,0x34,0xFF,0xBB,0x3E,0x03,0x44,
- 0x78,0x00,0x90,0xCB,0x88,0x11,0x3A,0x94,0x65,0xC0,0x7C,0x63,0x87,0xF0,0x3C,0xAF,
- 0xD6,0x25,0xE4,0x8B,0x38,0x0A,0xAC,0x72,0x21,0xD4,0xF8,0x07};
-
-/*char *trim(char *s, int len)
-{
- char *ptr = NULL;
- if (!s) return NULL;
- if (!*s) return s;
-
- if(len==-1)
- ptr = s + strlen(s) - 1;
- else ptr = s+len - 1;
- for (; (ptr >= s) && (!*ptr || isspace((uint8_t)*ptr)) ; ptr--);
- ptr[1] = '\0';
- return s;
-}*/
-
-/*char *removeSpecialChars(char *s)
-{
- char *buf = s;
- if (!s) return NULL;
- if (!*s) return s;
-
- for (uint32_t i = 0; i < strlen(s); i++)
- {
- if (isspace((uint8_t)s[i]) && (s[i] != 0x20))
- *buf = 0x20;
- else
- *buf = s[i];
- buf++;
- }
- *buf = 0;
- return s;
-}*/
-
--- a/src/in_2sf/desmume/common.h
+++ /dev/null
@@ -1,77 +1,1 @@
-/*
- Copyright (C) 2008-2010 DeSmuME team
- This file is free software: you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation, either version 2 of the License, or
- (at your option) any later version.
-
- This file is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with the this software. If not, see <http://www.gnu.org/licenses/>.
-*/
-
-//TODO - dismantle this file
-
-#ifndef _COMMON_H_
-#define _COMMON_H_
-
-#include <string>
-#include <cstdio>
-#include <cstring>
-
-#include "types.h"
-
-extern const uint8_t logo_data[156];
-
-#ifdef WIN32
-# include "windowsh_wrapper.h"
-//# define WIN32_LEAN_AND_MEAN
-//# include <winsock2.h>
-
-/*# define CLASSNAME "DeSmuME"
-
-extern HINSTANCE hAppInst;
-
-extern bool romloaded;
-
-extern char IniName[MAX_PATH];
-extern void GetINIPath();
-extern void WritePrivateProfileInt(char *appname, char *keyname, int val, char *file);
-
-bool GetPrivateProfileBool(const char *appname, const char *keyname, bool defval, const char *filename);
-void WritePrivateProfileBool(char *appname, char *keyname, bool val, char *file);
-#else // non Windows
-#define sscanf_s sscanf*/
-#endif
-
-/*template<typename T> T reverseBits(T x)
-{
- T h = 0;
-
- for (unsigned i = 0; i < sizeof(T) * 8; ++i)
- {
- h = (h << 1) + (x & 1);
- x >>= 1;
- }
-
- return h;
-}*/
-
-/*template<typename T> char *intToBin(T val)
-{
- char buf[256] = "";
- for (int i = sizeof(T) * 8, t = 0; i > 0; --i, ++t)
- buf[i - 1] = val & (1<<t) ? '1' : '0';
- return _strdup(buf);
-}*/
-
-//extern char *trim(char *s, int len = -1);
-//extern char *removeSpecialChars(char *s);
-
-#endif
-
--- a/src/in_2sf/desmume/cp15.cpp
+++ b/src/in_2sf/desmume/cp15.cpp
@@ -17,81 +17,75 @@
*/
#include <cstdlib>
-
#include "cp15.h"
-//#include "debug.h"
#include "MMU.h"
-armcp15_t *armcp15_new(armcpu_t * c)
+armcp15_t cp15;
+
+bool armcp15_t::reset(armcpu_t *c)
{
- int i;
- armcp15_t *armcp15 = (armcp15_t*)malloc(sizeof(armcp15_t));
- if(!armcp15) return NULL;
-
-
- armcp15->cpu = c;
- armcp15->IDCode = 0x41059461;
- armcp15->cacheType = 0x0F0D2112;
- armcp15->TCMSize = 0x00140180;
- armcp15->ctrl = 0x00012078;
- armcp15->DCConfig = 0x0;
- armcp15->ICConfig = 0x0;
- armcp15->writeBuffCtrl = 0x0;
- armcp15->und = 0x0;
- armcp15->DaccessPerm = 0x22222222;
- armcp15->IaccessPerm = 0x22222222;
- armcp15->protectBaseSize0 = 0x0;
- armcp15->protectBaseSize1 = 0x0;
- armcp15->protectBaseSize2 = 0x0;
- armcp15->protectBaseSize3 = 0x0;
- armcp15->protectBaseSize4 = 0x0;
- armcp15->protectBaseSize5 = 0x0;
- armcp15->protectBaseSize6 = 0x0;
- armcp15->protectBaseSize7 = 0x0;
- armcp15->cacheOp = 0x0;
- armcp15->DcacheLock = 0x0;
- armcp15->IcacheLock = 0x0;
- armcp15->ITCMRegion = 0x0C;
- armcp15->DTCMRegion = 0x0080000A;
- armcp15->processID = 0;
-
- MMU.ARM9_RW_MODE = static_cast<uint8_t>(BIT7(armcp15->ctrl));
- armcp15->cpu->intVector = 0xFFFF0000 * (BIT13(armcp15->ctrl));
- armcp15->cpu->LDTBit = !BIT15(armcp15->ctrl); //TBit
+ //printf("CP15 Reset\n");
+ this->cpu = c;
+ this->IDCode = 0x41059461;
+ this->cacheType = 0x0F0D2112;
+ this->TCMSize = 0x00140180;
+ this->ctrl = 0x00012078;
+ this->DCConfig = 0x0;
+ this->ICConfig = 0x0;
+ this->writeBuffCtrl = 0x0;
+ this->und = 0x0;
+ this->DaccessPerm = 0x22222222;
+ this->IaccessPerm = 0x22222222;
+ this->protectBaseSize0 = 0x0;
+ this->protectBaseSize1 = 0x0;
+ this->protectBaseSize2 = 0x0;
+ this->protectBaseSize3 = 0x0;
+ this->protectBaseSize4 = 0x0;
+ this->protectBaseSize5 = 0x0;
+ this->protectBaseSize6 = 0x0;
+ this->protectBaseSize7 = 0x0;
+ this->cacheOp = 0x0;
+ this->DcacheLock = 0x0;
+ this->IcacheLock = 0x0;
+ this->ITCMRegion = 0x0C;
+ this->DTCMRegion = 0x0080000A;
+ this->processID = 0;
+
+ MMU.ARM9_RW_MODE = BIT7(this->ctrl);
+ this->cpu->intVector = 0xFFFF0000 * BIT13(this->ctrl);
+ this->cpu->LDTBit = !BIT15(this->ctrl); // TBit
/* preset calculated regionmasks */
- for (i=0;i<8;i++) {
- armcp15->regionWriteMask_USR[i] = 0 ;
- armcp15->regionWriteMask_SYS[i] = 0 ;
- armcp15->regionReadMask_USR[i] = 0 ;
- armcp15->regionReadMask_SYS[i] = 0 ;
- armcp15->regionExecuteMask_USR[i] = 0 ;
- armcp15->regionExecuteMask_SYS[i] = 0 ;
- armcp15->regionWriteSet_USR[i] = 0 ;
- armcp15->regionWriteSet_SYS[i] = 0 ;
- armcp15->regionReadSet_USR[i] = 0 ;
- armcp15->regionReadSet_SYS[i] = 0 ;
- armcp15->regionExecuteSet_USR[i] = 0 ;
- armcp15->regionExecuteSet_SYS[i] = 0 ;
- } ;
-
- return armcp15;
-}
-
-//#define ACCESSTYPE(val,n) (((val) >> (4*n)) & 0x0F)
+ for (uint8_t i = 0; i < 8; ++i)
+ {
+ this->regionWriteMask_USR[i] = 0;
+ this->regionWriteMask_SYS[i] = 0;
+ this->regionReadMask_USR[i] = 0;
+ this->regionReadMask_SYS[i] = 0;
+ this->regionExecuteMask_USR[i] = 0;
+ this->regionExecuteMask_SYS[i] = 0;
+ this->regionWriteSet_USR[i] = 0;
+ this->regionWriteSet_SYS[i] = 0;
+ this->regionReadSet_USR[i] = 0;
+ this->regionReadSet_SYS[i] = 0;
+ this->regionExecuteSet_USR[i] = 0;
+ this->regionExecuteSet_SYS[i] = 0;
+ }
+
+ return true;
+}
+
static inline uint32_t ACCESSTYPE(uint32_t val, unsigned char n) { return (val >> (4 * n)) & 0x0F; }
-//#define SIZEIDENTIFIER(val) ((((val) >> 1) & 0x1F))
static inline uint32_t SIZEIDENTIFIER(uint32_t val) { return (val >> 1) & 0x1F; }
-//#define SIZEBINARY(val) (1 << (SIZEIDENTIFIER(val)+1))
static inline uint32_t SIZEBINARY(uint32_t val) { return 1 << (SIZEIDENTIFIER(val) + 1); }
-//#define MASKFROMREG(val) (~((SIZEBINARY(val)-1) | 0x3F))
static inline uint32_t MASKFROMREG(uint32_t val) { return ~((SIZEBINARY(val) - 1) | 0x3F); }
-//#define SETFROMREG(val) ((val) & MASKFROMREG(val))
static inline uint32_t SETFROMREG(uint32_t val) { return val & MASKFROMREG(val); }
/* sets the precalculated regions to mask,set for the affected accesstypes */
-static void armcp15_setSingleRegionAccess(armcp15_t *armcp15,uint32_t dAccess,uint32_t iAccess,unsigned char num, uint32_t mask,uint32_t set) {
-
- switch (ACCESSTYPE(dAccess,num)) {
+void armcp15_t::setSingleRegionAccess(uint32_t dAccess, uint32_t iAccess, unsigned char num, uint32_t mask, uint32_t set)
+{
+
+ switch (ACCESSTYPE(dAccess, num))
+ {
case 4: /* UNP */
case 7: /* UNP */
case 8: /* UNP */
@@ -103,67 +97,67 @@
case 14: /* UNP */
case 15: /* UNP */
case 0: /* no access at all */
- armcp15->regionWriteMask_USR[num] = 0 ;
- armcp15->regionWriteSet_USR[num] = 0xFFFFFFFF ;
- armcp15->regionReadMask_USR[num] = 0 ;
- armcp15->regionReadSet_USR[num] = 0xFFFFFFFF ;
- armcp15->regionWriteMask_SYS[num] = 0 ;
- armcp15->regionWriteSet_SYS[num] = 0xFFFFFFFF ;
- armcp15->regionReadMask_SYS[num] = 0 ;
- armcp15->regionReadSet_SYS[num] = 0xFFFFFFFF ;
- break ;
+ this->regionWriteMask_USR[num] = 0;
+ this->regionWriteSet_USR[num] = 0xFFFFFFFF;
+ this->regionReadMask_USR[num] = 0;
+ this->regionReadSet_USR[num] = 0xFFFFFFFF;
+ this->regionWriteMask_SYS[num] = 0;
+ this->regionWriteSet_SYS[num] = 0xFFFFFFFF;
+ this->regionReadMask_SYS[num] = 0;
+ this->regionReadSet_SYS[num] = 0xFFFFFFFF;
+ break;
case 1: /* no access at USR, all to sys */
- armcp15->regionWriteMask_USR[num] = 0 ;
- armcp15->regionWriteSet_USR[num] = 0xFFFFFFFF ;
- armcp15->regionReadMask_USR[num] = 0 ;
- armcp15->regionReadSet_USR[num] = 0xFFFFFFFF ;
- armcp15->regionWriteMask_SYS[num] = mask ;
- armcp15->regionWriteSet_SYS[num] = set ;
- armcp15->regionReadMask_SYS[num] = mask ;
- armcp15->regionReadSet_SYS[num] = set ;
- break ;
+ this->regionWriteMask_USR[num] = 0;
+ this->regionWriteSet_USR[num] = 0xFFFFFFFF;
+ this->regionReadMask_USR[num] = 0;
+ this->regionReadSet_USR[num] = 0xFFFFFFFF;
+ this->regionWriteMask_SYS[num] = mask;
+ this->regionWriteSet_SYS[num] = set;
+ this->regionReadMask_SYS[num] = mask;
+ this->regionReadSet_SYS[num] = set;
+ break;
case 2: /* read at USR, all to sys */
- armcp15->regionWriteMask_USR[num] = 0 ;
- armcp15->regionWriteSet_USR[num] = 0xFFFFFFFF ;
- armcp15->regionReadMask_USR[num] = mask ;
- armcp15->regionReadSet_USR[num] = set ;
- armcp15->regionWriteMask_SYS[num] = mask ;
- armcp15->regionWriteSet_SYS[num] = set ;
- armcp15->regionReadMask_SYS[num] = mask ;
- armcp15->regionReadSet_SYS[num] = set ;
- break ;
+ this->regionWriteMask_USR[num] = 0;
+ this->regionWriteSet_USR[num] = 0xFFFFFFFF;
+ this->regionReadMask_USR[num] = mask;
+ this->regionReadSet_USR[num] = set;
+ this->regionWriteMask_SYS[num] = mask;
+ this->regionWriteSet_SYS[num] = set;
+ this->regionReadMask_SYS[num] = mask;
+ this->regionReadSet_SYS[num] = set;
+ break;
case 3: /* all to USR, all to sys */
- armcp15->regionWriteMask_USR[num] = mask ;
- armcp15->regionWriteSet_USR[num] = set ;
- armcp15->regionReadMask_USR[num] = mask ;
- armcp15->regionReadSet_USR[num] = set ;
- armcp15->regionWriteMask_SYS[num] = mask ;
- armcp15->regionWriteSet_SYS[num] = set ;
- armcp15->regionReadMask_SYS[num] = mask ;
- armcp15->regionReadSet_SYS[num] = set ;
- break ;
+ this->regionWriteMask_USR[num] = mask;
+ this->regionWriteSet_USR[num] = set;
+ this->regionReadMask_USR[num] = mask;
+ this->regionReadSet_USR[num] = set;
+ this->regionWriteMask_SYS[num] = mask;
+ this->regionWriteSet_SYS[num] = set;
+ this->regionReadMask_SYS[num] = mask;
+ this->regionReadSet_SYS[num] = set;
+ break;
case 5: /* no access at USR, read to sys */
- armcp15->regionWriteMask_USR[num] = 0 ;
- armcp15->regionWriteSet_USR[num] = 0xFFFFFFFF ;
- armcp15->regionReadMask_USR[num] = 0 ;
- armcp15->regionReadSet_USR[num] = 0xFFFFFFFF ;
- armcp15->regionWriteMask_SYS[num] = 0 ;
- armcp15->regionWriteSet_SYS[num] = 0xFFFFFFFF ;
- armcp15->regionReadMask_SYS[num] = mask ;
- armcp15->regionReadSet_SYS[num] = set ;
- break ;
+ this->regionWriteMask_USR[num] = 0;
+ this->regionWriteSet_USR[num] = 0xFFFFFFFF;
+ this->regionReadMask_USR[num] = 0;
+ this->regionReadSet_USR[num] = 0xFFFFFFFF;
+ this->regionWriteMask_SYS[num] = 0;
+ this->regionWriteSet_SYS[num] = 0xFFFFFFFF;
+ this->regionReadMask_SYS[num] = mask;
+ this->regionReadSet_SYS[num] = set;
+ break;
case 6: /* read at USR, read to sys */
- armcp15->regionWriteMask_USR[num] = 0 ;
- armcp15->regionWriteSet_USR[num] = 0xFFFFFFFF ;
- armcp15->regionReadMask_USR[num] = mask ;
- armcp15->regionReadSet_USR[num] = set ;
- armcp15->regionWriteMask_SYS[num] = 0 ;
- armcp15->regionWriteSet_SYS[num] = 0xFFFFFFFF ;
- armcp15->regionReadMask_SYS[num] = mask ;
- armcp15->regionReadSet_SYS[num] = set ;
- break ;
- }
- switch (ACCESSTYPE(iAccess,num)) {
+ this->regionWriteMask_USR[num] = 0;
+ this->regionWriteSet_USR[num] = 0xFFFFFFFF;
+ this->regionReadMask_USR[num] = mask;
+ this->regionReadSet_USR[num] = set;
+ this->regionWriteMask_SYS[num] = 0;
+ this->regionWriteSet_SYS[num] = 0xFFFFFFFF;
+ this->regionReadMask_SYS[num] = mask;
+ this->regionReadSet_SYS[num] = set;
+ }
+ switch (ACCESSTYPE(iAccess, num))
+ {
case 4: /* UNP */
case 7: /* UNP */
case 8: /* UNP */
@@ -175,401 +169,387 @@
case 14: /* UNP */
case 15: /* UNP */
case 0: /* no access at all */
- armcp15->regionExecuteMask_USR[num] = 0 ;
- armcp15->regionExecuteSet_USR[num] = 0xFFFFFFFF ;
- armcp15->regionExecuteMask_SYS[num] = 0 ;
- armcp15->regionExecuteSet_SYS[num] = 0xFFFFFFFF ;
- break ;
+ this->regionExecuteMask_USR[num] = 0;
+ this->regionExecuteSet_USR[num] = 0xFFFFFFFF;
+ this->regionExecuteMask_SYS[num] = 0;
+ this->regionExecuteSet_SYS[num] = 0xFFFFFFFF;
+ break;
case 1:
- armcp15->regionExecuteMask_USR[num] = 0 ;
- armcp15->regionExecuteSet_USR[num] = 0xFFFFFFFF ;
- armcp15->regionExecuteMask_SYS[num] = mask ;
- armcp15->regionExecuteSet_SYS[num] = set ;
- break ;
+ this->regionExecuteMask_USR[num] = 0;
+ this->regionExecuteSet_USR[num] = 0xFFFFFFFF;
+ this->regionExecuteMask_SYS[num] = mask;
+ this->regionExecuteSet_SYS[num] = set;
+ break;
case 2:
case 3:
case 6:
- armcp15->regionExecuteMask_USR[num] = mask ;
- armcp15->regionExecuteSet_USR[num] = set ;
- armcp15->regionExecuteMask_SYS[num] = mask ;
- armcp15->regionExecuteSet_SYS[num] = set ;
- break ;
+ this->regionExecuteMask_USR[num] = mask;
+ this->regionExecuteSet_USR[num] = set;
+ this->regionExecuteMask_SYS[num] = mask;
+ this->regionExecuteSet_SYS[num] = set;
}
}
/* precalculate region masks/sets from cp15 register */
-static void armcp15_maskPrecalc(armcp15_t *armcp15)
+void armcp15_t::maskPrecalc()
{
-#define precalc(num) { \
- uint32_t mask = 0, set = 0xFFFFFFFF ; /* (x & 0) == 0xFF..FF is allways false (disabled) */ \
- if (BIT_N(armcp15->protectBaseSize##num,0)) /* if region is enabled */ \
- { /* reason for this define: naming includes var */ \
- mask = MASKFROMREG(armcp15->protectBaseSize##num) ; \
- set = SETFROMREG(armcp15->protectBaseSize##num) ; \
- if (SIZEIDENTIFIER(armcp15->protectBaseSize##num)==0x1F) \
- { /* for the 4GB region, uint32_t suffers wraparound */ \
- mask = 0 ; set = 0 ; /* (x & 0) == 0 is allways true (enabled) */ \
-} \
-} \
- armcp15_setSingleRegionAccess(armcp15,armcp15->DaccessPerm,armcp15->IaccessPerm,num,mask,set) ; \
-}
- precalc(0) ;
- precalc(1) ;
- precalc(2) ;
- precalc(3) ;
- precalc(4) ;
- precalc(5) ;
- precalc(6) ;
- precalc(7) ;
-}
-
-/*bool armcp15_isAccessAllowed(armcp15_t *armcp15,uint32_t address,uint32_t access)
+#define precalc(num) \
+{ \
+ uint32_t mask = 0, set = 0xFFFFFFFF; /* (x & 0) == 0xFF..FF is allways false (disabled) */ \
+ if (BIT_N(this->protectBaseSize##num, 0)) /* if region is enabled */ \
+ { \
+ /* reason for this define: naming includes var */ \
+ mask = MASKFROMREG(this->protectBaseSize##num); \
+ set = SETFROMREG(this->protectBaseSize##num); \
+ if (SIZEIDENTIFIER(this->protectBaseSize##num) == 0x1F) \
+ { \
+ /* for the 4GB region, u32 suffers wraparound */ \
+ mask = 0; \
+ set = 0; /* (x & 0) == 0 is allways true (enabled) */ \
+ } \
+ } \
+ this->setSingleRegionAccess(this->DaccessPerm, this->IaccessPerm, num, mask, set); \
+}
+ precalc(0);
+ precalc(1);
+ precalc(2);
+ precalc(3);
+ precalc(4);
+ precalc(5);
+ precalc(6);
+ precalc(7);
+#undef precalc
+}
+
+bool armcp15_t::moveCP2ARM(uint32_t *R, uint8_t CRn, uint8_t CRm, uint8_t opcode1, uint8_t opcode2)
{
- int i ;
- if (!(armcp15->ctrl & 1)) return true ;*/ /* protection checking is not enabled */
- /*for (i=0;i<8;i++) {
- switch (access) {
- case CP15_ACCESS_WRITEUSR:
- if ((address & armcp15->regionWriteMask_USR[i]) == armcp15->regionWriteSet_USR[i]) return true ;
- break ;
- case CP15_ACCESS_WRITESYS:
- if ((address & armcp15->regionWriteMask_SYS[i]) == armcp15->regionWriteSet_SYS[i]) return true ;
- break ;
- case CP15_ACCESS_READUSR:
- if ((address & armcp15->regionReadMask_USR[i]) == armcp15->regionReadSet_USR[i]) return true ;
- break ;
- case CP15_ACCESS_READSYS:
- if ((address & armcp15->regionReadMask_SYS[i]) == armcp15->regionReadSet_SYS[i]) return true ;
- break ;
- case CP15_ACCESS_EXECUSR:
- if ((address & armcp15->regionExecuteMask_USR[i]) == armcp15->regionExecuteSet_USR[i]) return true ;
- break ;
- case CP15_ACCESS_EXECSYS:
- if ((address & armcp15->regionExecuteMask_SYS[i]) == armcp15->regionExecuteSet_SYS[i]) return true ;
- break ;
- }
- }*/
- /* when protections are enabled, but no region allows access, deny access */
- /*return false ;
-}*/
-
-/*bool armcp15_dataProcess(armcp15_t *, uint8_t, uint8_t, uint8_t, uint8_t, uint8_t)
+ if (!this->cpu)
+ {
+ printf("ERROR: cp15 don\'t allocated\n");
+ return false;
+ }
+ if (this->cpu->CPSR.bits.mode == USR)
+ return false;
+
+ switch (CRn)
+ {
+ case 0:
+ if (!opcode1 && !CRm)
+ {
+ switch (opcode2)
+ {
+ case 1:
+ *R = this->cacheType;
+ return true;
+ case 2:
+ *R = this->TCMSize;
+ return true;
+ default:
+ *R = this->IDCode;
+ return true;
+ }
+ }
+ return false;
+ case 1:
+ if (!opcode1 && !opcode2 && !CRm)
+ {
+ *R = this->ctrl;
+ return true;
+ }
+ return false;
+ case 2:
+ if (!opcode1 && !CRm)
+ {
+ switch (opcode2)
+ {
+ case 0:
+ *R = this->DCConfig;
+ return true;
+ case 1:
+ *R = this->ICConfig;
+ return true;
+ default:
+ return false;
+ }
+ }
+ return false;
+ case 3:
+ if (!opcode1 && ~opcode2 && !CRm)
+ {
+ *R = this->writeBuffCtrl;
+ return true;
+ }
+ return false;
+ case 5:
+ if (!opcode1 && !CRm)
+ {
+ switch (opcode2)
+ {
+ case 2:
+ *R = this->DaccessPerm;
+ return true;
+ case 3:
+ *R = this->IaccessPerm;
+ return true;
+ default:
+ return false;
+ }
+ }
+ return false;
+ case 6:
+ if (!opcode1 && !opcode2)
+ {
+ switch (CRm)
+ {
+ case 0:
+ *R = this->protectBaseSize0;
+ return true;
+ case 1:
+ *R = this->protectBaseSize1;
+ return true;
+ case 2:
+ *R = this->protectBaseSize2;
+ return true;
+ case 3:
+ *R = this->protectBaseSize3;
+ return true;
+ case 4:
+ *R = this->protectBaseSize4;
+ return true;
+ case 5:
+ *R = this->protectBaseSize5;
+ return true;
+ case 6:
+ *R = this->protectBaseSize6;
+ return true;
+ case 7:
+ *R = this->protectBaseSize7;
+ return true;
+ default:
+ return false;
+ }
+ }
+ return false;
+ case 9:
+ if (!opcode1)
+ {
+ switch (CRm)
+ {
+ case 0:
+ switch (opcode2)
+ {
+ case 0:
+ *R = this->DcacheLock;
+ return true;
+ case 1:
+ *R = this->IcacheLock;
+ return true;
+ default:
+ return false;
+ }
+ case 1:
+ switch (opcode2)
+ {
+ case 0:
+ *R = this->DTCMRegion;
+ return true;
+ case 1:
+ *R = this->ITCMRegion;
+ return true;
+ default:
+ return false;
+ }
+ }
+ }
+ return false;
+ default:
+ return false;
+ }
+}
+
+bool armcp15_t::moveARM2CP(uint32_t val, uint8_t CRn, uint8_t CRm, uint8_t opcode1, uint8_t opcode2)
{
- //LOG("Unsupported CP15 operation : DataProcess\n");
- return false;
-}*/
-
-/*bool armcp15_load(armcp15_t *, uint8_t, uint8_t)
+ if (!this->cpu)
+ {
+ printf("ERROR: cp15 don\'t allocated\n");
+ return false;
+ }
+ if (this->cpu->CPSR.bits.mode == USR)
+ return false;
+
+ switch (CRn)
+ {
+ case 1:
+ if (!opcode1 && !opcode2 && !CRm)
+ {
+ // On the NDS bit0,2,7,12..19 are R/W, Bit3..6 are always set, all other bits are always zero.
+ this->ctrl = (val & 0x000FF085) | 0x00000078;
+ MMU.ARM9_RW_MODE = static_cast<uint8_t>(BIT7(val));
+ // zero 31-jan-2010: change from 0x0FFF0000 to 0xFFFF0000 per gbatek
+ this->cpu->intVector = 0xFFFF0000 * BIT13(val);
+ this->cpu->LDTBit = !BIT15(val); // TBit
+ return true;
+ }
+ return false;
+ case 2:
+ if (!opcode1 && !CRm)
+ {
+ switch (opcode2)
+ {
+ case 0:
+ this->DCConfig = val;
+ return true;
+ case 1:
+ this->ICConfig = val;
+ return true;
+ default:
+ return false;
+ }
+ }
+ return false;
+ case 3:
+ if (!opcode1 && !opcode2 && !CRm)
+ {
+ this->writeBuffCtrl = val;
+ return true;
+ }
+ return false;
+ case 5:
+ if (!opcode1 && !CRm)
+ {
+ switch (opcode2)
+ {
+ case 2:
+ this->DaccessPerm = val;
+ this->maskPrecalc();
+ return true;
+ case 3:
+ this->IaccessPerm = val;
+ this->maskPrecalc();
+ return true;
+ default:
+ return false;
+ }
+ }
+ return false;
+ case 6:
+ if (!opcode1 && !opcode2)
+ {
+ switch (CRm)
+ {
+ case 0:
+ this->protectBaseSize0 = val;
+ this->maskPrecalc();
+ return true;
+ case 1:
+ this->protectBaseSize1 = val;
+ this->maskPrecalc();
+ return true;
+ case 2:
+ this->protectBaseSize2 = val;
+ this->maskPrecalc();
+ return true;
+ case 3:
+ this->protectBaseSize3 = val;
+ this->maskPrecalc();
+ return true;
+ case 4:
+ this->protectBaseSize4 = val;
+ this->maskPrecalc();
+ return true;
+ case 5:
+ this->protectBaseSize5 = val;
+ this->maskPrecalc();
+ return true;
+ case 6:
+ this->protectBaseSize6 = val;
+ this->maskPrecalc();
+ return true;
+ case 7:
+ this->protectBaseSize7 = val;
+ this->maskPrecalc();
+ return true;
+ default:
+ return false;
+ }
+ }
+ return false;
+ case 7:
+ if (!CRm && !opcode1 && opcode2 == 4)
+ {
+ this->cpu->waitIRQ = true;
+ this->cpu->halt_IE_and_IF = true;
+ // IME set deliberately omitted: only SWI sets IME to 1
+ return true;
+ }
+ return false;
+ case 9:
+ if (!opcode1)
+ {
+ switch (CRm)
+ {
+ case 0:
+ switch (opcode2)
+ {
+ case 0:
+ this->DcacheLock = val;
+ return true;
+ case 1:
+ this->IcacheLock = val;
+ return true;
+ default:
+ return false;
+ }
+ case 1:
+ switch (opcode2)
+ {
+ case 0:
+ MMU.DTCMRegion = this->DTCMRegion = val & 0x0FFFF000;
+ return true;
+ case 1:
+ this->ITCMRegion = val;
+ // ITCM base is not writeable!
+ MMU.ITCMRegion = 0;
+ return true;
+ default:
+ return false;
+ }
+ }
+ }
+ return false;
+ default:
+ return false;
+ }
+}
+
+/* precalculate region masks/sets from cp15 register ----- JIT */
+void maskPrecalc()
{
- //LOG("Unsupported CP15 operation : Load\n");
- return false;
-}*/
-
-/*bool armcp15_store(armcp15_t *, uint8_t, uint8_t)
-{
- //LOG("Unsupported CP15 operation : Store\n");
- return false;
-}*/
-
-bool armcp15_moveCP2ARM(armcp15_t *armcp15, uint32_t * R, uint8_t CRn, uint8_t CRm, uint8_t opcode1, uint8_t opcode2)
-{
- if(armcp15->cpu->CPSR.bits.mode == USR) return false;
-
- switch(CRn)
- {
- case 0:
- if((opcode1 == 0)&&(CRm==0))
- {
- switch(opcode2)
- {
- case 1:
- *R = armcp15->cacheType;
- return true;
- case 2:
- *R = armcp15->TCMSize;
- return true;
- default:
- *R = armcp15->IDCode;
- return true;
- }
- }
- return false;
- case 1:
- if((opcode1==0) && (opcode2==0) && (CRm==0))
- {
- *R = armcp15->ctrl;
- //LOG("CP15: CPtoARM ctrl %08X\n", armcp15->ctrl);
- return true;
- }
- return false;
-
- case 2:
- if((opcode1==0) && (CRm==0))
- {
- switch(opcode2)
- {
- case 0:
- *R = armcp15->DCConfig;
- return true;
- case 1:
- *R = armcp15->ICConfig;
- return true;
- default:
- return false;
- }
- }
- return false;
- case 3:
- if((opcode1==0) && (opcode2==0) && (CRm==0))
- {
- *R = armcp15->writeBuffCtrl;
- //LOG("CP15: CPtoARM writeBuffer ctrl %08X\n", armcp15->writeBuffCtrl);
- return true;
- }
- return false;
- case 5:
- if((opcode1==0) && (CRm==0))
- {
- switch(opcode2)
- {
- case 2:
- *R = armcp15->DaccessPerm;
- return true;
- case 3:
- *R = armcp15->IaccessPerm;
- return true;
- default:
- return false;
- }
- }
- return false;
- case 6:
- if((opcode1==0) && (opcode2==0))
- {
- switch(CRm)
- {
- case 0:
- *R = armcp15->protectBaseSize0;
- return true;
- case 1:
- *R = armcp15->protectBaseSize1;
- return true;
- case 2:
- *R = armcp15->protectBaseSize2;
- return true;
- case 3:
- *R = armcp15->protectBaseSize3;
- return true;
- case 4:
- *R = armcp15->protectBaseSize4;
- return true;
- case 5:
- *R = armcp15->protectBaseSize5;
- return true;
- case 6:
- *R = armcp15->protectBaseSize6;
- return true;
- case 7:
- *R = armcp15->protectBaseSize7;
- return true;
- default:
- return false;
- }
- }
- return false;
- case 9:
- if((opcode1==0))
- {
- switch(CRm)
- {
- case 0:
- switch(opcode2)
- {
- case 0:
- *R = armcp15->DcacheLock;
- return true;
- case 1:
- *R = armcp15->IcacheLock;
- return true;
- default:
- return false;
- }
- case 1:
- switch(opcode2)
- {
- case 0:
- *R = armcp15->DTCMRegion;
- return true;
- case 1:
- *R = armcp15->ITCMRegion;
- return true;
- default:
- return false;
- }
- }
- }
- return false;
- default:
- //LOG("Unsupported CP15 operation : MRC\n");
- return false;
- }
-}
-
-static uint32_t CP15wait4IRQ(armcpu_t *cpu)
-{
- cpu->waitIRQ = true;
- cpu->halt_IE_and_IF = true;
- //IME set deliberately omitted: only SWI sets IME to 1
- return 1;
-}
-
-bool armcp15_moveARM2CP(armcp15_t *armcp15, uint32_t val, uint8_t CRn, uint8_t CRm, uint8_t opcode1, uint8_t opcode2)
-{
- if(armcp15->cpu->CPSR.bits.mode == USR) return false;
-
- switch(CRn)
- {
- case 1:
- if((opcode1==0) && (opcode2==0) && (CRm==0))
- {
-
- //On the NDS bit0,2,7,12..19 are R/W, Bit3..6 are always set, all other bits are always zero.
- armcp15->ctrl = (val & 0x000FF085) | 0x00000078;
- MMU.ARM9_RW_MODE = static_cast<uint8_t>(BIT7(val));
- //zero 31-jan-2010: change from 0x0FFF0000 to 0xFFFF0000 per gbatek
- armcp15->cpu->intVector = 0xFFFF0000 * (BIT13(val));
- armcp15->cpu->LDTBit = !BIT15(val); //TBit
- //LOG("CP15: ARMtoCP ctrl %08X (val %08X)\n", armcp15->ctrl, val);
- return true;
- }
- return false;
- case 2:
- if((opcode1==0) && (CRm==0))
- {
- switch(opcode2)
- {
- case 0:
- armcp15->DCConfig = val;
- return true;
- case 1:
- armcp15->ICConfig = val;
- return true;
- default:
- return false;
- }
- }
- return false;
- case 3:
- if((opcode1==0) && (opcode2==0) && (CRm==0))
- {
- armcp15->writeBuffCtrl = val;
- //LOG("CP15: ARMtoCP writeBuffer ctrl %08X\n", armcp15->writeBuffCtrl);
- return true;
- }
- return false;
- case 5:
- if((opcode1==0) && (CRm==0))
- {
- switch(opcode2)
- {
- case 2:
- armcp15->DaccessPerm = val;
- armcp15_maskPrecalc(armcp15);
- return true;
- case 3:
- armcp15->IaccessPerm = val;
- armcp15_maskPrecalc(armcp15);
- return true;
- default:
- return false;
- }
- }
- return false;
- case 6:
- if((opcode1==0) && (opcode2==0))
- {
- switch(CRm)
- {
- case 0:
- armcp15->protectBaseSize0 = val;
- armcp15_maskPrecalc(armcp15) ;
- return true;
- case 1:
- armcp15->protectBaseSize1 = val;
- armcp15_maskPrecalc(armcp15) ;
- return true;
- case 2:
- armcp15->protectBaseSize2 = val;
- armcp15_maskPrecalc(armcp15) ;
- return true;
- case 3:
- armcp15->protectBaseSize3 = val;
- armcp15_maskPrecalc(armcp15) ;
- return true;
- case 4:
- armcp15->protectBaseSize4 = val;
- armcp15_maskPrecalc(armcp15) ;
- return true;
- case 5:
- armcp15->protectBaseSize5 = val;
- armcp15_maskPrecalc(armcp15) ;
- return true;
- case 6:
- armcp15->protectBaseSize6 = val;
- armcp15_maskPrecalc(armcp15) ;
- return true;
- case 7:
- armcp15->protectBaseSize7 = val;
- armcp15_maskPrecalc(armcp15) ;
- return true;
- default:
- return false;
- }
- }
- return false;
- case 7:
- if((CRm==0)&&(opcode1==0)&&((opcode2==4)))
- {
- CP15wait4IRQ(armcp15->cpu);
- return true;
- }
- return false;
- case 9:
- if((opcode1==0))
- {
- switch(CRm)
- {
- case 0:
- switch(opcode2)
- {
- case 0:
- armcp15->DcacheLock = val;
- return true;
- case 1:
- armcp15->IcacheLock = val;
- return true;
- default:
- return false;
- }
- case 1:
- switch(opcode2)
- {
- case 0:
- MMU.DTCMRegion = armcp15->DTCMRegion = val & 0x0FFFF000;
- return true;
- case 1:
- armcp15->ITCMRegion = val;
- //ITCM base is not writeable!
- MMU.ITCMRegion = 0;
- return true;
- default:
- return false;
- }
- }
- }
- return false;
- default:
- return false;
- }
-}
-
+#define precalc(num) \
+{ \
+ uint32_t mask = 0, set = 0xFFFFFFFF; /* (x & 0) == 0xFF..FF is allways false (disabled) */ \
+ if (BIT_N(cp15.protectBaseSize##num, 0)) /* if region is enabled */ \
+ { \
+ /* reason for this define: naming includes var */ \
+ mask = MASKFROMREG(cp15.protectBaseSize##num); \
+ set = SETFROMREG(cp15.protectBaseSize##num); \
+ if (SIZEIDENTIFIER(cp15.protectBaseSize##num) == 0x1F) \
+ { \
+ /* for the 4GB region, u32 suffers wraparound */ \
+ mask = 0; \
+ set = 0; /* (x & 0) == 0 is allways true (enabled) */ \
+ } \
+ } \
+ cp15.setSingleRegionAccess(cp15.DaccessPerm, cp15.IaccessPerm, num, mask, set); \
+}
+ precalc(0);
+ precalc(1);
+ precalc(2);
+ precalc(3);
+ precalc(4);
+ precalc(5);
+ precalc(6);
+ precalc(7);
+#undef precalc
+}
+
--- a/src/in_2sf/desmume/cp15.h
+++ b/src/in_2sf/desmume/cp15.h
@@ -21,8 +21,19 @@
#include "armcpu.h"
+const uint32_t CP15_ACCESS_WRITE = 0;
+const uint32_t CP15_ACCESS_READ = 2;
+const uint32_t CP15_ACCESS_EXECUTE = 4;
+const uint32_t CP15_ACCESS_WRITEUSR = CP15_ACCESS_WRITE;
+const uint32_t CP15_ACCESS_WRITESYS = 1;
+const uint32_t CP15_ACCESS_READUSR = CP15_ACCESS_READ;
+const uint32_t CP15_ACCESS_READSYS = 3;
+const uint32_t CP15_ACCESS_EXECUSR = CP15_ACCESS_EXECUTE;
+const uint32_t CP15_ACCESS_EXECSYS = 5;
+
struct armcp15_t
{
+public:
uint32_t IDCode;
uint32_t cacheType;
uint32_t TCMSize;
@@ -66,25 +77,39 @@
uint32_t regionExecuteSet_SYS[8];
armcpu_t *cpu;
+
+ void setSingleRegionAccess(uint32_t dAccess, uint32_t iAccess, unsigned char num, uint32_t mask, uint32_t set);
+ void maskPrecalc();
+
+public:
+ armcp15_t() : IDCode(0), cacheType(0), TCMSize(0), ctrl(0), DCConfig(0), ICConfig(0), writeBuffCtrl(0), und(0), DaccessPerm(0), IaccessPerm(0), protectBaseSize0(0), protectBaseSize1(0), protectBaseSize2(0),
+ protectBaseSize3(0), protectBaseSize4(0), protectBaseSize5(0), protectBaseSize6(0), protectBaseSize7(0), cacheOp(0), DcacheLock(0), IcacheLock(0), ITCMRegion(0), DTCMRegion(0), processID(0), RAM_TAG(0),
+ testState(0), cacheDbg(0), cpu(nullptr)
+ {
+ memset(&this->regionWriteMask_USR[0], 0, sizeof(this->regionWriteMask_USR));
+ memset(&this->regionWriteMask_SYS[0], 0, sizeof(this->regionWriteMask_SYS));
+ memset(&this->regionReadMask_USR[0], 0, sizeof(this->regionReadMask_USR));
+ memset(&this->regionReadMask_SYS[0], 0, sizeof(this->regionReadMask_SYS));
+ memset(&this->regionExecuteMask_USR[0], 0, sizeof(this->regionExecuteMask_USR));
+ memset(&this->regionExecuteMask_SYS[0], 0, sizeof(this->regionExecuteMask_SYS));
+ memset(&this->regionWriteSet_USR[0], 0, sizeof(this->regionWriteSet_USR));
+ memset(&this->regionWriteSet_SYS[0], 0, sizeof(this->regionWriteSet_SYS));
+ memset(&this->regionReadSet_USR[0], 0, sizeof(this->regionReadSet_USR));
+ memset(&this->regionReadSet_SYS[0], 0, sizeof(this->regionReadSet_SYS));
+ memset(&this->regionExecuteSet_USR[0], 0, sizeof(this->regionExecuteSet_USR));
+ memset(&this->regionExecuteSet_SYS[0], 0, sizeof(this->regionExecuteSet_SYS));
+ }
+ bool reset(armcpu_t *c);
+ bool dataProcess(uint8_t CRd, uint8_t CRn, uint8_t CRm, uint8_t opcode1, uint8_t opcode2);
+ bool load(uint8_t CRd, uint8_t adr);
+ bool store(uint8_t CRd, uint8_t adr);
+ bool moveCP2ARM(uint32_t *R, uint8_t CRn, uint8_t CRm, uint8_t opcode1, uint8_t opcode2);
+ bool moveARM2CP(uint32_t val, uint8_t CRn, uint8_t CRm, uint8_t opcode1, uint8_t opcode2);
+ bool isAccessAllowed(uint32_t address,uint32_t access);
};
-armcp15_t *armcp15_new(armcpu_t *c);
-//bool armcp15_dataProcess(armcp15_t *armcp15, uint8_t CRd, uint8_t CRn, uint8_t CRm, uint8_t opcode1, uint8_t opcode2);
-//bool armcp15_load(armcp15_t *armcp15, uint8_t CRd, uint8_t adr);
-//bool armcp15_store(armcp15_t *armcp15, uint8_t CRd, uint8_t adr);
-bool armcp15_moveCP2ARM(armcp15_t *armcp15, uint32_t * R, uint8_t CRn, uint8_t CRm, uint8_t opcode1, uint8_t opcode2);
-bool armcp15_moveARM2CP(armcp15_t *armcp15, uint32_t val, uint8_t CRn, uint8_t CRm, uint8_t opcode1, uint8_t opcode2);
-//bool armcp15_isAccessAllowed(armcp15_t *armcp15,uint32_t address,uint32_t access);
-
-static const uint32_t CP15_ACCESS_WRITE = 0;
-static const uint32_t CP15_ACCESS_READ = 2;
-static const uint32_t CP15_ACCESS_EXECUTE = 4;
-static const uint32_t CP15_ACCESS_WRITEUSR = CP15_ACCESS_WRITE;
-static const uint32_t CP15_ACCESS_WRITESYS = 1;
-static const uint32_t CP15_ACCESS_READUSR = CP15_ACCESS_READ;
-static const uint32_t CP15_ACCESS_READSYS = 3;
-static const uint32_t CP15_ACCESS_EXECUSR = CP15_ACCESS_EXECUTE;
-static const uint32_t CP15_ACCESS_EXECSYS = 5;
+extern armcp15_t cp15;
+void maskPrecalc();
#endif /* __CP15_H__*/
--- a/src/in_2sf/desmume/emufile.cpp
+++ b/src/in_2sf/desmume/emufile.cpp
@@ -22,238 +22,29 @@
THE SOFTWARE.
*/
-#include <vector>
-
#include "emufile.h"
-/*bool EMUFILE::readAllBytes(std::vector<uint8_t>* dstbuf, const std::string& fname)
+size_t EMUFILE_MEMORY::_fread(void *ptr, size_t bytes)
{
- EMUFILE_FILE file(fname.c_str(),"rb");
- if(file.fail()) return false;
- int size = file.size();
- dstbuf->resize(size);
- file.fread(&dstbuf->at(0),size);
- return true;
-}*/
-
-size_t EMUFILE_MEMORY::_fread(void *ptr, size_t bytes){
- uint32_t remain = len-pos;
- uint32_t todo = std::min<uint32_t>(remain,(uint32_t)bytes);
- if(len==0)
+ uint32_t remain = this->len - this->pos;
+ uint32_t todo = std::min<uint32_t>(remain, bytes);
+ if (!len)
{
- failbit = true;
+ this->failbit = true;
return 0;
}
- if(todo<=4)
+ if (todo <= 4)
{
- uint8_t* src = buf()+pos;
- uint8_t* dst = (uint8_t*)ptr;
- for(uint32_t i=0;i<todo;i++)
+ uint8_t *src = this->buf() + this->pos;
+ uint8_t *dst = static_cast<uint8_t *>(ptr);
+ for (uint32_t i = 0; i < todo; ++i)
*dst++ = *src++;
}
else
- {
- memcpy(ptr,buf()+pos,todo);
- }
- pos += todo;
- if(todo<bytes)
- failbit = true;
+ memcpy(ptr, this->buf() + this->pos, todo);
+ this->pos += todo;
+ if (todo < bytes)
+ this->failbit = true;
return todo;
}
-/*void EMUFILE_FILE::truncate(int32_t length)
-{
- ::fflush(fp);
- #if defined(_MSC_VER) || defined(__MINGW32__)
- _chsize(_fileno(fp),length);
- #else
- ftruncate(fileno(fp),length);
- #endif
- fclose(fp);
- fp = NULL;
- open(fname.c_str(),mode);
-}*/
-
-
-/*EMUFILE* EMUFILE_FILE::memwrap()
-{
- EMUFILE_MEMORY* mem = new EMUFILE_MEMORY(size());
- if(size()==0) return mem;
- fread(mem->buf(),size());
- return mem;
-}*/
-
-/*EMUFILE* EMUFILE_MEMORY::memwrap()
-{
- return this;
-}*/
-
-/*void EMUFILE::write64le(uint64_t *val)
-{
- write64le(*val);
-}
-
-void EMUFILE::write64le(uint64_t val)
-{
-#ifdef LOCAL_BE
- uint8_t s[8];
- s[0]=(uint8_t)val;
- s[1]=(uint8_t)(val>>8);
- s[2]=(uint8_t)(val>>16);
- s[3]=(uint8_t)(val>>24);
- s[4]=(uint8_t)(val>>32);
- s[5]=(uint8_t)(val>>40);
- s[6]=(uint8_t)(val>>48);
- s[7]=(uint8_t)(val>>56);
- fwrite((char*)&s,8);
-#else
- fwrite(&val,8);
-#endif
-}
-
-size_t EMUFILE::read64le(uint64_t *Bufo)
-{
- uint64_t buf;
- if(fread((char*)&buf,8) != 8)
- return 0;
-#ifndef LOCAL_BE
- *Bufo=buf;
-#else
- *Bufo = LE_TO_LOCAL_64(buf);
-#endif
- return 1;
-}
-
-uint64_t EMUFILE::read64le()
-{
- uint64_t temp;
- read64le(&temp);
- return temp;
-}
-
-void EMUFILE::write32le(uint32_t *val)
-{
- write32le(*val);
-}
-
-void EMUFILE::write32le(uint32_t val)
-{
-#ifdef LOCAL_BE
- uint8_t s[4];
- s[0]=(uint8_t)val;
- s[1]=(uint8_t)(val>>8);
- s[2]=(uint8_t)(val>>16);
- s[3]=(uint8_t)(val>>24);
- fwrite(s,4);
-#else
- fwrite(&val,4);
-#endif
-}
-
-size_t EMUFILE::read32le(int32_t *Bufo) { return read32le((uint32_t *)Bufo); }
-
-size_t EMUFILE::read32le(uint32_t *Bufo)
-{
- uint32_t buf;
- if(fread(&buf,4)<4)
- return 0;
-#ifndef LOCAL_BE
- *(uint32_t *)Bufo=buf;
-#else
- *(uint32_t *)Bufo=((buf&0xFF)<<24)|((buf&0xFF00)<<8)|((buf&0xFF0000)>>8)|((buf&0xFF000000)>>24);
-#endif
- return 1;
-}
-
-uint32_t EMUFILE::read32le()
-{
- uint32_t ret;
- read32le(&ret);
- return ret;
-}
-
-void EMUFILE::write16le(uint16_t *val)
-{
- write16le(*val);
-}
-
-void EMUFILE::write16le(uint16_t val)
-{
-#ifdef LOCAL_BE
- uint8_t s[2];
- s[0]=(uint8_t)val;
- s[1]=(uint8_t)(val>>8);
- fwrite(s,2);
-#else
- fwrite(&val,2);
-#endif
-}
-
-size_t EMUFILE::read16le(int16_t *Bufo) { return read16le((uint16_t *)Bufo); }
-
-size_t EMUFILE::read16le(uint16_t *Bufo)
-{
- uint32_t buf;
- if(fread(&buf,2)<2)
- return 0;
-#ifndef LOCAL_BE
- *(uint16_t *)Bufo=buf;
-#else
- *Bufo = LE_TO_LOCAL_16(buf);
-#endif
- return 1;
-}
-
-uint16_t EMUFILE::read16le()
-{
- uint16_t ret;
- read16le(&ret);
- return ret;
-}
-
-void EMUFILE::write8le(uint8_t *val)
-{
- write8le(*val);
-}
-
-void EMUFILE::write8le(uint8_t val)
-{
- fwrite(&val,1);
-}
-
-size_t EMUFILE::read8le(uint8_t *val)
-{
- return fread(val,1);
-}
-
-uint8_t EMUFILE::read8le()
-{
- uint8_t temp;
- fread(&temp,1);
- return temp;
-}
-
-void EMUFILE::writedouble(double* val)
-{
- write64le(double_to_u64(*val));
-}
-void EMUFILE::writedouble(double val)
-{
- write64le(double_to_u64(val));
-}
-
-double EMUFILE::readdouble()
-{
- double temp;
- readdouble(&temp);
- return temp;
-}
-
-size_t EMUFILE::readdouble(double* val)
-{
- uint64_t temp;
- size_t ret = read64le(&temp);
- *val = u64_to_double(temp);
- return ret;
-}*/
-
--- a/src/in_2sf/desmume/emufile.h
+++ b/src/in_2sf/desmume/emufile.h
@@ -22,7 +22,7 @@
THE SOFTWARE.
*/
-//don't use emufile for files bigger than 2GB! you have been warned! some day this will be fixed.
+// don't use emufile for files bigger than 2GB! you have been warned! some day this will be fixed.
#ifndef EMUFILE_H
#define EMUFILE_H
@@ -35,17 +35,13 @@
#include <cstring>
#include <cstdarg>
#include <cmath>
-
#include "types.h"
#if defined(_MSC_VER) || defined(__MINGW32__)
-/*#define WIN32_LEAN_AND_MEAN
-#define NOMINMAX
-#include <io.h>*/
-#include "windowsh_wrapper.h"
-#include <io.h>
+# include "windowsh_wrapper.h"
+# include <io.h>
#else
-#include <unistd.h>
+# include <unistd.h>
#endif
class EMUFILE
@@ -54,16 +50,8 @@
bool failbit;
public:
- EMUFILE() : failbit(false)
- {
- }
-
- //returns a new EMUFILE which is guranteed to be in memory. the EMUFILE you call this on may be deleted. use the returned EMUFILE in its place
- //virtual EMUFILE* memwrap() = 0;
-
- virtual ~EMUFILE() {}
-
- //static bool readAllBytes(std::vector<uint8_t> *buf, const std::string &fname);
+ EMUFILE() : failbit(false) { }
+ virtual ~EMUFILE() { }
bool fail(bool unset = false)
{
@@ -74,65 +62,21 @@
}
void unfail() { failbit = false; }
- //bool eof() { return size() == ftell(); }
-
size_t fread(void *ptr, size_t bytes)
{
return _fread(ptr, bytes);
}
- //void unget() { fseek(-1, SEEK_CUR); }
-
- //virtuals
-public:
- //virtual FILE *get_fp() = 0;
-
- //virtual int fprintf(const char *format, ...) = 0;
-
- //virtual int fgetc() = 0;
- //virtual int fputc(int c) = 0;
-
+ // virtuals
virtual size_t _fread(void *ptr, size_t bytes) = 0;
-
- //removing these return values for now so we can find any code that might be using them and make sure
- //they handle the return values correctly
-
- //virtual void fwrite(const void *ptr, size_t bytes) = 0;
-
- /*void write64le(uint64_t *val);
- void write64le(uint64_t val);
- size_t read64le(uint64_t *val);
- uint64_t read64le();
- void write32le(uint32_t *val);
- void write32le(int32_t *val) { write32le((uint32_t *)val); }
- void write32le(uint32_t val);
- size_t read32le(uint32_t *val);
- size_t read32le(int32_t *val);
- uint32_t read32le();
- void write16le(uint16_t *val);
- void write16le(int16_t *val) { write16le((uint16_t *)val); }
- void write16le(uint16_t val);
- size_t read16le(int16_t *Bufo);
- size_t read16le(uint16_t *val);
- uint16_t read16le();
- void write8le(uint8_t *val);
- void write8le(uint8_t val);
- size_t read8le(uint8_t *val);
- uint8_t read8le();
- void writedouble(double* val);
- void writedouble(double val);
- double readdouble();
- size_t readdouble(double* val);*/
virtual int fseek(int offset, int origin) = 0;
virtual size_t ftell() = 0;
virtual size_t size() = 0;
-
- //virtual void truncate(int32_t length) = 0;
};
-//todo - handle read-only specially?
+// todo - handle read-only specially?
class EMUFILE_MEMORY : public EMUFILE
{
protected:
@@ -142,144 +86,72 @@
void reserve(uint32_t amt)
{
- if (vec->size() < amt)
- vec->resize(amt);
- }
-
+ if (this->vec->size() < amt)
+ this->vec->resize(amt);
+ }
public:
EMUFILE_MEMORY(std::vector<uint8_t> *underlying) : vec(underlying), ownvec(false), pos(0), len(static_cast<int32_t>(underlying->size())) { }
EMUFILE_MEMORY(uint32_t preallocate) : vec(new std::vector<uint8_t>()), ownvec(true), pos(0), len(0)
{
- vec->resize(preallocate);
- len = preallocate;
- }
- EMUFILE_MEMORY() : vec(new std::vector<uint8_t>()), ownvec(true), pos(0), len(0) { vec->reserve(1024); }
+ this->vec->resize(preallocate);
+ this->len = preallocate;
+ }
+ EMUFILE_MEMORY() : vec(new std::vector<uint8_t>()), ownvec(true), pos(0), len(0)
+ {
+ this->vec->reserve(1024);
+ }
EMUFILE_MEMORY(void *Buf, int32_t Size) : vec(new std::vector<uint8_t>()), ownvec(true), pos(0), len(Size)
{
- vec->resize(Size);
+ this->vec->resize(Size);
if (Size)
- memcpy(&(*vec)[0], Buf, Size);
+ memcpy(&(*this->vec)[0], Buf, Size);
}
~EMUFILE_MEMORY()
{
- if (ownvec)
- delete vec;
- }
-
- //virtual EMUFILE *memwrap();
-
- /*virtual void truncate(int32_t length)
- {
- vec->resize(length);
- len = length;
- if (pos>length)
- pos = length;
- }*/
-
- uint8_t *buf() {
- if(size()==0) reserve(1);
- return &(*vec)[0];
- }
-
- //std::vector<uint8_t> *get_vec() { return vec; };
-
- //virtual FILE *get_fp() { return NULL; }
-
- /*virtual int fprintf(const char *format, ...)
- {
- va_list argptr;
- va_start(argptr, format);
-
- //we dont generate straight into the buffer because it will null terminate (one more byte than we want)
- int amt = vsnprintf(0, 0, format,argptr);
- char *tempbuf = new char[amt + 1];
-
- va_end(argptr);
- va_start(argptr, format);
- vsprintf(tempbuf, format, argptr);
-
- fwrite(tempbuf, amt);
- delete [] tempbuf;
-
- va_end(argptr);
- return amt;
- };*/
-
- /*virtual int fgetc()
- {
- uint8_t temp;
-
- //need an optimized codepath
- //if(_fread(&temp,1) != 1)
- // return EOF;
- //else return temp;
- uint32_t remain = len-pos;
- if (remain < 1)
- {
- failbit = true;
- return -1;
- }
- temp = buf()[pos];
- ++pos;
- return temp;
- }*/
-
- /*virtual int fputc(int c)
- {
- uint8_t temp = static_cast<uint8_t>(c);
- //TODO
- //if(fwrite(&temp,1)!=1) return EOF;
- fwrite(&temp, 1);
-
- return 0;
- }*/
+ if (this->ownvec)
+ delete this->vec;
+ }
+
+ uint8_t *buf()
+ {
+ if (!this->size())
+ this->reserve(1);
+ return &(*this->vec)[0];
+ }
virtual size_t _fread(void *ptr, size_t bytes);
- //removing these return values for now so we can find any code that might be using them and make sure
- //they handle the return values correctly
-
- /*virtual void fwrite(const void *ptr, size_t bytes)
- {
- reserve(pos + bytes);
- memcpy(buf() + pos, ptr, bytes);
- pos += bytes;
- len = std::max(pos, len);
- }*/
-
virtual int fseek(int offset, int origin)
{
- //work differently for read-only...?
+ // work differently for read-only...?
switch (origin)
{
case SEEK_SET:
- pos = offset;
+ this->pos = offset;
break;
case SEEK_CUR:
- pos += offset;
+ this->pos += offset;
break;
case SEEK_END:
- pos = size() + offset;
+ this->pos = this->size() + offset;
break;
default:
assert(false);
}
- reserve(pos);
+ this->reserve(pos);
return 0;
}
virtual size_t ftell()
{
- return pos;
- }
-
- /*void trim()
- {
- vec->resize(len);
- }*/
-
- virtual size_t size() { return len; }
+ return this->pos;
+ }
+
+ virtual size_t size()
+ {
+ return this->len;
+ }
};
class EMUFILE_FILE : public EMUFILE
@@ -288,98 +160,53 @@
FILE *fp;
std::string fname;
char mode[16];
-
private:
void open(const char *fn, const char *Mode)
{
- fp = fopen(fn, Mode);
- if (!fp)
- failbit = true;
+ this->fp = fopen(fn, Mode);
+ if (!this->fp)
+ this->failbit = true;
this->fname = fn;
strcpy(this->mode, Mode);
}
-
public:
- EMUFILE_FILE(const std::string &fn, const char *Mode) { open(fn.c_str(), Mode); }
- EMUFILE_FILE(const char *fn, const char *Mode) { open(fn, Mode); }
+ EMUFILE_FILE(const std::string &fn, const char *Mode)
+ {
+ this->open(fn.c_str(), Mode);
+ }
virtual ~EMUFILE_FILE()
{
- if (fp)
- fclose(fp);
- }
-
- /*virtual FILE *get_fp()
- {
- return fp;
- }*/
-
- //virtual EMUFILE *memwrap();
-
- //bool is_open() { return fp != NULL; }
-
- //virtual void truncate(int32_t length);
-
- /*virtual int fprintf(const char *format, ...)
- {
- va_list argptr;
- va_start(argptr, format);
- int ret = ::vfprintf(fp, format, argptr);
- va_end(argptr);
+ if (this->fp)
+ fclose(this->fp);
+ }
+
+ virtual size_t _fread(void *ptr, size_t bytes)
+ {
+ size_t ret = ::fread(ptr, 1, bytes, this->fp);
+ if (ret < bytes)
+ this->failbit = true;
return ret;
- };*/
-
- /*virtual int fgetc()
- {
- return ::fgetc(fp);
- }*/
-
- /*virtual int fputc(int c)
- {
- return ::fputc(c, fp);
- }*/
-
- virtual size_t _fread(void *ptr, size_t bytes)
- {
- size_t ret = ::fread(ptr, 1, bytes, fp);
- if (ret < bytes)
- failbit = true;
- return ret;
- }
-
- //removing these return values for now so we can find any code that might be using them and make sure
- //they handle the return values correctly
-
- /*virtual void fwrite(const void *ptr, size_t bytes)
- {
- size_t ret = ::fwrite(ptr, 1, bytes, fp);
- if (ret < bytes)
- failbit = true;
- }*/
+ }
virtual int fseek(int offset, int origin)
{
- return ::fseek(fp, offset, origin);
+ return ::fseek(this->fp, offset, origin);
}
virtual size_t ftell()
{
- return static_cast<uint32_t>(::ftell(fp));
+ return static_cast<size_t>(::ftell(this->fp));
}
virtual size_t size()
{
- int oldpos = ftell();
- fseek(0, SEEK_END);
- int len = ftell();
- fseek(oldpos, SEEK_SET);
+ int oldpos = this->ftell();
+ this->fseek(0, SEEK_END);
+ int len = this->ftell();
+ this->fseek(oldpos, SEEK_SET);
return len;
}
-
- /*virtual void fflush()
- {
- ::fflush(fp);
- }*/
};
#endif
--- a/src/in_2sf/desmume/firmware.cpp
+++ b/src/in_2sf/desmume/firmware.cpp
@@ -17,18 +17,17 @@
#include "firmware.h"
#include "NDSSystem.h"
-#include "path.h"
-
-//#define DWNUM(i) ((i) >> 2)
+
static inline uint32_t DWNUM(uint32_t i) { return i >> 2; }
bool CFIRMWARE::getKeyBuf()
{
FILE *file = fopen(CommonSettings.ARM7BIOS, "rb");
- if (!file) return false;
+ if (!file)
+ return false;
fseek(file, 0x30, SEEK_SET);
- size_t res = fread(keyBuf, 4, 0x412, file);
+ size_t res = fread(this->keyBuf, 4, 0x412, file);
fclose(file);
return res == 0x412;
}
@@ -38,19 +37,19 @@
uint32_t Y = ptr[0];
uint32_t X = ptr[1];
- for(uint32_t i = 0x00; i <= 0x0F; i++)
- {
- uint32_t Z = (keyBuf[i] ^ X);
- X = keyBuf[DWNUM(0x048 + (((Z >> 24) & 0xFF) << 2))];
- X = (keyBuf[DWNUM(0x448 + (((Z >> 16) & 0xFF) << 2))] + X);
- X = (keyBuf[DWNUM(0x848 + (((Z >> 8) & 0xFF) << 2))] ^ X);
- X = (keyBuf[DWNUM(0xC48 + ((Z & 0xFF) << 2))] + X);
- X = (Y ^ X);
+ for (uint32_t i = 0x00; i <= 0x0F; ++i)
+ {
+ uint32_t Z = this->keyBuf[i] ^ X;
+ X = this->keyBuf[DWNUM(0x048 + (((Z >> 24) & 0xFF) << 2))];
+ X = this->keyBuf[DWNUM(0x448 + (((Z >> 16) & 0xFF) << 2))] + X;
+ X = this->keyBuf[DWNUM(0x848 + (((Z >> 8) & 0xFF) << 2))] ^ X;
+ X = this->keyBuf[DWNUM(0xC48 + ((Z & 0xFF) << 2))] + X;
+ X = Y ^ X;
Y = Z;
}
- ptr[0] = (X ^ keyBuf[DWNUM(0x40)]);
- ptr[1] = (Y ^ keyBuf[DWNUM(0x44)]);
+ ptr[0] = X ^ this->keyBuf[DWNUM(0x40)];
+ ptr[1] = Y ^ this->keyBuf[DWNUM(0x44)];
}
void CFIRMWARE::crypt64BitDown(uint32_t *ptr)
@@ -58,361 +57,327 @@
uint32_t Y = ptr[0];
uint32_t X = ptr[1];
- for(uint32_t i = 0x11; i >= 0x02; i--)
- {
- uint32_t Z = (keyBuf[i] ^ X);
- X = keyBuf[DWNUM(0x048 + (((Z >> 24) & 0xFF) << 2))];
- X = (keyBuf[DWNUM(0x448 + (((Z >> 16) & 0xFF) << 2))] + X);
- X = (keyBuf[DWNUM(0x848 + (((Z >> 8) & 0xFF) << 2))] ^ X);
- X = (keyBuf[DWNUM(0xC48 + ((Z & 0xFF) << 2))] + X);
- X = (Y ^ X);
+ for (uint32_t i = 0x11; i >= 0x02; --i)
+ {
+ uint32_t Z = this->keyBuf[i] ^ X;
+ X = this->keyBuf[DWNUM(0x048 + (((Z >> 24) & 0xFF) << 2))];
+ X = this->keyBuf[DWNUM(0x448 + (((Z >> 16) & 0xFF) << 2))] + X;
+ X = this->keyBuf[DWNUM(0x848 + (((Z >> 8) & 0xFF) << 2))] ^ X;
+ X = this->keyBuf[DWNUM(0xC48 + ((Z & 0xFF) << 2))] + X;
+ X = Y ^ X;
Y = Z;
}
- ptr[0] = (X ^ keyBuf[DWNUM(0x04)]);
- ptr[1] = (Y ^ keyBuf[DWNUM(0x00)]);
-}
-
-//#define bswap32(val) (((val & 0x000000FF) << 24) | ((val & 0x0000FF00) << 8) | ((val & 0x00FF0000) >> 8) | ((val & 0xFF000000) >> 24))
+ ptr[0] = X ^ this->keyBuf[DWNUM(0x04)];
+ ptr[1] = Y ^ this->keyBuf[DWNUM(0x00)];
+}
+
static inline uint32_t bswap32(uint32_t val) { return ((val & 0x000000FF) << 24) | ((val & 0x0000FF00) << 8) | ((val & 0x00FF0000) >> 8) | ((val & 0xFF000000) >> 24); }
void CFIRMWARE::applyKeycode(uint32_t modulo)
{
- crypt64BitUp(&keyCode[1]);
- crypt64BitUp(&keyCode[0]);
-
- uint32_t scratch[2] = {0x00000000, 0x00000000};
-
- for(uint32_t i = 0; i <= 0x44; i += 4)
- {
- keyBuf[DWNUM(i)] = (keyBuf[DWNUM(i)] ^ bswap32(keyCode[DWNUM(i % modulo)]));
- }
-
- for(uint32_t i = 0; i <= 0x1040; i += 8)
- {
- crypt64BitUp(scratch);
- keyBuf[DWNUM(i)] = scratch[1];
- keyBuf[DWNUM(i+4)] = scratch[0];
- }
-}
-//#undef bswap32
+ this->crypt64BitUp(&this->keyCode[1]);
+ this->crypt64BitUp(&this->keyCode[0]);
+
+ uint32_t scratch[] = { 0x00000000, 0x00000000 };
+
+ for (uint32_t i = 0; i <= 0x44; i += 4)
+ this->keyBuf[DWNUM(i)] = this->keyBuf[DWNUM(i)] ^ bswap32(this->keyCode[DWNUM(i % modulo)]);
+
+ for (uint32_t i = 0; i <= 0x1040; i += 8)
+ {
+ this->crypt64BitUp(scratch);
+ this->keyBuf[DWNUM(i)] = scratch[1];
+ this->keyBuf[DWNUM(i + 4)] = scratch[0];
+ }
+}
bool CFIRMWARE::initKeycode(uint32_t idCode, int level, uint32_t modulo)
{
- if(getKeyBuf() == false)
- return false;
-
- keyCode[0] = idCode;
- keyCode[1] = (idCode >> 1);
- keyCode[2] = (idCode << 1);
-
- if(level >= 1) applyKeycode(modulo);
- if(level >= 2) applyKeycode(modulo);
-
- keyCode[1] <<= 1;
- keyCode[2] >>= 1;
-
- if(level >= 3) applyKeycode(modulo);
+ if (!this->getKeyBuf())
+ return false;
+
+ this->keyCode[0] = idCode;
+ this->keyCode[1] = idCode >> 1;
+ this->keyCode[2] = idCode << 1;
+
+ if (level >= 1)
+ this->applyKeycode(modulo);
+ if (level >= 2)
+ this->applyKeycode(modulo);
+
+ this->keyCode[1] <<= 1;
+ this->keyCode[2] >>= 1;
+
+ if (level >= 3)
+ this->applyKeycode(modulo);
return true;
}
uint16_t CFIRMWARE::getBootCodeCRC16()
{
- unsigned int i, j;
uint32_t crc = 0xFFFF;
- const uint16_t val[8] = {0xC0C1, 0xC181, 0xC301, 0xC601, 0xCC01, 0xD801, 0xF001, 0xA001};
-
- for(i = 0; i < size9; i++)
- {
- crc = (crc ^ tmp_data9[i]);
-
- for(j = 0; j < 8; j++)
- {
- if(crc & 0x0001)
- crc = ((crc >> 1) ^ (val[j] << (7-j)));
+ const uint16_t val[] = { 0xC0C1, 0xC181, 0xC301, 0xC601, 0xCC01, 0xD801, 0xF001, 0xA001 };
+
+ unsigned i, j;
+ for (i = 0; i < this->size9; ++i)
+ {
+ crc ^= this->tmp_data9[i];
+
+ for (j = 0; j < 8; ++j)
+ {
+ if (crc & 0x0001)
+ crc = (crc >> 1) ^ (val[j] << (7 - j));
else
- crc = (crc >> 1);
- }
- }
-
- for(i = 0; i < size7; i++)
- {
- crc = (crc ^ tmp_data7[i]);
-
- for(j = 0; j < 8; j++)
- {
- if(crc & 0x0001)
- crc = ((crc >> 1) ^ (val[j] << (7-j)));
+ crc >>= 1;
+ }
+ }
+
+ for (i = 0; i < this->size7; ++i)
+ {
+ crc ^= this->tmp_data7[i];
+
+ for (j = 0; j < 8; ++j)
+ {
+ if (crc & 0x0001)
+ crc = (crc >> 1) ^ (val[j] << (7 - j));
else
- crc = (crc >> 1);
+ crc >>= 1;
}
}
return crc & 0xFFFF;
}
-uint32_t CFIRMWARE::decrypt(const uint8_t *in, uint8_t* &out)
+uint32_t CFIRMWARE::decrypt(const uint8_t *in, std::unique_ptr<uint8_t[]> &out)
{
uint32_t curBlock[2] = { 0 };
- uint32_t blockSize = 0;
- uint32_t xLen = 0;
-
- uint32_t i = 0, j = 0;
+
uint32_t xIn = 4, xOut = 0;
- uint32_t len = 0;
- uint32_t offset = 0;
- uint32_t windowOffset = 0;
- uint8_t d = 0;
-
- uint16_t data = 0;
memcpy(curBlock, in, 8);
- crypt64BitDown(curBlock);
- blockSize = (curBlock[0] >> 8);
-
- if (blockSize == 0) return 0;
-
- out = new uint8_t [blockSize];
- if (!out ) return 0;
- memset(out, 0xFF, blockSize);
-
- xLen = blockSize;
- while(xLen > 0)
- {
- d = T1ReadByte((uint8_t*)curBlock, (xIn % 8));
- xIn++;
- if((xIn % 8) == 0)
+ this->crypt64BitDown(curBlock);
+ uint32_t blockSize = curBlock[0] >> 8;
+
+ if (!blockSize)
+ return 0;
+
+ out.reset(new uint8_t[blockSize]);
+ if (!out)
+ return 0;
+ memset(&out[0], 0xFF, blockSize);
+
+ uint32_t xLen = blockSize;
+ while (xLen > 0)
+ {
+ uint8_t d = T1ReadByte(reinterpret_cast<uint8_t *>(curBlock), xIn % 8);
+ ++xIn;
+ if (!(xIn % 8))
{
memcpy(curBlock, in + xIn, 8);
- crypt64BitDown(curBlock);
- }
-
- for(i = 0; i < 8; i++)
- {
- if(d & 0x80)
+ this->crypt64BitDown(curBlock);
+ }
+
+ for (uint32_t i = 0; i < 8; ++i)
+ {
+ if (d & 0x80)
{
- data = (T1ReadByte((uint8_t*)curBlock, (xIn % 8)) << 8);
- xIn++;
- if((xIn % 8) == 0)
+ uint16_t data = T1ReadByte(reinterpret_cast<uint8_t *>(curBlock), xIn % 8) << 8;
+ ++xIn;
+ if (!(xIn % 8))
{
memcpy(curBlock, in + xIn, 8);
- crypt64BitDown(curBlock);
+ this->crypt64BitDown(curBlock);
}
- data |= T1ReadByte((uint8_t*)curBlock, (xIn % 8));
- xIn++;
- if((xIn % 8) == 0)
+ data |= T1ReadByte(reinterpret_cast<uint8_t *>(curBlock), xIn % 8);
+ ++xIn;
+ if (!(xIn % 8))
{
memcpy(curBlock, in + xIn, 8);
- crypt64BitDown(curBlock);
+ this->crypt64BitDown(curBlock);
}
- len = (data >> 12) + 3;
- offset = (data & 0xFFF);
- windowOffset = (xOut - offset - 1);
-
- for(j = 0; j < len; j++)
+ uint32_t len = (data >> 12) + 3;
+ uint32_t offset = data & 0xFFF;
+ uint32_t windowOffset = xOut - offset - 1;
+
+ for (uint32_t j = 0; j < len; ++j)
{
- T1WriteByte(out, xOut, T1ReadByte(out, windowOffset));
- xOut++;
- windowOffset++;
-
- xLen--;
- if(xLen == 0) return blockSize;
+ T1WriteByte(&out[0], xOut, T1ReadByte(&out[0], windowOffset));
+ ++xOut;
+ ++windowOffset;
+
+ --xLen;
+ if (!xLen)
+ return blockSize;
}
}
else
{
- T1WriteByte(out, xOut, T1ReadByte((uint8_t*)curBlock, (xIn % 8)));
- xOut++;
- xIn++;
- if((xIn % 8) == 0)
+ T1WriteByte(&out[0], xOut, T1ReadByte(reinterpret_cast<uint8_t *>(curBlock), xIn % 8));
+ ++xOut;
+ ++xIn;
+ if (!(xIn % 8))
{
memcpy(curBlock, in + xIn, 8);
- crypt64BitDown(curBlock);
+ this->crypt64BitDown(curBlock);
}
- xLen--;
- if(xLen == 0) return blockSize;
+ --xLen;
+ if (!xLen)
+ return blockSize;
}
- d = ((d << 1) & 0xFF);
+ d = (d << 1) & 0xFF;
}
}
return blockSize;
}
-uint32_t CFIRMWARE::decompress(const uint8_t *in, uint8_t* &out)
+uint32_t CFIRMWARE::decompress(const uint8_t *in, std::unique_ptr<uint8_t[]> &out)
{
uint32_t curBlock[2] = { 0 };
- uint32_t blockSize = 0;
- uint32_t xLen = 0;
-
- uint32_t i = 0, j = 0;
+
uint32_t xIn = 4, xOut = 0;
- uint32_t len = 0;
- uint32_t offset = 0;
- uint32_t windowOffset = 0;
- uint8_t d = 0;
- uint16_t data = 0;
memcpy(curBlock, in, 8);
- blockSize = (curBlock[0] >> 8);
-
- if (blockSize == 0) return 0;
-
- out = new uint8_t [blockSize];
- if (!out ) return 0;
- memset(out, 0xFF, blockSize);
-
- xLen = blockSize;
- while(xLen > 0)
- {
- d = T1ReadByte((uint8_t*)curBlock, (xIn % 8));
- xIn++;
- if((xIn % 8) == 0)
- {
+ uint32_t blockSize = curBlock[0] >> 8;
+
+ if (!blockSize)
+ return 0;
+
+ out.reset(new uint8_t[blockSize]);
+ if (!out)
+ return 0;
+ memset(&out[0], 0xFF, blockSize);
+
+ uint32_t xLen = blockSize;
+ while (xLen > 0)
+ {
+ uint8_t d = T1ReadByte(reinterpret_cast<uint8_t *>(curBlock), xIn % 8);
+ ++xIn;
+ if (!(xIn % 8))
memcpy(curBlock, in + xIn, 8);
- }
-
- for(i = 0; i < 8; i++)
- {
- if(d & 0x80)
+
+ for (uint32_t i = 0; i < 8; ++i)
+ {
+ if (d & 0x80)
{
- data = (T1ReadByte((uint8_t*)curBlock, (xIn % 8)) << 8);
- xIn++;
- if((xIn % 8) == 0)
+ uint16_t data = T1ReadByte(reinterpret_cast<uint8_t *>(curBlock), xIn % 8) << 8;
+ ++xIn;
+ if (!(xIn % 8))
+ memcpy(curBlock, in + xIn, 8);
+ data |= T1ReadByte(reinterpret_cast<uint8_t *>(curBlock), xIn % 8);
+ ++xIn;
+ if (!(xIn % 8))
+ memcpy(curBlock, in + xIn, 8);
+
+ uint32_t len = (data >> 12) + 3;
+ uint32_t offset = data & 0xFFF;
+ uint32_t windowOffset = xOut - offset - 1;
+
+ for (uint32_t j = 0; j < len; ++j)
{
- memcpy(curBlock, in + xIn, 8);
- }
- data |= T1ReadByte((uint8_t*)curBlock, (xIn % 8));
- xIn++;
- if((xIn % 8) == 0)
- {
- memcpy(curBlock, in + xIn, 8);
- }
-
- len = (data >> 12) + 3;
- offset = (data & 0xFFF);
- windowOffset = (xOut - offset - 1);
-
- for(j = 0; j < len; j++)
- {
- T1WriteByte(out, xOut, T1ReadByte(out, windowOffset));
- xOut++;
- windowOffset++;
-
- xLen--;
- if(xLen == 0) return blockSize;
+ T1WriteByte(&out[0], xOut, T1ReadByte(&out[0], windowOffset));
+ ++xOut;
+ ++windowOffset;
+
+ --xLen;
+ if (!xLen)
+ return blockSize;
}
}
else
{
- T1WriteByte(out, xOut, T1ReadByte((uint8_t*)curBlock, (xIn % 8)));
- xOut++;
- xIn++;
- if((xIn % 8) == 0)
- {
+ T1WriteByte(&out[0], xOut, T1ReadByte(reinterpret_cast<uint8_t *>(curBlock), xIn % 8));
+ ++xOut;
+ ++xIn;
+ if (!(xIn % 8))
memcpy(curBlock, in + xIn, 8);
- }
-
- xLen--;
- if(xLen == 0) return blockSize;
+
+ --xLen;
+ if (!xLen)
+ return blockSize;
}
- d = ((d << 1) & 0xFF);
+ d = (d << 1) & 0xFF;
}
}
return blockSize;
}
-//================================================================================
+
+// ================================================================================
bool CFIRMWARE::load()
{
- uint32_t size = 0;
- uint8_t *data = NULL;
- uint16_t shift1 = 0, shift2 = 0, shift3 = 0, shift4 = 0;
- uint32_t part1addr = 0, part2addr = 0/*, part3addr = 0, part4addr = 0, part5addr = 0*/;
- uint32_t part1ram = 0, part2ram = 0;
-
- uint32_t src = 0;
-
- if (CommonSettings.UseExtFirmware == false)
- return false;
- if (strlen(CommonSettings.Firmware) == 0)
- return false;
-
- FILE *fp = fopen(CommonSettings.Firmware, "rb");
+ if (!CommonSettings.UseExtFirmware)
+ return false;
+ if (!strlen(CommonSettings.Firmware))
+ return false;
+
+ FILE *fp = fopen(CommonSettings.Firmware, "rb");
if (!fp)
return false;
fseek(fp, 0, SEEK_END);
- size = ftell(fp);
+ uint32_t size = ftell(fp);
fseek(fp, 0, SEEK_SET);
- if( (size != 256*1024) && (size != 512*1024) )
+ if (size != 262144 && size != 524288)
{
fclose(fp);
return false;
}
#if 1
- if (size == 512*1024)
- {
- //INFO("ERROR: 32Mbit (512Kb) firmware not supported\n");
+ if (size == 524288)
+ {
fclose(fp);
return false;
}
#endif
- data = new uint8_t [size];
+ auto data = std::unique_ptr<uint8_t[]>(new uint8_t[size]);
if (!data)
{
fclose(fp);
return false;
}
- if (fread(data, 1, size, fp) != size)
- {
- delete [] data;
- fclose(fp);
- return false;
- }
-
- memcpy(&header, data, sizeof(header));
- if ((header.fw_identifier[0] != 'M') ||
- (header.fw_identifier[1] != 'A') ||
- (header.fw_identifier[2] != 'C'))
- {
- delete [] data;
- fclose(fp);
- return false;
- }
-
- shift1 = ((header.shift_amounts >> 0) & 0x07);
- shift2 = ((header.shift_amounts >> 3) & 0x07);
- shift3 = ((header.shift_amounts >> 6) & 0x07);
- shift4 = ((header.shift_amounts >> 9) & 0x07);
+ if (fread(&data[0], 1, size, fp) != size)
+ {
+ fclose(fp);
+ return false;
+ }
+
+ memcpy(&header, &data[0], sizeof(header));
+ if (header.fw_identifier[0] != 'M' || header.fw_identifier[1] != 'A' || header.fw_identifier[2] != 'C')
+ {
+ fclose(fp);
+ return false;
+ }
+
+ uint16_t shift1 = header.shift_amounts & 0x07;
+ uint16_t shift2 = (header.shift_amounts >> 3) & 0x07;
+ uint16_t shift3 = (header.shift_amounts >> 6) & 0x07;
+ uint16_t shift4 = (header.shift_amounts >> 9) & 0x07;
// todo - add support for 512Kb
- part1addr = (header.part1_rom_boot9_addr << (2 + shift1));
- part1ram = (0x02800000 - (header.part1_ram_boot9_addr << (2+shift2)));
- part2addr = (header.part2_rom_boot7_addr << (2+shift3));
- part2ram = (0x03810000 - (header.part2_ram_boot7_addr << (2+shift4)));
- //part3addr = (header.part3_rom_gui9_addr << 3);
- //part4addr = (header.part4_rom_wifi7_addr << 3);
- //part5addr = (header.part5_data_gfx_addr << 3);
-
- ARM9bootAddr = part1ram;
- ARM7bootAddr = part2ram;
-
- if(initKeycode(T1ReadLong(data, 0x08), 1, 0xC) == false)
- {
- delete [] data;
+ uint32_t part1addr = header.part1_rom_boot9_addr << (2 + shift1);
+ uint32_t part1ram = 0x02800000 - (header.part1_ram_boot9_addr << (2 + shift2));
+ uint32_t part2addr = header.part2_rom_boot7_addr << (2 + shift3);
+ uint32_t part2ram = 0x03810000 - (header.part2_ram_boot7_addr << (2 + shift4));
+
+ this->ARM9bootAddr = part1ram;
+ this->ARM7bootAddr = part2ram;
+
+ if (!this->initKeycode(T1ReadLong(&data[0], 0x08), 1, 0xC))
+ {
fclose(fp);
return false;
}
#if 0
- crypt64BitDown((uint32_t*)&data[0x18]);
+ this->crypt64BitDown(reinterpret_cast<uint32_t *>(&data[0x18]));
#else
// fix touch coords
data[0x18] = 0x00;
@@ -426,267 +391,181 @@
data[0x1F] = 0x00;
#endif
- if(initKeycode(T1ReadLong(data, 0x08), 2, 0xC) == false)
- {
- delete [] data;
- fclose(fp);
- return false;
- }
-
- size9 = decrypt(data + part1addr, tmp_data9);
- if (!tmp_data9)
- {
- delete [] data;
- fclose(fp);
- return false;
- }
-
- size7 = decrypt(data + part2addr, tmp_data7);
- if (!tmp_data7)
- {
- delete [] tmp_data9;
- delete [] data;
- fclose(fp);
- return false;
- }
-
- uint16_t crc16_mine = getBootCodeCRC16();
+ if (!this->initKeycode(T1ReadLong(&data[0], 0x08), 2, 0xC))
+ {
+ fclose(fp);
+ return false;
+ }
+
+ this->size9 = this->decrypt(&data[part1addr], this->tmp_data9);
+ if (!this->tmp_data9)
+ {
+ fclose(fp);
+ return false;
+ }
+
+ this->size7 = this->decrypt(&data[part2addr], this->tmp_data7);
+ if (!this->tmp_data7)
+ {
+ this->tmp_data9.reset();
+ fclose(fp);
+ return false;
+ }
+
+ uint16_t crc16_mine = this->getBootCodeCRC16();
if (crc16_mine != header.part12_boot_crc16)
{
- //INFO("Firmware: ERROR: the boot code CRC16 (0x%04X) doesn't match the value in the firmware header (0x%04X)", crc16_mine, header.part12_boot_crc16);
- delete [] tmp_data9;
- delete [] tmp_data7;
- delete [] data;
+ this->tmp_data9.reset();
+ this->tmp_data7.reset();
fclose(fp);
return false;
}
// Copy firmware boot codes to their respective locations
+ uint32_t src = 0;
+ for (uint32_t i = 0; i < (this->size9 >> 2); ++i)
+ {
+ _MMU_write32<ARMCPU_ARM9>(part1ram, T1ReadLong(&this->tmp_data9[0], src));
+ src += 4;
+ part1ram += 4;
+ }
+
src = 0;
- for(uint32_t i = 0; i < (size9 >> 2); i++)
- {
- _MMU_write32<ARMCPU_ARM9>(part1ram, T1ReadLong(tmp_data9, src));
- src += 4; part1ram += 4;
- }
-
- src = 0;
- for(uint32_t i = 0; i < (size7 >> 2); i++)
- {
- _MMU_write32<ARMCPU_ARM7>(part2ram, T1ReadLong(tmp_data7, src));
- src += 4; part2ram += 4;
- }
- delete [] tmp_data7;
- delete [] tmp_data9;
-
- patched = false;
+ for (uint32_t i = 0; i < (this->size7 >> 2); ++i)
+ {
+ _MMU_write32<ARMCPU_ARM7>(part2ram, T1ReadLong(&this->tmp_data7[0], src));
+ src += 4;
+ part2ram += 4;
+ }
+ this->tmp_data7.reset();
+ this->tmp_data9.reset();
+
+ this->patched = false;
if (data[0x17C] != 0xFF)
- patched = true;
-
- //INFO("Firmware:\n");
- //INFO("- path: %s\n", CommonSettings.Firmware);
- //INFO("- size: %i bytes (%i Mbit)\n", size, size/1024/8);
- //INFO("- CRC : 0x%04X\n", header.part12_boot_crc16);
- //INFO("- header: \n");
- //INFO(" * size firmware %i\n", ((header.shift_amounts >> 12) & 0xF) * 128 * 1024);
- //INFO(" * ARM9 boot code address: 0x%08X\n", part1addr);
- //INFO(" * ARM9 boot code RAM address: 0x%08X\n", ARM9bootAddr);
- //INFO(" * ARM9 unpacked size: 0x%08X (%i) bytes\n", size9, size9);
- //INFO(" * ARM9 GUI code address: 0x%08X\n", part3addr);
- //INFO("\n");
- //INFO(" * ARM7 boot code address: 0x%08X\n", part2addr);
- //INFO(" * ARM7 boot code RAM address: 0x%08X\n", ARM7bootAddr);
- //INFO(" * ARM7 WiFi code address: 0x%08X\n", part4addr);
- //INFO(" * ARM7 unpacked size: 0x%08X (%i) bytes\n", size7, size7);
- //INFO("\n");
- //INFO(" * Data/GFX address: 0x%08X\n", part5addr);
-
- if (patched)
+ this->patched = true;
+
+ if (this->patched)
{
uint32_t patch_offset = 0x3FC80;
if (data[0x17C] > 1)
patch_offset = 0x3F680;
- memcpy(&header, data + patch_offset, sizeof(header));
-
- shift1 = ((header.shift_amounts >> 0) & 0x07);
- shift2 = ((header.shift_amounts >> 3) & 0x07);
- shift3 = ((header.shift_amounts >> 6) & 0x07);
- shift4 = ((header.shift_amounts >> 9) & 0x07);
+ memcpy(&header, &data[patch_offset], sizeof(header));
+
+ shift1 = header.shift_amounts & 0x07;
+ shift2 = (header.shift_amounts >> 3) & 0x07;
+ shift3 = (header.shift_amounts >> 6) & 0x07;
+ shift4 = (header.shift_amounts >> 9) & 0x07;
// todo - add support for 512Kb
- part1addr = (header.part1_rom_boot9_addr << (2 + shift1));
- part1ram = (0x02800000 - (header.part1_ram_boot9_addr << (2+shift2)));
- part2addr = (header.part2_rom_boot7_addr << (2+shift3));
- part2ram = (0x03810000 - (header.part2_ram_boot7_addr << (2+shift4)));
-
- ARM9bootAddr = part1ram;
- ARM7bootAddr = part2ram;
-
- size9 = decompress(data + part1addr, tmp_data9);
- if (!tmp_data9)
- {
- delete [] data;
+ part1addr = header.part1_rom_boot9_addr << (2 + shift1);
+ part1ram = 0x02800000 - (header.part1_ram_boot9_addr << (2 + shift2));
+ part2addr = header.part2_rom_boot7_addr << (2 + shift3);
+ part2ram = 0x03810000 - (header.part2_ram_boot7_addr << (2 + shift4));
+
+ this->ARM9bootAddr = part1ram;
+ this->ARM7bootAddr = part2ram;
+
+ this->size9 = this->decompress(&data[part1addr], this->tmp_data9);
+ if (!this->tmp_data9)
+ {
fclose(fp);
return false;
}
- size7 = decompress(data + part2addr, tmp_data7);
- if (!tmp_data7)
- {
- delete [] tmp_data9;
- delete [] data;
+ this->size7 = this->decompress(&data[part2addr], this->tmp_data7);
+ if (!this->tmp_data7)
+ {
+ this->tmp_data9.reset();
fclose(fp);
return false;
};
// Copy firmware boot codes to their respective locations
src = 0;
- for(uint32_t i = 0; i < (size9 >> 2); i++)
- {
- _MMU_write32<ARMCPU_ARM9>(part1ram, T1ReadLong(tmp_data9, src));
- src += 4; part1ram += 4;
+ for (uint32_t i = 0; i < (this->size9 >> 2); ++i)
+ {
+ _MMU_write32<ARMCPU_ARM9>(part1ram, T1ReadLong(&this->tmp_data9[0], src));
+ src += 4;
+ part1ram += 4;
}
src = 0;
- for(uint32_t i = 0; i < (size7 >> 2); i++)
- {
- _MMU_write32<ARMCPU_ARM7>(part2ram, T1ReadLong(tmp_data7, src));
- src += 4; part2ram += 4;
- }
- delete [] tmp_data7;
- delete [] tmp_data9;
-
- //INFO("\nFlashme:\n");
- //INFO("- header: \n");
- //INFO(" * ARM9 boot code address: 0x%08X\n", part1addr);
- //INFO(" * ARM9 boot code RAM address: 0x%08X\n", ARM9bootAddr);
- //INFO(" * ARM9 unpacked size: 0x%08X (%i) bytes\n", size9, size9);
- //INFO("\n");
- //INFO(" * ARM7 boot code address: 0x%08X\n", part2addr);
- //INFO(" * ARM7 boot code RAM address: 0x%08X\n", ARM7bootAddr);
- //INFO(" * ARM7 unpacked size: 0x%08X (%i) bytes\n", size7, size7);
- }
-
- // Generate the path for the external firmware config file.
- std::string extFilePath = CFIRMWARE::GetExternalFilePath();
- strncpy(MMU.fw.userfile, extFilePath.c_str(), MAX_PATH);
-
- fclose(fp);
- fp = fopen(MMU.fw.userfile, "rb");
- if (fp)
- {
- char buf[0x300];
- memset(buf, 0, 0x300);
- if (fread(buf, 1, 0x100, fp) == 0x100)
- {
- printf("- loaded from %s:\n", MMU.fw.userfile);
- memcpy(&data[0x3FE00], &buf[0], 0x100);
- memcpy(&data[0x3FF00], &buf[0], 0x100);
- printf(" * User settings\n");
- memset(buf, 0, 0x100);
- if (fread(buf, 1, 0x1D6, fp) == 0x1D6)
- {
- memcpy(&data[0x002A], &buf[0], 0x1D6);
- printf(" * WiFi settings\n");
-
- memset(buf, 0, 0x1D6);
- if (fread(buf, 1, 0x300, fp) == 0x300)
- {
- memcpy(&data[0x3FA00], &buf[0], 0x300);
- printf(" * WiFi AP settings\n");
- }
- }
-
- }
- fclose(fp);
- }
- printf("\n");
+ for (uint32_t i = 0; i < (this->size7 >> 2); ++i)
+ {
+ _MMU_write32<ARMCPU_ARM7>(part2ram, T1ReadLong(&this->tmp_data7[0], src));
+ src += 4;
+ part2ram += 4;
+ }
+ this->tmp_data7.reset();
+ this->tmp_data9.reset();
+ }
// TODO: add 512Kb support
- memcpy(&MMU.fw.data[0], data, 256*1024);
- MMU.fw.fp = NULL;
-
- delete [] data; data = NULL;
+ memcpy(&MMU.fw.data[0], &data[0], 262144);
+ MMU.fw.fp = nullptr;
+
return true;
}
-std::string CFIRMWARE::GetExternalFilePath()
-{
- std::string fwPath = CommonSettings.Firmware;
- std::string fwFileName = Path::GetFileNameFromPathWithoutExt(fwPath);
- std::string configPath = path.pathToBattery;
- std::string finalPath = configPath + DIRECTORY_DELIMITER_CHAR + fwFileName + FILE_EXT_DELIMITER_CHAR + FW_CONFIG_FILE_EXT;
-
- return finalPath;
-}
-
-//=====================================================================================================
-static uint32_t
-calc_CRC16( uint32_t start, const uint8_t *data, int count) {
- int i,j;
+// =====================================================================================================
+static uint32_t calc_CRC16(uint32_t start, const uint8_t *data, int count)
+{
uint32_t crc = start & 0xffff;
- const uint16_t val[8] = { 0xC0C1,0xC181,0xC301,0xC601,0xCC01,0xD801,0xF001,0xA001 };
- for(i = 0; i < count; i++)
- {
- crc = crc ^ data[i];
-
- for(j = 0; j < 8; j++) {
- int do_bit = 0;
-
- if ( crc & 0x1)
- do_bit = 1;
-
- crc = crc >> 1;
-
- if ( do_bit) {
- crc = crc ^ (val[j] << (7-j));
- }
+ const uint16_t val[] = { 0xC0C1, 0xC181, 0xC301, 0xC601, 0xCC01, 0xD801, 0xF001, 0xA001 };
+ for (int i = 0; i < count; ++i)
+ {
+ crc ^= data[i];
+
+ for (int j = 0; j < 8; ++j)
+ {
+ bool do_bit = false;
+
+ if (crc & 0x1)
+ do_bit = true;
+
+ crc >>= 1;
+
+ if (do_bit)
+ crc ^= val[j] << (7 - j);
}
}
return crc;
}
-int copy_firmware_user_data( uint8_t *dest_buffer, const uint8_t *fw_data)
+int copy_firmware_user_data(uint8_t *dest_buffer, const uint8_t *fw_data)
{
/*
- * Determine which of the two user settings in the firmware is the current
- * and valid one and then copy this into the destination buffer.
- *
- * The current setting will have a greater count.
- * Settings are only valid if its CRC16 is correct.
- */
- int user1_valid = 0;
- int user2_valid = 0;
- uint32_t user_settings_offset;
- uint32_t fw_crc;
- uint32_t crc;
+ * Determine which of the two user settings in the firmware is the current
+ * and valid one and then copy this into the destination buffer.
+ *
+ * The current setting will have a greater count.
+ * Settings are only valid if its CRC16 is correct.
+ */
int copy_good = 0;
- user_settings_offset = fw_data[0x20];
+ uint32_t user_settings_offset = fw_data[0x20];
user_settings_offset |= fw_data[0x21] << 8;
user_settings_offset <<= 3;
- if ( user_settings_offset <= 0x3FE00) {
+ if (user_settings_offset <= 0x3FE00)
+ {
int32_t copy_settings_offset = -1;
- crc = calc_CRC16( 0xffff, &fw_data[user_settings_offset],
- NDS_FW_USER_SETTINGS_MEM_BYTE_COUNT);
- fw_crc = fw_data[user_settings_offset + 0x72];
+ uint32_t crc = calc_CRC16(0xffff, &fw_data[user_settings_offset], NDS_FW_USER_SETTINGS_MEM_BYTE_COUNT);
+ uint32_t fw_crc = fw_data[user_settings_offset + 0x72];
fw_crc |= fw_data[user_settings_offset + 0x73] << 8;
- if ( crc == fw_crc) {
- user1_valid = 1;
- }
-
- crc = calc_CRC16( 0xffff, &fw_data[user_settings_offset + 0x100],
- NDS_FW_USER_SETTINGS_MEM_BYTE_COUNT);
+ bool user1_valid = crc == fw_crc;
+
+ crc = calc_CRC16(0xffff, &fw_data[user_settings_offset + 0x100], NDS_FW_USER_SETTINGS_MEM_BYTE_COUNT);
fw_crc = fw_data[user_settings_offset + 0x100 + 0x72];
fw_crc |= fw_data[user_settings_offset + 0x100 + 0x73] << 8;
- if ( crc == fw_crc) {
- user2_valid = 1;
- }
-
- if ( user1_valid) {
- if ( user2_valid) {
+ bool user2_valid = crc == fw_crc;
+
+ if (user1_valid)
+ {
+ if (user2_valid)
+ {
uint16_t count1, count2;
count1 = fw_data[user_settings_offset + 0x70];
@@ -695,25 +574,21 @@
count2 = fw_data[user_settings_offset + 0x100 + 0x70];
count2 |= fw_data[user_settings_offset + 0x100 + 0x71] << 8;
- if ( count2 > count1) {
+ if (count2 > count1)
copy_settings_offset = user_settings_offset + 0x100;
- }
- else {
+ else
copy_settings_offset = user_settings_offset;
- }
}
- else {
+ else
copy_settings_offset = user_settings_offset;
- }
- }
- else if ( user2_valid) {
+ }
+ else if (user2_valid)
/* copy the second user settings */
copy_settings_offset = user_settings_offset + 0x100;
- }
-
- if ( copy_settings_offset > 0) {
- memcpy( dest_buffer, &fw_data[copy_settings_offset],
- NDS_FW_USER_SETTINGS_MEM_BYTE_COUNT);
+
+ if (copy_settings_offset > 0)
+ {
+ memcpy(dest_buffer, &fw_data[copy_settings_offset], NDS_FW_USER_SETTINGS_MEM_BYTE_COUNT);
copy_good = 1;
}
}
@@ -721,167 +596,12 @@
return copy_good;
}
-/*static void fill_user_data_area( struct NDS_fw_config_data *user_settings,uint8_t *data, int count)
-{
- uint32_t crc;
- int i;
- //uint8_t *ts_cal_data_area;
-
- memset( data, 0, 0x100);
-
- // version
- data[0x00] = 5;
- data[0x01] = 0;
-
- // colour
- data[0x02] = user_settings->fav_colour;
-
- // birthday month and day
- data[0x03] = user_settings->birth_month;
- data[0x04] = user_settings->birth_day;
-
- //nickname and length
- for ( i = 0; i < MAX_FW_NICKNAME_LENGTH; i++) {
- data[0x06 + (i * 2)] = user_settings->nickname[i] & 0xff;
- data[0x06 + (i * 2) + 1] = (user_settings->nickname[i] >> 8) & 0xff;
- }
-
- data[0x1a] = user_settings->nickname_len;
-
- //Message
- for ( i = 0; i < MAX_FW_MESSAGE_LENGTH; i++) {
- data[0x1c + (i * 2)] = user_settings->message[i] & 0xff;
- data[0x1c + (i * 2) + 1] = (user_settings->message[i] >> 8) & 0xff;
- }
-
- data[0x50] = user_settings->message_len;*/
-
- //touch screen calibration
- /*ts_cal_data_area = &data[0x58];
- for ( i = 0; i < 2; i++) {
- // ADC x y
- *ts_cal_data_area++ = user_settings->touch_cal[i].adc_x & 0xff;
- *ts_cal_data_area++ = (user_settings->touch_cal[i].adc_x >> 8) & 0xff;
- *ts_cal_data_area++ = user_settings->touch_cal[i].adc_y & 0xff;
- *ts_cal_data_area++ = (user_settings->touch_cal[i].adc_y >> 8) & 0xff;
-
- //screen x y
- *ts_cal_data_area++ = user_settings->touch_cal[i].screen_x;
- *ts_cal_data_area++ = user_settings->touch_cal[i].screen_y;
- }*/
-
- //language and flags
- /*data[0x64] = user_settings->language;
- data[0x65] = 0xfc;
-
- //update count and crc
- data[0x70] = count & 0xff;
- data[0x71] = (count >> 8) & 0xff;
-
- crc = calc_CRC16( 0xffff, data, 0x70);
- data[0x72] = crc & 0xff;
- data[0x73] = (crc >> 8) & 0xff;
-
- memset( &data[0x74], 0xff, 0x100 - 0x74);
-}*/
-
-// creates an firmware flash image, which contains all needed info to initiate a wifi connection
-/*int NDS_CreateDummyFirmware( struct NDS_fw_config_data *user_settings)
-{
- //Create the firmware header
-
- memset(&MMU.fw.data[0], 0, 0x40000);
-
- //firmware identifier
- MMU.fw.data[0x8] = 'M';
- MMU.fw.data[0x8 + 1] = 'A';
- MMU.fw.data[0x8 + 2] = 'C';
- MMU.fw.data[0x8 + 3] = 'P';
-
- // DS type
- if ( user_settings->ds_type == NDS_FW_DS_TYPE_LITE)
- MMU.fw.data[0x1d] = 0x20;
- else
- MMU.fw.data[0x1d] = 0xff;
-
- //User Settings offset 0x3fe00 / 8
- MMU.fw.data[0x20] = 0xc0;
- MMU.fw.data[0x21] = 0x7f;
-
-
- //User settings (at 0x3FE00 and 0x3FF00)
-
- fill_user_data_area( user_settings, &MMU.fw.data[ 0x3FE00], 0);
- fill_user_data_area( user_settings, &MMU.fw.data[ 0x3FF00], 1);
-
- // Wifi config length
- //MMU.fw.data[0x2C] = 0x38;
- //MMU.fw.data[0x2D] = 0x01;
-
- //MMU.fw.data[0x2E] = 0x00;
-
- //Wifi version
- //MMU.fw.data[0x2F] = 0x00;
-
- //MAC address
- //memcpy((MMU.fw.data + 0x36), FW_Mac, sizeof(FW_Mac));
-
- //Enabled channels
- MMU.fw.data[0x3C] = 0xFE;
- MMU.fw.data[0x3D] = 0x3F;
-
- MMU.fw.data[0x3E] = 0xFF;
- MMU.fw.data[0x3F] = 0xFF;
-
- //RF related
- MMU.fw.data[0x40] = 0x02;
- MMU.fw.data[0x41] = 0x18;
- MMU.fw.data[0x42] = 0x0C;
-
- MMU.fw.data[0x43] = 0x01;
-
- //Wifi I/O init values
- //memcpy((MMU.fw.data + 0x44), FW_WIFIInit, sizeof(FW_WIFIInit));
-
- //Wifi BB init values
- //memcpy((MMU.fw.data + 0x64), FW_BBInit, sizeof(FW_BBInit));
-
- //Wifi RF init values
- //memcpy((MMU.fw.data + 0xCE), FW_RFInit, sizeof(FW_RFInit));
-
- //Wifi channel-related init values
- //memcpy((MMU.fw.data + 0xF2), FW_RFChannel, sizeof(FW_RFChannel));
- //memcpy((MMU.fw.data + 0x146), FW_BBChannel, sizeof(FW_BBChannel));
- memset(&MMU.fw.data[0x154], 0x10, 0xE);*/
-
- //WFC profiles
- /*memcpy((MMU.fw.data + 0x3FA40), &FW_WFCProfile1, sizeof(FW_WFCProfile));
- memcpy((MMU.fw.data + 0x3FB40), &FW_WFCProfile2, sizeof(FW_WFCProfile));
- memcpy((MMU.fw.data + 0x3FC40), &FW_WFCProfile3, sizeof(FW_WFCProfile));
- (*(uint16_t*)(MMU.fw.data + 0x3FAFE)) = (uint16_t)calc_CRC16(0, (MMU.fw.data + 0x3FA00), 0xFE);
- (*(uint16_t*)(MMU.fw.data + 0x3FBFE)) = (uint16_t)calc_CRC16(0, (MMU.fw.data + 0x3FB00), 0xFE);
- (*(uint16_t*)(MMU.fw.data + 0x3FCFE)) = (uint16_t)calc_CRC16(0, (MMU.fw.data + 0x3FC00), 0xFE);*/
-
-
- /*MMU.fw.data[0x162] = 0x19;
- memset(&MMU.fw.data[0x163], 0xFF, 0x9D);
-
- //Wifi settings CRC16
- (*(uint16_t*)(&MMU.fw.data[0x2A])) = calc_CRC16(0, &MMU.fw.data[0x2C], 0x138);
-
- if (&CommonSettings.InternalFirmConf != user_settings)
- memcpy(&CommonSettings.InternalFirmConf, user_settings, sizeof(struct NDS_fw_config_data));
-
- return true ;
-}*/
-
-void NDS_FillDefaultFirmwareConfigData( struct NDS_fw_config_data *fw_config) {
+void NDS_FillDefaultFirmwareConfigData(NDS_fw_config_data *fw_config)
+{
const char *default_nickname = "DeSmuME";
const char *default_message = "DeSmuME makes you happy!";
- int i;
- int str_length;
-
- memset( fw_config, 0, sizeof( struct NDS_fw_config_data));
+
+ memset(fw_config, 0, sizeof(struct NDS_fw_config_data));
fw_config->ds_type = NDS_CONSOLE_TYPE_FAT;
fw_config->fav_colour = 7;
@@ -889,36 +609,18 @@
fw_config->birth_day = 23;
fw_config->birth_month = 6;
- str_length = strlen( default_nickname);
- for ( i = 0; i < str_length; i++) {
+ int str_length = strlen(default_nickname);
+ int i;
+ for (i = 0; i < str_length; ++i)
fw_config->nickname[i] = default_nickname[i];
- }
fw_config->nickname_len = str_length;
- str_length = strlen( default_message);
- for ( i = 0; i < str_length; i++) {
+ str_length = strlen(default_message);
+ for (i = 0; i < str_length; ++i)
fw_config->message[i] = default_message[i];
- }
fw_config->message_len = str_length;
/* default to English */
fw_config->language = 1;
-
- /* default touchscreen calibration */
- //fw_config->touch_cal[0].adc_x = 0x200;
- //fw_config->touch_cal[0].adc_y = 0x200;
- //fw_config->touch_cal[0].screen_x = 0x20 + 1; // calibration screen coords are 1-based,
- //fw_config->touch_cal[0].screen_y = 0x20 + 1; // either that or NDS_getADCTouchPosX/Y are wrong.
-
- //fw_config->touch_cal[1].adc_x = 0xe00;
- //fw_config->touch_cal[1].adc_y = 0x800;
- //fw_config->touch_cal[1].screen_x = 0xe0 + 1;
- //fw_config->touch_cal[1].screen_y = 0x80 + 1;
-}
-
-/*void NDS_PatchFirmwareMAC()
-{
- //memcpy((MMU.fw.data + 0x36), FW_Mac, sizeof(FW_Mac));
- //(*(uint16_t*)(MMU.fw.data + 0x2A)) = calc_CRC16(0, (MMU.fw.data + 0x2C), 0x138);
-}*/
-
+}
+
--- a/src/in_2sf/desmume/firmware.h
+++ b/src/in_2sf/desmume/firmware.h
@@ -18,18 +18,19 @@
#ifndef _FIRMWARE_H_
#define _FIRMWARE_H_
-#include "common.h"
+#include <memory>
+#include "types.h"
// the count of bytes copied from the firmware into memory
-static const int NDS_FW_USER_SETTINGS_MEM_BYTE_COUNT = 0x70;
+const int NDS_FW_USER_SETTINGS_MEM_BYTE_COUNT = 0x70;
#define FW_CONFIG_FILE_EXT "dfc"
class CFIRMWARE
{
private:
- uint8_t *tmp_data9;
- uint8_t *tmp_data7;
+ std::unique_ptr<uint8_t[]> tmp_data9;
+ std::unique_ptr<uint8_t[]> tmp_data7;
uint32_t size9, size7;
uint32_t keyBuf[0x412];
@@ -41,15 +42,12 @@
void applyKeycode(uint32_t modulo);
bool initKeycode(uint32_t idCode, int level, uint32_t modulo);
uint16_t getBootCodeCRC16();
- uint32_t decrypt(const uint8_t *in, uint8_t* &out);
- uint32_t decompress(const uint8_t *in, uint8_t* &out);
-
+ uint32_t decrypt(const uint8_t *in, std::unique_ptr<uint8_t[]> &out);
+ uint32_t decompress(const uint8_t *in, std::unique_ptr<uint8_t[]> &out);
public:
- CFIRMWARE(): size9(0), size7(0), ARM9bootAddr(0), ARM7bootAddr(0), patched(0) {}
+ CFIRMWARE(): size9(0), size7(0), ARM9bootAddr(0), ARM7bootAddr(0), patched(0) { }
bool load();
-
- static std::string GetExternalFilePath();
struct HEADER
{
@@ -81,9 +79,7 @@
};
int copy_firmware_user_data(uint8_t *dest_buffer, const uint8_t *fw_data);
-//int NDS_CreateDummyFirmware(struct NDS_fw_config_data *user_settings);
void NDS_FillDefaultFirmwareConfigData(struct NDS_fw_config_data *fw_config);
-//void NDS_PatchFirmwareMAC();
#endif
--- /dev/null
+++ b/src/in_2sf/desmume/instruction_attributes.h
@@ -1,1 +1,5175 @@
+/* Copyright (C) 2006 yopyop
+ Copyright (C) 2011 Loren Merritt
+ Copyright (C) 2012 DeSmuME team
+ This file is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This file is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with the this software. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef instruction_attributes_H_
+#define instruction_attributes_H_
+
+#include "types.h"
+
+#define INSTR_CYCLES_MASK 0x7
+#define INSTR_CYCLES(c) c // constant cycles. does not include the penalty for writing to r15 for instructions other than dedicated branches.
+#define INSTR_CYCLES_VARIABLE 0 // duration to be determined at runtime
+#define INSTR_CYCLES_V INSTR_CYCLES_VARIABLE
+
+#define SRCREG_NONE 0x0000
+#define SRCREG_POS0 0x0008
+#define SRCREG_POS3 0x0010
+#define SRCREG_POS8 0x0020
+#define SRCREG_POS12 0x0040
+#define SRCREG_POS16 0x0080
+#define SRCREG_STM 0x0100
+
+#define BRANCH_NEVER 0x00000000
+#define BRANCH_ALWAYS 0x00000800
+#define BRANCH_POS0 0x00001000 // branch if (REG_NUM(i,0)|((i>>4)&8))==15
+#define BRANCH_POS12 0x00002000 // branch if REG_POS(i,12)==15
+#define BRANCH_LDM 0x00004000
+#define BRANCH_SWI 0x00008000 // branch if use external SWI - if (cpu->swi_tab == NULL)
+
+#define JIT_BYPASS 0x80000000 // JIT makes no assumptions about what this instruction does
+
+const uint32_t instruction_attributes[] =
+{
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_AND_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_AND_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_AND_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_AND_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_AND_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_AND_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_AND_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_AND_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_AND_LSL_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8, //OP_MUL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_AND_LSR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRH_POS_INDE_M_REG_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_AND_ASR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_POST_INDEX
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_AND_ROR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_POST_INDEX
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_AND_S_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_AND_S_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_AND_S_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_AND_S_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_AND_S_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_AND_S_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_AND_S_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_AND_S_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_AND_S_LSL_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8, //OP_MUL_S
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_AND_S_LSR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRH_POS_INDE_M_REG_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_AND_S_ASR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRSB_POS_INDE_M_REG_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_AND_S_ROR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRSH_POS_INDE_M_REG_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_EOR_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_EOR_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_EOR_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_EOR_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_EOR_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_EOR_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_EOR_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_EOR_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_EOR_LSL_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS12, //OP_MLA
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_EOR_LSR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_EOR_ASR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_EOR_ROR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_EOR_S_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_EOR_S_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_EOR_S_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_EOR_S_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_EOR_S_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_EOR_S_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_EOR_S_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_EOR_S_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_EOR_S_LSL_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS12, //OP_MLA_S
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_EOR_S_LSR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_EOR_S_ASR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_EOR_S_ROR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SUB_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_SUB_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SUB_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_SUB_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SUB_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_SUB_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SUB_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_SUB_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SUB_LSL_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SUB_LSR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRH_POS_INDE_M_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SUB_ASR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_POST_INDEX
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SUB_ROR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_POST_INDEX
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SUB_S_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_SUB_S_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SUB_S_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_SUB_S_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SUB_S_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_SUB_S_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SUB_S_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_SUB_S_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SUB_S_LSL_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SUB_S_LSR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRH_POS_INDE_M_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SUB_S_ASR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRSB_POS_INDE_M_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SUB_S_ROR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRSH_POS_INDE_M_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSB_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_RSB_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSB_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_RSB_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSB_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_RSB_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSB_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_RSB_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSB_LSL_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSB_LSR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSB_ASR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSB_ROR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSB_S_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_RSB_S_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSB_S_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_RSB_S_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSB_S_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_RSB_S_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSB_S_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_RSB_S_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSB_S_LSL_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSB_S_LSR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSB_S_ASR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSB_S_ROR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADD_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ADD_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADD_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ADD_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADD_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ADD_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADD_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ADD_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADD_LSL_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8, //OP_UMULL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADD_LSR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRH_POS_INDE_P_REG_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADD_ASR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_POST_INDEX
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADD_ROR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_POST_INDEX
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADD_S_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ADD_S_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADD_S_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ADD_S_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADD_S_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ADD_S_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADD_S_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ADD_S_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADD_S_LSL_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8, //OP_UMULL_S
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADD_S_LSR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRH_POS_INDE_P_REG_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADD_S_ASR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRSB_POS_INDE_P_REG_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADD_S_ROR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRSH_POS_INDE_P_REG_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADC_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ADC_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADC_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ADC_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADC_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ADC_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADC_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ADC_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADC_LSL_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS12 | SRCREG_POS16, //OP_UMLAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADC_LSR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADC_ASR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADC_ROR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADC_S_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ADC_S_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADC_S_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ADC_S_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADC_S_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ADC_S_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADC_S_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ADC_S_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADC_S_LSL_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS12 | SRCREG_POS16, //OP_UMLAL_S
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADC_S_LSR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADC_S_ASR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ADC_S_ROR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SBC_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_SBC_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SBC_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_SBC_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SBC_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_SBC_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SBC_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_SBC_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SBC_LSL_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8, //OP_SMULL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SBC_LSR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRH_POS_INDE_P_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SBC_ASR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_POST_INDEX
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SBC_ROR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_POST_INDEX
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SBC_S_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_SBC_S_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SBC_S_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_SBC_S_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SBC_S_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_SBC_S_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SBC_S_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_SBC_S_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SBC_S_LSL_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8, //OP_SMULL_S
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SBC_S_LSR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRH_POS_INDE_P_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SBC_S_ASR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRSB_POS_INDE_P_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_SBC_S_ROR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRSH_POS_INDE_P_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSC_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_RSC_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSC_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_RSC_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSC_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_RSC_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSC_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_RSC_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSC_LSL_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS12 | SRCREG_POS16, //OP_SMLAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSC_LSR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSC_ASR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSC_ROR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSC_S_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_RSC_S_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSC_S_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_RSC_S_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSC_S_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_RSC_S_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSC_S_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_RSC_S_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSC_S_LSL_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS12 | SRCREG_POS16, //OP_SMLAL_S
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSC_S_LSR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSC_S_ASR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_RSC_S_ROR_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MRS_CPSR
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_QADD
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS12, //OP_SMLA_B_B
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_SWP
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS12, //OP_SMLA_T_B
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRH_M_REG_OFF
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS12, //OP_SMLA_B_T
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_OFFSET_PRE_INDEX
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS12, //OP_SMLA_T_T
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_OFFSET_PRE_INDEX
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_TST_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_TST_LSL_REG
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_TST_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_TST_LSR_REG
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_TST_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_TST_ASR_REG
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_TST_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_TST_ROR_REG
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_TST_LSL_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_TST_LSR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRH_M_REG_OFF
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_TST_ASR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRSB_M_REG_OFF
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_TST_ROR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRSH_M_REG_OFF
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0, //OP_MSR_CPSR
+INSTR_CYCLES(3) | BRANCH_ALWAYS | SRCREG_POS0, //OP_BX
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(3) | BRANCH_ALWAYS | SRCREG_POS0, //OP_BLX_REG
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_QSUB
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_BKPT
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS12, //OP_SMLAW_B
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8, //OP_SMULW_B
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRH_PRE_INDE_M_REG_OFF
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS12, //OP_SMLAW_T
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_OFFSET_PRE_INDEX
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8, //OP_SMULW_T
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_OFFSET_PRE_INDEX
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_TEQ_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_TEQ_LSL_REG
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_TEQ_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_TEQ_LSR_REG
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_TEQ_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_TEQ_ASR_REG
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_TEQ_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_TEQ_ROR_REG
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_TEQ_LSL_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_TEQ_LSR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRH_PRE_INDE_M_REG_OFF
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_TEQ_ASR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRSB_PRE_INDE_M_REG_OFF
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_TEQ_ROR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRSH_PRE_INDE_M_REG_OFF
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MRS_SPSR
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_QDADD
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS12 | SRCREG_POS16, //OP_SMLAL_B_B
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_SWPB
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS12 | SRCREG_POS16, //OP_SMLAL_T_B
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRH_M_IMM_OFF
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS12 | SRCREG_POS16, //OP_SMLAL_B_T
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_OFFSET_PRE_INDEX
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS12 | SRCREG_POS16, //OP_SMLAL_T_T
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_OFFSET_PRE_INDEX
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_CMP_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_CMP_LSL_REG
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_CMP_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_CMP_LSR_REG
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_CMP_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_CMP_ASR_REG
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_CMP_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_CMP_ROR_REG
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_CMP_LSL_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_CMP_LSR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRH_M_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_CMP_ASR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRSB_M_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_CMP_ROR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRSH_M_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0, //OP_MSR_SPSR
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0, //OP_CLZ
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_QDSUB
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8, //OP_SMUL_B_B
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8, //OP_SMUL_T_B
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRH_PRE_INDE_M_IMM_OFF
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8, //OP_SMUL_B_T
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_OFFSET_PRE_INDEX
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8, //OP_SMUL_T_T
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_OFFSET_PRE_INDEX
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_CMN_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_CMN_LSL_REG
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_CMN_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_CMN_LSR_REG
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_CMN_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_CMN_ASR_REG
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_CMN_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_CMN_ROR_REG
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_CMN_LSL_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_CMN_LSR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRH_PRE_INDE_M_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_CMN_ASR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRSB_PRE_INDE_M_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_CMN_ROR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRSH_PRE_INDE_M_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ORR_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ORR_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ORR_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ORR_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ORR_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ORR_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ORR_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ORR_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ORR_LSL_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ORR_LSR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRH_P_REG_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ORR_ASR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_OFFSET_PRE_INDEX
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ORR_ROR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_OFFSET_PRE_INDEX
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ORR_S_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ORR_S_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ORR_S_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ORR_S_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ORR_S_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ORR_S_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ORR_S_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_ORR_S_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ORR_S_LSL_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ORR_S_LSR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRH_P_REG_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ORR_S_ASR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRSB_P_REG_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_ORR_S_ROR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRSH_P_REG_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MOV_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8, //OP_MOV_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MOV_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8, //OP_MOV_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MOV_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8, //OP_MOV_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MOV_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8, //OP_MOV_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MOV_LSL_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MOV_LSR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRH_PRE_INDE_P_REG_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MOV_ASR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_OFFSET_PRE_INDEX
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MOV_ROR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_OFFSET_PRE_INDEX
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MOV_S_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8, //OP_MOV_S_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MOV_S_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8, //OP_MOV_S_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MOV_S_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8, //OP_MOV_S_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MOV_S_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8, //OP_MOV_S_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MOV_S_LSL_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MOV_S_LSR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRH_PRE_INDE_P_REG_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MOV_S_ASR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRSB_PRE_INDE_P_REG_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MOV_S_ROR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRSH_PRE_INDE_P_REG_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_BIC_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_BIC_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_BIC_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_BIC_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_BIC_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_BIC_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_BIC_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_BIC_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_BIC_LSL_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_BIC_LSR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRH_P_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_BIC_ASR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_OFFSET_PRE_INDEX
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_BIC_ROR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_OFFSET_PRE_INDEX
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_BIC_S_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_BIC_S_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_BIC_S_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_BIC_S_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_BIC_S_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_BIC_S_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_BIC_S_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8 | SRCREG_POS16, //OP_BIC_S_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_BIC_S_LSL_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_BIC_S_LSR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRH_P_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_BIC_S_ASR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRSB_P_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_BIC_S_ROR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRSH_P_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MVN_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8, //OP_MVN_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MVN_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8, //OP_MVN_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MVN_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8, //OP_MVN_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MVN_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8, //OP_MVN_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MVN_LSL_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MVN_LSR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRH_PRE_INDE_P_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MVN_ASR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_OFFSET_PRE_INDEX
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MVN_ROR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRD_STRD_OFFSET_PRE_INDEX
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MVN_S_LSL_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8, //OP_MVN_S_LSL_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MVN_S_LSR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8, //OP_MVN_S_LSR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MVN_S_ASR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8, //OP_MVN_S_ASR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MVN_S_ROR_IMM
+INSTR_CYCLES(2) | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS8, //OP_MVN_S_ROR_REG
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MVN_S_LSL_IMM
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MVN_S_LSR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRH_PRE_INDE_P_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MVN_S_ASR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRSB_PRE_INDE_P_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS0, //OP_MVN_S_ROR_IMM
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRSH_PRE_INDE_P_IMM_OFF
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_AND_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_EOR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SUB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSB_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADD_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ADC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_SBC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_RSC_S_IMM_VAL
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TST_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TST_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TST_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TST_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TST_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TST_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TST_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TST_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TST_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TST_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TST_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TST_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TST_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TST_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TST_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TST_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_CPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_CPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_CPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_CPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_CPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_CPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_CPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_CPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_CPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_CPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_CPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_CPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_CPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_CPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_CPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_CPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TEQ_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TEQ_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TEQ_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TEQ_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TEQ_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TEQ_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TEQ_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TEQ_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TEQ_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TEQ_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TEQ_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TEQ_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TEQ_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TEQ_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TEQ_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_TEQ_IMM_VAL
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMP_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMP_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMP_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMP_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMP_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMP_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMP_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMP_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMP_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMP_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMP_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMP_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMP_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMP_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMP_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMP_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_SPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_SPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_SPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_SPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_SPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_SPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_SPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_SPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_SPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_SPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_SPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_SPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_SPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_SPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_SPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MSR_SPSR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS16, //OP_CMN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_ORR_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MOV_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_POS16, //OP_BIC_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_S_IMM_VAL
+INSTR_CYCLES(1) | BRANCH_POS12 | SRCREG_NONE, //OP_MVN_S_IMM_VAL
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_POSTIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_M_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS16, //OP_LDR_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS16, //OP_LDRB_P_IMM_OFF_PREIND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_LSL_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_LSR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_ASR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_ROR_IMM_OFF_POSTIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_LSL_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_LSR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_ASR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_ROR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_LSL_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_LSR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_ASR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_ROR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_LSL_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_LSR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_ASR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_ROR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_LSL_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_LSR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_ASR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_ROR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_LSL_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_LSR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_ASR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_ROR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_LSL_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_LSR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_ASR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_M_ROR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_LSL_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_LSR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_ASR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_ROR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_LSL_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_LSR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_ASR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_M_ROR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_LSL_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_LSR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_ASR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_ROR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_LSL_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_LSR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_ASR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_ROR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_LSL_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_LSR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_ASR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_ROR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_LSL_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_LSR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_ASR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_ROR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_LSL_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_LSR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_ASR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_ROR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_LSL_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_LSR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_ASR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_M_ROR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_LSL_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_LSR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_ASR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_ROR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_LSL_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_LSR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_ASR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_M_ROR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_LSL_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_LSR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_ASR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_ROR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_LSL_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_LSR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_ASR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_ROR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_LSL_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_LSR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_ASR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_ROR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_LSL_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_LSR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_ASR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_ROR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_LSL_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_LSR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_ASR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_ROR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_LSL_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_LSR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_ASR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STR_P_ROR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_LSL_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_LSR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_ASR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_ROR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_LSL_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_LSR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_ASR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_POS12 | SRCREG_POS0 | SRCREG_POS16, //OP_LDR_P_ROR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_LSL_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_LSR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_ASR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_ROR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_LSL_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_LSR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_ASR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_ROR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_LSL_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_LSR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_ASR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_ROR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_LSL_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_LSR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_ASR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_ROR_IMM_OFF
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_LSL_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_LSR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_ASR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_ROR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_LSL_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_LSR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_ASR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS12 | SRCREG_POS16, //OP_STRB_P_ROR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_LSL_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_LSR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_ASR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_ROR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_LSL_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_LSR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_ASR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS16, //OP_LDRB_P_ROR_IMM_OFF_PREIND
+JIT_BYPASS, //OP_UND
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIA2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMDB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMDB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2_W
+INSTR_CYCLES_V | BRANCH_NEVER | SRCREG_STM | SRCREG_POS16, //OP_STMIB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2_W
+INSTR_CYCLES_V | BRANCH_LDM | SRCREG_POS16, //OP_LDMIB2_W
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_B
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BL
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_STC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_LDC_M_POSTIND
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_STC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_LDC_OPTION
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_STC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_LDC_P_POSTIND
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_LDC_M_IMM_OFF
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_STC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_LDC_M_PREIND
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_LDC_P_IMM_OFF
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_STC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_LDC_P_PREIND
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_MCR
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+JIT_BYPASS, //OP_CDP
+INSTR_CYCLES(3) | BRANCH_NEVER, //OP_MRC
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI
+};
+
+const uint32_t thumb_attributes[] =
+{
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL_0
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR_0
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_LSR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR_0
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ASR
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_REG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_REG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_REG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_REG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_REG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_REG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_REG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_REG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_REG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_REG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_REG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_REG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_REG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_REG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_REG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_REG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM3
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM3
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM3
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM3
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM3
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM3
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM3
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM3
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM3
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM3
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM3
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM3
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM3
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM3
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM3
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM3
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MOV_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SUB_IMM8
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_AND
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_EOR
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_LSL_REG
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_LSR_REG
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_ASR_REG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADC_REG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_SBC_REG
+INSTR_CYCLES(2) | BRANCH_NEVER, //OP_ROR_REG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_TST
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_NEG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_CMN
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ORR
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_MUL_REG
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_BIC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_MVN
+INSTR_CYCLES(1) | BRANCH_POS0 | SRCREG_POS0 | SRCREG_POS3, //OP_ADD_SPE
+INSTR_CYCLES(1) | BRANCH_POS0 | SRCREG_POS0 | SRCREG_POS3, //OP_ADD_SPE
+INSTR_CYCLES(1) | BRANCH_POS0 | SRCREG_POS0 | SRCREG_POS3, //OP_ADD_SPE
+INSTR_CYCLES(1) | BRANCH_POS0 | SRCREG_POS0 | SRCREG_POS3, //OP_ADD_SPE
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS3, //OP_CMP_SPE
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS3, //OP_CMP_SPE
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS3, //OP_CMP_SPE
+INSTR_CYCLES(1) | BRANCH_NEVER | SRCREG_POS0 | SRCREG_POS3, //OP_CMP_SPE
+INSTR_CYCLES(1) | BRANCH_POS0 | SRCREG_POS3, //OP_MOV_SPE
+INSTR_CYCLES(1) | BRANCH_POS0 | SRCREG_POS3, //OP_MOV_SPE
+INSTR_CYCLES(1) | BRANCH_POS0 | SRCREG_POS3, //OP_MOV_SPE
+INSTR_CYCLES(1) | BRANCH_POS0 | SRCREG_POS3, //OP_MOV_SPE
+INSTR_CYCLES(3) | BRANCH_ALWAYS | SRCREG_POS3, //OP_BX_THUMB
+INSTR_CYCLES(3) | BRANCH_ALWAYS | SRCREG_POS3, //OP_BX_THUMB
+INSTR_CYCLES(4) | BRANCH_ALWAYS | SRCREG_POS3, //OP_BLX_THUMB
+INSTR_CYCLES(4) | BRANCH_ALWAYS | SRCREG_POS3, //OP_BLX_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_PCREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRSB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRSB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRSB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRSB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRSB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRSB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRSB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRSB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRSH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRSH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRSH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRSH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRSH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRSH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRSH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRSH_REG_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRB_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDRH_IMM_OFF
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDR_SPREL
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2PC
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADD_2SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADJUST_P_SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADJUST_P_SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADJUST_M_SP
+INSTR_CYCLES(1) | BRANCH_NEVER, //OP_ADJUST_M_SP
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_PUSH
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_PUSH
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_PUSH
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_PUSH
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_PUSH_LR
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_PUSH_LR
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_PUSH_LR
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_PUSH_LR
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_POP
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_POP
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_POP
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_POP
+INSTR_CYCLES_V | BRANCH_ALWAYS, //OP_POP_PC
+INSTR_CYCLES_V | BRANCH_ALWAYS, //OP_POP_PC
+INSTR_CYCLES_V | BRANCH_ALWAYS, //OP_POP_PC
+INSTR_CYCLES_V | BRANCH_ALWAYS, //OP_POP_PC
+JIT_BYPASS, //OP_BKPT_THUMB
+JIT_BYPASS, //OP_BKPT_THUMB
+JIT_BYPASS, //OP_BKPT_THUMB
+JIT_BYPASS, //OP_BKPT_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+JIT_BYPASS, //OP_UND_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_STMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES_V | BRANCH_NEVER, //OP_LDMIA_THUMB
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_COND
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI_THUMB
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI_THUMB
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI_THUMB
+INSTR_CYCLES_V | BRANCH_SWI, //OP_SWI_THUMB
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(1) | BRANCH_ALWAYS, //OP_B_UNCOND
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(3) | BRANCH_ALWAYS, //OP_BLX
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(1) | BRANCH_NEVER , //OP_BL_10
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+INSTR_CYCLES(4) | BRANCH_ALWAYS, //OP_BL_11
+};
+
+#endif
+
--- a/src/in_2sf/desmume/instruction_tabdef.inc
+++ b/src/in_2sf/desmume/instruction_tabdef.inc
@@ -15,4105 +15,4356 @@
along with the this software. If not, see <http://www.gnu.org/licenses/>.
*/
-/* 0XX000X0 */
-
-/* 0000 0000 0000 */ TABDECL( OP_AND_LSL_IMM),
-/* 0000 0000 0001 */ TABDECL( OP_AND_LSL_REG),
-/* 0000 0000 0010 */ TABDECL( OP_AND_LSR_IMM),
-/* 0000 0000 0011 */ TABDECL( OP_AND_LSR_REG),
-/* 0000 0000 0100 */ TABDECL( OP_AND_ASR_IMM),
-/* 0000 0000 0101 */ TABDECL( OP_AND_ASR_REG),
-/* 0000 0000 0110 */ TABDECL( OP_AND_ROR_IMM),
-/* 0000 0000 0111 */ TABDECL( OP_AND_ROR_REG),
-/* 0000 0000 1000 */ TABDECL( OP_AND_LSL_IMM),
-/* 0000 0000 1001 */ TABDECL( OP_MUL),
-/* 0000 0000 1010 */ TABDECL( OP_AND_LSR_IMM),
-/* 0000 0000 1011 */ TABDECL( OP_STRH_POS_INDE_M_REG_OFF),
-/* 0000 0000 1100 */ TABDECL( OP_AND_ASR_IMM),
-/* 0000 0000 1101 */ TABDECL( OP_LDRD_STRD_POST_INDEX),
-/* 0000 0000 1110 */ TABDECL( OP_AND_ROR_IMM),
-/* 0000 0000 1111 */ TABDECL( OP_LDRD_STRD_POST_INDEX),
-/* 0000 0001 0000 */ TABDECL( OP_AND_S_LSL_IMM),
-/* 0000 0001 0001 */ TABDECL( OP_AND_S_LSL_REG),
-/* 0000 0001 0010 */ TABDECL( OP_AND_S_LSR_IMM),
-/* 0000 0001 0011 */ TABDECL( OP_AND_S_LSR_REG),
-/* 0000 0001 0100 */ TABDECL( OP_AND_S_ASR_IMM),
-/* 0000 0001 0101 */ TABDECL( OP_AND_S_ASR_REG),
-/* 0000 0001 0110 */ TABDECL( OP_AND_S_ROR_IMM),
-/* 0000 0001 0111 */ TABDECL( OP_AND_S_ROR_REG),
-/* 0000 0001 1000 */ TABDECL( OP_AND_S_LSL_IMM),
-/* 0000 0001 1001 */ TABDECL( OP_MUL_S),
-/* 0000 0001 1010 */ TABDECL( OP_AND_S_LSR_IMM),
-/* 0000 0001 1011 */ TABDECL( OP_LDRH_POS_INDE_M_REG_OFF),
-/* 0000 0001 1100 */ TABDECL( OP_AND_S_ASR_IMM),
-/* 0000 0001 1101 */ TABDECL( OP_LDRSB_POS_INDE_M_REG_OFF),
-/* 0000 0001 1110 */ TABDECL( OP_AND_S_ROR_IMM),
-/* 0000 0001 1111 */ TABDECL( OP_LDRSH_POS_INDE_M_REG_OFF),
-/* 0000 0010 0000 */ TABDECL( OP_EOR_LSL_IMM),
-/* 0000 0010 0001 */ TABDECL( OP_EOR_LSL_REG),
-/* 0000 0010 0010 */ TABDECL( OP_EOR_LSR_IMM),
-/* 0000 0010 0011 */ TABDECL( OP_EOR_LSR_REG),
-/* 0000 0010 0100 */ TABDECL( OP_EOR_ASR_IMM),
-/* 0000 0010 0101 */ TABDECL( OP_EOR_ASR_REG),
-/* 0000 0010 0110 */ TABDECL( OP_EOR_ROR_IMM),
-/* 0000 0010 0111 */ TABDECL( OP_EOR_ROR_REG),
-/* 0000 0010 1000 */ TABDECL( OP_EOR_LSL_IMM),
-/* 0000 0010 1001 */ TABDECL( OP_MLA),
-/* 0000 0010 1010 */ TABDECL( OP_EOR_LSR_IMM), // OOO OOO1 O 1010
-/* 0000 0010 1011 */ TABDECL( OP_UND),
-/* 0000 0010 1100 */ TABDECL( OP_EOR_ASR_IMM),
-/* 0000 0010 1101 */ TABDECL( OP_UND),
-/* 0000 0010 1110 */ TABDECL( OP_EOR_ROR_IMM),
-/* 0000 0010 1111 */ TABDECL( OP_UND),
-/* 0000 0011 0000 */ TABDECL( OP_EOR_S_LSL_IMM),
-/* 0000 0011 0001 */ TABDECL( OP_EOR_S_LSL_REG),
-/* 0000 0011 0010 */ TABDECL( OP_EOR_S_LSR_IMM),
-/* 0000 0011 0011 */ TABDECL( OP_EOR_S_LSR_REG),
-/* 0000 0011 0100 */ TABDECL( OP_EOR_S_ASR_IMM),
-/* 0000 0011 0101 */ TABDECL( OP_EOR_S_ASR_REG),
-/* 0000 0011 0110 */ TABDECL( OP_EOR_S_ROR_IMM),
-/* 0000 0011 0111 */ TABDECL( OP_EOR_S_ROR_REG),
-/* 0000 0011 1000 */ TABDECL( OP_EOR_S_LSL_IMM),
-/* 0000 0011 1001 */ TABDECL( OP_MLA_S),
-/* 0000 0011 1010 */ TABDECL( OP_EOR_S_LSR_IMM),
-/* 0000 0011 1011 */ TABDECL( OP_UND),
-/* 0000 0011 1100 */ TABDECL( OP_EOR_S_ASR_IMM),
-/* 0000 0011 1101 */ TABDECL( OP_UND),
-/* 0000 0011 1110 */ TABDECL( OP_EOR_S_ROR_IMM),
-/* 0000 0011 1111 */ TABDECL( OP_UND),
-/* 0000 0100 0000 */ TABDECL( OP_SUB_LSL_IMM),
-/* 0000 0100 0001 */ TABDECL( OP_SUB_LSL_REG),
-/* 0000 0100 0010 */ TABDECL( OP_SUB_LSR_IMM),
-/* 0000 0100 0011 */ TABDECL( OP_SUB_LSR_REG),
-/* 0000 0100 0100 */ TABDECL( OP_SUB_ASR_IMM),
-/* 0000 0100 0101 */ TABDECL( OP_SUB_ASR_REG),
-/* 0000 0100 0110 */ TABDECL( OP_SUB_ROR_IMM),
-/* 0000 0100 0111 */ TABDECL( OP_SUB_ROR_REG),
-/* 0000 0100 1000 */ TABDECL( OP_SUB_LSL_IMM),
-/* 0000 0100 1001 */ TABDECL( OP_UND),
-/* 0000 0100 1010 */ TABDECL( OP_SUB_LSR_IMM), // OOO OO1O O 1010
-/* 0000 0100 1011 */ TABDECL( OP_STRH_POS_INDE_M_IMM_OFF),
-/* 0000 0100 1100 */ TABDECL( OP_SUB_ASR_IMM),
-/* 0000 0100 1101 */ TABDECL( OP_LDRD_STRD_POST_INDEX),
-/* 0000 0100 1110 */ TABDECL( OP_SUB_ROR_IMM),
-/* 0000 0100 1111 */ TABDECL( OP_LDRD_STRD_POST_INDEX),
-/* 0000 0101 0000 */ TABDECL( OP_SUB_S_LSL_IMM),
-/* 0000 0101 0001 */ TABDECL( OP_SUB_S_LSL_REG),
-/* 0000 0101 0010 */ TABDECL( OP_SUB_S_LSR_IMM),
-/* 0000 0101 0011 */ TABDECL( OP_SUB_S_LSR_REG),
-/* 0000 0101 0100 */ TABDECL( OP_SUB_S_ASR_IMM),
-/* 0000 0101 0101 */ TABDECL( OP_SUB_S_ASR_REG),
-/* 0000 0101 0110 */ TABDECL( OP_SUB_S_ROR_IMM),
-/* 0000 0101 0111 */ TABDECL( OP_SUB_S_ROR_REG),
-/* 0000 0101 1000 */ TABDECL( OP_SUB_S_LSL_IMM),
-/* 0000 0101 1001 */ TABDECL( OP_UND),
-/* 0000 0101 1010 */ TABDECL( OP_SUB_S_LSR_IMM),
-/* 0000 0101 1011 */ TABDECL( OP_LDRH_POS_INDE_M_IMM_OFF),
-/* 0000 0101 1100 */ TABDECL( OP_SUB_S_ASR_IMM),
-/* 0000 0101 1101 */ TABDECL( OP_LDRSB_POS_INDE_M_IMM_OFF),
-/* 0000 0101 1110 */ TABDECL( OP_SUB_S_ROR_IMM),
-/* 0000 0101 1111 */ TABDECL( OP_LDRSH_POS_INDE_M_IMM_OFF),
-/* 0000 0110 0000 */ TABDECL( OP_RSB_LSL_IMM),
-/* 0000 0110 0001 */ TABDECL( OP_RSB_LSL_REG),
-/* 0000 0110 0010 */ TABDECL( OP_RSB_LSR_IMM),
-/* 0000 0110 0011 */ TABDECL( OP_RSB_LSR_REG),
-/* 0000 0110 0100 */ TABDECL( OP_RSB_ASR_IMM),
-/* 0000 0110 0101 */ TABDECL( OP_RSB_ASR_REG),
-/* 0000 0110 0110 */ TABDECL( OP_RSB_ROR_IMM),
-/* 0000 0110 0111 */ TABDECL( OP_RSB_ROR_REG),
-/* 0000 0110 1000 */ TABDECL( OP_RSB_LSL_IMM),
-/* 0000 0110 1001 */ TABDECL( OP_UND),
-/* 0000 0110 1010 */ TABDECL( OP_RSB_LSR_IMM), // OOO OO11 O 1010
-/* 0000 0110 1011 */ TABDECL( OP_UND),
-/* 0000 0110 1100 */ TABDECL( OP_RSB_ASR_IMM),
-/* 0000 0110 1101 */ TABDECL( OP_UND),
-/* 0000 0110 1110 */ TABDECL( OP_RSB_ROR_IMM),
-/* 0000 0110 1111 */ TABDECL( OP_UND),
-/* 0000 0111 0000 */ TABDECL( OP_RSB_S_LSL_IMM),
-/* 0000 0111 0001 */ TABDECL( OP_RSB_S_LSL_REG),
-/* 0000 0111 0010 */ TABDECL( OP_RSB_S_LSR_IMM),
-/* 0000 0111 0011 */ TABDECL( OP_RSB_S_LSR_REG),
-/* 0000 0111 0100 */ TABDECL( OP_RSB_S_ASR_IMM),
-/* 0000 0111 0101 */ TABDECL( OP_RSB_S_ASR_REG),
-/* 0000 0111 0110 */ TABDECL( OP_RSB_S_ROR_IMM),
-/* 0000 0111 0111 */ TABDECL( OP_RSB_S_ROR_REG),
-/* 0000 0111 1000 */ TABDECL( OP_RSB_S_LSL_IMM),
-/* 0000 0111 1001 */ TABDECL( OP_UND),
-/* 0000 0111 1010 */ TABDECL( OP_RSB_S_LSR_IMM),
-/* 0000 0111 1011 */ TABDECL( OP_UND),
-/* 0000 0111 1100 */ TABDECL( OP_RSB_S_ASR_IMM),
-/* 0000 0111 1101 */ TABDECL( OP_UND),
-/* 0000 0111 1110 */ TABDECL( OP_RSB_S_ROR_IMM),
-/* 0000 0111 1111 */ TABDECL( OP_UND),
-/* 0000 1000 0000 */ TABDECL( OP_ADD_LSL_IMM),
-/* 0000 1000 0001 */ TABDECL( OP_ADD_LSL_REG),
-/* 0000 1000 0010 */ TABDECL( OP_ADD_LSR_IMM),
-/* 0000 1000 0011 */ TABDECL( OP_ADD_LSR_REG),
-/* 0000 1000 0100 */ TABDECL( OP_ADD_ASR_IMM),
-/* 0000 1000 0101 */ TABDECL( OP_ADD_ASR_REG),
-/* 0000 1000 0110 */ TABDECL( OP_ADD_ROR_IMM),
-/* 0000 1000 0111 */ TABDECL( OP_ADD_ROR_REG),
-/* 0000 1000 1000 */ TABDECL( OP_ADD_LSL_IMM),
-/* 0000 1000 1001 */ TABDECL( OP_UMULL),
-/* 0000 1000 1010 */ TABDECL( OP_ADD_LSR_IMM), // OOO O10O O 1010
-/* 0000 1000 1011 */ TABDECL( OP_STRH_POS_INDE_P_REG_OFF),
-/* 0000 1000 1100 */ TABDECL( OP_ADD_ASR_IMM),
-/* 0000 1000 1101 */ TABDECL( OP_LDRD_STRD_POST_INDEX),
-/* 0000 1000 1110 */ TABDECL( OP_ADD_ROR_IMM),
-/* 0000 1000 1111 */ TABDECL( OP_LDRD_STRD_POST_INDEX),
-/* 0000 1001 0000 */ TABDECL( OP_ADD_S_LSL_IMM),
-/* 0000 1001 0001 */ TABDECL( OP_ADD_S_LSL_REG),
-/* 0000 1001 0010 */ TABDECL( OP_ADD_S_LSR_IMM),
-/* 0000 1001 0011 */ TABDECL( OP_ADD_S_LSR_REG),
-/* 0000 1001 0100 */ TABDECL( OP_ADD_S_ASR_IMM),
-/* 0000 1001 0101 */ TABDECL( OP_ADD_S_ASR_REG),
-/* 0000 1001 0110 */ TABDECL( OP_ADD_S_ROR_IMM),
-/* 0000 1001 0111 */ TABDECL( OP_ADD_S_ROR_REG),
-/* 0000 1001 1000 */ TABDECL( OP_ADD_S_LSL_IMM),
-/* 0000 1001 1001 */ TABDECL( OP_UMULL_S),
-/* 0000 1001 1010 */ TABDECL( OP_ADD_S_LSR_IMM),
-/* 0000 1001 1011 */ TABDECL( OP_LDRH_POS_INDE_P_REG_OFF),
-/* 0000 1001 1100 */ TABDECL( OP_ADD_S_ASR_IMM),
-/* 0000 1001 1101 */ TABDECL( OP_LDRSB_POS_INDE_P_REG_OFF),
-/* 0000 1001 1110 */ TABDECL( OP_ADD_S_ROR_IMM),
-/* 0000 1001 1111 */ TABDECL( OP_LDRSH_POS_INDE_P_REG_OFF),
-/* 0000 1010 0000 */ TABDECL( OP_ADC_LSL_IMM),
-/* 0000 1010 0001 */ TABDECL( OP_ADC_LSL_REG),
-/* 0000 1010 0010 */ TABDECL( OP_ADC_LSR_IMM),
-/* 0000 1010 0011 */ TABDECL( OP_ADC_LSR_REG),
-/* 0000 1010 0100 */ TABDECL( OP_ADC_ASR_IMM),
-/* 0000 1010 0101 */ TABDECL( OP_ADC_ASR_REG),
-/* 0000 1010 0110 */ TABDECL( OP_ADC_ROR_IMM),
-/* 0000 1010 0111 */ TABDECL( OP_ADC_ROR_REG),
-/* 0000 1010 1000 */ TABDECL( OP_ADC_LSL_IMM),
-/* 0000 1010 1001 */ TABDECL( OP_UMLAL),
-/* 0000 1010 1010 */ TABDECL( OP_ADC_LSR_IMM), // OOO O101 O 1010
-/* 0000 1010 1011 */ TABDECL( OP_UND),
-/* 0000 1010 1100 */ TABDECL( OP_ADC_ASR_IMM),
-/* 0000 1010 1101 */ TABDECL( OP_UND),
-/* 0000 1010 1110 */ TABDECL( OP_ADC_ROR_IMM),
-/* 0000 1010 1111 */ TABDECL( OP_UND),
-/* 0000 1011 0000 */ TABDECL( OP_ADC_S_LSL_IMM),
-/* 0000 1011 0001 */ TABDECL( OP_ADC_S_LSL_REG),
-/* 0000 1011 0010 */ TABDECL( OP_ADC_S_LSR_IMM),
-/* 0000 1011 0011 */ TABDECL( OP_ADC_S_LSR_REG),
-/* 0000 1011 0100 */ TABDECL( OP_ADC_S_ASR_IMM),
-/* 0000 1011 0101 */ TABDECL( OP_ADC_S_ASR_REG),
-/* 0000 1011 0110 */ TABDECL( OP_ADC_S_ROR_IMM),
-/* 0000 1011 0111 */ TABDECL( OP_ADC_S_ROR_REG),
-/* 0000 1011 1000 */ TABDECL( OP_ADC_S_LSL_IMM),
-/* 0000 1011 1001 */ TABDECL( OP_UMLAL_S),
-/* 0000 1011 1010 */ TABDECL( OP_ADC_S_LSR_IMM),
-/* 0000 1011 1011 */ TABDECL( OP_UND),
-/* 0000 1011 1100 */ TABDECL( OP_ADC_S_ASR_IMM),
-/* 0000 1011 1101 */ TABDECL( OP_UND),
-/* 0000 1011 1110 */ TABDECL( OP_ADC_S_ROR_IMM),
-/* 0000 1011 1111 */ TABDECL( OP_UND),
-/* 0000 1100 0000 */ TABDECL( OP_SBC_LSL_IMM),
-/* 0000 1100 0001 */ TABDECL( OP_SBC_LSL_REG),
-/* 0000 1100 0010 */ TABDECL( OP_SBC_LSR_IMM),
-/* 0000 1100 0011 */ TABDECL( OP_SBC_LSR_REG),
-/* 0000 1100 0100 */ TABDECL( OP_SBC_ASR_IMM),
-/* 0000 1100 0101 */ TABDECL( OP_SBC_ASR_REG),
-/* 0000 1100 0110 */ TABDECL( OP_SBC_ROR_IMM),
-/* 0000 1100 0111 */ TABDECL( OP_SBC_ROR_REG),
-/* 0000 1100 1000 */ TABDECL( OP_SBC_LSL_IMM),
-/* 0000 1100 1001 */ TABDECL( OP_SMULL),
-/* 0000 1100 1010 */ TABDECL( OP_SBC_LSR_IMM), // OOO O11O O 1010
-/* 0000 1100 1011 */ TABDECL( OP_STRH_POS_INDE_P_IMM_OFF),
-/* 0000 1100 1100 */ TABDECL( OP_SBC_ASR_IMM),
-/* 0000 1100 1101 */ TABDECL( OP_LDRD_STRD_POST_INDEX),
-/* 0000 1100 1110 */ TABDECL( OP_SBC_ROR_IMM),
-/* 0000 1100 1111 */ TABDECL( OP_LDRD_STRD_POST_INDEX),
-/* 0000 1101 0000 */ TABDECL( OP_SBC_S_LSL_IMM),
-/* 0000 1101 0001 */ TABDECL( OP_SBC_S_LSL_REG),
-/* 0000 1101 0010 */ TABDECL( OP_SBC_S_LSR_IMM),
-/* 0000 1101 0011 */ TABDECL( OP_SBC_S_LSR_REG),
-/* 0000 1101 0100 */ TABDECL( OP_SBC_S_ASR_IMM),
-/* 0000 1101 0101 */ TABDECL( OP_SBC_S_ASR_REG),
-/* 0000 1101 0110 */ TABDECL( OP_SBC_S_ROR_IMM),
-/* 0000 1101 0111 */ TABDECL( OP_SBC_S_ROR_REG),
-/* 0000 1101 1000 */ TABDECL( OP_SBC_S_LSL_IMM),
-/* 0000 1101 1001 */ TABDECL( OP_SMULL_S),
-/* 0000 1101 1010 */ TABDECL( OP_SBC_S_LSR_IMM),
-/* 0000 1101 1011 */ TABDECL( OP_LDRH_POS_INDE_P_IMM_OFF),
-/* 0000 1101 1100 */ TABDECL( OP_SBC_S_ASR_IMM),
-/* 0000 1101 1101 */ TABDECL( OP_LDRSB_POS_INDE_P_IMM_OFF),
-/* 0000 1101 1110 */ TABDECL( OP_SBC_S_ROR_IMM),
-/* 0000 1101 1111 */ TABDECL( OP_LDRSH_POS_INDE_P_IMM_OFF),
-/* 0000 1110 0000 */ TABDECL( OP_RSC_LSL_IMM),
-/* 0000 1110 0001 */ TABDECL( OP_RSC_LSL_REG),
-/* 0000 1110 0010 */ TABDECL( OP_RSC_LSR_IMM),
-/* 0000 1110 0011 */ TABDECL( OP_RSC_LSR_REG),
-/* 0000 1110 0100 */ TABDECL( OP_RSC_ASR_IMM),
-/* 0000 1110 0101 */ TABDECL( OP_RSC_ASR_REG),
-/* 0000 1110 0110 */ TABDECL( OP_RSC_ROR_IMM),
-/* 0000 1110 0111 */ TABDECL( OP_RSC_ROR_REG),
-/* 0000 1110 1000 */ TABDECL( OP_RSC_LSL_IMM),
-/* 0000 1110 1001 */ TABDECL( OP_SMLAL),
-/* 0000 1110 1010 */ TABDECL( OP_RSC_LSR_IMM), // OOO O111 O 1010
-/* 0000 1110 1011 */ TABDECL( OP_UND),
-/* 0000 1110 1100 */ TABDECL( OP_RSC_ASR_IMM),
-/* 0000 1110 1101 */ TABDECL( OP_UND),
-/* 0000 1110 1110 */ TABDECL( OP_RSC_ROR_IMM),
-/* 0000 1110 1111 */ TABDECL( OP_UND),
-/* 0000 1111 0000 */ TABDECL( OP_RSC_S_LSL_IMM),
-/* 0000 1111 0001 */ TABDECL( OP_RSC_S_LSL_REG),
-/* 0000 1111 0010 */ TABDECL( OP_RSC_S_LSR_IMM),
-/* 0000 1111 0011 */ TABDECL( OP_RSC_S_LSR_REG),
-/* 0000 1111 0100 */ TABDECL( OP_RSC_S_ASR_IMM),
-/* 0000 1111 0101 */ TABDECL( OP_RSC_S_ASR_REG),
-/* 0000 1111 0110 */ TABDECL( OP_RSC_S_ROR_IMM),
-/* 0000 1111 0111 */ TABDECL( OP_RSC_S_ROR_REG),
-/* 0000 1111 1000 */ TABDECL( OP_RSC_S_LSL_IMM),
-/* 0000 1111 1001 */ TABDECL( OP_SMLAL_S),
-/* 0000 1111 1010 */ TABDECL( OP_RSC_S_LSR_IMM),
-/* 0000 1111 1011 */ TABDECL( OP_UND),
-/* 0000 1111 1100 */ TABDECL( OP_RSC_S_ASR_IMM),
-/* 0000 1111 1101 */ TABDECL( OP_UND),
-/* 0000 1111 1110 */ TABDECL( OP_RSC_S_ROR_IMM),
-/* 0000 1111 1111 */ TABDECL( OP_UND),
-/* 0001 0000 0000 */ TABDECL( OP_MRS_CPSR),
-/* 0001 0000 0001 */ TABDECL( OP_UND),
-/* 0001 0000 0010 */ TABDECL( OP_UND),
-/* 0001 0000 0011 */ TABDECL( OP_UND),
-/* 0001 0000 0100 */ TABDECL( OP_UND),
-/* 0001 0000 0101 */ TABDECL( OP_QADD),
-/* 0001 0000 0110 */ TABDECL( OP_UND),
-/* 0001 0000 0111 */ TABDECL( OP_UND),
-/* 0001 0000 1000 */ TABDECL( OP_SMLA_B_B),
-/* 0001 0000 1001 */ TABDECL( OP_SWP),
-/* 0001 0000 1010 */ TABDECL( OP_SMLA_T_B),
-/* 0001 0000 1011 */ TABDECL( OP_STRH_M_REG_OFF),
-/* 0001 0000 1100 */ TABDECL( OP_SMLA_B_T),
-/* 0001 0000 1101 */ TABDECL( OP_LDRD_STRD_OFFSET_PRE_INDEX),
-/* 0001 0000 1110 */ TABDECL( OP_SMLA_T_T),
-/* 0001 0000 1111 */ TABDECL( OP_LDRD_STRD_OFFSET_PRE_INDEX),
-/* 0001 0001 0000 */ TABDECL( OP_TST_LSL_IMM),
-/* 0001 0001 0001 */ TABDECL( OP_TST_LSL_REG),
-/* 0001 0001 0010 */ TABDECL( OP_TST_LSR_IMM),
-/* 0001 0001 0011 */ TABDECL( OP_TST_LSR_REG),
-/* 0001 0001 0100 */ TABDECL( OP_TST_ASR_IMM),
-/* 0001 0001 0101 */ TABDECL( OP_TST_ASR_REG),
-/* 0001 0001 0110 */ TABDECL( OP_TST_ROR_IMM),
-/* 0001 0001 0111 */ TABDECL( OP_TST_ROR_REG),
-/* 0001 0001 1000 */ TABDECL( OP_TST_LSL_IMM),
-/* 0001 0001 1001 */ TABDECL( OP_UND),
-/* 0001 0001 1010 */ TABDECL( OP_TST_LSR_IMM), // OOO 100O 1 1010
-/* 0001 0001 1011 */ TABDECL( OP_LDRH_M_REG_OFF),
-/* 0001 0001 1100 */ TABDECL( OP_TST_ASR_IMM),
-/* 0001 0001 1101 */ TABDECL( OP_LDRSB_M_REG_OFF),
-/* 0001 0001 1110 */ TABDECL( OP_TST_ROR_IMM),
-/* 0001 0001 1111 */ TABDECL( OP_LDRSH_M_REG_OFF),
-/* 0001 0010 0000 */ TABDECL( OP_MSR_CPSR),
-/* 0001 0010 0001 */ TABDECL( OP_BX),
-/* 0001 0010 0010 */ TABDECL( OP_UND),
-/* 0001 0010 0011 */ TABDECL( OP_BLX_REG),
-/* 0001 0010 0100 */ TABDECL( OP_UND),
-/* 0001 0010 0101 */ TABDECL( OP_QSUB),
-/* 0001 0010 0110 */ TABDECL( OP_UND),
-/* 0001 0010 0111 */ TABDECL( OP_BKPT),
-/* 0001 0010 1000 */ TABDECL( OP_SMLAW_B),
-/* 0001 0010 1001 */ TABDECL( OP_UND),
-/* 0001 0010 1010 */ TABDECL( OP_SMULW_B),
-/* 0001 0010 1011 */ TABDECL( OP_STRH_PRE_INDE_M_REG_OFF),
-/* 0001 0010 1100 */ TABDECL( OP_SMLAW_T),
-/* 0001 0010 1101 */ TABDECL( OP_LDRD_STRD_OFFSET_PRE_INDEX),
-/* 0001 0010 1110 */ TABDECL( OP_SMULW_T),
-/* 0001 0010 1111 */ TABDECL( OP_LDRD_STRD_OFFSET_PRE_INDEX),
-/* 0001 0011 0000 */ TABDECL( OP_TEQ_LSL_IMM),
-/* 0001 0011 0001 */ TABDECL( OP_TEQ_LSL_REG),
-/* 0001 0011 0010 */ TABDECL( OP_TEQ_LSR_IMM),
-/* 0001 0011 0011 */ TABDECL( OP_TEQ_LSR_REG),
-/* 0001 0011 0100 */ TABDECL( OP_TEQ_ASR_IMM),
-/* 0001 0011 0101 */ TABDECL( OP_TEQ_ASR_REG),
-/* 0001 0011 0110 */ TABDECL( OP_TEQ_ROR_IMM),
-/* 0001 0011 0111 */ TABDECL( OP_TEQ_ROR_REG),
-/* 0001 0011 1000 */ TABDECL( OP_TEQ_LSL_IMM),
-/* 0001 0011 1001 */ TABDECL( OP_UND),
-/* 0001 0011 1010 */ TABDECL( OP_TEQ_LSR_IMM), // OOO 1001 1 1010
-/* 0001 0011 1011 */ TABDECL( OP_LDRH_PRE_INDE_M_REG_OFF),
-/* 0001 0011 1100 */ TABDECL( OP_TEQ_ASR_IMM),
-/* 0001 0011 1101 */ TABDECL( OP_LDRSB_PRE_INDE_M_REG_OFF),
-/* 0001 0011 1110 */ TABDECL( OP_TEQ_ROR_IMM),
-/* 0001 0011 1111 */ TABDECL( OP_LDRSH_PRE_INDE_M_REG_OFF),
-/* 0001 0100 0000 */ TABDECL( OP_MRS_SPSR),
-/* 0001 0100 0001 */ TABDECL( OP_UND),
-/* 0001 0100 0010 */ TABDECL( OP_UND),
-/* 0001 0100 0011 */ TABDECL( OP_UND),
-/* 0001 0100 0100 */ TABDECL( OP_UND),
-/* 0001 0100 0101 */ TABDECL( OP_QDADD),
-/* 0001 0100 0110 */ TABDECL( OP_UND),
-/* 0001 0100 0111 */ TABDECL( OP_UND),
-/* 0001 0100 1000 */ TABDECL( OP_SMLAL_B_B),
-/* 0001 0100 1001 */ TABDECL( OP_SWPB),
-/* 0001 0100 1010 */ TABDECL( OP_SMLAL_T_B),
-/* 0001 0100 1011 */ TABDECL( OP_STRH_M_IMM_OFF),
-/* 0001 0100 1100 */ TABDECL( OP_SMLAL_B_T),
-/* 0001 0100 1101 */ TABDECL( OP_LDRD_STRD_OFFSET_PRE_INDEX),
-/* 0001 0100 1110 */ TABDECL( OP_SMLAL_T_T),
-/* 0001 0100 1111 */ TABDECL( OP_LDRD_STRD_OFFSET_PRE_INDEX),
-/* 0001 0101 0000 */ TABDECL( OP_CMP_LSL_IMM),
-/* 0001 0101 0001 */ TABDECL( OP_CMP_LSL_REG),
-/* 0001 0101 0010 */ TABDECL( OP_CMP_LSR_IMM),
-/* 0001 0101 0011 */ TABDECL( OP_CMP_LSR_REG),
-/* 0001 0101 0100 */ TABDECL( OP_CMP_ASR_IMM),
-/* 0001 0101 0101 */ TABDECL( OP_CMP_ASR_REG),
-/* 0001 0101 0110 */ TABDECL( OP_CMP_ROR_IMM),
-/* 0001 0101 0111 */ TABDECL( OP_CMP_ROR_REG),
-/* 0001 0101 1000 */ TABDECL( OP_CMP_LSL_IMM),
-/* 0001 0101 1001 */ TABDECL( OP_UND),
-/* 0001 0101 1010 */ TABDECL( OP_CMP_LSR_IMM), // OOO 1O1O 1 1010
-/* 0001 0101 1011 */ TABDECL( OP_LDRH_M_IMM_OFF),
-/* 0001 0101 1100 */ TABDECL( OP_CMP_ASR_IMM),
-/* 0001 0101 1101 */ TABDECL( OP_LDRSB_M_IMM_OFF),
-/* 0001 0101 1110 */ TABDECL( OP_CMP_ROR_IMM),
-/* 0001 0101 1111 */ TABDECL( OP_LDRSH_M_IMM_OFF),
-/* 0001 0110 0000 */ TABDECL( OP_MSR_SPSR),
-/* 0001 0110 0001 */ TABDECL( OP_CLZ),
-/* 0001 0110 0010 */ TABDECL( OP_UND),
-/* 0001 0110 0011 */ TABDECL( OP_UND),
-/* 0001 0110 0100 */ TABDECL( OP_UND),
-/* 0001 0110 0101 */ TABDECL( OP_QDSUB),
-/* 0001 0110 0110 */ TABDECL( OP_UND),
-/* 0001 0110 0111 */ TABDECL( OP_UND),
-/* 0001 0110 1000 */ TABDECL( OP_SMUL_B_B),
-/* 0001 0110 1001 */ TABDECL( OP_UND),
-/* 0001 0110 1010 */ TABDECL( OP_SMUL_T_B),
-/* 0001 0110 1011 */ TABDECL( OP_STRH_PRE_INDE_M_IMM_OFF),
-/* 0001 0110 1100 */ TABDECL( OP_SMUL_B_T),
-/* 0001 0110 1101 */ TABDECL( OP_LDRD_STRD_OFFSET_PRE_INDEX),
-/* 0001 0110 1110 */ TABDECL( OP_SMUL_T_T),
-/* 0001 0110 1111 */ TABDECL( OP_LDRD_STRD_OFFSET_PRE_INDEX),
-/* 0001 0111 0000 */ TABDECL( OP_CMN_LSL_IMM),
-/* 0001 0111 0001 */ TABDECL( OP_CMN_LSL_REG),
-/* 0001 0111 0010 */ TABDECL( OP_CMN_LSR_IMM),
-/* 0001 0111 0011 */ TABDECL( OP_CMN_LSR_REG),
-/* 0001 0111 0100 */ TABDECL( OP_CMN_ASR_IMM),
-/* 0001 0111 0101 */ TABDECL( OP_CMN_ASR_REG),
-/* 0001 0111 0110 */ TABDECL( OP_CMN_ROR_IMM),
-/* 0001 0111 0111 */ TABDECL( OP_CMN_ROR_REG),
-/* 0001 0111 1000 */ TABDECL( OP_CMN_LSL_IMM),
-/* 0001 0111 1001 */ TABDECL( OP_UND),
-/* 0001 0111 1010 */ TABDECL( OP_CMN_LSR_IMM), // OOO 1O11 1 1010
-/* 0001 0111 1011 */ TABDECL( OP_LDRH_PRE_INDE_M_IMM_OFF),
-/* 0001 0111 1100 */ TABDECL( OP_CMN_ASR_IMM),
-/* 0001 0111 1101 */ TABDECL( OP_LDRSB_PRE_INDE_M_IMM_OFF),
-/* 0001 0111 1110 */ TABDECL( OP_CMN_ROR_IMM),
-/* 0001 0111 1111 */ TABDECL( OP_LDRSH_PRE_INDE_M_IMM_OFF),
-/* 0001 1000 0000 */ TABDECL( OP_ORR_LSL_IMM),
-/* 0001 1000 0001 */ TABDECL( OP_ORR_LSL_REG),
-/* 0001 1000 0010 */ TABDECL( OP_ORR_LSR_IMM),
-/* 0001 1000 0011 */ TABDECL( OP_ORR_LSR_REG),
-/* 0001 1000 0100 */ TABDECL( OP_ORR_ASR_IMM),
-/* 0001 1000 0101 */ TABDECL( OP_ORR_ASR_REG),
-/* 0001 1000 0110 */ TABDECL( OP_ORR_ROR_IMM),
-/* 0001 1000 0111 */ TABDECL( OP_ORR_ROR_REG),
-/* 0001 1000 1000 */ TABDECL( OP_ORR_LSL_IMM),
-/* 0001 1000 1001 */ TABDECL( OP_STREX),
-/* 0001 1000 1010 */ TABDECL( OP_ORR_LSR_IMM), // OOO 110O O 1010
-/* 0001 1000 1011 */ TABDECL( OP_STRH_P_REG_OFF),
-/* 0001 1000 1100 */ TABDECL( OP_ORR_ASR_IMM),
-/* 0001 1000 1101 */ TABDECL( OP_LDRD_STRD_OFFSET_PRE_INDEX),
-/* 0001 1000 1110 */ TABDECL( OP_ORR_ROR_IMM),
-/* 0001 1000 1111 */ TABDECL( OP_LDRD_STRD_OFFSET_PRE_INDEX),
-/* 0001 1001 0000 */ TABDECL( OP_ORR_S_LSL_IMM),
-/* 0001 1001 0001 */ TABDECL( OP_ORR_S_LSL_REG),
-/* 0001 1001 0010 */ TABDECL( OP_ORR_S_LSR_IMM),
-/* 0001 1001 0011 */ TABDECL( OP_ORR_S_LSR_REG),
-/* 0001 1001 0100 */ TABDECL( OP_ORR_S_ASR_IMM),
-/* 0001 1001 0101 */ TABDECL( OP_ORR_S_ASR_REG),
-/* 0001 1001 0110 */ TABDECL( OP_ORR_S_ROR_IMM),
-/* 0001 1001 0111 */ TABDECL( OP_ORR_S_ROR_REG),
-/* 0001 1001 1000 */ TABDECL( OP_ORR_S_LSL_IMM),
-/* 0001 1001 1001 */ TABDECL( OP_LDREX),
-/* 0001 1001 1010 */ TABDECL( OP_ORR_S_LSR_IMM),
-/* 0001 1001 1011 */ TABDECL( OP_LDRH_P_REG_OFF),
-/* 0001 1001 1100 */ TABDECL( OP_ORR_S_ASR_IMM),
-/* 0001 1001 1101 */ TABDECL( OP_LDRSB_P_REG_OFF),
-/* 0001 1001 1110 */ TABDECL( OP_ORR_S_ROR_IMM),
-/* 0001 1001 1111 */ TABDECL( OP_LDRSH_P_REG_OFF),
-/* 0001 1010 0000 */ TABDECL( OP_MOV_LSL_IMM),
-/* 0001 1010 0001 */ TABDECL( OP_MOV_LSL_REG),
-/* 0001 1010 0010 */ TABDECL( OP_MOV_LSR_IMM),
-/* 0001 1010 0011 */ TABDECL( OP_MOV_LSR_REG),
-/* 0001 1010 0100 */ TABDECL( OP_MOV_ASR_IMM),
-/* 0001 1010 0101 */ TABDECL( OP_MOV_ASR_REG),
-/* 0001 1010 0110 */ TABDECL( OP_MOV_ROR_IMM),
-/* 0001 1010 0111 */ TABDECL( OP_MOV_ROR_REG),
-/* 0001 1010 1000 */ TABDECL( OP_MOV_LSL_IMM),
-/* 0001 1010 1001 */ TABDECL( OP_UND),
-/* 0001 1010 1010 */ TABDECL( OP_MOV_LSR_IMM), // OOO 1101 O 1010
-/* 0001 1010 1011 */ TABDECL( OP_STRH_PRE_INDE_P_REG_OFF),
-/* 0001 1010 1100 */ TABDECL( OP_MOV_ASR_IMM),
-/* 0001 1010 1101 */ TABDECL( OP_LDRD_STRD_OFFSET_PRE_INDEX),
-/* 0001 1010 1110 */ TABDECL( OP_MOV_ROR_IMM),
-/* 0001 1010 1111 */ TABDECL( OP_LDRD_STRD_OFFSET_PRE_INDEX),
-/* 0001 1011 0000 */ TABDECL( OP_MOV_S_LSL_IMM),
-/* 0001 1011 0001 */ TABDECL( OP_MOV_S_LSL_REG),
-/* 0001 1011 0010 */ TABDECL( OP_MOV_S_LSR_IMM),
-/* 0001 1011 0011 */ TABDECL( OP_MOV_S_LSR_REG),
-/* 0001 1011 0100 */ TABDECL( OP_MOV_S_ASR_IMM),
-/* 0001 1011 0101 */ TABDECL( OP_MOV_S_ASR_REG),
-/* 0001 1011 0110 */ TABDECL( OP_MOV_S_ROR_IMM),
-/* 0001 1011 0111 */ TABDECL( OP_MOV_S_ROR_REG),
-/* 0001 1011 1000 */ TABDECL( OP_MOV_S_LSL_IMM),
-/* 0001 1011 1001 */ TABDECL( OP_UND),
-/* 0001 1011 1010 */ TABDECL( OP_MOV_S_LSR_IMM),
-/* 0001 1011 1011 */ TABDECL( OP_LDRH_PRE_INDE_P_REG_OFF),
-/* 0001 1011 1100 */ TABDECL( OP_MOV_S_ASR_IMM),
-/* 0001 1011 1101 */ TABDECL( OP_LDRSB_PRE_INDE_P_REG_OFF),
-/* 0001 1011 1110 */ TABDECL( OP_MOV_S_ROR_IMM),
-/* 0001 1011 1111 */ TABDECL( OP_LDRSH_PRE_INDE_P_REG_OFF),
-/* 0001 1100 0000 */ TABDECL( OP_BIC_LSL_IMM),
-/* 0001 1100 0001 */ TABDECL( OP_BIC_LSL_REG),
-/* 0001 1100 0010 */ TABDECL( OP_BIC_LSR_IMM),
-/* 0001 1100 0011 */ TABDECL( OP_BIC_LSR_REG),
-/* 0001 1100 0100 */ TABDECL( OP_BIC_ASR_IMM),
-/* 0001 1100 0101 */ TABDECL( OP_BIC_ASR_REG),
-/* 0001 1100 0110 */ TABDECL( OP_BIC_ROR_IMM),
-/* 0001 1100 0111 */ TABDECL( OP_BIC_ROR_REG),
-/* 0001 1100 1000 */ TABDECL( OP_BIC_LSL_IMM),
-/* 0001 1100 1001 */ TABDECL( OP_UND),
-/* 0001 1100 1010 */ TABDECL( OP_BIC_LSR_IMM), // OOO 111O O 1010
-/* 0001 1100 1011 */ TABDECL( OP_STRH_P_IMM_OFF),
-/* 0001 1100 1100 */ TABDECL( OP_BIC_ASR_IMM),
-/* 0001 1100 1101 */ TABDECL( OP_LDRD_STRD_OFFSET_PRE_INDEX),
-/* 0001 1100 1110 */ TABDECL( OP_BIC_ROR_IMM),
-/* 0001 1100 1111 */ TABDECL( OP_LDRD_STRD_OFFSET_PRE_INDEX),
-/* 0001 1101 0000 */ TABDECL( OP_BIC_S_LSL_IMM),
-/* 0001 1101 0001 */ TABDECL( OP_BIC_S_LSL_REG),
-/* 0001 1101 0010 */ TABDECL( OP_BIC_S_LSR_IMM),
-/* 0001 1101 0011 */ TABDECL( OP_BIC_S_LSR_REG),
-/* 0001 1101 0100 */ TABDECL( OP_BIC_S_ASR_IMM),
-/* 0001 1101 0101 */ TABDECL( OP_BIC_S_ASR_REG),
-/* 0001 1101 0110 */ TABDECL( OP_BIC_S_ROR_IMM),
-/* 0001 1101 0111 */ TABDECL( OP_BIC_S_ROR_REG),
-/* 0001 1101 1000 */ TABDECL( OP_BIC_S_LSL_IMM),
-/* 0001 1101 1001 */ TABDECL( OP_UND),
-/* 0001 1101 1010 */ TABDECL( OP_BIC_S_LSR_IMM),
-/* 0001 1101 1011 */ TABDECL( OP_LDRH_P_IMM_OFF),
-/* 0001 1101 1100 */ TABDECL( OP_BIC_S_ASR_IMM),
-/* 0001 1101 1101 */ TABDECL( OP_LDRSB_P_IMM_OFF),
-/* 0001 1101 1110 */ TABDECL( OP_BIC_S_ROR_IMM),
-/* 0001 1101 1111 */ TABDECL( OP_LDRSH_P_IMM_OFF),
-/* 0001 1110 0000 */ TABDECL( OP_MVN_LSL_IMM),
-/* 0001 1110 0001 */ TABDECL( OP_MVN_LSL_REG),
-/* 0001 1110 0010 */ TABDECL( OP_MVN_LSR_IMM),
-/* 0001 1110 0011 */ TABDECL( OP_MVN_LSR_REG),
-/* 0001 1110 0100 */ TABDECL( OP_MVN_ASR_IMM),
-/* 0001 1110 0101 */ TABDECL( OP_MVN_ASR_REG),
-/* 0001 1110 0110 */ TABDECL( OP_MVN_ROR_IMM),
-/* 0001 1110 0111 */ TABDECL( OP_MVN_ROR_REG),
-/* 0001 1110 1000 */ TABDECL( OP_MVN_LSL_IMM),
-/* 0001 1110 1001 */ TABDECL( OP_UND),
-/* 0001 1110 1010 */ TABDECL( OP_MVN_LSR_IMM), // OOO 1111 O 1010
-/* 0001 1110 1011 */ TABDECL( OP_STRH_PRE_INDE_P_IMM_OFF),
-/* 0001 1110 1100 */ TABDECL( OP_MVN_ASR_IMM),
-/* 0001 1110 1101 */ TABDECL( OP_LDRD_STRD_OFFSET_PRE_INDEX),
-/* 0001 1110 1110 */ TABDECL( OP_MVN_ROR_IMM),
-/* 0001 1110 1111 */ TABDECL( OP_LDRD_STRD_OFFSET_PRE_INDEX),
-/* 0001 1111 0000 */ TABDECL( OP_MVN_S_LSL_IMM),
-/* 0001 1111 0001 */ TABDECL( OP_MVN_S_LSL_REG),
-/* 0001 1111 0010 */ TABDECL( OP_MVN_S_LSR_IMM),
-/* 0001 1111 0011 */ TABDECL( OP_MVN_S_LSR_REG),
-/* 0001 1111 0100 */ TABDECL( OP_MVN_S_ASR_IMM),
-/* 0001 1111 0101 */ TABDECL( OP_MVN_S_ASR_REG),
-/* 0001 1111 0110 */ TABDECL( OP_MVN_S_ROR_IMM),
-/* 0001 1111 0111 */ TABDECL( OP_MVN_S_ROR_REG),
-/* 0001 1111 1000 */ TABDECL( OP_MVN_S_LSL_IMM),
-/* 0001 1111 1001 */ TABDECL( OP_UND),
-/* 0001 1111 1010 */ TABDECL( OP_MVN_S_LSR_IMM),
-/* 0001 1111 1011 */ TABDECL( OP_LDRH_PRE_INDE_P_IMM_OFF),
-/* 0001 1111 1100 */ TABDECL( OP_MVN_S_ASR_IMM),
-/* 0001 1111 1101 */ TABDECL( OP_LDRSB_PRE_INDE_P_IMM_OFF),
-/* 0001 1111 1110 */ TABDECL( OP_MVN_S_ROR_IMM),
-/* 0001 1111 1111 */ TABDECL( OP_LDRSH_PRE_INDE_P_IMM_OFF),
-/* 0010 0000 0000 */ TABDECL( OP_AND_IMM_VAL),
-/* 0010 0000 0001 */ TABDECL( OP_AND_IMM_VAL),
-/* 0010 0000 0010 */ TABDECL( OP_AND_IMM_VAL),
-/* 0010 0000 0011 */ TABDECL( OP_AND_IMM_VAL),
-/* 0010 0000 0100 */ TABDECL( OP_AND_IMM_VAL),
-/* 0010 0000 0101 */ TABDECL( OP_AND_IMM_VAL),
-/* 0010 0000 0110 */ TABDECL( OP_AND_IMM_VAL),
-/* 0010 0000 0111 */ TABDECL( OP_AND_IMM_VAL),
-/* 0010 0000 1000 */ TABDECL( OP_AND_IMM_VAL),
-/* 0010 0000 1001 */ TABDECL( OP_AND_IMM_VAL),
-/* 0010 0000 1010 */ TABDECL( OP_AND_IMM_VAL),
-/* 0010 0000 1011 */ TABDECL( OP_AND_IMM_VAL),
-/* 0010 0000 1100 */ TABDECL( OP_AND_IMM_VAL),
-/* 0010 0000 1101 */ TABDECL( OP_AND_IMM_VAL),
-/* 0010 0000 1110 */ TABDECL( OP_AND_IMM_VAL),
-/* 0010 0000 1111 */ TABDECL( OP_AND_IMM_VAL),
-/* 0010 0001 0000 */ TABDECL( OP_AND_S_IMM_VAL),
-/* 0010 0001 0001 */ TABDECL( OP_AND_S_IMM_VAL),
-/* 0010 0001 0010 */ TABDECL( OP_AND_S_IMM_VAL),
-/* 0010 0001 0011 */ TABDECL( OP_AND_S_IMM_VAL),
-/* 0010 0001 0100 */ TABDECL( OP_AND_S_IMM_VAL),
-/* 0010 0001 0101 */ TABDECL( OP_AND_S_IMM_VAL),
-/* 0010 0001 0110 */ TABDECL( OP_AND_S_IMM_VAL),
-/* 0010 0001 0111 */ TABDECL( OP_AND_S_IMM_VAL),
-/* 0010 0001 1000 */ TABDECL( OP_AND_S_IMM_VAL),
-/* 0010 0001 1001 */ TABDECL( OP_AND_S_IMM_VAL),
-/* 0010 0001 1010 */ TABDECL( OP_AND_S_IMM_VAL),
-/* 0010 0001 1011 */ TABDECL( OP_AND_S_IMM_VAL),
-/* 0010 0001 1100 */ TABDECL( OP_AND_S_IMM_VAL),
-/* 0010 0001 1101 */ TABDECL( OP_AND_S_IMM_VAL),
-/* 0010 0001 1110 */ TABDECL( OP_AND_S_IMM_VAL),
-/* 0010 0001 1111 */ TABDECL( OP_AND_S_IMM_VAL),
-/* 0010 0010 0000 */ TABDECL( OP_EOR_IMM_VAL),
-/* 0010 0010 0001 */ TABDECL( OP_EOR_IMM_VAL),
-/* 0010 0010 0010 */ TABDECL( OP_EOR_IMM_VAL),
-/* 0010 0010 0011 */ TABDECL( OP_EOR_IMM_VAL),
-/* 0010 0010 0100 */ TABDECL( OP_EOR_IMM_VAL),
-/* 0010 0010 0101 */ TABDECL( OP_EOR_IMM_VAL),
-/* 0010 0010 0110 */ TABDECL( OP_EOR_IMM_VAL),
-/* 0010 0010 0111 */ TABDECL( OP_EOR_IMM_VAL),
-/* 0010 0010 1000 */ TABDECL( OP_EOR_IMM_VAL),
-/* 0010 0010 1001 */ TABDECL( OP_EOR_IMM_VAL),
-/* 0010 0010 1010 */ TABDECL( OP_EOR_IMM_VAL),
-/* 0010 0010 1011 */ TABDECL( OP_EOR_IMM_VAL),
-/* 0010 0010 1100 */ TABDECL( OP_EOR_IMM_VAL),
-/* 0010 0010 1101 */ TABDECL( OP_EOR_IMM_VAL),
-/* 0010 0010 1110 */ TABDECL( OP_EOR_IMM_VAL),
-/* 0010 0010 1111 */ TABDECL( OP_EOR_IMM_VAL),
-/* 0010 0011 0000 */ TABDECL( OP_EOR_S_IMM_VAL),
-/* 0010 0011 0001 */ TABDECL( OP_EOR_S_IMM_VAL),
-/* 0010 0011 0010 */ TABDECL( OP_EOR_S_IMM_VAL),
-/* 0010 0011 0011 */ TABDECL( OP_EOR_S_IMM_VAL),
-/* 0010 0011 0100 */ TABDECL( OP_EOR_S_IMM_VAL),
-/* 0010 0011 0101 */ TABDECL( OP_EOR_S_IMM_VAL),
-/* 0010 0011 0110 */ TABDECL( OP_EOR_S_IMM_VAL),
-/* 0010 0011 0111 */ TABDECL( OP_EOR_S_IMM_VAL),
-/* 0010 0011 1000 */ TABDECL( OP_EOR_S_IMM_VAL),
-/* 0010 0011 1001 */ TABDECL( OP_EOR_S_IMM_VAL),
-/* 0010 0011 1010 */ TABDECL( OP_EOR_S_IMM_VAL),
-/* 0010 0011 1011 */ TABDECL( OP_EOR_S_IMM_VAL),
-/* 0010 0011 1100 */ TABDECL( OP_EOR_S_IMM_VAL),
-/* 0010 0011 1101 */ TABDECL( OP_EOR_S_IMM_VAL),
-/* 0010 0011 1110 */ TABDECL( OP_EOR_S_IMM_VAL),
-/* 0010 0011 1111 */ TABDECL( OP_EOR_S_IMM_VAL),
-/* 0010 0100 0000 */ TABDECL( OP_SUB_IMM_VAL),
-/* 0010 0100 0001 */ TABDECL( OP_SUB_IMM_VAL),
-/* 0010 0100 0010 */ TABDECL( OP_SUB_IMM_VAL),
-/* 0010 0100 0011 */ TABDECL( OP_SUB_IMM_VAL),
-/* 0010 0100 0100 */ TABDECL( OP_SUB_IMM_VAL),
-/* 0010 0100 0101 */ TABDECL( OP_SUB_IMM_VAL),
-/* 0010 0100 0110 */ TABDECL( OP_SUB_IMM_VAL),
-/* 0010 0100 0111 */ TABDECL( OP_SUB_IMM_VAL),
-/* 0010 0100 1000 */ TABDECL( OP_SUB_IMM_VAL),
-/* 0010 0100 1001 */ TABDECL( OP_SUB_IMM_VAL),
-/* 0010 0100 1010 */ TABDECL( OP_SUB_IMM_VAL),
-/* 0010 0100 1011 */ TABDECL( OP_SUB_IMM_VAL),
-/* 0010 0100 1100 */ TABDECL( OP_SUB_IMM_VAL),
-/* 0010 0100 1101 */ TABDECL( OP_SUB_IMM_VAL),
-/* 0010 0100 1110 */ TABDECL( OP_SUB_IMM_VAL),
-/* 0010 0100 1111 */ TABDECL( OP_SUB_IMM_VAL),
-/* 0010 0101 0000 */ TABDECL( OP_SUB_S_IMM_VAL),
-/* 0010 0101 0001 */ TABDECL( OP_SUB_S_IMM_VAL),
-/* 0010 0101 0010 */ TABDECL( OP_SUB_S_IMM_VAL),
-/* 0010 0101 0011 */ TABDECL( OP_SUB_S_IMM_VAL),
-/* 0010 0101 0100 */ TABDECL( OP_SUB_S_IMM_VAL),
-/* 0010 0101 0101 */ TABDECL( OP_SUB_S_IMM_VAL),
-/* 0010 0101 0110 */ TABDECL( OP_SUB_S_IMM_VAL),
-/* 0010 0101 0111 */ TABDECL( OP_SUB_S_IMM_VAL),
-/* 0010 0101 1000 */ TABDECL( OP_SUB_S_IMM_VAL),
-/* 0010 0101 1001 */ TABDECL( OP_SUB_S_IMM_VAL),
-/* 0010 0101 1010 */ TABDECL( OP_SUB_S_IMM_VAL),
-/* 0010 0101 1011 */ TABDECL( OP_SUB_S_IMM_VAL),
-/* 0010 0101 1100 */ TABDECL( OP_SUB_S_IMM_VAL),
-/* 0010 0101 1101 */ TABDECL( OP_SUB_S_IMM_VAL),
-/* 0010 0101 1110 */ TABDECL( OP_SUB_S_IMM_VAL),
-/* 0010 0101 1111 */ TABDECL( OP_SUB_S_IMM_VAL),
-/* 0010 0110 0000 */ TABDECL( OP_RSB_IMM_VAL),
-/* 0010 0110 0001 */ TABDECL( OP_RSB_IMM_VAL),
-/* 0010 0110 0010 */ TABDECL( OP_RSB_IMM_VAL),
-/* 0010 0110 0011 */ TABDECL( OP_RSB_IMM_VAL),
-/* 0010 0110 0100 */ TABDECL( OP_RSB_IMM_VAL),
-/* 0010 0110 0101 */ TABDECL( OP_RSB_IMM_VAL),
-/* 0010 0110 0110 */ TABDECL( OP_RSB_IMM_VAL),
-/* 0010 0110 0111 */ TABDECL( OP_RSB_IMM_VAL),
-/* 0010 0110 1000 */ TABDECL( OP_RSB_IMM_VAL),
-/* 0010 0110 1001 */ TABDECL( OP_RSB_IMM_VAL),
-/* 0010 0110 1010 */ TABDECL( OP_RSB_IMM_VAL),
-/* 0010 0110 1011 */ TABDECL( OP_RSB_IMM_VAL),
-/* 0010 0110 1100 */ TABDECL( OP_RSB_IMM_VAL),
-/* 0010 0110 1101 */ TABDECL( OP_RSB_IMM_VAL),
-/* 0010 0110 1110 */ TABDECL( OP_RSB_IMM_VAL),
-/* 0010 0110 1111 */ TABDECL( OP_RSB_IMM_VAL),
-/* 0010 0111 0000 */ TABDECL( OP_RSB_S_IMM_VAL),
-/* 0010 0111 0001 */ TABDECL( OP_RSB_S_IMM_VAL),
-/* 0010 0111 0010 */ TABDECL( OP_RSB_S_IMM_VAL),
-/* 0010 0111 0011 */ TABDECL( OP_RSB_S_IMM_VAL),
-/* 0010 0111 0100 */ TABDECL( OP_RSB_S_IMM_VAL),
-/* 0010 0111 0101 */ TABDECL( OP_RSB_S_IMM_VAL),
-/* 0010 0111 0110 */ TABDECL( OP_RSB_S_IMM_VAL),
-/* 0010 0111 0111 */ TABDECL( OP_RSB_S_IMM_VAL),
-/* 0010 0111 1000 */ TABDECL( OP_RSB_S_IMM_VAL),
-/* 0010 0111 1001 */ TABDECL( OP_RSB_S_IMM_VAL),
-/* 0010 0111 1010 */ TABDECL( OP_RSB_S_IMM_VAL),
-/* 0010 0111 1011 */ TABDECL( OP_RSB_S_IMM_VAL),
-/* 0010 0111 1100 */ TABDECL( OP_RSB_S_IMM_VAL),
-/* 0010 0111 1101 */ TABDECL( OP_RSB_S_IMM_VAL),
-/* 0010 0111 1110 */ TABDECL( OP_RSB_S_IMM_VAL),
-/* 0010 0111 1111 */ TABDECL( OP_RSB_S_IMM_VAL),
-/* 0010 1000 0000 */ TABDECL( OP_ADD_IMM_VAL),
-/* 0010 1000 0001 */ TABDECL( OP_ADD_IMM_VAL),
-/* 0010 1000 0010 */ TABDECL( OP_ADD_IMM_VAL),
-/* 0010 1000 0011 */ TABDECL( OP_ADD_IMM_VAL),
-/* 0010 1000 0100 */ TABDECL( OP_ADD_IMM_VAL),
-/* 0010 1000 0101 */ TABDECL( OP_ADD_IMM_VAL),
-/* 0010 1000 0110 */ TABDECL( OP_ADD_IMM_VAL),
-/* 0010 1000 0111 */ TABDECL( OP_ADD_IMM_VAL),
-/* 0010 1000 1000 */ TABDECL( OP_ADD_IMM_VAL),
-/* 0010 1000 1001 */ TABDECL( OP_ADD_IMM_VAL),
-/* 0010 1000 1010 */ TABDECL( OP_ADD_IMM_VAL),
-/* 0010 1000 1011 */ TABDECL( OP_ADD_IMM_VAL),
-/* 0010 1000 1100 */ TABDECL( OP_ADD_IMM_VAL),
-/* 0010 1000 1101 */ TABDECL( OP_ADD_IMM_VAL),
-/* 0010 1000 1110 */ TABDECL( OP_ADD_IMM_VAL),
-/* 0010 1000 1111 */ TABDECL( OP_ADD_IMM_VAL),
-/* 0010 1001 0000 */ TABDECL( OP_ADD_S_IMM_VAL),
-/* 0010 1001 0001 */ TABDECL( OP_ADD_S_IMM_VAL),
-/* 0010 1001 0010 */ TABDECL( OP_ADD_S_IMM_VAL),
-/* 0010 1001 0011 */ TABDECL( OP_ADD_S_IMM_VAL),
-/* 0010 1001 0100 */ TABDECL( OP_ADD_S_IMM_VAL),
-/* 0010 1001 0101 */ TABDECL( OP_ADD_S_IMM_VAL),
-/* 0010 1001 0110 */ TABDECL( OP_ADD_S_IMM_VAL),
-/* 0010 1001 0111 */ TABDECL( OP_ADD_S_IMM_VAL),
-/* 0010 1001 1000 */ TABDECL( OP_ADD_S_IMM_VAL),
-/* 0010 1001 1001 */ TABDECL( OP_ADD_S_IMM_VAL),
-/* 0010 1001 1010 */ TABDECL( OP_ADD_S_IMM_VAL),
-/* 0010 1001 1011 */ TABDECL( OP_ADD_S_IMM_VAL),
-/* 0010 1001 1100 */ TABDECL( OP_ADD_S_IMM_VAL),
-/* 0010 1001 1101 */ TABDECL( OP_ADD_S_IMM_VAL),
-/* 0010 1001 1110 */ TABDECL( OP_ADD_S_IMM_VAL),
-/* 0010 1001 1111 */ TABDECL( OP_ADD_S_IMM_VAL),
-/* 0010 1010 0000 */ TABDECL( OP_ADC_IMM_VAL),
-/* 0010 1010 0001 */ TABDECL( OP_ADC_IMM_VAL),
-/* 0010 1010 0010 */ TABDECL( OP_ADC_IMM_VAL),
-/* 0010 1010 0011 */ TABDECL( OP_ADC_IMM_VAL),
-/* 0010 1010 0100 */ TABDECL( OP_ADC_IMM_VAL),
-/* 0010 1010 0101 */ TABDECL( OP_ADC_IMM_VAL),
-/* 0010 1010 0110 */ TABDECL( OP_ADC_IMM_VAL),
-/* 0010 1010 0111 */ TABDECL( OP_ADC_IMM_VAL),
-/* 0010 1010 1000 */ TABDECL( OP_ADC_IMM_VAL),
-/* 0010 1010 1001 */ TABDECL( OP_ADC_IMM_VAL),
-/* 0010 1010 1010 */ TABDECL( OP_ADC_IMM_VAL),
-/* 0010 1010 1011 */ TABDECL( OP_ADC_IMM_VAL),
-/* 0010 1010 1100 */ TABDECL( OP_ADC_IMM_VAL),
-/* 0010 1010 1101 */ TABDECL( OP_ADC_IMM_VAL),
-/* 0010 1010 1110 */ TABDECL( OP_ADC_IMM_VAL),
-/* 0010 1010 1111 */ TABDECL( OP_ADC_IMM_VAL),
-/* 0010 1011 0000 */ TABDECL( OP_ADC_S_IMM_VAL),
-/* 0010 1011 0001 */ TABDECL( OP_ADC_S_IMM_VAL),
-/* 0010 1011 0010 */ TABDECL( OP_ADC_S_IMM_VAL),
-/* 0010 1011 0011 */ TABDECL( OP_ADC_S_IMM_VAL),
-/* 0010 1011 0100 */ TABDECL( OP_ADC_S_IMM_VAL),
-/* 0010 1011 0101 */ TABDECL( OP_ADC_S_IMM_VAL),
-/* 0010 1011 0110 */ TABDECL( OP_ADC_S_IMM_VAL),
-/* 0010 1011 0111 */ TABDECL( OP_ADC_S_IMM_VAL),
-/* 0010 1011 1000 */ TABDECL( OP_ADC_S_IMM_VAL),
-/* 0010 1011 1001 */ TABDECL( OP_ADC_S_IMM_VAL),
-/* 0010 1011 1010 */ TABDECL( OP_ADC_S_IMM_VAL),
-/* 0010 1011 1011 */ TABDECL( OP_ADC_S_IMM_VAL),
-/* 0010 1011 1100 */ TABDECL( OP_ADC_S_IMM_VAL),
-/* 0010 1011 1101 */ TABDECL( OP_ADC_S_IMM_VAL),
-/* 0010 1011 1110 */ TABDECL( OP_ADC_S_IMM_VAL),
-/* 0010 1011 1111 */ TABDECL( OP_ADC_S_IMM_VAL),
-/* 0010 1100 0000 */ TABDECL( OP_SBC_IMM_VAL),
-/* 0010 1100 0001 */ TABDECL( OP_SBC_IMM_VAL),
-/* 0010 1100 0010 */ TABDECL( OP_SBC_IMM_VAL),
-/* 0010 1100 0011 */ TABDECL( OP_SBC_IMM_VAL),
-/* 0010 1100 0100 */ TABDECL( OP_SBC_IMM_VAL),
-/* 0010 1100 0101 */ TABDECL( OP_SBC_IMM_VAL),
-/* 0010 1100 0110 */ TABDECL( OP_SBC_IMM_VAL),
-/* 0010 1100 0111 */ TABDECL( OP_SBC_IMM_VAL),
-/* 0010 1100 1000 */ TABDECL( OP_SBC_IMM_VAL),
-/* 0010 1100 1001 */ TABDECL( OP_SBC_IMM_VAL),
-/* 0010 1100 1010 */ TABDECL( OP_SBC_IMM_VAL),
-/* 0010 1100 1011 */ TABDECL( OP_SBC_IMM_VAL),
-/* 0010 1100 1100 */ TABDECL( OP_SBC_IMM_VAL),
-/* 0010 1100 1101 */ TABDECL( OP_SBC_IMM_VAL),
-/* 0010 1100 1110 */ TABDECL( OP_SBC_IMM_VAL),
-/* 0010 1100 1111 */ TABDECL( OP_SBC_IMM_VAL),
-/* 0010 1101 0000 */ TABDECL( OP_SBC_S_IMM_VAL),
-/* 0010 1101 0001 */ TABDECL( OP_SBC_S_IMM_VAL),
-/* 0010 1101 0010 */ TABDECL( OP_SBC_S_IMM_VAL),
-/* 0010 1101 0011 */ TABDECL( OP_SBC_S_IMM_VAL),
-/* 0010 1101 0100 */ TABDECL( OP_SBC_S_IMM_VAL),
-/* 0010 1101 0101 */ TABDECL( OP_SBC_S_IMM_VAL),
-/* 0010 1101 0110 */ TABDECL( OP_SBC_S_IMM_VAL),
-/* 0010 1101 0111 */ TABDECL( OP_SBC_S_IMM_VAL),
-/* 0010 1101 1000 */ TABDECL( OP_SBC_S_IMM_VAL),
-/* 0010 1101 1001 */ TABDECL( OP_SBC_S_IMM_VAL),
-/* 0010 1101 1010 */ TABDECL( OP_SBC_S_IMM_VAL),
-/* 0010 1101 1011 */ TABDECL( OP_SBC_S_IMM_VAL),
-/* 0010 1101 1100 */ TABDECL( OP_SBC_S_IMM_VAL),
-/* 0010 1101 1101 */ TABDECL( OP_SBC_S_IMM_VAL),
-/* 0010 1101 1110 */ TABDECL( OP_SBC_S_IMM_VAL),
-/* 0010 1101 1111 */ TABDECL( OP_SBC_S_IMM_VAL),
-/* 0010 1110 0000 */ TABDECL( OP_RSC_IMM_VAL),
-/* 0010 1110 0001 */ TABDECL( OP_RSC_IMM_VAL),
-/* 0010 1110 0010 */ TABDECL( OP_RSC_IMM_VAL),
-/* 0010 1110 0011 */ TABDECL( OP_RSC_IMM_VAL),
-/* 0010 1110 0100 */ TABDECL( OP_RSC_IMM_VAL),
-/* 0010 1110 0101 */ TABDECL( OP_RSC_IMM_VAL),
-/* 0010 1110 0110 */ TABDECL( OP_RSC_IMM_VAL),
-/* 0010 1110 0111 */ TABDECL( OP_RSC_IMM_VAL),
-/* 0010 1110 1000 */ TABDECL( OP_RSC_IMM_VAL),
-/* 0010 1110 1001 */ TABDECL( OP_RSC_IMM_VAL),
-/* 0010 1110 1010 */ TABDECL( OP_RSC_IMM_VAL),
-/* 0010 1110 1011 */ TABDECL( OP_RSC_IMM_VAL),
-/* 0010 1110 1100 */ TABDECL( OP_RSC_IMM_VAL),
-/* 0010 1110 1101 */ TABDECL( OP_RSC_IMM_VAL),
-/* 0010 1110 1110 */ TABDECL( OP_RSC_IMM_VAL),
-/* 0010 1110 1111 */ TABDECL( OP_RSC_IMM_VAL),
-/* 0010 1111 0000 */ TABDECL( OP_RSC_S_IMM_VAL),
-/* 0010 1111 0001 */ TABDECL( OP_RSC_S_IMM_VAL),
-/* 0010 1111 0010 */ TABDECL( OP_RSC_S_IMM_VAL),
-/* 0010 1111 0011 */ TABDECL( OP_RSC_S_IMM_VAL),
-/* 0010 1111 0100 */ TABDECL( OP_RSC_S_IMM_VAL),
-/* 0010 1111 0101 */ TABDECL( OP_RSC_S_IMM_VAL),
-/* 0010 1111 0110 */ TABDECL( OP_RSC_S_IMM_VAL),
-/* 0010 1111 0111 */ TABDECL( OP_RSC_S_IMM_VAL),
-/* 0010 1111 1000 */ TABDECL( OP_RSC_S_IMM_VAL),
-/* 0010 1111 1001 */ TABDECL( OP_RSC_S_IMM_VAL),
-/* 0010 1111 1010 */ TABDECL( OP_RSC_S_IMM_VAL),
-/* 0010 1111 1011 */ TABDECL( OP_RSC_S_IMM_VAL),
-/* 0010 1111 1100 */ TABDECL( OP_RSC_S_IMM_VAL),
-/* 0010 1111 1101 */ TABDECL( OP_RSC_S_IMM_VAL),
-/* 0010 1111 1110 */ TABDECL( OP_RSC_S_IMM_VAL),
-/* 0010 1111 1111 */ TABDECL( OP_RSC_S_IMM_VAL),
-/* 0011 0000 0000 */ TABDECL( OP_UND),
-/* 0011 0000 0001 */ TABDECL( OP_UND),
-/* 0011 0000 0010 */ TABDECL( OP_UND),
-/* 0011 0000 0011 */ TABDECL( OP_UND),
-/* 0011 0000 0100 */ TABDECL( OP_UND),
-/* 0011 0000 0101 */ TABDECL( OP_UND),
-/* 0011 0000 0110 */ TABDECL( OP_UND),
-/* 0011 0000 0111 */ TABDECL( OP_UND),
-/* 0011 0000 1000 */ TABDECL( OP_UND),
-/* 0011 0000 1001 */ TABDECL( OP_UND),
-/* 0011 0000 1010 */ TABDECL( OP_UND),
-/* 0011 0000 1011 */ TABDECL( OP_UND),
-/* 0011 0000 1100 */ TABDECL( OP_UND),
-/* 0011 0000 1101 */ TABDECL( OP_UND),
-/* 0011 0000 1110 */ TABDECL( OP_UND),
-/* 0011 0000 1111 */ TABDECL( OP_UND),
-/* 0011 0001 0000 */ TABDECL( OP_TST_IMM_VAL),
-/* 0011 0001 0001 */ TABDECL( OP_TST_IMM_VAL),
-/* 0011 0001 0010 */ TABDECL( OP_TST_IMM_VAL),
-/* 0011 0001 0011 */ TABDECL( OP_TST_IMM_VAL),
-/* 0011 0001 0100 */ TABDECL( OP_TST_IMM_VAL),
-/* 0011 0001 0101 */ TABDECL( OP_TST_IMM_VAL),
-/* 0011 0001 0110 */ TABDECL( OP_TST_IMM_VAL),
-/* 0011 0001 0111 */ TABDECL( OP_TST_IMM_VAL),
-/* 0011 0001 1000 */ TABDECL( OP_TST_IMM_VAL),
-/* 0011 0001 1001 */ TABDECL( OP_TST_IMM_VAL),
-/* 0011 0001 1010 */ TABDECL( OP_TST_IMM_VAL),
-/* 0011 0001 1011 */ TABDECL( OP_TST_IMM_VAL),
-/* 0011 0001 1100 */ TABDECL( OP_TST_IMM_VAL),
-/* 0011 0001 1101 */ TABDECL( OP_TST_IMM_VAL),
-/* 0011 0001 1110 */ TABDECL( OP_TST_IMM_VAL),
-/* 0011 0001 1111 */ TABDECL( OP_TST_IMM_VAL),
-/* 0011 0010 0000 */ TABDECL( OP_MSR_CPSR_IMM_VAL),
-/* 0011 0010 0001 */ TABDECL( OP_MSR_CPSR_IMM_VAL),
-/* 0011 0010 0010 */ TABDECL( OP_MSR_CPSR_IMM_VAL),
-/* 0011 0010 0011 */ TABDECL( OP_MSR_CPSR_IMM_VAL),
-/* 0011 0010 0100 */ TABDECL( OP_MSR_CPSR_IMM_VAL),
-/* 0011 0010 0101 */ TABDECL( OP_MSR_CPSR_IMM_VAL),
-/* 0011 0010 0110 */ TABDECL( OP_MSR_CPSR_IMM_VAL),
-/* 0011 0010 0111 */ TABDECL( OP_MSR_CPSR_IMM_VAL),
-/* 0011 0010 1000 */ TABDECL( OP_MSR_CPSR_IMM_VAL),
-/* 0011 0010 1001 */ TABDECL( OP_MSR_CPSR_IMM_VAL),
-/* 0011 0010 1010 */ TABDECL( OP_MSR_CPSR_IMM_VAL),
-/* 0011 0010 1011 */ TABDECL( OP_MSR_CPSR_IMM_VAL),
-/* 0011 0010 1100 */ TABDECL( OP_MSR_CPSR_IMM_VAL),
-/* 0011 0010 1101 */ TABDECL( OP_MSR_CPSR_IMM_VAL),
-/* 0011 0010 1110 */ TABDECL( OP_MSR_CPSR_IMM_VAL),
-/* 0011 0010 1111 */ TABDECL( OP_MSR_CPSR_IMM_VAL),
-/* 0011 0011 0000 */ TABDECL( OP_TEQ_IMM_VAL),
-/* 0011 0011 0001 */ TABDECL( OP_TEQ_IMM_VAL),
-/* 0011 0011 0010 */ TABDECL( OP_TEQ_IMM_VAL),
-/* 0011 0011 0011 */ TABDECL( OP_TEQ_IMM_VAL),
-/* 0011 0011 0100 */ TABDECL( OP_TEQ_IMM_VAL),
-/* 0011 0011 0101 */ TABDECL( OP_TEQ_IMM_VAL),
-/* 0011 0011 0110 */ TABDECL( OP_TEQ_IMM_VAL),
-/* 0011 0011 0111 */ TABDECL( OP_TEQ_IMM_VAL),
-/* 0011 0011 1000 */ TABDECL( OP_TEQ_IMM_VAL),
-/* 0011 0011 1001 */ TABDECL( OP_TEQ_IMM_VAL),
-/* 0011 0011 1010 */ TABDECL( OP_TEQ_IMM_VAL),
-/* 0011 0011 1011 */ TABDECL( OP_TEQ_IMM_VAL),
-/* 0011 0011 1100 */ TABDECL( OP_TEQ_IMM_VAL),
-/* 0011 0011 1101 */ TABDECL( OP_TEQ_IMM_VAL),
-/* 0011 0011 1110 */ TABDECL( OP_TEQ_IMM_VAL),
-/* 0011 0011 1111 */ TABDECL( OP_TEQ_IMM_VAL),
-/* 0011 0100 0000 */ TABDECL( OP_UND),
-/* 0011 0100 0001 */ TABDECL( OP_UND),
-/* 0011 0100 0010 */ TABDECL( OP_UND),
-/* 0011 0100 0011 */ TABDECL( OP_UND),
-/* 0011 0100 0100 */ TABDECL( OP_UND),
-/* 0011 0100 0101 */ TABDECL( OP_UND),
-/* 0011 0100 0110 */ TABDECL( OP_UND),
-/* 0011 0100 0111 */ TABDECL( OP_UND),
-/* 0011 0100 1000 */ TABDECL( OP_UND),
-/* 0011 0100 1001 */ TABDECL( OP_UND),
-/* 0011 0100 1010 */ TABDECL( OP_UND),
-/* 0011 0100 1011 */ TABDECL( OP_UND),
-/* 0011 0100 1100 */ TABDECL( OP_UND),
-/* 0011 0100 1101 */ TABDECL( OP_UND),
-/* 0011 0100 1110 */ TABDECL( OP_UND),
-/* 0011 0100 1111 */ TABDECL( OP_UND),
-/* 0011 0101 0000 */ TABDECL( OP_CMP_IMM_VAL),
-/* 0011 0101 0001 */ TABDECL( OP_CMP_IMM_VAL),
-/* 0011 0101 0010 */ TABDECL( OP_CMP_IMM_VAL),
-/* 0011 0101 0011 */ TABDECL( OP_CMP_IMM_VAL),
-/* 0011 0101 0100 */ TABDECL( OP_CMP_IMM_VAL),
-/* 0011 0101 0101 */ TABDECL( OP_CMP_IMM_VAL),
-/* 0011 0101 0110 */ TABDECL( OP_CMP_IMM_VAL),
-/* 0011 0101 0111 */ TABDECL( OP_CMP_IMM_VAL),
-/* 0011 0101 1000 */ TABDECL( OP_CMP_IMM_VAL),
-/* 0011 0101 1001 */ TABDECL( OP_CMP_IMM_VAL),
-/* 0011 0101 1010 */ TABDECL( OP_CMP_IMM_VAL),
-/* 0011 0101 1011 */ TABDECL( OP_CMP_IMM_VAL),
-/* 0011 0101 1100 */ TABDECL( OP_CMP_IMM_VAL),
-/* 0011 0101 1101 */ TABDECL( OP_CMP_IMM_VAL),
-/* 0011 0101 1110 */ TABDECL( OP_CMP_IMM_VAL),
-/* 0011 0101 1111 */ TABDECL( OP_CMP_IMM_VAL),
-/* 0011 0110 0000 */ TABDECL( OP_MSR_SPSR_IMM_VAL),
-/* 0011 0110 0001 */ TABDECL( OP_MSR_SPSR_IMM_VAL),
-/* 0011 0110 0010 */ TABDECL( OP_MSR_SPSR_IMM_VAL),
-/* 0011 0110 0011 */ TABDECL( OP_MSR_SPSR_IMM_VAL),
-/* 0011 0110 0100 */ TABDECL( OP_MSR_SPSR_IMM_VAL),
-/* 0011 0110 0101 */ TABDECL( OP_MSR_SPSR_IMM_VAL),
-/* 0011 0110 0110 */ TABDECL( OP_MSR_SPSR_IMM_VAL),
-/* 0011 0110 0111 */ TABDECL( OP_MSR_SPSR_IMM_VAL),
-/* 0011 0110 1000 */ TABDECL( OP_MSR_SPSR_IMM_VAL),
-/* 0011 0110 1001 */ TABDECL( OP_MSR_SPSR_IMM_VAL),
-/* 0011 0110 1010 */ TABDECL( OP_MSR_SPSR_IMM_VAL),
-/* 0011 0110 1011 */ TABDECL( OP_MSR_SPSR_IMM_VAL),
-/* 0011 0110 1100 */ TABDECL( OP_MSR_SPSR_IMM_VAL),
-/* 0011 0110 1101 */ TABDECL( OP_MSR_SPSR_IMM_VAL),
-/* 0011 0110 1110 */ TABDECL( OP_MSR_SPSR_IMM_VAL),
-/* 0011 0110 1111 */ TABDECL( OP_MSR_SPSR_IMM_VAL),
-/* 0011 0111 0000 */ TABDECL( OP_CMN_IMM_VAL),
-/* 0011 0111 0001 */ TABDECL( OP_CMN_IMM_VAL),
-/* 0011 0111 0010 */ TABDECL( OP_CMN_IMM_VAL),
-/* 0011 0111 0011 */ TABDECL( OP_CMN_IMM_VAL),
-/* 0011 0111 0100 */ TABDECL( OP_CMN_IMM_VAL),
-/* 0011 0111 0101 */ TABDECL( OP_CMN_IMM_VAL),
-/* 0011 0111 0110 */ TABDECL( OP_CMN_IMM_VAL),
-/* 0011 0111 0111 */ TABDECL( OP_CMN_IMM_VAL),
-/* 0011 0111 1000 */ TABDECL( OP_CMN_IMM_VAL),
-/* 0011 0111 1001 */ TABDECL( OP_CMN_IMM_VAL),
-/* 0011 0111 1010 */ TABDECL( OP_CMN_IMM_VAL),
-/* 0011 0111 1011 */ TABDECL( OP_CMN_IMM_VAL),
-/* 0011 0111 1100 */ TABDECL( OP_CMN_IMM_VAL),
-/* 0011 0111 1101 */ TABDECL( OP_CMN_IMM_VAL),
-/* 0011 0111 1110 */ TABDECL( OP_CMN_IMM_VAL),
-/* 0011 0111 1111 */ TABDECL( OP_CMN_IMM_VAL),
-/* 0011 1000 0000 */ TABDECL( OP_ORR_IMM_VAL),
-/* 0011 1000 0001 */ TABDECL( OP_ORR_IMM_VAL),
-/* 0011 1000 0010 */ TABDECL( OP_ORR_IMM_VAL),
-/* 0011 1000 0011 */ TABDECL( OP_ORR_IMM_VAL),
-/* 0011 1000 0100 */ TABDECL( OP_ORR_IMM_VAL),
-/* 0011 1000 0101 */ TABDECL( OP_ORR_IMM_VAL),
-/* 0011 1000 0110 */ TABDECL( OP_ORR_IMM_VAL),
-/* 0011 1000 0111 */ TABDECL( OP_ORR_IMM_VAL),
-/* 0011 1000 1000 */ TABDECL( OP_ORR_IMM_VAL),
-/* 0011 1000 1001 */ TABDECL( OP_ORR_IMM_VAL),
-/* 0011 1000 1010 */ TABDECL( OP_ORR_IMM_VAL),
-/* 0011 1000 1011 */ TABDECL( OP_ORR_IMM_VAL),
-/* 0011 1000 1100 */ TABDECL( OP_ORR_IMM_VAL),
-/* 0011 1000 1101 */ TABDECL( OP_ORR_IMM_VAL),
-/* 0011 1000 1110 */ TABDECL( OP_ORR_IMM_VAL),
-/* 0011 1000 1111 */ TABDECL( OP_ORR_IMM_VAL),
-/* 0011 1001 0000 */ TABDECL( OP_ORR_S_IMM_VAL),
-/* 0011 1001 0001 */ TABDECL( OP_ORR_S_IMM_VAL),
-/* 0011 1001 0010 */ TABDECL( OP_ORR_S_IMM_VAL),
-/* 0011 1001 0011 */ TABDECL( OP_ORR_S_IMM_VAL),
-/* 0011 1001 0100 */ TABDECL( OP_ORR_S_IMM_VAL),
-/* 0011 1001 0101 */ TABDECL( OP_ORR_S_IMM_VAL),
-/* 0011 1001 0110 */ TABDECL( OP_ORR_S_IMM_VAL),
-/* 0011 1001 0111 */ TABDECL( OP_ORR_S_IMM_VAL),
-/* 0011 1001 1000 */ TABDECL( OP_ORR_S_IMM_VAL),
-/* 0011 1001 1001 */ TABDECL( OP_ORR_S_IMM_VAL),
-/* 0011 1001 1010 */ TABDECL( OP_ORR_S_IMM_VAL),
-/* 0011 1001 1011 */ TABDECL( OP_ORR_S_IMM_VAL),
-/* 0011 1001 1100 */ TABDECL( OP_ORR_S_IMM_VAL),
-/* 0011 1001 1101 */ TABDECL( OP_ORR_S_IMM_VAL),
-/* 0011 1001 1110 */ TABDECL( OP_ORR_S_IMM_VAL),
-/* 0011 1001 1111 */ TABDECL( OP_ORR_S_IMM_VAL),
-/* 0011 1010 0000 */ TABDECL( OP_MOV_IMM_VAL),
-/* 0011 1010 0001 */ TABDECL( OP_MOV_IMM_VAL),
-/* 0011 1010 0010 */ TABDECL( OP_MOV_IMM_VAL),
-/* 0011 1010 0011 */ TABDECL( OP_MOV_IMM_VAL),
-/* 0011 1010 0100 */ TABDECL( OP_MOV_IMM_VAL),
-/* 0011 1010 0101 */ TABDECL( OP_MOV_IMM_VAL),
-/* 0011 1010 0110 */ TABDECL( OP_MOV_IMM_VAL),
-/* 0011 1010 0111 */ TABDECL( OP_MOV_IMM_VAL),
-/* 0011 1010 1000 */ TABDECL( OP_MOV_IMM_VAL),
-/* 0011 1010 1001 */ TABDECL( OP_MOV_IMM_VAL),
-/* 0011 1010 1010 */ TABDECL( OP_MOV_IMM_VAL),
-/* 0011 1010 1011 */ TABDECL( OP_MOV_IMM_VAL),
-/* 0011 1010 1100 */ TABDECL( OP_MOV_IMM_VAL),
-/* 0011 1010 1101 */ TABDECL( OP_MOV_IMM_VAL),
-/* 0011 1010 1110 */ TABDECL( OP_MOV_IMM_VAL),
-/* 0011 1010 1111 */ TABDECL( OP_MOV_IMM_VAL),
-/* 0011 1011 0000 */ TABDECL( OP_MOV_S_IMM_VAL),
-/* 0011 1011 0001 */ TABDECL( OP_MOV_S_IMM_VAL),
-/* 0011 1011 0010 */ TABDECL( OP_MOV_S_IMM_VAL),
-/* 0011 1011 0011 */ TABDECL( OP_MOV_S_IMM_VAL),
-/* 0011 1011 0100 */ TABDECL( OP_MOV_S_IMM_VAL),
-/* 0011 1011 0101 */ TABDECL( OP_MOV_S_IMM_VAL),
-/* 0011 1011 0110 */ TABDECL( OP_MOV_S_IMM_VAL),
-/* 0011 1011 0111 */ TABDECL( OP_MOV_S_IMM_VAL),
-/* 0011 1011 1000 */ TABDECL( OP_MOV_S_IMM_VAL),
-/* 0011 1011 1001 */ TABDECL( OP_MOV_S_IMM_VAL),
-/* 0011 1011 1010 */ TABDECL( OP_MOV_S_IMM_VAL),
-/* 0011 1011 1011 */ TABDECL( OP_MOV_S_IMM_VAL),
-/* 0011 1011 1100 */ TABDECL( OP_MOV_S_IMM_VAL),
-/* 0011 1011 1101 */ TABDECL( OP_MOV_S_IMM_VAL),
-/* 0011 1011 1110 */ TABDECL( OP_MOV_S_IMM_VAL),
-/* 0011 1011 1111 */ TABDECL( OP_MOV_S_IMM_VAL),
-/* 0011 1100 0000 */ TABDECL( OP_BIC_IMM_VAL),
-/* 0011 1100 0001 */ TABDECL( OP_BIC_IMM_VAL),
-/* 0011 1100 0010 */ TABDECL( OP_BIC_IMM_VAL),
-/* 0011 1100 0011 */ TABDECL( OP_BIC_IMM_VAL),
-/* 0011 1100 0100 */ TABDECL( OP_BIC_IMM_VAL),
-/* 0011 1100 0101 */ TABDECL( OP_BIC_IMM_VAL),
-/* 0011 1100 0110 */ TABDECL( OP_BIC_IMM_VAL),
-/* 0011 1100 0111 */ TABDECL( OP_BIC_IMM_VAL),
-/* 0011 1100 1000 */ TABDECL( OP_BIC_IMM_VAL),
-/* 0011 1100 1001 */ TABDECL( OP_BIC_IMM_VAL),
-/* 0011 1100 1010 */ TABDECL( OP_BIC_IMM_VAL),
-/* 0011 1100 1011 */ TABDECL( OP_BIC_IMM_VAL),
-/* 0011 1100 1100 */ TABDECL( OP_BIC_IMM_VAL),
-/* 0011 1100 1101 */ TABDECL( OP_BIC_IMM_VAL),
-/* 0011 1100 1110 */ TABDECL( OP_BIC_IMM_VAL),
-/* 0011 1100 1111 */ TABDECL( OP_BIC_IMM_VAL),
-/* 0011 1101 0000 */ TABDECL( OP_BIC_S_IMM_VAL),
-/* 0011 1101 0001 */ TABDECL( OP_BIC_S_IMM_VAL),
-/* 0011 1101 0010 */ TABDECL( OP_BIC_S_IMM_VAL),
-/* 0011 1101 0011 */ TABDECL( OP_BIC_S_IMM_VAL),
-/* 0011 1101 0100 */ TABDECL( OP_BIC_S_IMM_VAL),
-/* 0011 1101 0101 */ TABDECL( OP_BIC_S_IMM_VAL),
-/* 0011 1101 0110 */ TABDECL( OP_BIC_S_IMM_VAL),
-/* 0011 1101 0111 */ TABDECL( OP_BIC_S_IMM_VAL),
-/* 0011 1101 1000 */ TABDECL( OP_BIC_S_IMM_VAL),
-/* 0011 1101 1001 */ TABDECL( OP_BIC_S_IMM_VAL),
-/* 0011 1101 1010 */ TABDECL( OP_BIC_S_IMM_VAL),
-/* 0011 1101 1011 */ TABDECL( OP_BIC_S_IMM_VAL),
-/* 0011 1101 1100 */ TABDECL( OP_BIC_S_IMM_VAL),
-/* 0011 1101 1101 */ TABDECL( OP_BIC_S_IMM_VAL),
-/* 0011 1101 1110 */ TABDECL( OP_BIC_S_IMM_VAL),
-/* 0011 1101 1111 */ TABDECL( OP_BIC_S_IMM_VAL),
-/* 0011 1110 0000 */ TABDECL( OP_MVN_IMM_VAL),
-/* 0011 1110 0001 */ TABDECL( OP_MVN_IMM_VAL),
-/* 0011 1110 0010 */ TABDECL( OP_MVN_IMM_VAL),
-/* 0011 1110 0011 */ TABDECL( OP_MVN_IMM_VAL),
-/* 0011 1110 0100 */ TABDECL( OP_MVN_IMM_VAL),
-/* 0011 1110 0101 */ TABDECL( OP_MVN_IMM_VAL),
-/* 0011 1110 0110 */ TABDECL( OP_MVN_IMM_VAL),
-/* 0011 1110 0111 */ TABDECL( OP_MVN_IMM_VAL),
-/* 0011 1110 1000 */ TABDECL( OP_MVN_IMM_VAL),
-/* 0011 1110 1001 */ TABDECL( OP_MVN_IMM_VAL),
-/* 0011 1110 1010 */ TABDECL( OP_MVN_IMM_VAL),
-/* 0011 1110 1011 */ TABDECL( OP_MVN_IMM_VAL),
-/* 0011 1110 1100 */ TABDECL( OP_MVN_IMM_VAL),
-/* 0011 1110 1101 */ TABDECL( OP_MVN_IMM_VAL),
-/* 0011 1110 1110 */ TABDECL( OP_MVN_IMM_VAL),
-/* 0011 1110 1111 */ TABDECL( OP_MVN_IMM_VAL),
-/* 0011 1111 0000 */ TABDECL( OP_MVN_S_IMM_VAL),
-/* 0011 1111 0001 */ TABDECL( OP_MVN_S_IMM_VAL),
-/* 0011 1111 0010 */ TABDECL( OP_MVN_S_IMM_VAL),
-/* 0011 1111 0011 */ TABDECL( OP_MVN_S_IMM_VAL),
-/* 0011 1111 0100 */ TABDECL( OP_MVN_S_IMM_VAL),
-/* 0011 1111 0101 */ TABDECL( OP_MVN_S_IMM_VAL),
-/* 0011 1111 0110 */ TABDECL( OP_MVN_S_IMM_VAL),
-/* 0011 1111 0111 */ TABDECL( OP_MVN_S_IMM_VAL),
-/* 0011 1111 1000 */ TABDECL( OP_MVN_S_IMM_VAL),
-/* 0011 1111 1001 */ TABDECL( OP_MVN_S_IMM_VAL),
-/* 0011 1111 1010 */ TABDECL( OP_MVN_S_IMM_VAL),
-/* 0011 1111 1011 */ TABDECL( OP_MVN_S_IMM_VAL),
-/* 0011 1111 1100 */ TABDECL( OP_MVN_S_IMM_VAL),
-/* 0011 1111 1101 */ TABDECL( OP_MVN_S_IMM_VAL),
-/* 0011 1111 1110 */ TABDECL( OP_MVN_S_IMM_VAL),
-/* 0011 1111 1111 */ TABDECL( OP_MVN_S_IMM_VAL),
-/* 0100 0000 0000 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0000 0001 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0000 0010 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0000 0011 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0000 0100 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0000 0101 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0000 0110 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0000 0111 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0000 1000 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0000 1001 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0000 1010 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0000 1011 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0000 1100 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0000 1101 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0000 1110 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0000 1111 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0001 0000 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0001 0001 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0001 0010 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0001 0011 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0001 0100 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0001 0101 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0001 0110 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0001 0111 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0001 1000 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0001 1001 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0001 1010 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0001 1011 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0001 1100 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0001 1101 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0001 1110 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0001 1111 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0010 0000 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0010 0001 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0010 0010 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0010 0011 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0010 0100 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0010 0101 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0010 0110 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0010 0111 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0010 1000 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0010 1001 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0010 1010 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0010 1011 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0010 1100 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0010 1101 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0010 1110 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0010 1111 */ TABDECL( OP_STR_M_IMM_OFF_POSTIND),
-/* 0100 0011 0000 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0011 0001 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0011 0010 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0011 0011 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0011 0100 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0011 0101 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0011 0110 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0011 0111 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0011 1000 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0011 1001 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0011 1010 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0011 1011 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0011 1100 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0011 1101 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0011 1110 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0011 1111 */ TABDECL( OP_LDR_M_IMM_OFF_POSTIND),
-/* 0100 0100 0000 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0100 0001 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0100 0010 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0100 0011 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0100 0100 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0100 0101 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0100 0110 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0100 0111 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0100 1000 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0100 1001 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0100 1010 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0100 1011 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0100 1100 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0100 1101 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0100 1110 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0100 1111 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0101 0000 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0101 0001 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0101 0010 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0101 0011 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0101 0100 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0101 0101 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0101 0110 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0101 0111 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0101 1000 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0101 1001 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0101 1010 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0101 1011 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0101 1100 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0101 1101 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0101 1110 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0101 1111 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0110 0000 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0110 0001 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0110 0010 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0110 0011 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0110 0100 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0110 0101 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0110 0110 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0110 0111 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0110 1000 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0110 1001 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0110 1010 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0110 1011 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0110 1100 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0110 1101 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0110 1110 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0110 1111 */ TABDECL( OP_STRB_M_IMM_OFF_POSTIND),
-/* 0100 0111 0000 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0111 0001 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0111 0010 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0111 0011 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0111 0100 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0111 0101 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0111 0110 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0111 0111 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0111 1000 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0111 1001 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0111 1010 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0111 1011 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0111 1100 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0111 1101 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0111 1110 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 0111 1111 */ TABDECL( OP_LDRB_M_IMM_OFF_POSTIND),
-/* 0100 1000 0000 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1000 0001 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1000 0010 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1000 0011 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1000 0100 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1000 0101 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1000 0110 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1000 0111 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1000 1000 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1000 1001 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1000 1010 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1000 1011 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1000 1100 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1000 1101 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1000 1110 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1000 1111 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1001 0000 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1001 0001 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1001 0010 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1001 0011 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1001 0100 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1001 0101 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1001 0110 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1001 0111 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1001 1000 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1001 1001 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1001 1010 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1001 1011 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1001 1100 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1001 1101 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1001 1110 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1001 1111 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1010 0000 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1010 0001 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1010 0010 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1010 0011 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1010 0100 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1010 0101 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1010 0110 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1010 0111 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1010 1000 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1010 1001 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1010 1010 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1010 1011 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1010 1100 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1010 1101 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1010 1110 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1010 1111 */ TABDECL( OP_STR_P_IMM_OFF_POSTIND),
-/* 0100 1011 0000 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1011 0001 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1011 0010 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1011 0011 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1011 0100 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1011 0101 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1011 0110 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1011 0111 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1011 1000 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1011 1001 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1011 1010 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1011 1011 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1011 1100 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1011 1101 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1011 1110 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1011 1111 */ TABDECL( OP_LDR_P_IMM_OFF_POSTIND),
-/* 0100 1100 0000 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1100 0001 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1100 0010 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1100 0011 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1100 0100 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1100 0101 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1100 0110 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1100 0111 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1100 1000 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1100 1001 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1100 1010 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1100 1011 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1100 1100 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1100 1101 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1100 1110 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1100 1111 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1101 0000 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1101 0001 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1101 0010 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1101 0011 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1101 0100 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1101 0101 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1101 0110 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1101 0111 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1101 1000 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1101 1001 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1101 1010 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1101 1011 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1101 1100 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1101 1101 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1101 1110 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1101 1111 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1110 0000 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1110 0001 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1110 0010 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1110 0011 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1110 0100 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1110 0101 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1110 0110 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1110 0111 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1110 1000 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1110 1001 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1110 1010 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1110 1011 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1110 1100 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1110 1101 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1110 1110 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1110 1111 */ TABDECL( OP_STRB_P_IMM_OFF_POSTIND),
-/* 0100 1111 0000 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1111 0001 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1111 0010 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1111 0011 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1111 0100 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1111 0101 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1111 0110 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1111 0111 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1111 1000 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1111 1001 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1111 1010 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1111 1011 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1111 1100 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1111 1101 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1111 1110 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0100 1111 1111 */ TABDECL( OP_LDRB_P_IMM_OFF_POSTIND),
-/* 0101 0000 0000 */ TABDECL( OP_STR_M_IMM_OFF),
-/* 0101 0000 0001 */ TABDECL( OP_STR_M_IMM_OFF),
-/* 0101 0000 0010 */ TABDECL( OP_STR_M_IMM_OFF),
-/* 0101 0000 0011 */ TABDECL( OP_STR_M_IMM_OFF),
-/* 0101 0000 0100 */ TABDECL( OP_STR_M_IMM_OFF),
-/* 0101 0000 0101 */ TABDECL( OP_STR_M_IMM_OFF),
-/* 0101 0000 0110 */ TABDECL( OP_STR_M_IMM_OFF),
-/* 0101 0000 0111 */ TABDECL( OP_STR_M_IMM_OFF),
-/* 0101 0000 1000 */ TABDECL( OP_STR_M_IMM_OFF),
-/* 0101 0000 1001 */ TABDECL( OP_STR_M_IMM_OFF),
-/* 0101 0000 1010 */ TABDECL( OP_STR_M_IMM_OFF),
-/* 0101 0000 1011 */ TABDECL( OP_STR_M_IMM_OFF),
-/* 0101 0000 1100 */ TABDECL( OP_STR_M_IMM_OFF),
-/* 0101 0000 1101 */ TABDECL( OP_STR_M_IMM_OFF),
-/* 0101 0000 1110 */ TABDECL( OP_STR_M_IMM_OFF),
-/* 0101 0000 1111 */ TABDECL( OP_STR_M_IMM_OFF),
-/* 0101 0001 0000 */ TABDECL( OP_LDR_M_IMM_OFF),
-/* 0101 0001 0001 */ TABDECL( OP_LDR_M_IMM_OFF),
-/* 0101 0001 0010 */ TABDECL( OP_LDR_M_IMM_OFF),
-/* 0101 0001 0011 */ TABDECL( OP_LDR_M_IMM_OFF),
-/* 0101 0001 0100 */ TABDECL( OP_LDR_M_IMM_OFF),
-/* 0101 0001 0101 */ TABDECL( OP_LDR_M_IMM_OFF),
-/* 0101 0001 0110 */ TABDECL( OP_LDR_M_IMM_OFF),
-/* 0101 0001 0111 */ TABDECL( OP_LDR_M_IMM_OFF),
-/* 0101 0001 1000 */ TABDECL( OP_LDR_M_IMM_OFF),
-/* 0101 0001 1001 */ TABDECL( OP_LDR_M_IMM_OFF),
-/* 0101 0001 1010 */ TABDECL( OP_LDR_M_IMM_OFF),
-/* 0101 0001 1011 */ TABDECL( OP_LDR_M_IMM_OFF),
-/* 0101 0001 1100 */ TABDECL( OP_LDR_M_IMM_OFF),
-/* 0101 0001 1101 */ TABDECL( OP_LDR_M_IMM_OFF),
-/* 0101 0001 1110 */ TABDECL( OP_LDR_M_IMM_OFF),
-/* 0101 0001 1111 */ TABDECL( OP_LDR_M_IMM_OFF),
-/* 0101 0010 0000 */ TABDECL( OP_STR_M_IMM_OFF_PREIND),
-/* 0101 0010 0001 */ TABDECL( OP_STR_M_IMM_OFF_PREIND),
-/* 0101 0010 0010 */ TABDECL( OP_STR_M_IMM_OFF_PREIND),
-/* 0101 0010 0011 */ TABDECL( OP_STR_M_IMM_OFF_PREIND),
-/* 0101 0010 0100 */ TABDECL( OP_STR_M_IMM_OFF_PREIND),
-/* 0101 0010 0101 */ TABDECL( OP_STR_M_IMM_OFF_PREIND),
-/* 0101 0010 0110 */ TABDECL( OP_STR_M_IMM_OFF_PREIND),
-/* 0101 0010 0111 */ TABDECL( OP_STR_M_IMM_OFF_PREIND),
-/* 0101 0010 1000 */ TABDECL( OP_STR_M_IMM_OFF_PREIND),
-/* 0101 0010 1001 */ TABDECL( OP_STR_M_IMM_OFF_PREIND),
-/* 0101 0010 1010 */ TABDECL( OP_STR_M_IMM_OFF_PREIND),
-/* 0101 0010 1011 */ TABDECL( OP_STR_M_IMM_OFF_PREIND),
-/* 0101 0010 1100 */ TABDECL( OP_STR_M_IMM_OFF_PREIND),
-/* 0101 0010 1101 */ TABDECL( OP_STR_M_IMM_OFF_PREIND),
-/* 0101 0010 1110 */ TABDECL( OP_STR_M_IMM_OFF_PREIND),
-/* 0101 0010 1111 */ TABDECL( OP_STR_M_IMM_OFF_PREIND),
-/* 0101 0011 0000 */ TABDECL( OP_LDR_M_IMM_OFF_PREIND),
-/* 0101 0011 0001 */ TABDECL( OP_LDR_M_IMM_OFF_PREIND),
-/* 0101 0011 0010 */ TABDECL( OP_LDR_M_IMM_OFF_PREIND),
-/* 0101 0011 0011 */ TABDECL( OP_LDR_M_IMM_OFF_PREIND),
-/* 0101 0011 0100 */ TABDECL( OP_LDR_M_IMM_OFF_PREIND),
-/* 0101 0011 0101 */ TABDECL( OP_LDR_M_IMM_OFF_PREIND),
-/* 0101 0011 0110 */ TABDECL( OP_LDR_M_IMM_OFF_PREIND),
-/* 0101 0011 0111 */ TABDECL( OP_LDR_M_IMM_OFF_PREIND),
-/* 0101 0011 1000 */ TABDECL( OP_LDR_M_IMM_OFF_PREIND),
-/* 0101 0011 1001 */ TABDECL( OP_LDR_M_IMM_OFF_PREIND),
-/* 0101 0011 1010 */ TABDECL( OP_LDR_M_IMM_OFF_PREIND),
-/* 0101 0011 1011 */ TABDECL( OP_LDR_M_IMM_OFF_PREIND),
-/* 0101 0011 1100 */ TABDECL( OP_LDR_M_IMM_OFF_PREIND),
-/* 0101 0011 1101 */ TABDECL( OP_LDR_M_IMM_OFF_PREIND),
-/* 0101 0011 1110 */ TABDECL( OP_LDR_M_IMM_OFF_PREIND),
-/* 0101 0011 1111 */ TABDECL( OP_LDR_M_IMM_OFF_PREIND),
-/* 0101 0100 0000 */ TABDECL( OP_STRB_M_IMM_OFF),
-/* 0101 0100 0001 */ TABDECL( OP_STRB_M_IMM_OFF),
-/* 0101 0100 0010 */ TABDECL( OP_STRB_M_IMM_OFF),
-/* 0101 0100 0011 */ TABDECL( OP_STRB_M_IMM_OFF),
-/* 0101 0100 0100 */ TABDECL( OP_STRB_M_IMM_OFF),
-/* 0101 0100 0101 */ TABDECL( OP_STRB_M_IMM_OFF),
-/* 0101 0100 0110 */ TABDECL( OP_STRB_M_IMM_OFF),
-/* 0101 0100 0111 */ TABDECL( OP_STRB_M_IMM_OFF),
-/* 0101 0100 1000 */ TABDECL( OP_STRB_M_IMM_OFF),
-/* 0101 0100 1001 */ TABDECL( OP_STRB_M_IMM_OFF),
-/* 0101 0100 1010 */ TABDECL( OP_STRB_M_IMM_OFF),
-/* 0101 0100 1011 */ TABDECL( OP_STRB_M_IMM_OFF),
-/* 0101 0100 1100 */ TABDECL( OP_STRB_M_IMM_OFF),
-/* 0101 0100 1101 */ TABDECL( OP_STRB_M_IMM_OFF),
-/* 0101 0100 1110 */ TABDECL( OP_STRB_M_IMM_OFF),
-/* 0101 0100 1111 */ TABDECL( OP_STRB_M_IMM_OFF),
-/* 0101 0101 0000 */ TABDECL( OP_LDRB_M_IMM_OFF),
-/* 0101 0101 0001 */ TABDECL( OP_LDRB_M_IMM_OFF),
-/* 0101 0101 0010 */ TABDECL( OP_LDRB_M_IMM_OFF),
-/* 0101 0101 0011 */ TABDECL( OP_LDRB_M_IMM_OFF),
-/* 0101 0101 0100 */ TABDECL( OP_LDRB_M_IMM_OFF),
-/* 0101 0101 0101 */ TABDECL( OP_LDRB_M_IMM_OFF),
-/* 0101 0101 0110 */ TABDECL( OP_LDRB_M_IMM_OFF),
-/* 0101 0101 0111 */ TABDECL( OP_LDRB_M_IMM_OFF),
-/* 0101 0101 1000 */ TABDECL( OP_LDRB_M_IMM_OFF),
-/* 0101 0101 1001 */ TABDECL( OP_LDRB_M_IMM_OFF),
-/* 0101 0101 1010 */ TABDECL( OP_LDRB_M_IMM_OFF),
-/* 0101 0101 1011 */ TABDECL( OP_LDRB_M_IMM_OFF),
-/* 0101 0101 1100 */ TABDECL( OP_LDRB_M_IMM_OFF),
-/* 0101 0101 1101 */ TABDECL( OP_LDRB_M_IMM_OFF),
-/* 0101 0101 1110 */ TABDECL( OP_LDRB_M_IMM_OFF),
-/* 0101 0101 1111 */ TABDECL( OP_LDRB_M_IMM_OFF),
-/* 0101 0110 0000 */ TABDECL( OP_STRB_M_IMM_OFF_PREIND),
-/* 0101 0110 0001 */ TABDECL( OP_STRB_M_IMM_OFF_PREIND),
-/* 0101 0110 0010 */ TABDECL( OP_STRB_M_IMM_OFF_PREIND),
-/* 0101 0110 0011 */ TABDECL( OP_STRB_M_IMM_OFF_PREIND),
-/* 0101 0110 0100 */ TABDECL( OP_STRB_M_IMM_OFF_PREIND),
-/* 0101 0110 0101 */ TABDECL( OP_STRB_M_IMM_OFF_PREIND),
-/* 0101 0110 0110 */ TABDECL( OP_STRB_M_IMM_OFF_PREIND),
-/* 0101 0110 0111 */ TABDECL( OP_STRB_M_IMM_OFF_PREIND),
-/* 0101 0110 1000 */ TABDECL( OP_STRB_M_IMM_OFF_PREIND),
-/* 0101 0110 1001 */ TABDECL( OP_STRB_M_IMM_OFF_PREIND),
-/* 0101 0110 1010 */ TABDECL( OP_STRB_M_IMM_OFF_PREIND),
-/* 0101 0110 1011 */ TABDECL( OP_STRB_M_IMM_OFF_PREIND),
-/* 0101 0110 1100 */ TABDECL( OP_STRB_M_IMM_OFF_PREIND),
-/* 0101 0110 1101 */ TABDECL( OP_STRB_M_IMM_OFF_PREIND),
-/* 0101 0110 1110 */ TABDECL( OP_STRB_M_IMM_OFF_PREIND),
-/* 0101 0110 1111 */ TABDECL( OP_STRB_M_IMM_OFF_PREIND),
-/* 0101 0111 0000 */ TABDECL( OP_LDRB_M_IMM_OFF_PREIND),
-/* 0101 0111 0001 */ TABDECL( OP_LDRB_M_IMM_OFF_PREIND),
-/* 0101 0111 0010 */ TABDECL( OP_LDRB_M_IMM_OFF_PREIND),
-/* 0101 0111 0011 */ TABDECL( OP_LDRB_M_IMM_OFF_PREIND),
-/* 0101 0111 0100 */ TABDECL( OP_LDRB_M_IMM_OFF_PREIND),
-/* 0101 0111 0101 */ TABDECL( OP_LDRB_M_IMM_OFF_PREIND),
-/* 0101 0111 0110 */ TABDECL( OP_LDRB_M_IMM_OFF_PREIND),
-/* 0101 0111 0111 */ TABDECL( OP_LDRB_M_IMM_OFF_PREIND),
-/* 0101 0111 1000 */ TABDECL( OP_LDRB_M_IMM_OFF_PREIND),
-/* 0101 0111 1001 */ TABDECL( OP_LDRB_M_IMM_OFF_PREIND),
-/* 0101 0111 1010 */ TABDECL( OP_LDRB_M_IMM_OFF_PREIND),
-/* 0101 0111 1011 */ TABDECL( OP_LDRB_M_IMM_OFF_PREIND),
-/* 0101 0111 1100 */ TABDECL( OP_LDRB_M_IMM_OFF_PREIND),
-/* 0101 0111 1101 */ TABDECL( OP_LDRB_M_IMM_OFF_PREIND),
-/* 0101 0111 1110 */ TABDECL( OP_LDRB_M_IMM_OFF_PREIND),
-/* 0101 0111 1111 */ TABDECL( OP_LDRB_M_IMM_OFF_PREIND),
-/* 0101 1000 0000 */ TABDECL( OP_STR_P_IMM_OFF),
-/* 0101 1000 0001 */ TABDECL( OP_STR_P_IMM_OFF),
-/* 0101 1000 0010 */ TABDECL( OP_STR_P_IMM_OFF),
-/* 0101 1000 0011 */ TABDECL( OP_STR_P_IMM_OFF),
-/* 0101 1000 0100 */ TABDECL( OP_STR_P_IMM_OFF),
-/* 0101 1000 0101 */ TABDECL( OP_STR_P_IMM_OFF),
-/* 0101 1000 0110 */ TABDECL( OP_STR_P_IMM_OFF),
-/* 0101 1000 0111 */ TABDECL( OP_STR_P_IMM_OFF),
-/* 0101 1000 1000 */ TABDECL( OP_STR_P_IMM_OFF),
-/* 0101 1000 1001 */ TABDECL( OP_STR_P_IMM_OFF),
-/* 0101 1000 1010 */ TABDECL( OP_STR_P_IMM_OFF),
-/* 0101 1000 1011 */ TABDECL( OP_STR_P_IMM_OFF),
-/* 0101 1000 1100 */ TABDECL( OP_STR_P_IMM_OFF),
-/* 0101 1000 1101 */ TABDECL( OP_STR_P_IMM_OFF),
-/* 0101 1000 1110 */ TABDECL( OP_STR_P_IMM_OFF),
-/* 0101 1000 1111 */ TABDECL( OP_STR_P_IMM_OFF),
-/* 0101 1001 0000 */ TABDECL( OP_LDR_P_IMM_OFF),
-/* 0101 1001 0001 */ TABDECL( OP_LDR_P_IMM_OFF),
-/* 0101 1001 0010 */ TABDECL( OP_LDR_P_IMM_OFF),
-/* 0101 1001 0011 */ TABDECL( OP_LDR_P_IMM_OFF),
-/* 0101 1001 0100 */ TABDECL( OP_LDR_P_IMM_OFF),
-/* 0101 1001 0101 */ TABDECL( OP_LDR_P_IMM_OFF),
-/* 0101 1001 0110 */ TABDECL( OP_LDR_P_IMM_OFF),
-/* 0101 1001 0111 */ TABDECL( OP_LDR_P_IMM_OFF),
-/* 0101 1001 1000 */ TABDECL( OP_LDR_P_IMM_OFF),
-/* 0101 1001 1001 */ TABDECL( OP_LDR_P_IMM_OFF),
-/* 0101 1001 1010 */ TABDECL( OP_LDR_P_IMM_OFF),
-/* 0101 1001 1011 */ TABDECL( OP_LDR_P_IMM_OFF),
-/* 0101 1001 1100 */ TABDECL( OP_LDR_P_IMM_OFF),
-/* 0101 1001 1101 */ TABDECL( OP_LDR_P_IMM_OFF),
-/* 0101 1001 1110 */ TABDECL( OP_LDR_P_IMM_OFF),
-/* 0101 1001 1111 */ TABDECL( OP_LDR_P_IMM_OFF),
-/* 0101 1010 0000 */ TABDECL( OP_STR_P_IMM_OFF_PREIND),
-/* 0101 1010 0001 */ TABDECL( OP_STR_P_IMM_OFF_PREIND),
-/* 0101 1010 0010 */ TABDECL( OP_STR_P_IMM_OFF_PREIND),
-/* 0101 1010 0011 */ TABDECL( OP_STR_P_IMM_OFF_PREIND),
-/* 0101 1010 0100 */ TABDECL( OP_STR_P_IMM_OFF_PREIND),
-/* 0101 1010 0101 */ TABDECL( OP_STR_P_IMM_OFF_PREIND),
-/* 0101 1010 0110 */ TABDECL( OP_STR_P_IMM_OFF_PREIND),
-/* 0101 1010 0111 */ TABDECL( OP_STR_P_IMM_OFF_PREIND),
-/* 0101 1010 1000 */ TABDECL( OP_STR_P_IMM_OFF_PREIND),
-/* 0101 1010 1001 */ TABDECL( OP_STR_P_IMM_OFF_PREIND),
-/* 0101 1010 1010 */ TABDECL( OP_STR_P_IMM_OFF_PREIND),
-/* 0101 1010 1011 */ TABDECL( OP_STR_P_IMM_OFF_PREIND),
-/* 0101 1010 1100 */ TABDECL( OP_STR_P_IMM_OFF_PREIND),
-/* 0101 1010 1101 */ TABDECL( OP_STR_P_IMM_OFF_PREIND),
-/* 0101 1010 1110 */ TABDECL( OP_STR_P_IMM_OFF_PREIND),
-/* 0101 1010 1111 */ TABDECL( OP_STR_P_IMM_OFF_PREIND),
-/* 0101 1011 0000 */ TABDECL( OP_LDR_P_IMM_OFF_PREIND),
-/* 0101 1011 0001 */ TABDECL( OP_LDR_P_IMM_OFF_PREIND),
-/* 0101 1011 0010 */ TABDECL( OP_LDR_P_IMM_OFF_PREIND),
-/* 0101 1011 0011 */ TABDECL( OP_LDR_P_IMM_OFF_PREIND),
-/* 0101 1011 0100 */ TABDECL( OP_LDR_P_IMM_OFF_PREIND),
-/* 0101 1011 0101 */ TABDECL( OP_LDR_P_IMM_OFF_PREIND),
-/* 0101 1011 0110 */ TABDECL( OP_LDR_P_IMM_OFF_PREIND),
-/* 0101 1011 0111 */ TABDECL( OP_LDR_P_IMM_OFF_PREIND),
-/* 0101 1011 1000 */ TABDECL( OP_LDR_P_IMM_OFF_PREIND),
-/* 0101 1011 1001 */ TABDECL( OP_LDR_P_IMM_OFF_PREIND),
-/* 0101 1011 1010 */ TABDECL( OP_LDR_P_IMM_OFF_PREIND),
-/* 0101 1011 1011 */ TABDECL( OP_LDR_P_IMM_OFF_PREIND),
-/* 0101 1011 1100 */ TABDECL( OP_LDR_P_IMM_OFF_PREIND),
-/* 0101 1011 1101 */ TABDECL( OP_LDR_P_IMM_OFF_PREIND),
-/* 0101 1011 1110 */ TABDECL( OP_LDR_P_IMM_OFF_PREIND),
-/* 0101 1011 1111 */ TABDECL( OP_LDR_P_IMM_OFF_PREIND),
-/* 0101 1100 0000 */ TABDECL( OP_STRB_P_IMM_OFF),
-/* 0101 1100 0001 */ TABDECL( OP_STRB_P_IMM_OFF),
-/* 0101 1100 0010 */ TABDECL( OP_STRB_P_IMM_OFF),
-/* 0101 1100 0011 */ TABDECL( OP_STRB_P_IMM_OFF),
-/* 0101 1100 0100 */ TABDECL( OP_STRB_P_IMM_OFF),
-/* 0101 1100 0101 */ TABDECL( OP_STRB_P_IMM_OFF),
-/* 0101 1100 0110 */ TABDECL( OP_STRB_P_IMM_OFF),
-/* 0101 1100 0111 */ TABDECL( OP_STRB_P_IMM_OFF),
-/* 0101 1100 1000 */ TABDECL( OP_STRB_P_IMM_OFF),
-/* 0101 1100 1001 */ TABDECL( OP_STRB_P_IMM_OFF),
-/* 0101 1100 1010 */ TABDECL( OP_STRB_P_IMM_OFF),
-/* 0101 1100 1011 */ TABDECL( OP_STRB_P_IMM_OFF),
-/* 0101 1100 1100 */ TABDECL( OP_STRB_P_IMM_OFF),
-/* 0101 1100 1101 */ TABDECL( OP_STRB_P_IMM_OFF),
-/* 0101 1100 1110 */ TABDECL( OP_STRB_P_IMM_OFF),
-/* 0101 1100 1111 */ TABDECL( OP_STRB_P_IMM_OFF),
-/* 0101 1101 0000 */ TABDECL( OP_LDRB_P_IMM_OFF),
-/* 0101 1101 0001 */ TABDECL( OP_LDRB_P_IMM_OFF),
-/* 0101 1101 0010 */ TABDECL( OP_LDRB_P_IMM_OFF),
-/* 0101 1101 0011 */ TABDECL( OP_LDRB_P_IMM_OFF),
-/* 0101 1101 0100 */ TABDECL( OP_LDRB_P_IMM_OFF),
-/* 0101 1101 0101 */ TABDECL( OP_LDRB_P_IMM_OFF),
-/* 0101 1101 0110 */ TABDECL( OP_LDRB_P_IMM_OFF),
-/* 0101 1101 0111 */ TABDECL( OP_LDRB_P_IMM_OFF),
-/* 0101 1101 1000 */ TABDECL( OP_LDRB_P_IMM_OFF),
-/* 0101 1101 1001 */ TABDECL( OP_LDRB_P_IMM_OFF),
-/* 0101 1101 1010 */ TABDECL( OP_LDRB_P_IMM_OFF),
-/* 0101 1101 1011 */ TABDECL( OP_LDRB_P_IMM_OFF),
-/* 0101 1101 1100 */ TABDECL( OP_LDRB_P_IMM_OFF),
-/* 0101 1101 1101 */ TABDECL( OP_LDRB_P_IMM_OFF),
-/* 0101 1101 1110 */ TABDECL( OP_LDRB_P_IMM_OFF),
-/* 0101 1101 1111 */ TABDECL( OP_LDRB_P_IMM_OFF),
-/* 0101 1110 0000 */ TABDECL( OP_STRB_P_IMM_OFF_PREIND),
-/* 0101 1110 0001 */ TABDECL( OP_STRB_P_IMM_OFF_PREIND),
-/* 0101 1110 0010 */ TABDECL( OP_STRB_P_IMM_OFF_PREIND),
-/* 0101 1110 0011 */ TABDECL( OP_STRB_P_IMM_OFF_PREIND),
-/* 0101 1110 0100 */ TABDECL( OP_STRB_P_IMM_OFF_PREIND),
-/* 0101 1110 0101 */ TABDECL( OP_STRB_P_IMM_OFF_PREIND),
-/* 0101 1110 0110 */ TABDECL( OP_STRB_P_IMM_OFF_PREIND),
-/* 0101 1110 0111 */ TABDECL( OP_STRB_P_IMM_OFF_PREIND),
-/* 0101 1110 1000 */ TABDECL( OP_STRB_P_IMM_OFF_PREIND),
-/* 0101 1110 1001 */ TABDECL( OP_STRB_P_IMM_OFF_PREIND),
-/* 0101 1110 1010 */ TABDECL( OP_STRB_P_IMM_OFF_PREIND),
-/* 0101 1110 1011 */ TABDECL( OP_STRB_P_IMM_OFF_PREIND),
-/* 0101 1110 1100 */ TABDECL( OP_STRB_P_IMM_OFF_PREIND),
-/* 0101 1110 1101 */ TABDECL( OP_STRB_P_IMM_OFF_PREIND),
-/* 0101 1110 1110 */ TABDECL( OP_STRB_P_IMM_OFF_PREIND),
-/* 0101 1110 1111 */ TABDECL( OP_STRB_P_IMM_OFF_PREIND),
-/* 0101 1111 0000 */ TABDECL( OP_LDRB_P_IMM_OFF_PREIND),
-/* 0101 1111 0001 */ TABDECL( OP_LDRB_P_IMM_OFF_PREIND),
-/* 0101 1111 0010 */ TABDECL( OP_LDRB_P_IMM_OFF_PREIND),
-/* 0101 1111 0011 */ TABDECL( OP_LDRB_P_IMM_OFF_PREIND),
-/* 0101 1111 0100 */ TABDECL( OP_LDRB_P_IMM_OFF_PREIND),
-/* 0101 1111 0101 */ TABDECL( OP_LDRB_P_IMM_OFF_PREIND),
-/* 0101 1111 0110 */ TABDECL( OP_LDRB_P_IMM_OFF_PREIND),
-/* 0101 1111 0111 */ TABDECL( OP_LDRB_P_IMM_OFF_PREIND),
-/* 0101 1111 1000 */ TABDECL( OP_LDRB_P_IMM_OFF_PREIND),
-/* 0101 1111 1001 */ TABDECL( OP_LDRB_P_IMM_OFF_PREIND),
-/* 0101 1111 1010 */ TABDECL( OP_LDRB_P_IMM_OFF_PREIND),
-/* 0101 1111 1011 */ TABDECL( OP_LDRB_P_IMM_OFF_PREIND),
-/* 0101 1111 1100 */ TABDECL( OP_LDRB_P_IMM_OFF_PREIND),
-/* 0101 1111 1101 */ TABDECL( OP_LDRB_P_IMM_OFF_PREIND),
-/* 0101 1111 1110 */ TABDECL( OP_LDRB_P_IMM_OFF_PREIND),
-/* 0101 1111 1111 */ TABDECL( OP_LDRB_P_IMM_OFF_PREIND),
-/* 0110 0000 0000 */ TABDECL( OP_STR_M_LSL_IMM_OFF_POSTIND),
-/* 0110 0000 0001 */ TABDECL( OP_UND),
-/* 0110 0000 0010 */ TABDECL( OP_STR_M_LSR_IMM_OFF_POSTIND),
-/* 0110 0000 0011 */ TABDECL( OP_UND),
-/* 0110 0000 0100 */ TABDECL( OP_STR_M_ASR_IMM_OFF_POSTIND),
-/* 0110 0000 0101 */ TABDECL( OP_UND),
-/* 0110 0000 0110 */ TABDECL( OP_STR_M_ROR_IMM_OFF_POSTIND),
-/* 0110 0000 0111 */ TABDECL( OP_UND),
-/* 0110 0000 1000 */ TABDECL( OP_STR_M_LSL_IMM_OFF_POSTIND),
-/* 0110 0000 1001 */ TABDECL( OP_UND),
-/* 0110 0000 1010 */ TABDECL( OP_STR_M_LSR_IMM_OFF_POSTIND),
-/* 0110 0000 1011 */ TABDECL( OP_UND),
-/* 0110 0000 1100 */ TABDECL( OP_STR_M_ASR_IMM_OFF_POSTIND),
-/* 0110 0000 1101 */ TABDECL( OP_UND),
-/* 0110 0000 1110 */ TABDECL( OP_STR_M_ROR_IMM_OFF_POSTIND),
-/* 0110 0000 1111 */ TABDECL( OP_UND),
-/* 0110 0001 0000 */ TABDECL( OP_LDR_M_LSL_IMM_OFF_POSTIND),
-/* 0110 0001 0001 */ TABDECL( OP_UND),
-/* 0110 0001 0010 */ TABDECL( OP_LDR_M_LSR_IMM_OFF_POSTIND),
-/* 0110 0001 0011 */ TABDECL( OP_UND),
-/* 0110 0001 0100 */ TABDECL( OP_LDR_M_ASR_IMM_OFF_POSTIND),
-/* 0110 0001 0101 */ TABDECL( OP_UND),
-/* 0110 0001 0110 */ TABDECL( OP_LDR_M_ROR_IMM_OFF_POSTIND),
-/* 0110 0001 0111 */ TABDECL( OP_UND),
-/* 0110 0001 1000 */ TABDECL( OP_LDR_M_LSL_IMM_OFF_POSTIND),
-/* 0110 0001 1001 */ TABDECL( OP_UND),
-/* 0110 0001 1010 */ TABDECL( OP_LDR_M_LSR_IMM_OFF_POSTIND),
-/* 0110 0001 1011 */ TABDECL( OP_UND),
-/* 0110 0001 1100 */ TABDECL( OP_LDR_M_ASR_IMM_OFF_POSTIND),
-/* 0110 0001 1101 */ TABDECL( OP_UND),
-/* 0110 0001 1110 */ TABDECL( OP_LDR_M_ROR_IMM_OFF_POSTIND),
-/* 0110 0001 1111 */ TABDECL( OP_UND),
-/* 0110 0010 0000 */ TABDECL( OP_STR_M_LSL_IMM_OFF_POSTIND),
-/* 0110 0010 0001 */ TABDECL( OP_UND),
-/* 0110 0010 0010 */ TABDECL( OP_STR_M_LSR_IMM_OFF_POSTIND),
-/* 0110 0010 0011 */ TABDECL( OP_UND),
-/* 0110 0010 0100 */ TABDECL( OP_STR_M_ASR_IMM_OFF_POSTIND),
-/* 0110 0010 0101 */ TABDECL( OP_UND),
-/* 0110 0010 0110 */ TABDECL( OP_STR_M_ROR_IMM_OFF_POSTIND),
-/* 0110 0010 0111 */ TABDECL( OP_UND),
-/* 0110 0010 1000 */ TABDECL( OP_STR_M_LSL_IMM_OFF_POSTIND),
-/* 0110 0010 1001 */ TABDECL( OP_UND),
-/* 0110 0010 1010 */ TABDECL( OP_STR_M_LSR_IMM_OFF_POSTIND),
-/* 0110 0010 1011 */ TABDECL( OP_UND),
-/* 0110 0010 1100 */ TABDECL( OP_STR_M_ASR_IMM_OFF_POSTIND),
-/* 0110 0010 1101 */ TABDECL( OP_UND),
-/* 0110 0010 1110 */ TABDECL( OP_STR_M_ROR_IMM_OFF_POSTIND),
-/* 0110 0010 1111 */ TABDECL( OP_UND),
-/* 0110 0011 0000 */ TABDECL( OP_LDR_M_LSL_IMM_OFF_POSTIND),
-/* 0110 0011 0001 */ TABDECL( OP_UND),
-/* 0110 0011 0010 */ TABDECL( OP_LDR_M_LSR_IMM_OFF_POSTIND),
-/* 0110 0011 0011 */ TABDECL( OP_UND),
-/* 0110 0011 0100 */ TABDECL( OP_LDR_M_ASR_IMM_OFF_POSTIND),
-/* 0110 0011 0101 */ TABDECL( OP_UND),
-/* 0110 0011 0110 */ TABDECL( OP_LDR_M_ROR_IMM_OFF_POSTIND),
-/* 0110 0011 0111 */ TABDECL( OP_UND),
-/* 0110 0011 1000 */ TABDECL( OP_LDR_M_LSL_IMM_OFF_POSTIND),
-/* 0110 0011 1001 */ TABDECL( OP_UND),
-/* 0110 0011 1010 */ TABDECL( OP_LDR_M_LSR_IMM_OFF_POSTIND),
-/* 0110 0011 1011 */ TABDECL( OP_UND),
-/* 0110 0011 1100 */ TABDECL( OP_LDR_M_ASR_IMM_OFF_POSTIND),
-/* 0110 0011 1101 */ TABDECL( OP_UND),
-/* 0110 0011 1110 */ TABDECL( OP_LDR_M_ROR_IMM_OFF_POSTIND),
-/* 0110 0011 1111 */ TABDECL( OP_UND),
-/* 0110 0100 0000 */ TABDECL( OP_STRB_M_LSL_IMM_OFF_POSTIND),
-/* 0110 0100 0001 */ TABDECL( OP_UND),
-/* 0110 0100 0010 */ TABDECL( OP_STRB_M_LSR_IMM_OFF_POSTIND),
-/* 0110 0100 0011 */ TABDECL( OP_UND),
-/* 0110 0100 0100 */ TABDECL( OP_STRB_M_ASR_IMM_OFF_POSTIND),
-/* 0110 0100 0101 */ TABDECL( OP_UND),
-/* 0110 0100 0110 */ TABDECL( OP_STRB_M_ROR_IMM_OFF_POSTIND),
-/* 0110 0100 0111 */ TABDECL( OP_UND),
-/* 0110 0100 1000 */ TABDECL( OP_STRB_M_LSL_IMM_OFF_POSTIND),
-/* 0110 0100 1001 */ TABDECL( OP_UND),
-/* 0110 0100 1010 */ TABDECL( OP_STRB_M_LSR_IMM_OFF_POSTIND),
-/* 0110 0100 1011 */ TABDECL( OP_UND),
-/* 0110 0100 1100 */ TABDECL( OP_STRB_M_ASR_IMM_OFF_POSTIND),
-/* 0110 0100 1101 */ TABDECL( OP_UND),
-/* 0110 0100 1110 */ TABDECL( OP_STRB_M_ROR_IMM_OFF_POSTIND),
-/* 0110 0100 1111 */ TABDECL( OP_UND),
-/* 0110 0101 0000 */ TABDECL( OP_LDRB_M_LSL_IMM_OFF_POSTIND),
-/* 0110 0101 0001 */ TABDECL( OP_UND),
-/* 0110 0101 0010 */ TABDECL( OP_LDRB_M_LSR_IMM_OFF_POSTIND),
-/* 0110 0101 0011 */ TABDECL( OP_UND),
-/* 0110 0101 0100 */ TABDECL( OP_LDRB_M_ASR_IMM_OFF_POSTIND),
-/* 0110 0101 0101 */ TABDECL( OP_UND),
-/* 0110 0101 0110 */ TABDECL( OP_LDRB_M_ROR_IMM_OFF_POSTIND),
-/* 0110 0101 0111 */ TABDECL( OP_UND),
-/* 0110 0101 1000 */ TABDECL( OP_LDRB_M_LSL_IMM_OFF_POSTIND),
-/* 0110 0101 1001 */ TABDECL( OP_UND),
-/* 0110 0101 1010 */ TABDECL( OP_LDRB_M_LSR_IMM_OFF_POSTIND),
-/* 0110 0101 1011 */ TABDECL( OP_UND),
-/* 0110 0101 1100 */ TABDECL( OP_LDRB_M_ASR_IMM_OFF_POSTIND),
-/* 0110 0101 1101 */ TABDECL( OP_UND),
-/* 0110 0101 1110 */ TABDECL( OP_LDRB_M_ROR_IMM_OFF_POSTIND),
-/* 0110 0101 1111 */ TABDECL( OP_UND),
-/* 0110 0110 0000 */ TABDECL( OP_STRB_M_LSL_IMM_OFF_POSTIND),
-/* 0110 0110 0001 */ TABDECL( OP_UND),
-/* 0110 0110 0010 */ TABDECL( OP_STRB_M_LSR_IMM_OFF_POSTIND),
-/* 0110 0110 0011 */ TABDECL( OP_UND),
-/* 0110 0110 0100 */ TABDECL( OP_STRB_M_ASR_IMM_OFF_POSTIND),
-/* 0110 0110 0101 */ TABDECL( OP_UND),
-/* 0110 0110 0110 */ TABDECL( OP_STRB_M_ROR_IMM_OFF_POSTIND),
-/* 0110 0110 0111 */ TABDECL( OP_UND),
-/* 0110 0110 1000 */ TABDECL( OP_STRB_M_LSL_IMM_OFF_POSTIND),
-/* 0110 0110 1001 */ TABDECL( OP_UND),
-/* 0110 0110 1010 */ TABDECL( OP_STRB_M_LSR_IMM_OFF_POSTIND),
-/* 0110 0110 1011 */ TABDECL( OP_UND),
-/* 0110 0110 1100 */ TABDECL( OP_STRB_M_ASR_IMM_OFF_POSTIND),
-/* 0110 0110 1101 */ TABDECL( OP_UND),
-/* 0110 0110 1110 */ TABDECL( OP_STRB_M_ROR_IMM_OFF_POSTIND),
-/* 0110 0110 1111 */ TABDECL( OP_UND),
-/* 0110 0111 0000 */ TABDECL( OP_LDRB_M_LSL_IMM_OFF_POSTIND),
-/* 0110 0111 0001 */ TABDECL( OP_UND),
-/* 0110 0111 0010 */ TABDECL( OP_LDRB_M_LSR_IMM_OFF_POSTIND),
-/* 0110 0111 0011 */ TABDECL( OP_UND),
-/* 0110 0111 0100 */ TABDECL( OP_LDRB_M_ASR_IMM_OFF_POSTIND),
-/* 0110 0111 0101 */ TABDECL( OP_UND),
-/* 0110 0111 0110 */ TABDECL( OP_LDRB_M_ROR_IMM_OFF_POSTIND),
-/* 0110 0111 0111 */ TABDECL( OP_UND),
-/* 0110 0111 1000 */ TABDECL( OP_LDRB_M_LSL_IMM_OFF_POSTIND),
-/* 0110 0111 1001 */ TABDECL( OP_UND),
-/* 0110 0111 1010 */ TABDECL( OP_LDRB_M_LSR_IMM_OFF_POSTIND),
-/* 0110 0111 1011 */ TABDECL( OP_UND),
-/* 0110 0111 1100 */ TABDECL( OP_LDRB_M_ASR_IMM_OFF_POSTIND),
-/* 0110 0111 1101 */ TABDECL( OP_UND),
-/* 0110 0111 1110 */ TABDECL( OP_LDRB_M_ROR_IMM_OFF_POSTIND),
-/* 0110 0111 1111 */ TABDECL( OP_UND),
-/* 0110 1000 0000 */ TABDECL( OP_STR_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1000 0001 */ TABDECL( OP_UND),
-/* 0110 1000 0010 */ TABDECL( OP_STR_P_LSR_IMM_OFF_POSTIND),
-/* 0110 1000 0011 */ TABDECL( OP_UND),
-/* 0110 1000 0100 */ TABDECL( OP_STR_P_ASR_IMM_OFF_POSTIND),
-/* 0110 1000 0101 */ TABDECL( OP_UND),
-/* 0110 1000 0110 */ TABDECL( OP_STR_P_ROR_IMM_OFF_POSTIND),
-/* 0110 1000 0111 */ TABDECL( OP_UND),
-/* 0110 1000 1000 */ TABDECL( OP_STR_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1000 1001 */ TABDECL( OP_UND),
-/* 0110 1000 1010 */ TABDECL( OP_STR_P_LSR_IMM_OFF_POSTIND),
-/* 0110 1000 1011 */ TABDECL( OP_UND),
-/* 0110 1000 1100 */ TABDECL( OP_STR_P_ASR_IMM_OFF_POSTIND),
-/* 0110 1000 1101 */ TABDECL( OP_UND),
-/* 0110 1000 1110 */ TABDECL( OP_STR_P_ROR_IMM_OFF_POSTIND),
-/* 0110 1000 1111 */ TABDECL( OP_UND),
-/* 0110 1001 0000 */ TABDECL( OP_LDR_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1001 0001 */ TABDECL( OP_UND),
-/* 0110 1001 0010 */ TABDECL( OP_LDR_P_LSR_IMM_OFF_POSTIND),
-/* 0110 1001 0011 */ TABDECL( OP_UND),
-/* 0110 1001 0100 */ TABDECL( OP_LDR_P_ASR_IMM_OFF_POSTIND),
-/* 0110 1001 0101 */ TABDECL( OP_UND),
-/* 0110 1001 0110 */ TABDECL( OP_LDR_P_ROR_IMM_OFF_POSTIND),
-/* 0110 1001 0111 */ TABDECL( OP_UND),
-/* 0110 1001 1000 */ TABDECL( OP_LDR_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1001 1001 */ TABDECL( OP_UND),
-/* 0110 1001 1010 */ TABDECL( OP_LDR_P_LSR_IMM_OFF_POSTIND),
-/* 0110 1001 1011 */ TABDECL( OP_UND),
-/* 0110 1001 1100 */ TABDECL( OP_LDR_P_ASR_IMM_OFF_POSTIND),
-/* 0110 1001 1101 */ TABDECL( OP_UND),
-/* 0110 1001 1110 */ TABDECL( OP_LDR_P_ROR_IMM_OFF_POSTIND),
-/* 0110 1001 1111 */ TABDECL( OP_UND),
-/* 0110 1010 0000 */ TABDECL( OP_STR_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1010 0001 */ TABDECL( OP_UND),
-/* 0110 1010 0010 */ TABDECL( OP_STR_P_LSR_IMM_OFF_POSTIND),
-/* 0110 1010 0011 */ TABDECL( OP_UND),
-/* 0110 1010 0100 */ TABDECL( OP_STR_P_ASR_IMM_OFF_POSTIND),
-/* 0110 1010 0101 */ TABDECL( OP_UND),
-/* 0110 1010 0110 */ TABDECL( OP_STR_P_ROR_IMM_OFF_POSTIND),
-/* 0110 1010 0111 */ TABDECL( OP_UND),
-/* 0110 1010 1000 */ TABDECL( OP_STR_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1010 1001 */ TABDECL( OP_UND),
-/* 0110 1010 1010 */ TABDECL( OP_STR_P_LSR_IMM_OFF_POSTIND),
-/* 0110 1010 1011 */ TABDECL( OP_UND),
-/* 0110 1010 1100 */ TABDECL( OP_STR_P_ASR_IMM_OFF_POSTIND),
-/* 0110 1010 1101 */ TABDECL( OP_UND),
-/* 0110 1010 1110 */ TABDECL( OP_STR_P_ROR_IMM_OFF_POSTIND),
-/* 0110 1010 1111 */ TABDECL( OP_UND),
-/* 0110 1011 0000 */ TABDECL( OP_LDR_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1011 0001 */ TABDECL( OP_UND),
-/* 0110 1011 0010 */ TABDECL( OP_LDR_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1011 0011 */ TABDECL( OP_UND),
-/* 0110 1011 0100 */ TABDECL( OP_LDR_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1011 0101 */ TABDECL( OP_UND),
-/* 0110 1011 0110 */ TABDECL( OP_LDR_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1011 0111 */ TABDECL( OP_UND),
-/* 0110 1011 1000 */ TABDECL( OP_LDR_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1011 1001 */ TABDECL( OP_UND),
-/* 0110 1011 1010 */ TABDECL( OP_LDR_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1011 1011 */ TABDECL( OP_UND),
-/* 0110 1011 1100 */ TABDECL( OP_LDR_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1011 1101 */ TABDECL( OP_UND),
-/* 0110 1011 1110 */ TABDECL( OP_LDR_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1011 1111 */ TABDECL( OP_UND),
-/* 0110 1100 0000 */ TABDECL( OP_STRB_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1100 0001 */ TABDECL( OP_UND),
-/* 0110 1100 0010 */ TABDECL( OP_STRB_P_LSR_IMM_OFF_POSTIND),
-/* 0110 1100 0011 */ TABDECL( OP_UND),
-/* 0110 1100 0100 */ TABDECL( OP_STRB_P_ASR_IMM_OFF_POSTIND),
-/* 0110 1100 0101 */ TABDECL( OP_UND),
-/* 0110 1100 0110 */ TABDECL( OP_STRB_P_ROR_IMM_OFF_POSTIND),
-/* 0110 1100 0111 */ TABDECL( OP_UND),
-/* 0110 1100 1000 */ TABDECL( OP_STRB_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1100 1001 */ TABDECL( OP_UND),
-/* 0110 1100 1010 */ TABDECL( OP_STRB_P_LSR_IMM_OFF_POSTIND),
-/* 0110 1100 1011 */ TABDECL( OP_UND),
-/* 0110 1100 1100 */ TABDECL( OP_STRB_P_ASR_IMM_OFF_POSTIND),
-/* 0110 1100 1101 */ TABDECL( OP_UND),
-/* 0110 1100 1110 */ TABDECL( OP_STRB_P_ROR_IMM_OFF_POSTIND),
-/* 0110 1100 1111 */ TABDECL( OP_UND),
-/* 0110 1101 0000 */ TABDECL( OP_LDRB_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1101 0001 */ TABDECL( OP_UND),
-/* 0110 1101 0010 */ TABDECL( OP_LDRB_P_LSR_IMM_OFF_POSTIND),
-/* 0110 1101 0011 */ TABDECL( OP_UND),
-/* 0110 1101 0100 */ TABDECL( OP_LDRB_P_ASR_IMM_OFF_POSTIND),
-/* 0110 1101 0101 */ TABDECL( OP_UND),
-/* 0110 1101 0110 */ TABDECL( OP_LDRB_P_ROR_IMM_OFF_POSTIND),
-/* 0110 1101 0111 */ TABDECL( OP_UND),
-/* 0110 1101 1000 */ TABDECL( OP_LDRB_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1101 1001 */ TABDECL( OP_UND),
-/* 0110 1101 1010 */ TABDECL( OP_LDRB_P_LSR_IMM_OFF_POSTIND),
-/* 0110 1101 1011 */ TABDECL( OP_UND),
-/* 0110 1101 1100 */ TABDECL( OP_LDRB_P_ASR_IMM_OFF_POSTIND),
-/* 0110 1101 1101 */ TABDECL( OP_UND),
-/* 0110 1101 1110 */ TABDECL( OP_LDRB_P_ROR_IMM_OFF_POSTIND),
-/* 0110 1101 1111 */ TABDECL( OP_UND),
-/* 0110 1110 0000 */ TABDECL( OP_STRB_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1110 0001 */ TABDECL( OP_UND),
-/* 0110 1110 0010 */ TABDECL( OP_STRB_P_LSR_IMM_OFF_POSTIND),
-/* 0110 1110 0011 */ TABDECL( OP_UND),
-/* 0110 1110 0100 */ TABDECL( OP_STRB_P_ASR_IMM_OFF_POSTIND),
-/* 0110 1110 0101 */ TABDECL( OP_UND),
-/* 0110 1110 0110 */ TABDECL( OP_STRB_P_ROR_IMM_OFF_POSTIND),
-/* 0110 1110 0111 */ TABDECL( OP_UND),
-/* 0110 1110 1000 */ TABDECL( OP_STRB_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1110 1001 */ TABDECL( OP_UND),
-/* 0110 1110 1010 */ TABDECL( OP_STRB_P_LSR_IMM_OFF_POSTIND),
-/* 0110 1110 1011 */ TABDECL( OP_UND),
-/* 0110 1110 1100 */ TABDECL( OP_STRB_P_ASR_IMM_OFF_POSTIND),
-/* 0110 1110 1101 */ TABDECL( OP_UND),
-/* 0110 1110 1110 */ TABDECL( OP_STRB_P_ROR_IMM_OFF_POSTIND),
-/* 0110 1110 1111 */ TABDECL( OP_UND),
-/* 0110 1111 0000 */ TABDECL( OP_LDRB_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1111 0001 */ TABDECL( OP_UND),
-/* 0110 1111 0010 */ TABDECL( OP_LDRB_P_LSR_IMM_OFF_POSTIND),
-/* 0110 1111 0011 */ TABDECL( OP_UND),
-/* 0110 1111 0100 */ TABDECL( OP_LDRB_P_ASR_IMM_OFF_POSTIND),
-/* 0110 1111 0101 */ TABDECL( OP_UND),
-/* 0110 1111 0110 */ TABDECL( OP_LDRB_P_ROR_IMM_OFF_POSTIND),
-/* 0110 1111 0111 */ TABDECL( OP_UND),
-/* 0110 1111 1000 */ TABDECL( OP_LDRB_P_LSL_IMM_OFF_POSTIND),
-/* 0110 1111 1001 */ TABDECL( OP_UND),
-/* 0110 1111 1010 */ TABDECL( OP_LDRB_P_LSR_IMM_OFF_POSTIND),
-/* 0110 1111 1011 */ TABDECL( OP_UND),
-/* 0110 1111 1100 */ TABDECL( OP_LDRB_P_ASR_IMM_OFF_POSTIND),
-/* 0110 1111 1101 */ TABDECL( OP_UND),
-/* 0110 1111 1110 */ TABDECL( OP_LDRB_P_ROR_IMM_OFF_POSTIND),
-/* 0110 1111 1111 */ TABDECL( OP_UND),
-/* 0111 0000 0000 */ TABDECL( OP_STR_M_LSL_IMM_OFF),
-/* 0111 0000 0001 */ TABDECL( OP_UND),
-/* 0111 0000 0010 */ TABDECL( OP_STR_M_LSR_IMM_OFF),
-/* 0111 0000 0011 */ TABDECL( OP_UND),
-/* 0111 0000 0100 */ TABDECL( OP_STR_M_ASR_IMM_OFF),
-/* 0111 0000 0101 */ TABDECL( OP_UND),
-/* 0111 0000 0110 */ TABDECL( OP_STR_M_ROR_IMM_OFF),
-/* 0111 0000 0111 */ TABDECL( OP_UND),
-/* 0111 0000 1000 */ TABDECL( OP_STR_M_LSL_IMM_OFF),
-/* 0111 0000 1001 */ TABDECL( OP_UND),
-/* 0111 0000 1010 */ TABDECL( OP_STR_M_LSR_IMM_OFF),
-/* 0111 0000 1011 */ TABDECL( OP_UND),
-/* 0111 0000 1100 */ TABDECL( OP_STR_M_ASR_IMM_OFF),
-/* 0111 0000 1101 */ TABDECL( OP_UND),
-/* 0111 0000 1110 */ TABDECL( OP_STR_M_ROR_IMM_OFF),
-/* 0111 0000 1111 */ TABDECL( OP_UND),
-/* 0111 0001 0000 */ TABDECL( OP_LDR_M_LSL_IMM_OFF),
-/* 0111 0001 0001 */ TABDECL( OP_UND),
-/* 0111 0001 0010 */ TABDECL( OP_LDR_M_LSR_IMM_OFF),
-/* 0111 0001 0011 */ TABDECL( OP_UND),
-/* 0111 0001 0100 */ TABDECL( OP_LDR_M_ASR_IMM_OFF),
-/* 0111 0001 0101 */ TABDECL( OP_UND),
-/* 0111 0001 0110 */ TABDECL( OP_LDR_M_ROR_IMM_OFF),
-/* 0111 0001 0111 */ TABDECL( OP_UND),
-/* 0111 0001 1000 */ TABDECL( OP_LDR_M_LSL_IMM_OFF),
-/* 0111 0001 1001 */ TABDECL( OP_UND),
-/* 0111 0001 1010 */ TABDECL( OP_LDR_M_LSR_IMM_OFF),
-/* 0111 0001 1011 */ TABDECL( OP_UND),
-/* 0111 0001 1100 */ TABDECL( OP_LDR_M_ASR_IMM_OFF),
-/* 0111 0001 1101 */ TABDECL( OP_UND),
-/* 0111 0001 1110 */ TABDECL( OP_LDR_M_ROR_IMM_OFF),
-/* 0111 0001 1111 */ TABDECL( OP_UND),
-/* 0111 0010 0000 */ TABDECL( OP_STR_M_LSL_IMM_OFF_PREIND),
-/* 0111 0010 0001 */ TABDECL( OP_UND),
-/* 0111 0010 0010 */ TABDECL( OP_STR_M_LSR_IMM_OFF_PREIND),
-/* 0111 0010 0011 */ TABDECL( OP_UND),
-/* 0111 0010 0100 */ TABDECL( OP_STR_M_ASR_IMM_OFF_PREIND),
-/* 0111 0010 0101 */ TABDECL( OP_UND),
-/* 0111 0010 0110 */ TABDECL( OP_STR_M_ROR_IMM_OFF_PREIND),
-/* 0111 0010 0111 */ TABDECL( OP_UND),
-/* 0111 0010 1000 */ TABDECL( OP_STR_M_LSL_IMM_OFF_PREIND),
-/* 0111 0010 1001 */ TABDECL( OP_UND),
-/* 0111 0010 1010 */ TABDECL( OP_STR_M_LSR_IMM_OFF_PREIND),
-/* 0111 0010 1011 */ TABDECL( OP_UND),
-/* 0111 0010 1100 */ TABDECL( OP_STR_M_ASR_IMM_OFF_PREIND),
-/* 0111 0010 1101 */ TABDECL( OP_UND),
-/* 0111 0010 1110 */ TABDECL( OP_STR_M_ROR_IMM_OFF_PREIND),
-/* 0111 0010 1111 */ TABDECL( OP_UND),
-/* 0111 0011 0000 */ TABDECL( OP_LDR_M_LSL_IMM_OFF_PREIND),
-/* 0111 0011 0001 */ TABDECL( OP_UND),
-/* 0111 0011 0010 */ TABDECL( OP_LDR_M_LSR_IMM_OFF_PREIND),
-/* 0111 0011 0011 */ TABDECL( OP_UND),
-/* 0111 0011 0100 */ TABDECL( OP_LDR_M_ASR_IMM_OFF_PREIND),
-/* 0111 0011 0101 */ TABDECL( OP_UND),
-/* 0111 0011 0110 */ TABDECL( OP_LDR_M_ROR_IMM_OFF_PREIND),
-/* 0111 0011 0111 */ TABDECL( OP_UND),
-/* 0111 0011 1000 */ TABDECL( OP_LDR_M_LSL_IMM_OFF_PREIND),
-/* 0111 0011 1001 */ TABDECL( OP_UND),
-/* 0111 0011 1010 */ TABDECL( OP_LDR_M_LSR_IMM_OFF_PREIND),
-/* 0111 0011 1011 */ TABDECL( OP_UND),
-/* 0111 0011 1100 */ TABDECL( OP_LDR_M_ASR_IMM_OFF_PREIND),
-/* 0111 0011 1101 */ TABDECL( OP_UND),
-/* 0111 0011 1110 */ TABDECL( OP_LDR_M_ROR_IMM_OFF_PREIND),
-/* 0111 0011 1111 */ TABDECL( OP_UND),
-/* 0111 0100 0000 */ TABDECL( OP_STRB_M_LSL_IMM_OFF),
-/* 0111 0100 0001 */ TABDECL( OP_UND),
-/* 0111 0100 0010 */ TABDECL( OP_STRB_M_LSR_IMM_OFF),
-/* 0111 0100 0011 */ TABDECL( OP_UND),
-/* 0111 0100 0100 */ TABDECL( OP_STRB_M_ASR_IMM_OFF),
-/* 0111 0100 0101 */ TABDECL( OP_UND),
-/* 0111 0100 0110 */ TABDECL( OP_STRB_M_ROR_IMM_OFF),
-/* 0111 0100 0111 */ TABDECL( OP_UND),
-/* 0111 0100 1000 */ TABDECL( OP_STRB_M_LSL_IMM_OFF),
-/* 0111 0100 1001 */ TABDECL( OP_UND),
-/* 0111 0100 1010 */ TABDECL( OP_STRB_M_LSR_IMM_OFF),
-/* 0111 0100 1011 */ TABDECL( OP_UND),
-/* 0111 0100 1100 */ TABDECL( OP_STRB_M_ASR_IMM_OFF),
-/* 0111 0100 1101 */ TABDECL( OP_UND),
-/* 0111 0100 1110 */ TABDECL( OP_STRB_M_ROR_IMM_OFF),
-/* 0111 0100 1111 */ TABDECL( OP_UND),
-/* 0111 0101 0000 */ TABDECL( OP_LDRB_M_LSL_IMM_OFF),
-/* 0111 0101 0001 */ TABDECL( OP_UND),
-/* 0111 0101 0010 */ TABDECL( OP_LDRB_M_LSR_IMM_OFF),
-/* 0111 0101 0011 */ TABDECL( OP_UND),
-/* 0111 0101 0100 */ TABDECL( OP_LDRB_M_ASR_IMM_OFF),
-/* 0111 0101 0101 */ TABDECL( OP_UND),
-/* 0111 0101 0110 */ TABDECL( OP_LDRB_M_ROR_IMM_OFF),
-/* 0111 0101 0111 */ TABDECL( OP_UND),
-/* 0111 0101 1000 */ TABDECL( OP_LDRB_M_LSL_IMM_OFF),
-/* 0111 0101 1001 */ TABDECL( OP_UND),
-/* 0111 0101 1010 */ TABDECL( OP_LDRB_M_LSR_IMM_OFF),
-/* 0111 0101 1011 */ TABDECL( OP_UND),
-/* 0111 0101 1100 */ TABDECL( OP_LDRB_M_ASR_IMM_OFF),
-/* 0111 0101 1101 */ TABDECL( OP_UND),
-/* 0111 0101 1110 */ TABDECL( OP_LDRB_M_ROR_IMM_OFF),
-/* 0111 0101 1111 */ TABDECL( OP_UND),
-/* 0111 0110 0000 */ TABDECL( OP_STRB_M_LSL_IMM_OFF_PREIND),
-/* 0111 0110 0001 */ TABDECL( OP_UND),
-/* 0111 0110 0010 */ TABDECL( OP_STRB_M_LSR_IMM_OFF_PREIND),
-/* 0111 0110 0011 */ TABDECL( OP_UND),
-/* 0111 0110 0100 */ TABDECL( OP_STRB_M_ASR_IMM_OFF_PREIND),
-/* 0111 0110 0101 */ TABDECL( OP_UND),
-/* 0111 0110 0110 */ TABDECL( OP_STRB_M_ROR_IMM_OFF_PREIND),
-/* 0111 0110 0111 */ TABDECL( OP_UND),
-/* 0111 0110 1000 */ TABDECL( OP_STRB_M_LSL_IMM_OFF_PREIND),
-/* 0111 0110 1001 */ TABDECL( OP_UND),
-/* 0111 0110 1010 */ TABDECL( OP_STRB_M_LSR_IMM_OFF_PREIND),
-/* 0111 0110 1011 */ TABDECL( OP_UND),
-/* 0111 0110 1100 */ TABDECL( OP_STRB_M_ASR_IMM_OFF_PREIND),
-/* 0111 0110 1101 */ TABDECL( OP_UND),
-/* 0111 0110 1110 */ TABDECL( OP_STRB_M_ROR_IMM_OFF_PREIND),
-/* 0111 0110 1111 */ TABDECL( OP_UND),
-/* 0111 0111 0000 */ TABDECL( OP_LDRB_M_LSL_IMM_OFF_PREIND),
-/* 0111 0111 0001 */ TABDECL( OP_UND),
-/* 0111 0111 0010 */ TABDECL( OP_LDRB_M_LSR_IMM_OFF_PREIND),
-/* 0111 0111 0011 */ TABDECL( OP_UND),
-/* 0111 0111 0100 */ TABDECL( OP_LDRB_M_ASR_IMM_OFF_PREIND),
-/* 0111 0111 0101 */ TABDECL( OP_UND),
-/* 0111 0111 0110 */ TABDECL( OP_LDRB_M_ROR_IMM_OFF_PREIND),
-/* 0111 0111 0111 */ TABDECL( OP_UND),
-/* 0111 0111 1000 */ TABDECL( OP_LDRB_M_LSL_IMM_OFF_PREIND),
-/* 0111 0111 1001 */ TABDECL( OP_UND),
-/* 0111 0111 1010 */ TABDECL( OP_LDRB_M_LSR_IMM_OFF_PREIND),
-/* 0111 0111 1011 */ TABDECL( OP_UND),
-/* 0111 0111 1100 */ TABDECL( OP_LDRB_M_ASR_IMM_OFF_PREIND),
-/* 0111 0111 1101 */ TABDECL( OP_UND),
-/* 0111 0111 1110 */ TABDECL( OP_LDRB_M_ROR_IMM_OFF_PREIND),
-/* 0111 0111 1111 */ TABDECL( OP_UND),
-/* 0111 1000 0000 */ TABDECL( OP_STR_P_LSL_IMM_OFF),
-/* 0111 1000 0001 */ TABDECL( OP_UND),
-/* 0111 1000 0010 */ TABDECL( OP_STR_P_LSR_IMM_OFF),
-/* 0111 1000 0011 */ TABDECL( OP_UND),
-/* 0111 1000 0100 */ TABDECL( OP_STR_P_ASR_IMM_OFF),
-/* 0111 1000 0101 */ TABDECL( OP_UND),
-/* 0111 1000 0110 */ TABDECL( OP_STR_P_ROR_IMM_OFF),
-/* 0111 1000 0111 */ TABDECL( OP_UND),
-/* 0111 1000 1000 */ TABDECL( OP_STR_P_LSL_IMM_OFF),
-/* 0111 1000 1001 */ TABDECL( OP_UND),
-/* 0111 1000 1010 */ TABDECL( OP_STR_P_LSR_IMM_OFF),
-/* 0111 1000 1011 */ TABDECL( OP_UND),
-/* 0111 1000 1100 */ TABDECL( OP_STR_P_ASR_IMM_OFF),
-/* 0111 1000 1101 */ TABDECL( OP_UND),
-/* 0111 1000 1110 */ TABDECL( OP_STR_P_ROR_IMM_OFF),
-/* 0111 1000 1111 */ TABDECL( OP_UND),
-/* 0111 1001 0000 */ TABDECL( OP_LDR_P_LSL_IMM_OFF),
-/* 0111 1001 0001 */ TABDECL( OP_UND),
-/* 0111 1001 0010 */ TABDECL( OP_LDR_P_LSR_IMM_OFF),
-/* 0111 1001 0011 */ TABDECL( OP_UND),
-/* 0111 1001 0100 */ TABDECL( OP_LDR_P_ASR_IMM_OFF),
-/* 0111 1001 0101 */ TABDECL( OP_UND),
-/* 0111 1001 0110 */ TABDECL( OP_LDR_P_ROR_IMM_OFF),
-/* 0111 1001 0111 */ TABDECL( OP_UND),
-/* 0111 1001 1000 */ TABDECL( OP_LDR_P_LSL_IMM_OFF),
-/* 0111 1001 1001 */ TABDECL( OP_UND),
-/* 0111 1001 1010 */ TABDECL( OP_LDR_P_LSR_IMM_OFF),
-/* 0111 1001 1011 */ TABDECL( OP_UND),
-/* 0111 1001 1100 */ TABDECL( OP_LDR_P_ASR_IMM_OFF),
-/* 0111 1001 1101 */ TABDECL( OP_UND),
-/* 0111 1001 1110 */ TABDECL( OP_LDR_P_ROR_IMM_OFF),
-/* 0111 1001 1111 */ TABDECL( OP_UND),
-/* 0111 1010 0000 */ TABDECL( OP_STR_P_LSL_IMM_OFF_PREIND),
-/* 0111 1010 0001 */ TABDECL( OP_UND),
-/* 0111 1010 0010 */ TABDECL( OP_STR_P_LSR_IMM_OFF_PREIND),
-/* 0111 1010 0011 */ TABDECL( OP_UND),
-/* 0111 1010 0100 */ TABDECL( OP_STR_P_ASR_IMM_OFF_PREIND),
-/* 0111 1010 0101 */ TABDECL( OP_UND),
-/* 0111 1010 0110 */ TABDECL( OP_STR_P_ROR_IMM_OFF_PREIND),
-/* 0111 1010 0111 */ TABDECL( OP_UND),
-/* 0111 1010 1000 */ TABDECL( OP_STR_P_LSL_IMM_OFF_PREIND),
-/* 0111 1010 1001 */ TABDECL( OP_UND),
-/* 0111 1010 1010 */ TABDECL( OP_STR_P_LSR_IMM_OFF_PREIND),
-/* 0111 1010 1011 */ TABDECL( OP_UND),
-/* 0111 1010 1100 */ TABDECL( OP_STR_P_ASR_IMM_OFF_PREIND),
-/* 0111 1010 1101 */ TABDECL( OP_UND),
-/* 0111 1010 1110 */ TABDECL( OP_STR_P_ROR_IMM_OFF_PREIND),
-/* 0111 1010 1111 */ TABDECL( OP_UND),
-/* 0111 1011 0000 */ TABDECL( OP_LDR_P_LSL_IMM_OFF_PREIND),
-/* 0111 1011 0001 */ TABDECL( OP_UND),
-/* 0111 1011 0010 */ TABDECL( OP_LDR_P_LSR_IMM_OFF_PREIND),
-/* 0111 1011 0011 */ TABDECL( OP_UND),
-/* 0111 1011 0100 */ TABDECL( OP_LDR_P_ASR_IMM_OFF_PREIND),
-/* 0111 1011 0101 */ TABDECL( OP_UND),
-/* 0111 1011 0110 */ TABDECL( OP_LDR_P_ROR_IMM_OFF_PREIND),
-/* 0111 1011 0111 */ TABDECL( OP_UND),
-/* 0111 1011 1000 */ TABDECL( OP_LDR_P_LSL_IMM_OFF_PREIND),
-/* 0111 1011 1001 */ TABDECL( OP_UND),
-/* 0111 1011 1010 */ TABDECL( OP_LDR_P_LSR_IMM_OFF_PREIND),
-/* 0111 1011 1011 */ TABDECL( OP_UND),
-/* 0111 1011 1100 */ TABDECL( OP_LDR_P_ASR_IMM_OFF_PREIND),
-/* 0111 1011 1101 */ TABDECL( OP_UND),
-/* 0111 1011 1110 */ TABDECL( OP_LDR_P_ROR_IMM_OFF_PREIND),
-/* 0111 1011 1111 */ TABDECL( OP_UND),
-/* 0111 1100 0000 */ TABDECL( OP_STRB_P_LSL_IMM_OFF),
-/* 0111 1100 0001 */ TABDECL( OP_UND),
-/* 0111 1100 0010 */ TABDECL( OP_STRB_P_LSR_IMM_OFF),
-/* 0111 1100 0011 */ TABDECL( OP_UND),
-/* 0111 1100 0100 */ TABDECL( OP_STRB_P_ASR_IMM_OFF),
-/* 0111 1100 0101 */ TABDECL( OP_UND),
-/* 0111 1100 0110 */ TABDECL( OP_STRB_P_ROR_IMM_OFF),
-/* 0111 1100 0111 */ TABDECL( OP_UND),
-/* 0111 1100 1000 */ TABDECL( OP_STRB_P_LSL_IMM_OFF),
-/* 0111 1100 1001 */ TABDECL( OP_UND),
-/* 0111 1100 1010 */ TABDECL( OP_STRB_P_LSR_IMM_OFF),
-/* 0111 1100 1011 */ TABDECL( OP_UND),
-/* 0111 1100 1100 */ TABDECL( OP_STRB_P_ASR_IMM_OFF),
-/* 0111 1100 1101 */ TABDECL( OP_UND),
-/* 0111 1100 1110 */ TABDECL( OP_STRB_P_ROR_IMM_OFF),
-/* 0111 1100 1111 */ TABDECL( OP_UND),
-/* 0111 1101 0000 */ TABDECL( OP_LDRB_P_LSL_IMM_OFF),
-/* 0111 1101 0001 */ TABDECL( OP_UND),
-/* 0111 1101 0010 */ TABDECL( OP_LDRB_P_LSR_IMM_OFF),
-/* 0111 1101 0011 */ TABDECL( OP_UND),
-/* 0111 1101 0100 */ TABDECL( OP_LDRB_P_ASR_IMM_OFF),
-/* 0111 1101 0101 */ TABDECL( OP_UND),
-/* 0111 1101 0110 */ TABDECL( OP_LDRB_P_ROR_IMM_OFF),
-/* 0111 1101 0111 */ TABDECL( OP_UND),
-/* 0111 1101 1000 */ TABDECL( OP_LDRB_P_LSL_IMM_OFF),
-/* 0111 1101 1001 */ TABDECL( OP_UND),
-/* 0111 1101 1010 */ TABDECL( OP_LDRB_P_LSR_IMM_OFF),
-/* 0111 1101 1011 */ TABDECL( OP_UND),
-/* 0111 1101 1100 */ TABDECL( OP_LDRB_P_ASR_IMM_OFF),
-/* 0111 1101 1101 */ TABDECL( OP_UND),
-/* 0111 1101 1110 */ TABDECL( OP_LDRB_P_ROR_IMM_OFF),
-/* 0111 1101 1111 */ TABDECL( OP_UND),
-/* 0111 1110 0000 */ TABDECL( OP_STRB_P_LSL_IMM_OFF_PREIND),
-/* 0111 1110 0001 */ TABDECL( OP_UND),
-/* 0111 1110 0010 */ TABDECL( OP_STRB_P_LSR_IMM_OFF_PREIND),
-/* 0111 1110 0011 */ TABDECL( OP_UND),
-/* 0111 1110 0100 */ TABDECL( OP_STRB_P_ASR_IMM_OFF_PREIND),
-/* 0111 1110 0101 */ TABDECL( OP_UND),
-/* 0111 1110 0110 */ TABDECL( OP_STRB_P_ROR_IMM_OFF_PREIND),
-/* 0111 1110 0111 */ TABDECL( OP_UND),
-/* 0111 1110 1000 */ TABDECL( OP_STRB_P_LSL_IMM_OFF_PREIND),
-/* 0111 1110 1001 */ TABDECL( OP_UND),
-/* 0111 1110 1010 */ TABDECL( OP_STRB_P_LSR_IMM_OFF_PREIND),
-/* 0111 1110 1011 */ TABDECL( OP_UND),
-/* 0111 1110 1100 */ TABDECL( OP_STRB_P_ASR_IMM_OFF_PREIND),
-/* 0111 1110 1101 */ TABDECL( OP_UND),
-/* 0111 1110 1110 */ TABDECL( OP_STRB_P_ROR_IMM_OFF_PREIND),
-/* 0111 1110 1111 */ TABDECL( OP_UND),
-/* 0111 1111 0000 */ TABDECL( OP_LDRB_P_LSL_IMM_OFF_PREIND),
-/* 0111 1111 0001 */ TABDECL( OP_UND),
-/* 0111 1111 0010 */ TABDECL( OP_LDRB_P_LSR_IMM_OFF_PREIND),
-/* 0111 1111 0011 */ TABDECL( OP_UND),
-/* 0111 1111 0100 */ TABDECL( OP_LDRB_P_ASR_IMM_OFF_PREIND),
-/* 0111 1111 0101 */ TABDECL( OP_UND),
-/* 0111 1111 0110 */ TABDECL( OP_LDRB_P_ROR_IMM_OFF_PREIND),
-/* 0111 1111 0111 */ TABDECL( OP_UND),
-/* 0111 1111 1000 */ TABDECL( OP_LDRB_P_LSL_IMM_OFF_PREIND),
-/* 0111 1111 1001 */ TABDECL( OP_UND),
-/* 0111 1111 1010 */ TABDECL( OP_LDRB_P_LSR_IMM_OFF_PREIND),
-/* 0111 1111 1011 */ TABDECL( OP_UND),
-/* 0111 1111 1100 */ TABDECL( OP_LDRB_P_ASR_IMM_OFF_PREIND),
-/* 0111 1111 1101 */ TABDECL( OP_UND),
-/* 0111 1111 1110 */ TABDECL( OP_LDRB_P_ROR_IMM_OFF_PREIND),
-/* 0111 1111 1111 */ TABDECL( OP_UND),
-/* 1000 0000 0000 */ TABDECL( OP_STMDA),
-/* 1000 0000 0001 */ TABDECL( OP_STMDA),
-/* 1000 0000 0010 */ TABDECL( OP_STMDA),
-/* 1000 0000 0011 */ TABDECL( OP_STMDA),
-/* 1000 0000 0100 */ TABDECL( OP_STMDA),
-/* 1000 0000 0101 */ TABDECL( OP_STMDA),
-/* 1000 0000 0110 */ TABDECL( OP_STMDA),
-/* 1000 0000 0111 */ TABDECL( OP_STMDA),
-/* 1000 0000 1000 */ TABDECL( OP_STMDA),
-/* 1000 0000 1001 */ TABDECL( OP_STMDA),
-/* 1000 0000 1010 */ TABDECL( OP_STMDA),
-/* 1000 0000 1011 */ TABDECL( OP_STMDA),
-/* 1000 0000 1100 */ TABDECL( OP_STMDA),
-/* 1000 0000 1101 */ TABDECL( OP_STMDA),
-/* 1000 0000 1110 */ TABDECL( OP_STMDA),
-/* 1000 0000 1111 */ TABDECL( OP_STMDA),
-/* 1000 0001 0000 */ TABDECL( OP_LDMDA),
-/* 1000 0001 0001 */ TABDECL( OP_LDMDA),
-/* 1000 0001 0010 */ TABDECL( OP_LDMDA),
-/* 1000 0001 0011 */ TABDECL( OP_LDMDA),
-/* 1000 0001 0100 */ TABDECL( OP_LDMDA),
-/* 1000 0001 0101 */ TABDECL( OP_LDMDA),
-/* 1000 0001 0110 */ TABDECL( OP_LDMDA),
-/* 1000 0001 0111 */ TABDECL( OP_LDMDA),
-/* 1000 0001 1000 */ TABDECL( OP_LDMDA),
-/* 1000 0001 1001 */ TABDECL( OP_LDMDA),
-/* 1000 0001 1010 */ TABDECL( OP_LDMDA),
-/* 1000 0001 1011 */ TABDECL( OP_LDMDA),
-/* 1000 0001 1100 */ TABDECL( OP_LDMDA),
-/* 1000 0001 1101 */ TABDECL( OP_LDMDA),
-/* 1000 0001 1110 */ TABDECL( OP_LDMDA),
-/* 1000 0001 1111 */ TABDECL( OP_LDMDA),
-/* 1000 0010 0000 */ TABDECL( OP_STMDA_W),
-/* 1000 0010 0001 */ TABDECL( OP_STMDA_W),
-/* 1000 0010 0010 */ TABDECL( OP_STMDA_W),
-/* 1000 0010 0011 */ TABDECL( OP_STMDA_W),
-/* 1000 0010 0100 */ TABDECL( OP_STMDA_W),
-/* 1000 0010 0101 */ TABDECL( OP_STMDA_W),
-/* 1000 0010 0110 */ TABDECL( OP_STMDA_W),
-/* 1000 0010 0111 */ TABDECL( OP_STMDA_W),
-/* 1000 0010 1000 */ TABDECL( OP_STMDA_W),
-/* 1000 0010 1001 */ TABDECL( OP_STMDA_W),
-/* 1000 0010 1010 */ TABDECL( OP_STMDA_W),
-/* 1000 0010 1011 */ TABDECL( OP_STMDA_W),
-/* 1000 0010 1100 */ TABDECL( OP_STMDA_W),
-/* 1000 0010 1101 */ TABDECL( OP_STMDA_W),
-/* 1000 0010 1110 */ TABDECL( OP_STMDA_W),
-/* 1000 0010 1111 */ TABDECL( OP_STMDA_W),
-/* 1000 0011 0000 */ TABDECL( OP_LDMDA_W),
-/* 1000 0011 0001 */ TABDECL( OP_LDMDA_W),
-/* 1000 0011 0010 */ TABDECL( OP_LDMDA_W),
-/* 1000 0011 0011 */ TABDECL( OP_LDMDA_W),
-/* 1000 0011 0100 */ TABDECL( OP_LDMDA_W),
-/* 1000 0011 0101 */ TABDECL( OP_LDMDA_W),
-/* 1000 0011 0110 */ TABDECL( OP_LDMDA_W),
-/* 1000 0011 0111 */ TABDECL( OP_LDMDA_W),
-/* 1000 0011 1000 */ TABDECL( OP_LDMDA_W),
-/* 1000 0011 1001 */ TABDECL( OP_LDMDA_W),
-/* 1000 0011 1010 */ TABDECL( OP_LDMDA_W),
-/* 1000 0011 1011 */ TABDECL( OP_LDMDA_W),
-/* 1000 0011 1100 */ TABDECL( OP_LDMDA_W),
-/* 1000 0011 1101 */ TABDECL( OP_LDMDA_W),
-/* 1000 0011 1110 */ TABDECL( OP_LDMDA_W),
-/* 1000 0011 1111 */ TABDECL( OP_LDMDA_W),
-/* 1000 0100 0000 */ TABDECL( OP_STMDA2),
-/* 1000 0100 0001 */ TABDECL( OP_STMDA2),
-/* 1000 0100 0010 */ TABDECL( OP_STMDA2),
-/* 1000 0100 0011 */ TABDECL( OP_STMDA2),
-/* 1000 0100 0100 */ TABDECL( OP_STMDA2),
-/* 1000 0100 0101 */ TABDECL( OP_STMDA2),
-/* 1000 0100 0110 */ TABDECL( OP_STMDA2),
-/* 1000 0100 0111 */ TABDECL( OP_STMDA2),
-/* 1000 0100 1000 */ TABDECL( OP_STMDA2),
-/* 1000 0100 1001 */ TABDECL( OP_STMDA2),
-/* 1000 0100 1010 */ TABDECL( OP_STMDA2),
-/* 1000 0100 1011 */ TABDECL( OP_STMDA2),
-/* 1000 0100 1100 */ TABDECL( OP_STMDA2),
-/* 1000 0100 1101 */ TABDECL( OP_STMDA2),
-/* 1000 0100 1110 */ TABDECL( OP_STMDA2),
-/* 1000 0100 1111 */ TABDECL( OP_STMDA2),
-/* 1000 0101 0000 */ TABDECL( OP_LDMDA2),
-/* 1000 0101 0001 */ TABDECL( OP_LDMDA2),
-/* 1000 0101 0010 */ TABDECL( OP_LDMDA2),
-/* 1000 0101 0011 */ TABDECL( OP_LDMDA2),
-/* 1000 0101 0100 */ TABDECL( OP_LDMDA2),
-/* 1000 0101 0101 */ TABDECL( OP_LDMDA2),
-/* 1000 0101 0110 */ TABDECL( OP_LDMDA2),
-/* 1000 0101 0111 */ TABDECL( OP_LDMDA2),
-/* 1000 0101 1000 */ TABDECL( OP_LDMDA2),
-/* 1000 0101 1001 */ TABDECL( OP_LDMDA2),
-/* 1000 0101 1010 */ TABDECL( OP_LDMDA2),
-/* 1000 0101 1011 */ TABDECL( OP_LDMDA2),
-/* 1000 0101 1100 */ TABDECL( OP_LDMDA2),
-/* 1000 0101 1101 */ TABDECL( OP_LDMDA2),
-/* 1000 0101 1110 */ TABDECL( OP_LDMDA2),
-/* 1000 0101 1111 */ TABDECL( OP_LDMDA2),
-/* 1000 0110 0000 */ TABDECL( OP_STMDA2_W),
-/* 1000 0110 0001 */ TABDECL( OP_STMDA2_W),
-/* 1000 0110 0010 */ TABDECL( OP_STMDA2_W),
-/* 1000 0110 0011 */ TABDECL( OP_STMDA2_W),
-/* 1000 0110 0100 */ TABDECL( OP_STMDA2_W),
-/* 1000 0110 0101 */ TABDECL( OP_STMDA2_W),
-/* 1000 0110 0110 */ TABDECL( OP_STMDA2_W),
-/* 1000 0110 0111 */ TABDECL( OP_STMDA2_W),
-/* 1000 0110 1000 */ TABDECL( OP_STMDA2_W),
-/* 1000 0110 1001 */ TABDECL( OP_STMDA2_W),
-/* 1000 0110 1010 */ TABDECL( OP_STMDA2_W),
-/* 1000 0110 1011 */ TABDECL( OP_STMDA2_W),
-/* 1000 0110 1100 */ TABDECL( OP_STMDA2_W),
-/* 1000 0110 1101 */ TABDECL( OP_STMDA2_W),
-/* 1000 0110 1110 */ TABDECL( OP_STMDA2_W),
-/* 1000 0110 1111 */ TABDECL( OP_STMDA2_W),
-/* 1000 0111 0000 */ TABDECL( OP_LDMDA2_W),
-/* 1000 0111 0001 */ TABDECL( OP_LDMDA2_W),
-/* 1000 0111 0010 */ TABDECL( OP_LDMDA2_W),
-/* 1000 0111 0011 */ TABDECL( OP_LDMDA2_W),
-/* 1000 0111 0100 */ TABDECL( OP_LDMDA2_W),
-/* 1000 0111 0101 */ TABDECL( OP_LDMDA2_W),
-/* 1000 0111 0110 */ TABDECL( OP_LDMDA2_W),
-/* 1000 0111 0111 */ TABDECL( OP_LDMDA2_W),
-/* 1000 0111 1000 */ TABDECL( OP_LDMDA2_W),
-/* 1000 0111 1001 */ TABDECL( OP_LDMDA2_W),
-/* 1000 0111 1010 */ TABDECL( OP_LDMDA2_W),
-/* 1000 0111 1011 */ TABDECL( OP_LDMDA2_W),
-/* 1000 0111 1100 */ TABDECL( OP_LDMDA2_W),
-/* 1000 0111 1101 */ TABDECL( OP_LDMDA2_W),
-/* 1000 0111 1110 */ TABDECL( OP_LDMDA2_W),
-/* 1000 0111 1111 */ TABDECL( OP_LDMDA2_W),
-/* 1000 1000 0000 */ TABDECL( OP_STMIA),
-/* 1000 1000 0001 */ TABDECL( OP_STMIA),
-/* 1000 1000 0010 */ TABDECL( OP_STMIA),
-/* 1000 1000 0011 */ TABDECL( OP_STMIA),
-/* 1000 1000 0100 */ TABDECL( OP_STMIA),
-/* 1000 1000 0101 */ TABDECL( OP_STMIA),
-/* 1000 1000 0110 */ TABDECL( OP_STMIA),
-/* 1000 1000 0111 */ TABDECL( OP_STMIA),
-/* 1000 1000 1000 */ TABDECL( OP_STMIA),
-/* 1000 1000 1001 */ TABDECL( OP_STMIA),
-/* 1000 1000 1010 */ TABDECL( OP_STMIA),
-/* 1000 1000 1011 */ TABDECL( OP_STMIA),
-/* 1000 1000 1100 */ TABDECL( OP_STMIA),
-/* 1000 1000 1101 */ TABDECL( OP_STMIA),
-/* 1000 1000 1110 */ TABDECL( OP_STMIA),
-/* 1000 1000 1111 */ TABDECL( OP_STMIA),
-/* 1000 1001 0000 */ TABDECL( OP_LDMIA),
-/* 1000 1001 0001 */ TABDECL( OP_LDMIA),
-/* 1000 1001 0010 */ TABDECL( OP_LDMIA),
-/* 1000 1001 0011 */ TABDECL( OP_LDMIA),
-/* 1000 1001 0100 */ TABDECL( OP_LDMIA),
-/* 1000 1001 0101 */ TABDECL( OP_LDMIA),
-/* 1000 1001 0110 */ TABDECL( OP_LDMIA),
-/* 1000 1001 0111 */ TABDECL( OP_LDMIA),
-/* 1000 1001 1000 */ TABDECL( OP_LDMIA),
-/* 1000 1001 1001 */ TABDECL( OP_LDMIA),
-/* 1000 1001 1010 */ TABDECL( OP_LDMIA),
-/* 1000 1001 1011 */ TABDECL( OP_LDMIA),
-/* 1000 1001 1100 */ TABDECL( OP_LDMIA),
-/* 1000 1001 1101 */ TABDECL( OP_LDMIA),
-/* 1000 1001 1110 */ TABDECL( OP_LDMIA),
-/* 1000 1001 1111 */ TABDECL( OP_LDMIA),
-/* 1000 1010 0000 */ TABDECL( OP_STMIA_W),
-/* 1000 1010 0001 */ TABDECL( OP_STMIA_W),
-/* 1000 1010 0010 */ TABDECL( OP_STMIA_W),
-/* 1000 1010 0011 */ TABDECL( OP_STMIA_W),
-/* 1000 1010 0100 */ TABDECL( OP_STMIA_W),
-/* 1000 1010 0101 */ TABDECL( OP_STMIA_W),
-/* 1000 1010 0110 */ TABDECL( OP_STMIA_W),
-/* 1000 1010 0111 */ TABDECL( OP_STMIA_W),
-/* 1000 1010 1000 */ TABDECL( OP_STMIA_W),
-/* 1000 1010 1001 */ TABDECL( OP_STMIA_W),
-/* 1000 1010 1010 */ TABDECL( OP_STMIA_W),
-/* 1000 1010 1011 */ TABDECL( OP_STMIA_W),
-/* 1000 1010 1100 */ TABDECL( OP_STMIA_W),
-/* 1000 1010 1101 */ TABDECL( OP_STMIA_W),
-/* 1000 1010 1110 */ TABDECL( OP_STMIA_W),
-/* 1000 1010 1111 */ TABDECL( OP_STMIA_W),
-/* 1000 1011 0000 */ TABDECL( OP_LDMIA_W),
-/* 1000 1011 0001 */ TABDECL( OP_LDMIA_W),
-/* 1000 1011 0010 */ TABDECL( OP_LDMIA_W),
-/* 1000 1011 0011 */ TABDECL( OP_LDMIA_W),
-/* 1000 1011 0100 */ TABDECL( OP_LDMIA_W),
-/* 1000 1011 0101 */ TABDECL( OP_LDMIA_W),
-/* 1000 1011 0110 */ TABDECL( OP_LDMIA_W),
-/* 1000 1011 0111 */ TABDECL( OP_LDMIA_W),
-/* 1000 1011 1000 */ TABDECL( OP_LDMIA_W),
-/* 1000 1011 1001 */ TABDECL( OP_LDMIA_W),
-/* 1000 1011 1010 */ TABDECL( OP_LDMIA_W),
-/* 1000 1011 1011 */ TABDECL( OP_LDMIA_W),
-/* 1000 1011 1100 */ TABDECL( OP_LDMIA_W),
-/* 1000 1011 1101 */ TABDECL( OP_LDMIA_W),
-/* 1000 1011 1110 */ TABDECL( OP_LDMIA_W),
-/* 1000 1011 1111 */ TABDECL( OP_LDMIA_W),
-/* 1000 1100 0000 */ TABDECL( OP_STMIA2),
-/* 1000 1100 0001 */ TABDECL( OP_STMIA2),
-/* 1000 1100 0010 */ TABDECL( OP_STMIA2),
-/* 1000 1100 0011 */ TABDECL( OP_STMIA2),
-/* 1000 1100 0100 */ TABDECL( OP_STMIA2),
-/* 1000 1100 0101 */ TABDECL( OP_STMIA2),
-/* 1000 1100 0110 */ TABDECL( OP_STMIA2),
-/* 1000 1100 0111 */ TABDECL( OP_STMIA2),
-/* 1000 1100 1000 */ TABDECL( OP_STMIA2),
-/* 1000 1100 1001 */ TABDECL( OP_STMIA2),
-/* 1000 1100 1010 */ TABDECL( OP_STMIA2),
-/* 1000 1100 1011 */ TABDECL( OP_STMIA2),
-/* 1000 1100 1100 */ TABDECL( OP_STMIA2),
-/* 1000 1100 1101 */ TABDECL( OP_STMIA2),
-/* 1000 1100 1110 */ TABDECL( OP_STMIA2),
-/* 1000 1100 1111 */ TABDECL( OP_STMIA2),
-/* 1000 1101 0000 */ TABDECL( OP_LDMIA2),
-/* 1000 1101 0001 */ TABDECL( OP_LDMIA2),
-/* 1000 1101 0010 */ TABDECL( OP_LDMIA2),
-/* 1000 1101 0011 */ TABDECL( OP_LDMIA2),
-/* 1000 1101 0100 */ TABDECL( OP_LDMIA2),
-/* 1000 1101 0101 */ TABDECL( OP_LDMIA2),
-/* 1000 1101 0110 */ TABDECL( OP_LDMIA2),
-/* 1000 1101 0111 */ TABDECL( OP_LDMIA2),
-/* 1000 1101 1000 */ TABDECL( OP_LDMIA2),
-/* 1000 1101 1001 */ TABDECL( OP_LDMIA2),
-/* 1000 1101 1010 */ TABDECL( OP_LDMIA2),
-/* 1000 1101 1011 */ TABDECL( OP_LDMIA2),
-/* 1000 1101 1100 */ TABDECL( OP_LDMIA2),
-/* 1000 1101 1101 */ TABDECL( OP_LDMIA2),
-/* 1000 1101 1110 */ TABDECL( OP_LDMIA2),
-/* 1000 1101 1111 */ TABDECL( OP_LDMIA2),
-/* 1000 1110 0000 */ TABDECL( OP_STMIA2_W),
-/* 1000 1110 0001 */ TABDECL( OP_STMIA2_W),
-/* 1000 1110 0010 */ TABDECL( OP_STMIA2_W),
-/* 1000 1110 0011 */ TABDECL( OP_STMIA2_W),
-/* 1000 1110 0100 */ TABDECL( OP_STMIA2_W),
-/* 1000 1110 0101 */ TABDECL( OP_STMIA2_W),
-/* 1000 1110 0110 */ TABDECL( OP_STMIA2_W),
-/* 1000 1110 0111 */ TABDECL( OP_STMIA2_W),
-/* 1000 1110 1000 */ TABDECL( OP_STMIA2_W),
-/* 1000 1110 1001 */ TABDECL( OP_STMIA2_W),
-/* 1000 1110 1010 */ TABDECL( OP_STMIA2_W),
-/* 1000 1110 1011 */ TABDECL( OP_STMIA2_W),
-/* 1000 1110 1100 */ TABDECL( OP_STMIA2_W),
-/* 1000 1110 1101 */ TABDECL( OP_STMIA2_W),
-/* 1000 1110 1110 */ TABDECL( OP_STMIA2_W),
-/* 1000 1110 1111 */ TABDECL( OP_STMIA2_W),
-/* 1000 1111 0000 */ TABDECL( OP_LDMIA2_W),
-/* 1000 1111 0001 */ TABDECL( OP_LDMIA2_W),
-/* 1000 1111 0010 */ TABDECL( OP_LDMIA2_W),
-/* 1000 1111 0011 */ TABDECL( OP_LDMIA2_W),
-/* 1000 1111 0100 */ TABDECL( OP_LDMIA2_W),
-/* 1000 1111 0101 */ TABDECL( OP_LDMIA2_W),
-/* 1000 1111 0110 */ TABDECL( OP_LDMIA2_W),
-/* 1000 1111 0111 */ TABDECL( OP_LDMIA2_W),
-/* 1000 1111 1000 */ TABDECL( OP_LDMIA2_W),
-/* 1000 1111 1001 */ TABDECL( OP_LDMIA2_W),
-/* 1000 1111 1010 */ TABDECL( OP_LDMIA2_W),
-/* 1000 1111 1011 */ TABDECL( OP_LDMIA2_W),
-/* 1000 1111 1100 */ TABDECL( OP_LDMIA2_W),
-/* 1000 1111 1101 */ TABDECL( OP_LDMIA2_W),
-/* 1000 1111 1110 */ TABDECL( OP_LDMIA2_W),
-/* 1000 1111 1111 */ TABDECL( OP_LDMIA2_W),
-/* 1001 0000 0000 */ TABDECL( OP_STMDB),
-/* 1001 0000 0001 */ TABDECL( OP_STMDB),
-/* 1001 0000 0010 */ TABDECL( OP_STMDB),
-/* 1001 0000 0011 */ TABDECL( OP_STMDB),
-/* 1001 0000 0100 */ TABDECL( OP_STMDB),
-/* 1001 0000 0101 */ TABDECL( OP_STMDB),
-/* 1001 0000 0110 */ TABDECL( OP_STMDB),
-/* 1001 0000 0111 */ TABDECL( OP_STMDB),
-/* 1001 0000 1000 */ TABDECL( OP_STMDB),
-/* 1001 0000 1001 */ TABDECL( OP_STMDB),
-/* 1001 0000 1010 */ TABDECL( OP_STMDB),
-/* 1001 0000 1011 */ TABDECL( OP_STMDB),
-/* 1001 0000 1100 */ TABDECL( OP_STMDB),
-/* 1001 0000 1101 */ TABDECL( OP_STMDB),
-/* 1001 0000 1110 */ TABDECL( OP_STMDB),
-/* 1001 0000 1111 */ TABDECL( OP_STMDB),
-/* 1001 0001 0000 */ TABDECL( OP_LDMDB),
-/* 1001 0001 0001 */ TABDECL( OP_LDMDB),
-/* 1001 0001 0010 */ TABDECL( OP_LDMDB),
-/* 1001 0001 0011 */ TABDECL( OP_LDMDB),
-/* 1001 0001 0100 */ TABDECL( OP_LDMDB),
-/* 1001 0001 0101 */ TABDECL( OP_LDMDB),
-/* 1001 0001 0110 */ TABDECL( OP_LDMDB),
-/* 1001 0001 0111 */ TABDECL( OP_LDMDB),
-/* 1001 0001 1000 */ TABDECL( OP_LDMDB),
-/* 1001 0001 1001 */ TABDECL( OP_LDMDB),
-/* 1001 0001 1010 */ TABDECL( OP_LDMDB),
-/* 1001 0001 1011 */ TABDECL( OP_LDMDB),
-/* 1001 0001 1100 */ TABDECL( OP_LDMDB),
-/* 1001 0001 1101 */ TABDECL( OP_LDMDB),
-/* 1001 0001 1110 */ TABDECL( OP_LDMDB),
-/* 1001 0001 1111 */ TABDECL( OP_LDMDB),
-/* 1001 0010 0000 */ TABDECL( OP_STMDB_W),
-/* 1001 0010 0001 */ TABDECL( OP_STMDB_W),
-/* 1001 0010 0010 */ TABDECL( OP_STMDB_W),
-/* 1001 0010 0011 */ TABDECL( OP_STMDB_W),
-/* 1001 0010 0100 */ TABDECL( OP_STMDB_W),
-/* 1001 0010 0101 */ TABDECL( OP_STMDB_W),
-/* 1001 0010 0110 */ TABDECL( OP_STMDB_W),
-/* 1001 0010 0111 */ TABDECL( OP_STMDB_W),
-/* 1001 0010 1000 */ TABDECL( OP_STMDB_W),
-/* 1001 0010 1001 */ TABDECL( OP_STMDB_W),
-/* 1001 0010 1010 */ TABDECL( OP_STMDB_W),
-/* 1001 0010 1011 */ TABDECL( OP_STMDB_W),
-/* 1001 0010 1100 */ TABDECL( OP_STMDB_W),
-/* 1001 0010 1101 */ TABDECL( OP_STMDB_W),
-/* 1001 0010 1110 */ TABDECL( OP_STMDB_W),
-/* 1001 0010 1111 */ TABDECL( OP_STMDB_W),
-/* 1001 0011 0000 */ TABDECL( OP_LDMDB_W),
-/* 1001 0011 0001 */ TABDECL( OP_LDMDB_W),
-/* 1001 0011 0010 */ TABDECL( OP_LDMDB_W),
-/* 1001 0011 0011 */ TABDECL( OP_LDMDB_W),
-/* 1001 0011 0100 */ TABDECL( OP_LDMDB_W),
-/* 1001 0011 0101 */ TABDECL( OP_LDMDB_W),
-/* 1001 0011 0110 */ TABDECL( OP_LDMDB_W),
-/* 1001 0011 0111 */ TABDECL( OP_LDMDB_W),
-/* 1001 0011 1000 */ TABDECL( OP_LDMDB_W),
-/* 1001 0011 1001 */ TABDECL( OP_LDMDB_W),
-/* 1001 0011 1010 */ TABDECL( OP_LDMDB_W),
-/* 1001 0011 1011 */ TABDECL( OP_LDMDB_W),
-/* 1001 0011 1100 */ TABDECL( OP_LDMDB_W),
-/* 1001 0011 1101 */ TABDECL( OP_LDMDB_W),
-/* 1001 0011 1110 */ TABDECL( OP_LDMDB_W),
-/* 1001 0011 1111 */ TABDECL( OP_LDMDB_W),
-/* 1001 0100 0000 */ TABDECL( OP_STMDB2),
-/* 1001 0100 0001 */ TABDECL( OP_STMDB2),
-/* 1001 0100 0010 */ TABDECL( OP_STMDB2),
-/* 1001 0100 0011 */ TABDECL( OP_STMDB2),
-/* 1001 0100 0100 */ TABDECL( OP_STMDB2),
-/* 1001 0100 0101 */ TABDECL( OP_STMDB2),
-/* 1001 0100 0110 */ TABDECL( OP_STMDB2),
-/* 1001 0100 0111 */ TABDECL( OP_STMDB2),
-/* 1001 0100 1000 */ TABDECL( OP_STMDB2),
-/* 1001 0100 1001 */ TABDECL( OP_STMDB2),
-/* 1001 0100 1010 */ TABDECL( OP_STMDB2),
-/* 1001 0100 1011 */ TABDECL( OP_STMDB2),
-/* 1001 0100 1100 */ TABDECL( OP_STMDB2),
-/* 1001 0100 1101 */ TABDECL( OP_STMDB2),
-/* 1001 0100 1110 */ TABDECL( OP_STMDB2),
-/* 1001 0100 1111 */ TABDECL( OP_STMDB2),
-/* 1001 0101 0000 */ TABDECL( OP_LDMDB2),
-/* 1001 0101 0001 */ TABDECL( OP_LDMDB2),
-/* 1001 0101 0010 */ TABDECL( OP_LDMDB2),
-/* 1001 0101 0011 */ TABDECL( OP_LDMDB2),
-/* 1001 0101 0100 */ TABDECL( OP_LDMDB2),
-/* 1001 0101 0101 */ TABDECL( OP_LDMDB2),
-/* 1001 0101 0110 */ TABDECL( OP_LDMDB2),
-/* 1001 0101 0111 */ TABDECL( OP_LDMDB2),
-/* 1001 0101 1000 */ TABDECL( OP_LDMDB2),
-/* 1001 0101 1001 */ TABDECL( OP_LDMDB2),
-/* 1001 0101 1010 */ TABDECL( OP_LDMDB2),
-/* 1001 0101 1011 */ TABDECL( OP_LDMDB2),
-/* 1001 0101 1100 */ TABDECL( OP_LDMDB2),
-/* 1001 0101 1101 */ TABDECL( OP_LDMDB2),
-/* 1001 0101 1110 */ TABDECL( OP_LDMDB2),
-/* 1001 0101 1111 */ TABDECL( OP_LDMDB2),
-/* 1001 0110 0000 */ TABDECL( OP_STMDB2_W),
-/* 1001 0110 0001 */ TABDECL( OP_STMDB2_W),
-/* 1001 0110 0010 */ TABDECL( OP_STMDB2_W),
-/* 1001 0110 0011 */ TABDECL( OP_STMDB2_W),
-/* 1001 0110 0100 */ TABDECL( OP_STMDB2_W),
-/* 1001 0110 0101 */ TABDECL( OP_STMDB2_W),
-/* 1001 0110 0110 */ TABDECL( OP_STMDB2_W),
-/* 1001 0110 0111 */ TABDECL( OP_STMDB2_W),
-/* 1001 0110 1000 */ TABDECL( OP_STMDB2_W),
-/* 1001 0110 1001 */ TABDECL( OP_STMDB2_W),
-/* 1001 0110 1010 */ TABDECL( OP_STMDB2_W),
-/* 1001 0110 1011 */ TABDECL( OP_STMDB2_W),
-/* 1001 0110 1100 */ TABDECL( OP_STMDB2_W),
-/* 1001 0110 1101 */ TABDECL( OP_STMDB2_W),
-/* 1001 0110 1110 */ TABDECL( OP_STMDB2_W),
-/* 1001 0110 1111 */ TABDECL( OP_STMDB2_W),
-/* 1001 0111 0000 */ TABDECL( OP_LDMDB2_W),
-/* 1001 0111 0001 */ TABDECL( OP_LDMDB2_W),
-/* 1001 0111 0010 */ TABDECL( OP_LDMDB2_W),
-/* 1001 0111 0011 */ TABDECL( OP_LDMDB2_W),
-/* 1001 0111 0100 */ TABDECL( OP_LDMDB2_W),
-/* 1001 0111 0101 */ TABDECL( OP_LDMDB2_W),
-/* 1001 0111 0110 */ TABDECL( OP_LDMDB2_W),
-/* 1001 0111 0111 */ TABDECL( OP_LDMDB2_W),
-/* 1001 0111 1000 */ TABDECL( OP_LDMDB2_W),
-/* 1001 0111 1001 */ TABDECL( OP_LDMDB2_W),
-/* 1001 0111 1010 */ TABDECL( OP_LDMDB2_W),
-/* 1001 0111 1011 */ TABDECL( OP_LDMDB2_W),
-/* 1001 0111 1100 */ TABDECL( OP_LDMDB2_W),
-/* 1001 0111 1101 */ TABDECL( OP_LDMDB2_W),
-/* 1001 0111 1110 */ TABDECL( OP_LDMDB2_W),
-/* 1001 0111 1111 */ TABDECL( OP_LDMDB2_W),
-/* 1001 1000 0000 */ TABDECL( OP_STMIB),
-/* 1001 1000 0001 */ TABDECL( OP_STMIB),
-/* 1001 1000 0010 */ TABDECL( OP_STMIB),
-/* 1001 1000 0011 */ TABDECL( OP_STMIB),
-/* 1001 1000 0100 */ TABDECL( OP_STMIB),
-/* 1001 1000 0101 */ TABDECL( OP_STMIB),
-/* 1001 1000 0110 */ TABDECL( OP_STMIB),
-/* 1001 1000 0111 */ TABDECL( OP_STMIB),
-/* 1001 1000 1000 */ TABDECL( OP_STMIB),
-/* 1001 1000 1001 */ TABDECL( OP_STMIB),
-/* 1001 1000 1010 */ TABDECL( OP_STMIB),
-/* 1001 1000 1011 */ TABDECL( OP_STMIB),
-/* 1001 1000 1100 */ TABDECL( OP_STMIB),
-/* 1001 1000 1101 */ TABDECL( OP_STMIB),
-/* 1001 1000 1110 */ TABDECL( OP_STMIB),
-/* 1001 1000 1111 */ TABDECL( OP_STMIB),
-/* 1001 1001 0000 */ TABDECL( OP_LDMIB),
-/* 1001 1001 0001 */ TABDECL( OP_LDMIB),
-/* 1001 1001 0010 */ TABDECL( OP_LDMIB),
-/* 1001 1001 0011 */ TABDECL( OP_LDMIB),
-/* 1001 1001 0100 */ TABDECL( OP_LDMIB),
-/* 1001 1001 0101 */ TABDECL( OP_LDMIB),
-/* 1001 1001 0110 */ TABDECL( OP_LDMIB),
-/* 1001 1001 0111 */ TABDECL( OP_LDMIB),
-/* 1001 1001 1000 */ TABDECL( OP_LDMIB),
-/* 1001 1001 1001 */ TABDECL( OP_LDMIB),
-/* 1001 1001 1010 */ TABDECL( OP_LDMIB),
-/* 1001 1001 1011 */ TABDECL( OP_LDMIB),
-/* 1001 1001 1100 */ TABDECL( OP_LDMIB),
-/* 1001 1001 1101 */ TABDECL( OP_LDMIB),
-/* 1001 1001 1110 */ TABDECL( OP_LDMIB),
-/* 1001 1001 1111 */ TABDECL( OP_LDMIB),
-/* 1001 1010 0000 */ TABDECL( OP_STMIB_W),
-/* 1001 1010 0001 */ TABDECL( OP_STMIB_W),
-/* 1001 1010 0010 */ TABDECL( OP_STMIB_W),
-/* 1001 1010 0011 */ TABDECL( OP_STMIB_W),
-/* 1001 1010 0100 */ TABDECL( OP_STMIB_W),
-/* 1001 1010 0101 */ TABDECL( OP_STMIB_W),
-/* 1001 1010 0110 */ TABDECL( OP_STMIB_W),
-/* 1001 1010 0111 */ TABDECL( OP_STMIB_W),
-/* 1001 1010 1000 */ TABDECL( OP_STMIB_W),
-/* 1001 1010 1001 */ TABDECL( OP_STMIB_W),
-/* 1001 1010 1010 */ TABDECL( OP_STMIB_W),
-/* 1001 1010 1011 */ TABDECL( OP_STMIB_W),
-/* 1001 1010 1100 */ TABDECL( OP_STMIB_W),
-/* 1001 1010 1101 */ TABDECL( OP_STMIB_W),
-/* 1001 1010 1110 */ TABDECL( OP_STMIB_W),
-/* 1001 1010 1111 */ TABDECL( OP_STMIB_W),
-/* 1001 1011 0000 */ TABDECL( OP_LDMIB_W),
-/* 1001 1011 0001 */ TABDECL( OP_LDMIB_W),
-/* 1001 1011 0010 */ TABDECL( OP_LDMIB_W),
-/* 1001 1011 0011 */ TABDECL( OP_LDMIB_W),
-/* 1001 1011 0100 */ TABDECL( OP_LDMIB_W),
-/* 1001 1011 0101 */ TABDECL( OP_LDMIB_W),
-/* 1001 1011 0110 */ TABDECL( OP_LDMIB_W),
-/* 1001 1011 0111 */ TABDECL( OP_LDMIB_W),
-/* 1001 1011 1000 */ TABDECL( OP_LDMIB_W),
-/* 1001 1011 1001 */ TABDECL( OP_LDMIB_W),
-/* 1001 1011 1010 */ TABDECL( OP_LDMIB_W),
-/* 1001 1011 1011 */ TABDECL( OP_LDMIB_W),
-/* 1001 1011 1100 */ TABDECL( OP_LDMIB_W),
-/* 1001 1011 1101 */ TABDECL( OP_LDMIB_W),
-/* 1001 1011 1110 */ TABDECL( OP_LDMIB_W),
-/* 1001 1011 1111 */ TABDECL( OP_LDMIB_W),
-/* 1001 1100 0000 */ TABDECL( OP_STMIB2),
-/* 1001 1100 0001 */ TABDECL( OP_STMIB2),
-/* 1001 1100 0010 */ TABDECL( OP_STMIB2),
-/* 1001 1100 0011 */ TABDECL( OP_STMIB2),
-/* 1001 1100 0100 */ TABDECL( OP_STMIB2),
-/* 1001 1100 0101 */ TABDECL( OP_STMIB2),
-/* 1001 1100 0110 */ TABDECL( OP_STMIB2),
-/* 1001 1100 0111 */ TABDECL( OP_STMIB2),
-/* 1001 1100 1000 */ TABDECL( OP_STMIB2),
-/* 1001 1100 1001 */ TABDECL( OP_STMIB2),
-/* 1001 1100 1010 */ TABDECL( OP_STMIB2),
-/* 1001 1100 1011 */ TABDECL( OP_STMIB2),
-/* 1001 1100 1100 */ TABDECL( OP_STMIB2),
-/* 1001 1100 1101 */ TABDECL( OP_STMIB2),
-/* 1001 1100 1110 */ TABDECL( OP_STMIB2),
-/* 1001 1100 1111 */ TABDECL( OP_STMIB2),
-/* 1001 1101 0000 */ TABDECL( OP_LDMIB2),
-/* 1001 1101 0001 */ TABDECL( OP_LDMIB2),
-/* 1001 1101 0010 */ TABDECL( OP_LDMIB2),
-/* 1001 1101 0011 */ TABDECL( OP_LDMIB2),
-/* 1001 1101 0100 */ TABDECL( OP_LDMIB2),
-/* 1001 1101 0101 */ TABDECL( OP_LDMIB2),
-/* 1001 1101 0110 */ TABDECL( OP_LDMIB2),
-/* 1001 1101 0111 */ TABDECL( OP_LDMIB2),
-/* 1001 1101 1000 */ TABDECL( OP_LDMIB2),
-/* 1001 1101 1001 */ TABDECL( OP_LDMIB2),
-/* 1001 1101 1010 */ TABDECL( OP_LDMIB2),
-/* 1001 1101 1011 */ TABDECL( OP_LDMIB2),
-/* 1001 1101 1100 */ TABDECL( OP_LDMIB2),
-/* 1001 1101 1101 */ TABDECL( OP_LDMIB2),
-/* 1001 1101 1110 */ TABDECL( OP_LDMIB2),
-/* 1001 1101 1111 */ TABDECL( OP_LDMIB2),
-/* 1001 1110 0000 */ TABDECL( OP_STMIB2_W),
-/* 1001 1110 0001 */ TABDECL( OP_STMIB2_W),
-/* 1001 1110 0010 */ TABDECL( OP_STMIB2_W),
-/* 1001 1110 0011 */ TABDECL( OP_STMIB2_W),
-/* 1001 1110 0100 */ TABDECL( OP_STMIB2_W),
-/* 1001 1110 0101 */ TABDECL( OP_STMIB2_W),
-/* 1001 1110 0110 */ TABDECL( OP_STMIB2_W),
-/* 1001 1110 0111 */ TABDECL( OP_STMIB2_W),
-/* 1001 1110 1000 */ TABDECL( OP_STMIB2_W),
-/* 1001 1110 1001 */ TABDECL( OP_STMIB2_W),
-/* 1001 1110 1010 */ TABDECL( OP_STMIB2_W),
-/* 1001 1110 1011 */ TABDECL( OP_STMIB2_W),
-/* 1001 1110 1100 */ TABDECL( OP_STMIB2_W),
-/* 1001 1110 1101 */ TABDECL( OP_STMIB2_W),
-/* 1001 1110 1110 */ TABDECL( OP_STMIB2_W),
-/* 1001 1110 1111 */ TABDECL( OP_STMIB2_W),
-/* 1001 1111 0000 */ TABDECL( OP_LDMIB2_W),
-/* 1001 1111 0001 */ TABDECL( OP_LDMIB2_W),
-/* 1001 1111 0010 */ TABDECL( OP_LDMIB2_W),
-/* 1001 1111 0011 */ TABDECL( OP_LDMIB2_W),
-/* 1001 1111 0100 */ TABDECL( OP_LDMIB2_W),
-/* 1001 1111 0101 */ TABDECL( OP_LDMIB2_W),
-/* 1001 1111 0110 */ TABDECL( OP_LDMIB2_W),
-/* 1001 1111 0111 */ TABDECL( OP_LDMIB2_W),
-/* 1001 1111 1000 */ TABDECL( OP_LDMIB2_W),
-/* 1001 1111 1001 */ TABDECL( OP_LDMIB2_W),
-/* 1001 1111 1010 */ TABDECL( OP_LDMIB2_W),
-/* 1001 1111 1011 */ TABDECL( OP_LDMIB2_W),
-/* 1001 1111 1100 */ TABDECL( OP_LDMIB2_W),
-/* 1001 1111 1101 */ TABDECL( OP_LDMIB2_W),
-/* 1001 1111 1110 */ TABDECL( OP_LDMIB2_W),
-/* 1001 1111 1111 */ TABDECL( OP_LDMIB2_W),
-/* 1010 0000 0000 */ TABDECL( OP_B),
-/* 1010 0000 0001 */ TABDECL( OP_B),
-/* 1010 0000 0010 */ TABDECL( OP_B),
-/* 1010 0000 0011 */ TABDECL( OP_B),
-/* 1010 0000 0100 */ TABDECL( OP_B),
-/* 1010 0000 0101 */ TABDECL( OP_B),
-/* 1010 0000 0110 */ TABDECL( OP_B),
-/* 1010 0000 0111 */ TABDECL( OP_B),
-/* 1010 0000 1000 */ TABDECL( OP_B),
-/* 1010 0000 1001 */ TABDECL( OP_B),
-/* 1010 0000 1010 */ TABDECL( OP_B),
-/* 1010 0000 1011 */ TABDECL( OP_B),
-/* 1010 0000 1100 */ TABDECL( OP_B),
-/* 1010 0000 1101 */ TABDECL( OP_B),
-/* 1010 0000 1110 */ TABDECL( OP_B),
-/* 1010 0000 1111 */ TABDECL( OP_B),
-/* 1010 0001 0000 */ TABDECL( OP_B),
-/* 1010 0001 0001 */ TABDECL( OP_B),
-/* 1010 0001 0010 */ TABDECL( OP_B),
-/* 1010 0001 0011 */ TABDECL( OP_B),
-/* 1010 0001 0100 */ TABDECL( OP_B),
-/* 1010 0001 0101 */ TABDECL( OP_B),
-/* 1010 0001 0110 */ TABDECL( OP_B),
-/* 1010 0001 0111 */ TABDECL( OP_B),
-/* 1010 0001 1000 */ TABDECL( OP_B),
-/* 1010 0001 1001 */ TABDECL( OP_B),
-/* 1010 0001 1010 */ TABDECL( OP_B),
-/* 1010 0001 1011 */ TABDECL( OP_B),
-/* 1010 0001 1100 */ TABDECL( OP_B),
-/* 1010 0001 1101 */ TABDECL( OP_B),
-/* 1010 0001 1110 */ TABDECL( OP_B),
-/* 1010 0001 1111 */ TABDECL( OP_B),
-/* 1010 0010 0000 */ TABDECL( OP_B),
-/* 1010 0010 0001 */ TABDECL( OP_B),
-/* 1010 0010 0010 */ TABDECL( OP_B),
-/* 1010 0010 0011 */ TABDECL( OP_B),
-/* 1010 0010 0100 */ TABDECL( OP_B),
-/* 1010 0010 0101 */ TABDECL( OP_B),
-/* 1010 0010 0110 */ TABDECL( OP_B),
-/* 1010 0010 0111 */ TABDECL( OP_B),
-/* 1010 0010 1000 */ TABDECL( OP_B),
-/* 1010 0010 1001 */ TABDECL( OP_B),
-/* 1010 0010 1010 */ TABDECL( OP_B),
-/* 1010 0010 1011 */ TABDECL( OP_B),
-/* 1010 0010 1100 */ TABDECL( OP_B),
-/* 1010 0010 1101 */ TABDECL( OP_B),
-/* 1010 0010 1110 */ TABDECL( OP_B),
-/* 1010 0010 1111 */ TABDECL( OP_B),
-/* 1010 0011 0000 */ TABDECL( OP_B),
-/* 1010 0011 0001 */ TABDECL( OP_B),
-/* 1010 0011 0010 */ TABDECL( OP_B),
-/* 1010 0011 0011 */ TABDECL( OP_B),
-/* 1010 0011 0100 */ TABDECL( OP_B),
-/* 1010 0011 0101 */ TABDECL( OP_B),
-/* 1010 0011 0110 */ TABDECL( OP_B),
-/* 1010 0011 0111 */ TABDECL( OP_B),
-/* 1010 0011 1000 */ TABDECL( OP_B),
-/* 1010 0011 1001 */ TABDECL( OP_B),
-/* 1010 0011 1010 */ TABDECL( OP_B),
-/* 1010 0011 1011 */ TABDECL( OP_B),
-/* 1010 0011 1100 */ TABDECL( OP_B),
-/* 1010 0011 1101 */ TABDECL( OP_B),
-/* 1010 0011 1110 */ TABDECL( OP_B),
-/* 1010 0011 1111 */ TABDECL( OP_B),
-/* 1010 0100 0000 */ TABDECL( OP_B),
-/* 1010 0100 0001 */ TABDECL( OP_B),
-/* 1010 0100 0010 */ TABDECL( OP_B),
-/* 1010 0100 0011 */ TABDECL( OP_B),
-/* 1010 0100 0100 */ TABDECL( OP_B),
-/* 1010 0100 0101 */ TABDECL( OP_B),
-/* 1010 0100 0110 */ TABDECL( OP_B),
-/* 1010 0100 0111 */ TABDECL( OP_B),
-/* 1010 0100 1000 */ TABDECL( OP_B),
-/* 1010 0100 1001 */ TABDECL( OP_B),
-/* 1010 0100 1010 */ TABDECL( OP_B),
-/* 1010 0100 1011 */ TABDECL( OP_B),
-/* 1010 0100 1100 */ TABDECL( OP_B),
-/* 1010 0100 1101 */ TABDECL( OP_B),
-/* 1010 0100 1110 */ TABDECL( OP_B),
-/* 1010 0100 1111 */ TABDECL( OP_B),
-/* 1010 0101 0000 */ TABDECL( OP_B),
-/* 1010 0101 0001 */ TABDECL( OP_B),
-/* 1010 0101 0010 */ TABDECL( OP_B),
-/* 1010 0101 0011 */ TABDECL( OP_B),
-/* 1010 0101 0100 */ TABDECL( OP_B),
-/* 1010 0101 0101 */ TABDECL( OP_B),
-/* 1010 0101 0110 */ TABDECL( OP_B),
-/* 1010 0101 0111 */ TABDECL( OP_B),
-/* 1010 0101 1000 */ TABDECL( OP_B),
-/* 1010 0101 1001 */ TABDECL( OP_B),
-/* 1010 0101 1010 */ TABDECL( OP_B),
-/* 1010 0101 1011 */ TABDECL( OP_B),
-/* 1010 0101 1100 */ TABDECL( OP_B),
-/* 1010 0101 1101 */ TABDECL( OP_B),
-/* 1010 0101 1110 */ TABDECL( OP_B),
-/* 1010 0101 1111 */ TABDECL( OP_B),
-/* 1010 0110 0000 */ TABDECL( OP_B),
-/* 1010 0110 0001 */ TABDECL( OP_B),
-/* 1010 0110 0010 */ TABDECL( OP_B),
-/* 1010 0110 0011 */ TABDECL( OP_B),
-/* 1010 0110 0100 */ TABDECL( OP_B),
-/* 1010 0110 0101 */ TABDECL( OP_B),
-/* 1010 0110 0110 */ TABDECL( OP_B),
-/* 1010 0110 0111 */ TABDECL( OP_B),
-/* 1010 0110 1000 */ TABDECL( OP_B),
-/* 1010 0110 1001 */ TABDECL( OP_B),
-/* 1010 0110 1010 */ TABDECL( OP_B),
-/* 1010 0110 1011 */ TABDECL( OP_B),
-/* 1010 0110 1100 */ TABDECL( OP_B),
-/* 1010 0110 1101 */ TABDECL( OP_B),
-/* 1010 0110 1110 */ TABDECL( OP_B),
-/* 1010 0110 1111 */ TABDECL( OP_B),
-/* 1010 0111 0000 */ TABDECL( OP_B),
-/* 1010 0111 0001 */ TABDECL( OP_B),
-/* 1010 0111 0010 */ TABDECL( OP_B),
-/* 1010 0111 0011 */ TABDECL( OP_B),
-/* 1010 0111 0100 */ TABDECL( OP_B),
-/* 1010 0111 0101 */ TABDECL( OP_B),
-/* 1010 0111 0110 */ TABDECL( OP_B),
-/* 1010 0111 0111 */ TABDECL( OP_B),
-/* 1010 0111 1000 */ TABDECL( OP_B),
-/* 1010 0111 1001 */ TABDECL( OP_B),
-/* 1010 0111 1010 */ TABDECL( OP_B),
-/* 1010 0111 1011 */ TABDECL( OP_B),
-/* 1010 0111 1100 */ TABDECL( OP_B),
-/* 1010 0111 1101 */ TABDECL( OP_B),
-/* 1010 0111 1110 */ TABDECL( OP_B),
-/* 1010 0111 1111 */ TABDECL( OP_B),
-/* 1010 1000 0000 */ TABDECL( OP_B),
-/* 1010 1000 0001 */ TABDECL( OP_B),
-/* 1010 1000 0010 */ TABDECL( OP_B),
-/* 1010 1000 0011 */ TABDECL( OP_B),
-/* 1010 1000 0100 */ TABDECL( OP_B),
-/* 1010 1000 0101 */ TABDECL( OP_B),
-/* 1010 1000 0110 */ TABDECL( OP_B),
-/* 1010 1000 0111 */ TABDECL( OP_B),
-/* 1010 1000 1000 */ TABDECL( OP_B),
-/* 1010 1000 1001 */ TABDECL( OP_B),
-/* 1010 1000 1010 */ TABDECL( OP_B),
-/* 1010 1000 1011 */ TABDECL( OP_B),
-/* 1010 1000 1100 */ TABDECL( OP_B),
-/* 1010 1000 1101 */ TABDECL( OP_B),
-/* 1010 1000 1110 */ TABDECL( OP_B),
-/* 1010 1000 1111 */ TABDECL( OP_B),
-/* 1010 1001 0000 */ TABDECL( OP_B),
-/* 1010 1001 0001 */ TABDECL( OP_B),
-/* 1010 1001 0010 */ TABDECL( OP_B),
-/* 1010 1001 0011 */ TABDECL( OP_B),
-/* 1010 1001 0100 */ TABDECL( OP_B),
-/* 1010 1001 0101 */ TABDECL( OP_B),
-/* 1010 1001 0110 */ TABDECL( OP_B),
-/* 1010 1001 0111 */ TABDECL( OP_B),
-/* 1010 1001 1000 */ TABDECL( OP_B),
-/* 1010 1001 1001 */ TABDECL( OP_B),
-/* 1010 1001 1010 */ TABDECL( OP_B),
-/* 1010 1001 1011 */ TABDECL( OP_B),
-/* 1010 1001 1100 */ TABDECL( OP_B),
-/* 1010 1001 1101 */ TABDECL( OP_B),
-/* 1010 1001 1110 */ TABDECL( OP_B),
-/* 1010 1001 1111 */ TABDECL( OP_B),
-/* 1010 1010 0000 */ TABDECL( OP_B),
-/* 1010 1010 0001 */ TABDECL( OP_B),
-/* 1010 1010 0010 */ TABDECL( OP_B),
-/* 1010 1010 0011 */ TABDECL( OP_B),
-/* 1010 1010 0100 */ TABDECL( OP_B),
-/* 1010 1010 0101 */ TABDECL( OP_B),
-/* 1010 1010 0110 */ TABDECL( OP_B),
-/* 1010 1010 0111 */ TABDECL( OP_B),
-/* 1010 1010 1000 */ TABDECL( OP_B),
-/* 1010 1010 1001 */ TABDECL( OP_B),
-/* 1010 1010 1010 */ TABDECL( OP_B),
-/* 1010 1010 1011 */ TABDECL( OP_B),
-/* 1010 1010 1100 */ TABDECL( OP_B),
-/* 1010 1010 1101 */ TABDECL( OP_B),
-/* 1010 1010 1110 */ TABDECL( OP_B),
-/* 1010 1010 1111 */ TABDECL( OP_B),
-/* 1010 1011 0000 */ TABDECL( OP_B),
-/* 1010 1011 0001 */ TABDECL( OP_B),
-/* 1010 1011 0010 */ TABDECL( OP_B),
-/* 1010 1011 0011 */ TABDECL( OP_B),
-/* 1010 1011 0100 */ TABDECL( OP_B),
-/* 1010 1011 0101 */ TABDECL( OP_B),
-/* 1010 1011 0110 */ TABDECL( OP_B),
-/* 1010 1011 0111 */ TABDECL( OP_B),
-/* 1010 1011 1000 */ TABDECL( OP_B),
-/* 1010 1011 1001 */ TABDECL( OP_B),
-/* 1010 1011 1010 */ TABDECL( OP_B),
-/* 1010 1011 1011 */ TABDECL( OP_B),
-/* 1010 1011 1100 */ TABDECL( OP_B),
-/* 1010 1011 1101 */ TABDECL( OP_B),
-/* 1010 1011 1110 */ TABDECL( OP_B),
-/* 1010 1011 1111 */ TABDECL( OP_B),
-/* 1010 1100 0000 */ TABDECL( OP_B),
-/* 1010 1100 0001 */ TABDECL( OP_B),
-/* 1010 1100 0010 */ TABDECL( OP_B),
-/* 1010 1100 0011 */ TABDECL( OP_B),
-/* 1010 1100 0100 */ TABDECL( OP_B),
-/* 1010 1100 0101 */ TABDECL( OP_B),
-/* 1010 1100 0110 */ TABDECL( OP_B),
-/* 1010 1100 0111 */ TABDECL( OP_B),
-/* 1010 1100 1000 */ TABDECL( OP_B),
-/* 1010 1100 1001 */ TABDECL( OP_B),
-/* 1010 1100 1010 */ TABDECL( OP_B),
-/* 1010 1100 1011 */ TABDECL( OP_B),
-/* 1010 1100 1100 */ TABDECL( OP_B),
-/* 1010 1100 1101 */ TABDECL( OP_B),
-/* 1010 1100 1110 */ TABDECL( OP_B),
-/* 1010 1100 1111 */ TABDECL( OP_B),
-/* 1010 1101 0000 */ TABDECL( OP_B),
-/* 1010 1101 0001 */ TABDECL( OP_B),
-/* 1010 1101 0010 */ TABDECL( OP_B),
-/* 1010 1101 0011 */ TABDECL( OP_B),
-/* 1010 1101 0100 */ TABDECL( OP_B),
-/* 1010 1101 0101 */ TABDECL( OP_B),
-/* 1010 1101 0110 */ TABDECL( OP_B),
-/* 1010 1101 0111 */ TABDECL( OP_B),
-/* 1010 1101 1000 */ TABDECL( OP_B),
-/* 1010 1101 1001 */ TABDECL( OP_B),
-/* 1010 1101 1010 */ TABDECL( OP_B),
-/* 1010 1101 1011 */ TABDECL( OP_B),
-/* 1010 1101 1100 */ TABDECL( OP_B),
-/* 1010 1101 1101 */ TABDECL( OP_B),
-/* 1010 1101 1110 */ TABDECL( OP_B),
-/* 1010 1101 1111 */ TABDECL( OP_B),
-/* 1010 1110 0000 */ TABDECL( OP_B),
-/* 1010 1110 0001 */ TABDECL( OP_B),
-/* 1010 1110 0010 */ TABDECL( OP_B),
-/* 1010 1110 0011 */ TABDECL( OP_B),
-/* 1010 1110 0100 */ TABDECL( OP_B),
-/* 1010 1110 0101 */ TABDECL( OP_B),
-/* 1010 1110 0110 */ TABDECL( OP_B),
-/* 1010 1110 0111 */ TABDECL( OP_B),
-/* 1010 1110 1000 */ TABDECL( OP_B),
-/* 1010 1110 1001 */ TABDECL( OP_B),
-/* 1010 1110 1010 */ TABDECL( OP_B),
-/* 1010 1110 1011 */ TABDECL( OP_B),
-/* 1010 1110 1100 */ TABDECL( OP_B),
-/* 1010 1110 1101 */ TABDECL( OP_B),
-/* 1010 1110 1110 */ TABDECL( OP_B),
-/* 1010 1110 1111 */ TABDECL( OP_B),
-/* 1010 1111 0000 */ TABDECL( OP_B),
-/* 1010 1111 0001 */ TABDECL( OP_B),
-/* 1010 1111 0010 */ TABDECL( OP_B),
-/* 1010 1111 0011 */ TABDECL( OP_B),
-/* 1010 1111 0100 */ TABDECL( OP_B),
-/* 1010 1111 0101 */ TABDECL( OP_B),
-/* 1010 1111 0110 */ TABDECL( OP_B),
-/* 1010 1111 0111 */ TABDECL( OP_B),
-/* 1010 1111 1000 */ TABDECL( OP_B),
-/* 1010 1111 1001 */ TABDECL( OP_B),
-/* 1010 1111 1010 */ TABDECL( OP_B),
-/* 1010 1111 1011 */ TABDECL( OP_B),
-/* 1010 1111 1100 */ TABDECL( OP_B),
-/* 1010 1111 1101 */ TABDECL( OP_B),
-/* 1010 1111 1110 */ TABDECL( OP_B),
-/* 1010 1111 1111 */ TABDECL( OP_B),
-/* 1011 0000 0000 */ TABDECL( OP_BL),
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-/* 1011 0000 0011 */ TABDECL( OP_BL),
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-/* 1011 0000 0101 */ TABDECL( OP_BL),
-/* 1011 0000 0110 */ TABDECL( OP_BL),
-/* 1011 0000 0111 */ TABDECL( OP_BL),
-/* 1011 0000 1000 */ TABDECL( OP_BL),
-/* 1011 0000 1001 */ TABDECL( OP_BL),
-/* 1011 0000 1010 */ TABDECL( OP_BL),
-/* 1011 0000 1011 */ TABDECL( OP_BL),
-/* 1011 0000 1100 */ TABDECL( OP_BL),
-/* 1011 0000 1101 */ TABDECL( OP_BL),
-/* 1011 0000 1110 */ TABDECL( OP_BL),
-/* 1011 0000 1111 */ TABDECL( OP_BL),
-/* 1011 0001 0000 */ TABDECL( OP_BL),
-/* 1011 0001 0001 */ TABDECL( OP_BL),
-/* 1011 0001 0010 */ TABDECL( OP_BL),
-/* 1011 0001 0011 */ TABDECL( OP_BL),
-/* 1011 0001 0100 */ TABDECL( OP_BL),
-/* 1011 0001 0101 */ TABDECL( OP_BL),
-/* 1011 0001 0110 */ TABDECL( OP_BL),
-/* 1011 0001 0111 */ TABDECL( OP_BL),
-/* 1011 0001 1000 */ TABDECL( OP_BL),
-/* 1011 0001 1001 */ TABDECL( OP_BL),
-/* 1011 0001 1010 */ TABDECL( OP_BL),
-/* 1011 0001 1011 */ TABDECL( OP_BL),
-/* 1011 0001 1100 */ TABDECL( OP_BL),
-/* 1011 0001 1101 */ TABDECL( OP_BL),
-/* 1011 0001 1110 */ TABDECL( OP_BL),
-/* 1011 0001 1111 */ TABDECL( OP_BL),
-/* 1011 0010 0000 */ TABDECL( OP_BL),
-/* 1011 0010 0001 */ TABDECL( OP_BL),
-/* 1011 0010 0010 */ TABDECL( OP_BL),
-/* 1011 0010 0011 */ TABDECL( OP_BL),
-/* 1011 0010 0100 */ TABDECL( OP_BL),
-/* 1011 0010 0101 */ TABDECL( OP_BL),
-/* 1011 0010 0110 */ TABDECL( OP_BL),
-/* 1011 0010 0111 */ TABDECL( OP_BL),
-/* 1011 0010 1000 */ TABDECL( OP_BL),
-/* 1011 0010 1001 */ TABDECL( OP_BL),
-/* 1011 0010 1010 */ TABDECL( OP_BL),
-/* 1011 0010 1011 */ TABDECL( OP_BL),
-/* 1011 0010 1100 */ TABDECL( OP_BL),
-/* 1011 0010 1101 */ TABDECL( OP_BL),
-/* 1011 0010 1110 */ TABDECL( OP_BL),
-/* 1011 0010 1111 */ TABDECL( OP_BL),
-/* 1011 0011 0000 */ TABDECL( OP_BL),
-/* 1011 0011 0001 */ TABDECL( OP_BL),
-/* 1011 0011 0010 */ TABDECL( OP_BL),
-/* 1011 0011 0011 */ TABDECL( OP_BL),
-/* 1011 0011 0100 */ TABDECL( OP_BL),
-/* 1011 0011 0101 */ TABDECL( OP_BL),
-/* 1011 0011 0110 */ TABDECL( OP_BL),
-/* 1011 0011 0111 */ TABDECL( OP_BL),
-/* 1011 0011 1000 */ TABDECL( OP_BL),
-/* 1011 0011 1001 */ TABDECL( OP_BL),
-/* 1011 0011 1010 */ TABDECL( OP_BL),
-/* 1011 0011 1011 */ TABDECL( OP_BL),
-/* 1011 0011 1100 */ TABDECL( OP_BL),
-/* 1011 0011 1101 */ TABDECL( OP_BL),
-/* 1011 0011 1110 */ TABDECL( OP_BL),
-/* 1011 0011 1111 */ TABDECL( OP_BL),
-/* 1011 0100 0000 */ TABDECL( OP_BL),
-/* 1011 0100 0001 */ TABDECL( OP_BL),
-/* 1011 0100 0010 */ TABDECL( OP_BL),
-/* 1011 0100 0011 */ TABDECL( OP_BL),
-/* 1011 0100 0100 */ TABDECL( OP_BL),
-/* 1011 0100 0101 */ TABDECL( OP_BL),
-/* 1011 0100 0110 */ TABDECL( OP_BL),
-/* 1011 0100 0111 */ TABDECL( OP_BL),
-/* 1011 0100 1000 */ TABDECL( OP_BL),
-/* 1011 0100 1001 */ TABDECL( OP_BL),
-/* 1011 0100 1010 */ TABDECL( OP_BL),
-/* 1011 0100 1011 */ TABDECL( OP_BL),
-/* 1011 0100 1100 */ TABDECL( OP_BL),
-/* 1011 0100 1101 */ TABDECL( OP_BL),
-/* 1011 0100 1110 */ TABDECL( OP_BL),
-/* 1011 0100 1111 */ TABDECL( OP_BL),
-/* 1011 0101 0000 */ TABDECL( OP_BL),
-/* 1011 0101 0001 */ TABDECL( OP_BL),
-/* 1011 0101 0010 */ TABDECL( OP_BL),
-/* 1011 0101 0011 */ TABDECL( OP_BL),
-/* 1011 0101 0100 */ TABDECL( OP_BL),
-/* 1011 0101 0101 */ TABDECL( OP_BL),
-/* 1011 0101 0110 */ TABDECL( OP_BL),
-/* 1011 0101 0111 */ TABDECL( OP_BL),
-/* 1011 0101 1000 */ TABDECL( OP_BL),
-/* 1011 0101 1001 */ TABDECL( OP_BL),
-/* 1011 0101 1010 */ TABDECL( OP_BL),
-/* 1011 0101 1011 */ TABDECL( OP_BL),
-/* 1011 0101 1100 */ TABDECL( OP_BL),
-/* 1011 0101 1101 */ TABDECL( OP_BL),
-/* 1011 0101 1110 */ TABDECL( OP_BL),
-/* 1011 0101 1111 */ TABDECL( OP_BL),
-/* 1011 0110 0000 */ TABDECL( OP_BL),
-/* 1011 0110 0001 */ TABDECL( OP_BL),
-/* 1011 0110 0010 */ TABDECL( OP_BL),
-/* 1011 0110 0011 */ TABDECL( OP_BL),
-/* 1011 0110 0100 */ TABDECL( OP_BL),
-/* 1011 0110 0101 */ TABDECL( OP_BL),
-/* 1011 0110 0110 */ TABDECL( OP_BL),
-/* 1011 0110 0111 */ TABDECL( OP_BL),
-/* 1011 0110 1000 */ TABDECL( OP_BL),
-/* 1011 0110 1001 */ TABDECL( OP_BL),
-/* 1011 0110 1010 */ TABDECL( OP_BL),
-/* 1011 0110 1011 */ TABDECL( OP_BL),
-/* 1011 0110 1100 */ TABDECL( OP_BL),
-/* 1011 0110 1101 */ TABDECL( OP_BL),
-/* 1011 0110 1110 */ TABDECL( OP_BL),
-/* 1011 0110 1111 */ TABDECL( OP_BL),
-/* 1011 0111 0000 */ TABDECL( OP_BL),
-/* 1011 0111 0001 */ TABDECL( OP_BL),
-/* 1011 0111 0010 */ TABDECL( OP_BL),
-/* 1011 0111 0011 */ TABDECL( OP_BL),
-/* 1011 0111 0100 */ TABDECL( OP_BL),
-/* 1011 0111 0101 */ TABDECL( OP_BL),
-/* 1011 0111 0110 */ TABDECL( OP_BL),
-/* 1011 0111 0111 */ TABDECL( OP_BL),
-/* 1011 0111 1000 */ TABDECL( OP_BL),
-/* 1011 0111 1001 */ TABDECL( OP_BL),
-/* 1011 0111 1010 */ TABDECL( OP_BL),
-/* 1011 0111 1011 */ TABDECL( OP_BL),
-/* 1011 0111 1100 */ TABDECL( OP_BL),
-/* 1011 0111 1101 */ TABDECL( OP_BL),
-/* 1011 0111 1110 */ TABDECL( OP_BL),
-/* 1011 0111 1111 */ TABDECL( OP_BL),
-/* 1011 1000 0000 */ TABDECL( OP_BL),
-/* 1011 1000 0001 */ TABDECL( OP_BL),
-/* 1011 1000 0010 */ TABDECL( OP_BL),
-/* 1011 1000 0011 */ TABDECL( OP_BL),
-/* 1011 1000 0100 */ TABDECL( OP_BL),
-/* 1011 1000 0101 */ TABDECL( OP_BL),
-/* 1011 1000 0110 */ TABDECL( OP_BL),
-/* 1011 1000 0111 */ TABDECL( OP_BL),
-/* 1011 1000 1000 */ TABDECL( OP_BL),
-/* 1011 1000 1001 */ TABDECL( OP_BL),
-/* 1011 1000 1010 */ TABDECL( OP_BL),
-/* 1011 1000 1011 */ TABDECL( OP_BL),
-/* 1011 1000 1100 */ TABDECL( OP_BL),
-/* 1011 1000 1101 */ TABDECL( OP_BL),
-/* 1011 1000 1110 */ TABDECL( OP_BL),
-/* 1011 1000 1111 */ TABDECL( OP_BL),
-/* 1011 1001 0000 */ TABDECL( OP_BL),
-/* 1011 1001 0001 */ TABDECL( OP_BL),
-/* 1011 1001 0010 */ TABDECL( OP_BL),
-/* 1011 1001 0011 */ TABDECL( OP_BL),
-/* 1011 1001 0100 */ TABDECL( OP_BL),
-/* 1011 1001 0101 */ TABDECL( OP_BL),
-/* 1011 1001 0110 */ TABDECL( OP_BL),
-/* 1011 1001 0111 */ TABDECL( OP_BL),
-/* 1011 1001 1000 */ TABDECL( OP_BL),
-/* 1011 1001 1001 */ TABDECL( OP_BL),
-/* 1011 1001 1010 */ TABDECL( OP_BL),
-/* 1011 1001 1011 */ TABDECL( OP_BL),
-/* 1011 1001 1100 */ TABDECL( OP_BL),
-/* 1011 1001 1101 */ TABDECL( OP_BL),
-/* 1011 1001 1110 */ TABDECL( OP_BL),
-/* 1011 1001 1111 */ TABDECL( OP_BL),
-/* 1011 1010 0000 */ TABDECL( OP_BL),
-/* 1011 1010 0001 */ TABDECL( OP_BL),
-/* 1011 1010 0010 */ TABDECL( OP_BL),
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-/* 1011 1010 0111 */ TABDECL( OP_BL),
-/* 1011 1010 1000 */ TABDECL( OP_BL),
-/* 1011 1010 1001 */ TABDECL( OP_BL),
-/* 1011 1010 1010 */ TABDECL( OP_BL),
-/* 1011 1010 1011 */ TABDECL( OP_BL),
-/* 1011 1010 1100 */ TABDECL( OP_BL),
-/* 1011 1010 1101 */ TABDECL( OP_BL),
-/* 1011 1010 1110 */ TABDECL( OP_BL),
-/* 1011 1010 1111 */ TABDECL( OP_BL),
-/* 1011 1011 0000 */ TABDECL( OP_BL),
-/* 1011 1011 0001 */ TABDECL( OP_BL),
-/* 1011 1011 0010 */ TABDECL( OP_BL),
-/* 1011 1011 0011 */ TABDECL( OP_BL),
-/* 1011 1011 0100 */ TABDECL( OP_BL),
-/* 1011 1011 0101 */ TABDECL( OP_BL),
-/* 1011 1011 0110 */ TABDECL( OP_BL),
-/* 1011 1011 0111 */ TABDECL( OP_BL),
-/* 1011 1011 1000 */ TABDECL( OP_BL),
-/* 1011 1011 1001 */ TABDECL( OP_BL),
-/* 1011 1011 1010 */ TABDECL( OP_BL),
-/* 1011 1011 1011 */ TABDECL( OP_BL),
-/* 1011 1011 1100 */ TABDECL( OP_BL),
-/* 1011 1011 1101 */ TABDECL( OP_BL),
-/* 1011 1011 1110 */ TABDECL( OP_BL),
-/* 1011 1011 1111 */ TABDECL( OP_BL),
-/* 1011 1100 0000 */ TABDECL( OP_BL),
-/* 1011 1100 0001 */ TABDECL( OP_BL),
-/* 1011 1100 0010 */ TABDECL( OP_BL),
-/* 1011 1100 0011 */ TABDECL( OP_BL),
-/* 1011 1100 0100 */ TABDECL( OP_BL),
-/* 1011 1100 0101 */ TABDECL( OP_BL),
-/* 1011 1100 0110 */ TABDECL( OP_BL),
-/* 1011 1100 0111 */ TABDECL( OP_BL),
-/* 1011 1100 1000 */ TABDECL( OP_BL),
-/* 1011 1100 1001 */ TABDECL( OP_BL),
-/* 1011 1100 1010 */ TABDECL( OP_BL),
-/* 1011 1100 1011 */ TABDECL( OP_BL),
-/* 1011 1100 1100 */ TABDECL( OP_BL),
-/* 1011 1100 1101 */ TABDECL( OP_BL),
-/* 1011 1100 1110 */ TABDECL( OP_BL),
-/* 1011 1100 1111 */ TABDECL( OP_BL),
-/* 1011 1101 0000 */ TABDECL( OP_BL),
-/* 1011 1101 0001 */ TABDECL( OP_BL),
-/* 1011 1101 0010 */ TABDECL( OP_BL),
-/* 1011 1101 0011 */ TABDECL( OP_BL),
-/* 1011 1101 0100 */ TABDECL( OP_BL),
-/* 1011 1101 0101 */ TABDECL( OP_BL),
-/* 1011 1101 0110 */ TABDECL( OP_BL),
-/* 1011 1101 0111 */ TABDECL( OP_BL),
-/* 1011 1101 1000 */ TABDECL( OP_BL),
-/* 1011 1101 1001 */ TABDECL( OP_BL),
-/* 1011 1101 1010 */ TABDECL( OP_BL),
-/* 1011 1101 1011 */ TABDECL( OP_BL),
-/* 1011 1101 1100 */ TABDECL( OP_BL),
-/* 1011 1101 1101 */ TABDECL( OP_BL),
-/* 1011 1101 1110 */ TABDECL( OP_BL),
-/* 1011 1101 1111 */ TABDECL( OP_BL),
-/* 1011 1110 0000 */ TABDECL( OP_BL),
-/* 1011 1110 0001 */ TABDECL( OP_BL),
-/* 1011 1110 0010 */ TABDECL( OP_BL),
-/* 1011 1110 0011 */ TABDECL( OP_BL),
-/* 1011 1110 0100 */ TABDECL( OP_BL),
-/* 1011 1110 0101 */ TABDECL( OP_BL),
-/* 1011 1110 0110 */ TABDECL( OP_BL),
-/* 1011 1110 0111 */ TABDECL( OP_BL),
-/* 1011 1110 1000 */ TABDECL( OP_BL),
-/* 1011 1110 1001 */ TABDECL( OP_BL),
-/* 1011 1110 1010 */ TABDECL( OP_BL),
-/* 1011 1110 1011 */ TABDECL( OP_BL),
-/* 1011 1110 1100 */ TABDECL( OP_BL),
-/* 1011 1110 1101 */ TABDECL( OP_BL),
-/* 1011 1110 1110 */ TABDECL( OP_BL),
-/* 1011 1110 1111 */ TABDECL( OP_BL),
-/* 1011 1111 0000 */ TABDECL( OP_BL),
-/* 1011 1111 0001 */ TABDECL( OP_BL),
-/* 1011 1111 0010 */ TABDECL( OP_BL),
-/* 1011 1111 0011 */ TABDECL( OP_BL),
-/* 1011 1111 0100 */ TABDECL( OP_BL),
-/* 1011 1111 0101 */ TABDECL( OP_BL),
-/* 1011 1111 0110 */ TABDECL( OP_BL),
-/* 1011 1111 0111 */ TABDECL( OP_BL),
-/* 1011 1111 1000 */ TABDECL( OP_BL),
-/* 1011 1111 1001 */ TABDECL( OP_BL),
-/* 1011 1111 1010 */ TABDECL( OP_BL),
-/* 1011 1111 1011 */ TABDECL( OP_BL),
-/* 1011 1111 1100 */ TABDECL( OP_BL),
-/* 1011 1111 1101 */ TABDECL( OP_BL),
-/* 1011 1111 1110 */ TABDECL( OP_BL),
-/* 1011 1111 1111 */ TABDECL( OP_BL),
-/* 1100 0000 0000 */ TABDECL( OP_STC_OPTION),
-/* 1100 0000 0001 */ TABDECL( OP_STC_OPTION),
-/* 1100 0000 0010 */ TABDECL( OP_STC_OPTION),
-/* 1100 0000 0011 */ TABDECL( OP_STC_OPTION),
-/* 1100 0000 0100 */ TABDECL( OP_STC_OPTION),
-/* 1100 0000 0101 */ TABDECL( OP_STC_OPTION),
-/* 1100 0000 0110 */ TABDECL( OP_STC_OPTION),
-/* 1100 0000 0111 */ TABDECL( OP_STC_OPTION),
-/* 1100 0000 1000 */ TABDECL( OP_STC_OPTION),
-/* 1100 0000 1001 */ TABDECL( OP_STC_OPTION),
-/* 1100 0000 1010 */ TABDECL( OP_STC_OPTION),
-/* 1100 0000 1011 */ TABDECL( OP_STC_OPTION),
-/* 1100 0000 1100 */ TABDECL( OP_STC_OPTION),
-/* 1100 0000 1101 */ TABDECL( OP_STC_OPTION),
-/* 1100 0000 1110 */ TABDECL( OP_STC_OPTION),
-/* 1100 0000 1111 */ TABDECL( OP_STC_OPTION),
-/* 1100 0001 0000 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0001 0001 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0001 0010 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0001 0011 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0001 0100 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0001 0101 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0001 0110 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0001 0111 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0001 1000 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0001 1001 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0001 1010 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0001 1011 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0001 1100 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0001 1101 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0001 1110 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0001 1111 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0010 0000 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0010 0001 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0010 0010 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0010 0011 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0010 0100 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0010 0101 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0010 0110 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0010 0111 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0010 1000 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0010 1001 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0010 1010 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0010 1011 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0010 1100 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0010 1101 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0010 1110 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0010 1111 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0011 0000 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0011 0001 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0011 0010 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0011 0011 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0011 0100 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0011 0101 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0011 0110 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0011 0111 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0011 1000 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0011 1001 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0011 1010 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0011 1011 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0011 1100 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0011 1101 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0011 1110 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0011 1111 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0100 0000 */ TABDECL( OP_STC_OPTION),
-/* 1100 0100 0001 */ TABDECL( OP_STC_OPTION),
-/* 1100 0100 0010 */ TABDECL( OP_STC_OPTION),
-/* 1100 0100 0011 */ TABDECL( OP_STC_OPTION),
-/* 1100 0100 0100 */ TABDECL( OP_STC_OPTION),
-/* 1100 0100 0101 */ TABDECL( OP_STC_OPTION),
-/* 1100 0100 0110 */ TABDECL( OP_STC_OPTION),
-/* 1100 0100 0111 */ TABDECL( OP_STC_OPTION),
-/* 1100 0100 1000 */ TABDECL( OP_STC_OPTION),
-/* 1100 0100 1001 */ TABDECL( OP_STC_OPTION),
-/* 1100 0100 1010 */ TABDECL( OP_STC_OPTION),
-/* 1100 0100 1011 */ TABDECL( OP_STC_OPTION),
-/* 1100 0100 1100 */ TABDECL( OP_STC_OPTION),
-/* 1100 0100 1101 */ TABDECL( OP_STC_OPTION),
-/* 1100 0100 1110 */ TABDECL( OP_STC_OPTION),
-/* 1100 0100 1111 */ TABDECL( OP_STC_OPTION),
-/* 1100 0101 0000 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0101 0001 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0101 0010 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0101 0011 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0101 0100 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0101 0101 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0101 0110 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0101 0111 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0101 1000 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0101 1001 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0101 1010 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0101 1011 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0101 1100 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0101 1101 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0101 1110 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0101 1111 */ TABDECL( OP_LDC_OPTION),
-/* 1100 0110 0000 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0110 0001 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0110 0010 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0110 0011 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0110 0100 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0110 0101 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0110 0110 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0110 0111 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0110 1000 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0110 1001 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0110 1010 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0110 1011 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0110 1100 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0110 1101 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0110 1110 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0110 1111 */ TABDECL( OP_STC_M_POSTIND),
-/* 1100 0111 0000 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0111 0001 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0111 0010 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0111 0011 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0111 0100 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0111 0101 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0111 0110 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0111 0111 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0111 1000 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0111 1001 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0111 1010 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0111 1011 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0111 1100 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0111 1101 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0111 1110 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 0111 1111 */ TABDECL( OP_LDC_M_POSTIND),
-/* 1100 1000 0000 */ TABDECL( OP_STC_OPTION),
-/* 1100 1000 0001 */ TABDECL( OP_STC_OPTION),
-/* 1100 1000 0010 */ TABDECL( OP_STC_OPTION),
-/* 1100 1000 0011 */ TABDECL( OP_STC_OPTION),
-/* 1100 1000 0100 */ TABDECL( OP_STC_OPTION),
-/* 1100 1000 0101 */ TABDECL( OP_STC_OPTION),
-/* 1100 1000 0110 */ TABDECL( OP_STC_OPTION),
-/* 1100 1000 0111 */ TABDECL( OP_STC_OPTION),
-/* 1100 1000 1000 */ TABDECL( OP_STC_OPTION),
-/* 1100 1000 1001 */ TABDECL( OP_STC_OPTION),
-/* 1100 1000 1010 */ TABDECL( OP_STC_OPTION),
-/* 1100 1000 1011 */ TABDECL( OP_STC_OPTION),
-/* 1100 1000 1100 */ TABDECL( OP_STC_OPTION),
-/* 1100 1000 1101 */ TABDECL( OP_STC_OPTION),
-/* 1100 1000 1110 */ TABDECL( OP_STC_OPTION),
-/* 1100 1000 1111 */ TABDECL( OP_STC_OPTION),
-/* 1100 1001 0000 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1001 0001 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1001 0010 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1001 0011 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1001 0100 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1001 0101 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1001 0110 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1001 0111 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1001 1000 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1001 1001 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1001 1010 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1001 1011 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1001 1100 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1001 1101 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1001 1110 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1001 1111 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1010 0000 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1010 0001 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1010 0010 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1010 0011 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1010 0100 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1010 0101 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1010 0110 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1010 0111 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1010 1000 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1010 1001 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1010 1010 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1010 1011 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1010 1100 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1010 1101 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1010 1110 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1010 1111 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1011 0000 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1011 0001 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1011 0010 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1011 0011 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1011 0100 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1011 0101 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1011 0110 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1011 0111 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1011 1000 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1011 1001 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1011 1010 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1011 1011 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1011 1100 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1011 1101 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1011 1110 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1011 1111 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1100 0000 */ TABDECL( OP_STC_OPTION),
-/* 1100 1100 0001 */ TABDECL( OP_STC_OPTION),
-/* 1100 1100 0010 */ TABDECL( OP_STC_OPTION),
-/* 1100 1100 0011 */ TABDECL( OP_STC_OPTION),
-/* 1100 1100 0100 */ TABDECL( OP_STC_OPTION),
-/* 1100 1100 0101 */ TABDECL( OP_STC_OPTION),
-/* 1100 1100 0110 */ TABDECL( OP_STC_OPTION),
-/* 1100 1100 0111 */ TABDECL( OP_STC_OPTION),
-/* 1100 1100 1000 */ TABDECL( OP_STC_OPTION),
-/* 1100 1100 1001 */ TABDECL( OP_STC_OPTION),
-/* 1100 1100 1010 */ TABDECL( OP_STC_OPTION),
-/* 1100 1100 1011 */ TABDECL( OP_STC_OPTION),
-/* 1100 1100 1100 */ TABDECL( OP_STC_OPTION),
-/* 1100 1100 1101 */ TABDECL( OP_STC_OPTION),
-/* 1100 1100 1110 */ TABDECL( OP_STC_OPTION),
-/* 1100 1100 1111 */ TABDECL( OP_STC_OPTION),
-/* 1100 1101 0000 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1101 0001 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1101 0010 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1101 0011 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1101 0100 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1101 0101 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1101 0110 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1101 0111 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1101 1000 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1101 1001 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1101 1010 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1101 1011 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1101 1100 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1101 1101 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1101 1110 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1101 1111 */ TABDECL( OP_LDC_OPTION),
-/* 1100 1110 0000 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1110 0001 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1110 0010 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1110 0011 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1110 0100 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1110 0101 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1110 0110 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1110 0111 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1110 1000 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1110 1001 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1110 1010 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1110 1011 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1110 1100 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1110 1101 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1110 1110 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1110 1111 */ TABDECL( OP_STC_P_POSTIND),
-/* 1100 1111 0000 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1111 0001 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1111 0010 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1111 0011 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1111 0100 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1111 0101 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1111 0110 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1111 0111 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1111 1000 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1111 1001 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1111 1010 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1111 1011 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1111 1100 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1111 1101 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1111 1110 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1100 1111 1111 */ TABDECL( OP_LDC_P_POSTIND),
-/* 1101 0000 0000 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0000 0001 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0000 0010 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0000 0011 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0000 0100 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0000 0101 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0000 0110 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0000 0111 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0000 1000 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0000 1001 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0000 1010 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0000 1011 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0000 1100 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0000 1101 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0000 1110 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0000 1111 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0001 0000 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0001 0001 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0001 0010 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0001 0011 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0001 0100 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0001 0101 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0001 0110 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0001 0111 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0001 1000 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0001 1001 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0001 1010 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0001 1011 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0001 1100 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0001 1101 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0001 1110 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0001 1111 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0010 0000 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0010 0001 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0010 0010 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0010 0011 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0010 0100 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0010 0101 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0010 0110 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0010 0111 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0010 1000 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0010 1001 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0010 1010 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0010 1011 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0010 1100 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0010 1101 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0010 1110 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0010 1111 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0011 0000 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0011 0001 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0011 0010 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0011 0011 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0011 0100 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0011 0101 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0011 0110 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0011 0111 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0011 1000 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0011 1001 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0011 1010 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0011 1011 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0011 1100 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0011 1101 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0011 1110 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0011 1111 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0100 0000 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0100 0001 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0100 0010 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0100 0011 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0100 0100 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0100 0101 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0100 0110 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0100 0111 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0100 1000 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0100 1001 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0100 1010 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0100 1011 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0100 1100 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0100 1101 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0100 1110 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0100 1111 */ TABDECL( OP_STC_M_IMM_OFF),
-/* 1101 0101 0000 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0101 0001 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0101 0010 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0101 0011 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0101 0100 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0101 0101 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0101 0110 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0101 0111 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0101 1000 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0101 1001 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0101 1010 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0101 1011 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0101 1100 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0101 1101 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0101 1110 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0101 1111 */ TABDECL( OP_LDC_M_IMM_OFF),
-/* 1101 0110 0000 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0110 0001 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0110 0010 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0110 0011 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0110 0100 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0110 0101 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0110 0110 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0110 0111 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0110 1000 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0110 1001 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0110 1010 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0110 1011 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0110 1100 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0110 1101 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0110 1110 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0110 1111 */ TABDECL( OP_STC_M_PREIND),
-/* 1101 0111 0000 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0111 0001 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0111 0010 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0111 0011 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0111 0100 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0111 0101 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0111 0110 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0111 0111 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0111 1000 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0111 1001 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0111 1010 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0111 1011 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0111 1100 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0111 1101 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0111 1110 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 0111 1111 */ TABDECL( OP_LDC_M_PREIND),
-/* 1101 1000 0000 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1000 0001 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1000 0010 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1000 0011 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1000 0100 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1000 0101 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1000 0110 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1000 0111 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1000 1000 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1000 1001 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1000 1010 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1000 1011 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1000 1100 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1000 1101 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1000 1110 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1000 1111 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1001 0000 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1001 0001 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1001 0010 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1001 0011 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1001 0100 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1001 0101 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1001 0110 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1001 0111 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1001 1000 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1001 1001 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1001 1010 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1001 1011 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1001 1100 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1001 1101 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1001 1110 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1001 1111 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1010 0000 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1010 0001 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1010 0010 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1010 0011 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1010 0100 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1010 0101 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1010 0110 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1010 0111 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1010 1000 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1010 1001 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1010 1010 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1010 1011 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1010 1100 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1010 1101 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1010 1110 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1010 1111 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1011 0000 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1011 0001 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1011 0010 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1011 0011 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1011 0100 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1011 0101 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1011 0110 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1011 0111 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1011 1000 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1011 1001 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1011 1010 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1011 1011 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1011 1100 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1011 1101 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1011 1110 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1011 1111 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1100 0000 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1100 0001 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1100 0010 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1100 0011 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1100 0100 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1100 0101 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1100 0110 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1100 0111 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1100 1000 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1100 1001 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1100 1010 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1100 1011 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1100 1100 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1100 1101 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1100 1110 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1100 1111 */ TABDECL( OP_STC_P_IMM_OFF),
-/* 1101 1101 0000 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1101 0001 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1101 0010 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1101 0011 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1101 0100 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1101 0101 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1101 0110 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1101 0111 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1101 1000 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1101 1001 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1101 1010 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1101 1011 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1101 1100 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1101 1101 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1101 1110 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1101 1111 */ TABDECL( OP_LDC_P_IMM_OFF),
-/* 1101 1110 0000 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1110 0001 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1110 0010 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1110 0011 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1110 0100 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1110 0101 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1110 0110 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1110 0111 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1110 1000 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1110 1001 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1110 1010 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1110 1011 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1110 1100 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1110 1101 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1110 1110 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1110 1111 */ TABDECL( OP_STC_P_PREIND),
-/* 1101 1111 0000 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1111 0001 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1111 0010 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1111 0011 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1111 0100 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1111 0101 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1111 0110 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1111 0111 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1111 1000 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1111 1001 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1111 1010 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1111 1011 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1111 1100 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1111 1101 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1111 1110 */ TABDECL( OP_LDC_P_PREIND),
-/* 1101 1111 1111 */ TABDECL( OP_LDC_P_PREIND),
-/* 1110 0000 0000 */ TABDECL( OP_CDP),
-/* 1110 0000 0001 */ TABDECL( OP_MCR),
-/* 1110 0000 0010 */ TABDECL( OP_CDP),
-/* 1110 0000 0011 */ TABDECL( OP_MCR),
-/* 1110 0000 0100 */ TABDECL( OP_CDP),
-/* 1110 0000 0101 */ TABDECL( OP_MCR),
-/* 1110 0000 0110 */ TABDECL( OP_CDP),
-/* 1110 0000 0111 */ TABDECL( OP_MCR),
-/* 1110 0000 1000 */ TABDECL( OP_CDP),
-/* 1110 0000 1001 */ TABDECL( OP_MCR),
-/* 1110 0000 1010 */ TABDECL( OP_CDP),
-/* 1110 0000 1011 */ TABDECL( OP_MCR),
-/* 1110 0000 1100 */ TABDECL( OP_CDP),
-/* 1110 0000 1101 */ TABDECL( OP_MCR),
-/* 1110 0000 1110 */ TABDECL( OP_CDP),
-/* 1110 0000 1111 */ TABDECL( OP_MCR),
-/* 1110 0001 0000 */ TABDECL( OP_CDP),
-/* 1110 0001 0001 */ TABDECL( OP_MRC),
-/* 1110 0001 0010 */ TABDECL( OP_CDP),
-/* 1110 0001 0011 */ TABDECL( OP_MRC),
-/* 1110 0001 0100 */ TABDECL( OP_CDP),
-/* 1110 0001 0101 */ TABDECL( OP_MRC),
-/* 1110 0001 0110 */ TABDECL( OP_CDP),
-/* 1110 0001 0111 */ TABDECL( OP_MRC),
-/* 1110 0001 1000 */ TABDECL( OP_CDP),
-/* 1110 0001 1001 */ TABDECL( OP_MRC),
-/* 1110 0001 1010 */ TABDECL( OP_CDP),
-/* 1110 0001 1011 */ TABDECL( OP_MRC),
-/* 1110 0001 1100 */ TABDECL( OP_CDP),
-/* 1110 0001 1101 */ TABDECL( OP_MRC),
-/* 1110 0001 1110 */ TABDECL( OP_CDP),
-/* 1110 0001 1111 */ TABDECL( OP_MRC),
-/* 1110 0010 0000 */ TABDECL( OP_CDP),
-/* 1110 0010 0001 */ TABDECL( OP_MCR),
-/* 1110 0010 0010 */ TABDECL( OP_CDP),
-/* 1110 0010 0011 */ TABDECL( OP_MCR),
-/* 1110 0010 0100 */ TABDECL( OP_CDP),
-/* 1110 0010 0101 */ TABDECL( OP_MCR),
-/* 1110 0010 0110 */ TABDECL( OP_CDP),
-/* 1110 0010 0111 */ TABDECL( OP_MCR),
-/* 1110 0010 1000 */ TABDECL( OP_CDP),
-/* 1110 0010 1001 */ TABDECL( OP_MCR),
-/* 1110 0010 1010 */ TABDECL( OP_CDP),
-/* 1110 0010 1011 */ TABDECL( OP_MCR),
-/* 1110 0010 1100 */ TABDECL( OP_CDP),
-/* 1110 0010 1101 */ TABDECL( OP_MCR),
-/* 1110 0010 1110 */ TABDECL( OP_CDP),
-/* 1110 0010 1111 */ TABDECL( OP_MCR),
-/* 1110 0011 0000 */ TABDECL( OP_CDP),
-/* 1110 0011 0001 */ TABDECL( OP_MRC),
-/* 1110 0011 0010 */ TABDECL( OP_CDP),
-/* 1110 0011 0011 */ TABDECL( OP_MRC),
-/* 1110 0011 0100 */ TABDECL( OP_CDP),
-/* 1110 0011 0101 */ TABDECL( OP_MRC),
-/* 1110 0011 0110 */ TABDECL( OP_CDP),
-/* 1110 0011 0111 */ TABDECL( OP_MRC),
-/* 1110 0011 1000 */ TABDECL( OP_CDP),
-/* 1110 0011 1001 */ TABDECL( OP_MRC),
-/* 1110 0011 1010 */ TABDECL( OP_CDP),
-/* 1110 0011 1011 */ TABDECL( OP_MRC),
-/* 1110 0011 1100 */ TABDECL( OP_CDP),
-/* 1110 0011 1101 */ TABDECL( OP_MRC),
-/* 1110 0011 1110 */ TABDECL( OP_CDP),
-/* 1110 0011 1111 */ TABDECL( OP_MRC),
-/* 1110 0100 0000 */ TABDECL( OP_CDP),
-/* 1110 0100 0001 */ TABDECL( OP_MCR),
-/* 1110 0100 0010 */ TABDECL( OP_CDP),
-/* 1110 0100 0011 */ TABDECL( OP_MCR),
-/* 1110 0100 0100 */ TABDECL( OP_CDP),
-/* 1110 0100 0101 */ TABDECL( OP_MCR),
-/* 1110 0100 0110 */ TABDECL( OP_CDP),
-/* 1110 0100 0111 */ TABDECL( OP_MCR),
-/* 1110 0100 1000 */ TABDECL( OP_CDP),
-/* 1110 0100 1001 */ TABDECL( OP_MCR),
-/* 1110 0100 1010 */ TABDECL( OP_CDP),
-/* 1110 0100 1011 */ TABDECL( OP_MCR),
-/* 1110 0100 1100 */ TABDECL( OP_CDP),
-/* 1110 0100 1101 */ TABDECL( OP_MCR),
-/* 1110 0100 1110 */ TABDECL( OP_CDP),
-/* 1110 0100 1111 */ TABDECL( OP_MCR),
-/* 1110 0101 0000 */ TABDECL( OP_CDP),
-/* 1110 0101 0001 */ TABDECL( OP_MRC),
-/* 1110 0101 0010 */ TABDECL( OP_CDP),
-/* 1110 0101 0011 */ TABDECL( OP_MRC),
-/* 1110 0101 0100 */ TABDECL( OP_CDP),
-/* 1110 0101 0101 */ TABDECL( OP_MRC),
-/* 1110 0101 0110 */ TABDECL( OP_CDP),
-/* 1110 0101 0111 */ TABDECL( OP_MRC),
-/* 1110 0101 1000 */ TABDECL( OP_CDP),
-/* 1110 0101 1001 */ TABDECL( OP_MRC),
-/* 1110 0101 1010 */ TABDECL( OP_CDP),
-/* 1110 0101 1011 */ TABDECL( OP_MRC),
-/* 1110 0101 1100 */ TABDECL( OP_CDP),
-/* 1110 0101 1101 */ TABDECL( OP_MRC),
-/* 1110 0101 1110 */ TABDECL( OP_CDP),
-/* 1110 0101 1111 */ TABDECL( OP_MRC),
-/* 1110 0110 0000 */ TABDECL( OP_CDP),
-/* 1110 0110 0001 */ TABDECL( OP_MCR),
-/* 1110 0110 0010 */ TABDECL( OP_CDP),
-/* 1110 0110 0011 */ TABDECL( OP_MCR),
-/* 1110 0110 0100 */ TABDECL( OP_CDP),
-/* 1110 0110 0101 */ TABDECL( OP_MCR),
-/* 1110 0110 0110 */ TABDECL( OP_CDP),
-/* 1110 0110 0111 */ TABDECL( OP_MCR),
-/* 1110 0110 1000 */ TABDECL( OP_CDP),
-/* 1110 0110 1001 */ TABDECL( OP_MCR),
-/* 1110 0110 1010 */ TABDECL( OP_CDP),
-/* 1110 0110 1011 */ TABDECL( OP_MCR),
-/* 1110 0110 1100 */ TABDECL( OP_CDP),
-/* 1110 0110 1101 */ TABDECL( OP_MCR),
-/* 1110 0110 1110 */ TABDECL( OP_CDP),
-/* 1110 0110 1111 */ TABDECL( OP_MCR),
-/* 1110 0111 0000 */ TABDECL( OP_CDP),
-/* 1110 0111 0001 */ TABDECL( OP_MRC),
-/* 1110 0111 0010 */ TABDECL( OP_CDP),
-/* 1110 0111 0011 */ TABDECL( OP_MRC),
-/* 1110 0111 0100 */ TABDECL( OP_CDP),
-/* 1110 0111 0101 */ TABDECL( OP_MRC),
-/* 1110 0111 0110 */ TABDECL( OP_CDP),
-/* 1110 0111 0111 */ TABDECL( OP_MRC),
-/* 1110 0111 1000 */ TABDECL( OP_CDP),
-/* 1110 0111 1001 */ TABDECL( OP_MRC),
-/* 1110 0111 1010 */ TABDECL( OP_CDP),
-/* 1110 0111 1011 */ TABDECL( OP_MRC),
-/* 1110 0111 1100 */ TABDECL( OP_CDP),
-/* 1110 0111 1101 */ TABDECL( OP_MRC),
-/* 1110 0111 1110 */ TABDECL( OP_CDP),
-/* 1110 0111 1111 */ TABDECL( OP_MRC),
-/* 1110 1000 0000 */ TABDECL( OP_CDP),
-/* 1110 1000 0001 */ TABDECL( OP_MCR),
-/* 1110 1000 0010 */ TABDECL( OP_CDP),
-/* 1110 1000 0011 */ TABDECL( OP_MCR),
-/* 1110 1000 0100 */ TABDECL( OP_CDP),
-/* 1110 1000 0101 */ TABDECL( OP_MCR),
-/* 1110 1000 0110 */ TABDECL( OP_CDP),
-/* 1110 1000 0111 */ TABDECL( OP_MCR),
-/* 1110 1000 1000 */ TABDECL( OP_CDP),
-/* 1110 1000 1001 */ TABDECL( OP_MCR),
-/* 1110 1000 1010 */ TABDECL( OP_CDP),
-/* 1110 1000 1011 */ TABDECL( OP_MCR),
-/* 1110 1000 1100 */ TABDECL( OP_CDP),
-/* 1110 1000 1101 */ TABDECL( OP_MCR),
-/* 1110 1000 1110 */ TABDECL( OP_CDP),
-/* 1110 1000 1111 */ TABDECL( OP_MCR),
-/* 1110 1001 0000 */ TABDECL( OP_CDP),
-/* 1110 1001 0001 */ TABDECL( OP_MRC),
-/* 1110 1001 0010 */ TABDECL( OP_CDP),
-/* 1110 1001 0011 */ TABDECL( OP_MRC),
-/* 1110 1001 0100 */ TABDECL( OP_CDP),
-/* 1110 1001 0101 */ TABDECL( OP_MRC),
-/* 1110 1001 0110 */ TABDECL( OP_CDP),
-/* 1110 1001 0111 */ TABDECL( OP_MRC),
-/* 1110 1001 1000 */ TABDECL( OP_CDP),
-/* 1110 1001 1001 */ TABDECL( OP_MRC),
-/* 1110 1001 1010 */ TABDECL( OP_CDP),
-/* 1110 1001 1011 */ TABDECL( OP_MRC),
-/* 1110 1001 1100 */ TABDECL( OP_CDP),
-/* 1110 1001 1101 */ TABDECL( OP_MRC),
-/* 1110 1001 1110 */ TABDECL( OP_CDP),
-/* 1110 1001 1111 */ TABDECL( OP_MRC),
-/* 1110 1010 0000 */ TABDECL( OP_CDP),
-/* 1110 1010 0001 */ TABDECL( OP_MCR),
-/* 1110 1010 0010 */ TABDECL( OP_CDP),
-/* 1110 1010 0011 */ TABDECL( OP_MCR),
-/* 1110 1010 0100 */ TABDECL( OP_CDP),
-/* 1110 1010 0101 */ TABDECL( OP_MCR),
-/* 1110 1010 0110 */ TABDECL( OP_CDP),
-/* 1110 1010 0111 */ TABDECL( OP_MCR),
-/* 1110 1010 1000 */ TABDECL( OP_CDP),
-/* 1110 1010 1001 */ TABDECL( OP_MCR),
-/* 1110 1010 1010 */ TABDECL( OP_CDP),
-/* 1110 1010 1011 */ TABDECL( OP_MCR),
-/* 1110 1010 1100 */ TABDECL( OP_CDP),
-/* 1110 1010 1101 */ TABDECL( OP_MCR),
-/* 1110 1010 1110 */ TABDECL( OP_CDP),
-/* 1110 1010 1111 */ TABDECL( OP_MCR),
-/* 1110 1011 0000 */ TABDECL( OP_CDP),
-/* 1110 1011 0001 */ TABDECL( OP_MRC),
-/* 1110 1011 0010 */ TABDECL( OP_CDP),
-/* 1110 1011 0011 */ TABDECL( OP_MRC),
-/* 1110 1011 0100 */ TABDECL( OP_CDP),
-/* 1110 1011 0101 */ TABDECL( OP_MRC),
-/* 1110 1011 0110 */ TABDECL( OP_CDP),
-/* 1110 1011 0111 */ TABDECL( OP_MRC),
-/* 1110 1011 1000 */ TABDECL( OP_CDP),
-/* 1110 1011 1001 */ TABDECL( OP_MRC),
-/* 1110 1011 1010 */ TABDECL( OP_CDP),
-/* 1110 1011 1011 */ TABDECL( OP_MRC),
-/* 1110 1011 1100 */ TABDECL( OP_CDP),
-/* 1110 1011 1101 */ TABDECL( OP_MRC),
-/* 1110 1011 1110 */ TABDECL( OP_CDP),
-/* 1110 1011 1111 */ TABDECL( OP_MRC),
-/* 1110 1100 0000 */ TABDECL( OP_CDP),
-/* 1110 1100 0001 */ TABDECL( OP_MCR),
-/* 1110 1100 0010 */ TABDECL( OP_CDP),
-/* 1110 1100 0011 */ TABDECL( OP_MCR),
-/* 1110 1100 0100 */ TABDECL( OP_CDP),
-/* 1110 1100 0101 */ TABDECL( OP_MCR),
-/* 1110 1100 0110 */ TABDECL( OP_CDP),
-/* 1110 1100 0111 */ TABDECL( OP_MCR),
-/* 1110 1100 1000 */ TABDECL( OP_CDP),
-/* 1110 1100 1001 */ TABDECL( OP_MCR),
-/* 1110 1100 1010 */ TABDECL( OP_CDP),
-/* 1110 1100 1011 */ TABDECL( OP_MCR),
-/* 1110 1100 1100 */ TABDECL( OP_CDP),
-/* 1110 1100 1101 */ TABDECL( OP_MCR),
-/* 1110 1100 1110 */ TABDECL( OP_CDP),
-/* 1110 1100 1111 */ TABDECL( OP_MCR),
-/* 1110 1101 0000 */ TABDECL( OP_CDP),
-/* 1110 1101 0001 */ TABDECL( OP_MRC),
-/* 1110 1101 0010 */ TABDECL( OP_CDP),
-/* 1110 1101 0011 */ TABDECL( OP_MRC),
-/* 1110 1101 0100 */ TABDECL( OP_CDP),
-/* 1110 1101 0101 */ TABDECL( OP_MRC),
-/* 1110 1101 0110 */ TABDECL( OP_CDP),
-/* 1110 1101 0111 */ TABDECL( OP_MRC),
-/* 1110 1101 1000 */ TABDECL( OP_CDP),
-/* 1110 1101 1001 */ TABDECL( OP_MRC),
-/* 1110 1101 1010 */ TABDECL( OP_CDP),
-/* 1110 1101 1011 */ TABDECL( OP_MRC),
-/* 1110 1101 1100 */ TABDECL( OP_CDP),
-/* 1110 1101 1101 */ TABDECL( OP_MRC),
-/* 1110 1101 1110 */ TABDECL( OP_CDP),
-/* 1110 1101 1111 */ TABDECL( OP_MRC),
-/* 1110 1110 0000 */ TABDECL( OP_CDP),
-/* 1110 1110 0001 */ TABDECL( OP_MCR),
-/* 1110 1110 0010 */ TABDECL( OP_CDP),
-/* 1110 1110 0011 */ TABDECL( OP_MCR),
-/* 1110 1110 0100 */ TABDECL( OP_CDP),
-/* 1110 1110 0101 */ TABDECL( OP_MCR),
-/* 1110 1110 0110 */ TABDECL( OP_CDP),
-/* 1110 1110 0111 */ TABDECL( OP_MCR),
-/* 1110 1110 1000 */ TABDECL( OP_CDP),
-/* 1110 1110 1001 */ TABDECL( OP_MCR),
-/* 1110 1110 1010 */ TABDECL( OP_CDP),
-/* 1110 1110 1011 */ TABDECL( OP_MCR),
-/* 1110 1110 1100 */ TABDECL( OP_CDP),
-/* 1110 1110 1101 */ TABDECL( OP_MCR),
-/* 1110 1110 1110 */ TABDECL( OP_CDP),
-/* 1110 1110 1111 */ TABDECL( OP_MCR),
-/* 1110 1111 0000 */ TABDECL( OP_CDP),
-/* 1110 1111 0001 */ TABDECL( OP_MRC),
-/* 1110 1111 0010 */ TABDECL( OP_CDP),
-/* 1110 1111 0011 */ TABDECL( OP_MRC),
-/* 1110 1111 0100 */ TABDECL( OP_CDP),
-/* 1110 1111 0101 */ TABDECL( OP_MRC),
-/* 1110 1111 0110 */ TABDECL( OP_CDP),
-/* 1110 1111 0111 */ TABDECL( OP_MRC),
-/* 1110 1111 1000 */ TABDECL( OP_CDP),
-/* 1110 1111 1001 */ TABDECL( OP_MRC),
-/* 1110 1111 1010 */ TABDECL( OP_CDP),
-/* 1110 1111 1011 */ TABDECL( OP_MRC),
-/* 1110 1111 1100 */ TABDECL( OP_CDP),
-/* 1110 1111 1101 */ TABDECL( OP_MRC),
-/* 1110 1111 1110 */ TABDECL( OP_CDP),
-/* 1110 1111 1111 */ TABDECL( OP_MRC),
-/* 1111 0000 0000 */ TABDECL( OP_SWI),
-/* 1111 0000 0001 */ TABDECL( OP_SWI),
-/* 1111 0000 0010 */ TABDECL( OP_SWI),
-/* 1111 0000 0011 */ TABDECL( OP_SWI),
-/* 1111 0000 0100 */ TABDECL( OP_SWI),
-/* 1111 0000 0101 */ TABDECL( OP_SWI),
-/* 1111 0000 0110 */ TABDECL( OP_SWI),
-/* 1111 0000 0111 */ TABDECL( OP_SWI),
-/* 1111 0000 1000 */ TABDECL( OP_SWI),
-/* 1111 0000 1001 */ TABDECL( OP_SWI),
-/* 1111 0000 1010 */ TABDECL( OP_SWI),
-/* 1111 0000 1011 */ TABDECL( OP_SWI),
-/* 1111 0000 1100 */ TABDECL( OP_SWI),
-/* 1111 0000 1101 */ TABDECL( OP_SWI),
-/* 1111 0000 1110 */ TABDECL( OP_SWI),
-/* 1111 0000 1111 */ TABDECL( OP_SWI),
-/* 1111 0001 0000 */ TABDECL( OP_SWI),
-/* 1111 0001 0001 */ TABDECL( OP_SWI),
-/* 1111 0001 0010 */ TABDECL( OP_SWI),
-/* 1111 0001 0011 */ TABDECL( OP_SWI),
-/* 1111 0001 0100 */ TABDECL( OP_SWI),
-/* 1111 0001 0101 */ TABDECL( OP_SWI),
-/* 1111 0001 0110 */ TABDECL( OP_SWI),
-/* 1111 0001 0111 */ TABDECL( OP_SWI),
-/* 1111 0001 1000 */ TABDECL( OP_SWI),
-/* 1111 0001 1001 */ TABDECL( OP_SWI),
-/* 1111 0001 1010 */ TABDECL( OP_SWI),
-/* 1111 0001 1011 */ TABDECL( OP_SWI),
-/* 1111 0001 1100 */ TABDECL( OP_SWI),
-/* 1111 0001 1101 */ TABDECL( OP_SWI),
-/* 1111 0001 1110 */ TABDECL( OP_SWI),
-/* 1111 0001 1111 */ TABDECL( OP_SWI),
-/* 1111 0010 0000 */ TABDECL( OP_SWI),
-/* 1111 0010 0001 */ TABDECL( OP_SWI),
-/* 1111 0010 0010 */ TABDECL( OP_SWI),
-/* 1111 0010 0011 */ TABDECL( OP_SWI),
-/* 1111 0010 0100 */ TABDECL( OP_SWI),
-/* 1111 0010 0101 */ TABDECL( OP_SWI),
-/* 1111 0010 0110 */ TABDECL( OP_SWI),
-/* 1111 0010 0111 */ TABDECL( OP_SWI),
-/* 1111 0010 1000 */ TABDECL( OP_SWI),
-/* 1111 0010 1001 */ TABDECL( OP_SWI),
-/* 1111 0010 1010 */ TABDECL( OP_SWI),
-/* 1111 0010 1011 */ TABDECL( OP_SWI),
-/* 1111 0010 1100 */ TABDECL( OP_SWI),
-/* 1111 0010 1101 */ TABDECL( OP_SWI),
-/* 1111 0010 1110 */ TABDECL( OP_SWI),
-/* 1111 0010 1111 */ TABDECL( OP_SWI),
-/* 1111 0011 0000 */ TABDECL( OP_SWI),
-/* 1111 0011 0001 */ TABDECL( OP_SWI),
-/* 1111 0011 0010 */ TABDECL( OP_SWI),
-/* 1111 0011 0011 */ TABDECL( OP_SWI),
-/* 1111 0011 0100 */ TABDECL( OP_SWI),
-/* 1111 0011 0101 */ TABDECL( OP_SWI),
-/* 1111 0011 0110 */ TABDECL( OP_SWI),
-/* 1111 0011 0111 */ TABDECL( OP_SWI),
-/* 1111 0011 1000 */ TABDECL( OP_SWI),
-/* 1111 0011 1001 */ TABDECL( OP_SWI),
-/* 1111 0011 1010 */ TABDECL( OP_SWI),
-/* 1111 0011 1011 */ TABDECL( OP_SWI),
-/* 1111 0011 1100 */ TABDECL( OP_SWI),
-/* 1111 0011 1101 */ TABDECL( OP_SWI),
-/* 1111 0011 1110 */ TABDECL( OP_SWI),
-/* 1111 0011 1111 */ TABDECL( OP_SWI),
-/* 1111 0100 0000 */ TABDECL( OP_SWI),
-/* 1111 0100 0001 */ TABDECL( OP_SWI),
-/* 1111 0100 0010 */ TABDECL( OP_SWI),
-/* 1111 0100 0011 */ TABDECL( OP_SWI),
-/* 1111 0100 0100 */ TABDECL( OP_SWI),
-/* 1111 0100 0101 */ TABDECL( OP_SWI),
-/* 1111 0100 0110 */ TABDECL( OP_SWI),
-/* 1111 0100 0111 */ TABDECL( OP_SWI),
-/* 1111 0100 1000 */ TABDECL( OP_SWI),
-/* 1111 0100 1001 */ TABDECL( OP_SWI),
-/* 1111 0100 1010 */ TABDECL( OP_SWI),
-/* 1111 0100 1011 */ TABDECL( OP_SWI),
-/* 1111 0100 1100 */ TABDECL( OP_SWI),
-/* 1111 0100 1101 */ TABDECL( OP_SWI),
-/* 1111 0100 1110 */ TABDECL( OP_SWI),
-/* 1111 0100 1111 */ TABDECL( OP_SWI),
-/* 1111 0101 0000 */ TABDECL( OP_SWI),
-/* 1111 0101 0001 */ TABDECL( OP_SWI),
-/* 1111 0101 0010 */ TABDECL( OP_SWI),
-/* 1111 0101 0011 */ TABDECL( OP_SWI),
-/* 1111 0101 0100 */ TABDECL( OP_SWI),
-/* 1111 0101 0101 */ TABDECL( OP_SWI),
-/* 1111 0101 0110 */ TABDECL( OP_SWI),
-/* 1111 0101 0111 */ TABDECL( OP_SWI),
-/* 1111 0101 1000 */ TABDECL( OP_SWI),
-/* 1111 0101 1001 */ TABDECL( OP_SWI),
-/* 1111 0101 1010 */ TABDECL( OP_SWI),
-/* 1111 0101 1011 */ TABDECL( OP_SWI),
-/* 1111 0101 1100 */ TABDECL( OP_SWI),
-/* 1111 0101 1101 */ TABDECL( OP_SWI),
-/* 1111 0101 1110 */ TABDECL( OP_SWI),
-/* 1111 0101 1111 */ TABDECL( OP_SWI),
-/* 1111 0110 0000 */ TABDECL( OP_SWI),
-/* 1111 0110 0001 */ TABDECL( OP_SWI),
-/* 1111 0110 0010 */ TABDECL( OP_SWI),
-/* 1111 0110 0011 */ TABDECL( OP_SWI),
-/* 1111 0110 0100 */ TABDECL( OP_SWI),
-/* 1111 0110 0101 */ TABDECL( OP_SWI),
-/* 1111 0110 0110 */ TABDECL( OP_SWI),
-/* 1111 0110 0111 */ TABDECL( OP_SWI),
-/* 1111 0110 1000 */ TABDECL( OP_SWI),
-/* 1111 0110 1001 */ TABDECL( OP_SWI),
-/* 1111 0110 1010 */ TABDECL( OP_SWI),
-/* 1111 0110 1011 */ TABDECL( OP_SWI),
-/* 1111 0110 1100 */ TABDECL( OP_SWI),
-/* 1111 0110 1101 */ TABDECL( OP_SWI),
-/* 1111 0110 1110 */ TABDECL( OP_SWI),
-/* 1111 0110 1111 */ TABDECL( OP_SWI),
-/* 1111 0111 0000 */ TABDECL( OP_SWI),
-/* 1111 0111 0001 */ TABDECL( OP_SWI),
-/* 1111 0111 0010 */ TABDECL( OP_SWI),
-/* 1111 0111 0011 */ TABDECL( OP_SWI),
-/* 1111 0111 0100 */ TABDECL( OP_SWI),
-/* 1111 0111 0101 */ TABDECL( OP_SWI),
-/* 1111 0111 0110 */ TABDECL( OP_SWI),
-/* 1111 0111 0111 */ TABDECL( OP_SWI),
-/* 1111 0111 1000 */ TABDECL( OP_SWI),
-/* 1111 0111 1001 */ TABDECL( OP_SWI),
-/* 1111 0111 1010 */ TABDECL( OP_SWI),
-/* 1111 0111 1011 */ TABDECL( OP_SWI),
-/* 1111 0111 1100 */ TABDECL( OP_SWI),
-/* 1111 0111 1101 */ TABDECL( OP_SWI),
-/* 1111 0111 1110 */ TABDECL( OP_SWI),
-/* 1111 0111 1111 */ TABDECL( OP_SWI),
-/* 1111 1000 0000 */ TABDECL( OP_SWI),
-/* 1111 1000 0001 */ TABDECL( OP_SWI),
-/* 1111 1000 0010 */ TABDECL( OP_SWI),
-/* 1111 1000 0011 */ TABDECL( OP_SWI),
-/* 1111 1000 0100 */ TABDECL( OP_SWI),
-/* 1111 1000 0101 */ TABDECL( OP_SWI),
-/* 1111 1000 0110 */ TABDECL( OP_SWI),
-/* 1111 1000 0111 */ TABDECL( OP_SWI),
-/* 1111 1000 1000 */ TABDECL( OP_SWI),
-/* 1111 1000 1001 */ TABDECL( OP_SWI),
-/* 1111 1000 1010 */ TABDECL( OP_SWI),
-/* 1111 1000 1011 */ TABDECL( OP_SWI),
-/* 1111 1000 1100 */ TABDECL( OP_SWI),
-/* 1111 1000 1101 */ TABDECL( OP_SWI),
-/* 1111 1000 1110 */ TABDECL( OP_SWI),
-/* 1111 1000 1111 */ TABDECL( OP_SWI),
-/* 1111 1001 0000 */ TABDECL( OP_SWI),
-/* 1111 1001 0001 */ TABDECL( OP_SWI),
-/* 1111 1001 0010 */ TABDECL( OP_SWI),
-/* 1111 1001 0011 */ TABDECL( OP_SWI),
-/* 1111 1001 0100 */ TABDECL( OP_SWI),
-/* 1111 1001 0101 */ TABDECL( OP_SWI),
-/* 1111 1001 0110 */ TABDECL( OP_SWI),
-/* 1111 1001 0111 */ TABDECL( OP_SWI),
-/* 1111 1001 1000 */ TABDECL( OP_SWI),
-/* 1111 1001 1001 */ TABDECL( OP_SWI),
-/* 1111 1001 1010 */ TABDECL( OP_SWI),
-/* 1111 1001 1011 */ TABDECL( OP_SWI),
-/* 1111 1001 1100 */ TABDECL( OP_SWI),
-/* 1111 1001 1101 */ TABDECL( OP_SWI),
-/* 1111 1001 1110 */ TABDECL( OP_SWI),
-/* 1111 1001 1111 */ TABDECL( OP_SWI),
-/* 1111 1010 0000 */ TABDECL( OP_SWI),
-/* 1111 1010 0001 */ TABDECL( OP_SWI),
-/* 1111 1010 0010 */ TABDECL( OP_SWI),
-/* 1111 1010 0011 */ TABDECL( OP_SWI),
-/* 1111 1010 0100 */ TABDECL( OP_SWI),
-/* 1111 1010 0101 */ TABDECL( OP_SWI),
-/* 1111 1010 0110 */ TABDECL( OP_SWI),
-/* 1111 1010 0111 */ TABDECL( OP_SWI),
-/* 1111 1010 1000 */ TABDECL( OP_SWI),
-/* 1111 1010 1001 */ TABDECL( OP_SWI),
-/* 1111 1010 1010 */ TABDECL( OP_SWI),
-/* 1111 1010 1011 */ TABDECL( OP_SWI),
-/* 1111 1010 1100 */ TABDECL( OP_SWI),
-/* 1111 1010 1101 */ TABDECL( OP_SWI),
-/* 1111 1010 1110 */ TABDECL( OP_SWI),
-/* 1111 1010 1111 */ TABDECL( OP_SWI),
-/* 1111 1011 0000 */ TABDECL( OP_SWI),
-/* 1111 1011 0001 */ TABDECL( OP_SWI),
-/* 1111 1011 0010 */ TABDECL( OP_SWI),
-/* 1111 1011 0011 */ TABDECL( OP_SWI),
-/* 1111 1011 0100 */ TABDECL( OP_SWI),
-/* 1111 1011 0101 */ TABDECL( OP_SWI),
-/* 1111 1011 0110 */ TABDECL( OP_SWI),
-/* 1111 1011 0111 */ TABDECL( OP_SWI),
-/* 1111 1011 1000 */ TABDECL( OP_SWI),
-/* 1111 1011 1001 */ TABDECL( OP_SWI),
-/* 1111 1011 1010 */ TABDECL( OP_SWI),
-/* 1111 1011 1011 */ TABDECL( OP_SWI),
-/* 1111 1011 1100 */ TABDECL( OP_SWI),
-/* 1111 1011 1101 */ TABDECL( OP_SWI),
-/* 1111 1011 1110 */ TABDECL( OP_SWI),
-/* 1111 1011 1111 */ TABDECL( OP_SWI),
-/* 1111 1100 0000 */ TABDECL( OP_SWI),
-/* 1111 1100 0001 */ TABDECL( OP_SWI),
-/* 1111 1100 0010 */ TABDECL( OP_SWI),
-/* 1111 1100 0011 */ TABDECL( OP_SWI),
-/* 1111 1100 0100 */ TABDECL( OP_SWI),
-/* 1111 1100 0101 */ TABDECL( OP_SWI),
-/* 1111 1100 0110 */ TABDECL( OP_SWI),
-/* 1111 1100 0111 */ TABDECL( OP_SWI),
-/* 1111 1100 1000 */ TABDECL( OP_SWI),
-/* 1111 1100 1001 */ TABDECL( OP_SWI),
-/* 1111 1100 1010 */ TABDECL( OP_SWI),
-/* 1111 1100 1011 */ TABDECL( OP_SWI),
-/* 1111 1100 1100 */ TABDECL( OP_SWI),
-/* 1111 1100 1101 */ TABDECL( OP_SWI),
-/* 1111 1100 1110 */ TABDECL( OP_SWI),
-/* 1111 1100 1111 */ TABDECL( OP_SWI),
-/* 1111 1101 0000 */ TABDECL( OP_SWI),
-/* 1111 1101 0001 */ TABDECL( OP_SWI),
-/* 1111 1101 0010 */ TABDECL( OP_SWI),
-/* 1111 1101 0011 */ TABDECL( OP_SWI),
-/* 1111 1101 0100 */ TABDECL( OP_SWI),
-/* 1111 1101 0101 */ TABDECL( OP_SWI),
-/* 1111 1101 0110 */ TABDECL( OP_SWI),
-/* 1111 1101 0111 */ TABDECL( OP_SWI),
-/* 1111 1101 1000 */ TABDECL( OP_SWI),
-/* 1111 1101 1001 */ TABDECL( OP_SWI),
-/* 1111 1101 1010 */ TABDECL( OP_SWI),
-/* 1111 1101 1011 */ TABDECL( OP_SWI),
-/* 1111 1101 1100 */ TABDECL( OP_SWI),
-/* 1111 1101 1101 */ TABDECL( OP_SWI),
-/* 1111 1101 1110 */ TABDECL( OP_SWI),
-/* 1111 1101 1111 */ TABDECL( OP_SWI),
-/* 1111 1110 0000 */ TABDECL( OP_SWI),
-/* 1111 1110 0001 */ TABDECL( OP_SWI),
-/* 1111 1110 0010 */ TABDECL( OP_SWI),
-/* 1111 1110 0011 */ TABDECL( OP_SWI),
-/* 1111 1110 0100 */ TABDECL( OP_SWI),
-/* 1111 1110 0101 */ TABDECL( OP_SWI),
-/* 1111 1110 0110 */ TABDECL( OP_SWI),
-/* 1111 1110 0111 */ TABDECL( OP_SWI),
-/* 1111 1110 1000 */ TABDECL( OP_SWI),
-/* 1111 1110 1001 */ TABDECL( OP_SWI),
-/* 1111 1110 1010 */ TABDECL( OP_SWI),
-/* 1111 1110 1011 */ TABDECL( OP_SWI),
-/* 1111 1110 1100 */ TABDECL( OP_SWI),
-/* 1111 1110 1101 */ TABDECL( OP_SWI),
-/* 1111 1110 1110 */ TABDECL( OP_SWI),
-/* 1111 1110 1111 */ TABDECL( OP_SWI),
-/* 1111 1111 0000 */ TABDECL( OP_SWI),
-/* 1111 1111 0001 */ TABDECL( OP_SWI),
-/* 1111 1111 0010 */ TABDECL( OP_SWI),
-/* 1111 1111 0011 */ TABDECL( OP_SWI),
-/* 1111 1111 0100 */ TABDECL( OP_SWI),
-/* 1111 1111 0101 */ TABDECL( OP_SWI),
-/* 1111 1111 0110 */ TABDECL( OP_SWI),
-/* 1111 1111 0111 */ TABDECL( OP_SWI),
-/* 1111 1111 1000 */ TABDECL( OP_SWI),
-/* 1111 1111 1001 */ TABDECL( OP_SWI),
-/* 1111 1111 1010 */ TABDECL( OP_SWI),
-/* 1111 1111 1011 */ TABDECL( OP_SWI),
-/* 1111 1111 1100 */ TABDECL( OP_SWI),
-/* 1111 1111 1101 */ TABDECL( OP_SWI),
-/* 1111 1111 1110 */ TABDECL( OP_SWI),
-/* 1111 1111 1111 */ TABDECL( OP_SWI),
-
-
-
-
+/* 0000 0000 0000 */ TABDECL(OP_AND_LSL_IMM), // OP_AND_LSL_IMM
+/* 0000 0000 0001 */ TABDECL(OP_AND_LSL_REG), // OP_AND_LSL_REG
+/* 0000 0000 0010 */ TABDECL(OP_AND_LSR_IMM), // OP_AND_LSR_IMM
+/* 0000 0000 0011 */ TABDECL(OP_AND_LSR_REG), // OP_AND_LSR_REG
+/* 0000 0000 0100 */ TABDECL(OP_AND_ASR_IMM), // OP_AND_ASR_IMM
+/* 0000 0000 0101 */ TABDECL(OP_AND_ASR_REG), // OP_AND_ASR_REG
+/* 0000 0000 0110 */ TABDECL(OP_AND_ROR_IMM), // OP_AND_ROR_IMM
+/* 0000 0000 0111 */ TABDECL(OP_AND_ROR_REG), // OP_AND_ROR_REG
+/* 0000 0000 1000 */ TABDECL(OP_AND_LSL_IMM), // OP_AND_LSL_IMM
+/* 0000 0000 1001 */ TABDECL(OP_MUL), // OP_MUL
+/* 0000 0000 1010 */ TABDECL(OP_AND_LSR_IMM), // OP_AND_LSR_IMM
+/* 0000 0000 1011 */ TABDECL(OP_STRH_POS_INDE_M_REG_OFF), // OP_STRH_POS_INDE_M_REG_OFF
+/* 0000 0000 1100 */ TABDECL(OP_AND_ASR_IMM), // OP_AND_ASR_IMM
+/* 0000 0000 1101 */ TABDECL(OP_LDRD_STRD_POST_INDEX), // OP_LDRD_STRD_POST_INDEX
+/* 0000 0000 1110 */ TABDECL(OP_AND_ROR_IMM), // OP_AND_ROR_IMM
+/* 0000 0000 1111 */ TABDECL(OP_LDRD_STRD_POST_INDEX), // OP_LDRD_STRD_POST_INDEX
+
+/* 0000 0001 0000 */ TABDECL(OP_AND_S_LSL_IMM), // OP_AND_S_LSL_IMM
+/* 0000 0001 0001 */ TABDECL(OP_AND_S_LSL_REG), // OP_AND_S_LSL_REG
+/* 0000 0001 0010 */ TABDECL(OP_AND_S_LSR_IMM), // OP_AND_S_LSR_IMM
+/* 0000 0001 0011 */ TABDECL(OP_AND_S_LSR_REG), // OP_AND_S_LSR_REG
+/* 0000 0001 0100 */ TABDECL(OP_AND_S_ASR_IMM), // OP_AND_S_ASR_IMM
+/* 0000 0001 0101 */ TABDECL(OP_AND_S_ASR_REG), // OP_AND_S_ASR_REG
+/* 0000 0001 0110 */ TABDECL(OP_AND_S_ROR_IMM), // OP_AND_S_ROR_IMM
+/* 0000 0001 0111 */ TABDECL(OP_AND_S_ROR_REG), // OP_AND_S_ROR_REG
+/* 0000 0001 1000 */ TABDECL(OP_AND_S_LSL_IMM), // OP_AND_S_LSL_IMM
+/* 0000 0001 1001 */ TABDECL(OP_MUL_S), // OP_MUL_S
+/* 0000 0001 1010 */ TABDECL(OP_AND_S_LSR_IMM), // OP_AND_S_LSR_IMM
+/* 0000 0001 1011 */ TABDECL(OP_LDRH_POS_INDE_M_REG_OFF), // OP_LDRH_POS_INDE_M_REG_OFF
+/* 0000 0001 1100 */ TABDECL(OP_AND_S_ASR_IMM), // OP_AND_S_ASR_IMM
+/* 0000 0001 1101 */ TABDECL(OP_LDRSB_POS_INDE_M_REG_OFF), // OP_LDRSB_POS_INDE_M_REG_OFF
+/* 0000 0001 1110 */ TABDECL(OP_AND_S_ROR_IMM), // OP_AND_S_ROR_IMM
+/* 0000 0001 1111 */ TABDECL(OP_LDRSH_POS_INDE_M_REG_OFF), // OP_LDRSH_POS_INDE_M_REG_OFF
+
+/* 0000 0010 0000 */ TABDECL(OP_EOR_LSL_IMM), // OP_EOR_LSL_IMM
+/* 0000 0010 0001 */ TABDECL(OP_EOR_LSL_REG), // OP_EOR_LSL_REG
+/* 0000 0010 0010 */ TABDECL(OP_EOR_LSR_IMM), // OP_EOR_LSR_IMM
+/* 0000 0010 0011 */ TABDECL(OP_EOR_LSR_REG), // OP_EOR_LSR_REG
+/* 0000 0010 0100 */ TABDECL(OP_EOR_ASR_IMM), // OP_EOR_ASR_IMM
+/* 0000 0010 0101 */ TABDECL(OP_EOR_ASR_REG), // OP_EOR_ASR_REG
+/* 0000 0010 0110 */ TABDECL(OP_EOR_ROR_IMM), // OP_EOR_ROR_IMM
+/* 0000 0010 0111 */ TABDECL(OP_EOR_ROR_REG), // OP_EOR_ROR_REG
+/* 0000 0010 1000 */ TABDECL(OP_EOR_LSL_IMM), // OP_EOR_LSL_IMM
+/* 0000 0010 1001 */ TABDECL(OP_MLA), // OP_MLA
+/* 0000 0010 1010 */ TABDECL(OP_EOR_LSR_IMM), // OP_EOR_LSR_IMM
+/* 0000 0010 1011 */ TABDECL(OP_UND),
+/* 0000 0010 1100 */ TABDECL(OP_EOR_ASR_IMM), // OP_EOR_ASR_IMM
+/* 0000 0010 1101 */ TABDECL(OP_UND),
+/* 0000 0010 1110 */ TABDECL(OP_EOR_ROR_IMM), // OP_EOR_ROR_IMM
+/* 0000 0010 1111 */ TABDECL(OP_UND),
+
+/* 0000 0011 0000 */ TABDECL(OP_EOR_S_LSL_IMM), // OP_EOR_S_LSL_IMM
+/* 0000 0011 0001 */ TABDECL(OP_EOR_S_LSL_REG), // OP_EOR_S_LSL_REG
+/* 0000 0011 0010 */ TABDECL(OP_EOR_S_LSR_IMM), // OP_EOR_S_LSR_IMM
+/* 0000 0011 0011 */ TABDECL(OP_EOR_S_LSR_REG), // OP_EOR_S_LSR_REG
+/* 0000 0011 0100 */ TABDECL(OP_EOR_S_ASR_IMM), // OP_EOR_S_ASR_IMM
+/* 0000 0011 0101 */ TABDECL(OP_EOR_S_ASR_REG), // OP_EOR_S_ASR_REG
+/* 0000 0011 0110 */ TABDECL(OP_EOR_S_ROR_IMM), // OP_EOR_S_ROR_IMM
+/* 0000 0011 0111 */ TABDECL(OP_EOR_S_ROR_REG), // OP_EOR_S_ROR_REG
+/* 0000 0011 1000 */ TABDECL(OP_EOR_S_LSL_IMM), // OP_EOR_S_LSL_IMM
+/* 0000 0011 1001 */ TABDECL(OP_MLA_S), // OP_MLA_S
+/* 0000 0011 1010 */ TABDECL(OP_EOR_S_LSR_IMM), // OP_EOR_S_LSR_IMM
+/* 0000 0011 1011 */ TABDECL(OP_UND),
+/* 0000 0011 1100 */ TABDECL(OP_EOR_S_ASR_IMM), // OP_EOR_S_ASR_IMM
+/* 0000 0011 1101 */ TABDECL(OP_UND),
+/* 0000 0011 1110 */ TABDECL(OP_EOR_S_ROR_IMM), // OP_EOR_S_ROR_IMM
+/* 0000 0011 1111 */ TABDECL(OP_UND),
+
+/* 0000 0100 0000 */ TABDECL(OP_SUB_LSL_IMM), // OP_SUB_LSL_IMM
+/* 0000 0100 0001 */ TABDECL(OP_SUB_LSL_REG), // OP_SUB_LSL_REG
+/* 0000 0100 0010 */ TABDECL(OP_SUB_LSR_IMM), // OP_SUB_LSR_IMM
+/* 0000 0100 0011 */ TABDECL(OP_SUB_LSR_REG), // OP_SUB_LSR_REG
+/* 0000 0100 0100 */ TABDECL(OP_SUB_ASR_IMM), // OP_SUB_ASR_IMM
+/* 0000 0100 0101 */ TABDECL(OP_SUB_ASR_REG), // OP_SUB_ASR_REG
+/* 0000 0100 0110 */ TABDECL(OP_SUB_ROR_IMM), // OP_SUB_ROR_IMM
+/* 0000 0100 0111 */ TABDECL(OP_SUB_ROR_REG), // OP_SUB_ROR_REG
+/* 0000 0100 1000 */ TABDECL(OP_SUB_LSL_IMM), // OP_SUB_LSL_IMM
+/* 0000 0100 1001 */ TABDECL(OP_UND),
+/* 0000 0100 1010 */ TABDECL(OP_SUB_LSR_IMM), // OP_SUB_LSR_IMM
+/* 0000 0100 1011 */ TABDECL(OP_STRH_POS_INDE_M_IMM_OFF), // OP_STRH_POS_INDE_M_IMM_OFF
+/* 0000 0100 1100 */ TABDECL(OP_SUB_ASR_IMM), // OP_SUB_ASR_IMM
+/* 0000 0100 1101 */ TABDECL(OP_LDRD_STRD_POST_INDEX), // OP_LDRD_STRD_POST_INDEX
+/* 0000 0100 1110 */ TABDECL(OP_SUB_ROR_IMM), // OP_SUB_ROR_IMM
+/* 0000 0100 1111 */ TABDECL(OP_LDRD_STRD_POST_INDEX), // OP_LDRD_STRD_POST_INDEX
+
+/* 0000 0101 0000 */ TABDECL(OP_SUB_S_LSL_IMM), // OP_SUB_S_LSL_IMM
+/* 0000 0101 0001 */ TABDECL(OP_SUB_S_LSL_REG), // OP_SUB_S_LSL_REG
+/* 0000 0101 0010 */ TABDECL(OP_SUB_S_LSR_IMM), // OP_SUB_S_LSR_IMM
+/* 0000 0101 0011 */ TABDECL(OP_SUB_S_LSR_REG), // OP_SUB_S_LSR_REG
+/* 0000 0101 0100 */ TABDECL(OP_SUB_S_ASR_IMM), // OP_SUB_S_ASR_IMM
+/* 0000 0101 0101 */ TABDECL(OP_SUB_S_ASR_REG), // OP_SUB_S_ASR_REG
+/* 0000 0101 0110 */ TABDECL(OP_SUB_S_ROR_IMM), // OP_SUB_S_ROR_IMM
+/* 0000 0101 0111 */ TABDECL(OP_SUB_S_ROR_REG), // OP_SUB_S_ROR_REG
+/* 0000 0101 1000 */ TABDECL(OP_SUB_S_LSL_IMM), // OP_SUB_S_LSL_IMM
+/* 0000 0101 1001 */ TABDECL(OP_UND),
+/* 0000 0101 1010 */ TABDECL(OP_SUB_S_LSR_IMM), // OP_SUB_S_LSR_IMM
+/* 0000 0101 1011 */ TABDECL(OP_LDRH_POS_INDE_M_IMM_OFF), // OP_LDRH_POS_INDE_M_IMM_OFF
+/* 0000 0101 1100 */ TABDECL(OP_SUB_S_ASR_IMM), // OP_SUB_S_ASR_IMM
+/* 0000 0101 1101 */ TABDECL(OP_LDRSB_POS_INDE_M_IMM_OFF), // OP_LDRSB_POS_INDE_M_IMM_OFF
+/* 0000 0101 1110 */ TABDECL(OP_SUB_S_ROR_IMM), // OP_SUB_S_ROR_IMM
+/* 0000 0101 1111 */ TABDECL(OP_LDRSH_POS_INDE_M_IMM_OFF), // OP_LDRSH_POS_INDE_M_IMM_OFF
+
+/* 0000 0110 0000 */ TABDECL(OP_RSB_LSL_IMM), // OP_RSB_LSL_IMM
+/* 0000 0110 0001 */ TABDECL(OP_RSB_LSL_REG), // OP_RSB_LSL_REG
+/* 0000 0110 0010 */ TABDECL(OP_RSB_LSR_IMM), // OP_RSB_LSR_IMM
+/* 0000 0110 0011 */ TABDECL(OP_RSB_LSR_REG), // OP_RSB_LSR_REG
+/* 0000 0110 0100 */ TABDECL(OP_RSB_ASR_IMM), // OP_RSB_ASR_IMM
+/* 0000 0110 0101 */ TABDECL(OP_RSB_ASR_REG), // OP_RSB_ASR_REG
+/* 0000 0110 0110 */ TABDECL(OP_RSB_ROR_IMM), // OP_RSB_ROR_IMM
+/* 0000 0110 0111 */ TABDECL(OP_RSB_ROR_REG), // OP_RSB_ROR_REG
+/* 0000 0110 1000 */ TABDECL(OP_RSB_LSL_IMM), // OP_RSB_LSL_IMM
+/* 0000 0110 1001 */ TABDECL(OP_UND),
+/* 0000 0110 1010 */ TABDECL(OP_RSB_LSR_IMM), // OP_RSB_LSR_IMM
+/* 0000 0110 1011 */ TABDECL(OP_UND),
+/* 0000 0110 1100 */ TABDECL(OP_RSB_ASR_IMM), // OP_RSB_ASR_IMM
+/* 0000 0110 1101 */ TABDECL(OP_UND),
+/* 0000 0110 1110 */ TABDECL(OP_RSB_ROR_IMM), // OP_RSB_ROR_IMM
+/* 0000 0110 1111 */ TABDECL(OP_UND),
+
+/* 0000 0111 0000 */ TABDECL(OP_RSB_S_LSL_IMM), // OP_RSB_S_LSL_IMM
+/* 0000 0111 0001 */ TABDECL(OP_RSB_S_LSL_REG), // OP_RSB_S_LSL_REG
+/* 0000 0111 0010 */ TABDECL(OP_RSB_S_LSR_IMM), // OP_RSB_S_LSR_IMM
+/* 0000 0111 0011 */ TABDECL(OP_RSB_S_LSR_REG), // OP_RSB_S_LSR_REG
+/* 0000 0111 0100 */ TABDECL(OP_RSB_S_ASR_IMM), // OP_RSB_S_ASR_IMM
+/* 0000 0111 0101 */ TABDECL(OP_RSB_S_ASR_REG), // OP_RSB_S_ASR_REG
+/* 0000 0111 0110 */ TABDECL(OP_RSB_S_ROR_IMM), // OP_RSB_S_ROR_IMM
+/* 0000 0111 0111 */ TABDECL(OP_RSB_S_ROR_REG), // OP_RSB_S_ROR_REG
+/* 0000 0111 1000 */ TABDECL(OP_RSB_S_LSL_IMM), // OP_RSB_S_LSL_IMM
+/* 0000 0111 1001 */ TABDECL(OP_UND),
+/* 0000 0111 1010 */ TABDECL(OP_RSB_S_LSR_IMM), // OP_RSB_S_LSR_IMM
+/* 0000 0111 1011 */ TABDECL(OP_UND),
+/* 0000 0111 1100 */ TABDECL(OP_RSB_S_ASR_IMM), // OP_RSB_S_ASR_IMM
+/* 0000 0111 1101 */ TABDECL(OP_UND),
+/* 0000 0111 1110 */ TABDECL(OP_RSB_S_ROR_IMM), // OP_RSB_S_ROR_IMM
+/* 0000 0111 1111 */ TABDECL(OP_UND),
+
+/* 0000 1000 0000 */ TABDECL(OP_ADD_LSL_IMM), // OP_ADD_LSL_IMM
+/* 0000 1000 0001 */ TABDECL(OP_ADD_LSL_REG), // OP_ADD_LSL_REG
+/* 0000 1000 0010 */ TABDECL(OP_ADD_LSR_IMM), // OP_ADD_LSR_IMM
+/* 0000 1000 0011 */ TABDECL(OP_ADD_LSR_REG), // OP_ADD_LSR_REG
+/* 0000 1000 0100 */ TABDECL(OP_ADD_ASR_IMM), // OP_ADD_ASR_IMM
+/* 0000 1000 0101 */ TABDECL(OP_ADD_ASR_REG), // OP_ADD_ASR_REG
+/* 0000 1000 0110 */ TABDECL(OP_ADD_ROR_IMM), // OP_ADD_ROR_IMM
+/* 0000 1000 0111 */ TABDECL(OP_ADD_ROR_REG), // OP_ADD_ROR_REG
+/* 0000 1000 1000 */ TABDECL(OP_ADD_LSL_IMM), // OP_ADD_LSL_IMM
+/* 0000 1000 1001 */ TABDECL(OP_UMULL), // OP_UMULL
+/* 0000 1000 1010 */ TABDECL(OP_ADD_LSR_IMM), // OP_ADD_LSR_IMM
+/* 0000 1000 1011 */ TABDECL(OP_STRH_POS_INDE_P_REG_OFF), // OP_STRH_POS_INDE_P_REG_OFF
+/* 0000 1000 1100 */ TABDECL(OP_ADD_ASR_IMM), // OP_ADD_ASR_IMM
+/* 0000 1000 1101 */ TABDECL(OP_LDRD_STRD_POST_INDEX), // OP_LDRD_STRD_POST_INDEX
+/* 0000 1000 1110 */ TABDECL(OP_ADD_ROR_IMM), // OP_ADD_ROR_IMM
+/* 0000 1000 1111 */ TABDECL(OP_LDRD_STRD_POST_INDEX), // OP_LDRD_STRD_POST_INDEX
+
+/* 0000 1001 0000 */ TABDECL(OP_ADD_S_LSL_IMM), // OP_ADD_S_LSL_IMM
+/* 0000 1001 0001 */ TABDECL(OP_ADD_S_LSL_REG), // OP_ADD_S_LSL_REG
+/* 0000 1001 0010 */ TABDECL(OP_ADD_S_LSR_IMM), // OP_ADD_S_LSR_IMM
+/* 0000 1001 0011 */ TABDECL(OP_ADD_S_LSR_REG), // OP_ADD_S_LSR_REG
+/* 0000 1001 0100 */ TABDECL(OP_ADD_S_ASR_IMM), // OP_ADD_S_ASR_IMM
+/* 0000 1001 0101 */ TABDECL(OP_ADD_S_ASR_REG), // OP_ADD_S_ASR_REG
+/* 0000 1001 0110 */ TABDECL(OP_ADD_S_ROR_IMM), // OP_ADD_S_ROR_IMM
+/* 0000 1001 0111 */ TABDECL(OP_ADD_S_ROR_REG), // OP_ADD_S_ROR_REG
+/* 0000 1001 1000 */ TABDECL(OP_ADD_S_LSL_IMM), // OP_ADD_S_LSL_IMM
+/* 0000 1001 1001 */ TABDECL(OP_UMULL_S), // OP_UMULL_S
+/* 0000 1001 1010 */ TABDECL(OP_ADD_S_LSR_IMM), // OP_ADD_S_LSR_IMM
+/* 0000 1001 1011 */ TABDECL(OP_LDRH_POS_INDE_P_REG_OFF), // OP_LDRH_POS_INDE_P_REG_OFF
+/* 0000 1001 1100 */ TABDECL(OP_ADD_S_ASR_IMM), // OP_ADD_S_ASR_IMM
+/* 0000 1001 1101 */ TABDECL(OP_LDRSB_POS_INDE_P_REG_OFF), // OP_LDRSB_POS_INDE_P_REG_OFF
+/* 0000 1001 1110 */ TABDECL(OP_ADD_S_ROR_IMM), // OP_ADD_S_ROR_IMM
+/* 0000 1001 1111 */ TABDECL(OP_LDRSH_POS_INDE_P_REG_OFF), // OP_LDRSH_POS_INDE_P_REG_OFF
+
+/* 0000 1010 0000 */ TABDECL(OP_ADC_LSL_IMM), // OP_ADC_LSL_IMM
+/* 0000 1010 0001 */ TABDECL(OP_ADC_LSL_REG), // OP_ADC_LSL_REG
+/* 0000 1010 0010 */ TABDECL(OP_ADC_LSR_IMM), // OP_ADC_LSR_IMM
+/* 0000 1010 0011 */ TABDECL(OP_ADC_LSR_REG), // OP_ADC_LSR_REG
+/* 0000 1010 0100 */ TABDECL(OP_ADC_ASR_IMM), // OP_ADC_ASR_IMM
+/* 0000 1010 0101 */ TABDECL(OP_ADC_ASR_REG), // OP_ADC_ASR_REG
+/* 0000 1010 0110 */ TABDECL(OP_ADC_ROR_IMM), // OP_ADC_ROR_IMM
+/* 0000 1010 0111 */ TABDECL(OP_ADC_ROR_REG), // OP_ADC_ROR_REG
+/* 0000 1010 1000 */ TABDECL(OP_ADC_LSL_IMM), // OP_ADC_LSL_IMM
+/* 0000 1010 1001 */ TABDECL(OP_UMLAL), // OP_UMLAL
+/* 0000 1010 1010 */ TABDECL(OP_ADC_LSR_IMM), // OP_ADC_LSR_IMM
+/* 0000 1010 1011 */ TABDECL(OP_UND),
+/* 0000 1010 1100 */ TABDECL(OP_ADC_ASR_IMM), // OP_ADC_ASR_IMM
+/* 0000 1010 1101 */ TABDECL(OP_UND),
+/* 0000 1010 1110 */ TABDECL(OP_ADC_ROR_IMM), // OP_ADC_ROR_IMM
+/* 0000 1010 1111 */ TABDECL(OP_UND),
+
+/* 0000 1011 0000 */ TABDECL(OP_ADC_S_LSL_IMM), // OP_ADC_S_LSL_IMM
+/* 0000 1011 0001 */ TABDECL(OP_ADC_S_LSL_REG), // OP_ADC_S_LSL_REG
+/* 0000 1011 0010 */ TABDECL(OP_ADC_S_LSR_IMM), // OP_ADC_S_LSR_IMM
+/* 0000 1011 0011 */ TABDECL(OP_ADC_S_LSR_REG), // OP_ADC_S_LSR_REG
+/* 0000 1011 0100 */ TABDECL(OP_ADC_S_ASR_IMM), // OP_ADC_S_ASR_IMM
+/* 0000 1011 0101 */ TABDECL(OP_ADC_S_ASR_REG), // OP_ADC_S_ASR_REG
+/* 0000 1011 0110 */ TABDECL(OP_ADC_S_ROR_IMM), // OP_ADC_S_ROR_IMM
+/* 0000 1011 0111 */ TABDECL(OP_ADC_S_ROR_REG), // OP_ADC_S_ROR_REG
+/* 0000 1011 1000 */ TABDECL(OP_ADC_S_LSL_IMM), // OP_ADC_S_LSL_IMM
+/* 0000 1011 1001 */ TABDECL(OP_UMLAL_S), // OP_UMLAL_S
+/* 0000 1011 1010 */ TABDECL(OP_ADC_S_LSR_IMM), // OP_ADC_S_LSR_IMM
+/* 0000 1011 1011 */ TABDECL(OP_UND),
+/* 0000 1011 1100 */ TABDECL(OP_ADC_S_ASR_IMM), // OP_ADC_S_ASR_IMM
+/* 0000 1011 1101 */ TABDECL(OP_UND),
+/* 0000 1011 1110 */ TABDECL(OP_ADC_S_ROR_IMM), // OP_ADC_S_ROR_IMM
+/* 0000 1011 1111 */ TABDECL(OP_UND),
+
+/* 0000 1100 0000 */ TABDECL(OP_SBC_LSL_IMM), // OP_SBC_LSL_IMM
+/* 0000 1100 0001 */ TABDECL(OP_SBC_LSL_REG), // OP_SBC_LSL_REG
+/* 0000 1100 0010 */ TABDECL(OP_SBC_LSR_IMM), // OP_SBC_LSR_IMM
+/* 0000 1100 0011 */ TABDECL(OP_SBC_LSR_REG), // OP_SBC_LSR_REG
+/* 0000 1100 0100 */ TABDECL(OP_SBC_ASR_IMM), // OP_SBC_ASR_IMM
+/* 0000 1100 0101 */ TABDECL(OP_SBC_ASR_REG), // OP_SBC_ASR_REG
+/* 0000 1100 0110 */ TABDECL(OP_SBC_ROR_IMM), // OP_SBC_ROR_IMM
+/* 0000 1100 0111 */ TABDECL(OP_SBC_ROR_REG), // OP_SBC_ROR_REG
+/* 0000 1100 1000 */ TABDECL(OP_SBC_LSL_IMM), // OP_SBC_LSL_IMM
+/* 0000 1100 1001 */ TABDECL(OP_SMULL), // OP_SMULL
+/* 0000 1100 1010 */ TABDECL(OP_SBC_LSR_IMM), // OP_SBC_LSR_IMM
+/* 0000 1100 1011 */ TABDECL(OP_STRH_POS_INDE_P_IMM_OFF), // OP_STRH_POS_INDE_P_IMM_OFF
+/* 0000 1100 1100 */ TABDECL(OP_SBC_ASR_IMM), // OP_SBC_ASR_IMM
+/* 0000 1100 1101 */ TABDECL(OP_LDRD_STRD_POST_INDEX), // OP_LDRD_STRD_POST_INDEX
+/* 0000 1100 1110 */ TABDECL(OP_SBC_ROR_IMM), // OP_SBC_ROR_IMM
+/* 0000 1100 1111 */ TABDECL(OP_LDRD_STRD_POST_INDEX), // OP_LDRD_STRD_POST_INDEX
+
+/* 0000 1101 0000 */ TABDECL(OP_SBC_S_LSL_IMM), // OP_SBC_S_LSL_IMM
+/* 0000 1101 0001 */ TABDECL(OP_SBC_S_LSL_REG), // OP_SBC_S_LSL_REG
+/* 0000 1101 0010 */ TABDECL(OP_SBC_S_LSR_IMM), // OP_SBC_S_LSR_IMM
+/* 0000 1101 0011 */ TABDECL(OP_SBC_S_LSR_REG), // OP_SBC_S_LSR_REG
+/* 0000 1101 0100 */ TABDECL(OP_SBC_S_ASR_IMM), // OP_SBC_S_ASR_IMM
+/* 0000 1101 0101 */ TABDECL(OP_SBC_S_ASR_REG), // OP_SBC_S_ASR_REG
+/* 0000 1101 0110 */ TABDECL(OP_SBC_S_ROR_IMM), // OP_SBC_S_ROR_IMM
+/* 0000 1101 0111 */ TABDECL(OP_SBC_S_ROR_REG), // OP_SBC_S_ROR_REG
+/* 0000 1101 1000 */ TABDECL(OP_SBC_S_LSL_IMM), // OP_SBC_S_LSL_IMM
+/* 0000 1101 1001 */ TABDECL(OP_SMULL_S), // OP_SMULL_S
+/* 0000 1101 1010 */ TABDECL(OP_SBC_S_LSR_IMM), // OP_SBC_S_LSR_IMM
+/* 0000 1101 1011 */ TABDECL(OP_LDRH_POS_INDE_P_IMM_OFF), // OP_LDRH_POS_INDE_P_IMM_OFF
+/* 0000 1101 1100 */ TABDECL(OP_SBC_S_ASR_IMM), // OP_SBC_S_ASR_IMM
+/* 0000 1101 1101 */ TABDECL(OP_LDRSB_POS_INDE_P_IMM_OFF), // OP_LDRSB_POS_INDE_P_IMM_OFF
+/* 0000 1101 1110 */ TABDECL(OP_SBC_S_ROR_IMM), // OP_SBC_S_ROR_IMM
+/* 0000 1101 1111 */ TABDECL(OP_LDRSH_POS_INDE_P_IMM_OFF), // OP_LDRSH_POS_INDE_P_IMM_OFF
+
+/* 0000 1110 0000 */ TABDECL(OP_RSC_LSL_IMM), // OP_RSC_LSL_IMM
+/* 0000 1110 0001 */ TABDECL(OP_RSC_LSL_REG), // OP_RSC_LSL_REG
+/* 0000 1110 0010 */ TABDECL(OP_RSC_LSR_IMM), // OP_RSC_LSR_IMM
+/* 0000 1110 0011 */ TABDECL(OP_RSC_LSR_REG), // OP_RSC_LSR_REG
+/* 0000 1110 0100 */ TABDECL(OP_RSC_ASR_IMM), // OP_RSC_ASR_IMM
+/* 0000 1110 0101 */ TABDECL(OP_RSC_ASR_REG), // OP_RSC_ASR_REG
+/* 0000 1110 0110 */ TABDECL(OP_RSC_ROR_IMM), // OP_RSC_ROR_IMM
+/* 0000 1110 0111 */ TABDECL(OP_RSC_ROR_REG), // OP_RSC_ROR_REG
+/* 0000 1110 1000 */ TABDECL(OP_RSC_LSL_IMM), // OP_RSC_LSL_IMM
+/* 0000 1110 1001 */ TABDECL(OP_SMLAL), // OP_SMLAL
+/* 0000 1110 1010 */ TABDECL(OP_RSC_LSR_IMM), // OP_RSC_LSR_IMM
+/* 0000 1110 1011 */ TABDECL(OP_UND),
+/* 0000 1110 1100 */ TABDECL(OP_RSC_ASR_IMM), // OP_RSC_ASR_IMM
+/* 0000 1110 1101 */ TABDECL(OP_UND),
+/* 0000 1110 1110 */ TABDECL(OP_RSC_ROR_IMM), // OP_RSC_ROR_IMM
+/* 0000 1110 1111 */ TABDECL(OP_UND),
+
+/* 0000 1111 0000 */ TABDECL(OP_RSC_S_LSL_IMM), // OP_RSC_S_LSL_IMM
+/* 0000 1111 0001 */ TABDECL(OP_RSC_S_LSL_REG), // OP_RSC_S_LSL_REG
+/* 0000 1111 0010 */ TABDECL(OP_RSC_S_LSR_IMM), // OP_RSC_S_LSR_IMM
+/* 0000 1111 0011 */ TABDECL(OP_RSC_S_LSR_REG), // OP_RSC_S_LSR_REG
+/* 0000 1111 0100 */ TABDECL(OP_RSC_S_ASR_IMM), // OP_RSC_S_ASR_IMM
+/* 0000 1111 0101 */ TABDECL(OP_RSC_S_ASR_REG), // OP_RSC_S_ASR_REG
+/* 0000 1111 0110 */ TABDECL(OP_RSC_S_ROR_IMM), // OP_RSC_S_ROR_IMM
+/* 0000 1111 0111 */ TABDECL(OP_RSC_S_ROR_REG), // OP_RSC_S_ROR_REG
+/* 0000 1111 1000 */ TABDECL(OP_RSC_S_LSL_IMM), // OP_RSC_S_LSL_IMM
+/* 0000 1111 1001 */ TABDECL(OP_SMLAL_S), // OP_SMLAL_S
+/* 0000 1111 1010 */ TABDECL(OP_RSC_S_LSR_IMM), // OP_RSC_S_LSR_IMM
+/* 0000 1111 1011 */ TABDECL(OP_UND),
+/* 0000 1111 1100 */ TABDECL(OP_RSC_S_ASR_IMM), // OP_RSC_S_ASR_IMM
+/* 0000 1111 1101 */ TABDECL(OP_UND),
+/* 0000 1111 1110 */ TABDECL(OP_RSC_S_ROR_IMM), // OP_RSC_S_ROR_IMM
+/* 0000 1111 1111 */ TABDECL(OP_UND),
+
+/* 0001 0000 0000 */ TABDECL(OP_MRS_CPSR), // OP_MRS_CPSR
+/* 0001 0000 0001 */ TABDECL(OP_UND),
+/* 0001 0000 0010 */ TABDECL(OP_UND),
+/* 0001 0000 0011 */ TABDECL(OP_UND),
+/* 0001 0000 0100 */ TABDECL(OP_UND),
+/* 0001 0000 0101 */ TABDECL(OP_QADD), // OP_QADD
+/* 0001 0000 0110 */ TABDECL(OP_UND),
+/* 0001 0000 0111 */ TABDECL(OP_UND),
+/* 0001 0000 1000 */ TABDECL(OP_SMLA_B_B), // OP_SMLA_B_B
+/* 0001 0000 1001 */ TABDECL(OP_SWP), // OP_SWP
+/* 0001 0000 1010 */ TABDECL(OP_SMLA_T_B), // OP_SMLA_T_B
+/* 0001 0000 1011 */ TABDECL(OP_STRH_M_REG_OFF), // OP_STRH_M_REG_OFF
+/* 0001 0000 1100 */ TABDECL(OP_SMLA_B_T), // OP_SMLA_B_T
+/* 0001 0000 1101 */ TABDECL(OP_LDRD_STRD_OFFSET_PRE_INDEX), // OP_LDRD_STRD_OFFSET_PRE_INDEX
+/* 0001 0000 1110 */ TABDECL(OP_SMLA_T_T), // OP_SMLA_T_T
+/* 0001 0000 1111 */ TABDECL(OP_LDRD_STRD_OFFSET_PRE_INDEX), // OP_LDRD_STRD_OFFSET_PRE_INDEX
+
+/* 0001 0001 0000 */ TABDECL(OP_TST_LSL_IMM), // OP_TST_LSL_IMM
+/* 0001 0001 0001 */ TABDECL(OP_TST_LSL_REG), // OP_TST_LSL_REG
+/* 0001 0001 0010 */ TABDECL(OP_TST_LSR_IMM), // OP_TST_LSR_IMM
+/* 0001 0001 0011 */ TABDECL(OP_TST_LSR_REG), // OP_TST_LSR_REG
+/* 0001 0001 0100 */ TABDECL(OP_TST_ASR_IMM), // OP_TST_ASR_IMM
+/* 0001 0001 0101 */ TABDECL(OP_TST_ASR_REG), // OP_TST_ASR_REG
+/* 0001 0001 0110 */ TABDECL(OP_TST_ROR_IMM), // OP_TST_ROR_IMM
+/* 0001 0001 0111 */ TABDECL(OP_TST_ROR_REG), // OP_TST_ROR_REG
+/* 0001 0001 1000 */ TABDECL(OP_TST_LSL_IMM), // OP_TST_LSL_IMM
+/* 0001 0001 1001 */ TABDECL(OP_UND),
+/* 0001 0001 1010 */ TABDECL(OP_TST_LSR_IMM), // OP_TST_LSR_IMM
+/* 0001 0001 1011 */ TABDECL(OP_LDRH_M_REG_OFF), // OP_LDRH_M_REG_OFF
+/* 0001 0001 1100 */ TABDECL(OP_TST_ASR_IMM), // OP_TST_ASR_IMM
+/* 0001 0001 1101 */ TABDECL(OP_LDRSB_M_REG_OFF), // OP_LDRSB_M_REG_OFF
+/* 0001 0001 1110 */ TABDECL(OP_TST_ROR_IMM), // OP_TST_ROR_IMM
+/* 0001 0001 1111 */ TABDECL(OP_LDRSH_M_REG_OFF), // OP_LDRSH_M_REG_OFF
+
+/* 0001 0010 0000 */ TABDECL(OP_MSR_CPSR), // OP_MSR_CPSR
+/* 0001 0010 0001 */ TABDECL(OP_BX), // OP_BX
+/* 0001 0010 0010 */ TABDECL(OP_UND),
+/* 0001 0010 0011 */ TABDECL(OP_BLX_REG), // OP_BLX_REG
+/* 0001 0010 0100 */ TABDECL(OP_UND),
+/* 0001 0010 0101 */ TABDECL(OP_QSUB), // OP_QSUB
+/* 0001 0010 0110 */ TABDECL(OP_UND),
+/* 0001 0010 0111 */ TABDECL(OP_BKPT), // OP_BKPT
+/* 0001 0010 1000 */ TABDECL(OP_SMLAW_B), // OP_SMLAW_B
+/* 0001 0010 1001 */ TABDECL(OP_UND),
+/* 0001 0010 1010 */ TABDECL(OP_SMULW_B), // OP_SMULW_B
+/* 0001 0010 1011 */ TABDECL(OP_STRH_PRE_INDE_M_REG_OFF), // OP_STRH_PRE_INDE_M_REG_OFF
+/* 0001 0010 1100 */ TABDECL(OP_SMLAW_T), // OP_SMLAW_T
+/* 0001 0010 1101 */ TABDECL(OP_LDRD_STRD_OFFSET_PRE_INDEX), // OP_LDRD_STRD_OFFSET_PRE_INDEX
+/* 0001 0010 1110 */ TABDECL(OP_SMULW_T), // OP_SMULW_T
+/* 0001 0010 1111 */ TABDECL(OP_LDRD_STRD_OFFSET_PRE_INDEX), // OP_LDRD_STRD_OFFSET_PRE_INDEX
+
+/* 0001 0011 0000 */ TABDECL(OP_TEQ_LSL_IMM), // OP_TEQ_LSL_IMM
+/* 0001 0011 0001 */ TABDECL(OP_TEQ_LSL_REG), // OP_TEQ_LSL_REG
+/* 0001 0011 0010 */ TABDECL(OP_TEQ_LSR_IMM), // OP_TEQ_LSR_IMM
+/* 0001 0011 0011 */ TABDECL(OP_TEQ_LSR_REG), // OP_TEQ_LSR_REG
+/* 0001 0011 0100 */ TABDECL(OP_TEQ_ASR_IMM), // OP_TEQ_ASR_IMM
+/* 0001 0011 0101 */ TABDECL(OP_TEQ_ASR_REG), // OP_TEQ_ASR_REG
+/* 0001 0011 0110 */ TABDECL(OP_TEQ_ROR_IMM), // OP_TEQ_ROR_IMM
+/* 0001 0011 0111 */ TABDECL(OP_TEQ_ROR_REG), // OP_TEQ_ROR_REG
+/* 0001 0011 1000 */ TABDECL(OP_TEQ_LSL_IMM), // OP_TEQ_LSL_IMM
+/* 0001 0011 1001 */ TABDECL(OP_UND),
+/* 0001 0011 1010 */ TABDECL(OP_TEQ_LSR_IMM), // OP_TEQ_LSR_IMM
+/* 0001 0011 1011 */ TABDECL(OP_LDRH_PRE_INDE_M_REG_OFF), // OP_LDRH_PRE_INDE_M_REG_OFF
+/* 0001 0011 1100 */ TABDECL(OP_TEQ_ASR_IMM), // OP_TEQ_ASR_IMM
+/* 0001 0011 1101 */ TABDECL(OP_LDRSB_PRE_INDE_M_REG_OFF), // OP_LDRSB_PRE_INDE_M_REG_OFF
+/* 0001 0011 1110 */ TABDECL(OP_TEQ_ROR_IMM), // OP_TEQ_ROR_IMM
+/* 0001 0011 1111 */ TABDECL(OP_LDRSH_PRE_INDE_M_REG_OFF), // OP_LDRSH_PRE_INDE_M_REG_OFF
+
+/* 0001 0100 0000 */ TABDECL(OP_MRS_SPSR), // OP_MRS_SPSR
+/* 0001 0100 0001 */ TABDECL(OP_UND),
+/* 0001 0100 0010 */ TABDECL(OP_UND),
+/* 0001 0100 0011 */ TABDECL(OP_UND),
+/* 0001 0100 0100 */ TABDECL(OP_UND),
+/* 0001 0100 0101 */ TABDECL(OP_QDADD), // OP_QDADD
+/* 0001 0100 0110 */ TABDECL(OP_UND),
+/* 0001 0100 0111 */ TABDECL(OP_UND),
+/* 0001 0100 1000 */ TABDECL(OP_SMLAL_B_B), // OP_SMLAL_B_B
+/* 0001 0100 1001 */ TABDECL(OP_SWPB), // OP_SWPB
+/* 0001 0100 1010 */ TABDECL(OP_SMLAL_T_B), // OP_SMLAL_T_B
+/* 0001 0100 1011 */ TABDECL(OP_STRH_M_IMM_OFF), // OP_STRH_M_IMM_OFF
+/* 0001 0100 1100 */ TABDECL(OP_SMLAL_B_T), // OP_SMLAL_B_T
+/* 0001 0100 1101 */ TABDECL(OP_LDRD_STRD_OFFSET_PRE_INDEX), // OP_LDRD_STRD_OFFSET_PRE_INDEX
+/* 0001 0100 1110 */ TABDECL(OP_SMLAL_T_T), // OP_SMLAL_T_T
+/* 0001 0100 1111 */ TABDECL(OP_LDRD_STRD_OFFSET_PRE_INDEX), // OP_LDRD_STRD_OFFSET_PRE_INDEX
+
+/* 0001 0101 0000 */ TABDECL(OP_CMP_LSL_IMM), // OP_CMP_LSL_IMM
+/* 0001 0101 0001 */ TABDECL(OP_CMP_LSL_REG), // OP_CMP_LSL_REG
+/* 0001 0101 0010 */ TABDECL(OP_CMP_LSR_IMM), // OP_CMP_LSR_IMM
+/* 0001 0101 0011 */ TABDECL(OP_CMP_LSR_REG), // OP_CMP_LSR_REG
+/* 0001 0101 0100 */ TABDECL(OP_CMP_ASR_IMM), // OP_CMP_ASR_IMM
+/* 0001 0101 0101 */ TABDECL(OP_CMP_ASR_REG), // OP_CMP_ASR_REG
+/* 0001 0101 0110 */ TABDECL(OP_CMP_ROR_IMM), // OP_CMP_ROR_IMM
+/* 0001 0101 0111 */ TABDECL(OP_CMP_ROR_REG), // OP_CMP_ROR_REG
+/* 0001 0101 1000 */ TABDECL(OP_CMP_LSL_IMM), // OP_CMP_LSL_IMM
+/* 0001 0101 1001 */ TABDECL(OP_UND),
+/* 0001 0101 1010 */ TABDECL(OP_CMP_LSR_IMM), // OP_CMP_LSR_IMM
+/* 0001 0101 1011 */ TABDECL(OP_LDRH_M_IMM_OFF), // OP_LDRH_M_IMM_OFF
+/* 0001 0101 1100 */ TABDECL(OP_CMP_ASR_IMM), // OP_CMP_ASR_IMM
+/* 0001 0101 1101 */ TABDECL(OP_LDRSB_M_IMM_OFF), // OP_LDRSB_M_IMM_OFF
+/* 0001 0101 1110 */ TABDECL(OP_CMP_ROR_IMM), // OP_CMP_ROR_IMM
+/* 0001 0101 1111 */ TABDECL(OP_LDRSH_M_IMM_OFF), // OP_LDRSH_M_IMM_OFF
+
+/* 0001 0110 0000 */ TABDECL(OP_MSR_SPSR), // OP_MSR_SPSR
+/* 0001 0110 0001 */ TABDECL(OP_CLZ), // OP_CLZ
+/* 0001 0110 0010 */ TABDECL(OP_UND),
+/* 0001 0110 0011 */ TABDECL(OP_UND),
+/* 0001 0110 0100 */ TABDECL(OP_UND),
+/* 0001 0110 0101 */ TABDECL(OP_QDSUB), // OP_QDSUB
+/* 0001 0110 0110 */ TABDECL(OP_UND),
+/* 0001 0110 0111 */ TABDECL(OP_UND),
+/* 0001 0110 1000 */ TABDECL(OP_SMUL_B_B), // OP_SMUL_B_B
+/* 0001 0110 1001 */ TABDECL(OP_UND),
+/* 0001 0110 1010 */ TABDECL(OP_SMUL_T_B), // OP_SMUL_T_B
+/* 0001 0110 1011 */ TABDECL(OP_STRH_PRE_INDE_M_IMM_OFF), // OP_STRH_PRE_INDE_M_IMM_OFF
+/* 0001 0110 1100 */ TABDECL(OP_SMUL_B_T), // OP_SMUL_B_T
+/* 0001 0110 1101 */ TABDECL(OP_LDRD_STRD_OFFSET_PRE_INDEX), // OP_LDRD_STRD_OFFSET_PRE_INDEX
+/* 0001 0110 1110 */ TABDECL(OP_SMUL_T_T), // OP_SMUL_T_T
+/* 0001 0110 1111 */ TABDECL(OP_LDRD_STRD_OFFSET_PRE_INDEX), // OP_LDRD_STRD_OFFSET_PRE_INDEX
+
+/* 0001 0111 0000 */ TABDECL(OP_CMN_LSL_IMM), // OP_CMN_LSL_IMM
+/* 0001 0111 0001 */ TABDECL(OP_CMN_LSL_REG), // OP_CMN_LSL_REG
+/* 0001 0111 0010 */ TABDECL(OP_CMN_LSR_IMM), // OP_CMN_LSR_IMM
+/* 0001 0111 0011 */ TABDECL(OP_CMN_LSR_REG), // OP_CMN_LSR_REG
+/* 0001 0111 0100 */ TABDECL(OP_CMN_ASR_IMM), // OP_CMN_ASR_IMM
+/* 0001 0111 0101 */ TABDECL(OP_CMN_ASR_REG), // OP_CMN_ASR_REG
+/* 0001 0111 0110 */ TABDECL(OP_CMN_ROR_IMM), // OP_CMN_ROR_IMM
+/* 0001 0111 0111 */ TABDECL(OP_CMN_ROR_REG), // OP_CMN_ROR_REG
+/* 0001 0111 1000 */ TABDECL(OP_CMN_LSL_IMM), // OP_CMN_LSL_IMM
+/* 0001 0111 1001 */ TABDECL(OP_UND),
+/* 0001 0111 1010 */ TABDECL(OP_CMN_LSR_IMM), // OP_CMN_LSR_IMM
+/* 0001 0111 1011 */ TABDECL(OP_LDRH_PRE_INDE_M_IMM_OFF), // OP_LDRH_PRE_INDE_M_IMM_OFF
+/* 0001 0111 1100 */ TABDECL(OP_CMN_ASR_IMM), // OP_CMN_ASR_IMM
+/* 0001 0111 1101 */ TABDECL(OP_LDRSB_PRE_INDE_M_IMM_OFF), // OP_LDRSB_PRE_INDE_M_IMM_OFF
+/* 0001 0111 1110 */ TABDECL(OP_CMN_ROR_IMM), // OP_CMN_ROR_IMM
+/* 0001 0111 1111 */ TABDECL(OP_LDRSH_PRE_INDE_M_IMM_OFF), // OP_LDRSH_PRE_INDE_M_IMM_OFF
+
+/* 0001 1000 0000 */ TABDECL(OP_ORR_LSL_IMM), // OP_ORR_LSL_IMM
+/* 0001 1000 0001 */ TABDECL(OP_ORR_LSL_REG), // OP_ORR_LSL_REG
+/* 0001 1000 0010 */ TABDECL(OP_ORR_LSR_IMM), // OP_ORR_LSR_IMM
+/* 0001 1000 0011 */ TABDECL(OP_ORR_LSR_REG), // OP_ORR_LSR_REG
+/* 0001 1000 0100 */ TABDECL(OP_ORR_ASR_IMM), // OP_ORR_ASR_IMM
+/* 0001 1000 0101 */ TABDECL(OP_ORR_ASR_REG), // OP_ORR_ASR_REG
+/* 0001 1000 0110 */ TABDECL(OP_ORR_ROR_IMM), // OP_ORR_ROR_IMM
+/* 0001 1000 0111 */ TABDECL(OP_ORR_ROR_REG), // OP_ORR_ROR_REG
+/* 0001 1000 1000 */ TABDECL(OP_ORR_LSL_IMM), // OP_ORR_LSL_IMM
+/* 0001 1000 1001 */ TABDECL(OP_STREX), // OP_STREX
+/* 0001 1000 1010 */ TABDECL(OP_ORR_LSR_IMM), // OP_ORR_LSR_IMM
+/* 0001 1000 1011 */ TABDECL(OP_STRH_P_REG_OFF), // OP_STRH_P_REG_OFF
+/* 0001 1000 1100 */ TABDECL(OP_ORR_ASR_IMM), // OP_ORR_ASR_IMM
+/* 0001 1000 1101 */ TABDECL(OP_LDRD_STRD_OFFSET_PRE_INDEX), // OP_LDRD_STRD_OFFSET_PRE_INDEX
+/* 0001 1000 1110 */ TABDECL(OP_ORR_ROR_IMM), // OP_ORR_ROR_IMM
+/* 0001 1000 1111 */ TABDECL(OP_LDRD_STRD_OFFSET_PRE_INDEX), // OP_LDRD_STRD_OFFSET_PRE_INDEX
+
+/* 0001 1001 0000 */ TABDECL(OP_ORR_S_LSL_IMM), // OP_ORR_S_LSL_IMM
+/* 0001 1001 0001 */ TABDECL(OP_ORR_S_LSL_REG), // OP_ORR_S_LSL_REG
+/* 0001 1001 0010 */ TABDECL(OP_ORR_S_LSR_IMM), // OP_ORR_S_LSR_IMM
+/* 0001 1001 0011 */ TABDECL(OP_ORR_S_LSR_REG), // OP_ORR_S_LSR_REG
+/* 0001 1001 0100 */ TABDECL(OP_ORR_S_ASR_IMM), // OP_ORR_S_ASR_IMM
+/* 0001 1001 0101 */ TABDECL(OP_ORR_S_ASR_REG), // OP_ORR_S_ASR_REG
+/* 0001 1001 0110 */ TABDECL(OP_ORR_S_ROR_IMM), // OP_ORR_S_ROR_IMM
+/* 0001 1001 0111 */ TABDECL(OP_ORR_S_ROR_REG), // OP_ORR_S_ROR_REG
+/* 0001 1001 1000 */ TABDECL(OP_ORR_S_LSL_IMM), // OP_ORR_S_LSL_IMM
+/* 0001 1001 1001 */ TABDECL(OP_LDREX), // OP_LDREX
+/* 0001 1001 1010 */ TABDECL(OP_ORR_S_LSR_IMM), // OP_ORR_S_LSR_IMM
+/* 0001 1001 1011 */ TABDECL(OP_LDRH_P_REG_OFF), // OP_LDRH_P_REG_OFF
+/* 0001 1001 1100 */ TABDECL(OP_ORR_S_ASR_IMM), // OP_ORR_S_ASR_IMM
+/* 0001 1001 1101 */ TABDECL(OP_LDRSB_P_REG_OFF), // OP_LDRSB_P_REG_OFF
+/* 0001 1001 1110 */ TABDECL(OP_ORR_S_ROR_IMM), // OP_ORR_S_ROR_IMM
+/* 0001 1001 1111 */ TABDECL(OP_LDRSH_P_REG_OFF), // OP_LDRSH_P_REG_OFF
+
+/* 0001 1010 0000 */ TABDECL(OP_MOV_LSL_IMM), // OP_MOV_LSL_IMM
+/* 0001 1010 0001 */ TABDECL(OP_MOV_LSL_REG), // OP_MOV_LSL_REG
+/* 0001 1010 0010 */ TABDECL(OP_MOV_LSR_IMM), // OP_MOV_LSR_IMM
+/* 0001 1010 0011 */ TABDECL(OP_MOV_LSR_REG), // OP_MOV_LSR_REG
+/* 0001 1010 0100 */ TABDECL(OP_MOV_ASR_IMM), // OP_MOV_ASR_IMM
+/* 0001 1010 0101 */ TABDECL(OP_MOV_ASR_REG), // OP_MOV_ASR_REG
+/* 0001 1010 0110 */ TABDECL(OP_MOV_ROR_IMM), // OP_MOV_ROR_IMM
+/* 0001 1010 0111 */ TABDECL(OP_MOV_ROR_REG), // OP_MOV_ROR_REG
+/* 0001 1010 1000 */ TABDECL(OP_MOV_LSL_IMM), // OP_MOV_LSL_IMM
+/* 0001 1010 1001 */ TABDECL(OP_UND),
+/* 0001 1010 1010 */ TABDECL(OP_MOV_LSR_IMM), // OP_MOV_LSR_IMM
+/* 0001 1010 1011 */ TABDECL(OP_STRH_PRE_INDE_P_REG_OFF), // OP_STRH_PRE_INDE_P_REG_OFF
+/* 0001 1010 1100 */ TABDECL(OP_MOV_ASR_IMM), // OP_MOV_ASR_IMM
+/* 0001 1010 1101 */ TABDECL(OP_LDRD_STRD_OFFSET_PRE_INDEX), // OP_LDRD_STRD_OFFSET_PRE_INDEX
+/* 0001 1010 1110 */ TABDECL(OP_MOV_ROR_IMM), // OP_MOV_ROR_IMM
+/* 0001 1010 1111 */ TABDECL(OP_LDRD_STRD_OFFSET_PRE_INDEX), // OP_LDRD_STRD_OFFSET_PRE_INDEX
+
+/* 0001 1011 0000 */ TABDECL(OP_MOV_S_LSL_IMM), // OP_MOV_S_LSL_IMM
+/* 0001 1011 0001 */ TABDECL(OP_MOV_S_LSL_REG), // OP_MOV_S_LSL_REG
+/* 0001 1011 0010 */ TABDECL(OP_MOV_S_LSR_IMM), // OP_MOV_S_LSR_IMM
+/* 0001 1011 0011 */ TABDECL(OP_MOV_S_LSR_REG), // OP_MOV_S_LSR_REG
+/* 0001 1011 0100 */ TABDECL(OP_MOV_S_ASR_IMM), // OP_MOV_S_ASR_IMM
+/* 0001 1011 0101 */ TABDECL(OP_MOV_S_ASR_REG), // OP_MOV_S_ASR_REG
+/* 0001 1011 0110 */ TABDECL(OP_MOV_S_ROR_IMM), // OP_MOV_S_ROR_IMM
+/* 0001 1011 0111 */ TABDECL(OP_MOV_S_ROR_REG), // OP_MOV_S_ROR_REG
+/* 0001 1011 1000 */ TABDECL(OP_MOV_S_LSL_IMM), // OP_MOV_S_LSL_IMM
+/* 0001 1011 1001 */ TABDECL(OP_UND),
+/* 0001 1011 1010 */ TABDECL(OP_MOV_S_LSR_IMM), // OP_MOV_S_LSR_IMM
+/* 0001 1011 1011 */ TABDECL(OP_LDRH_PRE_INDE_P_REG_OFF), // OP_LDRH_PRE_INDE_P_REG_OFF
+/* 0001 1011 1100 */ TABDECL(OP_MOV_S_ASR_IMM), // OP_MOV_S_ASR_IMM
+/* 0001 1011 1101 */ TABDECL(OP_LDRSB_PRE_INDE_P_REG_OFF), // OP_LDRSB_PRE_INDE_P_REG_OFF
+/* 0001 1011 1110 */ TABDECL(OP_MOV_S_ROR_IMM), // OP_MOV_S_ROR_IMM
+/* 0001 1011 1111 */ TABDECL(OP_LDRSH_PRE_INDE_P_REG_OFF), // OP_LDRSH_PRE_INDE_P_REG_OFF
+
+/* 0001 1100 0000 */ TABDECL(OP_BIC_LSL_IMM), // OP_BIC_LSL_IMM
+/* 0001 1100 0001 */ TABDECL(OP_BIC_LSL_REG), // OP_BIC_LSL_REG
+/* 0001 1100 0010 */ TABDECL(OP_BIC_LSR_IMM), // OP_BIC_LSR_IMM
+/* 0001 1100 0011 */ TABDECL(OP_BIC_LSR_REG), // OP_BIC_LSR_REG
+/* 0001 1100 0100 */ TABDECL(OP_BIC_ASR_IMM), // OP_BIC_ASR_IMM
+/* 0001 1100 0101 */ TABDECL(OP_BIC_ASR_REG), // OP_BIC_ASR_REG
+/* 0001 1100 0110 */ TABDECL(OP_BIC_ROR_IMM), // OP_BIC_ROR_IMM
+/* 0001 1100 0111 */ TABDECL(OP_BIC_ROR_REG), // OP_BIC_ROR_REG
+/* 0001 1100 1000 */ TABDECL(OP_BIC_LSL_IMM), // OP_BIC_LSL_IMM
+/* 0001 1100 1001 */ TABDECL(OP_UND),
+/* 0001 1100 1010 */ TABDECL(OP_BIC_LSR_IMM), // OP_BIC_LSR_IMM
+/* 0001 1100 1011 */ TABDECL(OP_STRH_P_IMM_OFF), // OP_STRH_P_IMM_OFF
+/* 0001 1100 1100 */ TABDECL(OP_BIC_ASR_IMM), // OP_BIC_ASR_IMM
+/* 0001 1100 1101 */ TABDECL(OP_LDRD_STRD_OFFSET_PRE_INDEX), // OP_LDRD_STRD_OFFSET_PRE_INDEX
+/* 0001 1100 1110 */ TABDECL(OP_BIC_ROR_IMM), // OP_BIC_ROR_IMM
+/* 0001 1100 1111 */ TABDECL(OP_LDRD_STRD_OFFSET_PRE_INDEX), // OP_LDRD_STRD_OFFSET_PRE_INDEX
+
+/* 0001 1101 0000 */ TABDECL(OP_BIC_S_LSL_IMM), // OP_BIC_S_LSL_IMM
+/* 0001 1101 0001 */ TABDECL(OP_BIC_S_LSL_REG), // OP_BIC_S_LSL_REG
+/* 0001 1101 0010 */ TABDECL(OP_BIC_S_LSR_IMM), // OP_BIC_S_LSR_IMM
+/* 0001 1101 0011 */ TABDECL(OP_BIC_S_LSR_REG), // OP_BIC_S_LSR_REG
+/* 0001 1101 0100 */ TABDECL(OP_BIC_S_ASR_IMM), // OP_BIC_S_ASR_IMM
+/* 0001 1101 0101 */ TABDECL(OP_BIC_S_ASR_REG), // OP_BIC_S_ASR_REG
+/* 0001 1101 0110 */ TABDECL(OP_BIC_S_ROR_IMM), // OP_BIC_S_ROR_IMM
+/* 0001 1101 0111 */ TABDECL(OP_BIC_S_ROR_REG), // OP_BIC_S_ROR_REG
+/* 0001 1101 1000 */ TABDECL(OP_BIC_S_LSL_IMM), // OP_BIC_S_LSL_IMM
+/* 0001 1101 1001 */ TABDECL(OP_UND),
+/* 0001 1101 1010 */ TABDECL(OP_BIC_S_LSR_IMM), // OP_BIC_S_LSR_IMM
+/* 0001 1101 1011 */ TABDECL(OP_LDRH_P_IMM_OFF), // OP_LDRH_P_IMM_OFF
+/* 0001 1101 1100 */ TABDECL(OP_BIC_S_ASR_IMM), // OP_BIC_S_ASR_IMM
+/* 0001 1101 1101 */ TABDECL(OP_LDRSB_P_IMM_OFF), // OP_LDRSB_P_IMM_OFF
+/* 0001 1101 1110 */ TABDECL(OP_BIC_S_ROR_IMM), // OP_BIC_S_ROR_IMM
+/* 0001 1101 1111 */ TABDECL(OP_LDRSH_P_IMM_OFF), // OP_LDRSH_P_IMM_OFF
+
+/* 0001 1110 0000 */ TABDECL(OP_MVN_LSL_IMM), // OP_MVN_LSL_IMM
+/* 0001 1110 0001 */ TABDECL(OP_MVN_LSL_REG), // OP_MVN_LSL_REG
+/* 0001 1110 0010 */ TABDECL(OP_MVN_LSR_IMM), // OP_MVN_LSR_IMM
+/* 0001 1110 0011 */ TABDECL(OP_MVN_LSR_REG), // OP_MVN_LSR_REG
+/* 0001 1110 0100 */ TABDECL(OP_MVN_ASR_IMM), // OP_MVN_ASR_IMM
+/* 0001 1110 0101 */ TABDECL(OP_MVN_ASR_REG), // OP_MVN_ASR_REG
+/* 0001 1110 0110 */ TABDECL(OP_MVN_ROR_IMM), // OP_MVN_ROR_IMM
+/* 0001 1110 0111 */ TABDECL(OP_MVN_ROR_REG), // OP_MVN_ROR_REG
+/* 0001 1110 1000 */ TABDECL(OP_MVN_LSL_IMM), // OP_MVN_LSL_IMM
+/* 0001 1110 1001 */ TABDECL(OP_UND),
+/* 0001 1110 1010 */ TABDECL(OP_MVN_LSR_IMM), // OP_MVN_LSR_IMM
+/* 0001 1110 1011 */ TABDECL(OP_STRH_PRE_INDE_P_IMM_OFF), // OP_STRH_PRE_INDE_P_IMM_OFF
+/* 0001 1110 1100 */ TABDECL(OP_MVN_ASR_IMM), // OP_MVN_ASR_IMM
+/* 0001 1110 1101 */ TABDECL(OP_LDRD_STRD_OFFSET_PRE_INDEX), // OP_LDRD_STRD_OFFSET_PRE_INDEX
+/* 0001 1110 1110 */ TABDECL(OP_MVN_ROR_IMM), // OP_MVN_ROR_IMM
+/* 0001 1110 1111 */ TABDECL(OP_LDRD_STRD_OFFSET_PRE_INDEX), // OP_LDRD_STRD_OFFSET_PRE_INDEX
+
+/* 0001 1111 0000 */ TABDECL(OP_MVN_S_LSL_IMM), // OP_MVN_S_LSL_IMM
+/* 0001 1111 0001 */ TABDECL(OP_MVN_S_LSL_REG), // OP_MVN_S_LSL_REG
+/* 0001 1111 0010 */ TABDECL(OP_MVN_S_LSR_IMM), // OP_MVN_S_LSR_IMM
+/* 0001 1111 0011 */ TABDECL(OP_MVN_S_LSR_REG), // OP_MVN_S_LSR_REG
+/* 0001 1111 0100 */ TABDECL(OP_MVN_S_ASR_IMM), // OP_MVN_S_ASR_IMM
+/* 0001 1111 0101 */ TABDECL(OP_MVN_S_ASR_REG), // OP_MVN_S_ASR_REG
+/* 0001 1111 0110 */ TABDECL(OP_MVN_S_ROR_IMM), // OP_MVN_S_ROR_IMM
+/* 0001 1111 0111 */ TABDECL(OP_MVN_S_ROR_REG), // OP_MVN_S_ROR_REG
+/* 0001 1111 1000 */ TABDECL(OP_MVN_S_LSL_IMM), // OP_MVN_S_LSL_IMM
+/* 0001 1111 1001 */ TABDECL(OP_UND),
+/* 0001 1111 1010 */ TABDECL(OP_MVN_S_LSR_IMM), // OP_MVN_S_LSR_IMM
+/* 0001 1111 1011 */ TABDECL(OP_LDRH_PRE_INDE_P_IMM_OFF), // OP_LDRH_PRE_INDE_P_IMM_OFF
+/* 0001 1111 1100 */ TABDECL(OP_MVN_S_ASR_IMM), // OP_MVN_S_ASR_IMM
+/* 0001 1111 1101 */ TABDECL(OP_LDRSB_PRE_INDE_P_IMM_OFF), // OP_LDRSB_PRE_INDE_P_IMM_OFF
+/* 0001 1111 1110 */ TABDECL(OP_MVN_S_ROR_IMM), // OP_MVN_S_ROR_IMM
+/* 0001 1111 1111 */ TABDECL(OP_LDRSH_PRE_INDE_P_IMM_OFF), // OP_LDRSH_PRE_INDE_P_IMM_OFF
+
+/* 0010 0000 0000 */ TABDECL(OP_AND_IMM_VAL), // OP_AND_IMM_VAL
+/* 0010 0000 0001 */ TABDECL(OP_AND_IMM_VAL), // OP_AND_IMM_VAL
+/* 0010 0000 0010 */ TABDECL(OP_AND_IMM_VAL), // OP_AND_IMM_VAL
+/* 0010 0000 0011 */ TABDECL(OP_AND_IMM_VAL), // OP_AND_IMM_VAL
+/* 0010 0000 0100 */ TABDECL(OP_AND_IMM_VAL), // OP_AND_IMM_VAL
+/* 0010 0000 0101 */ TABDECL(OP_AND_IMM_VAL), // OP_AND_IMM_VAL
+/* 0010 0000 0110 */ TABDECL(OP_AND_IMM_VAL), // OP_AND_IMM_VAL
+/* 0010 0000 0111 */ TABDECL(OP_AND_IMM_VAL), // OP_AND_IMM_VAL
+/* 0010 0000 1000 */ TABDECL(OP_AND_IMM_VAL), // OP_AND_IMM_VAL
+/* 0010 0000 1001 */ TABDECL(OP_AND_IMM_VAL), // OP_AND_IMM_VAL
+/* 0010 0000 1010 */ TABDECL(OP_AND_IMM_VAL), // OP_AND_IMM_VAL
+/* 0010 0000 1011 */ TABDECL(OP_AND_IMM_VAL), // OP_AND_IMM_VAL
+/* 0010 0000 1100 */ TABDECL(OP_AND_IMM_VAL), // OP_AND_IMM_VAL
+/* 0010 0000 1101 */ TABDECL(OP_AND_IMM_VAL), // OP_AND_IMM_VAL
+/* 0010 0000 1110 */ TABDECL(OP_AND_IMM_VAL), // OP_AND_IMM_VAL
+/* 0010 0000 1111 */ TABDECL(OP_AND_IMM_VAL), // OP_AND_IMM_VAL
+
+/* 0010 0001 0000 */ TABDECL(OP_AND_S_IMM_VAL), // OP_AND_S_IMM_VAL
+/* 0010 0001 0001 */ TABDECL(OP_AND_S_IMM_VAL), // OP_AND_S_IMM_VAL
+/* 0010 0001 0010 */ TABDECL(OP_AND_S_IMM_VAL), // OP_AND_S_IMM_VAL
+/* 0010 0001 0011 */ TABDECL(OP_AND_S_IMM_VAL), // OP_AND_S_IMM_VAL
+/* 0010 0001 0100 */ TABDECL(OP_AND_S_IMM_VAL), // OP_AND_S_IMM_VAL
+/* 0010 0001 0101 */ TABDECL(OP_AND_S_IMM_VAL), // OP_AND_S_IMM_VAL
+/* 0010 0001 0110 */ TABDECL(OP_AND_S_IMM_VAL), // OP_AND_S_IMM_VAL
+/* 0010 0001 0111 */ TABDECL(OP_AND_S_IMM_VAL), // OP_AND_S_IMM_VAL
+/* 0010 0001 1000 */ TABDECL(OP_AND_S_IMM_VAL), // OP_AND_S_IMM_VAL
+/* 0010 0001 1001 */ TABDECL(OP_AND_S_IMM_VAL), // OP_AND_S_IMM_VAL
+/* 0010 0001 1010 */ TABDECL(OP_AND_S_IMM_VAL), // OP_AND_S_IMM_VAL
+/* 0010 0001 1011 */ TABDECL(OP_AND_S_IMM_VAL), // OP_AND_S_IMM_VAL
+/* 0010 0001 1100 */ TABDECL(OP_AND_S_IMM_VAL), // OP_AND_S_IMM_VAL
+/* 0010 0001 1101 */ TABDECL(OP_AND_S_IMM_VAL), // OP_AND_S_IMM_VAL
+/* 0010 0001 1110 */ TABDECL(OP_AND_S_IMM_VAL), // OP_AND_S_IMM_VAL
+/* 0010 0001 1111 */ TABDECL(OP_AND_S_IMM_VAL), // OP_AND_S_IMM_VAL
+
+/* 0010 0010 0000 */ TABDECL(OP_EOR_IMM_VAL), // OP_EOR_IMM_VAL
+/* 0010 0010 0001 */ TABDECL(OP_EOR_IMM_VAL), // OP_EOR_IMM_VAL
+/* 0010 0010 0010 */ TABDECL(OP_EOR_IMM_VAL), // OP_EOR_IMM_VAL
+/* 0010 0010 0011 */ TABDECL(OP_EOR_IMM_VAL), // OP_EOR_IMM_VAL
+/* 0010 0010 0100 */ TABDECL(OP_EOR_IMM_VAL), // OP_EOR_IMM_VAL
+/* 0010 0010 0101 */ TABDECL(OP_EOR_IMM_VAL), // OP_EOR_IMM_VAL
+/* 0010 0010 0110 */ TABDECL(OP_EOR_IMM_VAL), // OP_EOR_IMM_VAL
+/* 0010 0010 0111 */ TABDECL(OP_EOR_IMM_VAL), // OP_EOR_IMM_VAL
+/* 0010 0010 1000 */ TABDECL(OP_EOR_IMM_VAL), // OP_EOR_IMM_VAL
+/* 0010 0010 1001 */ TABDECL(OP_EOR_IMM_VAL), // OP_EOR_IMM_VAL
+/* 0010 0010 1010 */ TABDECL(OP_EOR_IMM_VAL), // OP_EOR_IMM_VAL
+/* 0010 0010 1011 */ TABDECL(OP_EOR_IMM_VAL), // OP_EOR_IMM_VAL
+/* 0010 0010 1100 */ TABDECL(OP_EOR_IMM_VAL), // OP_EOR_IMM_VAL
+/* 0010 0010 1101 */ TABDECL(OP_EOR_IMM_VAL), // OP_EOR_IMM_VAL
+/* 0010 0010 1110 */ TABDECL(OP_EOR_IMM_VAL), // OP_EOR_IMM_VAL
+/* 0010 0010 1111 */ TABDECL(OP_EOR_IMM_VAL), // OP_EOR_IMM_VAL
+
+/* 0010 0011 0000 */ TABDECL(OP_EOR_S_IMM_VAL), // OP_EOR_S_IMM_VAL
+/* 0010 0011 0001 */ TABDECL(OP_EOR_S_IMM_VAL), // OP_EOR_S_IMM_VAL
+/* 0010 0011 0010 */ TABDECL(OP_EOR_S_IMM_VAL), // OP_EOR_S_IMM_VAL
+/* 0010 0011 0011 */ TABDECL(OP_EOR_S_IMM_VAL), // OP_EOR_S_IMM_VAL
+/* 0010 0011 0100 */ TABDECL(OP_EOR_S_IMM_VAL), // OP_EOR_S_IMM_VAL
+/* 0010 0011 0101 */ TABDECL(OP_EOR_S_IMM_VAL), // OP_EOR_S_IMM_VAL
+/* 0010 0011 0110 */ TABDECL(OP_EOR_S_IMM_VAL), // OP_EOR_S_IMM_VAL
+/* 0010 0011 0111 */ TABDECL(OP_EOR_S_IMM_VAL), // OP_EOR_S_IMM_VAL
+/* 0010 0011 1000 */ TABDECL(OP_EOR_S_IMM_VAL), // OP_EOR_S_IMM_VAL
+/* 0010 0011 1001 */ TABDECL(OP_EOR_S_IMM_VAL), // OP_EOR_S_IMM_VAL
+/* 0010 0011 1010 */ TABDECL(OP_EOR_S_IMM_VAL), // OP_EOR_S_IMM_VAL
+/* 0010 0011 1011 */ TABDECL(OP_EOR_S_IMM_VAL), // OP_EOR_S_IMM_VAL
+/* 0010 0011 1100 */ TABDECL(OP_EOR_S_IMM_VAL), // OP_EOR_S_IMM_VAL
+/* 0010 0011 1101 */ TABDECL(OP_EOR_S_IMM_VAL), // OP_EOR_S_IMM_VAL
+/* 0010 0011 1110 */ TABDECL(OP_EOR_S_IMM_VAL), // OP_EOR_S_IMM_VAL
+/* 0010 0011 1111 */ TABDECL(OP_EOR_S_IMM_VAL), // OP_EOR_S_IMM_VAL
+
+/* 0010 0100 0000 */ TABDECL(OP_SUB_IMM_VAL), // OP_SUB_IMM_VAL
+/* 0010 0100 0001 */ TABDECL(OP_SUB_IMM_VAL), // OP_SUB_IMM_VAL
+/* 0010 0100 0010 */ TABDECL(OP_SUB_IMM_VAL), // OP_SUB_IMM_VAL
+/* 0010 0100 0011 */ TABDECL(OP_SUB_IMM_VAL), // OP_SUB_IMM_VAL
+/* 0010 0100 0100 */ TABDECL(OP_SUB_IMM_VAL), // OP_SUB_IMM_VAL
+/* 0010 0100 0101 */ TABDECL(OP_SUB_IMM_VAL), // OP_SUB_IMM_VAL
+/* 0010 0100 0110 */ TABDECL(OP_SUB_IMM_VAL), // OP_SUB_IMM_VAL
+/* 0010 0100 0111 */ TABDECL(OP_SUB_IMM_VAL), // OP_SUB_IMM_VAL
+/* 0010 0100 1000 */ TABDECL(OP_SUB_IMM_VAL), // OP_SUB_IMM_VAL
+/* 0010 0100 1001 */ TABDECL(OP_SUB_IMM_VAL), // OP_SUB_IMM_VAL
+/* 0010 0100 1010 */ TABDECL(OP_SUB_IMM_VAL), // OP_SUB_IMM_VAL
+/* 0010 0100 1011 */ TABDECL(OP_SUB_IMM_VAL), // OP_SUB_IMM_VAL
+/* 0010 0100 1100 */ TABDECL(OP_SUB_IMM_VAL), // OP_SUB_IMM_VAL
+/* 0010 0100 1101 */ TABDECL(OP_SUB_IMM_VAL), // OP_SUB_IMM_VAL
+/* 0010 0100 1110 */ TABDECL(OP_SUB_IMM_VAL), // OP_SUB_IMM_VAL
+/* 0010 0100 1111 */ TABDECL(OP_SUB_IMM_VAL), // OP_SUB_IMM_VAL
+
+/* 0010 0101 0000 */ TABDECL(OP_SUB_S_IMM_VAL), // OP_SUB_S_IMM_VAL
+/* 0010 0101 0001 */ TABDECL(OP_SUB_S_IMM_VAL), // OP_SUB_S_IMM_VAL
+/* 0010 0101 0010 */ TABDECL(OP_SUB_S_IMM_VAL), // OP_SUB_S_IMM_VAL
+/* 0010 0101 0011 */ TABDECL(OP_SUB_S_IMM_VAL), // OP_SUB_S_IMM_VAL
+/* 0010 0101 0100 */ TABDECL(OP_SUB_S_IMM_VAL), // OP_SUB_S_IMM_VAL
+/* 0010 0101 0101 */ TABDECL(OP_SUB_S_IMM_VAL), // OP_SUB_S_IMM_VAL
+/* 0010 0101 0110 */ TABDECL(OP_SUB_S_IMM_VAL), // OP_SUB_S_IMM_VAL
+/* 0010 0101 0111 */ TABDECL(OP_SUB_S_IMM_VAL), // OP_SUB_S_IMM_VAL
+/* 0010 0101 1000 */ TABDECL(OP_SUB_S_IMM_VAL), // OP_SUB_S_IMM_VAL
+/* 0010 0101 1001 */ TABDECL(OP_SUB_S_IMM_VAL), // OP_SUB_S_IMM_VAL
+/* 0010 0101 1010 */ TABDECL(OP_SUB_S_IMM_VAL), // OP_SUB_S_IMM_VAL
+/* 0010 0101 1011 */ TABDECL(OP_SUB_S_IMM_VAL), // OP_SUB_S_IMM_VAL
+/* 0010 0101 1100 */ TABDECL(OP_SUB_S_IMM_VAL), // OP_SUB_S_IMM_VAL
+/* 0010 0101 1101 */ TABDECL(OP_SUB_S_IMM_VAL), // OP_SUB_S_IMM_VAL
+/* 0010 0101 1110 */ TABDECL(OP_SUB_S_IMM_VAL), // OP_SUB_S_IMM_VAL
+/* 0010 0101 1111 */ TABDECL(OP_SUB_S_IMM_VAL), // OP_SUB_S_IMM_VAL
+
+/* 0010 0110 0000 */ TABDECL(OP_RSB_IMM_VAL), // OP_RSB_IMM_VAL
+/* 0010 0110 0001 */ TABDECL(OP_RSB_IMM_VAL), // OP_RSB_IMM_VAL
+/* 0010 0110 0010 */ TABDECL(OP_RSB_IMM_VAL), // OP_RSB_IMM_VAL
+/* 0010 0110 0011 */ TABDECL(OP_RSB_IMM_VAL), // OP_RSB_IMM_VAL
+/* 0010 0110 0100 */ TABDECL(OP_RSB_IMM_VAL), // OP_RSB_IMM_VAL
+/* 0010 0110 0101 */ TABDECL(OP_RSB_IMM_VAL), // OP_RSB_IMM_VAL
+/* 0010 0110 0110 */ TABDECL(OP_RSB_IMM_VAL), // OP_RSB_IMM_VAL
+/* 0010 0110 0111 */ TABDECL(OP_RSB_IMM_VAL), // OP_RSB_IMM_VAL
+/* 0010 0110 1000 */ TABDECL(OP_RSB_IMM_VAL), // OP_RSB_IMM_VAL
+/* 0010 0110 1001 */ TABDECL(OP_RSB_IMM_VAL), // OP_RSB_IMM_VAL
+/* 0010 0110 1010 */ TABDECL(OP_RSB_IMM_VAL), // OP_RSB_IMM_VAL
+/* 0010 0110 1011 */ TABDECL(OP_RSB_IMM_VAL), // OP_RSB_IMM_VAL
+/* 0010 0110 1100 */ TABDECL(OP_RSB_IMM_VAL), // OP_RSB_IMM_VAL
+/* 0010 0110 1101 */ TABDECL(OP_RSB_IMM_VAL), // OP_RSB_IMM_VAL
+/* 0010 0110 1110 */ TABDECL(OP_RSB_IMM_VAL), // OP_RSB_IMM_VAL
+/* 0010 0110 1111 */ TABDECL(OP_RSB_IMM_VAL), // OP_RSB_IMM_VAL
+
+/* 0010 0111 0000 */ TABDECL(OP_RSB_S_IMM_VAL), // OP_RSB_S_IMM_VAL
+/* 0010 0111 0001 */ TABDECL(OP_RSB_S_IMM_VAL), // OP_RSB_S_IMM_VAL
+/* 0010 0111 0010 */ TABDECL(OP_RSB_S_IMM_VAL), // OP_RSB_S_IMM_VAL
+/* 0010 0111 0011 */ TABDECL(OP_RSB_S_IMM_VAL), // OP_RSB_S_IMM_VAL
+/* 0010 0111 0100 */ TABDECL(OP_RSB_S_IMM_VAL), // OP_RSB_S_IMM_VAL
+/* 0010 0111 0101 */ TABDECL(OP_RSB_S_IMM_VAL), // OP_RSB_S_IMM_VAL
+/* 0010 0111 0110 */ TABDECL(OP_RSB_S_IMM_VAL), // OP_RSB_S_IMM_VAL
+/* 0010 0111 0111 */ TABDECL(OP_RSB_S_IMM_VAL), // OP_RSB_S_IMM_VAL
+/* 0010 0111 1000 */ TABDECL(OP_RSB_S_IMM_VAL), // OP_RSB_S_IMM_VAL
+/* 0010 0111 1001 */ TABDECL(OP_RSB_S_IMM_VAL), // OP_RSB_S_IMM_VAL
+/* 0010 0111 1010 */ TABDECL(OP_RSB_S_IMM_VAL), // OP_RSB_S_IMM_VAL
+/* 0010 0111 1011 */ TABDECL(OP_RSB_S_IMM_VAL), // OP_RSB_S_IMM_VAL
+/* 0010 0111 1100 */ TABDECL(OP_RSB_S_IMM_VAL), // OP_RSB_S_IMM_VAL
+/* 0010 0111 1101 */ TABDECL(OP_RSB_S_IMM_VAL), // OP_RSB_S_IMM_VAL
+/* 0010 0111 1110 */ TABDECL(OP_RSB_S_IMM_VAL), // OP_RSB_S_IMM_VAL
+/* 0010 0111 1111 */ TABDECL(OP_RSB_S_IMM_VAL), // OP_RSB_S_IMM_VAL
+
+/* 0010 1000 0000 */ TABDECL(OP_ADD_IMM_VAL), // OP_ADD_IMM_VAL
+/* 0010 1000 0001 */ TABDECL(OP_ADD_IMM_VAL), // OP_ADD_IMM_VAL
+/* 0010 1000 0010 */ TABDECL(OP_ADD_IMM_VAL), // OP_ADD_IMM_VAL
+/* 0010 1000 0011 */ TABDECL(OP_ADD_IMM_VAL), // OP_ADD_IMM_VAL
+/* 0010 1000 0100 */ TABDECL(OP_ADD_IMM_VAL), // OP_ADD_IMM_VAL
+/* 0010 1000 0101 */ TABDECL(OP_ADD_IMM_VAL), // OP_ADD_IMM_VAL
+/* 0010 1000 0110 */ TABDECL(OP_ADD_IMM_VAL), // OP_ADD_IMM_VAL
+/* 0010 1000 0111 */ TABDECL(OP_ADD_IMM_VAL), // OP_ADD_IMM_VAL
+/* 0010 1000 1000 */ TABDECL(OP_ADD_IMM_VAL), // OP_ADD_IMM_VAL
+/* 0010 1000 1001 */ TABDECL(OP_ADD_IMM_VAL), // OP_ADD_IMM_VAL
+/* 0010 1000 1010 */ TABDECL(OP_ADD_IMM_VAL), // OP_ADD_IMM_VAL
+/* 0010 1000 1011 */ TABDECL(OP_ADD_IMM_VAL), // OP_ADD_IMM_VAL
+/* 0010 1000 1100 */ TABDECL(OP_ADD_IMM_VAL), // OP_ADD_IMM_VAL
+/* 0010 1000 1101 */ TABDECL(OP_ADD_IMM_VAL), // OP_ADD_IMM_VAL
+/* 0010 1000 1110 */ TABDECL(OP_ADD_IMM_VAL), // OP_ADD_IMM_VAL
+/* 0010 1000 1111 */ TABDECL(OP_ADD_IMM_VAL), // OP_ADD_IMM_VAL
+
+/* 0010 1001 0000 */ TABDECL(OP_ADD_S_IMM_VAL), // OP_ADD_S_IMM_VAL
+/* 0010 1001 0001 */ TABDECL(OP_ADD_S_IMM_VAL), // OP_ADD_S_IMM_VAL
+/* 0010 1001 0010 */ TABDECL(OP_ADD_S_IMM_VAL), // OP_ADD_S_IMM_VAL
+/* 0010 1001 0011 */ TABDECL(OP_ADD_S_IMM_VAL), // OP_ADD_S_IMM_VAL
+/* 0010 1001 0100 */ TABDECL(OP_ADD_S_IMM_VAL), // OP_ADD_S_IMM_VAL
+/* 0010 1001 0101 */ TABDECL(OP_ADD_S_IMM_VAL), // OP_ADD_S_IMM_VAL
+/* 0010 1001 0110 */ TABDECL(OP_ADD_S_IMM_VAL), // OP_ADD_S_IMM_VAL
+/* 0010 1001 0111 */ TABDECL(OP_ADD_S_IMM_VAL), // OP_ADD_S_IMM_VAL
+/* 0010 1001 1000 */ TABDECL(OP_ADD_S_IMM_VAL), // OP_ADD_S_IMM_VAL
+/* 0010 1001 1001 */ TABDECL(OP_ADD_S_IMM_VAL), // OP_ADD_S_IMM_VAL
+/* 0010 1001 1010 */ TABDECL(OP_ADD_S_IMM_VAL), // OP_ADD_S_IMM_VAL
+/* 0010 1001 1011 */ TABDECL(OP_ADD_S_IMM_VAL), // OP_ADD_S_IMM_VAL
+/* 0010 1001 1100 */ TABDECL(OP_ADD_S_IMM_VAL), // OP_ADD_S_IMM_VAL
+/* 0010 1001 1101 */ TABDECL(OP_ADD_S_IMM_VAL), // OP_ADD_S_IMM_VAL
+/* 0010 1001 1110 */ TABDECL(OP_ADD_S_IMM_VAL), // OP_ADD_S_IMM_VAL
+/* 0010 1001 1111 */ TABDECL(OP_ADD_S_IMM_VAL), // OP_ADD_S_IMM_VAL
+
+/* 0010 1010 0000 */ TABDECL(OP_ADC_IMM_VAL), // OP_ADC_IMM_VAL
+/* 0010 1010 0001 */ TABDECL(OP_ADC_IMM_VAL), // OP_ADC_IMM_VAL
+/* 0010 1010 0010 */ TABDECL(OP_ADC_IMM_VAL), // OP_ADC_IMM_VAL
+/* 0010 1010 0011 */ TABDECL(OP_ADC_IMM_VAL), // OP_ADC_IMM_VAL
+/* 0010 1010 0100 */ TABDECL(OP_ADC_IMM_VAL), // OP_ADC_IMM_VAL
+/* 0010 1010 0101 */ TABDECL(OP_ADC_IMM_VAL), // OP_ADC_IMM_VAL
+/* 0010 1010 0110 */ TABDECL(OP_ADC_IMM_VAL), // OP_ADC_IMM_VAL
+/* 0010 1010 0111 */ TABDECL(OP_ADC_IMM_VAL), // OP_ADC_IMM_VAL
+/* 0010 1010 1000 */ TABDECL(OP_ADC_IMM_VAL), // OP_ADC_IMM_VAL
+/* 0010 1010 1001 */ TABDECL(OP_ADC_IMM_VAL), // OP_ADC_IMM_VAL
+/* 0010 1010 1010 */ TABDECL(OP_ADC_IMM_VAL), // OP_ADC_IMM_VAL
+/* 0010 1010 1011 */ TABDECL(OP_ADC_IMM_VAL), // OP_ADC_IMM_VAL
+/* 0010 1010 1100 */ TABDECL(OP_ADC_IMM_VAL), // OP_ADC_IMM_VAL
+/* 0010 1010 1101 */ TABDECL(OP_ADC_IMM_VAL), // OP_ADC_IMM_VAL
+/* 0010 1010 1110 */ TABDECL(OP_ADC_IMM_VAL), // OP_ADC_IMM_VAL
+/* 0010 1010 1111 */ TABDECL(OP_ADC_IMM_VAL), // OP_ADC_IMM_VAL
+
+/* 0010 1011 0000 */ TABDECL(OP_ADC_S_IMM_VAL), // OP_ADC_S_IMM_VAL
+/* 0010 1011 0001 */ TABDECL(OP_ADC_S_IMM_VAL), // OP_ADC_S_IMM_VAL
+/* 0010 1011 0010 */ TABDECL(OP_ADC_S_IMM_VAL), // OP_ADC_S_IMM_VAL
+/* 0010 1011 0011 */ TABDECL(OP_ADC_S_IMM_VAL), // OP_ADC_S_IMM_VAL
+/* 0010 1011 0100 */ TABDECL(OP_ADC_S_IMM_VAL), // OP_ADC_S_IMM_VAL
+/* 0010 1011 0101 */ TABDECL(OP_ADC_S_IMM_VAL), // OP_ADC_S_IMM_VAL
+/* 0010 1011 0110 */ TABDECL(OP_ADC_S_IMM_VAL), // OP_ADC_S_IMM_VAL
+/* 0010 1011 0111 */ TABDECL(OP_ADC_S_IMM_VAL), // OP_ADC_S_IMM_VAL
+/* 0010 1011 1000 */ TABDECL(OP_ADC_S_IMM_VAL), // OP_ADC_S_IMM_VAL
+/* 0010 1011 1001 */ TABDECL(OP_ADC_S_IMM_VAL), // OP_ADC_S_IMM_VAL
+/* 0010 1011 1010 */ TABDECL(OP_ADC_S_IMM_VAL), // OP_ADC_S_IMM_VAL
+/* 0010 1011 1011 */ TABDECL(OP_ADC_S_IMM_VAL), // OP_ADC_S_IMM_VAL
+/* 0010 1011 1100 */ TABDECL(OP_ADC_S_IMM_VAL), // OP_ADC_S_IMM_VAL
+/* 0010 1011 1101 */ TABDECL(OP_ADC_S_IMM_VAL), // OP_ADC_S_IMM_VAL
+/* 0010 1011 1110 */ TABDECL(OP_ADC_S_IMM_VAL), // OP_ADC_S_IMM_VAL
+/* 0010 1011 1111 */ TABDECL(OP_ADC_S_IMM_VAL), // OP_ADC_S_IMM_VAL
+
+/* 0010 1100 0000 */ TABDECL(OP_SBC_IMM_VAL), // OP_SBC_IMM_VAL
+/* 0010 1100 0001 */ TABDECL(OP_SBC_IMM_VAL), // OP_SBC_IMM_VAL
+/* 0010 1100 0010 */ TABDECL(OP_SBC_IMM_VAL), // OP_SBC_IMM_VAL
+/* 0010 1100 0011 */ TABDECL(OP_SBC_IMM_VAL), // OP_SBC_IMM_VAL
+/* 0010 1100 0100 */ TABDECL(OP_SBC_IMM_VAL), // OP_SBC_IMM_VAL
+/* 0010 1100 0101 */ TABDECL(OP_SBC_IMM_VAL), // OP_SBC_IMM_VAL
+/* 0010 1100 0110 */ TABDECL(OP_SBC_IMM_VAL), // OP_SBC_IMM_VAL
+/* 0010 1100 0111 */ TABDECL(OP_SBC_IMM_VAL), // OP_SBC_IMM_VAL
+/* 0010 1100 1000 */ TABDECL(OP_SBC_IMM_VAL), // OP_SBC_IMM_VAL
+/* 0010 1100 1001 */ TABDECL(OP_SBC_IMM_VAL), // OP_SBC_IMM_VAL
+/* 0010 1100 1010 */ TABDECL(OP_SBC_IMM_VAL), // OP_SBC_IMM_VAL
+/* 0010 1100 1011 */ TABDECL(OP_SBC_IMM_VAL), // OP_SBC_IMM_VAL
+/* 0010 1100 1100 */ TABDECL(OP_SBC_IMM_VAL), // OP_SBC_IMM_VAL
+/* 0010 1100 1101 */ TABDECL(OP_SBC_IMM_VAL), // OP_SBC_IMM_VAL
+/* 0010 1100 1110 */ TABDECL(OP_SBC_IMM_VAL), // OP_SBC_IMM_VAL
+/* 0010 1100 1111 */ TABDECL(OP_SBC_IMM_VAL), // OP_SBC_IMM_VAL
+
+/* 0010 1101 0000 */ TABDECL(OP_SBC_S_IMM_VAL), // OP_SBC_S_IMM_VAL
+/* 0010 1101 0001 */ TABDECL(OP_SBC_S_IMM_VAL), // OP_SBC_S_IMM_VAL
+/* 0010 1101 0010 */ TABDECL(OP_SBC_S_IMM_VAL), // OP_SBC_S_IMM_VAL
+/* 0010 1101 0011 */ TABDECL(OP_SBC_S_IMM_VAL), // OP_SBC_S_IMM_VAL
+/* 0010 1101 0100 */ TABDECL(OP_SBC_S_IMM_VAL), // OP_SBC_S_IMM_VAL
+/* 0010 1101 0101 */ TABDECL(OP_SBC_S_IMM_VAL), // OP_SBC_S_IMM_VAL
+/* 0010 1101 0110 */ TABDECL(OP_SBC_S_IMM_VAL), // OP_SBC_S_IMM_VAL
+/* 0010 1101 0111 */ TABDECL(OP_SBC_S_IMM_VAL), // OP_SBC_S_IMM_VAL
+/* 0010 1101 1000 */ TABDECL(OP_SBC_S_IMM_VAL), // OP_SBC_S_IMM_VAL
+/* 0010 1101 1001 */ TABDECL(OP_SBC_S_IMM_VAL), // OP_SBC_S_IMM_VAL
+/* 0010 1101 1010 */ TABDECL(OP_SBC_S_IMM_VAL), // OP_SBC_S_IMM_VAL
+/* 0010 1101 1011 */ TABDECL(OP_SBC_S_IMM_VAL), // OP_SBC_S_IMM_VAL
+/* 0010 1101 1100 */ TABDECL(OP_SBC_S_IMM_VAL), // OP_SBC_S_IMM_VAL
+/* 0010 1101 1101 */ TABDECL(OP_SBC_S_IMM_VAL), // OP_SBC_S_IMM_VAL
+/* 0010 1101 1110 */ TABDECL(OP_SBC_S_IMM_VAL), // OP_SBC_S_IMM_VAL
+/* 0010 1101 1111 */ TABDECL(OP_SBC_S_IMM_VAL), // OP_SBC_S_IMM_VAL
+
+/* 0010 1110 0000 */ TABDECL(OP_RSC_IMM_VAL), // OP_RSC_IMM_VAL
+/* 0010 1110 0001 */ TABDECL(OP_RSC_IMM_VAL), // OP_RSC_IMM_VAL
+/* 0010 1110 0010 */ TABDECL(OP_RSC_IMM_VAL), // OP_RSC_IMM_VAL
+/* 0010 1110 0011 */ TABDECL(OP_RSC_IMM_VAL), // OP_RSC_IMM_VAL
+/* 0010 1110 0100 */ TABDECL(OP_RSC_IMM_VAL), // OP_RSC_IMM_VAL
+/* 0010 1110 0101 */ TABDECL(OP_RSC_IMM_VAL), // OP_RSC_IMM_VAL
+/* 0010 1110 0110 */ TABDECL(OP_RSC_IMM_VAL), // OP_RSC_IMM_VAL
+/* 0010 1110 0111 */ TABDECL(OP_RSC_IMM_VAL), // OP_RSC_IMM_VAL
+/* 0010 1110 1000 */ TABDECL(OP_RSC_IMM_VAL), // OP_RSC_IMM_VAL
+/* 0010 1110 1001 */ TABDECL(OP_RSC_IMM_VAL), // OP_RSC_IMM_VAL
+/* 0010 1110 1010 */ TABDECL(OP_RSC_IMM_VAL), // OP_RSC_IMM_VAL
+/* 0010 1110 1011 */ TABDECL(OP_RSC_IMM_VAL), // OP_RSC_IMM_VAL
+/* 0010 1110 1100 */ TABDECL(OP_RSC_IMM_VAL), // OP_RSC_IMM_VAL
+/* 0010 1110 1101 */ TABDECL(OP_RSC_IMM_VAL), // OP_RSC_IMM_VAL
+/* 0010 1110 1110 */ TABDECL(OP_RSC_IMM_VAL), // OP_RSC_IMM_VAL
+/* 0010 1110 1111 */ TABDECL(OP_RSC_IMM_VAL), // OP_RSC_IMM_VAL
+
+/* 0010 1111 0000 */ TABDECL(OP_RSC_S_IMM_VAL), // OP_RSC_S_IMM_VAL
+/* 0010 1111 0001 */ TABDECL(OP_RSC_S_IMM_VAL), // OP_RSC_S_IMM_VAL
+/* 0010 1111 0010 */ TABDECL(OP_RSC_S_IMM_VAL), // OP_RSC_S_IMM_VAL
+/* 0010 1111 0011 */ TABDECL(OP_RSC_S_IMM_VAL), // OP_RSC_S_IMM_VAL
+/* 0010 1111 0100 */ TABDECL(OP_RSC_S_IMM_VAL), // OP_RSC_S_IMM_VAL
+/* 0010 1111 0101 */ TABDECL(OP_RSC_S_IMM_VAL), // OP_RSC_S_IMM_VAL
+/* 0010 1111 0110 */ TABDECL(OP_RSC_S_IMM_VAL), // OP_RSC_S_IMM_VAL
+/* 0010 1111 0111 */ TABDECL(OP_RSC_S_IMM_VAL), // OP_RSC_S_IMM_VAL
+/* 0010 1111 1000 */ TABDECL(OP_RSC_S_IMM_VAL), // OP_RSC_S_IMM_VAL
+/* 0010 1111 1001 */ TABDECL(OP_RSC_S_IMM_VAL), // OP_RSC_S_IMM_VAL
+/* 0010 1111 1010 */ TABDECL(OP_RSC_S_IMM_VAL), // OP_RSC_S_IMM_VAL
+/* 0010 1111 1011 */ TABDECL(OP_RSC_S_IMM_VAL), // OP_RSC_S_IMM_VAL
+/* 0010 1111 1100 */ TABDECL(OP_RSC_S_IMM_VAL), // OP_RSC_S_IMM_VAL
+/* 0010 1111 1101 */ TABDECL(OP_RSC_S_IMM_VAL), // OP_RSC_S_IMM_VAL
+/* 0010 1111 1110 */ TABDECL(OP_RSC_S_IMM_VAL), // OP_RSC_S_IMM_VAL
+/* 0010 1111 1111 */ TABDECL(OP_RSC_S_IMM_VAL), // OP_RSC_S_IMM_VAL
+
+/* 0011 0000 0000 */ TABDECL(OP_UND),
+/* 0011 0000 0001 */ TABDECL(OP_UND),
+/* 0011 0000 0010 */ TABDECL(OP_UND),
+/* 0011 0000 0011 */ TABDECL(OP_UND),
+/* 0011 0000 0100 */ TABDECL(OP_UND),
+/* 0011 0000 0101 */ TABDECL(OP_UND),
+/* 0011 0000 0110 */ TABDECL(OP_UND),
+/* 0011 0000 0111 */ TABDECL(OP_UND),
+/* 0011 0000 1000 */ TABDECL(OP_UND),
+/* 0011 0000 1001 */ TABDECL(OP_UND),
+/* 0011 0000 1010 */ TABDECL(OP_UND),
+/* 0011 0000 1011 */ TABDECL(OP_UND),
+/* 0011 0000 1100 */ TABDECL(OP_UND),
+/* 0011 0000 1101 */ TABDECL(OP_UND),
+/* 0011 0000 1110 */ TABDECL(OP_UND),
+/* 0011 0000 1111 */ TABDECL(OP_UND),
+
+/* 0011 0001 0000 */ TABDECL(OP_TST_IMM_VAL), // OP_TST_IMM_VAL
+/* 0011 0001 0001 */ TABDECL(OP_TST_IMM_VAL), // OP_TST_IMM_VAL
+/* 0011 0001 0010 */ TABDECL(OP_TST_IMM_VAL), // OP_TST_IMM_VAL
+/* 0011 0001 0011 */ TABDECL(OP_TST_IMM_VAL), // OP_TST_IMM_VAL
+/* 0011 0001 0100 */ TABDECL(OP_TST_IMM_VAL), // OP_TST_IMM_VAL
+/* 0011 0001 0101 */ TABDECL(OP_TST_IMM_VAL), // OP_TST_IMM_VAL
+/* 0011 0001 0110 */ TABDECL(OP_TST_IMM_VAL), // OP_TST_IMM_VAL
+/* 0011 0001 0111 */ TABDECL(OP_TST_IMM_VAL), // OP_TST_IMM_VAL
+/* 0011 0001 1000 */ TABDECL(OP_TST_IMM_VAL), // OP_TST_IMM_VAL
+/* 0011 0001 1001 */ TABDECL(OP_TST_IMM_VAL), // OP_TST_IMM_VAL
+/* 0011 0001 1010 */ TABDECL(OP_TST_IMM_VAL), // OP_TST_IMM_VAL
+/* 0011 0001 1011 */ TABDECL(OP_TST_IMM_VAL), // OP_TST_IMM_VAL
+/* 0011 0001 1100 */ TABDECL(OP_TST_IMM_VAL), // OP_TST_IMM_VAL
+/* 0011 0001 1101 */ TABDECL(OP_TST_IMM_VAL), // OP_TST_IMM_VAL
+/* 0011 0001 1110 */ TABDECL(OP_TST_IMM_VAL), // OP_TST_IMM_VAL
+/* 0011 0001 1111 */ TABDECL(OP_TST_IMM_VAL), // OP_TST_IMM_VAL
+
+/* 0011 0010 0000 */ TABDECL(OP_MSR_CPSR_IMM_VAL), // OP_MSR_CPSR_IMM_VAL
+/* 0011 0010 0001 */ TABDECL(OP_MSR_CPSR_IMM_VAL), // OP_MSR_CPSR_IMM_VAL
+/* 0011 0010 0010 */ TABDECL(OP_MSR_CPSR_IMM_VAL), // OP_MSR_CPSR_IMM_VAL
+/* 0011 0010 0011 */ TABDECL(OP_MSR_CPSR_IMM_VAL), // OP_MSR_CPSR_IMM_VAL
+/* 0011 0010 0100 */ TABDECL(OP_MSR_CPSR_IMM_VAL), // OP_MSR_CPSR_IMM_VAL
+/* 0011 0010 0101 */ TABDECL(OP_MSR_CPSR_IMM_VAL), // OP_MSR_CPSR_IMM_VAL
+/* 0011 0010 0110 */ TABDECL(OP_MSR_CPSR_IMM_VAL), // OP_MSR_CPSR_IMM_VAL
+/* 0011 0010 0111 */ TABDECL(OP_MSR_CPSR_IMM_VAL), // OP_MSR_CPSR_IMM_VAL
+/* 0011 0010 1000 */ TABDECL(OP_MSR_CPSR_IMM_VAL), // OP_MSR_CPSR_IMM_VAL
+/* 0011 0010 1001 */ TABDECL(OP_MSR_CPSR_IMM_VAL), // OP_MSR_CPSR_IMM_VAL
+/* 0011 0010 1010 */ TABDECL(OP_MSR_CPSR_IMM_VAL), // OP_MSR_CPSR_IMM_VAL
+/* 0011 0010 1011 */ TABDECL(OP_MSR_CPSR_IMM_VAL), // OP_MSR_CPSR_IMM_VAL
+/* 0011 0010 1100 */ TABDECL(OP_MSR_CPSR_IMM_VAL), // OP_MSR_CPSR_IMM_VAL
+/* 0011 0010 1101 */ TABDECL(OP_MSR_CPSR_IMM_VAL), // OP_MSR_CPSR_IMM_VAL
+/* 0011 0010 1110 */ TABDECL(OP_MSR_CPSR_IMM_VAL), // OP_MSR_CPSR_IMM_VAL
+/* 0011 0010 1111 */ TABDECL(OP_MSR_CPSR_IMM_VAL), // OP_MSR_CPSR_IMM_VAL
+
+/* 0011 0011 0000 */ TABDECL(OP_TEQ_IMM_VAL), // OP_TEQ_IMM_VAL
+/* 0011 0011 0001 */ TABDECL(OP_TEQ_IMM_VAL), // OP_TEQ_IMM_VAL
+/* 0011 0011 0010 */ TABDECL(OP_TEQ_IMM_VAL), // OP_TEQ_IMM_VAL
+/* 0011 0011 0011 */ TABDECL(OP_TEQ_IMM_VAL), // OP_TEQ_IMM_VAL
+/* 0011 0011 0100 */ TABDECL(OP_TEQ_IMM_VAL), // OP_TEQ_IMM_VAL
+/* 0011 0011 0101 */ TABDECL(OP_TEQ_IMM_VAL), // OP_TEQ_IMM_VAL
+/* 0011 0011 0110 */ TABDECL(OP_TEQ_IMM_VAL), // OP_TEQ_IMM_VAL
+/* 0011 0011 0111 */ TABDECL(OP_TEQ_IMM_VAL), // OP_TEQ_IMM_VAL
+/* 0011 0011 1000 */ TABDECL(OP_TEQ_IMM_VAL), // OP_TEQ_IMM_VAL
+/* 0011 0011 1001 */ TABDECL(OP_TEQ_IMM_VAL), // OP_TEQ_IMM_VAL
+/* 0011 0011 1010 */ TABDECL(OP_TEQ_IMM_VAL), // OP_TEQ_IMM_VAL
+/* 0011 0011 1011 */ TABDECL(OP_TEQ_IMM_VAL), // OP_TEQ_IMM_VAL
+/* 0011 0011 1100 */ TABDECL(OP_TEQ_IMM_VAL), // OP_TEQ_IMM_VAL
+/* 0011 0011 1101 */ TABDECL(OP_TEQ_IMM_VAL), // OP_TEQ_IMM_VAL
+/* 0011 0011 1110 */ TABDECL(OP_TEQ_IMM_VAL), // OP_TEQ_IMM_VAL
+/* 0011 0011 1111 */ TABDECL(OP_TEQ_IMM_VAL), // OP_TEQ_IMM_VAL
+
+/* 0011 0100 0000 */ TABDECL(OP_UND),
+/* 0011 0100 0001 */ TABDECL(OP_UND),
+/* 0011 0100 0010 */ TABDECL(OP_UND),
+/* 0011 0100 0011 */ TABDECL(OP_UND),
+/* 0011 0100 0100 */ TABDECL(OP_UND),
+/* 0011 0100 0101 */ TABDECL(OP_UND),
+/* 0011 0100 0110 */ TABDECL(OP_UND),
+/* 0011 0100 0111 */ TABDECL(OP_UND),
+/* 0011 0100 1000 */ TABDECL(OP_UND),
+/* 0011 0100 1001 */ TABDECL(OP_UND),
+/* 0011 0100 1010 */ TABDECL(OP_UND),
+/* 0011 0100 1011 */ TABDECL(OP_UND),
+/* 0011 0100 1100 */ TABDECL(OP_UND),
+/* 0011 0100 1101 */ TABDECL(OP_UND),
+/* 0011 0100 1110 */ TABDECL(OP_UND),
+/* 0011 0100 1111 */ TABDECL(OP_UND),
+
+/* 0011 0101 0000 */ TABDECL(OP_CMP_IMM_VAL), // OP_CMP_IMM_VAL
+/* 0011 0101 0001 */ TABDECL(OP_CMP_IMM_VAL), // OP_CMP_IMM_VAL
+/* 0011 0101 0010 */ TABDECL(OP_CMP_IMM_VAL), // OP_CMP_IMM_VAL
+/* 0011 0101 0011 */ TABDECL(OP_CMP_IMM_VAL), // OP_CMP_IMM_VAL
+/* 0011 0101 0100 */ TABDECL(OP_CMP_IMM_VAL), // OP_CMP_IMM_VAL
+/* 0011 0101 0101 */ TABDECL(OP_CMP_IMM_VAL), // OP_CMP_IMM_VAL
+/* 0011 0101 0110 */ TABDECL(OP_CMP_IMM_VAL), // OP_CMP_IMM_VAL
+/* 0011 0101 0111 */ TABDECL(OP_CMP_IMM_VAL), // OP_CMP_IMM_VAL
+/* 0011 0101 1000 */ TABDECL(OP_CMP_IMM_VAL), // OP_CMP_IMM_VAL
+/* 0011 0101 1001 */ TABDECL(OP_CMP_IMM_VAL), // OP_CMP_IMM_VAL
+/* 0011 0101 1010 */ TABDECL(OP_CMP_IMM_VAL), // OP_CMP_IMM_VAL
+/* 0011 0101 1011 */ TABDECL(OP_CMP_IMM_VAL), // OP_CMP_IMM_VAL
+/* 0011 0101 1100 */ TABDECL(OP_CMP_IMM_VAL), // OP_CMP_IMM_VAL
+/* 0011 0101 1101 */ TABDECL(OP_CMP_IMM_VAL), // OP_CMP_IMM_VAL
+/* 0011 0101 1110 */ TABDECL(OP_CMP_IMM_VAL), // OP_CMP_IMM_VAL
+/* 0011 0101 1111 */ TABDECL(OP_CMP_IMM_VAL), // OP_CMP_IMM_VAL
+
+/* 0011 0110 0000 */ TABDECL(OP_MSR_SPSR_IMM_VAL), // OP_MSR_SPSR_IMM_VAL
+/* 0011 0110 0001 */ TABDECL(OP_MSR_SPSR_IMM_VAL), // OP_MSR_SPSR_IMM_VAL
+/* 0011 0110 0010 */ TABDECL(OP_MSR_SPSR_IMM_VAL), // OP_MSR_SPSR_IMM_VAL
+/* 0011 0110 0011 */ TABDECL(OP_MSR_SPSR_IMM_VAL), // OP_MSR_SPSR_IMM_VAL
+/* 0011 0110 0100 */ TABDECL(OP_MSR_SPSR_IMM_VAL), // OP_MSR_SPSR_IMM_VAL
+/* 0011 0110 0101 */ TABDECL(OP_MSR_SPSR_IMM_VAL), // OP_MSR_SPSR_IMM_VAL
+/* 0011 0110 0110 */ TABDECL(OP_MSR_SPSR_IMM_VAL), // OP_MSR_SPSR_IMM_VAL
+/* 0011 0110 0111 */ TABDECL(OP_MSR_SPSR_IMM_VAL), // OP_MSR_SPSR_IMM_VAL
+/* 0011 0110 1000 */ TABDECL(OP_MSR_SPSR_IMM_VAL), // OP_MSR_SPSR_IMM_VAL
+/* 0011 0110 1001 */ TABDECL(OP_MSR_SPSR_IMM_VAL), // OP_MSR_SPSR_IMM_VAL
+/* 0011 0110 1010 */ TABDECL(OP_MSR_SPSR_IMM_VAL), // OP_MSR_SPSR_IMM_VAL
+/* 0011 0110 1011 */ TABDECL(OP_MSR_SPSR_IMM_VAL), // OP_MSR_SPSR_IMM_VAL
+/* 0011 0110 1100 */ TABDECL(OP_MSR_SPSR_IMM_VAL), // OP_MSR_SPSR_IMM_VAL
+/* 0011 0110 1101 */ TABDECL(OP_MSR_SPSR_IMM_VAL), // OP_MSR_SPSR_IMM_VAL
+/* 0011 0110 1110 */ TABDECL(OP_MSR_SPSR_IMM_VAL), // OP_MSR_SPSR_IMM_VAL
+/* 0011 0110 1111 */ TABDECL(OP_MSR_SPSR_IMM_VAL), // OP_MSR_SPSR_IMM_VAL
+
+/* 0011 0111 0000 */ TABDECL(OP_CMN_IMM_VAL), // OP_CMN_IMM_VAL
+/* 0011 0111 0001 */ TABDECL(OP_CMN_IMM_VAL), // OP_CMN_IMM_VAL
+/* 0011 0111 0010 */ TABDECL(OP_CMN_IMM_VAL), // OP_CMN_IMM_VAL
+/* 0011 0111 0011 */ TABDECL(OP_CMN_IMM_VAL), // OP_CMN_IMM_VAL
+/* 0011 0111 0100 */ TABDECL(OP_CMN_IMM_VAL), // OP_CMN_IMM_VAL
+/* 0011 0111 0101 */ TABDECL(OP_CMN_IMM_VAL), // OP_CMN_IMM_VAL
+/* 0011 0111 0110 */ TABDECL(OP_CMN_IMM_VAL), // OP_CMN_IMM_VAL
+/* 0011 0111 0111 */ TABDECL(OP_CMN_IMM_VAL), // OP_CMN_IMM_VAL
+/* 0011 0111 1000 */ TABDECL(OP_CMN_IMM_VAL), // OP_CMN_IMM_VAL
+/* 0011 0111 1001 */ TABDECL(OP_CMN_IMM_VAL), // OP_CMN_IMM_VAL
+/* 0011 0111 1010 */ TABDECL(OP_CMN_IMM_VAL), // OP_CMN_IMM_VAL
+/* 0011 0111 1011 */ TABDECL(OP_CMN_IMM_VAL), // OP_CMN_IMM_VAL
+/* 0011 0111 1100 */ TABDECL(OP_CMN_IMM_VAL), // OP_CMN_IMM_VAL
+/* 0011 0111 1101 */ TABDECL(OP_CMN_IMM_VAL), // OP_CMN_IMM_VAL
+/* 0011 0111 1110 */ TABDECL(OP_CMN_IMM_VAL), // OP_CMN_IMM_VAL
+/* 0011 0111 1111 */ TABDECL(OP_CMN_IMM_VAL), // OP_CMN_IMM_VAL
+
+/* 0011 1000 0000 */ TABDECL(OP_ORR_IMM_VAL), // OP_ORR_IMM_VAL
+/* 0011 1000 0001 */ TABDECL(OP_ORR_IMM_VAL), // OP_ORR_IMM_VAL
+/* 0011 1000 0010 */ TABDECL(OP_ORR_IMM_VAL), // OP_ORR_IMM_VAL
+/* 0011 1000 0011 */ TABDECL(OP_ORR_IMM_VAL), // OP_ORR_IMM_VAL
+/* 0011 1000 0100 */ TABDECL(OP_ORR_IMM_VAL), // OP_ORR_IMM_VAL
+/* 0011 1000 0101 */ TABDECL(OP_ORR_IMM_VAL), // OP_ORR_IMM_VAL
+/* 0011 1000 0110 */ TABDECL(OP_ORR_IMM_VAL), // OP_ORR_IMM_VAL
+/* 0011 1000 0111 */ TABDECL(OP_ORR_IMM_VAL), // OP_ORR_IMM_VAL
+/* 0011 1000 1000 */ TABDECL(OP_ORR_IMM_VAL), // OP_ORR_IMM_VAL
+/* 0011 1000 1001 */ TABDECL(OP_ORR_IMM_VAL), // OP_ORR_IMM_VAL
+/* 0011 1000 1010 */ TABDECL(OP_ORR_IMM_VAL), // OP_ORR_IMM_VAL
+/* 0011 1000 1011 */ TABDECL(OP_ORR_IMM_VAL), // OP_ORR_IMM_VAL
+/* 0011 1000 1100 */ TABDECL(OP_ORR_IMM_VAL), // OP_ORR_IMM_VAL
+/* 0011 1000 1101 */ TABDECL(OP_ORR_IMM_VAL), // OP_ORR_IMM_VAL
+/* 0011 1000 1110 */ TABDECL(OP_ORR_IMM_VAL), // OP_ORR_IMM_VAL
+/* 0011 1000 1111 */ TABDECL(OP_ORR_IMM_VAL), // OP_ORR_IMM_VAL
+
+/* 0011 1001 0000 */ TABDECL(OP_ORR_S_IMM_VAL), // OP_ORR_S_IMM_VAL
+/* 0011 1001 0001 */ TABDECL(OP_ORR_S_IMM_VAL), // OP_ORR_S_IMM_VAL
+/* 0011 1001 0010 */ TABDECL(OP_ORR_S_IMM_VAL), // OP_ORR_S_IMM_VAL
+/* 0011 1001 0011 */ TABDECL(OP_ORR_S_IMM_VAL), // OP_ORR_S_IMM_VAL
+/* 0011 1001 0100 */ TABDECL(OP_ORR_S_IMM_VAL), // OP_ORR_S_IMM_VAL
+/* 0011 1001 0101 */ TABDECL(OP_ORR_S_IMM_VAL), // OP_ORR_S_IMM_VAL
+/* 0011 1001 0110 */ TABDECL(OP_ORR_S_IMM_VAL), // OP_ORR_S_IMM_VAL
+/* 0011 1001 0111 */ TABDECL(OP_ORR_S_IMM_VAL), // OP_ORR_S_IMM_VAL
+/* 0011 1001 1000 */ TABDECL(OP_ORR_S_IMM_VAL), // OP_ORR_S_IMM_VAL
+/* 0011 1001 1001 */ TABDECL(OP_ORR_S_IMM_VAL), // OP_ORR_S_IMM_VAL
+/* 0011 1001 1010 */ TABDECL(OP_ORR_S_IMM_VAL), // OP_ORR_S_IMM_VAL
+/* 0011 1001 1011 */ TABDECL(OP_ORR_S_IMM_VAL), // OP_ORR_S_IMM_VAL
+/* 0011 1001 1100 */ TABDECL(OP_ORR_S_IMM_VAL), // OP_ORR_S_IMM_VAL
+/* 0011 1001 1101 */ TABDECL(OP_ORR_S_IMM_VAL), // OP_ORR_S_IMM_VAL
+/* 0011 1001 1110 */ TABDECL(OP_ORR_S_IMM_VAL), // OP_ORR_S_IMM_VAL
+/* 0011 1001 1111 */ TABDECL(OP_ORR_S_IMM_VAL), // OP_ORR_S_IMM_VAL
+
+/* 0011 1010 0000 */ TABDECL(OP_MOV_IMM_VAL), // OP_MOV_IMM_VAL
+/* 0011 1010 0001 */ TABDECL(OP_MOV_IMM_VAL), // OP_MOV_IMM_VAL
+/* 0011 1010 0010 */ TABDECL(OP_MOV_IMM_VAL), // OP_MOV_IMM_VAL
+/* 0011 1010 0011 */ TABDECL(OP_MOV_IMM_VAL), // OP_MOV_IMM_VAL
+/* 0011 1010 0100 */ TABDECL(OP_MOV_IMM_VAL), // OP_MOV_IMM_VAL
+/* 0011 1010 0101 */ TABDECL(OP_MOV_IMM_VAL), // OP_MOV_IMM_VAL
+/* 0011 1010 0110 */ TABDECL(OP_MOV_IMM_VAL), // OP_MOV_IMM_VAL
+/* 0011 1010 0111 */ TABDECL(OP_MOV_IMM_VAL), // OP_MOV_IMM_VAL
+/* 0011 1010 1000 */ TABDECL(OP_MOV_IMM_VAL), // OP_MOV_IMM_VAL
+/* 0011 1010 1001 */ TABDECL(OP_MOV_IMM_VAL), // OP_MOV_IMM_VAL
+/* 0011 1010 1010 */ TABDECL(OP_MOV_IMM_VAL), // OP_MOV_IMM_VAL
+/* 0011 1010 1011 */ TABDECL(OP_MOV_IMM_VAL), // OP_MOV_IMM_VAL
+/* 0011 1010 1100 */ TABDECL(OP_MOV_IMM_VAL), // OP_MOV_IMM_VAL
+/* 0011 1010 1101 */ TABDECL(OP_MOV_IMM_VAL), // OP_MOV_IMM_VAL
+/* 0011 1010 1110 */ TABDECL(OP_MOV_IMM_VAL), // OP_MOV_IMM_VAL
+/* 0011 1010 1111 */ TABDECL(OP_MOV_IMM_VAL), // OP_MOV_IMM_VAL
+
+/* 0011 1011 0000 */ TABDECL(OP_MOV_S_IMM_VAL), // OP_MOV_S_IMM_VAL
+/* 0011 1011 0001 */ TABDECL(OP_MOV_S_IMM_VAL), // OP_MOV_S_IMM_VAL
+/* 0011 1011 0010 */ TABDECL(OP_MOV_S_IMM_VAL), // OP_MOV_S_IMM_VAL
+/* 0011 1011 0011 */ TABDECL(OP_MOV_S_IMM_VAL), // OP_MOV_S_IMM_VAL
+/* 0011 1011 0100 */ TABDECL(OP_MOV_S_IMM_VAL), // OP_MOV_S_IMM_VAL
+/* 0011 1011 0101 */ TABDECL(OP_MOV_S_IMM_VAL), // OP_MOV_S_IMM_VAL
+/* 0011 1011 0110 */ TABDECL(OP_MOV_S_IMM_VAL), // OP_MOV_S_IMM_VAL
+/* 0011 1011 0111 */ TABDECL(OP_MOV_S_IMM_VAL), // OP_MOV_S_IMM_VAL
+/* 0011 1011 1000 */ TABDECL(OP_MOV_S_IMM_VAL), // OP_MOV_S_IMM_VAL
+/* 0011 1011 1001 */ TABDECL(OP_MOV_S_IMM_VAL), // OP_MOV_S_IMM_VAL
+/* 0011 1011 1010 */ TABDECL(OP_MOV_S_IMM_VAL), // OP_MOV_S_IMM_VAL
+/* 0011 1011 1011 */ TABDECL(OP_MOV_S_IMM_VAL), // OP_MOV_S_IMM_VAL
+/* 0011 1011 1100 */ TABDECL(OP_MOV_S_IMM_VAL), // OP_MOV_S_IMM_VAL
+/* 0011 1011 1101 */ TABDECL(OP_MOV_S_IMM_VAL), // OP_MOV_S_IMM_VAL
+/* 0011 1011 1110 */ TABDECL(OP_MOV_S_IMM_VAL), // OP_MOV_S_IMM_VAL
+/* 0011 1011 1111 */ TABDECL(OP_MOV_S_IMM_VAL), // OP_MOV_S_IMM_VAL
+
+/* 0011 1100 0000 */ TABDECL(OP_BIC_IMM_VAL), // OP_BIC_IMM_VAL
+/* 0011 1100 0001 */ TABDECL(OP_BIC_IMM_VAL), // OP_BIC_IMM_VAL
+/* 0011 1100 0010 */ TABDECL(OP_BIC_IMM_VAL), // OP_BIC_IMM_VAL
+/* 0011 1100 0011 */ TABDECL(OP_BIC_IMM_VAL), // OP_BIC_IMM_VAL
+/* 0011 1100 0100 */ TABDECL(OP_BIC_IMM_VAL), // OP_BIC_IMM_VAL
+/* 0011 1100 0101 */ TABDECL(OP_BIC_IMM_VAL), // OP_BIC_IMM_VAL
+/* 0011 1100 0110 */ TABDECL(OP_BIC_IMM_VAL), // OP_BIC_IMM_VAL
+/* 0011 1100 0111 */ TABDECL(OP_BIC_IMM_VAL), // OP_BIC_IMM_VAL
+/* 0011 1100 1000 */ TABDECL(OP_BIC_IMM_VAL), // OP_BIC_IMM_VAL
+/* 0011 1100 1001 */ TABDECL(OP_BIC_IMM_VAL), // OP_BIC_IMM_VAL
+/* 0011 1100 1010 */ TABDECL(OP_BIC_IMM_VAL), // OP_BIC_IMM_VAL
+/* 0011 1100 1011 */ TABDECL(OP_BIC_IMM_VAL), // OP_BIC_IMM_VAL
+/* 0011 1100 1100 */ TABDECL(OP_BIC_IMM_VAL), // OP_BIC_IMM_VAL
+/* 0011 1100 1101 */ TABDECL(OP_BIC_IMM_VAL), // OP_BIC_IMM_VAL
+/* 0011 1100 1110 */ TABDECL(OP_BIC_IMM_VAL), // OP_BIC_IMM_VAL
+/* 0011 1100 1111 */ TABDECL(OP_BIC_IMM_VAL), // OP_BIC_IMM_VAL
+
+/* 0011 1101 0000 */ TABDECL(OP_BIC_S_IMM_VAL), // OP_BIC_S_IMM_VAL
+/* 0011 1101 0001 */ TABDECL(OP_BIC_S_IMM_VAL), // OP_BIC_S_IMM_VAL
+/* 0011 1101 0010 */ TABDECL(OP_BIC_S_IMM_VAL), // OP_BIC_S_IMM_VAL
+/* 0011 1101 0011 */ TABDECL(OP_BIC_S_IMM_VAL), // OP_BIC_S_IMM_VAL
+/* 0011 1101 0100 */ TABDECL(OP_BIC_S_IMM_VAL), // OP_BIC_S_IMM_VAL
+/* 0011 1101 0101 */ TABDECL(OP_BIC_S_IMM_VAL), // OP_BIC_S_IMM_VAL
+/* 0011 1101 0110 */ TABDECL(OP_BIC_S_IMM_VAL), // OP_BIC_S_IMM_VAL
+/* 0011 1101 0111 */ TABDECL(OP_BIC_S_IMM_VAL), // OP_BIC_S_IMM_VAL
+/* 0011 1101 1000 */ TABDECL(OP_BIC_S_IMM_VAL), // OP_BIC_S_IMM_VAL
+/* 0011 1101 1001 */ TABDECL(OP_BIC_S_IMM_VAL), // OP_BIC_S_IMM_VAL
+/* 0011 1101 1010 */ TABDECL(OP_BIC_S_IMM_VAL), // OP_BIC_S_IMM_VAL
+/* 0011 1101 1011 */ TABDECL(OP_BIC_S_IMM_VAL), // OP_BIC_S_IMM_VAL
+/* 0011 1101 1100 */ TABDECL(OP_BIC_S_IMM_VAL), // OP_BIC_S_IMM_VAL
+/* 0011 1101 1101 */ TABDECL(OP_BIC_S_IMM_VAL), // OP_BIC_S_IMM_VAL
+/* 0011 1101 1110 */ TABDECL(OP_BIC_S_IMM_VAL), // OP_BIC_S_IMM_VAL
+/* 0011 1101 1111 */ TABDECL(OP_BIC_S_IMM_VAL), // OP_BIC_S_IMM_VAL
+
+/* 0011 1110 0000 */ TABDECL(OP_MVN_IMM_VAL), // OP_MVN_IMM_VAL
+/* 0011 1110 0001 */ TABDECL(OP_MVN_IMM_VAL), // OP_MVN_IMM_VAL
+/* 0011 1110 0010 */ TABDECL(OP_MVN_IMM_VAL), // OP_MVN_IMM_VAL
+/* 0011 1110 0011 */ TABDECL(OP_MVN_IMM_VAL), // OP_MVN_IMM_VAL
+/* 0011 1110 0100 */ TABDECL(OP_MVN_IMM_VAL), // OP_MVN_IMM_VAL
+/* 0011 1110 0101 */ TABDECL(OP_MVN_IMM_VAL), // OP_MVN_IMM_VAL
+/* 0011 1110 0110 */ TABDECL(OP_MVN_IMM_VAL), // OP_MVN_IMM_VAL
+/* 0011 1110 0111 */ TABDECL(OP_MVN_IMM_VAL), // OP_MVN_IMM_VAL
+/* 0011 1110 1000 */ TABDECL(OP_MVN_IMM_VAL), // OP_MVN_IMM_VAL
+/* 0011 1110 1001 */ TABDECL(OP_MVN_IMM_VAL), // OP_MVN_IMM_VAL
+/* 0011 1110 1010 */ TABDECL(OP_MVN_IMM_VAL), // OP_MVN_IMM_VAL
+/* 0011 1110 1011 */ TABDECL(OP_MVN_IMM_VAL), // OP_MVN_IMM_VAL
+/* 0011 1110 1100 */ TABDECL(OP_MVN_IMM_VAL), // OP_MVN_IMM_VAL
+/* 0011 1110 1101 */ TABDECL(OP_MVN_IMM_VAL), // OP_MVN_IMM_VAL
+/* 0011 1110 1110 */ TABDECL(OP_MVN_IMM_VAL), // OP_MVN_IMM_VAL
+/* 0011 1110 1111 */ TABDECL(OP_MVN_IMM_VAL), // OP_MVN_IMM_VAL
+
+/* 0011 1111 0000 */ TABDECL(OP_MVN_S_IMM_VAL), // OP_MVN_S_IMM_VAL
+/* 0011 1111 0001 */ TABDECL(OP_MVN_S_IMM_VAL), // OP_MVN_S_IMM_VAL
+/* 0011 1111 0010 */ TABDECL(OP_MVN_S_IMM_VAL), // OP_MVN_S_IMM_VAL
+/* 0011 1111 0011 */ TABDECL(OP_MVN_S_IMM_VAL), // OP_MVN_S_IMM_VAL
+/* 0011 1111 0100 */ TABDECL(OP_MVN_S_IMM_VAL), // OP_MVN_S_IMM_VAL
+/* 0011 1111 0101 */ TABDECL(OP_MVN_S_IMM_VAL), // OP_MVN_S_IMM_VAL
+/* 0011 1111 0110 */ TABDECL(OP_MVN_S_IMM_VAL), // OP_MVN_S_IMM_VAL
+/* 0011 1111 0111 */ TABDECL(OP_MVN_S_IMM_VAL), // OP_MVN_S_IMM_VAL
+/* 0011 1111 1000 */ TABDECL(OP_MVN_S_IMM_VAL), // OP_MVN_S_IMM_VAL
+/* 0011 1111 1001 */ TABDECL(OP_MVN_S_IMM_VAL), // OP_MVN_S_IMM_VAL
+/* 0011 1111 1010 */ TABDECL(OP_MVN_S_IMM_VAL), // OP_MVN_S_IMM_VAL
+/* 0011 1111 1011 */ TABDECL(OP_MVN_S_IMM_VAL), // OP_MVN_S_IMM_VAL
+/* 0011 1111 1100 */ TABDECL(OP_MVN_S_IMM_VAL), // OP_MVN_S_IMM_VAL
+/* 0011 1111 1101 */ TABDECL(OP_MVN_S_IMM_VAL), // OP_MVN_S_IMM_VAL
+/* 0011 1111 1110 */ TABDECL(OP_MVN_S_IMM_VAL), // OP_MVN_S_IMM_VAL
+/* 0011 1111 1111 */ TABDECL(OP_MVN_S_IMM_VAL), // OP_MVN_S_IMM_VAL
+
+/* 0100 0000 0000 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0000 0001 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0000 0010 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0000 0011 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0000 0100 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0000 0101 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0000 0110 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0000 0111 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0000 1000 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0000 1001 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0000 1010 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0000 1011 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0000 1100 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0000 1101 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0000 1110 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0000 1111 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+
+/* 0100 0001 0000 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0001 0001 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0001 0010 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0001 0011 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0001 0100 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0001 0101 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0001 0110 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0001 0111 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0001 1000 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0001 1001 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0001 1010 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0001 1011 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0001 1100 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0001 1101 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0001 1110 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0001 1111 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+
+/* 0100 0010 0000 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0010 0001 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0010 0010 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0010 0011 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0010 0100 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0010 0101 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0010 0110 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0010 0111 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0010 1000 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0010 1001 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0010 1010 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0010 1011 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0010 1100 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0010 1101 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0010 1110 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+/* 0100 0010 1111 */ TABDECL(OP_STR_M_IMM_OFF_POSTIND), // OP_STR_M_IMM_OFF_POSTIND
+
+/* 0100 0011 0000 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0011 0001 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0011 0010 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0011 0011 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0011 0100 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0011 0101 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0011 0110 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0011 0111 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0011 1000 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0011 1001 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0011 1010 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0011 1011 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0011 1100 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0011 1101 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0011 1110 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+/* 0100 0011 1111 */ TABDECL(OP_LDR_M_IMM_OFF_POSTIND), // OP_LDR_M_IMM_OFF_POSTIND
+
+/* 0100 0100 0000 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0100 0001 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0100 0010 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0100 0011 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0100 0100 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0100 0101 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0100 0110 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0100 0111 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0100 1000 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0100 1001 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0100 1010 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0100 1011 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0100 1100 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0100 1101 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0100 1110 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0100 1111 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+
+/* 0100 0101 0000 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0101 0001 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0101 0010 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0101 0011 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0101 0100 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0101 0101 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0101 0110 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0101 0111 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0101 1000 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0101 1001 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0101 1010 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0101 1011 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0101 1100 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0101 1101 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0101 1110 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0101 1111 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+
+/* 0100 0110 0000 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0110 0001 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0110 0010 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0110 0011 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0110 0100 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0110 0101 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0110 0110 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0110 0111 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0110 1000 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0110 1001 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0110 1010 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0110 1011 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0110 1100 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0110 1101 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0110 1110 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+/* 0100 0110 1111 */ TABDECL(OP_STRB_M_IMM_OFF_POSTIND), // OP_STRB_M_IMM_OFF_POSTIND
+
+/* 0100 0111 0000 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0111 0001 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0111 0010 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0111 0011 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0111 0100 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0111 0101 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0111 0110 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0111 0111 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0111 1000 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0111 1001 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0111 1010 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0111 1011 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0111 1100 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0111 1101 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0111 1110 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+/* 0100 0111 1111 */ TABDECL(OP_LDRB_M_IMM_OFF_POSTIND), // OP_LDRB_M_IMM_OFF_POSTIND
+
+/* 0100 1000 0000 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1000 0001 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1000 0010 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1000 0011 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1000 0100 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1000 0101 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1000 0110 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1000 0111 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1000 1000 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1000 1001 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1000 1010 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1000 1011 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1000 1100 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1000 1101 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1000 1110 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1000 1111 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+
+/* 0100 1001 0000 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1001 0001 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1001 0010 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1001 0011 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1001 0100 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1001 0101 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1001 0110 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1001 0111 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1001 1000 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1001 1001 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1001 1010 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1001 1011 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1001 1100 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1001 1101 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1001 1110 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1001 1111 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+
+/* 0100 1010 0000 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1010 0001 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1010 0010 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1010 0011 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1010 0100 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1010 0101 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1010 0110 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1010 0111 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1010 1000 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1010 1001 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1010 1010 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1010 1011 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1010 1100 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1010 1101 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1010 1110 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+/* 0100 1010 1111 */ TABDECL(OP_STR_P_IMM_OFF_POSTIND), // OP_STR_P_IMM_OFF_POSTIND
+
+/* 0100 1011 0000 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1011 0001 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1011 0010 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1011 0011 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1011 0100 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1011 0101 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1011 0110 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1011 0111 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1011 1000 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1011 1001 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1011 1010 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1011 1011 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1011 1100 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1011 1101 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1011 1110 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+/* 0100 1011 1111 */ TABDECL(OP_LDR_P_IMM_OFF_POSTIND), // OP_LDR_P_IMM_OFF_POSTIND
+
+/* 0100 1100 0000 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1100 0001 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1100 0010 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1100 0011 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1100 0100 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1100 0101 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1100 0110 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1100 0111 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1100 1000 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1100 1001 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1100 1010 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1100 1011 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1100 1100 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1100 1101 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1100 1110 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1100 1111 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+
+/* 0100 1101 0000 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1101 0001 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1101 0010 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1101 0011 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1101 0100 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1101 0101 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1101 0110 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1101 0111 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1101 1000 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1101 1001 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1101 1010 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1101 1011 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1101 1100 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1101 1101 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1101 1110 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1101 1111 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+
+/* 0100 1110 0000 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1110 0001 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1110 0010 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1110 0011 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1110 0100 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1110 0101 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1110 0110 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1110 0111 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1110 1000 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1110 1001 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1110 1010 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1110 1011 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1110 1100 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1110 1101 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1110 1110 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+/* 0100 1110 1111 */ TABDECL(OP_STRB_P_IMM_OFF_POSTIND), // OP_STRB_P_IMM_OFF_POSTIND
+
+/* 0100 1111 0000 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1111 0001 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1111 0010 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1111 0011 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1111 0100 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1111 0101 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1111 0110 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1111 0111 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1111 1000 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1111 1001 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1111 1010 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1111 1011 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1111 1100 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1111 1101 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1111 1110 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+/* 0100 1111 1111 */ TABDECL(OP_LDRB_P_IMM_OFF_POSTIND), // OP_LDRB_P_IMM_OFF_POSTIND
+
+/* 0101 0000 0000 */ TABDECL(OP_STR_M_IMM_OFF), // OP_STR_M_IMM_OFF
+/* 0101 0000 0001 */ TABDECL(OP_STR_M_IMM_OFF), // OP_STR_M_IMM_OFF
+/* 0101 0000 0010 */ TABDECL(OP_STR_M_IMM_OFF), // OP_STR_M_IMM_OFF
+/* 0101 0000 0011 */ TABDECL(OP_STR_M_IMM_OFF), // OP_STR_M_IMM_OFF
+/* 0101 0000 0100 */ TABDECL(OP_STR_M_IMM_OFF), // OP_STR_M_IMM_OFF
+/* 0101 0000 0101 */ TABDECL(OP_STR_M_IMM_OFF), // OP_STR_M_IMM_OFF
+/* 0101 0000 0110 */ TABDECL(OP_STR_M_IMM_OFF), // OP_STR_M_IMM_OFF
+/* 0101 0000 0111 */ TABDECL(OP_STR_M_IMM_OFF), // OP_STR_M_IMM_OFF
+/* 0101 0000 1000 */ TABDECL(OP_STR_M_IMM_OFF), // OP_STR_M_IMM_OFF
+/* 0101 0000 1001 */ TABDECL(OP_STR_M_IMM_OFF), // OP_STR_M_IMM_OFF
+/* 0101 0000 1010 */ TABDECL(OP_STR_M_IMM_OFF), // OP_STR_M_IMM_OFF
+/* 0101 0000 1011 */ TABDECL(OP_STR_M_IMM_OFF), // OP_STR_M_IMM_OFF
+/* 0101 0000 1100 */ TABDECL(OP_STR_M_IMM_OFF), // OP_STR_M_IMM_OFF
+/* 0101 0000 1101 */ TABDECL(OP_STR_M_IMM_OFF), // OP_STR_M_IMM_OFF
+/* 0101 0000 1110 */ TABDECL(OP_STR_M_IMM_OFF), // OP_STR_M_IMM_OFF
+/* 0101 0000 1111 */ TABDECL(OP_STR_M_IMM_OFF), // OP_STR_M_IMM_OFF
+
+/* 0101 0001 0000 */ TABDECL(OP_LDR_M_IMM_OFF), // OP_LDR_M_IMM_OFF
+/* 0101 0001 0001 */ TABDECL(OP_LDR_M_IMM_OFF), // OP_LDR_M_IMM_OFF
+/* 0101 0001 0010 */ TABDECL(OP_LDR_M_IMM_OFF), // OP_LDR_M_IMM_OFF
+/* 0101 0001 0011 */ TABDECL(OP_LDR_M_IMM_OFF), // OP_LDR_M_IMM_OFF
+/* 0101 0001 0100 */ TABDECL(OP_LDR_M_IMM_OFF), // OP_LDR_M_IMM_OFF
+/* 0101 0001 0101 */ TABDECL(OP_LDR_M_IMM_OFF), // OP_LDR_M_IMM_OFF
+/* 0101 0001 0110 */ TABDECL(OP_LDR_M_IMM_OFF), // OP_LDR_M_IMM_OFF
+/* 0101 0001 0111 */ TABDECL(OP_LDR_M_IMM_OFF), // OP_LDR_M_IMM_OFF
+/* 0101 0001 1000 */ TABDECL(OP_LDR_M_IMM_OFF), // OP_LDR_M_IMM_OFF
+/* 0101 0001 1001 */ TABDECL(OP_LDR_M_IMM_OFF), // OP_LDR_M_IMM_OFF
+/* 0101 0001 1010 */ TABDECL(OP_LDR_M_IMM_OFF), // OP_LDR_M_IMM_OFF
+/* 0101 0001 1011 */ TABDECL(OP_LDR_M_IMM_OFF), // OP_LDR_M_IMM_OFF
+/* 0101 0001 1100 */ TABDECL(OP_LDR_M_IMM_OFF), // OP_LDR_M_IMM_OFF
+/* 0101 0001 1101 */ TABDECL(OP_LDR_M_IMM_OFF), // OP_LDR_M_IMM_OFF
+/* 0101 0001 1110 */ TABDECL(OP_LDR_M_IMM_OFF), // OP_LDR_M_IMM_OFF
+/* 0101 0001 1111 */ TABDECL(OP_LDR_M_IMM_OFF), // OP_LDR_M_IMM_OFF
+
+/* 0101 0010 0000 */ TABDECL(OP_STR_M_IMM_OFF_PREIND), // OP_STR_M_IMM_OFF_PREIND
+/* 0101 0010 0001 */ TABDECL(OP_STR_M_IMM_OFF_PREIND), // OP_STR_M_IMM_OFF_PREIND
+/* 0101 0010 0010 */ TABDECL(OP_STR_M_IMM_OFF_PREIND), // OP_STR_M_IMM_OFF_PREIND
+/* 0101 0010 0011 */ TABDECL(OP_STR_M_IMM_OFF_PREIND), // OP_STR_M_IMM_OFF_PREIND
+/* 0101 0010 0100 */ TABDECL(OP_STR_M_IMM_OFF_PREIND), // OP_STR_M_IMM_OFF_PREIND
+/* 0101 0010 0101 */ TABDECL(OP_STR_M_IMM_OFF_PREIND), // OP_STR_M_IMM_OFF_PREIND
+/* 0101 0010 0110 */ TABDECL(OP_STR_M_IMM_OFF_PREIND), // OP_STR_M_IMM_OFF_PREIND
+/* 0101 0010 0111 */ TABDECL(OP_STR_M_IMM_OFF_PREIND), // OP_STR_M_IMM_OFF_PREIND
+/* 0101 0010 1000 */ TABDECL(OP_STR_M_IMM_OFF_PREIND), // OP_STR_M_IMM_OFF_PREIND
+/* 0101 0010 1001 */ TABDECL(OP_STR_M_IMM_OFF_PREIND), // OP_STR_M_IMM_OFF_PREIND
+/* 0101 0010 1010 */ TABDECL(OP_STR_M_IMM_OFF_PREIND), // OP_STR_M_IMM_OFF_PREIND
+/* 0101 0010 1011 */ TABDECL(OP_STR_M_IMM_OFF_PREIND), // OP_STR_M_IMM_OFF_PREIND
+/* 0101 0010 1100 */ TABDECL(OP_STR_M_IMM_OFF_PREIND), // OP_STR_M_IMM_OFF_PREIND
+/* 0101 0010 1101 */ TABDECL(OP_STR_M_IMM_OFF_PREIND), // OP_STR_M_IMM_OFF_PREIND
+/* 0101 0010 1110 */ TABDECL(OP_STR_M_IMM_OFF_PREIND), // OP_STR_M_IMM_OFF_PREIND
+/* 0101 0010 1111 */ TABDECL(OP_STR_M_IMM_OFF_PREIND), // OP_STR_M_IMM_OFF_PREIND
+
+/* 0101 0011 0000 */ TABDECL(OP_LDR_M_IMM_OFF_PREIND), // OP_LDR_M_IMM_OFF_PREIND
+/* 0101 0011 0001 */ TABDECL(OP_LDR_M_IMM_OFF_PREIND), // OP_LDR_M_IMM_OFF_PREIND
+/* 0101 0011 0010 */ TABDECL(OP_LDR_M_IMM_OFF_PREIND), // OP_LDR_M_IMM_OFF_PREIND
+/* 0101 0011 0011 */ TABDECL(OP_LDR_M_IMM_OFF_PREIND), // OP_LDR_M_IMM_OFF_PREIND
+/* 0101 0011 0100 */ TABDECL(OP_LDR_M_IMM_OFF_PREIND), // OP_LDR_M_IMM_OFF_PREIND
+/* 0101 0011 0101 */ TABDECL(OP_LDR_M_IMM_OFF_PREIND), // OP_LDR_M_IMM_OFF_PREIND
+/* 0101 0011 0110 */ TABDECL(OP_LDR_M_IMM_OFF_PREIND), // OP_LDR_M_IMM_OFF_PREIND
+/* 0101 0011 0111 */ TABDECL(OP_LDR_M_IMM_OFF_PREIND), // OP_LDR_M_IMM_OFF_PREIND
+/* 0101 0011 1000 */ TABDECL(OP_LDR_M_IMM_OFF_PREIND), // OP_LDR_M_IMM_OFF_PREIND
+/* 0101 0011 1001 */ TABDECL(OP_LDR_M_IMM_OFF_PREIND), // OP_LDR_M_IMM_OFF_PREIND
+/* 0101 0011 1010 */ TABDECL(OP_LDR_M_IMM_OFF_PREIND), // OP_LDR_M_IMM_OFF_PREIND
+/* 0101 0011 1011 */ TABDECL(OP_LDR_M_IMM_OFF_PREIND), // OP_LDR_M_IMM_OFF_PREIND
+/* 0101 0011 1100 */ TABDECL(OP_LDR_M_IMM_OFF_PREIND), // OP_LDR_M_IMM_OFF_PREIND
+/* 0101 0011 1101 */ TABDECL(OP_LDR_M_IMM_OFF_PREIND), // OP_LDR_M_IMM_OFF_PREIND
+/* 0101 0011 1110 */ TABDECL(OP_LDR_M_IMM_OFF_PREIND), // OP_LDR_M_IMM_OFF_PREIND
+/* 0101 0011 1111 */ TABDECL(OP_LDR_M_IMM_OFF_PREIND), // OP_LDR_M_IMM_OFF_PREIND
+
+/* 0101 0100 0000 */ TABDECL(OP_STRB_M_IMM_OFF), // OP_STRB_M_IMM_OFF
+/* 0101 0100 0001 */ TABDECL(OP_STRB_M_IMM_OFF), // OP_STRB_M_IMM_OFF
+/* 0101 0100 0010 */ TABDECL(OP_STRB_M_IMM_OFF), // OP_STRB_M_IMM_OFF
+/* 0101 0100 0011 */ TABDECL(OP_STRB_M_IMM_OFF), // OP_STRB_M_IMM_OFF
+/* 0101 0100 0100 */ TABDECL(OP_STRB_M_IMM_OFF), // OP_STRB_M_IMM_OFF
+/* 0101 0100 0101 */ TABDECL(OP_STRB_M_IMM_OFF), // OP_STRB_M_IMM_OFF
+/* 0101 0100 0110 */ TABDECL(OP_STRB_M_IMM_OFF), // OP_STRB_M_IMM_OFF
+/* 0101 0100 0111 */ TABDECL(OP_STRB_M_IMM_OFF), // OP_STRB_M_IMM_OFF
+/* 0101 0100 1000 */ TABDECL(OP_STRB_M_IMM_OFF), // OP_STRB_M_IMM_OFF
+/* 0101 0100 1001 */ TABDECL(OP_STRB_M_IMM_OFF), // OP_STRB_M_IMM_OFF
+/* 0101 0100 1010 */ TABDECL(OP_STRB_M_IMM_OFF), // OP_STRB_M_IMM_OFF
+/* 0101 0100 1011 */ TABDECL(OP_STRB_M_IMM_OFF), // OP_STRB_M_IMM_OFF
+/* 0101 0100 1100 */ TABDECL(OP_STRB_M_IMM_OFF), // OP_STRB_M_IMM_OFF
+/* 0101 0100 1101 */ TABDECL(OP_STRB_M_IMM_OFF), // OP_STRB_M_IMM_OFF
+/* 0101 0100 1110 */ TABDECL(OP_STRB_M_IMM_OFF), // OP_STRB_M_IMM_OFF
+/* 0101 0100 1111 */ TABDECL(OP_STRB_M_IMM_OFF), // OP_STRB_M_IMM_OFF
+
+/* 0101 0101 0000 */ TABDECL(OP_LDRB_M_IMM_OFF), // OP_LDRB_M_IMM_OFF
+/* 0101 0101 0001 */ TABDECL(OP_LDRB_M_IMM_OFF), // OP_LDRB_M_IMM_OFF
+/* 0101 0101 0010 */ TABDECL(OP_LDRB_M_IMM_OFF), // OP_LDRB_M_IMM_OFF
+/* 0101 0101 0011 */ TABDECL(OP_LDRB_M_IMM_OFF), // OP_LDRB_M_IMM_OFF
+/* 0101 0101 0100 */ TABDECL(OP_LDRB_M_IMM_OFF), // OP_LDRB_M_IMM_OFF
+/* 0101 0101 0101 */ TABDECL(OP_LDRB_M_IMM_OFF), // OP_LDRB_M_IMM_OFF
+/* 0101 0101 0110 */ TABDECL(OP_LDRB_M_IMM_OFF), // OP_LDRB_M_IMM_OFF
+/* 0101 0101 0111 */ TABDECL(OP_LDRB_M_IMM_OFF), // OP_LDRB_M_IMM_OFF
+/* 0101 0101 1000 */ TABDECL(OP_LDRB_M_IMM_OFF), // OP_LDRB_M_IMM_OFF
+/* 0101 0101 1001 */ TABDECL(OP_LDRB_M_IMM_OFF), // OP_LDRB_M_IMM_OFF
+/* 0101 0101 1010 */ TABDECL(OP_LDRB_M_IMM_OFF), // OP_LDRB_M_IMM_OFF
+/* 0101 0101 1011 */ TABDECL(OP_LDRB_M_IMM_OFF), // OP_LDRB_M_IMM_OFF
+/* 0101 0101 1100 */ TABDECL(OP_LDRB_M_IMM_OFF), // OP_LDRB_M_IMM_OFF
+/* 0101 0101 1101 */ TABDECL(OP_LDRB_M_IMM_OFF), // OP_LDRB_M_IMM_OFF
+/* 0101 0101 1110 */ TABDECL(OP_LDRB_M_IMM_OFF), // OP_LDRB_M_IMM_OFF
+/* 0101 0101 1111 */ TABDECL(OP_LDRB_M_IMM_OFF), // OP_LDRB_M_IMM_OFF
+
+/* 0101 0110 0000 */ TABDECL(OP_STRB_M_IMM_OFF_PREIND), // OP_STRB_M_IMM_OFF_PREIND
+/* 0101 0110 0001 */ TABDECL(OP_STRB_M_IMM_OFF_PREIND), // OP_STRB_M_IMM_OFF_PREIND
+/* 0101 0110 0010 */ TABDECL(OP_STRB_M_IMM_OFF_PREIND), // OP_STRB_M_IMM_OFF_PREIND
+/* 0101 0110 0011 */ TABDECL(OP_STRB_M_IMM_OFF_PREIND), // OP_STRB_M_IMM_OFF_PREIND
+/* 0101 0110 0100 */ TABDECL(OP_STRB_M_IMM_OFF_PREIND), // OP_STRB_M_IMM_OFF_PREIND
+/* 0101 0110 0101 */ TABDECL(OP_STRB_M_IMM_OFF_PREIND), // OP_STRB_M_IMM_OFF_PREIND
+/* 0101 0110 0110 */ TABDECL(OP_STRB_M_IMM_OFF_PREIND), // OP_STRB_M_IMM_OFF_PREIND
+/* 0101 0110 0111 */ TABDECL(OP_STRB_M_IMM_OFF_PREIND), // OP_STRB_M_IMM_OFF_PREIND
+/* 0101 0110 1000 */ TABDECL(OP_STRB_M_IMM_OFF_PREIND), // OP_STRB_M_IMM_OFF_PREIND
+/* 0101 0110 1001 */ TABDECL(OP_STRB_M_IMM_OFF_PREIND), // OP_STRB_M_IMM_OFF_PREIND
+/* 0101 0110 1010 */ TABDECL(OP_STRB_M_IMM_OFF_PREIND), // OP_STRB_M_IMM_OFF_PREIND
+/* 0101 0110 1011 */ TABDECL(OP_STRB_M_IMM_OFF_PREIND), // OP_STRB_M_IMM_OFF_PREIND
+/* 0101 0110 1100 */ TABDECL(OP_STRB_M_IMM_OFF_PREIND), // OP_STRB_M_IMM_OFF_PREIND
+/* 0101 0110 1101 */ TABDECL(OP_STRB_M_IMM_OFF_PREIND), // OP_STRB_M_IMM_OFF_PREIND
+/* 0101 0110 1110 */ TABDECL(OP_STRB_M_IMM_OFF_PREIND), // OP_STRB_M_IMM_OFF_PREIND
+/* 0101 0110 1111 */ TABDECL(OP_STRB_M_IMM_OFF_PREIND), // OP_STRB_M_IMM_OFF_PREIND
+
+/* 0101 0111 0000 */ TABDECL(OP_LDRB_M_IMM_OFF_PREIND), // OP_LDRB_M_IMM_OFF_PREIND
+/* 0101 0111 0001 */ TABDECL(OP_LDRB_M_IMM_OFF_PREIND), // OP_LDRB_M_IMM_OFF_PREIND
+/* 0101 0111 0010 */ TABDECL(OP_LDRB_M_IMM_OFF_PREIND), // OP_LDRB_M_IMM_OFF_PREIND
+/* 0101 0111 0011 */ TABDECL(OP_LDRB_M_IMM_OFF_PREIND), // OP_LDRB_M_IMM_OFF_PREIND
+/* 0101 0111 0100 */ TABDECL(OP_LDRB_M_IMM_OFF_PREIND), // OP_LDRB_M_IMM_OFF_PREIND
+/* 0101 0111 0101 */ TABDECL(OP_LDRB_M_IMM_OFF_PREIND), // OP_LDRB_M_IMM_OFF_PREIND
+/* 0101 0111 0110 */ TABDECL(OP_LDRB_M_IMM_OFF_PREIND), // OP_LDRB_M_IMM_OFF_PREIND
+/* 0101 0111 0111 */ TABDECL(OP_LDRB_M_IMM_OFF_PREIND), // OP_LDRB_M_IMM_OFF_PREIND
+/* 0101 0111 1000 */ TABDECL(OP_LDRB_M_IMM_OFF_PREIND), // OP_LDRB_M_IMM_OFF_PREIND
+/* 0101 0111 1001 */ TABDECL(OP_LDRB_M_IMM_OFF_PREIND), // OP_LDRB_M_IMM_OFF_PREIND
+/* 0101 0111 1010 */ TABDECL(OP_LDRB_M_IMM_OFF_PREIND), // OP_LDRB_M_IMM_OFF_PREIND
+/* 0101 0111 1011 */ TABDECL(OP_LDRB_M_IMM_OFF_PREIND), // OP_LDRB_M_IMM_OFF_PREIND
+/* 0101 0111 1100 */ TABDECL(OP_LDRB_M_IMM_OFF_PREIND), // OP_LDRB_M_IMM_OFF_PREIND
+/* 0101 0111 1101 */ TABDECL(OP_LDRB_M_IMM_OFF_PREIND), // OP_LDRB_M_IMM_OFF_PREIND
+/* 0101 0111 1110 */ TABDECL(OP_LDRB_M_IMM_OFF_PREIND), // OP_LDRB_M_IMM_OFF_PREIND
+/* 0101 0111 1111 */ TABDECL(OP_LDRB_M_IMM_OFF_PREIND), // OP_LDRB_M_IMM_OFF_PREIND
+
+/* 0101 1000 0000 */ TABDECL(OP_STR_P_IMM_OFF), // OP_STR_P_IMM_OFF
+/* 0101 1000 0001 */ TABDECL(OP_STR_P_IMM_OFF), // OP_STR_P_IMM_OFF
+/* 0101 1000 0010 */ TABDECL(OP_STR_P_IMM_OFF), // OP_STR_P_IMM_OFF
+/* 0101 1000 0011 */ TABDECL(OP_STR_P_IMM_OFF), // OP_STR_P_IMM_OFF
+/* 0101 1000 0100 */ TABDECL(OP_STR_P_IMM_OFF), // OP_STR_P_IMM_OFF
+/* 0101 1000 0101 */ TABDECL(OP_STR_P_IMM_OFF), // OP_STR_P_IMM_OFF
+/* 0101 1000 0110 */ TABDECL(OP_STR_P_IMM_OFF), // OP_STR_P_IMM_OFF
+/* 0101 1000 0111 */ TABDECL(OP_STR_P_IMM_OFF), // OP_STR_P_IMM_OFF
+/* 0101 1000 1000 */ TABDECL(OP_STR_P_IMM_OFF), // OP_STR_P_IMM_OFF
+/* 0101 1000 1001 */ TABDECL(OP_STR_P_IMM_OFF), // OP_STR_P_IMM_OFF
+/* 0101 1000 1010 */ TABDECL(OP_STR_P_IMM_OFF), // OP_STR_P_IMM_OFF
+/* 0101 1000 1011 */ TABDECL(OP_STR_P_IMM_OFF), // OP_STR_P_IMM_OFF
+/* 0101 1000 1100 */ TABDECL(OP_STR_P_IMM_OFF), // OP_STR_P_IMM_OFF
+/* 0101 1000 1101 */ TABDECL(OP_STR_P_IMM_OFF), // OP_STR_P_IMM_OFF
+/* 0101 1000 1110 */ TABDECL(OP_STR_P_IMM_OFF), // OP_STR_P_IMM_OFF
+/* 0101 1000 1111 */ TABDECL(OP_STR_P_IMM_OFF), // OP_STR_P_IMM_OFF
+
+/* 0101 1001 0000 */ TABDECL(OP_LDR_P_IMM_OFF), // OP_LDR_P_IMM_OFF
+/* 0101 1001 0001 */ TABDECL(OP_LDR_P_IMM_OFF), // OP_LDR_P_IMM_OFF
+/* 0101 1001 0010 */ TABDECL(OP_LDR_P_IMM_OFF), // OP_LDR_P_IMM_OFF
+/* 0101 1001 0011 */ TABDECL(OP_LDR_P_IMM_OFF), // OP_LDR_P_IMM_OFF
+/* 0101 1001 0100 */ TABDECL(OP_LDR_P_IMM_OFF), // OP_LDR_P_IMM_OFF
+/* 0101 1001 0101 */ TABDECL(OP_LDR_P_IMM_OFF), // OP_LDR_P_IMM_OFF
+/* 0101 1001 0110 */ TABDECL(OP_LDR_P_IMM_OFF), // OP_LDR_P_IMM_OFF
+/* 0101 1001 0111 */ TABDECL(OP_LDR_P_IMM_OFF), // OP_LDR_P_IMM_OFF
+/* 0101 1001 1000 */ TABDECL(OP_LDR_P_IMM_OFF), // OP_LDR_P_IMM_OFF
+/* 0101 1001 1001 */ TABDECL(OP_LDR_P_IMM_OFF), // OP_LDR_P_IMM_OFF
+/* 0101 1001 1010 */ TABDECL(OP_LDR_P_IMM_OFF), // OP_LDR_P_IMM_OFF
+/* 0101 1001 1011 */ TABDECL(OP_LDR_P_IMM_OFF), // OP_LDR_P_IMM_OFF
+/* 0101 1001 1100 */ TABDECL(OP_LDR_P_IMM_OFF), // OP_LDR_P_IMM_OFF
+/* 0101 1001 1101 */ TABDECL(OP_LDR_P_IMM_OFF), // OP_LDR_P_IMM_OFF
+/* 0101 1001 1110 */ TABDECL(OP_LDR_P_IMM_OFF), // OP_LDR_P_IMM_OFF
+/* 0101 1001 1111 */ TABDECL(OP_LDR_P_IMM_OFF), // OP_LDR_P_IMM_OFF
+
+/* 0101 1010 0000 */ TABDECL(OP_STR_P_IMM_OFF_PREIND), // OP_STR_P_IMM_OFF_PREIND
+/* 0101 1010 0001 */ TABDECL(OP_STR_P_IMM_OFF_PREIND), // OP_STR_P_IMM_OFF_PREIND
+/* 0101 1010 0010 */ TABDECL(OP_STR_P_IMM_OFF_PREIND), // OP_STR_P_IMM_OFF_PREIND
+/* 0101 1010 0011 */ TABDECL(OP_STR_P_IMM_OFF_PREIND), // OP_STR_P_IMM_OFF_PREIND
+/* 0101 1010 0100 */ TABDECL(OP_STR_P_IMM_OFF_PREIND), // OP_STR_P_IMM_OFF_PREIND
+/* 0101 1010 0101 */ TABDECL(OP_STR_P_IMM_OFF_PREIND), // OP_STR_P_IMM_OFF_PREIND
+/* 0101 1010 0110 */ TABDECL(OP_STR_P_IMM_OFF_PREIND), // OP_STR_P_IMM_OFF_PREIND
+/* 0101 1010 0111 */ TABDECL(OP_STR_P_IMM_OFF_PREIND), // OP_STR_P_IMM_OFF_PREIND
+/* 0101 1010 1000 */ TABDECL(OP_STR_P_IMM_OFF_PREIND), // OP_STR_P_IMM_OFF_PREIND
+/* 0101 1010 1001 */ TABDECL(OP_STR_P_IMM_OFF_PREIND), // OP_STR_P_IMM_OFF_PREIND
+/* 0101 1010 1010 */ TABDECL(OP_STR_P_IMM_OFF_PREIND), // OP_STR_P_IMM_OFF_PREIND
+/* 0101 1010 1011 */ TABDECL(OP_STR_P_IMM_OFF_PREIND), // OP_STR_P_IMM_OFF_PREIND
+/* 0101 1010 1100 */ TABDECL(OP_STR_P_IMM_OFF_PREIND), // OP_STR_P_IMM_OFF_PREIND
+/* 0101 1010 1101 */ TABDECL(OP_STR_P_IMM_OFF_PREIND), // OP_STR_P_IMM_OFF_PREIND
+/* 0101 1010 1110 */ TABDECL(OP_STR_P_IMM_OFF_PREIND), // OP_STR_P_IMM_OFF_PREIND
+/* 0101 1010 1111 */ TABDECL(OP_STR_P_IMM_OFF_PREIND), // OP_STR_P_IMM_OFF_PREIND
+
+/* 0101 1011 0000 */ TABDECL(OP_LDR_P_IMM_OFF_PREIND), // OP_LDR_P_IMM_OFF_PREIND
+/* 0101 1011 0001 */ TABDECL(OP_LDR_P_IMM_OFF_PREIND), // OP_LDR_P_IMM_OFF_PREIND
+/* 0101 1011 0010 */ TABDECL(OP_LDR_P_IMM_OFF_PREIND), // OP_LDR_P_IMM_OFF_PREIND
+/* 0101 1011 0011 */ TABDECL(OP_LDR_P_IMM_OFF_PREIND), // OP_LDR_P_IMM_OFF_PREIND
+/* 0101 1011 0100 */ TABDECL(OP_LDR_P_IMM_OFF_PREIND), // OP_LDR_P_IMM_OFF_PREIND
+/* 0101 1011 0101 */ TABDECL(OP_LDR_P_IMM_OFF_PREIND), // OP_LDR_P_IMM_OFF_PREIND
+/* 0101 1011 0110 */ TABDECL(OP_LDR_P_IMM_OFF_PREIND), // OP_LDR_P_IMM_OFF_PREIND
+/* 0101 1011 0111 */ TABDECL(OP_LDR_P_IMM_OFF_PREIND), // OP_LDR_P_IMM_OFF_PREIND
+/* 0101 1011 1000 */ TABDECL(OP_LDR_P_IMM_OFF_PREIND), // OP_LDR_P_IMM_OFF_PREIND
+/* 0101 1011 1001 */ TABDECL(OP_LDR_P_IMM_OFF_PREIND), // OP_LDR_P_IMM_OFF_PREIND
+/* 0101 1011 1010 */ TABDECL(OP_LDR_P_IMM_OFF_PREIND), // OP_LDR_P_IMM_OFF_PREIND
+/* 0101 1011 1011 */ TABDECL(OP_LDR_P_IMM_OFF_PREIND), // OP_LDR_P_IMM_OFF_PREIND
+/* 0101 1011 1100 */ TABDECL(OP_LDR_P_IMM_OFF_PREIND), // OP_LDR_P_IMM_OFF_PREIND
+/* 0101 1011 1101 */ TABDECL(OP_LDR_P_IMM_OFF_PREIND), // OP_LDR_P_IMM_OFF_PREIND
+/* 0101 1011 1110 */ TABDECL(OP_LDR_P_IMM_OFF_PREIND), // OP_LDR_P_IMM_OFF_PREIND
+/* 0101 1011 1111 */ TABDECL(OP_LDR_P_IMM_OFF_PREIND), // OP_LDR_P_IMM_OFF_PREIND
+
+/* 0101 1100 0000 */ TABDECL(OP_STRB_P_IMM_OFF), // OP_STRB_P_IMM_OFF
+/* 0101 1100 0001 */ TABDECL(OP_STRB_P_IMM_OFF), // OP_STRB_P_IMM_OFF
+/* 0101 1100 0010 */ TABDECL(OP_STRB_P_IMM_OFF), // OP_STRB_P_IMM_OFF
+/* 0101 1100 0011 */ TABDECL(OP_STRB_P_IMM_OFF), // OP_STRB_P_IMM_OFF
+/* 0101 1100 0100 */ TABDECL(OP_STRB_P_IMM_OFF), // OP_STRB_P_IMM_OFF
+/* 0101 1100 0101 */ TABDECL(OP_STRB_P_IMM_OFF), // OP_STRB_P_IMM_OFF
+/* 0101 1100 0110 */ TABDECL(OP_STRB_P_IMM_OFF), // OP_STRB_P_IMM_OFF
+/* 0101 1100 0111 */ TABDECL(OP_STRB_P_IMM_OFF), // OP_STRB_P_IMM_OFF
+/* 0101 1100 1000 */ TABDECL(OP_STRB_P_IMM_OFF), // OP_STRB_P_IMM_OFF
+/* 0101 1100 1001 */ TABDECL(OP_STRB_P_IMM_OFF), // OP_STRB_P_IMM_OFF
+/* 0101 1100 1010 */ TABDECL(OP_STRB_P_IMM_OFF), // OP_STRB_P_IMM_OFF
+/* 0101 1100 1011 */ TABDECL(OP_STRB_P_IMM_OFF), // OP_STRB_P_IMM_OFF
+/* 0101 1100 1100 */ TABDECL(OP_STRB_P_IMM_OFF), // OP_STRB_P_IMM_OFF
+/* 0101 1100 1101 */ TABDECL(OP_STRB_P_IMM_OFF), // OP_STRB_P_IMM_OFF
+/* 0101 1100 1110 */ TABDECL(OP_STRB_P_IMM_OFF), // OP_STRB_P_IMM_OFF
+/* 0101 1100 1111 */ TABDECL(OP_STRB_P_IMM_OFF), // OP_STRB_P_IMM_OFF
+
+/* 0101 1101 0000 */ TABDECL(OP_LDRB_P_IMM_OFF), // OP_LDRB_P_IMM_OFF
+/* 0101 1101 0001 */ TABDECL(OP_LDRB_P_IMM_OFF), // OP_LDRB_P_IMM_OFF
+/* 0101 1101 0010 */ TABDECL(OP_LDRB_P_IMM_OFF), // OP_LDRB_P_IMM_OFF
+/* 0101 1101 0011 */ TABDECL(OP_LDRB_P_IMM_OFF), // OP_LDRB_P_IMM_OFF
+/* 0101 1101 0100 */ TABDECL(OP_LDRB_P_IMM_OFF), // OP_LDRB_P_IMM_OFF
+/* 0101 1101 0101 */ TABDECL(OP_LDRB_P_IMM_OFF), // OP_LDRB_P_IMM_OFF
+/* 0101 1101 0110 */ TABDECL(OP_LDRB_P_IMM_OFF), // OP_LDRB_P_IMM_OFF
+/* 0101 1101 0111 */ TABDECL(OP_LDRB_P_IMM_OFF), // OP_LDRB_P_IMM_OFF
+/* 0101 1101 1000 */ TABDECL(OP_LDRB_P_IMM_OFF), // OP_LDRB_P_IMM_OFF
+/* 0101 1101 1001 */ TABDECL(OP_LDRB_P_IMM_OFF), // OP_LDRB_P_IMM_OFF
+/* 0101 1101 1010 */ TABDECL(OP_LDRB_P_IMM_OFF), // OP_LDRB_P_IMM_OFF
+/* 0101 1101 1011 */ TABDECL(OP_LDRB_P_IMM_OFF), // OP_LDRB_P_IMM_OFF
+/* 0101 1101 1100 */ TABDECL(OP_LDRB_P_IMM_OFF), // OP_LDRB_P_IMM_OFF
+/* 0101 1101 1101 */ TABDECL(OP_LDRB_P_IMM_OFF), // OP_LDRB_P_IMM_OFF
+/* 0101 1101 1110 */ TABDECL(OP_LDRB_P_IMM_OFF), // OP_LDRB_P_IMM_OFF
+/* 0101 1101 1111 */ TABDECL(OP_LDRB_P_IMM_OFF), // OP_LDRB_P_IMM_OFF
+
+/* 0101 1110 0000 */ TABDECL(OP_STRB_P_IMM_OFF_PREIND), // OP_STRB_P_IMM_OFF_PREIND
+/* 0101 1110 0001 */ TABDECL(OP_STRB_P_IMM_OFF_PREIND), // OP_STRB_P_IMM_OFF_PREIND
+/* 0101 1110 0010 */ TABDECL(OP_STRB_P_IMM_OFF_PREIND), // OP_STRB_P_IMM_OFF_PREIND
+/* 0101 1110 0011 */ TABDECL(OP_STRB_P_IMM_OFF_PREIND), // OP_STRB_P_IMM_OFF_PREIND
+/* 0101 1110 0100 */ TABDECL(OP_STRB_P_IMM_OFF_PREIND), // OP_STRB_P_IMM_OFF_PREIND
+/* 0101 1110 0101 */ TABDECL(OP_STRB_P_IMM_OFF_PREIND), // OP_STRB_P_IMM_OFF_PREIND
+/* 0101 1110 0110 */ TABDECL(OP_STRB_P_IMM_OFF_PREIND), // OP_STRB_P_IMM_OFF_PREIND
+/* 0101 1110 0111 */ TABDECL(OP_STRB_P_IMM_OFF_PREIND), // OP_STRB_P_IMM_OFF_PREIND
+/* 0101 1110 1000 */ TABDECL(OP_STRB_P_IMM_OFF_PREIND), // OP_STRB_P_IMM_OFF_PREIND
+/* 0101 1110 1001 */ TABDECL(OP_STRB_P_IMM_OFF_PREIND), // OP_STRB_P_IMM_OFF_PREIND
+/* 0101 1110 1010 */ TABDECL(OP_STRB_P_IMM_OFF_PREIND), // OP_STRB_P_IMM_OFF_PREIND
+/* 0101 1110 1011 */ TABDECL(OP_STRB_P_IMM_OFF_PREIND), // OP_STRB_P_IMM_OFF_PREIND
+/* 0101 1110 1100 */ TABDECL(OP_STRB_P_IMM_OFF_PREIND), // OP_STRB_P_IMM_OFF_PREIND
+/* 0101 1110 1101 */ TABDECL(OP_STRB_P_IMM_OFF_PREIND), // OP_STRB_P_IMM_OFF_PREIND
+/* 0101 1110 1110 */ TABDECL(OP_STRB_P_IMM_OFF_PREIND), // OP_STRB_P_IMM_OFF_PREIND
+/* 0101 1110 1111 */ TABDECL(OP_STRB_P_IMM_OFF_PREIND), // OP_STRB_P_IMM_OFF_PREIND
+
+/* 0101 1111 0000 */ TABDECL(OP_LDRB_P_IMM_OFF_PREIND), // OP_LDRB_P_IMM_OFF_PREIND
+/* 0101 1111 0001 */ TABDECL(OP_LDRB_P_IMM_OFF_PREIND), // OP_LDRB_P_IMM_OFF_PREIND
+/* 0101 1111 0010 */ TABDECL(OP_LDRB_P_IMM_OFF_PREIND), // OP_LDRB_P_IMM_OFF_PREIND
+/* 0101 1111 0011 */ TABDECL(OP_LDRB_P_IMM_OFF_PREIND), // OP_LDRB_P_IMM_OFF_PREIND
+/* 0101 1111 0100 */ TABDECL(OP_LDRB_P_IMM_OFF_PREIND), // OP_LDRB_P_IMM_OFF_PREIND
+/* 0101 1111 0101 */ TABDECL(OP_LDRB_P_IMM_OFF_PREIND), // OP_LDRB_P_IMM_OFF_PREIND
+/* 0101 1111 0110 */ TABDECL(OP_LDRB_P_IMM_OFF_PREIND), // OP_LDRB_P_IMM_OFF_PREIND
+/* 0101 1111 0111 */ TABDECL(OP_LDRB_P_IMM_OFF_PREIND), // OP_LDRB_P_IMM_OFF_PREIND
+/* 0101 1111 1000 */ TABDECL(OP_LDRB_P_IMM_OFF_PREIND), // OP_LDRB_P_IMM_OFF_PREIND
+/* 0101 1111 1001 */ TABDECL(OP_LDRB_P_IMM_OFF_PREIND), // OP_LDRB_P_IMM_OFF_PREIND
+/* 0101 1111 1010 */ TABDECL(OP_LDRB_P_IMM_OFF_PREIND), // OP_LDRB_P_IMM_OFF_PREIND
+/* 0101 1111 1011 */ TABDECL(OP_LDRB_P_IMM_OFF_PREIND), // OP_LDRB_P_IMM_OFF_PREIND
+/* 0101 1111 1100 */ TABDECL(OP_LDRB_P_IMM_OFF_PREIND), // OP_LDRB_P_IMM_OFF_PREIND
+/* 0101 1111 1101 */ TABDECL(OP_LDRB_P_IMM_OFF_PREIND), // OP_LDRB_P_IMM_OFF_PREIND
+/* 0101 1111 1110 */ TABDECL(OP_LDRB_P_IMM_OFF_PREIND), // OP_LDRB_P_IMM_OFF_PREIND
+/* 0101 1111 1111 */ TABDECL(OP_LDRB_P_IMM_OFF_PREIND), // OP_LDRB_P_IMM_OFF_PREIND
+
+/* 0110 0000 0000 */ TABDECL(OP_STR_M_LSL_IMM_OFF_POSTIND), // OP_STR_M_LSL_IMM_OFF_POSTIND
+/* 0110 0000 0001 */ TABDECL(OP_UND),
+/* 0110 0000 0010 */ TABDECL(OP_STR_M_LSR_IMM_OFF_POSTIND), // OP_STR_M_LSR_IMM_OFF_POSTIND
+/* 0110 0000 0011 */ TABDECL(OP_UND),
+/* 0110 0000 0100 */ TABDECL(OP_STR_M_ASR_IMM_OFF_POSTIND), // OP_STR_M_ASR_IMM_OFF_POSTIND
+/* 0110 0000 0101 */ TABDECL(OP_UND),
+/* 0110 0000 0110 */ TABDECL(OP_STR_M_ROR_IMM_OFF_POSTIND), // OP_STR_M_ROR_IMM_OFF_POSTIND
+/* 0110 0000 0111 */ TABDECL(OP_UND),
+/* 0110 0000 1000 */ TABDECL(OP_STR_M_LSL_IMM_OFF_POSTIND), // OP_STR_M_LSL_IMM_OFF_POSTIND
+/* 0110 0000 1001 */ TABDECL(OP_UND),
+/* 0110 0000 1010 */ TABDECL(OP_STR_M_LSR_IMM_OFF_POSTIND), // OP_STR_M_LSR_IMM_OFF_POSTIND
+/* 0110 0000 1011 */ TABDECL(OP_UND),
+/* 0110 0000 1100 */ TABDECL(OP_STR_M_ASR_IMM_OFF_POSTIND), // OP_STR_M_ASR_IMM_OFF_POSTIND
+/* 0110 0000 1101 */ TABDECL(OP_UND),
+/* 0110 0000 1110 */ TABDECL(OP_STR_M_ROR_IMM_OFF_POSTIND), // OP_STR_M_ROR_IMM_OFF_POSTIND
+/* 0110 0000 1111 */ TABDECL(OP_UND),
+
+/* 0110 0001 0000 */ TABDECL(OP_LDR_M_LSL_IMM_OFF_POSTIND), // OP_LDR_M_LSL_IMM_OFF_POSTIND
+/* 0110 0001 0001 */ TABDECL(OP_UND),
+/* 0110 0001 0010 */ TABDECL(OP_LDR_M_LSR_IMM_OFF_POSTIND), // OP_LDR_M_LSR_IMM_OFF_POSTIND
+/* 0110 0001 0011 */ TABDECL(OP_UND),
+/* 0110 0001 0100 */ TABDECL(OP_LDR_M_ASR_IMM_OFF_POSTIND), // OP_LDR_M_ASR_IMM_OFF_POSTIND
+/* 0110 0001 0101 */ TABDECL(OP_UND),
+/* 0110 0001 0110 */ TABDECL(OP_LDR_M_ROR_IMM_OFF_POSTIND), // OP_LDR_M_ROR_IMM_OFF_POSTIND
+/* 0110 0001 0111 */ TABDECL(OP_UND),
+/* 0110 0001 1000 */ TABDECL(OP_LDR_M_LSL_IMM_OFF_POSTIND), // OP_LDR_M_LSL_IMM_OFF_POSTIND
+/* 0110 0001 1001 */ TABDECL(OP_UND),
+/* 0110 0001 1010 */ TABDECL(OP_LDR_M_LSR_IMM_OFF_POSTIND), // OP_LDR_M_LSR_IMM_OFF_POSTIND
+/* 0110 0001 1011 */ TABDECL(OP_UND),
+/* 0110 0001 1100 */ TABDECL(OP_LDR_M_ASR_IMM_OFF_POSTIND), // OP_LDR_M_ASR_IMM_OFF_POSTIND
+/* 0110 0001 1101 */ TABDECL(OP_UND),
+/* 0110 0001 1110 */ TABDECL(OP_LDR_M_ROR_IMM_OFF_POSTIND), // OP_LDR_M_ROR_IMM_OFF_POSTIND
+/* 0110 0001 1111 */ TABDECL(OP_UND),
+
+/* 0110 0010 0000 */ TABDECL(OP_STR_M_LSL_IMM_OFF_POSTIND), // OP_STR_M_LSL_IMM_OFF_POSTIND
+/* 0110 0010 0001 */ TABDECL(OP_UND),
+/* 0110 0010 0010 */ TABDECL(OP_STR_M_LSR_IMM_OFF_POSTIND), // OP_STR_M_LSR_IMM_OFF_POSTIND
+/* 0110 0010 0011 */ TABDECL(OP_UND),
+/* 0110 0010 0100 */ TABDECL(OP_STR_M_ASR_IMM_OFF_POSTIND), // OP_STR_M_ASR_IMM_OFF_POSTIND
+/* 0110 0010 0101 */ TABDECL(OP_UND),
+/* 0110 0010 0110 */ TABDECL(OP_STR_M_ROR_IMM_OFF_POSTIND), // OP_STR_M_ROR_IMM_OFF_POSTIND
+/* 0110 0010 0111 */ TABDECL(OP_UND),
+/* 0110 0010 1000 */ TABDECL(OP_STR_M_LSL_IMM_OFF_POSTIND), // OP_STR_M_LSL_IMM_OFF_POSTIND
+/* 0110 0010 1001 */ TABDECL(OP_UND),
+/* 0110 0010 1010 */ TABDECL(OP_STR_M_LSR_IMM_OFF_POSTIND), // OP_STR_M_LSR_IMM_OFF_POSTIND
+/* 0110 0010 1011 */ TABDECL(OP_UND),
+/* 0110 0010 1100 */ TABDECL(OP_STR_M_ASR_IMM_OFF_POSTIND), // OP_STR_M_ASR_IMM_OFF_POSTIND
+/* 0110 0010 1101 */ TABDECL(OP_UND),
+/* 0110 0010 1110 */ TABDECL(OP_STR_M_ROR_IMM_OFF_POSTIND), // OP_STR_M_ROR_IMM_OFF_POSTIND
+/* 0110 0010 1111 */ TABDECL(OP_UND),
+
+/* 0110 0011 0000 */ TABDECL(OP_LDR_M_LSL_IMM_OFF_POSTIND), // OP_LDR_M_LSL_IMM_OFF_POSTIND
+/* 0110 0011 0001 */ TABDECL(OP_UND),
+/* 0110 0011 0010 */ TABDECL(OP_LDR_M_LSR_IMM_OFF_POSTIND), // OP_LDR_M_LSR_IMM_OFF_POSTIND
+/* 0110 0011 0011 */ TABDECL(OP_UND),
+/* 0110 0011 0100 */ TABDECL(OP_LDR_M_ASR_IMM_OFF_POSTIND), // OP_LDR_M_ASR_IMM_OFF_POSTIND
+/* 0110 0011 0101 */ TABDECL(OP_UND),
+/* 0110 0011 0110 */ TABDECL(OP_LDR_M_ROR_IMM_OFF_POSTIND), // OP_LDR_M_ROR_IMM_OFF_POSTIND
+/* 0110 0011 0111 */ TABDECL(OP_UND),
+/* 0110 0011 1000 */ TABDECL(OP_LDR_M_LSL_IMM_OFF_POSTIND), // OP_LDR_M_LSL_IMM_OFF_POSTIND
+/* 0110 0011 1001 */ TABDECL(OP_UND),
+/* 0110 0011 1010 */ TABDECL(OP_LDR_M_LSR_IMM_OFF_POSTIND), // OP_LDR_M_LSR_IMM_OFF_POSTIND
+/* 0110 0011 1011 */ TABDECL(OP_UND),
+/* 0110 0011 1100 */ TABDECL(OP_LDR_M_ASR_IMM_OFF_POSTIND), // OP_LDR_M_ASR_IMM_OFF_POSTIND
+/* 0110 0011 1101 */ TABDECL(OP_UND),
+/* 0110 0011 1110 */ TABDECL(OP_LDR_M_ROR_IMM_OFF_POSTIND), // OP_LDR_M_ROR_IMM_OFF_POSTIND
+/* 0110 0011 1111 */ TABDECL(OP_UND),
+
+/* 0110 0100 0000 */ TABDECL(OP_STRB_M_LSL_IMM_OFF_POSTIND), // OP_STRB_M_LSL_IMM_OFF_POSTIND
+/* 0110 0100 0001 */ TABDECL(OP_UND),
+/* 0110 0100 0010 */ TABDECL(OP_STRB_M_LSR_IMM_OFF_POSTIND), // OP_STRB_M_LSR_IMM_OFF_POSTIND
+/* 0110 0100 0011 */ TABDECL(OP_UND),
+/* 0110 0100 0100 */ TABDECL(OP_STRB_M_ASR_IMM_OFF_POSTIND), // OP_STRB_M_ASR_IMM_OFF_POSTIND
+/* 0110 0100 0101 */ TABDECL(OP_UND),
+/* 0110 0100 0110 */ TABDECL(OP_STRB_M_ROR_IMM_OFF_POSTIND), // OP_STRB_M_ROR_IMM_OFF_POSTIND
+/* 0110 0100 0111 */ TABDECL(OP_UND),
+/* 0110 0100 1000 */ TABDECL(OP_STRB_M_LSL_IMM_OFF_POSTIND), // OP_STRB_M_LSL_IMM_OFF_POSTIND
+/* 0110 0100 1001 */ TABDECL(OP_UND),
+/* 0110 0100 1010 */ TABDECL(OP_STRB_M_LSR_IMM_OFF_POSTIND), // OP_STRB_M_LSR_IMM_OFF_POSTIND
+/* 0110 0100 1011 */ TABDECL(OP_UND),
+/* 0110 0100 1100 */ TABDECL(OP_STRB_M_ASR_IMM_OFF_POSTIND), // OP_STRB_M_ASR_IMM_OFF_POSTIND
+/* 0110 0100 1101 */ TABDECL(OP_UND),
+/* 0110 0100 1110 */ TABDECL(OP_STRB_M_ROR_IMM_OFF_POSTIND), // OP_STRB_M_ROR_IMM_OFF_POSTIND
+/* 0110 0100 1111 */ TABDECL(OP_UND),
+
+/* 0110 0101 0000 */ TABDECL(OP_LDRB_M_LSL_IMM_OFF_POSTIND), // OP_LDRB_M_LSL_IMM_OFF_POSTIND
+/* 0110 0101 0001 */ TABDECL(OP_UND),
+/* 0110 0101 0010 */ TABDECL(OP_LDRB_M_LSR_IMM_OFF_POSTIND), // OP_LDRB_M_LSR_IMM_OFF_POSTIND
+/* 0110 0101 0011 */ TABDECL(OP_UND),
+/* 0110 0101 0100 */ TABDECL(OP_LDRB_M_ASR_IMM_OFF_POSTIND), // OP_LDRB_M_ASR_IMM_OFF_POSTIND
+/* 0110 0101 0101 */ TABDECL(OP_UND),
+/* 0110 0101 0110 */ TABDECL(OP_LDRB_M_ROR_IMM_OFF_POSTIND), // OP_LDRB_M_ROR_IMM_OFF_POSTIND
+/* 0110 0101 0111 */ TABDECL(OP_UND),
+/* 0110 0101 1000 */ TABDECL(OP_LDRB_M_LSL_IMM_OFF_POSTIND), // OP_LDRB_M_LSL_IMM_OFF_POSTIND
+/* 0110 0101 1001 */ TABDECL(OP_UND),
+/* 0110 0101 1010 */ TABDECL(OP_LDRB_M_LSR_IMM_OFF_POSTIND), // OP_LDRB_M_LSR_IMM_OFF_POSTIND
+/* 0110 0101 1011 */ TABDECL(OP_UND),
+/* 0110 0101 1100 */ TABDECL(OP_LDRB_M_ASR_IMM_OFF_POSTIND), // OP_LDRB_M_ASR_IMM_OFF_POSTIND
+/* 0110 0101 1101 */ TABDECL(OP_UND),
+/* 0110 0101 1110 */ TABDECL(OP_LDRB_M_ROR_IMM_OFF_POSTIND), // OP_LDRB_M_ROR_IMM_OFF_POSTIND
+/* 0110 0101 1111 */ TABDECL(OP_UND),
+
+/* 0110 0110 0000 */ TABDECL(OP_STRB_M_LSL_IMM_OFF_POSTIND), // OP_STRB_M_LSL_IMM_OFF_POSTIND
+/* 0110 0110 0001 */ TABDECL(OP_UND),
+/* 0110 0110 0010 */ TABDECL(OP_STRB_M_LSR_IMM_OFF_POSTIND), // OP_STRB_M_LSR_IMM_OFF_POSTIND
+/* 0110 0110 0011 */ TABDECL(OP_UND),
+/* 0110 0110 0100 */ TABDECL(OP_STRB_M_ASR_IMM_OFF_POSTIND), // OP_STRB_M_ASR_IMM_OFF_POSTIND
+/* 0110 0110 0101 */ TABDECL(OP_UND),
+/* 0110 0110 0110 */ TABDECL(OP_STRB_M_ROR_IMM_OFF_POSTIND), // OP_STRB_M_ROR_IMM_OFF_POSTIND
+/* 0110 0110 0111 */ TABDECL(OP_UND),
+/* 0110 0110 1000 */ TABDECL(OP_STRB_M_LSL_IMM_OFF_POSTIND), // OP_STRB_M_LSL_IMM_OFF_POSTIND
+/* 0110 0110 1001 */ TABDECL(OP_UND),
+/* 0110 0110 1010 */ TABDECL(OP_STRB_M_LSR_IMM_OFF_POSTIND), // OP_STRB_M_LSR_IMM_OFF_POSTIND
+/* 0110 0110 1011 */ TABDECL(OP_UND),
+/* 0110 0110 1100 */ TABDECL(OP_STRB_M_ASR_IMM_OFF_POSTIND), // OP_STRB_M_ASR_IMM_OFF_POSTIND
+/* 0110 0110 1101 */ TABDECL(OP_UND),
+/* 0110 0110 1110 */ TABDECL(OP_STRB_M_ROR_IMM_OFF_POSTIND), // OP_STRB_M_ROR_IMM_OFF_POSTIND
+/* 0110 0110 1111 */ TABDECL(OP_UND),
+
+/* 0110 0111 0000 */ TABDECL(OP_LDRB_M_LSL_IMM_OFF_POSTIND), // OP_LDRB_M_LSL_IMM_OFF_POSTIND
+/* 0110 0111 0001 */ TABDECL(OP_UND),
+/* 0110 0111 0010 */ TABDECL(OP_LDRB_M_LSR_IMM_OFF_POSTIND), // OP_LDRB_M_LSR_IMM_OFF_POSTIND
+/* 0110 0111 0011 */ TABDECL(OP_UND),
+/* 0110 0111 0100 */ TABDECL(OP_LDRB_M_ASR_IMM_OFF_POSTIND), // OP_LDRB_M_ASR_IMM_OFF_POSTIND
+/* 0110 0111 0101 */ TABDECL(OP_UND),
+/* 0110 0111 0110 */ TABDECL(OP_LDRB_M_ROR_IMM_OFF_POSTIND), // OP_LDRB_M_ROR_IMM_OFF_POSTIND
+/* 0110 0111 0111 */ TABDECL(OP_UND),
+/* 0110 0111 1000 */ TABDECL(OP_LDRB_M_LSL_IMM_OFF_POSTIND), // OP_LDRB_M_LSL_IMM_OFF_POSTIND
+/* 0110 0111 1001 */ TABDECL(OP_UND),
+/* 0110 0111 1010 */ TABDECL(OP_LDRB_M_LSR_IMM_OFF_POSTIND), // OP_LDRB_M_LSR_IMM_OFF_POSTIND
+/* 0110 0111 1011 */ TABDECL(OP_UND),
+/* 0110 0111 1100 */ TABDECL(OP_LDRB_M_ASR_IMM_OFF_POSTIND), // OP_LDRB_M_ASR_IMM_OFF_POSTIND
+/* 0110 0111 1101 */ TABDECL(OP_UND),
+/* 0110 0111 1110 */ TABDECL(OP_LDRB_M_ROR_IMM_OFF_POSTIND), // OP_LDRB_M_ROR_IMM_OFF_POSTIND
+/* 0110 0111 1111 */ TABDECL(OP_UND),
+
+/* 0110 1000 0000 */ TABDECL(OP_STR_P_LSL_IMM_OFF_POSTIND), // OP_STR_P_LSL_IMM_OFF_POSTIND
+/* 0110 1000 0001 */ TABDECL(OP_UND),
+/* 0110 1000 0010 */ TABDECL(OP_STR_P_LSR_IMM_OFF_POSTIND), // OP_STR_P_LSR_IMM_OFF_POSTIND
+/* 0110 1000 0011 */ TABDECL(OP_UND),
+/* 0110 1000 0100 */ TABDECL(OP_STR_P_ASR_IMM_OFF_POSTIND), // OP_STR_P_ASR_IMM_OFF_POSTIND
+/* 0110 1000 0101 */ TABDECL(OP_UND),
+/* 0110 1000 0110 */ TABDECL(OP_STR_P_ROR_IMM_OFF_POSTIND), // OP_STR_P_ROR_IMM_OFF_POSTIND
+/* 0110 1000 0111 */ TABDECL(OP_UND),
+/* 0110 1000 1000 */ TABDECL(OP_STR_P_LSL_IMM_OFF_POSTIND), // OP_STR_P_LSL_IMM_OFF_POSTIND
+/* 0110 1000 1001 */ TABDECL(OP_UND),
+/* 0110 1000 1010 */ TABDECL(OP_STR_P_LSR_IMM_OFF_POSTIND), // OP_STR_P_LSR_IMM_OFF_POSTIND
+/* 0110 1000 1011 */ TABDECL(OP_UND),
+/* 0110 1000 1100 */ TABDECL(OP_STR_P_ASR_IMM_OFF_POSTIND), // OP_STR_P_ASR_IMM_OFF_POSTIND
+/* 0110 1000 1101 */ TABDECL(OP_UND),
+/* 0110 1000 1110 */ TABDECL(OP_STR_P_ROR_IMM_OFF_POSTIND), // OP_STR_P_ROR_IMM_OFF_POSTIND
+/* 0110 1000 1111 */ TABDECL(OP_UND),
+
+/* 0110 1001 0000 */ TABDECL(OP_LDR_P_LSL_IMM_OFF_POSTIND), // OP_LDR_P_LSL_IMM_OFF_POSTIND
+/* 0110 1001 0001 */ TABDECL(OP_UND),
+/* 0110 1001 0010 */ TABDECL(OP_LDR_P_LSR_IMM_OFF_POSTIND), // OP_LDR_P_LSR_IMM_OFF_POSTIND
+/* 0110 1001 0011 */ TABDECL(OP_UND),
+/* 0110 1001 0100 */ TABDECL(OP_LDR_P_ASR_IMM_OFF_POSTIND), // OP_LDR_P_ASR_IMM_OFF_POSTIND
+/* 0110 1001 0101 */ TABDECL(OP_UND),
+/* 0110 1001 0110 */ TABDECL(OP_LDR_P_ROR_IMM_OFF_POSTIND), // OP_LDR_P_ROR_IMM_OFF_POSTIND
+/* 0110 1001 0111 */ TABDECL(OP_UND),
+/* 0110 1001 1000 */ TABDECL(OP_LDR_P_LSL_IMM_OFF_POSTIND), // OP_LDR_P_LSL_IMM_OFF_POSTIND
+/* 0110 1001 1001 */ TABDECL(OP_UND),
+/* 0110 1001 1010 */ TABDECL(OP_LDR_P_LSR_IMM_OFF_POSTIND), // OP_LDR_P_LSR_IMM_OFF_POSTIND
+/* 0110 1001 1011 */ TABDECL(OP_UND),
+/* 0110 1001 1100 */ TABDECL(OP_LDR_P_ASR_IMM_OFF_POSTIND), // OP_LDR_P_ASR_IMM_OFF_POSTIND
+/* 0110 1001 1101 */ TABDECL(OP_UND),
+/* 0110 1001 1110 */ TABDECL(OP_LDR_P_ROR_IMM_OFF_POSTIND), // OP_LDR_P_ROR_IMM_OFF_POSTIND
+/* 0110 1001 1111 */ TABDECL(OP_UND),
+
+/* 0110 1010 0000 */ TABDECL(OP_STR_P_LSL_IMM_OFF_POSTIND), // OP_STR_P_LSL_IMM_OFF_POSTIND
+/* 0110 1010 0001 */ TABDECL(OP_UND),
+/* 0110 1010 0010 */ TABDECL(OP_STR_P_LSR_IMM_OFF_POSTIND), // OP_STR_P_LSR_IMM_OFF_POSTIND
+/* 0110 1010 0011 */ TABDECL(OP_UND),
+/* 0110 1010 0100 */ TABDECL(OP_STR_P_ASR_IMM_OFF_POSTIND), // OP_STR_P_ASR_IMM_OFF_POSTIND
+/* 0110 1010 0101 */ TABDECL(OP_UND),
+/* 0110 1010 0110 */ TABDECL(OP_STR_P_ROR_IMM_OFF_POSTIND), // OP_STR_P_ROR_IMM_OFF_POSTIND
+/* 0110 1010 0111 */ TABDECL(OP_UND),
+/* 0110 1010 1000 */ TABDECL(OP_STR_P_LSL_IMM_OFF_POSTIND), // OP_STR_P_LSL_IMM_OFF_POSTIND
+/* 0110 1010 1001 */ TABDECL(OP_UND),
+/* 0110 1010 1010 */ TABDECL(OP_STR_P_LSR_IMM_OFF_POSTIND), // OP_STR_P_LSR_IMM_OFF_POSTIND
+/* 0110 1010 1011 */ TABDECL(OP_UND),
+/* 0110 1010 1100 */ TABDECL(OP_STR_P_ASR_IMM_OFF_POSTIND), // OP_STR_P_ASR_IMM_OFF_POSTIND
+/* 0110 1010 1101 */ TABDECL(OP_UND),
+/* 0110 1010 1110 */ TABDECL(OP_STR_P_ROR_IMM_OFF_POSTIND), // OP_STR_P_ROR_IMM_OFF_POSTIND
+/* 0110 1010 1111 */ TABDECL(OP_UND),
+
+/* 0110 1011 0000 */ TABDECL(OP_LDR_P_LSL_IMM_OFF_POSTIND), // OP_LDR_P_LSL_IMM_OFF_POSTIND
+/* 0110 1011 0001 */ TABDECL(OP_UND),
+/* 0110 1011 0010 */ TABDECL(OP_LDR_P_LSL_IMM_OFF_POSTIND), // OP_LDR_P_LSL_IMM_OFF_POSTIND
+/* 0110 1011 0011 */ TABDECL(OP_UND),
+/* 0110 1011 0100 */ TABDECL(OP_LDR_P_LSL_IMM_OFF_POSTIND), // OP_LDR_P_LSL_IMM_OFF_POSTIND
+/* 0110 1011 0101 */ TABDECL(OP_UND),
+/* 0110 1011 0110 */ TABDECL(OP_LDR_P_LSL_IMM_OFF_POSTIND), // OP_LDR_P_LSL_IMM_OFF_POSTIND
+/* 0110 1011 0111 */ TABDECL(OP_UND),
+/* 0110 1011 1000 */ TABDECL(OP_LDR_P_LSL_IMM_OFF_POSTIND), // OP_LDR_P_LSL_IMM_OFF_POSTIND
+/* 0110 1011 1001 */ TABDECL(OP_UND),
+/* 0110 1011 1010 */ TABDECL(OP_LDR_P_LSL_IMM_OFF_POSTIND), // OP_LDR_P_LSL_IMM_OFF_POSTIND
+/* 0110 1011 1011 */ TABDECL(OP_UND),
+/* 0110 1011 1100 */ TABDECL(OP_LDR_P_LSL_IMM_OFF_POSTIND), // OP_LDR_P_LSL_IMM_OFF_POSTIND
+/* 0110 1011 1101 */ TABDECL(OP_UND),
+/* 0110 1011 1110 */ TABDECL(OP_LDR_P_LSL_IMM_OFF_POSTIND), // OP_LDR_P_LSL_IMM_OFF_POSTIND
+/* 0110 1011 1111 */ TABDECL(OP_UND),
+
+/* 0110 1100 0000 */ TABDECL(OP_STRB_P_LSL_IMM_OFF_POSTIND), // OP_STRB_P_LSL_IMM_OFF_POSTIND
+/* 0110 1100 0001 */ TABDECL(OP_UND),
+/* 0110 1100 0010 */ TABDECL(OP_STRB_P_LSR_IMM_OFF_POSTIND), // OP_STRB_P_LSR_IMM_OFF_POSTIND
+/* 0110 1100 0011 */ TABDECL(OP_UND),
+/* 0110 1100 0100 */ TABDECL(OP_STRB_P_ASR_IMM_OFF_POSTIND), // OP_STRB_P_ASR_IMM_OFF_POSTIND
+/* 0110 1100 0101 */ TABDECL(OP_UND),
+/* 0110 1100 0110 */ TABDECL(OP_STRB_P_ROR_IMM_OFF_POSTIND), // OP_STRB_P_ROR_IMM_OFF_POSTIND
+/* 0110 1100 0111 */ TABDECL(OP_UND),
+/* 0110 1100 1000 */ TABDECL(OP_STRB_P_LSL_IMM_OFF_POSTIND), // OP_STRB_P_LSL_IMM_OFF_POSTIND
+/* 0110 1100 1001 */ TABDECL(OP_UND),
+/* 0110 1100 1010 */ TABDECL(OP_STRB_P_LSR_IMM_OFF_POSTIND), // OP_STRB_P_LSR_IMM_OFF_POSTIND
+/* 0110 1100 1011 */ TABDECL(OP_UND),
+/* 0110 1100 1100 */ TABDECL(OP_STRB_P_ASR_IMM_OFF_POSTIND), // OP_STRB_P_ASR_IMM_OFF_POSTIND
+/* 0110 1100 1101 */ TABDECL(OP_UND),
+/* 0110 1100 1110 */ TABDECL(OP_STRB_P_ROR_IMM_OFF_POSTIND), // OP_STRB_P_ROR_IMM_OFF_POSTIND
+/* 0110 1100 1111 */ TABDECL(OP_UND),
+
+/* 0110 1101 0000 */ TABDECL(OP_LDRB_P_LSL_IMM_OFF_POSTIND), // OP_LDRB_P_LSL_IMM_OFF_POSTIND
+/* 0110 1101 0001 */ TABDECL(OP_UND),
+/* 0110 1101 0010 */ TABDECL(OP_LDRB_P_LSR_IMM_OFF_POSTIND), // OP_LDRB_P_LSR_IMM_OFF_POSTIND
+/* 0110 1101 0011 */ TABDECL(OP_UND),
+/* 0110 1101 0100 */ TABDECL(OP_LDRB_P_ASR_IMM_OFF_POSTIND), // OP_LDRB_P_ASR_IMM_OFF_POSTIND
+/* 0110 1101 0101 */ TABDECL(OP_UND),
+/* 0110 1101 0110 */ TABDECL(OP_LDRB_P_ROR_IMM_OFF_POSTIND), // OP_LDRB_P_ROR_IMM_OFF_POSTIND
+/* 0110 1101 0111 */ TABDECL(OP_UND),
+/* 0110 1101 1000 */ TABDECL(OP_LDRB_P_LSL_IMM_OFF_POSTIND), // OP_LDRB_P_LSL_IMM_OFF_POSTIND
+/* 0110 1101 1001 */ TABDECL(OP_UND),
+/* 0110 1101 1010 */ TABDECL(OP_LDRB_P_LSR_IMM_OFF_POSTIND), // OP_LDRB_P_LSR_IMM_OFF_POSTIND
+/* 0110 1101 1011 */ TABDECL(OP_UND),
+/* 0110 1101 1100 */ TABDECL(OP_LDRB_P_ASR_IMM_OFF_POSTIND), // OP_LDRB_P_ASR_IMM_OFF_POSTIND
+/* 0110 1101 1101 */ TABDECL(OP_UND),
+/* 0110 1101 1110 */ TABDECL(OP_LDRB_P_ROR_IMM_OFF_POSTIND), // OP_LDRB_P_ROR_IMM_OFF_POSTIND
+/* 0110 1101 1111 */ TABDECL(OP_UND),
+
+/* 0110 1110 0000 */ TABDECL(OP_STRB_P_LSL_IMM_OFF_POSTIND), // OP_STRB_P_LSL_IMM_OFF_POSTIND
+/* 0110 1110 0001 */ TABDECL(OP_UND),
+/* 0110 1110 0010 */ TABDECL(OP_STRB_P_LSR_IMM_OFF_POSTIND), // OP_STRB_P_LSR_IMM_OFF_POSTIND
+/* 0110 1110 0011 */ TABDECL(OP_UND),
+/* 0110 1110 0100 */ TABDECL(OP_STRB_P_ASR_IMM_OFF_POSTIND), // OP_STRB_P_ASR_IMM_OFF_POSTIND
+/* 0110 1110 0101 */ TABDECL(OP_UND),
+/* 0110 1110 0110 */ TABDECL(OP_STRB_P_ROR_IMM_OFF_POSTIND), // OP_STRB_P_ROR_IMM_OFF_POSTIND
+/* 0110 1110 0111 */ TABDECL(OP_UND),
+/* 0110 1110 1000 */ TABDECL(OP_STRB_P_LSL_IMM_OFF_POSTIND), // OP_STRB_P_LSL_IMM_OFF_POSTIND
+/* 0110 1110 1001 */ TABDECL(OP_UND),
+/* 0110 1110 1010 */ TABDECL(OP_STRB_P_LSR_IMM_OFF_POSTIND), // OP_STRB_P_LSR_IMM_OFF_POSTIND
+/* 0110 1110 1011 */ TABDECL(OP_UND),
+/* 0110 1110 1100 */ TABDECL(OP_STRB_P_ASR_IMM_OFF_POSTIND), // OP_STRB_P_ASR_IMM_OFF_POSTIND
+/* 0110 1110 1101 */ TABDECL(OP_UND),
+/* 0110 1110 1110 */ TABDECL(OP_STRB_P_ROR_IMM_OFF_POSTIND), // OP_STRB_P_ROR_IMM_OFF_POSTIND
+/* 0110 1110 1111 */ TABDECL(OP_UND),
+
+/* 0110 1111 0000 */ TABDECL(OP_LDRB_P_LSL_IMM_OFF_POSTIND), // OP_LDRB_P_LSL_IMM_OFF_POSTIND
+/* 0110 1111 0001 */ TABDECL(OP_UND),
+/* 0110 1111 0010 */ TABDECL(OP_LDRB_P_LSR_IMM_OFF_POSTIND), // OP_LDRB_P_LSR_IMM_OFF_POSTIND
+/* 0110 1111 0011 */ TABDECL(OP_UND),
+/* 0110 1111 0100 */ TABDECL(OP_LDRB_P_ASR_IMM_OFF_POSTIND), // OP_LDRB_P_ASR_IMM_OFF_POSTIND
+/* 0110 1111 0101 */ TABDECL(OP_UND),
+/* 0110 1111 0110 */ TABDECL(OP_LDRB_P_ROR_IMM_OFF_POSTIND), // OP_LDRB_P_ROR_IMM_OFF_POSTIND
+/* 0110 1111 0111 */ TABDECL(OP_UND),
+/* 0110 1111 1000 */ TABDECL(OP_LDRB_P_LSL_IMM_OFF_POSTIND), // OP_LDRB_P_LSL_IMM_OFF_POSTIND
+/* 0110 1111 1001 */ TABDECL(OP_UND),
+/* 0110 1111 1010 */ TABDECL(OP_LDRB_P_LSR_IMM_OFF_POSTIND), // OP_LDRB_P_LSR_IMM_OFF_POSTIND
+/* 0110 1111 1011 */ TABDECL(OP_UND),
+/* 0110 1111 1100 */ TABDECL(OP_LDRB_P_ASR_IMM_OFF_POSTIND), // OP_LDRB_P_ASR_IMM_OFF_POSTIND
+/* 0110 1111 1101 */ TABDECL(OP_UND),
+/* 0110 1111 1110 */ TABDECL(OP_LDRB_P_ROR_IMM_OFF_POSTIND), // OP_LDRB_P_ROR_IMM_OFF_POSTIND
+/* 0110 1111 1111 */ TABDECL(OP_UND),
+
+/* 0111 0000 0000 */ TABDECL(OP_STR_M_LSL_IMM_OFF), // OP_STR_M_LSL_IMM_OFF
+/* 0111 0000 0001 */ TABDECL(OP_UND),
+/* 0111 0000 0010 */ TABDECL(OP_STR_M_LSR_IMM_OFF), // OP_STR_M_LSR_IMM_OFF
+/* 0111 0000 0011 */ TABDECL(OP_UND),
+/* 0111 0000 0100 */ TABDECL(OP_STR_M_ASR_IMM_OFF), // OP_STR_M_ASR_IMM_OFF
+/* 0111 0000 0101 */ TABDECL(OP_UND),
+/* 0111 0000 0110 */ TABDECL(OP_STR_M_ROR_IMM_OFF), // OP_STR_M_ROR_IMM_OFF
+/* 0111 0000 0111 */ TABDECL(OP_UND),
+/* 0111 0000 1000 */ TABDECL(OP_STR_M_LSL_IMM_OFF), // OP_STR_M_LSL_IMM_OFF
+/* 0111 0000 1001 */ TABDECL(OP_UND),
+/* 0111 0000 1010 */ TABDECL(OP_STR_M_LSR_IMM_OFF), // OP_STR_M_LSR_IMM_OFF
+/* 0111 0000 1011 */ TABDECL(OP_UND),
+/* 0111 0000 1100 */ TABDECL(OP_STR_M_ASR_IMM_OFF), // OP_STR_M_ASR_IMM_OFF
+/* 0111 0000 1101 */ TABDECL(OP_UND),
+/* 0111 0000 1110 */ TABDECL(OP_STR_M_ROR_IMM_OFF), // OP_STR_M_ROR_IMM_OFF
+/* 0111 0000 1111 */ TABDECL(OP_UND),
+
+/* 0111 0001 0000 */ TABDECL(OP_LDR_M_LSL_IMM_OFF), // OP_LDR_M_LSL_IMM_OFF
+/* 0111 0001 0001 */ TABDECL(OP_UND),
+/* 0111 0001 0010 */ TABDECL(OP_LDR_M_LSR_IMM_OFF), // OP_LDR_M_LSR_IMM_OFF
+/* 0111 0001 0011 */ TABDECL(OP_UND),
+/* 0111 0001 0100 */ TABDECL(OP_LDR_M_ASR_IMM_OFF), // OP_LDR_M_ASR_IMM_OFF
+/* 0111 0001 0101 */ TABDECL(OP_UND),
+/* 0111 0001 0110 */ TABDECL(OP_LDR_M_ROR_IMM_OFF), // OP_LDR_M_ROR_IMM_OFF
+/* 0111 0001 0111 */ TABDECL(OP_UND),
+/* 0111 0001 1000 */ TABDECL(OP_LDR_M_LSL_IMM_OFF), // OP_LDR_M_LSL_IMM_OFF
+/* 0111 0001 1001 */ TABDECL(OP_UND),
+/* 0111 0001 1010 */ TABDECL(OP_LDR_M_LSR_IMM_OFF), // OP_LDR_M_LSR_IMM_OFF
+/* 0111 0001 1011 */ TABDECL(OP_UND),
+/* 0111 0001 1100 */ TABDECL(OP_LDR_M_ASR_IMM_OFF), // OP_LDR_M_ASR_IMM_OFF
+/* 0111 0001 1101 */ TABDECL(OP_UND),
+/* 0111 0001 1110 */ TABDECL(OP_LDR_M_ROR_IMM_OFF), // OP_LDR_M_ROR_IMM_OFF
+/* 0111 0001 1111 */ TABDECL(OP_UND),
+
+/* 0111 0010 0000 */ TABDECL(OP_STR_M_LSL_IMM_OFF_PREIND), // OP_STR_M_LSL_IMM_OFF_PREIND
+/* 0111 0010 0001 */ TABDECL(OP_UND),
+/* 0111 0010 0010 */ TABDECL(OP_STR_M_LSR_IMM_OFF_PREIND), // OP_STR_M_LSR_IMM_OFF_PREIND
+/* 0111 0010 0011 */ TABDECL(OP_UND),
+/* 0111 0010 0100 */ TABDECL(OP_STR_M_ASR_IMM_OFF_PREIND), // OP_STR_M_ASR_IMM_OFF_PREIND
+/* 0111 0010 0101 */ TABDECL(OP_UND),
+/* 0111 0010 0110 */ TABDECL(OP_STR_M_ROR_IMM_OFF_PREIND), // OP_STR_M_ROR_IMM_OFF_PREIND
+/* 0111 0010 0111 */ TABDECL(OP_UND),
+/* 0111 0010 1000 */ TABDECL(OP_STR_M_LSL_IMM_OFF_PREIND), // OP_STR_M_LSL_IMM_OFF_PREIND
+/* 0111 0010 1001 */ TABDECL(OP_UND),
+/* 0111 0010 1010 */ TABDECL(OP_STR_M_LSR_IMM_OFF_PREIND), // OP_STR_M_LSR_IMM_OFF_PREIND
+/* 0111 0010 1011 */ TABDECL(OP_UND),
+/* 0111 0010 1100 */ TABDECL(OP_STR_M_ASR_IMM_OFF_PREIND), // OP_STR_M_ASR_IMM_OFF_PREIND
+/* 0111 0010 1101 */ TABDECL(OP_UND),
+/* 0111 0010 1110 */ TABDECL(OP_STR_M_ROR_IMM_OFF_PREIND), // OP_STR_M_ROR_IMM_OFF_PREIND
+/* 0111 0010 1111 */ TABDECL(OP_UND),
+
+/* 0111 0011 0000 */ TABDECL(OP_LDR_M_LSL_IMM_OFF_PREIND), // OP_LDR_M_LSL_IMM_OFF_PREIND
+/* 0111 0011 0001 */ TABDECL(OP_UND),
+/* 0111 0011 0010 */ TABDECL(OP_LDR_M_LSR_IMM_OFF_PREIND), // OP_LDR_M_LSR_IMM_OFF_PREIND
+/* 0111 0011 0011 */ TABDECL(OP_UND),
+/* 0111 0011 0100 */ TABDECL(OP_LDR_M_ASR_IMM_OFF_PREIND), // OP_LDR_M_ASR_IMM_OFF_PREIND
+/* 0111 0011 0101 */ TABDECL(OP_UND),
+/* 0111 0011 0110 */ TABDECL(OP_LDR_M_ROR_IMM_OFF_PREIND), // OP_LDR_M_ROR_IMM_OFF_PREIND
+/* 0111 0011 0111 */ TABDECL(OP_UND),
+/* 0111 0011 1000 */ TABDECL(OP_LDR_M_LSL_IMM_OFF_PREIND), // OP_LDR_M_LSL_IMM_OFF_PREIND
+/* 0111 0011 1001 */ TABDECL(OP_UND),
+/* 0111 0011 1010 */ TABDECL(OP_LDR_M_LSR_IMM_OFF_PREIND), // OP_LDR_M_LSR_IMM_OFF_PREIND
+/* 0111 0011 1011 */ TABDECL(OP_UND),
+/* 0111 0011 1100 */ TABDECL(OP_LDR_M_ASR_IMM_OFF_PREIND), // OP_LDR_M_ASR_IMM_OFF_PREIND
+/* 0111 0011 1101 */ TABDECL(OP_UND),
+/* 0111 0011 1110 */ TABDECL(OP_LDR_M_ROR_IMM_OFF_PREIND), // OP_LDR_M_ROR_IMM_OFF_PREIND
+/* 0111 0011 1111 */ TABDECL(OP_UND),
+
+/* 0111 0100 0000 */ TABDECL(OP_STRB_M_LSL_IMM_OFF), // OP_STRB_M_LSL_IMM_OFF
+/* 0111 0100 0001 */ TABDECL(OP_UND),
+/* 0111 0100 0010 */ TABDECL(OP_STRB_M_LSR_IMM_OFF), // OP_STRB_M_LSR_IMM_OFF
+/* 0111 0100 0011 */ TABDECL(OP_UND),
+/* 0111 0100 0100 */ TABDECL(OP_STRB_M_ASR_IMM_OFF), // OP_STRB_M_ASR_IMM_OFF
+/* 0111 0100 0101 */ TABDECL(OP_UND),
+/* 0111 0100 0110 */ TABDECL(OP_STRB_M_ROR_IMM_OFF), // OP_STRB_M_ROR_IMM_OFF
+/* 0111 0100 0111 */ TABDECL(OP_UND),
+/* 0111 0100 1000 */ TABDECL(OP_STRB_M_LSL_IMM_OFF), // OP_STRB_M_LSL_IMM_OFF
+/* 0111 0100 1001 */ TABDECL(OP_UND),
+/* 0111 0100 1010 */ TABDECL(OP_STRB_M_LSR_IMM_OFF), // OP_STRB_M_LSR_IMM_OFF
+/* 0111 0100 1011 */ TABDECL(OP_UND),
+/* 0111 0100 1100 */ TABDECL(OP_STRB_M_ASR_IMM_OFF), // OP_STRB_M_ASR_IMM_OFF
+/* 0111 0100 1101 */ TABDECL(OP_UND),
+/* 0111 0100 1110 */ TABDECL(OP_STRB_M_ROR_IMM_OFF), // OP_STRB_M_ROR_IMM_OFF
+/* 0111 0100 1111 */ TABDECL(OP_UND),
+
+/* 0111 0101 0000 */ TABDECL(OP_LDRB_M_LSL_IMM_OFF), // OP_LDRB_M_LSL_IMM_OFF
+/* 0111 0101 0001 */ TABDECL(OP_UND),
+/* 0111 0101 0010 */ TABDECL(OP_LDRB_M_LSR_IMM_OFF), // OP_LDRB_M_LSR_IMM_OFF
+/* 0111 0101 0011 */ TABDECL(OP_UND),
+/* 0111 0101 0100 */ TABDECL(OP_LDRB_M_ASR_IMM_OFF), // OP_LDRB_M_ASR_IMM_OFF
+/* 0111 0101 0101 */ TABDECL(OP_UND),
+/* 0111 0101 0110 */ TABDECL(OP_LDRB_M_ROR_IMM_OFF), // OP_LDRB_M_ROR_IMM_OFF
+/* 0111 0101 0111 */ TABDECL(OP_UND),
+/* 0111 0101 1000 */ TABDECL(OP_LDRB_M_LSL_IMM_OFF), // OP_LDRB_M_LSL_IMM_OFF
+/* 0111 0101 1001 */ TABDECL(OP_UND),
+/* 0111 0101 1010 */ TABDECL(OP_LDRB_M_LSR_IMM_OFF), // OP_LDRB_M_LSR_IMM_OFF
+/* 0111 0101 1011 */ TABDECL(OP_UND),
+/* 0111 0101 1100 */ TABDECL(OP_LDRB_M_ASR_IMM_OFF), // OP_LDRB_M_ASR_IMM_OFF
+/* 0111 0101 1101 */ TABDECL(OP_UND),
+/* 0111 0101 1110 */ TABDECL(OP_LDRB_M_ROR_IMM_OFF), // OP_LDRB_M_ROR_IMM_OFF
+/* 0111 0101 1111 */ TABDECL(OP_UND),
+
+/* 0111 0110 0000 */ TABDECL(OP_STRB_M_LSL_IMM_OFF_PREIND), // OP_STRB_M_LSL_IMM_OFF_PREIND
+/* 0111 0110 0001 */ TABDECL(OP_UND),
+/* 0111 0110 0010 */ TABDECL(OP_STRB_M_LSR_IMM_OFF_PREIND), // OP_STRB_M_LSR_IMM_OFF_PREIND
+/* 0111 0110 0011 */ TABDECL(OP_UND),
+/* 0111 0110 0100 */ TABDECL(OP_STRB_M_ASR_IMM_OFF_PREIND), // OP_STRB_M_ASR_IMM_OFF_PREIND
+/* 0111 0110 0101 */ TABDECL(OP_UND),
+/* 0111 0110 0110 */ TABDECL(OP_STRB_M_ROR_IMM_OFF_PREIND), // OP_STRB_M_ROR_IMM_OFF_PREIND
+/* 0111 0110 0111 */ TABDECL(OP_UND),
+/* 0111 0110 1000 */ TABDECL(OP_STRB_M_LSL_IMM_OFF_PREIND), // OP_STRB_M_LSL_IMM_OFF_PREIND
+/* 0111 0110 1001 */ TABDECL(OP_UND),
+/* 0111 0110 1010 */ TABDECL(OP_STRB_M_LSR_IMM_OFF_PREIND), // OP_STRB_M_LSR_IMM_OFF_PREIND
+/* 0111 0110 1011 */ TABDECL(OP_UND),
+/* 0111 0110 1100 */ TABDECL(OP_STRB_M_ASR_IMM_OFF_PREIND), // OP_STRB_M_ASR_IMM_OFF_PREIND
+/* 0111 0110 1101 */ TABDECL(OP_UND),
+/* 0111 0110 1110 */ TABDECL(OP_STRB_M_ROR_IMM_OFF_PREIND), // OP_STRB_M_ROR_IMM_OFF_PREIND
+/* 0111 0110 1111 */ TABDECL(OP_UND),
+
+/* 0111 0111 0000 */ TABDECL(OP_LDRB_M_LSL_IMM_OFF_PREIND), // OP_LDRB_M_LSL_IMM_OFF_PREIND
+/* 0111 0111 0001 */ TABDECL(OP_UND),
+/* 0111 0111 0010 */ TABDECL(OP_LDRB_M_LSR_IMM_OFF_PREIND), // OP_LDRB_M_LSR_IMM_OFF_PREIND
+/* 0111 0111 0011 */ TABDECL(OP_UND),
+/* 0111 0111 0100 */ TABDECL(OP_LDRB_M_ASR_IMM_OFF_PREIND), // OP_LDRB_M_ASR_IMM_OFF_PREIND
+/* 0111 0111 0101 */ TABDECL(OP_UND),
+/* 0111 0111 0110 */ TABDECL(OP_LDRB_M_ROR_IMM_OFF_PREIND), // OP_LDRB_M_ROR_IMM_OFF_PREIND
+/* 0111 0111 0111 */ TABDECL(OP_UND),
+/* 0111 0111 1000 */ TABDECL(OP_LDRB_M_LSL_IMM_OFF_PREIND), // OP_LDRB_M_LSL_IMM_OFF_PREIND
+/* 0111 0111 1001 */ TABDECL(OP_UND),
+/* 0111 0111 1010 */ TABDECL(OP_LDRB_M_LSR_IMM_OFF_PREIND), // OP_LDRB_M_LSR_IMM_OFF_PREIND
+/* 0111 0111 1011 */ TABDECL(OP_UND),
+/* 0111 0111 1100 */ TABDECL(OP_LDRB_M_ASR_IMM_OFF_PREIND), // OP_LDRB_M_ASR_IMM_OFF_PREIND
+/* 0111 0111 1101 */ TABDECL(OP_UND),
+/* 0111 0111 1110 */ TABDECL(OP_LDRB_M_ROR_IMM_OFF_PREIND), // OP_LDRB_M_ROR_IMM_OFF_PREIND
+/* 0111 0111 1111 */ TABDECL(OP_UND),
+
+/* 0111 1000 0000 */ TABDECL(OP_STR_P_LSL_IMM_OFF), // OP_STR_P_LSL_IMM_OFF
+/* 0111 1000 0001 */ TABDECL(OP_UND),
+/* 0111 1000 0010 */ TABDECL(OP_STR_P_LSR_IMM_OFF), // OP_STR_P_LSR_IMM_OFF
+/* 0111 1000 0011 */ TABDECL(OP_UND),
+/* 0111 1000 0100 */ TABDECL(OP_STR_P_ASR_IMM_OFF), // OP_STR_P_ASR_IMM_OFF
+/* 0111 1000 0101 */ TABDECL(OP_UND),
+/* 0111 1000 0110 */ TABDECL(OP_STR_P_ROR_IMM_OFF), // OP_STR_P_ROR_IMM_OFF
+/* 0111 1000 0111 */ TABDECL(OP_UND),
+/* 0111 1000 1000 */ TABDECL(OP_STR_P_LSL_IMM_OFF), // OP_STR_P_LSL_IMM_OFF
+/* 0111 1000 1001 */ TABDECL(OP_UND),
+/* 0111 1000 1010 */ TABDECL(OP_STR_P_LSR_IMM_OFF), // OP_STR_P_LSR_IMM_OFF
+/* 0111 1000 1011 */ TABDECL(OP_UND),
+/* 0111 1000 1100 */ TABDECL(OP_STR_P_ASR_IMM_OFF), // OP_STR_P_ASR_IMM_OFF
+/* 0111 1000 1101 */ TABDECL(OP_UND),
+/* 0111 1000 1110 */ TABDECL(OP_STR_P_ROR_IMM_OFF), // OP_STR_P_ROR_IMM_OFF
+/* 0111 1000 1111 */ TABDECL(OP_UND),
+
+/* 0111 1001 0000 */ TABDECL(OP_LDR_P_LSL_IMM_OFF), // OP_LDR_P_LSL_IMM_OFF
+/* 0111 1001 0001 */ TABDECL(OP_UND),
+/* 0111 1001 0010 */ TABDECL(OP_LDR_P_LSR_IMM_OFF), // OP_LDR_P_LSR_IMM_OFF
+/* 0111 1001 0011 */ TABDECL(OP_UND),
+/* 0111 1001 0100 */ TABDECL(OP_LDR_P_ASR_IMM_OFF), // OP_LDR_P_ASR_IMM_OFF
+/* 0111 1001 0101 */ TABDECL(OP_UND),
+/* 0111 1001 0110 */ TABDECL(OP_LDR_P_ROR_IMM_OFF), // OP_LDR_P_ROR_IMM_OFF
+/* 0111 1001 0111 */ TABDECL(OP_UND),
+/* 0111 1001 1000 */ TABDECL(OP_LDR_P_LSL_IMM_OFF), // OP_LDR_P_LSL_IMM_OFF
+/* 0111 1001 1001 */ TABDECL(OP_UND),
+/* 0111 1001 1010 */ TABDECL(OP_LDR_P_LSR_IMM_OFF), // OP_LDR_P_LSR_IMM_OFF
+/* 0111 1001 1011 */ TABDECL(OP_UND),
+/* 0111 1001 1100 */ TABDECL(OP_LDR_P_ASR_IMM_OFF), // OP_LDR_P_ASR_IMM_OFF
+/* 0111 1001 1101 */ TABDECL(OP_UND),
+/* 0111 1001 1110 */ TABDECL(OP_LDR_P_ROR_IMM_OFF), // OP_LDR_P_ROR_IMM_OFF
+/* 0111 1001 1111 */ TABDECL(OP_UND),
+
+/* 0111 1010 0000 */ TABDECL(OP_STR_P_LSL_IMM_OFF_PREIND), // OP_STR_P_LSL_IMM_OFF_PREIND
+/* 0111 1010 0001 */ TABDECL(OP_UND),
+/* 0111 1010 0010 */ TABDECL(OP_STR_P_LSR_IMM_OFF_PREIND), // OP_STR_P_LSR_IMM_OFF_PREIND
+/* 0111 1010 0011 */ TABDECL(OP_UND),
+/* 0111 1010 0100 */ TABDECL(OP_STR_P_ASR_IMM_OFF_PREIND), // OP_STR_P_ASR_IMM_OFF_PREIND
+/* 0111 1010 0101 */ TABDECL(OP_UND),
+/* 0111 1010 0110 */ TABDECL(OP_STR_P_ROR_IMM_OFF_PREIND), // OP_STR_P_ROR_IMM_OFF_PREIND
+/* 0111 1010 0111 */ TABDECL(OP_UND),
+/* 0111 1010 1000 */ TABDECL(OP_STR_P_LSL_IMM_OFF_PREIND), // OP_STR_P_LSL_IMM_OFF_PREIND
+/* 0111 1010 1001 */ TABDECL(OP_UND),
+/* 0111 1010 1010 */ TABDECL(OP_STR_P_LSR_IMM_OFF_PREIND), // OP_STR_P_LSR_IMM_OFF_PREIND
+/* 0111 1010 1011 */ TABDECL(OP_UND),
+/* 0111 1010 1100 */ TABDECL(OP_STR_P_ASR_IMM_OFF_PREIND), // OP_STR_P_ASR_IMM_OFF_PREIND
+/* 0111 1010 1101 */ TABDECL(OP_UND),
+/* 0111 1010 1110 */ TABDECL(OP_STR_P_ROR_IMM_OFF_PREIND), // OP_STR_P_ROR_IMM_OFF_PREIND
+/* 0111 1010 1111 */ TABDECL(OP_UND),
+
+/* 0111 1011 0000 */ TABDECL(OP_LDR_P_LSL_IMM_OFF_PREIND), // OP_LDR_P_LSL_IMM_OFF_PREIND
+/* 0111 1011 0001 */ TABDECL(OP_UND),
+/* 0111 1011 0010 */ TABDECL(OP_LDR_P_LSR_IMM_OFF_PREIND), // OP_LDR_P_LSR_IMM_OFF_PREIND
+/* 0111 1011 0011 */ TABDECL(OP_UND),
+/* 0111 1011 0100 */ TABDECL(OP_LDR_P_ASR_IMM_OFF_PREIND), // OP_LDR_P_ASR_IMM_OFF_PREIND
+/* 0111 1011 0101 */ TABDECL(OP_UND),
+/* 0111 1011 0110 */ TABDECL(OP_LDR_P_ROR_IMM_OFF_PREIND), // OP_LDR_P_ROR_IMM_OFF_PREIND
+/* 0111 1011 0111 */ TABDECL(OP_UND),
+/* 0111 1011 1000 */ TABDECL(OP_LDR_P_LSL_IMM_OFF_PREIND), // OP_LDR_P_LSL_IMM_OFF_PREIND
+/* 0111 1011 1001 */ TABDECL(OP_UND),
+/* 0111 1011 1010 */ TABDECL(OP_LDR_P_LSR_IMM_OFF_PREIND), // OP_LDR_P_LSR_IMM_OFF_PREIND
+/* 0111 1011 1011 */ TABDECL(OP_UND),
+/* 0111 1011 1100 */ TABDECL(OP_LDR_P_ASR_IMM_OFF_PREIND), // OP_LDR_P_ASR_IMM_OFF_PREIND
+/* 0111 1011 1101 */ TABDECL(OP_UND),
+/* 0111 1011 1110 */ TABDECL(OP_LDR_P_ROR_IMM_OFF_PREIND), // OP_LDR_P_ROR_IMM_OFF_PREIND
+/* 0111 1011 1111 */ TABDECL(OP_UND),
+
+/* 0111 1100 0000 */ TABDECL(OP_STRB_P_LSL_IMM_OFF), // OP_STRB_P_LSL_IMM_OFF
+/* 0111 1100 0001 */ TABDECL(OP_UND),
+/* 0111 1100 0010 */ TABDECL(OP_STRB_P_LSR_IMM_OFF), // OP_STRB_P_LSR_IMM_OFF
+/* 0111 1100 0011 */ TABDECL(OP_UND),
+/* 0111 1100 0100 */ TABDECL(OP_STRB_P_ASR_IMM_OFF), // OP_STRB_P_ASR_IMM_OFF
+/* 0111 1100 0101 */ TABDECL(OP_UND),
+/* 0111 1100 0110 */ TABDECL(OP_STRB_P_ROR_IMM_OFF), // OP_STRB_P_ROR_IMM_OFF
+/* 0111 1100 0111 */ TABDECL(OP_UND),
+/* 0111 1100 1000 */ TABDECL(OP_STRB_P_LSL_IMM_OFF), // OP_STRB_P_LSL_IMM_OFF
+/* 0111 1100 1001 */ TABDECL(OP_UND),
+/* 0111 1100 1010 */ TABDECL(OP_STRB_P_LSR_IMM_OFF), // OP_STRB_P_LSR_IMM_OFF
+/* 0111 1100 1011 */ TABDECL(OP_UND),
+/* 0111 1100 1100 */ TABDECL(OP_STRB_P_ASR_IMM_OFF), // OP_STRB_P_ASR_IMM_OFF
+/* 0111 1100 1101 */ TABDECL(OP_UND),
+/* 0111 1100 1110 */ TABDECL(OP_STRB_P_ROR_IMM_OFF), // OP_STRB_P_ROR_IMM_OFF
+/* 0111 1100 1111 */ TABDECL(OP_UND),
+
+/* 0111 1101 0000 */ TABDECL(OP_LDRB_P_LSL_IMM_OFF), // OP_LDRB_P_LSL_IMM_OFF
+/* 0111 1101 0001 */ TABDECL(OP_UND),
+/* 0111 1101 0010 */ TABDECL(OP_LDRB_P_LSR_IMM_OFF), // OP_LDRB_P_LSR_IMM_OFF
+/* 0111 1101 0011 */ TABDECL(OP_UND),
+/* 0111 1101 0100 */ TABDECL(OP_LDRB_P_ASR_IMM_OFF), // OP_LDRB_P_ASR_IMM_OFF
+/* 0111 1101 0101 */ TABDECL(OP_UND),
+/* 0111 1101 0110 */ TABDECL(OP_LDRB_P_ROR_IMM_OFF), // OP_LDRB_P_ROR_IMM_OFF
+/* 0111 1101 0111 */ TABDECL(OP_UND),
+/* 0111 1101 1000 */ TABDECL(OP_LDRB_P_LSL_IMM_OFF), // OP_LDRB_P_LSL_IMM_OFF
+/* 0111 1101 1001 */ TABDECL(OP_UND),
+/* 0111 1101 1010 */ TABDECL(OP_LDRB_P_LSR_IMM_OFF), // OP_LDRB_P_LSR_IMM_OFF
+/* 0111 1101 1011 */ TABDECL(OP_UND),
+/* 0111 1101 1100 */ TABDECL(OP_LDRB_P_ASR_IMM_OFF), // OP_LDRB_P_ASR_IMM_OFF
+/* 0111 1101 1101 */ TABDECL(OP_UND),
+/* 0111 1101 1110 */ TABDECL(OP_LDRB_P_ROR_IMM_OFF), // OP_LDRB_P_ROR_IMM_OFF
+/* 0111 1101 1111 */ TABDECL(OP_UND),
+
+/* 0111 1110 0000 */ TABDECL(OP_STRB_P_LSL_IMM_OFF_PREIND), // OP_STRB_P_LSL_IMM_OFF_PREIND
+/* 0111 1110 0001 */ TABDECL(OP_UND),
+/* 0111 1110 0010 */ TABDECL(OP_STRB_P_LSR_IMM_OFF_PREIND), // OP_STRB_P_LSR_IMM_OFF_PREIND
+/* 0111 1110 0011 */ TABDECL(OP_UND),
+/* 0111 1110 0100 */ TABDECL(OP_STRB_P_ASR_IMM_OFF_PREIND), // OP_STRB_P_ASR_IMM_OFF_PREIND
+/* 0111 1110 0101 */ TABDECL(OP_UND),
+/* 0111 1110 0110 */ TABDECL(OP_STRB_P_ROR_IMM_OFF_PREIND), // OP_STRB_P_ROR_IMM_OFF_PREIND
+/* 0111 1110 0111 */ TABDECL(OP_UND),
+/* 0111 1110 1000 */ TABDECL(OP_STRB_P_LSL_IMM_OFF_PREIND), // OP_STRB_P_LSL_IMM_OFF_PREIND
+/* 0111 1110 1001 */ TABDECL(OP_UND),
+/* 0111 1110 1010 */ TABDECL(OP_STRB_P_LSR_IMM_OFF_PREIND), // OP_STRB_P_LSR_IMM_OFF_PREIND
+/* 0111 1110 1011 */ TABDECL(OP_UND),
+/* 0111 1110 1100 */ TABDECL(OP_STRB_P_ASR_IMM_OFF_PREIND), // OP_STRB_P_ASR_IMM_OFF_PREIND
+/* 0111 1110 1101 */ TABDECL(OP_UND),
+/* 0111 1110 1110 */ TABDECL(OP_STRB_P_ROR_IMM_OFF_PREIND), // OP_STRB_P_ROR_IMM_OFF_PREIND
+/* 0111 1110 1111 */ TABDECL(OP_UND),
+
+/* 0111 1111 0000 */ TABDECL(OP_LDRB_P_LSL_IMM_OFF_PREIND), // OP_LDRB_P_LSL_IMM_OFF_PREIND
+/* 0111 1111 0001 */ TABDECL(OP_UND),
+/* 0111 1111 0010 */ TABDECL(OP_LDRB_P_LSR_IMM_OFF_PREIND), // OP_LDRB_P_LSR_IMM_OFF_PREIND
+/* 0111 1111 0011 */ TABDECL(OP_UND),
+/* 0111 1111 0100 */ TABDECL(OP_LDRB_P_ASR_IMM_OFF_PREIND), // OP_LDRB_P_ASR_IMM_OFF_PREIND
+/* 0111 1111 0101 */ TABDECL(OP_UND),
+/* 0111 1111 0110 */ TABDECL(OP_LDRB_P_ROR_IMM_OFF_PREIND), // OP_LDRB_P_ROR_IMM_OFF_PREIND
+/* 0111 1111 0111 */ TABDECL(OP_UND),
+/* 0111 1111 1000 */ TABDECL(OP_LDRB_P_LSL_IMM_OFF_PREIND), // OP_LDRB_P_LSL_IMM_OFF_PREIND
+/* 0111 1111 1001 */ TABDECL(OP_UND),
+/* 0111 1111 1010 */ TABDECL(OP_LDRB_P_LSR_IMM_OFF_PREIND), // OP_LDRB_P_LSR_IMM_OFF_PREIND
+/* 0111 1111 1011 */ TABDECL(OP_UND),
+/* 0111 1111 1100 */ TABDECL(OP_LDRB_P_ASR_IMM_OFF_PREIND), // OP_LDRB_P_ASR_IMM_OFF_PREIND
+/* 0111 1111 1101 */ TABDECL(OP_UND),
+/* 0111 1111 1110 */ TABDECL(OP_LDRB_P_ROR_IMM_OFF_PREIND), // OP_LDRB_P_ROR_IMM_OFF_PREIND
+/* 0111 1111 1111 */ TABDECL(OP_UND),
+
+/* 1000 0000 0000 */ TABDECL(OP_STMDA), // OP_STMDA
+/* 1000 0000 0001 */ TABDECL(OP_STMDA), // OP_STMDA
+/* 1000 0000 0010 */ TABDECL(OP_STMDA), // OP_STMDA
+/* 1000 0000 0011 */ TABDECL(OP_STMDA), // OP_STMDA
+/* 1000 0000 0100 */ TABDECL(OP_STMDA), // OP_STMDA
+/* 1000 0000 0101 */ TABDECL(OP_STMDA), // OP_STMDA
+/* 1000 0000 0110 */ TABDECL(OP_STMDA), // OP_STMDA
+/* 1000 0000 0111 */ TABDECL(OP_STMDA), // OP_STMDA
+/* 1000 0000 1000 */ TABDECL(OP_STMDA), // OP_STMDA
+/* 1000 0000 1001 */ TABDECL(OP_STMDA), // OP_STMDA
+/* 1000 0000 1010 */ TABDECL(OP_STMDA), // OP_STMDA
+/* 1000 0000 1011 */ TABDECL(OP_STMDA), // OP_STMDA
+/* 1000 0000 1100 */ TABDECL(OP_STMDA), // OP_STMDA
+/* 1000 0000 1101 */ TABDECL(OP_STMDA), // OP_STMDA
+/* 1000 0000 1110 */ TABDECL(OP_STMDA), // OP_STMDA
+/* 1000 0000 1111 */ TABDECL(OP_STMDA), // OP_STMDA
+
+/* 1000 0001 0000 */ TABDECL(OP_LDMDA), // OP_LDMDA
+/* 1000 0001 0001 */ TABDECL(OP_LDMDA), // OP_LDMDA
+/* 1000 0001 0010 */ TABDECL(OP_LDMDA), // OP_LDMDA
+/* 1000 0001 0011 */ TABDECL(OP_LDMDA), // OP_LDMDA
+/* 1000 0001 0100 */ TABDECL(OP_LDMDA), // OP_LDMDA
+/* 1000 0001 0101 */ TABDECL(OP_LDMDA), // OP_LDMDA
+/* 1000 0001 0110 */ TABDECL(OP_LDMDA), // OP_LDMDA
+/* 1000 0001 0111 */ TABDECL(OP_LDMDA), // OP_LDMDA
+/* 1000 0001 1000 */ TABDECL(OP_LDMDA), // OP_LDMDA
+/* 1000 0001 1001 */ TABDECL(OP_LDMDA), // OP_LDMDA
+/* 1000 0001 1010 */ TABDECL(OP_LDMDA), // OP_LDMDA
+/* 1000 0001 1011 */ TABDECL(OP_LDMDA), // OP_LDMDA
+/* 1000 0001 1100 */ TABDECL(OP_LDMDA), // OP_LDMDA
+/* 1000 0001 1101 */ TABDECL(OP_LDMDA), // OP_LDMDA
+/* 1000 0001 1110 */ TABDECL(OP_LDMDA), // OP_LDMDA
+/* 1000 0001 1111 */ TABDECL(OP_LDMDA), // OP_LDMDA
+
+/* 1000 0010 0000 */ TABDECL(OP_STMDA_W), // OP_STMDA_W
+/* 1000 0010 0001 */ TABDECL(OP_STMDA_W), // OP_STMDA_W
+/* 1000 0010 0010 */ TABDECL(OP_STMDA_W), // OP_STMDA_W
+/* 1000 0010 0011 */ TABDECL(OP_STMDA_W), // OP_STMDA_W
+/* 1000 0010 0100 */ TABDECL(OP_STMDA_W), // OP_STMDA_W
+/* 1000 0010 0101 */ TABDECL(OP_STMDA_W), // OP_STMDA_W
+/* 1000 0010 0110 */ TABDECL(OP_STMDA_W), // OP_STMDA_W
+/* 1000 0010 0111 */ TABDECL(OP_STMDA_W), // OP_STMDA_W
+/* 1000 0010 1000 */ TABDECL(OP_STMDA_W), // OP_STMDA_W
+/* 1000 0010 1001 */ TABDECL(OP_STMDA_W), // OP_STMDA_W
+/* 1000 0010 1010 */ TABDECL(OP_STMDA_W), // OP_STMDA_W
+/* 1000 0010 1011 */ TABDECL(OP_STMDA_W), // OP_STMDA_W
+/* 1000 0010 1100 */ TABDECL(OP_STMDA_W), // OP_STMDA_W
+/* 1000 0010 1101 */ TABDECL(OP_STMDA_W), // OP_STMDA_W
+/* 1000 0010 1110 */ TABDECL(OP_STMDA_W), // OP_STMDA_W
+/* 1000 0010 1111 */ TABDECL(OP_STMDA_W), // OP_STMDA_W
+
+/* 1000 0011 0000 */ TABDECL(OP_LDMDA_W), // OP_LDMDA_W
+/* 1000 0011 0001 */ TABDECL(OP_LDMDA_W), // OP_LDMDA_W
+/* 1000 0011 0010 */ TABDECL(OP_LDMDA_W), // OP_LDMDA_W
+/* 1000 0011 0011 */ TABDECL(OP_LDMDA_W), // OP_LDMDA_W
+/* 1000 0011 0100 */ TABDECL(OP_LDMDA_W), // OP_LDMDA_W
+/* 1000 0011 0101 */ TABDECL(OP_LDMDA_W), // OP_LDMDA_W
+/* 1000 0011 0110 */ TABDECL(OP_LDMDA_W), // OP_LDMDA_W
+/* 1000 0011 0111 */ TABDECL(OP_LDMDA_W), // OP_LDMDA_W
+/* 1000 0011 1000 */ TABDECL(OP_LDMDA_W), // OP_LDMDA_W
+/* 1000 0011 1001 */ TABDECL(OP_LDMDA_W), // OP_LDMDA_W
+/* 1000 0011 1010 */ TABDECL(OP_LDMDA_W), // OP_LDMDA_W
+/* 1000 0011 1011 */ TABDECL(OP_LDMDA_W), // OP_LDMDA_W
+/* 1000 0011 1100 */ TABDECL(OP_LDMDA_W), // OP_LDMDA_W
+/* 1000 0011 1101 */ TABDECL(OP_LDMDA_W), // OP_LDMDA_W
+/* 1000 0011 1110 */ TABDECL(OP_LDMDA_W), // OP_LDMDA_W
+/* 1000 0011 1111 */ TABDECL(OP_LDMDA_W), // OP_LDMDA_W
+
+/* 1000 0100 0000 */ TABDECL(OP_STMDA2), // OP_STMDA2
+/* 1000 0100 0001 */ TABDECL(OP_STMDA2), // OP_STMDA2
+/* 1000 0100 0010 */ TABDECL(OP_STMDA2), // OP_STMDA2
+/* 1000 0100 0011 */ TABDECL(OP_STMDA2), // OP_STMDA2
+/* 1000 0100 0100 */ TABDECL(OP_STMDA2), // OP_STMDA2
+/* 1000 0100 0101 */ TABDECL(OP_STMDA2), // OP_STMDA2
+/* 1000 0100 0110 */ TABDECL(OP_STMDA2), // OP_STMDA2
+/* 1000 0100 0111 */ TABDECL(OP_STMDA2), // OP_STMDA2
+/* 1000 0100 1000 */ TABDECL(OP_STMDA2), // OP_STMDA2
+/* 1000 0100 1001 */ TABDECL(OP_STMDA2), // OP_STMDA2
+/* 1000 0100 1010 */ TABDECL(OP_STMDA2), // OP_STMDA2
+/* 1000 0100 1011 */ TABDECL(OP_STMDA2), // OP_STMDA2
+/* 1000 0100 1100 */ TABDECL(OP_STMDA2), // OP_STMDA2
+/* 1000 0100 1101 */ TABDECL(OP_STMDA2), // OP_STMDA2
+/* 1000 0100 1110 */ TABDECL(OP_STMDA2), // OP_STMDA2
+/* 1000 0100 1111 */ TABDECL(OP_STMDA2), // OP_STMDA2
+
+/* 1000 0101 0000 */ TABDECL(OP_LDMDA2), // OP_LDMDA2
+/* 1000 0101 0001 */ TABDECL(OP_LDMDA2), // OP_LDMDA2
+/* 1000 0101 0010 */ TABDECL(OP_LDMDA2), // OP_LDMDA2
+/* 1000 0101 0011 */ TABDECL(OP_LDMDA2), // OP_LDMDA2
+/* 1000 0101 0100 */ TABDECL(OP_LDMDA2), // OP_LDMDA2
+/* 1000 0101 0101 */ TABDECL(OP_LDMDA2), // OP_LDMDA2
+/* 1000 0101 0110 */ TABDECL(OP_LDMDA2), // OP_LDMDA2
+/* 1000 0101 0111 */ TABDECL(OP_LDMDA2), // OP_LDMDA2
+/* 1000 0101 1000 */ TABDECL(OP_LDMDA2), // OP_LDMDA2
+/* 1000 0101 1001 */ TABDECL(OP_LDMDA2), // OP_LDMDA2
+/* 1000 0101 1010 */ TABDECL(OP_LDMDA2), // OP_LDMDA2
+/* 1000 0101 1011 */ TABDECL(OP_LDMDA2), // OP_LDMDA2
+/* 1000 0101 1100 */ TABDECL(OP_LDMDA2), // OP_LDMDA2
+/* 1000 0101 1101 */ TABDECL(OP_LDMDA2), // OP_LDMDA2
+/* 1000 0101 1110 */ TABDECL(OP_LDMDA2), // OP_LDMDA2
+/* 1000 0101 1111 */ TABDECL(OP_LDMDA2), // OP_LDMDA2
+
+/* 1000 0110 0000 */ TABDECL(OP_STMDA2_W), // OP_STMDA2_W
+/* 1000 0110 0001 */ TABDECL(OP_STMDA2_W), // OP_STMDA2_W
+/* 1000 0110 0010 */ TABDECL(OP_STMDA2_W), // OP_STMDA2_W
+/* 1000 0110 0011 */ TABDECL(OP_STMDA2_W), // OP_STMDA2_W
+/* 1000 0110 0100 */ TABDECL(OP_STMDA2_W), // OP_STMDA2_W
+/* 1000 0110 0101 */ TABDECL(OP_STMDA2_W), // OP_STMDA2_W
+/* 1000 0110 0110 */ TABDECL(OP_STMDA2_W), // OP_STMDA2_W
+/* 1000 0110 0111 */ TABDECL(OP_STMDA2_W), // OP_STMDA2_W
+/* 1000 0110 1000 */ TABDECL(OP_STMDA2_W), // OP_STMDA2_W
+/* 1000 0110 1001 */ TABDECL(OP_STMDA2_W), // OP_STMDA2_W
+/* 1000 0110 1010 */ TABDECL(OP_STMDA2_W), // OP_STMDA2_W
+/* 1000 0110 1011 */ TABDECL(OP_STMDA2_W), // OP_STMDA2_W
+/* 1000 0110 1100 */ TABDECL(OP_STMDA2_W), // OP_STMDA2_W
+/* 1000 0110 1101 */ TABDECL(OP_STMDA2_W), // OP_STMDA2_W
+/* 1000 0110 1110 */ TABDECL(OP_STMDA2_W), // OP_STMDA2_W
+/* 1000 0110 1111 */ TABDECL(OP_STMDA2_W), // OP_STMDA2_W
+
+/* 1000 0111 0000 */ TABDECL(OP_LDMDA2_W), // OP_LDMDA2_W
+/* 1000 0111 0001 */ TABDECL(OP_LDMDA2_W), // OP_LDMDA2_W
+/* 1000 0111 0010 */ TABDECL(OP_LDMDA2_W), // OP_LDMDA2_W
+/* 1000 0111 0011 */ TABDECL(OP_LDMDA2_W), // OP_LDMDA2_W
+/* 1000 0111 0100 */ TABDECL(OP_LDMDA2_W), // OP_LDMDA2_W
+/* 1000 0111 0101 */ TABDECL(OP_LDMDA2_W), // OP_LDMDA2_W
+/* 1000 0111 0110 */ TABDECL(OP_LDMDA2_W), // OP_LDMDA2_W
+/* 1000 0111 0111 */ TABDECL(OP_LDMDA2_W), // OP_LDMDA2_W
+/* 1000 0111 1000 */ TABDECL(OP_LDMDA2_W), // OP_LDMDA2_W
+/* 1000 0111 1001 */ TABDECL(OP_LDMDA2_W), // OP_LDMDA2_W
+/* 1000 0111 1010 */ TABDECL(OP_LDMDA2_W), // OP_LDMDA2_W
+/* 1000 0111 1011 */ TABDECL(OP_LDMDA2_W), // OP_LDMDA2_W
+/* 1000 0111 1100 */ TABDECL(OP_LDMDA2_W), // OP_LDMDA2_W
+/* 1000 0111 1101 */ TABDECL(OP_LDMDA2_W), // OP_LDMDA2_W
+/* 1000 0111 1110 */ TABDECL(OP_LDMDA2_W), // OP_LDMDA2_W
+/* 1000 0111 1111 */ TABDECL(OP_LDMDA2_W), // OP_LDMDA2_W
+
+/* 1000 1000 0000 */ TABDECL(OP_STMIA), // OP_STMIA
+/* 1000 1000 0001 */ TABDECL(OP_STMIA), // OP_STMIA
+/* 1000 1000 0010 */ TABDECL(OP_STMIA), // OP_STMIA
+/* 1000 1000 0011 */ TABDECL(OP_STMIA), // OP_STMIA
+/* 1000 1000 0100 */ TABDECL(OP_STMIA), // OP_STMIA
+/* 1000 1000 0101 */ TABDECL(OP_STMIA), // OP_STMIA
+/* 1000 1000 0110 */ TABDECL(OP_STMIA), // OP_STMIA
+/* 1000 1000 0111 */ TABDECL(OP_STMIA), // OP_STMIA
+/* 1000 1000 1000 */ TABDECL(OP_STMIA), // OP_STMIA
+/* 1000 1000 1001 */ TABDECL(OP_STMIA), // OP_STMIA
+/* 1000 1000 1010 */ TABDECL(OP_STMIA), // OP_STMIA
+/* 1000 1000 1011 */ TABDECL(OP_STMIA), // OP_STMIA
+/* 1000 1000 1100 */ TABDECL(OP_STMIA), // OP_STMIA
+/* 1000 1000 1101 */ TABDECL(OP_STMIA), // OP_STMIA
+/* 1000 1000 1110 */ TABDECL(OP_STMIA), // OP_STMIA
+/* 1000 1000 1111 */ TABDECL(OP_STMIA), // OP_STMIA
+
+/* 1000 1001 0000 */ TABDECL(OP_LDMIA), // OP_LDMIA
+/* 1000 1001 0001 */ TABDECL(OP_LDMIA), // OP_LDMIA
+/* 1000 1001 0010 */ TABDECL(OP_LDMIA), // OP_LDMIA
+/* 1000 1001 0011 */ TABDECL(OP_LDMIA), // OP_LDMIA
+/* 1000 1001 0100 */ TABDECL(OP_LDMIA), // OP_LDMIA
+/* 1000 1001 0101 */ TABDECL(OP_LDMIA), // OP_LDMIA
+/* 1000 1001 0110 */ TABDECL(OP_LDMIA), // OP_LDMIA
+/* 1000 1001 0111 */ TABDECL(OP_LDMIA), // OP_LDMIA
+/* 1000 1001 1000 */ TABDECL(OP_LDMIA), // OP_LDMIA
+/* 1000 1001 1001 */ TABDECL(OP_LDMIA), // OP_LDMIA
+/* 1000 1001 1010 */ TABDECL(OP_LDMIA), // OP_LDMIA
+/* 1000 1001 1011 */ TABDECL(OP_LDMIA), // OP_LDMIA
+/* 1000 1001 1100 */ TABDECL(OP_LDMIA), // OP_LDMIA
+/* 1000 1001 1101 */ TABDECL(OP_LDMIA), // OP_LDMIA
+/* 1000 1001 1110 */ TABDECL(OP_LDMIA), // OP_LDMIA
+/* 1000 1001 1111 */ TABDECL(OP_LDMIA), // OP_LDMIA
+
+/* 1000 1010 0000 */ TABDECL(OP_STMIA_W), // OP_STMIA_W
+/* 1000 1010 0001 */ TABDECL(OP_STMIA_W), // OP_STMIA_W
+/* 1000 1010 0010 */ TABDECL(OP_STMIA_W), // OP_STMIA_W
+/* 1000 1010 0011 */ TABDECL(OP_STMIA_W), // OP_STMIA_W
+/* 1000 1010 0100 */ TABDECL(OP_STMIA_W), // OP_STMIA_W
+/* 1000 1010 0101 */ TABDECL(OP_STMIA_W), // OP_STMIA_W
+/* 1000 1010 0110 */ TABDECL(OP_STMIA_W), // OP_STMIA_W
+/* 1000 1010 0111 */ TABDECL(OP_STMIA_W), // OP_STMIA_W
+/* 1000 1010 1000 */ TABDECL(OP_STMIA_W), // OP_STMIA_W
+/* 1000 1010 1001 */ TABDECL(OP_STMIA_W), // OP_STMIA_W
+/* 1000 1010 1010 */ TABDECL(OP_STMIA_W), // OP_STMIA_W
+/* 1000 1010 1011 */ TABDECL(OP_STMIA_W), // OP_STMIA_W
+/* 1000 1010 1100 */ TABDECL(OP_STMIA_W), // OP_STMIA_W
+/* 1000 1010 1101 */ TABDECL(OP_STMIA_W), // OP_STMIA_W
+/* 1000 1010 1110 */ TABDECL(OP_STMIA_W), // OP_STMIA_W
+/* 1000 1010 1111 */ TABDECL(OP_STMIA_W), // OP_STMIA_W
+
+/* 1000 1011 0000 */ TABDECL(OP_LDMIA_W), // OP_LDMIA_W
+/* 1000 1011 0001 */ TABDECL(OP_LDMIA_W), // OP_LDMIA_W
+/* 1000 1011 0010 */ TABDECL(OP_LDMIA_W), // OP_LDMIA_W
+/* 1000 1011 0011 */ TABDECL(OP_LDMIA_W), // OP_LDMIA_W
+/* 1000 1011 0100 */ TABDECL(OP_LDMIA_W), // OP_LDMIA_W
+/* 1000 1011 0101 */ TABDECL(OP_LDMIA_W), // OP_LDMIA_W
+/* 1000 1011 0110 */ TABDECL(OP_LDMIA_W), // OP_LDMIA_W
+/* 1000 1011 0111 */ TABDECL(OP_LDMIA_W), // OP_LDMIA_W
+/* 1000 1011 1000 */ TABDECL(OP_LDMIA_W), // OP_LDMIA_W
+/* 1000 1011 1001 */ TABDECL(OP_LDMIA_W), // OP_LDMIA_W
+/* 1000 1011 1010 */ TABDECL(OP_LDMIA_W), // OP_LDMIA_W
+/* 1000 1011 1011 */ TABDECL(OP_LDMIA_W), // OP_LDMIA_W
+/* 1000 1011 1100 */ TABDECL(OP_LDMIA_W), // OP_LDMIA_W
+/* 1000 1011 1101 */ TABDECL(OP_LDMIA_W), // OP_LDMIA_W
+/* 1000 1011 1110 */ TABDECL(OP_LDMIA_W), // OP_LDMIA_W
+/* 1000 1011 1111 */ TABDECL(OP_LDMIA_W), // OP_LDMIA_W
+
+/* 1000 1100 0000 */ TABDECL(OP_STMIA2), // OP_STMIA2
+/* 1000 1100 0001 */ TABDECL(OP_STMIA2), // OP_STMIA2
+/* 1000 1100 0010 */ TABDECL(OP_STMIA2), // OP_STMIA2
+/* 1000 1100 0011 */ TABDECL(OP_STMIA2), // OP_STMIA2
+/* 1000 1100 0100 */ TABDECL(OP_STMIA2), // OP_STMIA2
+/* 1000 1100 0101 */ TABDECL(OP_STMIA2), // OP_STMIA2
+/* 1000 1100 0110 */ TABDECL(OP_STMIA2), // OP_STMIA2
+/* 1000 1100 0111 */ TABDECL(OP_STMIA2), // OP_STMIA2
+/* 1000 1100 1000 */ TABDECL(OP_STMIA2), // OP_STMIA2
+/* 1000 1100 1001 */ TABDECL(OP_STMIA2), // OP_STMIA2
+/* 1000 1100 1010 */ TABDECL(OP_STMIA2), // OP_STMIA2
+/* 1000 1100 1011 */ TABDECL(OP_STMIA2), // OP_STMIA2
+/* 1000 1100 1100 */ TABDECL(OP_STMIA2), // OP_STMIA2
+/* 1000 1100 1101 */ TABDECL(OP_STMIA2), // OP_STMIA2
+/* 1000 1100 1110 */ TABDECL(OP_STMIA2), // OP_STMIA2
+/* 1000 1100 1111 */ TABDECL(OP_STMIA2), // OP_STMIA2
+
+/* 1000 1101 0000 */ TABDECL(OP_LDMIA2), // OP_LDMIA2
+/* 1000 1101 0001 */ TABDECL(OP_LDMIA2), // OP_LDMIA2
+/* 1000 1101 0010 */ TABDECL(OP_LDMIA2), // OP_LDMIA2
+/* 1000 1101 0011 */ TABDECL(OP_LDMIA2), // OP_LDMIA2
+/* 1000 1101 0100 */ TABDECL(OP_LDMIA2), // OP_LDMIA2
+/* 1000 1101 0101 */ TABDECL(OP_LDMIA2), // OP_LDMIA2
+/* 1000 1101 0110 */ TABDECL(OP_LDMIA2), // OP_LDMIA2
+/* 1000 1101 0111 */ TABDECL(OP_LDMIA2), // OP_LDMIA2
+/* 1000 1101 1000 */ TABDECL(OP_LDMIA2), // OP_LDMIA2
+/* 1000 1101 1001 */ TABDECL(OP_LDMIA2), // OP_LDMIA2
+/* 1000 1101 1010 */ TABDECL(OP_LDMIA2), // OP_LDMIA2
+/* 1000 1101 1011 */ TABDECL(OP_LDMIA2), // OP_LDMIA2
+/* 1000 1101 1100 */ TABDECL(OP_LDMIA2), // OP_LDMIA2
+/* 1000 1101 1101 */ TABDECL(OP_LDMIA2), // OP_LDMIA2
+/* 1000 1101 1110 */ TABDECL(OP_LDMIA2), // OP_LDMIA2
+/* 1000 1101 1111 */ TABDECL(OP_LDMIA2), // OP_LDMIA2
+
+/* 1000 1110 0000 */ TABDECL(OP_STMIA2_W), // OP_STMIA2_W
+/* 1000 1110 0001 */ TABDECL(OP_STMIA2_W), // OP_STMIA2_W
+/* 1000 1110 0010 */ TABDECL(OP_STMIA2_W), // OP_STMIA2_W
+/* 1000 1110 0011 */ TABDECL(OP_STMIA2_W), // OP_STMIA2_W
+/* 1000 1110 0100 */ TABDECL(OP_STMIA2_W), // OP_STMIA2_W
+/* 1000 1110 0101 */ TABDECL(OP_STMIA2_W), // OP_STMIA2_W
+/* 1000 1110 0110 */ TABDECL(OP_STMIA2_W), // OP_STMIA2_W
+/* 1000 1110 0111 */ TABDECL(OP_STMIA2_W), // OP_STMIA2_W
+/* 1000 1110 1000 */ TABDECL(OP_STMIA2_W), // OP_STMIA2_W
+/* 1000 1110 1001 */ TABDECL(OP_STMIA2_W), // OP_STMIA2_W
+/* 1000 1110 1010 */ TABDECL(OP_STMIA2_W), // OP_STMIA2_W
+/* 1000 1110 1011 */ TABDECL(OP_STMIA2_W), // OP_STMIA2_W
+/* 1000 1110 1100 */ TABDECL(OP_STMIA2_W), // OP_STMIA2_W
+/* 1000 1110 1101 */ TABDECL(OP_STMIA2_W), // OP_STMIA2_W
+/* 1000 1110 1110 */ TABDECL(OP_STMIA2_W), // OP_STMIA2_W
+/* 1000 1110 1111 */ TABDECL(OP_STMIA2_W), // OP_STMIA2_W
+
+/* 1000 1111 0000 */ TABDECL(OP_LDMIA2_W), // OP_LDMIA2_W
+/* 1000 1111 0001 */ TABDECL(OP_LDMIA2_W), // OP_LDMIA2_W
+/* 1000 1111 0010 */ TABDECL(OP_LDMIA2_W), // OP_LDMIA2_W
+/* 1000 1111 0011 */ TABDECL(OP_LDMIA2_W), // OP_LDMIA2_W
+/* 1000 1111 0100 */ TABDECL(OP_LDMIA2_W), // OP_LDMIA2_W
+/* 1000 1111 0101 */ TABDECL(OP_LDMIA2_W), // OP_LDMIA2_W
+/* 1000 1111 0110 */ TABDECL(OP_LDMIA2_W), // OP_LDMIA2_W
+/* 1000 1111 0111 */ TABDECL(OP_LDMIA2_W), // OP_LDMIA2_W
+/* 1000 1111 1000 */ TABDECL(OP_LDMIA2_W), // OP_LDMIA2_W
+/* 1000 1111 1001 */ TABDECL(OP_LDMIA2_W), // OP_LDMIA2_W
+/* 1000 1111 1010 */ TABDECL(OP_LDMIA2_W), // OP_LDMIA2_W
+/* 1000 1111 1011 */ TABDECL(OP_LDMIA2_W), // OP_LDMIA2_W
+/* 1000 1111 1100 */ TABDECL(OP_LDMIA2_W), // OP_LDMIA2_W
+/* 1000 1111 1101 */ TABDECL(OP_LDMIA2_W), // OP_LDMIA2_W
+/* 1000 1111 1110 */ TABDECL(OP_LDMIA2_W), // OP_LDMIA2_W
+/* 1000 1111 1111 */ TABDECL(OP_LDMIA2_W), // OP_LDMIA2_W
+
+/* 1001 0000 0000 */ TABDECL(OP_STMDB), // OP_STMDB
+/* 1001 0000 0001 */ TABDECL(OP_STMDB), // OP_STMDB
+/* 1001 0000 0010 */ TABDECL(OP_STMDB), // OP_STMDB
+/* 1001 0000 0011 */ TABDECL(OP_STMDB), // OP_STMDB
+/* 1001 0000 0100 */ TABDECL(OP_STMDB), // OP_STMDB
+/* 1001 0000 0101 */ TABDECL(OP_STMDB), // OP_STMDB
+/* 1001 0000 0110 */ TABDECL(OP_STMDB), // OP_STMDB
+/* 1001 0000 0111 */ TABDECL(OP_STMDB), // OP_STMDB
+/* 1001 0000 1000 */ TABDECL(OP_STMDB), // OP_STMDB
+/* 1001 0000 1001 */ TABDECL(OP_STMDB), // OP_STMDB
+/* 1001 0000 1010 */ TABDECL(OP_STMDB), // OP_STMDB
+/* 1001 0000 1011 */ TABDECL(OP_STMDB), // OP_STMDB
+/* 1001 0000 1100 */ TABDECL(OP_STMDB), // OP_STMDB
+/* 1001 0000 1101 */ TABDECL(OP_STMDB), // OP_STMDB
+/* 1001 0000 1110 */ TABDECL(OP_STMDB), // OP_STMDB
+/* 1001 0000 1111 */ TABDECL(OP_STMDB), // OP_STMDB
+
+/* 1001 0001 0000 */ TABDECL(OP_LDMDB), // OP_LDMDB
+/* 1001 0001 0001 */ TABDECL(OP_LDMDB), // OP_LDMDB
+/* 1001 0001 0010 */ TABDECL(OP_LDMDB), // OP_LDMDB
+/* 1001 0001 0011 */ TABDECL(OP_LDMDB), // OP_LDMDB
+/* 1001 0001 0100 */ TABDECL(OP_LDMDB), // OP_LDMDB
+/* 1001 0001 0101 */ TABDECL(OP_LDMDB), // OP_LDMDB
+/* 1001 0001 0110 */ TABDECL(OP_LDMDB), // OP_LDMDB
+/* 1001 0001 0111 */ TABDECL(OP_LDMDB), // OP_LDMDB
+/* 1001 0001 1000 */ TABDECL(OP_LDMDB), // OP_LDMDB
+/* 1001 0001 1001 */ TABDECL(OP_LDMDB), // OP_LDMDB
+/* 1001 0001 1010 */ TABDECL(OP_LDMDB), // OP_LDMDB
+/* 1001 0001 1011 */ TABDECL(OP_LDMDB), // OP_LDMDB
+/* 1001 0001 1100 */ TABDECL(OP_LDMDB), // OP_LDMDB
+/* 1001 0001 1101 */ TABDECL(OP_LDMDB), // OP_LDMDB
+/* 1001 0001 1110 */ TABDECL(OP_LDMDB), // OP_LDMDB
+/* 1001 0001 1111 */ TABDECL(OP_LDMDB), // OP_LDMDB
+
+/* 1001 0010 0000 */ TABDECL(OP_STMDB_W), // OP_STMDB_W
+/* 1001 0010 0001 */ TABDECL(OP_STMDB_W), // OP_STMDB_W
+/* 1001 0010 0010 */ TABDECL(OP_STMDB_W), // OP_STMDB_W
+/* 1001 0010 0011 */ TABDECL(OP_STMDB_W), // OP_STMDB_W
+/* 1001 0010 0100 */ TABDECL(OP_STMDB_W), // OP_STMDB_W
+/* 1001 0010 0101 */ TABDECL(OP_STMDB_W), // OP_STMDB_W
+/* 1001 0010 0110 */ TABDECL(OP_STMDB_W), // OP_STMDB_W
+/* 1001 0010 0111 */ TABDECL(OP_STMDB_W), // OP_STMDB_W
+/* 1001 0010 1000 */ TABDECL(OP_STMDB_W), // OP_STMDB_W
+/* 1001 0010 1001 */ TABDECL(OP_STMDB_W), // OP_STMDB_W
+/* 1001 0010 1010 */ TABDECL(OP_STMDB_W), // OP_STMDB_W
+/* 1001 0010 1011 */ TABDECL(OP_STMDB_W), // OP_STMDB_W
+/* 1001 0010 1100 */ TABDECL(OP_STMDB_W), // OP_STMDB_W
+/* 1001 0010 1101 */ TABDECL(OP_STMDB_W), // OP_STMDB_W
+/* 1001 0010 1110 */ TABDECL(OP_STMDB_W), // OP_STMDB_W
+/* 1001 0010 1111 */ TABDECL(OP_STMDB_W), // OP_STMDB_W
+
+/* 1001 0011 0000 */ TABDECL(OP_LDMDB_W), // OP_LDMDB_W
+/* 1001 0011 0001 */ TABDECL(OP_LDMDB_W), // OP_LDMDB_W
+/* 1001 0011 0010 */ TABDECL(OP_LDMDB_W), // OP_LDMDB_W
+/* 1001 0011 0011 */ TABDECL(OP_LDMDB_W), // OP_LDMDB_W
+/* 1001 0011 0100 */ TABDECL(OP_LDMDB_W), // OP_LDMDB_W
+/* 1001 0011 0101 */ TABDECL(OP_LDMDB_W), // OP_LDMDB_W
+/* 1001 0011 0110 */ TABDECL(OP_LDMDB_W), // OP_LDMDB_W
+/* 1001 0011 0111 */ TABDECL(OP_LDMDB_W), // OP_LDMDB_W
+/* 1001 0011 1000 */ TABDECL(OP_LDMDB_W), // OP_LDMDB_W
+/* 1001 0011 1001 */ TABDECL(OP_LDMDB_W), // OP_LDMDB_W
+/* 1001 0011 1010 */ TABDECL(OP_LDMDB_W), // OP_LDMDB_W
+/* 1001 0011 1011 */ TABDECL(OP_LDMDB_W), // OP_LDMDB_W
+/* 1001 0011 1100 */ TABDECL(OP_LDMDB_W), // OP_LDMDB_W
+/* 1001 0011 1101 */ TABDECL(OP_LDMDB_W), // OP_LDMDB_W
+/* 1001 0011 1110 */ TABDECL(OP_LDMDB_W), // OP_LDMDB_W
+/* 1001 0011 1111 */ TABDECL(OP_LDMDB_W), // OP_LDMDB_W
+
+/* 1001 0100 0000 */ TABDECL(OP_STMDB2), // OP_STMDB2
+/* 1001 0100 0001 */ TABDECL(OP_STMDB2), // OP_STMDB2
+/* 1001 0100 0010 */ TABDECL(OP_STMDB2), // OP_STMDB2
+/* 1001 0100 0011 */ TABDECL(OP_STMDB2), // OP_STMDB2
+/* 1001 0100 0100 */ TABDECL(OP_STMDB2), // OP_STMDB2
+/* 1001 0100 0101 */ TABDECL(OP_STMDB2), // OP_STMDB2
+/* 1001 0100 0110 */ TABDECL(OP_STMDB2), // OP_STMDB2
+/* 1001 0100 0111 */ TABDECL(OP_STMDB2), // OP_STMDB2
+/* 1001 0100 1000 */ TABDECL(OP_STMDB2), // OP_STMDB2
+/* 1001 0100 1001 */ TABDECL(OP_STMDB2), // OP_STMDB2
+/* 1001 0100 1010 */ TABDECL(OP_STMDB2), // OP_STMDB2
+/* 1001 0100 1011 */ TABDECL(OP_STMDB2), // OP_STMDB2
+/* 1001 0100 1100 */ TABDECL(OP_STMDB2), // OP_STMDB2
+/* 1001 0100 1101 */ TABDECL(OP_STMDB2), // OP_STMDB2
+/* 1001 0100 1110 */ TABDECL(OP_STMDB2), // OP_STMDB2
+/* 1001 0100 1111 */ TABDECL(OP_STMDB2), // OP_STMDB2
+
+/* 1001 0101 0000 */ TABDECL(OP_LDMDB2), // OP_LDMDB2
+/* 1001 0101 0001 */ TABDECL(OP_LDMDB2), // OP_LDMDB2
+/* 1001 0101 0010 */ TABDECL(OP_LDMDB2), // OP_LDMDB2
+/* 1001 0101 0011 */ TABDECL(OP_LDMDB2), // OP_LDMDB2
+/* 1001 0101 0100 */ TABDECL(OP_LDMDB2), // OP_LDMDB2
+/* 1001 0101 0101 */ TABDECL(OP_LDMDB2), // OP_LDMDB2
+/* 1001 0101 0110 */ TABDECL(OP_LDMDB2), // OP_LDMDB2
+/* 1001 0101 0111 */ TABDECL(OP_LDMDB2), // OP_LDMDB2
+/* 1001 0101 1000 */ TABDECL(OP_LDMDB2), // OP_LDMDB2
+/* 1001 0101 1001 */ TABDECL(OP_LDMDB2), // OP_LDMDB2
+/* 1001 0101 1010 */ TABDECL(OP_LDMDB2), // OP_LDMDB2
+/* 1001 0101 1011 */ TABDECL(OP_LDMDB2), // OP_LDMDB2
+/* 1001 0101 1100 */ TABDECL(OP_LDMDB2), // OP_LDMDB2
+/* 1001 0101 1101 */ TABDECL(OP_LDMDB2), // OP_LDMDB2
+/* 1001 0101 1110 */ TABDECL(OP_LDMDB2), // OP_LDMDB2
+/* 1001 0101 1111 */ TABDECL(OP_LDMDB2), // OP_LDMDB2
+
+/* 1001 0110 0000 */ TABDECL(OP_STMDB2_W), // OP_STMDB2_W
+/* 1001 0110 0001 */ TABDECL(OP_STMDB2_W), // OP_STMDB2_W
+/* 1001 0110 0010 */ TABDECL(OP_STMDB2_W), // OP_STMDB2_W
+/* 1001 0110 0011 */ TABDECL(OP_STMDB2_W), // OP_STMDB2_W
+/* 1001 0110 0100 */ TABDECL(OP_STMDB2_W), // OP_STMDB2_W
+/* 1001 0110 0101 */ TABDECL(OP_STMDB2_W), // OP_STMDB2_W
+/* 1001 0110 0110 */ TABDECL(OP_STMDB2_W), // OP_STMDB2_W
+/* 1001 0110 0111 */ TABDECL(OP_STMDB2_W), // OP_STMDB2_W
+/* 1001 0110 1000 */ TABDECL(OP_STMDB2_W), // OP_STMDB2_W
+/* 1001 0110 1001 */ TABDECL(OP_STMDB2_W), // OP_STMDB2_W
+/* 1001 0110 1010 */ TABDECL(OP_STMDB2_W), // OP_STMDB2_W
+/* 1001 0110 1011 */ TABDECL(OP_STMDB2_W), // OP_STMDB2_W
+/* 1001 0110 1100 */ TABDECL(OP_STMDB2_W), // OP_STMDB2_W
+/* 1001 0110 1101 */ TABDECL(OP_STMDB2_W), // OP_STMDB2_W
+/* 1001 0110 1110 */ TABDECL(OP_STMDB2_W), // OP_STMDB2_W
+/* 1001 0110 1111 */ TABDECL(OP_STMDB2_W), // OP_STMDB2_W
+
+/* 1001 0111 0000 */ TABDECL(OP_LDMDB2_W), // OP_LDMDB2_W
+/* 1001 0111 0001 */ TABDECL(OP_LDMDB2_W), // OP_LDMDB2_W
+/* 1001 0111 0010 */ TABDECL(OP_LDMDB2_W), // OP_LDMDB2_W
+/* 1001 0111 0011 */ TABDECL(OP_LDMDB2_W), // OP_LDMDB2_W
+/* 1001 0111 0100 */ TABDECL(OP_LDMDB2_W), // OP_LDMDB2_W
+/* 1001 0111 0101 */ TABDECL(OP_LDMDB2_W), // OP_LDMDB2_W
+/* 1001 0111 0110 */ TABDECL(OP_LDMDB2_W), // OP_LDMDB2_W
+/* 1001 0111 0111 */ TABDECL(OP_LDMDB2_W), // OP_LDMDB2_W
+/* 1001 0111 1000 */ TABDECL(OP_LDMDB2_W), // OP_LDMDB2_W
+/* 1001 0111 1001 */ TABDECL(OP_LDMDB2_W), // OP_LDMDB2_W
+/* 1001 0111 1010 */ TABDECL(OP_LDMDB2_W), // OP_LDMDB2_W
+/* 1001 0111 1011 */ TABDECL(OP_LDMDB2_W), // OP_LDMDB2_W
+/* 1001 0111 1100 */ TABDECL(OP_LDMDB2_W), // OP_LDMDB2_W
+/* 1001 0111 1101 */ TABDECL(OP_LDMDB2_W), // OP_LDMDB2_W
+/* 1001 0111 1110 */ TABDECL(OP_LDMDB2_W), // OP_LDMDB2_W
+/* 1001 0111 1111 */ TABDECL(OP_LDMDB2_W), // OP_LDMDB2_W
+
+/* 1001 1000 0000 */ TABDECL(OP_STMIB), // OP_STMIB
+/* 1001 1000 0001 */ TABDECL(OP_STMIB), // OP_STMIB
+/* 1001 1000 0010 */ TABDECL(OP_STMIB), // OP_STMIB
+/* 1001 1000 0011 */ TABDECL(OP_STMIB), // OP_STMIB
+/* 1001 1000 0100 */ TABDECL(OP_STMIB), // OP_STMIB
+/* 1001 1000 0101 */ TABDECL(OP_STMIB), // OP_STMIB
+/* 1001 1000 0110 */ TABDECL(OP_STMIB), // OP_STMIB
+/* 1001 1000 0111 */ TABDECL(OP_STMIB), // OP_STMIB
+/* 1001 1000 1000 */ TABDECL(OP_STMIB), // OP_STMIB
+/* 1001 1000 1001 */ TABDECL(OP_STMIB), // OP_STMIB
+/* 1001 1000 1010 */ TABDECL(OP_STMIB), // OP_STMIB
+/* 1001 1000 1011 */ TABDECL(OP_STMIB), // OP_STMIB
+/* 1001 1000 1100 */ TABDECL(OP_STMIB), // OP_STMIB
+/* 1001 1000 1101 */ TABDECL(OP_STMIB), // OP_STMIB
+/* 1001 1000 1110 */ TABDECL(OP_STMIB), // OP_STMIB
+/* 1001 1000 1111 */ TABDECL(OP_STMIB), // OP_STMIB
+
+/* 1001 1001 0000 */ TABDECL(OP_LDMIB), // OP_LDMIB
+/* 1001 1001 0001 */ TABDECL(OP_LDMIB), // OP_LDMIB
+/* 1001 1001 0010 */ TABDECL(OP_LDMIB), // OP_LDMIB
+/* 1001 1001 0011 */ TABDECL(OP_LDMIB), // OP_LDMIB
+/* 1001 1001 0100 */ TABDECL(OP_LDMIB), // OP_LDMIB
+/* 1001 1001 0101 */ TABDECL(OP_LDMIB), // OP_LDMIB
+/* 1001 1001 0110 */ TABDECL(OP_LDMIB), // OP_LDMIB
+/* 1001 1001 0111 */ TABDECL(OP_LDMIB), // OP_LDMIB
+/* 1001 1001 1000 */ TABDECL(OP_LDMIB), // OP_LDMIB
+/* 1001 1001 1001 */ TABDECL(OP_LDMIB), // OP_LDMIB
+/* 1001 1001 1010 */ TABDECL(OP_LDMIB), // OP_LDMIB
+/* 1001 1001 1011 */ TABDECL(OP_LDMIB), // OP_LDMIB
+/* 1001 1001 1100 */ TABDECL(OP_LDMIB), // OP_LDMIB
+/* 1001 1001 1101 */ TABDECL(OP_LDMIB), // OP_LDMIB
+/* 1001 1001 1110 */ TABDECL(OP_LDMIB), // OP_LDMIB
+/* 1001 1001 1111 */ TABDECL(OP_LDMIB), // OP_LDMIB
+
+/* 1001 1010 0000 */ TABDECL(OP_STMIB_W), // OP_STMIB_W
+/* 1001 1010 0001 */ TABDECL(OP_STMIB_W), // OP_STMIB_W
+/* 1001 1010 0010 */ TABDECL(OP_STMIB_W), // OP_STMIB_W
+/* 1001 1010 0011 */ TABDECL(OP_STMIB_W), // OP_STMIB_W
+/* 1001 1010 0100 */ TABDECL(OP_STMIB_W), // OP_STMIB_W
+/* 1001 1010 0101 */ TABDECL(OP_STMIB_W), // OP_STMIB_W
+/* 1001 1010 0110 */ TABDECL(OP_STMIB_W), // OP_STMIB_W
+/* 1001 1010 0111 */ TABDECL(OP_STMIB_W), // OP_STMIB_W
+/* 1001 1010 1000 */ TABDECL(OP_STMIB_W), // OP_STMIB_W
+/* 1001 1010 1001 */ TABDECL(OP_STMIB_W), // OP_STMIB_W
+/* 1001 1010 1010 */ TABDECL(OP_STMIB_W), // OP_STMIB_W
+/* 1001 1010 1011 */ TABDECL(OP_STMIB_W), // OP_STMIB_W
+/* 1001 1010 1100 */ TABDECL(OP_STMIB_W), // OP_STMIB_W
+/* 1001 1010 1101 */ TABDECL(OP_STMIB_W), // OP_STMIB_W
+/* 1001 1010 1110 */ TABDECL(OP_STMIB_W), // OP_STMIB_W
+/* 1001 1010 1111 */ TABDECL(OP_STMIB_W), // OP_STMIB_W
+
+/* 1001 1011 0000 */ TABDECL(OP_LDMIB_W), // OP_LDMIB_W
+/* 1001 1011 0001 */ TABDECL(OP_LDMIB_W), // OP_LDMIB_W
+/* 1001 1011 0010 */ TABDECL(OP_LDMIB_W), // OP_LDMIB_W
+/* 1001 1011 0011 */ TABDECL(OP_LDMIB_W), // OP_LDMIB_W
+/* 1001 1011 0100 */ TABDECL(OP_LDMIB_W), // OP_LDMIB_W
+/* 1001 1011 0101 */ TABDECL(OP_LDMIB_W), // OP_LDMIB_W
+/* 1001 1011 0110 */ TABDECL(OP_LDMIB_W), // OP_LDMIB_W
+/* 1001 1011 0111 */ TABDECL(OP_LDMIB_W), // OP_LDMIB_W
+/* 1001 1011 1000 */ TABDECL(OP_LDMIB_W), // OP_LDMIB_W
+/* 1001 1011 1001 */ TABDECL(OP_LDMIB_W), // OP_LDMIB_W
+/* 1001 1011 1010 */ TABDECL(OP_LDMIB_W), // OP_LDMIB_W
+/* 1001 1011 1011 */ TABDECL(OP_LDMIB_W), // OP_LDMIB_W
+/* 1001 1011 1100 */ TABDECL(OP_LDMIB_W), // OP_LDMIB_W
+/* 1001 1011 1101 */ TABDECL(OP_LDMIB_W), // OP_LDMIB_W
+/* 1001 1011 1110 */ TABDECL(OP_LDMIB_W), // OP_LDMIB_W
+/* 1001 1011 1111 */ TABDECL(OP_LDMIB_W), // OP_LDMIB_W
+
+/* 1001 1100 0000 */ TABDECL(OP_STMIB2), // OP_STMIB2
+/* 1001 1100 0001 */ TABDECL(OP_STMIB2), // OP_STMIB2
+/* 1001 1100 0010 */ TABDECL(OP_STMIB2), // OP_STMIB2
+/* 1001 1100 0011 */ TABDECL(OP_STMIB2), // OP_STMIB2
+/* 1001 1100 0100 */ TABDECL(OP_STMIB2), // OP_STMIB2
+/* 1001 1100 0101 */ TABDECL(OP_STMIB2), // OP_STMIB2
+/* 1001 1100 0110 */ TABDECL(OP_STMIB2), // OP_STMIB2
+/* 1001 1100 0111 */ TABDECL(OP_STMIB2), // OP_STMIB2
+/* 1001 1100 1000 */ TABDECL(OP_STMIB2), // OP_STMIB2
+/* 1001 1100 1001 */ TABDECL(OP_STMIB2), // OP_STMIB2
+/* 1001 1100 1010 */ TABDECL(OP_STMIB2), // OP_STMIB2
+/* 1001 1100 1011 */ TABDECL(OP_STMIB2), // OP_STMIB2
+/* 1001 1100 1100 */ TABDECL(OP_STMIB2), // OP_STMIB2
+/* 1001 1100 1101 */ TABDECL(OP_STMIB2), // OP_STMIB2
+/* 1001 1100 1110 */ TABDECL(OP_STMIB2), // OP_STMIB2
+/* 1001 1100 1111 */ TABDECL(OP_STMIB2), // OP_STMIB2
+
+/* 1001 1101 0000 */ TABDECL(OP_LDMIB2), // OP_LDMIB2
+/* 1001 1101 0001 */ TABDECL(OP_LDMIB2), // OP_LDMIB2
+/* 1001 1101 0010 */ TABDECL(OP_LDMIB2), // OP_LDMIB2
+/* 1001 1101 0011 */ TABDECL(OP_LDMIB2), // OP_LDMIB2
+/* 1001 1101 0100 */ TABDECL(OP_LDMIB2), // OP_LDMIB2
+/* 1001 1101 0101 */ TABDECL(OP_LDMIB2), // OP_LDMIB2
+/* 1001 1101 0110 */ TABDECL(OP_LDMIB2), // OP_LDMIB2
+/* 1001 1101 0111 */ TABDECL(OP_LDMIB2), // OP_LDMIB2
+/* 1001 1101 1000 */ TABDECL(OP_LDMIB2), // OP_LDMIB2
+/* 1001 1101 1001 */ TABDECL(OP_LDMIB2), // OP_LDMIB2
+/* 1001 1101 1010 */ TABDECL(OP_LDMIB2), // OP_LDMIB2
+/* 1001 1101 1011 */ TABDECL(OP_LDMIB2), // OP_LDMIB2
+/* 1001 1101 1100 */ TABDECL(OP_LDMIB2), // OP_LDMIB2
+/* 1001 1101 1101 */ TABDECL(OP_LDMIB2), // OP_LDMIB2
+/* 1001 1101 1110 */ TABDECL(OP_LDMIB2), // OP_LDMIB2
+/* 1001 1101 1111 */ TABDECL(OP_LDMIB2), // OP_LDMIB2
+
+/* 1001 1110 0000 */ TABDECL(OP_STMIB2_W), // OP_STMIB2_W
+/* 1001 1110 0001 */ TABDECL(OP_STMIB2_W), // OP_STMIB2_W
+/* 1001 1110 0010 */ TABDECL(OP_STMIB2_W), // OP_STMIB2_W
+/* 1001 1110 0011 */ TABDECL(OP_STMIB2_W), // OP_STMIB2_W
+/* 1001 1110 0100 */ TABDECL(OP_STMIB2_W), // OP_STMIB2_W
+/* 1001 1110 0101 */ TABDECL(OP_STMIB2_W), // OP_STMIB2_W
+/* 1001 1110 0110 */ TABDECL(OP_STMIB2_W), // OP_STMIB2_W
+/* 1001 1110 0111 */ TABDECL(OP_STMIB2_W), // OP_STMIB2_W
+/* 1001 1110 1000 */ TABDECL(OP_STMIB2_W), // OP_STMIB2_W
+/* 1001 1110 1001 */ TABDECL(OP_STMIB2_W), // OP_STMIB2_W
+/* 1001 1110 1010 */ TABDECL(OP_STMIB2_W), // OP_STMIB2_W
+/* 1001 1110 1011 */ TABDECL(OP_STMIB2_W), // OP_STMIB2_W
+/* 1001 1110 1100 */ TABDECL(OP_STMIB2_W), // OP_STMIB2_W
+/* 1001 1110 1101 */ TABDECL(OP_STMIB2_W), // OP_STMIB2_W
+/* 1001 1110 1110 */ TABDECL(OP_STMIB2_W), // OP_STMIB2_W
+/* 1001 1110 1111 */ TABDECL(OP_STMIB2_W), // OP_STMIB2_W
+
+/* 1001 1111 0000 */ TABDECL(OP_LDMIB2_W), // OP_LDMIB2_W
+/* 1001 1111 0001 */ TABDECL(OP_LDMIB2_W), // OP_LDMIB2_W
+/* 1001 1111 0010 */ TABDECL(OP_LDMIB2_W), // OP_LDMIB2_W
+/* 1001 1111 0011 */ TABDECL(OP_LDMIB2_W), // OP_LDMIB2_W
+/* 1001 1111 0100 */ TABDECL(OP_LDMIB2_W), // OP_LDMIB2_W
+/* 1001 1111 0101 */ TABDECL(OP_LDMIB2_W), // OP_LDMIB2_W
+/* 1001 1111 0110 */ TABDECL(OP_LDMIB2_W), // OP_LDMIB2_W
+/* 1001 1111 0111 */ TABDECL(OP_LDMIB2_W), // OP_LDMIB2_W
+/* 1001 1111 1000 */ TABDECL(OP_LDMIB2_W), // OP_LDMIB2_W
+/* 1001 1111 1001 */ TABDECL(OP_LDMIB2_W), // OP_LDMIB2_W
+/* 1001 1111 1010 */ TABDECL(OP_LDMIB2_W), // OP_LDMIB2_W
+/* 1001 1111 1011 */ TABDECL(OP_LDMIB2_W), // OP_LDMIB2_W
+/* 1001 1111 1100 */ TABDECL(OP_LDMIB2_W), // OP_LDMIB2_W
+/* 1001 1111 1101 */ TABDECL(OP_LDMIB2_W), // OP_LDMIB2_W
+/* 1001 1111 1110 */ TABDECL(OP_LDMIB2_W), // OP_LDMIB2_W
+/* 1001 1111 1111 */ TABDECL(OP_LDMIB2_W), // OP_LDMIB2_W
+
+/* 1010 0000 0000 */ TABDECL(OP_B), // OP_B
+/* 1010 0000 0001 */ TABDECL(OP_B), // OP_B
+/* 1010 0000 0010 */ TABDECL(OP_B), // OP_B
+/* 1010 0000 0011 */ TABDECL(OP_B), // OP_B
+/* 1010 0000 0100 */ TABDECL(OP_B), // OP_B
+/* 1010 0000 0101 */ TABDECL(OP_B), // OP_B
+/* 1010 0000 0110 */ TABDECL(OP_B), // OP_B
+/* 1010 0000 0111 */ TABDECL(OP_B), // OP_B
+/* 1010 0000 1000 */ TABDECL(OP_B), // OP_B
+/* 1010 0000 1001 */ TABDECL(OP_B), // OP_B
+/* 1010 0000 1010 */ TABDECL(OP_B), // OP_B
+/* 1010 0000 1011 */ TABDECL(OP_B), // OP_B
+/* 1010 0000 1100 */ TABDECL(OP_B), // OP_B
+/* 1010 0000 1101 */ TABDECL(OP_B), // OP_B
+/* 1010 0000 1110 */ TABDECL(OP_B), // OP_B
+/* 1010 0000 1111 */ TABDECL(OP_B), // OP_B
+
+/* 1010 0001 0000 */ TABDECL(OP_B), // OP_B
+/* 1010 0001 0001 */ TABDECL(OP_B), // OP_B
+/* 1010 0001 0010 */ TABDECL(OP_B), // OP_B
+/* 1010 0001 0011 */ TABDECL(OP_B), // OP_B
+/* 1010 0001 0100 */ TABDECL(OP_B), // OP_B
+/* 1010 0001 0101 */ TABDECL(OP_B), // OP_B
+/* 1010 0001 0110 */ TABDECL(OP_B), // OP_B
+/* 1010 0001 0111 */ TABDECL(OP_B), // OP_B
+/* 1010 0001 1000 */ TABDECL(OP_B), // OP_B
+/* 1010 0001 1001 */ TABDECL(OP_B), // OP_B
+/* 1010 0001 1010 */ TABDECL(OP_B), // OP_B
+/* 1010 0001 1011 */ TABDECL(OP_B), // OP_B
+/* 1010 0001 1100 */ TABDECL(OP_B), // OP_B
+/* 1010 0001 1101 */ TABDECL(OP_B), // OP_B
+/* 1010 0001 1110 */ TABDECL(OP_B), // OP_B
+/* 1010 0001 1111 */ TABDECL(OP_B), // OP_B
+
+/* 1010 0010 0000 */ TABDECL(OP_B), // OP_B
+/* 1010 0010 0001 */ TABDECL(OP_B), // OP_B
+/* 1010 0010 0010 */ TABDECL(OP_B), // OP_B
+/* 1010 0010 0011 */ TABDECL(OP_B), // OP_B
+/* 1010 0010 0100 */ TABDECL(OP_B), // OP_B
+/* 1010 0010 0101 */ TABDECL(OP_B), // OP_B
+/* 1010 0010 0110 */ TABDECL(OP_B), // OP_B
+/* 1010 0010 0111 */ TABDECL(OP_B), // OP_B
+/* 1010 0010 1000 */ TABDECL(OP_B), // OP_B
+/* 1010 0010 1001 */ TABDECL(OP_B), // OP_B
+/* 1010 0010 1010 */ TABDECL(OP_B), // OP_B
+/* 1010 0010 1011 */ TABDECL(OP_B), // OP_B
+/* 1010 0010 1100 */ TABDECL(OP_B), // OP_B
+/* 1010 0010 1101 */ TABDECL(OP_B), // OP_B
+/* 1010 0010 1110 */ TABDECL(OP_B), // OP_B
+/* 1010 0010 1111 */ TABDECL(OP_B), // OP_B
+
+/* 1010 0011 0000 */ TABDECL(OP_B), // OP_B
+/* 1010 0011 0001 */ TABDECL(OP_B), // OP_B
+/* 1010 0011 0010 */ TABDECL(OP_B), // OP_B
+/* 1010 0011 0011 */ TABDECL(OP_B), // OP_B
+/* 1010 0011 0100 */ TABDECL(OP_B), // OP_B
+/* 1010 0011 0101 */ TABDECL(OP_B), // OP_B
+/* 1010 0011 0110 */ TABDECL(OP_B), // OP_B
+/* 1010 0011 0111 */ TABDECL(OP_B), // OP_B
+/* 1010 0011 1000 */ TABDECL(OP_B), // OP_B
+/* 1010 0011 1001 */ TABDECL(OP_B), // OP_B
+/* 1010 0011 1010 */ TABDECL(OP_B), // OP_B
+/* 1010 0011 1011 */ TABDECL(OP_B), // OP_B
+/* 1010 0011 1100 */ TABDECL(OP_B), // OP_B
+/* 1010 0011 1101 */ TABDECL(OP_B), // OP_B
+/* 1010 0011 1110 */ TABDECL(OP_B), // OP_B
+/* 1010 0011 1111 */ TABDECL(OP_B), // OP_B
+
+/* 1010 0100 0000 */ TABDECL(OP_B), // OP_B
+/* 1010 0100 0001 */ TABDECL(OP_B), // OP_B
+/* 1010 0100 0010 */ TABDECL(OP_B), // OP_B
+/* 1010 0100 0011 */ TABDECL(OP_B), // OP_B
+/* 1010 0100 0100 */ TABDECL(OP_B), // OP_B
+/* 1010 0100 0101 */ TABDECL(OP_B), // OP_B
+/* 1010 0100 0110 */ TABDECL(OP_B), // OP_B
+/* 1010 0100 0111 */ TABDECL(OP_B), // OP_B
+/* 1010 0100 1000 */ TABDECL(OP_B), // OP_B
+/* 1010 0100 1001 */ TABDECL(OP_B), // OP_B
+/* 1010 0100 1010 */ TABDECL(OP_B), // OP_B
+/* 1010 0100 1011 */ TABDECL(OP_B), // OP_B
+/* 1010 0100 1100 */ TABDECL(OP_B), // OP_B
+/* 1010 0100 1101 */ TABDECL(OP_B), // OP_B
+/* 1010 0100 1110 */ TABDECL(OP_B), // OP_B
+/* 1010 0100 1111 */ TABDECL(OP_B), // OP_B
+
+/* 1010 0101 0000 */ TABDECL(OP_B), // OP_B
+/* 1010 0101 0001 */ TABDECL(OP_B), // OP_B
+/* 1010 0101 0010 */ TABDECL(OP_B), // OP_B
+/* 1010 0101 0011 */ TABDECL(OP_B), // OP_B
+/* 1010 0101 0100 */ TABDECL(OP_B), // OP_B
+/* 1010 0101 0101 */ TABDECL(OP_B), // OP_B
+/* 1010 0101 0110 */ TABDECL(OP_B), // OP_B
+/* 1010 0101 0111 */ TABDECL(OP_B), // OP_B
+/* 1010 0101 1000 */ TABDECL(OP_B), // OP_B
+/* 1010 0101 1001 */ TABDECL(OP_B), // OP_B
+/* 1010 0101 1010 */ TABDECL(OP_B), // OP_B
+/* 1010 0101 1011 */ TABDECL(OP_B), // OP_B
+/* 1010 0101 1100 */ TABDECL(OP_B), // OP_B
+/* 1010 0101 1101 */ TABDECL(OP_B), // OP_B
+/* 1010 0101 1110 */ TABDECL(OP_B), // OP_B
+/* 1010 0101 1111 */ TABDECL(OP_B), // OP_B
+
+/* 1010 0110 0000 */ TABDECL(OP_B), // OP_B
+/* 1010 0110 0001 */ TABDECL(OP_B), // OP_B
+/* 1010 0110 0010 */ TABDECL(OP_B), // OP_B
+/* 1010 0110 0011 */ TABDECL(OP_B), // OP_B
+/* 1010 0110 0100 */ TABDECL(OP_B), // OP_B
+/* 1010 0110 0101 */ TABDECL(OP_B), // OP_B
+/* 1010 0110 0110 */ TABDECL(OP_B), // OP_B
+/* 1010 0110 0111 */ TABDECL(OP_B), // OP_B
+/* 1010 0110 1000 */ TABDECL(OP_B), // OP_B
+/* 1010 0110 1001 */ TABDECL(OP_B), // OP_B
+/* 1010 0110 1010 */ TABDECL(OP_B), // OP_B
+/* 1010 0110 1011 */ TABDECL(OP_B), // OP_B
+/* 1010 0110 1100 */ TABDECL(OP_B), // OP_B
+/* 1010 0110 1101 */ TABDECL(OP_B), // OP_B
+/* 1010 0110 1110 */ TABDECL(OP_B), // OP_B
+/* 1010 0110 1111 */ TABDECL(OP_B), // OP_B
+
+/* 1010 0111 0000 */ TABDECL(OP_B), // OP_B
+/* 1010 0111 0001 */ TABDECL(OP_B), // OP_B
+/* 1010 0111 0010 */ TABDECL(OP_B), // OP_B
+/* 1010 0111 0011 */ TABDECL(OP_B), // OP_B
+/* 1010 0111 0100 */ TABDECL(OP_B), // OP_B
+/* 1010 0111 0101 */ TABDECL(OP_B), // OP_B
+/* 1010 0111 0110 */ TABDECL(OP_B), // OP_B
+/* 1010 0111 0111 */ TABDECL(OP_B), // OP_B
+/* 1010 0111 1000 */ TABDECL(OP_B), // OP_B
+/* 1010 0111 1001 */ TABDECL(OP_B), // OP_B
+/* 1010 0111 1010 */ TABDECL(OP_B), // OP_B
+/* 1010 0111 1011 */ TABDECL(OP_B), // OP_B
+/* 1010 0111 1100 */ TABDECL(OP_B), // OP_B
+/* 1010 0111 1101 */ TABDECL(OP_B), // OP_B
+/* 1010 0111 1110 */ TABDECL(OP_B), // OP_B
+/* 1010 0111 1111 */ TABDECL(OP_B), // OP_B
+
+/* 1010 1000 0000 */ TABDECL(OP_B), // OP_B
+/* 1010 1000 0001 */ TABDECL(OP_B), // OP_B
+/* 1010 1000 0010 */ TABDECL(OP_B), // OP_B
+/* 1010 1000 0011 */ TABDECL(OP_B), // OP_B
+/* 1010 1000 0100 */ TABDECL(OP_B), // OP_B
+/* 1010 1000 0101 */ TABDECL(OP_B), // OP_B
+/* 1010 1000 0110 */ TABDECL(OP_B), // OP_B
+/* 1010 1000 0111 */ TABDECL(OP_B), // OP_B
+/* 1010 1000 1000 */ TABDECL(OP_B), // OP_B
+/* 1010 1000 1001 */ TABDECL(OP_B), // OP_B
+/* 1010 1000 1010 */ TABDECL(OP_B), // OP_B
+/* 1010 1000 1011 */ TABDECL(OP_B), // OP_B
+/* 1010 1000 1100 */ TABDECL(OP_B), // OP_B
+/* 1010 1000 1101 */ TABDECL(OP_B), // OP_B
+/* 1010 1000 1110 */ TABDECL(OP_B), // OP_B
+/* 1010 1000 1111 */ TABDECL(OP_B), // OP_B
+
+/* 1010 1001 0000 */ TABDECL(OP_B), // OP_B
+/* 1010 1001 0001 */ TABDECL(OP_B), // OP_B
+/* 1010 1001 0010 */ TABDECL(OP_B), // OP_B
+/* 1010 1001 0011 */ TABDECL(OP_B), // OP_B
+/* 1010 1001 0100 */ TABDECL(OP_B), // OP_B
+/* 1010 1001 0101 */ TABDECL(OP_B), // OP_B
+/* 1010 1001 0110 */ TABDECL(OP_B), // OP_B
+/* 1010 1001 0111 */ TABDECL(OP_B), // OP_B
+/* 1010 1001 1000 */ TABDECL(OP_B), // OP_B
+/* 1010 1001 1001 */ TABDECL(OP_B), // OP_B
+/* 1010 1001 1010 */ TABDECL(OP_B), // OP_B
+/* 1010 1001 1011 */ TABDECL(OP_B), // OP_B
+/* 1010 1001 1100 */ TABDECL(OP_B), // OP_B
+/* 1010 1001 1101 */ TABDECL(OP_B), // OP_B
+/* 1010 1001 1110 */ TABDECL(OP_B), // OP_B
+/* 1010 1001 1111 */ TABDECL(OP_B), // OP_B
+
+/* 1010 1010 0000 */ TABDECL(OP_B), // OP_B
+/* 1010 1010 0001 */ TABDECL(OP_B), // OP_B
+/* 1010 1010 0010 */ TABDECL(OP_B), // OP_B
+/* 1010 1010 0011 */ TABDECL(OP_B), // OP_B
+/* 1010 1010 0100 */ TABDECL(OP_B), // OP_B
+/* 1010 1010 0101 */ TABDECL(OP_B), // OP_B
+/* 1010 1010 0110 */ TABDECL(OP_B), // OP_B
+/* 1010 1010 0111 */ TABDECL(OP_B), // OP_B
+/* 1010 1010 1000 */ TABDECL(OP_B), // OP_B
+/* 1010 1010 1001 */ TABDECL(OP_B), // OP_B
+/* 1010 1010 1010 */ TABDECL(OP_B), // OP_B
+/* 1010 1010 1011 */ TABDECL(OP_B), // OP_B
+/* 1010 1010 1100 */ TABDECL(OP_B), // OP_B
+/* 1010 1010 1101 */ TABDECL(OP_B), // OP_B
+/* 1010 1010 1110 */ TABDECL(OP_B), // OP_B
+/* 1010 1010 1111 */ TABDECL(OP_B), // OP_B
+
+/* 1010 1011 0000 */ TABDECL(OP_B), // OP_B
+/* 1010 1011 0001 */ TABDECL(OP_B), // OP_B
+/* 1010 1011 0010 */ TABDECL(OP_B), // OP_B
+/* 1010 1011 0011 */ TABDECL(OP_B), // OP_B
+/* 1010 1011 0100 */ TABDECL(OP_B), // OP_B
+/* 1010 1011 0101 */ TABDECL(OP_B), // OP_B
+/* 1010 1011 0110 */ TABDECL(OP_B), // OP_B
+/* 1010 1011 0111 */ TABDECL(OP_B), // OP_B
+/* 1010 1011 1000 */ TABDECL(OP_B), // OP_B
+/* 1010 1011 1001 */ TABDECL(OP_B), // OP_B
+/* 1010 1011 1010 */ TABDECL(OP_B), // OP_B
+/* 1010 1011 1011 */ TABDECL(OP_B), // OP_B
+/* 1010 1011 1100 */ TABDECL(OP_B), // OP_B
+/* 1010 1011 1101 */ TABDECL(OP_B), // OP_B
+/* 1010 1011 1110 */ TABDECL(OP_B), // OP_B
+/* 1010 1011 1111 */ TABDECL(OP_B), // OP_B
+
+/* 1010 1100 0000 */ TABDECL(OP_B), // OP_B
+/* 1010 1100 0001 */ TABDECL(OP_B), // OP_B
+/* 1010 1100 0010 */ TABDECL(OP_B), // OP_B
+/* 1010 1100 0011 */ TABDECL(OP_B), // OP_B
+/* 1010 1100 0100 */ TABDECL(OP_B), // OP_B
+/* 1010 1100 0101 */ TABDECL(OP_B), // OP_B
+/* 1010 1100 0110 */ TABDECL(OP_B), // OP_B
+/* 1010 1100 0111 */ TABDECL(OP_B), // OP_B
+/* 1010 1100 1000 */ TABDECL(OP_B), // OP_B
+/* 1010 1100 1001 */ TABDECL(OP_B), // OP_B
+/* 1010 1100 1010 */ TABDECL(OP_B), // OP_B
+/* 1010 1100 1011 */ TABDECL(OP_B), // OP_B
+/* 1010 1100 1100 */ TABDECL(OP_B), // OP_B
+/* 1010 1100 1101 */ TABDECL(OP_B), // OP_B
+/* 1010 1100 1110 */ TABDECL(OP_B), // OP_B
+/* 1010 1100 1111 */ TABDECL(OP_B), // OP_B
+
+/* 1010 1101 0000 */ TABDECL(OP_B), // OP_B
+/* 1010 1101 0001 */ TABDECL(OP_B), // OP_B
+/* 1010 1101 0010 */ TABDECL(OP_B), // OP_B
+/* 1010 1101 0011 */ TABDECL(OP_B), // OP_B
+/* 1010 1101 0100 */ TABDECL(OP_B), // OP_B
+/* 1010 1101 0101 */ TABDECL(OP_B), // OP_B
+/* 1010 1101 0110 */ TABDECL(OP_B), // OP_B
+/* 1010 1101 0111 */ TABDECL(OP_B), // OP_B
+/* 1010 1101 1000 */ TABDECL(OP_B), // OP_B
+/* 1010 1101 1001 */ TABDECL(OP_B), // OP_B
+/* 1010 1101 1010 */ TABDECL(OP_B), // OP_B
+/* 1010 1101 1011 */ TABDECL(OP_B), // OP_B
+/* 1010 1101 1100 */ TABDECL(OP_B), // OP_B
+/* 1010 1101 1101 */ TABDECL(OP_B), // OP_B
+/* 1010 1101 1110 */ TABDECL(OP_B), // OP_B
+/* 1010 1101 1111 */ TABDECL(OP_B), // OP_B
+
+/* 1010 1110 0000 */ TABDECL(OP_B), // OP_B
+/* 1010 1110 0001 */ TABDECL(OP_B), // OP_B
+/* 1010 1110 0010 */ TABDECL(OP_B), // OP_B
+/* 1010 1110 0011 */ TABDECL(OP_B), // OP_B
+/* 1010 1110 0100 */ TABDECL(OP_B), // OP_B
+/* 1010 1110 0101 */ TABDECL(OP_B), // OP_B
+/* 1010 1110 0110 */ TABDECL(OP_B), // OP_B
+/* 1010 1110 0111 */ TABDECL(OP_B), // OP_B
+/* 1010 1110 1000 */ TABDECL(OP_B), // OP_B
+/* 1010 1110 1001 */ TABDECL(OP_B), // OP_B
+/* 1010 1110 1010 */ TABDECL(OP_B), // OP_B
+/* 1010 1110 1011 */ TABDECL(OP_B), // OP_B
+/* 1010 1110 1100 */ TABDECL(OP_B), // OP_B
+/* 1010 1110 1101 */ TABDECL(OP_B), // OP_B
+/* 1010 1110 1110 */ TABDECL(OP_B), // OP_B
+/* 1010 1110 1111 */ TABDECL(OP_B), // OP_B
+
+/* 1010 1111 0000 */ TABDECL(OP_B), // OP_B
+/* 1010 1111 0001 */ TABDECL(OP_B), // OP_B
+/* 1010 1111 0010 */ TABDECL(OP_B), // OP_B
+/* 1010 1111 0011 */ TABDECL(OP_B), // OP_B
+/* 1010 1111 0100 */ TABDECL(OP_B), // OP_B
+/* 1010 1111 0101 */ TABDECL(OP_B), // OP_B
+/* 1010 1111 0110 */ TABDECL(OP_B), // OP_B
+/* 1010 1111 0111 */ TABDECL(OP_B), // OP_B
+/* 1010 1111 1000 */ TABDECL(OP_B), // OP_B
+/* 1010 1111 1001 */ TABDECL(OP_B), // OP_B
+/* 1010 1111 1010 */ TABDECL(OP_B), // OP_B
+/* 1010 1111 1011 */ TABDECL(OP_B), // OP_B
+/* 1010 1111 1100 */ TABDECL(OP_B), // OP_B
+/* 1010 1111 1101 */ TABDECL(OP_B), // OP_B
+/* 1010 1111 1110 */ TABDECL(OP_B), // OP_B
+/* 1010 1111 1111 */ TABDECL(OP_B), // OP_B
+
+/* 1011 0000 0000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0000 0001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0000 0010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0000 0011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0000 0100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0000 0101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0000 0110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0000 0111 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0000 1000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0000 1001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0000 1010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0000 1011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0000 1100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0000 1101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0000 1110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0000 1111 */ TABDECL(OP_BL), // OP_BL
+
+/* 1011 0001 0000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0001 0001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0001 0010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0001 0011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0001 0100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0001 0101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0001 0110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0001 0111 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0001 1000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0001 1001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0001 1010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0001 1011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0001 1100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0001 1101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0001 1110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0001 1111 */ TABDECL(OP_BL), // OP_BL
+
+/* 1011 0010 0000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0010 0001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0010 0010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0010 0011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0010 0100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0010 0101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0010 0110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0010 0111 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0010 1000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0010 1001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0010 1010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0010 1011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0010 1100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0010 1101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0010 1110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0010 1111 */ TABDECL(OP_BL), // OP_BL
+
+/* 1011 0011 0000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0011 0001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0011 0010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0011 0011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0011 0100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0011 0101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0011 0110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0011 0111 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0011 1000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0011 1001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0011 1010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0011 1011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0011 1100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0011 1101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0011 1110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0011 1111 */ TABDECL(OP_BL), // OP_BL
+
+/* 1011 0100 0000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0100 0001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0100 0010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0100 0011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0100 0100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0100 0101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0100 0110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0100 0111 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0100 1000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0100 1001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0100 1010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0100 1011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0100 1100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0100 1101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0100 1110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0100 1111 */ TABDECL(OP_BL), // OP_BL
+
+/* 1011 0101 0000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0101 0001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0101 0010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0101 0011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0101 0100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0101 0101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0101 0110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0101 0111 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0101 1000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0101 1001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0101 1010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0101 1011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0101 1100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0101 1101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0101 1110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0101 1111 */ TABDECL(OP_BL), // OP_BL
+
+/* 1011 0110 0000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0110 0001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0110 0010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0110 0011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0110 0100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0110 0101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0110 0110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0110 0111 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0110 1000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0110 1001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0110 1010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0110 1011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0110 1100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0110 1101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0110 1110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0110 1111 */ TABDECL(OP_BL), // OP_BL
+
+/* 1011 0111 0000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0111 0001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0111 0010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0111 0011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0111 0100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0111 0101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0111 0110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0111 0111 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0111 1000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0111 1001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0111 1010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0111 1011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0111 1100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0111 1101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0111 1110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 0111 1111 */ TABDECL(OP_BL), // OP_BL
+
+/* 1011 1000 0000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1000 0001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1000 0010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1000 0011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1000 0100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1000 0101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1000 0110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1000 0111 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1000 1000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1000 1001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1000 1010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1000 1011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1000 1100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1000 1101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1000 1110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1000 1111 */ TABDECL(OP_BL), // OP_BL
+
+/* 1011 1001 0000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1001 0001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1001 0010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1001 0011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1001 0100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1001 0101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1001 0110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1001 0111 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1001 1000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1001 1001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1001 1010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1001 1011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1001 1100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1001 1101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1001 1110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1001 1111 */ TABDECL(OP_BL), // OP_BL
+
+/* 1011 1010 0000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1010 0001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1010 0010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1010 0011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1010 0100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1010 0101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1010 0110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1010 0111 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1010 1000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1010 1001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1010 1010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1010 1011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1010 1100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1010 1101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1010 1110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1010 1111 */ TABDECL(OP_BL), // OP_BL
+
+/* 1011 1011 0000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1011 0001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1011 0010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1011 0011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1011 0100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1011 0101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1011 0110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1011 0111 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1011 1000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1011 1001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1011 1010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1011 1011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1011 1100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1011 1101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1011 1110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1011 1111 */ TABDECL(OP_BL), // OP_BL
+
+/* 1011 1100 0000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1100 0001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1100 0010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1100 0011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1100 0100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1100 0101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1100 0110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1100 0111 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1100 1000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1100 1001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1100 1010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1100 1011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1100 1100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1100 1101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1100 1110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1100 1111 */ TABDECL(OP_BL), // OP_BL
+
+/* 1011 1101 0000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1101 0001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1101 0010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1101 0011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1101 0100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1101 0101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1101 0110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1101 0111 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1101 1000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1101 1001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1101 1010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1101 1011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1101 1100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1101 1101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1101 1110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1101 1111 */ TABDECL(OP_BL), // OP_BL
+
+/* 1011 1110 0000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1110 0001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1110 0010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1110 0011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1110 0100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1110 0101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1110 0110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1110 0111 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1110 1000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1110 1001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1110 1010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1110 1011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1110 1100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1110 1101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1110 1110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1110 1111 */ TABDECL(OP_BL), // OP_BL
+
+/* 1011 1111 0000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1111 0001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1111 0010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1111 0011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1111 0100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1111 0101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1111 0110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1111 0111 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1111 1000 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1111 1001 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1111 1010 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1111 1011 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1111 1100 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1111 1101 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1111 1110 */ TABDECL(OP_BL), // OP_BL
+/* 1011 1111 1111 */ TABDECL(OP_BL), // OP_BL
+
+/* 1100 0000 0000 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0000 0001 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0000 0010 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0000 0011 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0000 0100 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0000 0101 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0000 0110 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0000 0111 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0000 1000 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0000 1001 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0000 1010 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0000 1011 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0000 1100 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0000 1101 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0000 1110 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0000 1111 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+
+/* 1100 0001 0000 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0001 0001 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0001 0010 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0001 0011 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0001 0100 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0001 0101 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0001 0110 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0001 0111 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0001 1000 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0001 1001 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0001 1010 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0001 1011 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0001 1100 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0001 1101 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0001 1110 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0001 1111 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+
+/* 1100 0010 0000 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0010 0001 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0010 0010 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0010 0011 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0010 0100 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0010 0101 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0010 0110 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0010 0111 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0010 1000 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0010 1001 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0010 1010 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0010 1011 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0010 1100 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0010 1101 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0010 1110 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0010 1111 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+
+/* 1100 0011 0000 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0011 0001 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0011 0010 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0011 0011 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0011 0100 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0011 0101 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0011 0110 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0011 0111 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0011 1000 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0011 1001 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0011 1010 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0011 1011 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0011 1100 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0011 1101 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0011 1110 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0011 1111 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+
+/* 1100 0100 0000 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0100 0001 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0100 0010 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0100 0011 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0100 0100 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0100 0101 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0100 0110 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0100 0111 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0100 1000 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0100 1001 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0100 1010 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0100 1011 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0100 1100 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0100 1101 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0100 1110 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 0100 1111 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+
+/* 1100 0101 0000 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0101 0001 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0101 0010 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0101 0011 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0101 0100 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0101 0101 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0101 0110 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0101 0111 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0101 1000 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0101 1001 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0101 1010 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0101 1011 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0101 1100 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0101 1101 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0101 1110 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 0101 1111 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+
+/* 1100 0110 0000 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0110 0001 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0110 0010 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0110 0011 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0110 0100 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0110 0101 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0110 0110 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0110 0111 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0110 1000 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0110 1001 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0110 1010 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0110 1011 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0110 1100 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0110 1101 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0110 1110 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+/* 1100 0110 1111 */ TABDECL(OP_STC_M_POSTIND), // OP_STC_M_POSTIND
+
+/* 1100 0111 0000 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0111 0001 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0111 0010 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0111 0011 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0111 0100 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0111 0101 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0111 0110 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0111 0111 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0111 1000 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0111 1001 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0111 1010 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0111 1011 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0111 1100 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0111 1101 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0111 1110 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+/* 1100 0111 1111 */ TABDECL(OP_LDC_M_POSTIND), // OP_LDC_M_POSTIND
+
+/* 1100 1000 0000 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1000 0001 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1000 0010 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1000 0011 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1000 0100 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1000 0101 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1000 0110 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1000 0111 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1000 1000 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1000 1001 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1000 1010 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1000 1011 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1000 1100 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1000 1101 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1000 1110 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1000 1111 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+
+/* 1100 1001 0000 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1001 0001 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1001 0010 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1001 0011 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1001 0100 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1001 0101 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1001 0110 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1001 0111 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1001 1000 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1001 1001 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1001 1010 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1001 1011 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1001 1100 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1001 1101 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1001 1110 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1001 1111 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+
+/* 1100 1010 0000 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1010 0001 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1010 0010 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1010 0011 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1010 0100 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1010 0101 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1010 0110 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1010 0111 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1010 1000 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1010 1001 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1010 1010 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1010 1011 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1010 1100 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1010 1101 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1010 1110 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1010 1111 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+
+/* 1100 1011 0000 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1011 0001 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1011 0010 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1011 0011 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1011 0100 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1011 0101 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1011 0110 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1011 0111 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1011 1000 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1011 1001 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1011 1010 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1011 1011 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1011 1100 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1011 1101 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1011 1110 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1011 1111 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+
+/* 1100 1100 0000 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1100 0001 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1100 0010 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1100 0011 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1100 0100 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1100 0101 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1100 0110 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1100 0111 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1100 1000 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1100 1001 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1100 1010 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1100 1011 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1100 1100 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1100 1101 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1100 1110 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+/* 1100 1100 1111 */ TABDECL(OP_STC_OPTION), // OP_STC_OPTION
+
+/* 1100 1101 0000 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1101 0001 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1101 0010 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1101 0011 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1101 0100 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1101 0101 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1101 0110 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1101 0111 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1101 1000 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1101 1001 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1101 1010 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1101 1011 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1101 1100 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1101 1101 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1101 1110 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+/* 1100 1101 1111 */ TABDECL(OP_LDC_OPTION), // OP_LDC_OPTION
+
+/* 1100 1110 0000 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1110 0001 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1110 0010 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1110 0011 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1110 0100 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1110 0101 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1110 0110 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1110 0111 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1110 1000 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1110 1001 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1110 1010 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1110 1011 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1110 1100 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1110 1101 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1110 1110 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+/* 1100 1110 1111 */ TABDECL(OP_STC_P_POSTIND), // OP_STC_P_POSTIND
+
+/* 1100 1111 0000 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1111 0001 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1111 0010 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1111 0011 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1111 0100 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1111 0101 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1111 0110 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1111 0111 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1111 1000 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1111 1001 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1111 1010 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1111 1011 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1111 1100 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1111 1101 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1111 1110 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+/* 1100 1111 1111 */ TABDECL(OP_LDC_P_POSTIND), // OP_LDC_P_POSTIND
+
+/* 1101 0000 0000 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0000 0001 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0000 0010 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0000 0011 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0000 0100 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0000 0101 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0000 0110 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0000 0111 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0000 1000 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0000 1001 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0000 1010 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0000 1011 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0000 1100 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0000 1101 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0000 1110 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0000 1111 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+
+/* 1101 0001 0000 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0001 0001 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0001 0010 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0001 0011 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0001 0100 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0001 0101 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0001 0110 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0001 0111 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0001 1000 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0001 1001 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0001 1010 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0001 1011 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0001 1100 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0001 1101 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0001 1110 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0001 1111 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+
+/* 1101 0010 0000 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0010 0001 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0010 0010 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0010 0011 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0010 0100 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0010 0101 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0010 0110 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0010 0111 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0010 1000 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0010 1001 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0010 1010 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0010 1011 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0010 1100 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0010 1101 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0010 1110 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0010 1111 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+
+/* 1101 0011 0000 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0011 0001 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0011 0010 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0011 0011 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0011 0100 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0011 0101 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0011 0110 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0011 0111 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0011 1000 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0011 1001 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0011 1010 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0011 1011 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0011 1100 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0011 1101 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0011 1110 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0011 1111 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+
+/* 1101 0100 0000 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0100 0001 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0100 0010 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0100 0011 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0100 0100 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0100 0101 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0100 0110 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0100 0111 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0100 1000 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0100 1001 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0100 1010 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0100 1011 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0100 1100 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0100 1101 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0100 1110 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+/* 1101 0100 1111 */ TABDECL(OP_STC_M_IMM_OFF), // OP_STC_M_IMM_OFF
+
+/* 1101 0101 0000 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0101 0001 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0101 0010 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0101 0011 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0101 0100 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0101 0101 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0101 0110 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0101 0111 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0101 1000 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0101 1001 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0101 1010 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0101 1011 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0101 1100 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0101 1101 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0101 1110 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+/* 1101 0101 1111 */ TABDECL(OP_LDC_M_IMM_OFF), // OP_LDC_M_IMM_OFF
+
+/* 1101 0110 0000 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0110 0001 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0110 0010 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0110 0011 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0110 0100 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0110 0101 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0110 0110 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0110 0111 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0110 1000 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0110 1001 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0110 1010 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0110 1011 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0110 1100 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0110 1101 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0110 1110 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+/* 1101 0110 1111 */ TABDECL(OP_STC_M_PREIND), // OP_STC_M_PREIND
+
+/* 1101 0111 0000 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0111 0001 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0111 0010 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0111 0011 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0111 0100 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0111 0101 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0111 0110 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0111 0111 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0111 1000 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0111 1001 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0111 1010 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0111 1011 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0111 1100 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0111 1101 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0111 1110 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+/* 1101 0111 1111 */ TABDECL(OP_LDC_M_PREIND), // OP_LDC_M_PREIND
+
+/* 1101 1000 0000 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1000 0001 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1000 0010 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1000 0011 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1000 0100 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1000 0101 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1000 0110 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1000 0111 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1000 1000 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1000 1001 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1000 1010 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1000 1011 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1000 1100 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1000 1101 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1000 1110 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1000 1111 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+
+/* 1101 1001 0000 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1001 0001 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1001 0010 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1001 0011 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1001 0100 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1001 0101 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1001 0110 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1001 0111 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1001 1000 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1001 1001 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1001 1010 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1001 1011 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1001 1100 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1001 1101 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1001 1110 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1001 1111 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+
+/* 1101 1010 0000 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1010 0001 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1010 0010 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1010 0011 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1010 0100 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1010 0101 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1010 0110 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1010 0111 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1010 1000 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1010 1001 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1010 1010 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1010 1011 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1010 1100 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1010 1101 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1010 1110 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1010 1111 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+
+/* 1101 1011 0000 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1011 0001 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1011 0010 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1011 0011 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1011 0100 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1011 0101 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1011 0110 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1011 0111 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1011 1000 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1011 1001 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1011 1010 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1011 1011 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1011 1100 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1011 1101 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1011 1110 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1011 1111 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+
+/* 1101 1100 0000 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1100 0001 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1100 0010 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1100 0011 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1100 0100 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1100 0101 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1100 0110 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1100 0111 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1100 1000 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1100 1001 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1100 1010 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1100 1011 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1100 1100 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1100 1101 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1100 1110 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+/* 1101 1100 1111 */ TABDECL(OP_STC_P_IMM_OFF), // OP_STC_P_IMM_OFF
+
+/* 1101 1101 0000 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1101 0001 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1101 0010 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1101 0011 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1101 0100 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1101 0101 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1101 0110 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1101 0111 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1101 1000 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1101 1001 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1101 1010 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1101 1011 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1101 1100 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1101 1101 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1101 1110 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+/* 1101 1101 1111 */ TABDECL(OP_LDC_P_IMM_OFF), // OP_LDC_P_IMM_OFF
+
+/* 1101 1110 0000 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1110 0001 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1110 0010 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1110 0011 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1110 0100 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1110 0101 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1110 0110 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1110 0111 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1110 1000 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1110 1001 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1110 1010 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1110 1011 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1110 1100 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1110 1101 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1110 1110 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+/* 1101 1110 1111 */ TABDECL(OP_STC_P_PREIND), // OP_STC_P_PREIND
+
+/* 1101 1111 0000 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1111 0001 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1111 0010 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1111 0011 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1111 0100 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1111 0101 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1111 0110 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1111 0111 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1111 1000 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1111 1001 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1111 1010 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1111 1011 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1111 1100 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1111 1101 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1111 1110 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+/* 1101 1111 1111 */ TABDECL(OP_LDC_P_PREIND), // OP_LDC_P_PREIND
+
+/* 1110 0000 0000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0000 0001 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0000 0010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0000 0011 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0000 0100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0000 0101 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0000 0110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0000 0111 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0000 1000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0000 1001 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0000 1010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0000 1011 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0000 1100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0000 1101 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0000 1110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0000 1111 */ TABDECL(OP_MCR), // OP_MCR
+
+/* 1110 0001 0000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0001 0001 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0001 0010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0001 0011 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0001 0100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0001 0101 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0001 0110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0001 0111 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0001 1000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0001 1001 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0001 1010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0001 1011 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0001 1100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0001 1101 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0001 1110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0001 1111 */ TABDECL(OP_MRC), // OP_MRC
+
+/* 1110 0010 0000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0010 0001 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0010 0010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0010 0011 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0010 0100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0010 0101 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0010 0110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0010 0111 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0010 1000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0010 1001 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0010 1010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0010 1011 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0010 1100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0010 1101 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0010 1110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0010 1111 */ TABDECL(OP_MCR), // OP_MCR
+
+/* 1110 0011 0000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0011 0001 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0011 0010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0011 0011 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0011 0100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0011 0101 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0011 0110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0011 0111 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0011 1000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0011 1001 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0011 1010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0011 1011 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0011 1100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0011 1101 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0011 1110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0011 1111 */ TABDECL(OP_MRC), // OP_MRC
+
+/* 1110 0100 0000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0100 0001 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0100 0010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0100 0011 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0100 0100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0100 0101 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0100 0110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0100 0111 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0100 1000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0100 1001 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0100 1010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0100 1011 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0100 1100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0100 1101 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0100 1110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0100 1111 */ TABDECL(OP_MCR), // OP_MCR
+
+/* 1110 0101 0000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0101 0001 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0101 0010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0101 0011 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0101 0100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0101 0101 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0101 0110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0101 0111 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0101 1000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0101 1001 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0101 1010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0101 1011 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0101 1100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0101 1101 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0101 1110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0101 1111 */ TABDECL(OP_MRC), // OP_MRC
+
+/* 1110 0110 0000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0110 0001 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0110 0010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0110 0011 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0110 0100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0110 0101 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0110 0110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0110 0111 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0110 1000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0110 1001 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0110 1010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0110 1011 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0110 1100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0110 1101 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 0110 1110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0110 1111 */ TABDECL(OP_MCR), // OP_MCR
+
+/* 1110 0111 0000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0111 0001 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0111 0010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0111 0011 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0111 0100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0111 0101 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0111 0110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0111 0111 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0111 1000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0111 1001 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0111 1010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0111 1011 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0111 1100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0111 1101 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 0111 1110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 0111 1111 */ TABDECL(OP_MRC), // OP_MRC
+
+/* 1110 1000 0000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1000 0001 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1000 0010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1000 0011 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1000 0100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1000 0101 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1000 0110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1000 0111 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1000 1000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1000 1001 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1000 1010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1000 1011 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1000 1100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1000 1101 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1000 1110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1000 1111 */ TABDECL(OP_MCR), // OP_MCR
+
+/* 1110 1001 0000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1001 0001 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1001 0010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1001 0011 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1001 0100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1001 0101 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1001 0110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1001 0111 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1001 1000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1001 1001 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1001 1010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1001 1011 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1001 1100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1001 1101 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1001 1110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1001 1111 */ TABDECL(OP_MRC), // OP_MRC
+
+/* 1110 1010 0000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1010 0001 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1010 0010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1010 0011 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1010 0100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1010 0101 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1010 0110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1010 0111 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1010 1000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1010 1001 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1010 1010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1010 1011 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1010 1100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1010 1101 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1010 1110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1010 1111 */ TABDECL(OP_MCR), // OP_MCR
+
+/* 1110 1011 0000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1011 0001 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1011 0010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1011 0011 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1011 0100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1011 0101 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1011 0110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1011 0111 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1011 1000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1011 1001 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1011 1010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1011 1011 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1011 1100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1011 1101 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1011 1110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1011 1111 */ TABDECL(OP_MRC), // OP_MRC
+
+/* 1110 1100 0000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1100 0001 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1100 0010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1100 0011 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1100 0100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1100 0101 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1100 0110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1100 0111 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1100 1000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1100 1001 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1100 1010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1100 1011 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1100 1100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1100 1101 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1100 1110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1100 1111 */ TABDECL(OP_MCR), // OP_MCR
+
+/* 1110 1101 0000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1101 0001 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1101 0010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1101 0011 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1101 0100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1101 0101 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1101 0110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1101 0111 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1101 1000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1101 1001 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1101 1010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1101 1011 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1101 1100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1101 1101 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1101 1110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1101 1111 */ TABDECL(OP_MRC), // OP_MRC
+
+/* 1110 1110 0000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1110 0001 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1110 0010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1110 0011 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1110 0100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1110 0101 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1110 0110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1110 0111 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1110 1000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1110 1001 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1110 1010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1110 1011 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1110 1100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1110 1101 */ TABDECL(OP_MCR), // OP_MCR
+/* 1110 1110 1110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1110 1111 */ TABDECL(OP_MCR), // OP_MCR
+
+/* 1110 1111 0000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1111 0001 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1111 0010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1111 0011 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1111 0100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1111 0101 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1111 0110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1111 0111 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1111 1000 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1111 1001 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1111 1010 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1111 1011 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1111 1100 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1111 1101 */ TABDECL(OP_MRC), // OP_MRC
+/* 1110 1111 1110 */ TABDECL(OP_CDP), // OP_CDP
+/* 1110 1111 1111 */ TABDECL(OP_MRC), // OP_MRC
+
+/* 1111 0000 0000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0000 0001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0000 0010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0000 0011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0000 0100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0000 0101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0000 0110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0000 0111 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0000 1000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0000 1001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0000 1010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0000 1011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0000 1100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0000 1101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0000 1110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0000 1111 */ TABDECL(OP_SWI), // OP_SWI
+
+/* 1111 0001 0000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0001 0001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0001 0010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0001 0011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0001 0100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0001 0101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0001 0110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0001 0111 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0001 1000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0001 1001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0001 1010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0001 1011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0001 1100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0001 1101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0001 1110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0001 1111 */ TABDECL(OP_SWI), // OP_SWI
+
+/* 1111 0010 0000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0010 0001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0010 0010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0010 0011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0010 0100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0010 0101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0010 0110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0010 0111 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0010 1000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0010 1001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0010 1010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0010 1011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0010 1100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0010 1101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0010 1110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0010 1111 */ TABDECL(OP_SWI), // OP_SWI
+
+/* 1111 0011 0000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0011 0001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0011 0010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0011 0011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0011 0100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0011 0101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0011 0110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0011 0111 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0011 1000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0011 1001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0011 1010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0011 1011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0011 1100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0011 1101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0011 1110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0011 1111 */ TABDECL(OP_SWI), // OP_SWI
+
+/* 1111 0100 0000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0100 0001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0100 0010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0100 0011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0100 0100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0100 0101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0100 0110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0100 0111 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0100 1000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0100 1001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0100 1010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0100 1011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0100 1100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0100 1101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0100 1110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0100 1111 */ TABDECL(OP_SWI), // OP_SWI
+
+/* 1111 0101 0000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0101 0001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0101 0010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0101 0011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0101 0100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0101 0101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0101 0110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0101 0111 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0101 1000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0101 1001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0101 1010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0101 1011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0101 1100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0101 1101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0101 1110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0101 1111 */ TABDECL(OP_SWI), // OP_SWI
+
+/* 1111 0110 0000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0110 0001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0110 0010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0110 0011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0110 0100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0110 0101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0110 0110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0110 0111 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0110 1000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0110 1001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0110 1010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0110 1011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0110 1100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0110 1101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0110 1110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0110 1111 */ TABDECL(OP_SWI), // OP_SWI
+
+/* 1111 0111 0000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0111 0001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0111 0010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0111 0011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0111 0100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0111 0101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0111 0110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0111 0111 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0111 1000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0111 1001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0111 1010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0111 1011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0111 1100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0111 1101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0111 1110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 0111 1111 */ TABDECL(OP_SWI), // OP_SWI
+
+/* 1111 1000 0000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1000 0001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1000 0010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1000 0011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1000 0100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1000 0101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1000 0110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1000 0111 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1000 1000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1000 1001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1000 1010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1000 1011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1000 1100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1000 1101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1000 1110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1000 1111 */ TABDECL(OP_SWI), // OP_SWI
+
+/* 1111 1001 0000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1001 0001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1001 0010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1001 0011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1001 0100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1001 0101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1001 0110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1001 0111 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1001 1000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1001 1001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1001 1010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1001 1011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1001 1100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1001 1101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1001 1110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1001 1111 */ TABDECL(OP_SWI), // OP_SWI
+
+/* 1111 1010 0000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1010 0001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1010 0010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1010 0011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1010 0100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1010 0101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1010 0110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1010 0111 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1010 1000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1010 1001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1010 1010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1010 1011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1010 1100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1010 1101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1010 1110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1010 1111 */ TABDECL(OP_SWI), // OP_SWI
+
+/* 1111 1011 0000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1011 0001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1011 0010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1011 0011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1011 0100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1011 0101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1011 0110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1011 0111 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1011 1000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1011 1001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1011 1010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1011 1011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1011 1100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1011 1101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1011 1110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1011 1111 */ TABDECL(OP_SWI), // OP_SWI
+
+/* 1111 1100 0000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1100 0001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1100 0010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1100 0011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1100 0100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1100 0101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1100 0110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1100 0111 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1100 1000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1100 1001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1100 1010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1100 1011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1100 1100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1100 1101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1100 1110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1100 1111 */ TABDECL(OP_SWI), // OP_SWI
+
+/* 1111 1101 0000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1101 0001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1101 0010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1101 0011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1101 0100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1101 0101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1101 0110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1101 0111 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1101 1000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1101 1001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1101 1010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1101 1011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1101 1100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1101 1101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1101 1110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1101 1111 */ TABDECL(OP_SWI), // OP_SWI
+
+/* 1111 1110 0000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1110 0001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1110 0010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1110 0011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1110 0100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1110 0101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1110 0110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1110 0111 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1110 1000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1110 1001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1110 1010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1110 1011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1110 1100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1110 1101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1110 1110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1110 1111 */ TABDECL(OP_SWI), // OP_SWI
+
+/* 1111 1111 0000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1111 0001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1111 0010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1111 0011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1111 0100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1111 0101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1111 0110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1111 0111 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1111 1000 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1111 1001 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1111 1010 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1111 1011 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1111 1100 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1111 1101 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1111 1110 */ TABDECL(OP_SWI), // OP_SWI
+/* 1111 1111 1111 */ TABDECL(OP_SWI), // OP_SWI
+
+
--- /dev/null
+++ b/src/in_2sf/desmume/instructions.h
@@ -1,1 +1,28 @@
+/* Copyright (C) 2006 yopyop
+ Copyright (C) 2012 DeSmuME team
+ This file is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This file is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with the this software. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef _INSTRUCIONS_H_
+#define _INSTRUCIONS_H_
+
+typedef uint32_t (FASTCALL *OpFunc)(const uint32_t i);
+extern const OpFunc arm_instructions_set[2][4096];
+extern const char* arm_instruction_names[4096];
+extern const OpFunc thumb_instructions_set[2][1024];
+extern const char* thumb_instruction_names[1024];
+
+#endif
+
--- a/src/in_2sf/desmume/matrix.h
+++ b/src/in_2sf/desmume/matrix.h
@@ -21,320 +21,47 @@
#include <cmath>
#include <cstring>
-
#include "types.h"
#include "mem.h"
-
-/*#ifdef __SSE__
-#include <xmmintrin.h>
-#endif*/
#ifdef __SSE2__
#include <emmintrin.h>
#endif
-/*struct MatrixStack
-{
- MatrixStack(int size, int type);
- int32_t *matrix;
- int32_t position;
- int32_t size;
- uint8_t type;
-};*/
-
-//void MatrixInit(float *matrix);
-//void MatrixInit(int32_t *matrix);
-
-//In order to conditionally use these asm optimized functions in visual studio
-//without having to make new build types to exclude the assembly files.
-//a bit sloppy, but there aint much to it
-
-//float MatrixGetMultipliedIndex (int index, float *matrix, float *rightMatrix);
-//int32_t MatrixGetMultipliedIndex (int index, int32_t *matrix, int32_t *rightMatrix);
-//void MatrixSet (float *matrix, int x, int y, float value);
-//void MatrixCopy (float * matrixDST, const float * matrixSRC);
-//void MatrixCopy (int32_t * matrixDST, const int32_t * matrixSRC);
-//int MatrixCompare (const float * matrixDST, const float * matrixSRC);
-//void MatrixIdentity (float *matrix);
-//void MatrixIdentity (int32_t *matrix);
-
-//void MatrixTranspose (float *matrix);
-//void MatrixStackInit (MatrixStack *stack);
-//void MatrixStackSetMaxSize (MatrixStack *stack, int size);
-//void MatrixStackPushMatrix (MatrixStack *stack, const int32_t *ptr);
-//void MatrixStackPopMatrix (int32_t *mtxCurr, MatrixStack *stack, int size);
-//int32_t* MatrixStackGetPos (MatrixStack *stack, int pos);
-//int32_t* MatrixStackGet (MatrixStack *stack);
-//void MatrixStackLoadMatrix (MatrixStack *stack, int pos, const int32_t *ptr);
-
-//void Vector2Copy(float *dst, const float *src);
-//void Vector2Add(float *dst, const float *src);
-//void Vector2Subtract(float *dst, const float *src);
-//float Vector2Dot(const float *a, const float *b);
-//float Vector2Cross(const float *a, const float *b);
-
-//float Vector3Dot(const float *a, const float *b);
-//void Vector3Cross(float* dst, const float *a, const float *b);
-//float Vector3Length(const float *a);
-//void Vector3Add(float *dst, const float *src);
-//void Vector3Subtract(float *dst, const float *src);
-//void Vector3Scale(float *dst, const float scale);
-//void Vector3Copy(float *dst, const float *src);
-//void Vector3Normalize(float *dst);
-
-//void Vector4Copy(float *dst, const float *src);
-
-//these functions are an unreliable, inaccurate floor.
-//it should only be used for positive numbers
-//this isnt as fast as it could be if we used a visual c++ intrinsic, but those appear not to be universally available
+// these functions are an unreliable, inaccurate floor.
+// it should only be used for positive numbers
+// this isnt as fast as it could be if we used a visual c++ intrinsic, but those appear not to be universally available
inline uint32_t u32floor(float f)
{
#ifdef __SSE2__
- return (uint32_t)_mm_cvtt_ss2si(_mm_set_ss(f));
+ return static_cast<uint32_t>(_mm_cvtt_ss2si(_mm_set_ss(f)));
#else
- return (uint32_t)f;
+ return static_cast<uint32_t>(f);
#endif
}
inline uint32_t u32floor(double d)
{
#ifdef __SSE2__
- return (uint32_t)_mm_cvttsd_si32(_mm_set_sd(d));
+ return static_cast<uint32_t>(_mm_cvttsd_si32(_mm_set_sd(d)));
#else
- return (uint32_t)d;
+ return static_cast<uint32_t>(d);
#endif
}
-//same as above but works for negative values too.
-//be sure that the results are the same thing as floorf!
+// same as above but works for negative values too.
+// be sure that the results are the same thing as floorf!
inline int32_t s32floor(float f)
{
#ifdef __SSE2__
- return _mm_cvtss_si32( _mm_add_ss(_mm_set_ss(-0.5f),_mm_add_ss(_mm_set_ss(f), _mm_set_ss(f))) ) >> 1;
+ return _mm_cvtss_si32(_mm_add_ss(_mm_set_ss(-0.5f),_mm_add_ss(_mm_set_ss(f), _mm_set_ss(f)))) >> 1;
#else
- return (int32_t)floorf(f);
+ return static_cast<int32_t>(floorf(f));
#endif
}
inline int32_t s32floor(double d)
{
- return s32floor((float)d);
+ return s32floor(static_cast<float>(d));
}
-
-//switched SSE2 functions
-//-------------
-#ifdef __SSE2__
-
-/*template<int NUM>
-inline void memset_u16_le(void* dst, uint16_t val)
-{
- uint32_t u32val;
- //just for the endian safety
- T1WriteWord((uint8_t*)&u32val,0,val);
- T1WriteWord((uint8_t*)&u32val,2,val);
- ////const __m128i temp = _mm_set_epi32(u32val,u32val,u32val,u32val);
-
-#if defined(__GNUC__) || defined(__INTEL_COMPILER)
- const __m128i temp = _mm_set_epi32(u32val,u32val,u32val,u32val);
- MACRODO_N(NUM/8,_mm_store_si128((__m128i*)((uint8_t*)dst+(X)*16), temp));
-#else
- __m128 temp; temp.m128_i32[0] = u32val;
- //MACRODO_N(NUM/8,_mm_store_si128((__m128i*)((uint8_t*)dst+(X)*16), temp));
- MACRODO_N(NUM/8,_mm_store_ps1((float*)((uint8_t*)dst+(X)*16), temp));
-#endif
-}*/
-
-#else //no sse2
-
-/*template<int NUM>
-static inline void memset_u16_le(void* dst, uint16_t val)
-{
- for(int i=0;i<NUM;i++)
- T1WriteWord((uint8_t*)dst,i<<1,val);
-}*/
#endif
-// NOSSE version always used in gfx3d.cpp
-//void _NOSSE_MatrixMultVec4x4 (const float *matrix, float *vecPtr);
-//void MatrixMultVec3x3_fixed(const int32_t *matrix, int32_t *vecPtr);
-
-//---------------------------
-//switched SSE functions
-#ifdef __SSE__
-
-/*struct SSE_MATRIX
-{
- SSE_MATRIX(const float *matrix)
- : row0(_mm_load_ps(matrix))
- , row1(_mm_load_ps(matrix+4))
- , row2(_mm_load_ps(matrix+8))
- , row3(_mm_load_ps(matrix+12))
- {}
-
- union {
- __m128 rows[4];
- struct { __m128 row0; __m128 row1; __m128 row2; __m128 row3; };
- };
-
-};*/
-
-/*inline __m128 _util_MatrixMultVec4x4_(const SSE_MATRIX &mat, __m128 vec)
-{
- __m128 xmm5 = _mm_shuffle_ps(vec, vec, B8(01010101));
- __m128 xmm6 = _mm_shuffle_ps(vec, vec, B8(10101010));
- __m128 xmm7 = _mm_shuffle_ps(vec, vec, B8(11111111));
- __m128 xmm4 = _mm_shuffle_ps(vec, vec, B8(00000000));
-
- xmm4 = _mm_mul_ps(xmm4,mat.row0);
- xmm5 = _mm_mul_ps(xmm5,mat.row1);
- xmm6 = _mm_mul_ps(xmm6,mat.row2);
- xmm7 = _mm_mul_ps(xmm7,mat.row3);
- xmm4 = _mm_add_ps(xmm4,xmm5);
- xmm4 = _mm_add_ps(xmm4,xmm6);
- xmm4 = _mm_add_ps(xmm4,xmm7);
- return xmm4;
-}*/
-
-/*inline void MatrixMultiply(float * matrix, const float * rightMatrix)
-{
- //this seems to generate larger code, including many movaps, but maybe it is less harsh on the registers than the
- //more hand-tailored approach
- __m128 row0 = _util_MatrixMultVec4x4_((SSE_MATRIX)matrix,_mm_load_ps(rightMatrix));
- __m128 row1 = _util_MatrixMultVec4x4_((SSE_MATRIX)matrix,_mm_load_ps(rightMatrix+4));
- __m128 row2 = _util_MatrixMultVec4x4_((SSE_MATRIX)matrix,_mm_load_ps(rightMatrix+8));
- __m128 row3 = _util_MatrixMultVec4x4_((SSE_MATRIX)matrix,_mm_load_ps(rightMatrix+12));
- _mm_store_ps(matrix,row0);
- _mm_store_ps(matrix+4,row1);
- _mm_store_ps(matrix+8,row2);
- _mm_store_ps(matrix+12,row3);
-}*/
-
-
-
-/*inline void MatrixMultVec4x4(const float *matrix, float *vecPtr)
-{
- _mm_store_ps(vecPtr,_util_MatrixMultVec4x4_((SSE_MATRIX)matrix,_mm_load_ps(vecPtr)));
-}*/
-
-/*inline void MatrixMultVec4x4_M2(const float *matrix, float *vecPtr)
-{
- //there are hardly any gains from merging these manually
- MatrixMultVec4x4(matrix+16,vecPtr);
- MatrixMultVec4x4(matrix,vecPtr);
-}*/
-
-/*inline void MatrixMultVec3x3(const float * matrix, float * vecPtr)
-{
- const __m128 vec = _mm_load_ps(vecPtr);
-
- __m128 xmm5 = _mm_shuffle_ps(vec, vec, B8(01010101));
- __m128 xmm6 = _mm_shuffle_ps(vec, vec, B8(10101010));
- __m128 xmm4 = _mm_shuffle_ps(vec, vec, B8(00000000));
-
- const SSE_MATRIX mat(matrix);
-
- xmm4 = _mm_mul_ps(xmm4,mat.row0);
- xmm5 = _mm_mul_ps(xmm5,mat.row1);
- xmm6 = _mm_mul_ps(xmm6,mat.row2);
- xmm4 = _mm_add_ps(xmm4,xmm5);
- xmm4 = _mm_add_ps(xmm4,xmm6);
-
- _mm_store_ps(vecPtr,xmm4);
-}*/
-
-/*inline void MatrixTranslate(float *matrix, const float *ptr)
-{
- __m128 xmm4 = _mm_load_ps(ptr);
- __m128 xmm5 = _mm_shuffle_ps(xmm4, xmm4, B8(01010101));
- __m128 xmm6 = _mm_shuffle_ps(xmm4, xmm4, B8(10101010));
- xmm4 = _mm_shuffle_ps(xmm4, xmm4, B8(00000000));
-
- xmm4 = _mm_mul_ps(xmm4,_mm_load_ps(matrix));
- xmm5 = _mm_mul_ps(xmm5,_mm_load_ps(matrix+4));
- xmm6 = _mm_mul_ps(xmm6,_mm_load_ps(matrix+8));
- xmm4 = _mm_add_ps(xmm4,xmm5);
- xmm4 = _mm_add_ps(xmm4,xmm6);
- xmm4 = _mm_add_ps(xmm4,_mm_load_ps(matrix+12));
- _mm_store_ps(matrix+12,xmm4);
-}*/
-
-/*inline void MatrixScale(float *matrix, const float *ptr)
-{
- __m128 xmm4 = _mm_load_ps(ptr);
- __m128 xmm5 = _mm_shuffle_ps(xmm4, xmm4, B8(01010101));
- __m128 xmm6 = _mm_shuffle_ps(xmm4, xmm4, B8(10101010));
- xmm4 = _mm_shuffle_ps(xmm4, xmm4, B8(00000000));
-
- xmm4 = _mm_mul_ps(xmm4,_mm_load_ps(matrix));
- xmm5 = _mm_mul_ps(xmm5,_mm_load_ps(matrix+4));
- xmm6 = _mm_mul_ps(xmm6,_mm_load_ps(matrix+8));
- _mm_store_ps(matrix,xmm4);
- _mm_store_ps(matrix+4,xmm5);
- _mm_store_ps(matrix+8,xmm6);
-}*/
-
-/*template<int NUM_ROWS>
-inline void vector_fix2float(float* matrix, const float divisor)
-{
- CTASSERT(NUM_ROWS==3 || NUM_ROWS==4);
-
- const __m128 val = _mm_set_ps1(divisor);
-
- _mm_store_ps(matrix,_mm_div_ps(_mm_load_ps(matrix),val));
- _mm_store_ps(matrix+4,_mm_div_ps(_mm_load_ps(matrix+4),val));
- _mm_store_ps(matrix+8,_mm_div_ps(_mm_load_ps(matrix+8),val));
- if(NUM_ROWS==4)
- _mm_store_ps(matrix+12,_mm_div_ps(_mm_load_ps(matrix+12),val));
-}*/
-
-//WARNING: I do not think this is as fast as a memset, for some reason.
-//at least in vc2005 with sse enabled. better figure out why before using it
-/*template<int NUM>
-static inline void memset_u8(void* _dst, uint8_t val)
-{
- memset(_dst,val,NUM);
- //const uint8_t* dst = (uint8_t*)_dst;
- //uint32_t u32val = (val<<24)|(val<<16)|(val<<8)|val;
- //const __m128i temp = _mm_set_epi32(u32val,u32val,u32val,u32val);
- //MACRODO_N(NUM/16,_mm_store_si128((__m128i*)(dst+(X)*16), temp));
-}*/
-
-#else //no sse
-
-//void MatrixMultVec4x4 (const float *matrix, float *vecPtr);
-//void MatrixMultVec3x3(const float * matrix, float * vecPtr);
-//void MatrixMultiply(float * matrix, const float * rightMatrix);
-//void MatrixTranslate(float *matrix, const float *ptr);
-//void MatrixScale(float * matrix, const float * ptr);
-
-/*inline void MatrixMultVec4x4_M2(const float *matrix, float *vecPtr)
-{
- //there are hardly any gains from merging these manually
- MatrixMultVec4x4(matrix+16,vecPtr);
- MatrixMultVec4x4(matrix,vecPtr);
-}*/
-
-/*template<int NUM_ROWS>
-inline void vector_fix2float(float* matrix, const float divisor)
-{
- for(int i=0;i<NUM_ROWS*4;i++)
- matrix[i] /= divisor;
-}*/
-
-/*template<int NUM>
-static inline void memset_u8(void* dst, uint8_t val)
-{
- memset(dst,val,NUM);
-}*/
-
-#endif //switched SSE functions
-
-//void MatrixMultVec4x4 (const int32_t *matrix, int32_t *vecPtr);
-
-//void MatrixMultVec4x4_M2(const int32_t *matrix, int32_t *vecPtr);
-
-//void MatrixMultiply(int32_t* matrix, const int32_t* rightMatrix);
-//void MatrixScale(int32_t *matrix, const int32_t *ptr);
-//void MatrixTranslate(int32_t *matrix, const int32_t *ptr);
-
-#endif
-
--- a/src/in_2sf/desmume/mc.cpp
+++ b/src/in_2sf/desmume/mc.cpp
@@ -1,7 +1,7 @@
/*
Copyright (C) 2006 thoduv
Copyright (C) 2006-2007 Theo Berkau
- Copyright (C) 2008-2012 DeSmuME team
+ Copyright (C) 2008-2013 DeSmuME team
This file is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -19,167 +19,90 @@
#include <cstdlib>
#include <cstring>
-
-//#include "debug.h"
#include "types.h"
#include "mc.h"
-//#include "movie.h"
#include "readwrite.h"
#include "NDSSystem.h"
-#define FW_CMD_READ 0x03
-#define FW_CMD_WRITEDISABLE 0x04
-#define FW_CMD_READSTATUS 0x05
-#define FW_CMD_WRITEENABLE 0x06
-#define FW_CMD_PAGEWRITE 0x0A
-#define FW_CMD_READ_ID 0x9F
-
-#define BM_CMD_AUTODETECT 0xFF
-#define BM_CMD_WRITESTATUS 0x01
-#define BM_CMD_WRITELOW 0x02
-#define BM_CMD_READLOW 0x03
-#define BM_CMD_WRITEDISABLE 0x04
-#define BM_CMD_READSTATUS 0x05
-#define BM_CMD_WRITEENABLE 0x06
-#define BM_CMD_WRITEHIGH 0x0A
-#define BM_CMD_READHIGH 0x0B
-
-/* FLASH*/
-#define COMM_PAGE_WRITE 0x0A
-#define COMM_PAGE_ERASE 0xDB
-#define COMM_SECTOR_ERASE 0xD8
-#define COMM_CHIP_ERASE 0xC7
-#define CARDFLASH_READ_BYTES_FAST 0x0B /* Not used*/
-#define CARDFLASH_DEEP_POWDOWN 0xB9 /* Not used*/
-#define CARDFLASH_WAKEUP 0xAB /* Not used*/
-
-//since r2203 this was 0x00.
-//but baby pals proves finally that it should be 0xFF:
-//the game reads its initial sound volumes from uninitialized data, and if it is 0, the game will be silent
-//if it is 0xFF then the game starts with its sound and music at max, as presumably it is supposed to.
-//so in r3303 I finally changed it (no$ appears definitely to initialized to 0xFF)
+static const uint8_t FW_CMD_READ = 0x03;
+static const uint8_t FW_CMD_WRITEDISABLE = 0x04;
+static const uint8_t FW_CMD_READSTATUS = 0x05;
+static const uint8_t FW_CMD_WRITEENABLE = 0x06;
+static const uint8_t FW_CMD_PAGEWRITE = 0x0A;
+static const uint8_t FW_CMD_READ_ID = 0x9F;
+
+// since r2203 this was 0x00.
+// but baby pals proves finally that it should be 0xFF:
+// the game reads its initial sound volumes from uninitialized data, and if it is 0, the game will be silent
+// if it is 0xFF then the game starts with its sound and music at max, as presumably it is supposed to.
+// so in r3303 I finally changed it (no$ appears definitely to initialized to 0xFF)
static const uint8_t kUninitializedSaveDataValue = 0xFF;
-static const char* kDesmumeSaveCookie = "|-DESMUME SAVE-|";
-
-static const uint32_t saveSizes[] = {512, // 4k
- 8*1024, // 64k
- 32*1024, // 512k
- 64*1024, // 1Mbit
- 256*1024, // 2Mbit
- 512*1024, // 4Mbit
- 1024*1024, // 8Mbit
- 2048*1024, // 16Mbit
- 4096*1024, // 32Mbit
- 8192*1024, // 64Mbit
- 16384*1024, // 128Mbit
- 32768*1024, // 256Mbit
- 65536*1024, // 512Mbit
- 0xFFFFFFFF};
-static const uint32_t saveSizes_count = ARRAY_SIZE(saveSizes);
+static const char *kDesmumeSaveCookie = "|-DESMUME SAVE-|";
//the lookup table from user save types to save parameters
-const int save_types[][2] = {
- {MC_TYPE_AUTODETECT,1},
- {MC_TYPE_EEPROM1,MC_SIZE_4KBITS},
- {MC_TYPE_EEPROM2,MC_SIZE_64KBITS},
- {MC_TYPE_EEPROM2,MC_SIZE_512KBITS},
- {MC_TYPE_FRAM,MC_SIZE_256KBITS},
- {MC_TYPE_FLASH,MC_SIZE_2MBITS},
- {MC_TYPE_FLASH,MC_SIZE_4MBITS},
- {MC_TYPE_FLASH,MC_SIZE_8MBITS},
- {MC_TYPE_FLASH,MC_SIZE_16MBITS},
- {MC_TYPE_FLASH,MC_SIZE_32MBITS},
- {MC_TYPE_FLASH,MC_SIZE_64MBITS},
- {MC_TYPE_FLASH,MC_SIZE_128MBITS},
- {MC_TYPE_FLASH,MC_SIZE_256MBITS},
- {MC_TYPE_FLASH,MC_SIZE_512MBITS}
+const SAVE_TYPE save_types[] =
+{
+ {"Autodetect", MC_TYPE_AUTODETECT, 1},
+ {"EEPROM 4kbit", MC_TYPE_EEPROM1, MC_SIZE_4KBITS},
+ {"EEPROM 64kbit", MC_TYPE_EEPROM2, MC_SIZE_64KBITS},
+ {"EEPROM 512kbit", MC_TYPE_EEPROM2, MC_SIZE_512KBITS},
+ {"FRAM 256kbit", MC_TYPE_FRAM, MC_SIZE_256KBITS},
+ {"FLASH 2Mbit", MC_TYPE_FLASH, MC_SIZE_2MBITS},
+ {"FLASH 4Mbit", MC_TYPE_FLASH, MC_SIZE_4MBITS},
+ {"FLASH 8Mbit", MC_TYPE_FLASH, MC_SIZE_8MBITS},
+ {"FLASH 16Mbit", MC_TYPE_FLASH, MC_SIZE_16MBITS},
+ {"FLASH 32Mbit", MC_TYPE_FLASH, MC_SIZE_32MBITS},
+ {"FLASH 64Mbit", MC_TYPE_FLASH, MC_SIZE_64MBITS},
+ {"FLASH 128Mbit", MC_TYPE_FLASH, MC_SIZE_128MBITS},
+ {"FLASH 256Mbit", MC_TYPE_FLASH, MC_SIZE_256MBITS},
+ {"FLASH 512Mbit", MC_TYPE_FLASH, MC_SIZE_512MBITS}
};
-
-/*const char *save_names[] = {
- "EEPROM 4kbit",
- "EEPROM 64kbit",
- "EEPROM 512kbit",
- "FRAM 256kbit",
- "FLASH 2Mbit",
- "FLASH 4Mbit",
- "FLASH 8Mbit",
- "FLASH 16Mbit",
- "FLASH 32Mbit",
- "FLASH 64Mbit",
- "FLASH 128Mbit",
- "FLASH 256Mbit",
- "FLASH 512Mbit"
-};*/
-
-//forces the currently selected backup type to be current
-//(can possibly be used to repair poorly chosen save types discovered late in gameplay i.e. pokemon gamers)
-/*void backup_forceManualBackupType()
-{
- MMU_new.backupDevice.forceManualBackupType();
-}*/
-
-/*void backup_setManualBackupType(int type)
-{
- CommonSettings.manualBackupType = type;
-}*/
-
void mc_init(memory_chip_t *mc, int type)
{
- mc->com = 0;
- mc->addr = 0;
- mc->addr_shift = 0;
- mc->data.clear();
- mc->size = 0;
- mc->write_enable = false;
- mc->writeable_buffer = false;
- mc->type = type;
- mc->autodetectsize = 0;
-
- switch(mc->type)
- {
- case MC_TYPE_EEPROM1:
- mc->addr_size = 1;
- break;
- case MC_TYPE_EEPROM2:
- case MC_TYPE_FRAM:
- mc->addr_size = 2;
- break;
- case MC_TYPE_FLASH:
- mc->addr_size = 3;
- break;
- default: break;
- }
+ mc->com = 0;
+ mc->addr = 0;
+ mc->addr_shift = 0;
+ mc->data.clear();
+ mc->size = 0;
+ mc->write_enable = false;
+ mc->writeable_buffer = false;
+ mc->type = type;
+ mc->autodetectsize = 0;
+
+ switch (mc->type)
+ {
+ case MC_TYPE_EEPROM1:
+ mc->addr_size = 1;
+ break;
+ case MC_TYPE_EEPROM2:
+ case MC_TYPE_FRAM:
+ mc->addr_size = 2;
+ break;
+ case MC_TYPE_FLASH:
+ mc->addr_size = 3;
+ }
}
uint8_t *mc_alloc(memory_chip_t *mc, uint32_t size)
{
- /*uint8_t *buffer;
- buffer = new uint8_t[size];
- memset(buffer,0,size);*/
-
- //if (mc->data) delete [] mc->data;
mc->data.clear();
- //mc->data = buffer;
- //if(!buffer) { return NULL; }
mc->data.resize(size, 0);
mc->size = size;
mc->writeable_buffer = true;
- //return buffer;
- return NULL;
+ return nullptr;
}
void mc_free(memory_chip_t *mc)
{
- //if(mc->data) delete[] mc->data;
mc->data.clear();
- mc_init(mc, 0);
+ mc_init(mc, 0);
}
void fw_reset_com(memory_chip_t *mc)
{
- if(mc->com == FW_CMD_PAGEWRITE)
+ if (mc->com == FW_CMD_PAGEWRITE)
{
if (mc->fp)
{
@@ -196,9 +119,9 @@
FILE *fp = fopen(mc->userfile, "wb");
if (fp)
{
- if (fwrite(&mc->data[0x3FF00], 1, 0x100, fp) == 0x100) // User Settings
+ if (fwrite(&mc->data[0x3FF00], 1, 0x100, fp) == 0x100) // User Settings
{
- if (fwrite(&mc->data[0x0002A], 1, 0x1D6, fp) == 0x1D6) // WiFi Settings
+ if (fwrite(&mc->data[0x0002A], 1, 0x1D6, fp) == 0x1D6) // WiFi Settings
{
if (fwrite(&mc->data[0x3FA00], 1, 0x300, fp) == 0x300) // WiFi AP Settings
printf(" - done\n");
@@ -220,478 +143,173 @@
uint8_t fw_transfer(memory_chip_t *mc, uint8_t data)
{
- if(mc->com == FW_CMD_READ || mc->com == FW_CMD_PAGEWRITE) /* check if we are in a command that needs 3 bytes address */
- {
- if(mc->addr_shift > 0) /* if we got a complete address */
- {
- mc->addr_shift--;
+ if (mc->com == FW_CMD_READ || mc->com == FW_CMD_PAGEWRITE) /* check if we are in a command that needs 3 bytes address */
+ {
+ if (mc->addr_shift > 0) /* if we got a complete address */
+ {
+ --mc->addr_shift;
mc->addr |= data << (mc->addr_shift * 8); /* argument is a byte of address */
}
- else /* if we have received 3 bytes of address, proceed command */
- {
- switch(mc->com)
+ else /* if we have received 3 bytes of address, proceed command */
+ {
+ switch (mc->com)
{
case FW_CMD_READ:
- if(mc->addr < mc->size) /* check if we can read */
+ if (mc->addr < mc->size) /* check if we can read */
{
- data = mc->data[mc->addr]; /* return byte */
- mc->addr++; /* then increment address */
+ data = mc->data[mc->addr]; /* return byte */
+ ++mc->addr; /* then increment address */
}
break;
-
case FW_CMD_PAGEWRITE:
- if(mc->addr < mc->size)
+ if (mc->addr < mc->size)
{
- mc->data[mc->addr] = data; /* write byte */
- mc->addr++;
+ mc->data[mc->addr] = data; /* write byte */
+ ++mc->addr;
}
- break;
}
-
- }
- }
- else if(mc->com == FW_CMD_READ_ID)
- {
- switch(mc->addr)
- {
- //here is an ID string measured from an old ds fat: 62 16 00 (0x62=sanyo)
- //but we chose to use an ST from martin's ds fat string so programs might have a clue as to the firmware size:
- //20 40 12
- case 0:
- data = 0x20;
- mc->addr=1;
- break;
- case 1:
- data = 0x40; //according to gbatek this is the device ID for the flash on someone's ds fat
- mc->addr=2;
- break;
- case 2:
- data = 0x12;
- mc->addr = 0;
- break;
- }
- }
- else if(mc->com == FW_CMD_READSTATUS)
- {
+ }
+ }
+ else if (mc->com == FW_CMD_READ_ID)
+ {
+ switch (mc->addr)
+ {
+ // here is an ID string measured from an old ds fat: 62 16 00 (0x62=sanyo)
+ // but we chose to use an ST from martin's ds fat string so programs might have a clue as to the firmware size:
+ // 20 40 12
+ case 0:
+ data = 0x20;
+ mc->addr = 1;
+ break;
+ case 1:
+ data = 0x40; // according to gbatek this is the device ID for the flash on someone's ds fat
+ mc->addr = 2;
+ break;
+ case 2:
+ data = 0x12;
+ mc->addr = 0;
+ }
+ }
+ else if (mc->com == FW_CMD_READSTATUS)
return mc->write_enable ? 0x02 : 0x00;
- }
- else //finally, check if it's a new command
- {
- switch(data)
- {
- case 0: break; //nothing
+ else // finally, check if it's a new command
+ {
+ switch (data)
+ {
+ case 0:
+ break; // nothing
case FW_CMD_READ_ID:
mc->addr = 0;
mc->com = FW_CMD_READ_ID;
break;
- case FW_CMD_READ: //read command
+ case FW_CMD_READ: //read command
mc->addr = 0;
mc->addr_shift = 3;
mc->com = FW_CMD_READ;
break;
- case FW_CMD_WRITEENABLE: //enable writing
- if(mc->writeable_buffer) { mc->write_enable = true; }
- break;
-
- case FW_CMD_WRITEDISABLE: //disable writing
-
+ case FW_CMD_WRITEENABLE: //enable writing
+ if (mc->writeable_buffer)
+ mc->write_enable = true;
+ break;
+
+ case FW_CMD_WRITEDISABLE: //disable writing
mc->write_enable = false;
break;
- case FW_CMD_PAGEWRITE: //write command
- if(mc->write_enable)
+ case FW_CMD_PAGEWRITE: //write command
+ if (mc->write_enable)
{
mc->addr = 0;
mc->addr_shift = 3;
mc->com = FW_CMD_PAGEWRITE;
}
- else { data = 0; }
- break;
-
- case FW_CMD_READSTATUS: //status register command
+ else
+ data = 0;
+ break;
+
+ case FW_CMD_READSTATUS: //status register command
mc->com = FW_CMD_READSTATUS;
break;
default:
printf("Unhandled FW command: %02X\n", data);
- break;
}
}
return data;
}
-/*bool BackupDevice::save_state(EMUFILE* os)
-{
- uint32_t version = 2;
- //v0
- write32le(version,os);
- write32le(write_enable,os);
- write32le(com,os);
- write32le(addr_size,os);
- write32le(addr_counter,os);
- write32le((uint32_t)state,os);
- writebuffer(data,os);
- writebuffer(data_autodetect,os);
- //v1
- write32le(addr,os);
- //v2
- write8le(motionInitState,os);
- write8le(motionFlag,os);
- return true;
-}*/
-
-bool BackupDevice::load_state(EMUFILE* is)
-{
- uint32_t version;
- if(read32le(&version,is)!=1) return false;
- //if(version>=0)
- {
- readbool(&write_enable,is);
- read32le(&com,is);
- read32le(&addr_size,is);
- read32le(&addr_counter,is);
- uint32_t temp;
- read32le(&temp,is);
- state = (STATE)temp;
- readbuffer(data,is);
- readbuffer(data_autodetect,is);
- }
- if(version>=1)
- read32le(&addr,is);
- if(version>=2)
- {
- read8le(&motionInitState,is);
- read8le(&motionFlag,is);
- }
-
- return true;
-}
-
BackupDevice::BackupDevice()
{
- //isMovieMode = false;
- reset();
-}
-
-//due to unfortunate shortcomings in the emulator architecture,
-//at reset-time, we won't have a filename to the .dsv file.
-//so the only difference between load_rom (init) and reset is that
-//one of them saves the filename
-void BackupDevice::load_rom(const char* fn)
-{
- //isMovieMode = false;
+ this->reset();
+}
+
+// due to unfortunate shortcomings in the emulator architecture,
+// at reset-time, we won't have a filename to the .dsv file.
+// so the only difference between load_rom (init) and reset is that
+// one of them saves the filename
+void BackupDevice::load_rom(const std::string &fn)
+{
this->filename = fn;
- reset();
-}
-
-/*void BackupDevice::movie_mode()
-{
- isMovieMode = true;
- reset();
-}*/
+ this->reset();
+}
void BackupDevice::reset_hardware()
{
- write_enable = false;
- com = 0;
- addr = addr_counter = 0;
- motionInitState = MOTION_INIT_STATE_IDLE;
- motionFlag = MOTION_FLAG_NONE;
- state = DETECTING;
- flushPending = false;
- lazyFlushPending = false;
+ this->write_enable = false;
+ this->com = 0;
+ this->addr = this->addr_counter = 0;
+ this->motionInitState = MOTION_INIT_STATE_IDLE;
+ this->motionFlag = MOTION_FLAG_NONE;
+ this->state = DETECTING;
+ this->flushPending = false;
+ this->lazyFlushPending = false;
}
void BackupDevice::reset()
{
- memset(&info, 0, sizeof(info));
- reset_hardware();
- resize(0);
- data_autodetect.resize(0);
- addr_size = 0;
- loadfile();
-
- //if the user has requested a manual choice for backup type, and we havent imported a raw save file, then apply it now
- if(state == DETECTING && CommonSettings.manualBackupType != MC_TYPE_AUTODETECT)
- {
- state = RUNNING;
- int savetype = save_types[CommonSettings.manualBackupType][0];
- int savesize = save_types[CommonSettings.manualBackupType][1];
- ensure((uint32_t)savesize); //expand properly if necessary
- resize(savesize); //truncate if necessary
- addr_size = addr_size_for_old_save_type(savetype);
- //flush();
- }
-}
-
-/*void BackupDevice::close_rom()
-{
- //flush();
-}*/
-
-/*void BackupDevice::reset_command()
-{
- //printf("MC RESET\n");
- //for a performance hack, save files are only flushed after each reset command
- //(hopefully, after each page)
- if(flushPending)
- {
- //flush();
- flushPending = false;
- lazyFlushPending = false;
- }
-
- if(state == DETECTING && data_autodetect.size()>0)
- {
- //we can now safely detect the save address size
- uint32_t autodetect_size = data_autodetect.size();
-
- printf("Autodetecting with autodetect_size=%d\n",autodetect_size);
-
- const uint8_t sm64_sig[] = {0x01,0x80,0x00,0x00};
- if(autodetect_size == 4 && !memcmp(&data_autodetect[0],sm64_sig,4))
- {
- addr_size = 2;
- }
- else //detect based on rules
- switch(autodetect_size)
- {
- case 0:
- case 1:
- printf("Catastrophic error while autodetecting save type.\nIt will need to be specified manually\n");
- #ifdef _WINDOWS
- MessageBoxA(0,"Catastrophic Error Code: Camel;\nyour save type has not been autodetected correctly;\nplease report to developers",0,0);
- #endif
- addr_size = 1; //choose 1 just to keep the busted savefile from growing too big
- break;
- case 2:
- //the modern typical case for small eeproms
- addr_size = 1;
- break;
- case 3:
- //another modern typical case..
- //but unfortunately we select this case for spider-man 3, when what it meant to do was
- //present the archaic 1+2 case
- //it seems that over the hedge does this also.
- addr_size = 2;
- break;
- case 4:
- //a modern typical case
- addr_size = 3;
- break;
- default:
- //the archaic case: write the address and then some modulo-4 number of bytes
- //why modulo 4? who knows.
- addr_size = autodetect_size & 3;
- break;
- }
-
- state = RUNNING;
- data_autodetect.resize(0);
- //flush();
- }
-
- com = 0;
-}*/
-/*uint8_t BackupDevice::data_command(uint8_t val, int cpu)
-{
- //printf("MC CMD: %02X\n",val);
-
- //motion: some guessing here... hope it doesn't break anything
- if(com == BM_CMD_READLOW && motionInitState == MOTION_INIT_STATE_RECEIVED_4_B && val == 0)
- {
- motionInitState = MOTION_INIT_STATE_IDLE;
- motionFlag |= MOTION_FLAG_ENABLED;
- //return 0x04; //return 0x04 to enable motion!!!!!
- return 0; //but we return 0 to disable it! since we don't emulate it anyway
- }
-
- //if the game firmly believes we have motion support, then ignore all motion commands, since theyre not emulated.
- if(motionFlag & MOTION_FLAG_SENSORMODE)
- {
- return 0;
- }
-
- if(com == BM_CMD_READLOW || com == BM_CMD_WRITELOW)
- {
- //handle data or address
- if(state == DETECTING)
- {
- if(com == BM_CMD_WRITELOW)
- {
- printf("Unexpected backup device initialization sequence using writes!\n");
- }
-
- //just buffer the data until we're no longer detecting
- data_autodetect.push_back(val);
- val = 0;
- }
- else
- {
- if(addr_counter<addr_size)
- {
- //continue building address
- addr <<= 8;
- addr |= val;
- addr_counter++;
- //if(addr_counter==addr_size) printf("ADR: %08X\n",addr);
- }
- else
- {
- //why does tomb raider underworld access 0x180 and go clear through to 0x280?
- //should this wrap around at 0 or at 0x100?
- if(addr_size == 1) addr &= 0x1FF;
-
- //address is complete
- ensure(addr+1);
- if(com == BM_CMD_READLOW)
- {
- //printf("READ ADR: %08X\n",addr);
- val = data[addr];
- //flushPending = true; //is this a good idea? it may slow stuff down, but it is helpful for debugging
- lazyFlushPending = true; //lets do this instead
- //printf("read: %08X\n",addr);
- }
- else
- {
- if(write_enable)
- {
- //printf("WRITE ADR: %08X\n",addr);
- data[addr] = val;
- flushPending = true;
- //printf("writ: %08X\n",addr);
- }
- }
- addr++;
-
- }
- }
- }
- else if(com == BM_CMD_READSTATUS)
- {
- //handle request to read status
- //LOG("Backup Memory Read Status: %02X\n", write_enable << 1);
- return (write_enable << 1) | (3<<2);
- }
- else
- {
- //there is no current command. receive one
- switch(val)
- {
- case 0: break; //??
-
- case 0xFE:
- if(motionInitState == MOTION_INIT_STATE_IDLE) { motionInitState = MOTION_INIT_STATE_FE; return 0; }
- break;
- case 0xFD:
- if(motionInitState == MOTION_INIT_STATE_FE) { motionInitState = MOTION_INIT_STATE_FD; return 0; }
- break;
- case 0xFB:
- if(motionInitState == MOTION_INIT_STATE_FD) { motionInitState = MOTION_INIT_STATE_FB; return 0; }
- break;
- case 0xF8:
- //enable sensor mode
- if(motionInitState == MOTION_INIT_STATE_FD)
- {
- motionInitState = MOTION_INIT_STATE_IDLE;
- motionFlag |= MOTION_FLAG_SENSORMODE;
- return 0;
- }
- break;
- case 0xF9:
- //disable sensor mode
- if(motionInitState == MOTION_INIT_STATE_FD)
- {
- motionInitState = MOTION_INIT_STATE_IDLE;
- motionFlag &= ~MOTION_FLAG_SENSORMODE;
- return 0;
- }
- break;
-
- case 8:
- printf("COMMAND%c: Unverified Backup Memory command: %02X FROM %08X\n",(cpu==ARMCPU_ARM9)?'9':'7',val, (cpu==ARMCPU_ARM9)?NDS_ARM9.instruct_adr:NDS_ARM7.instruct_adr);
- val = 0xAA;
- break;
-
- case BM_CMD_WRITEDISABLE:
- switch(motionInitState)
- {
- case MOTION_INIT_STATE_IDLE: motionInitState = MOTION_INIT_STATE_RECEIVED_4; break;
- case MOTION_INIT_STATE_RECEIVED_4: motionInitState = MOTION_INIT_STATE_RECEIVED_4_B; break;
- }
- write_enable = false;
- break;
-
- case BM_CMD_READSTATUS:
- com = BM_CMD_READSTATUS;
- val = (write_enable << 1) | (3<<2);
- break;
-
- case BM_CMD_WRITEENABLE:
- write_enable = true;
- break;
-
- case BM_CMD_WRITELOW:
- case BM_CMD_READLOW:
- //printf("XLO: %08X\n",addr);
- com = val;
- addr_counter = 0;
- addr = 0;
- break;
-
- case BM_CMD_WRITEHIGH:
- case BM_CMD_READHIGH:
- //printf("XHI: %08X\n",addr);
- if(val == BM_CMD_WRITEHIGH) val = BM_CMD_WRITELOW;
- if(val == BM_CMD_READHIGH) val = BM_CMD_READLOW;
- com = val;
- addr_counter = 0;
- addr = 0;
- if(addr_size==1) {
- //"write command that's only available on ST M95040-W that I know of"
- //this makes sense, since this device would only have a 256 bytes address space with writelow
- //and writehigh would allow access to the upper 256 bytes
- //but it was detected in pokemon diamond also during the main save process
- addr = 0x1;
- }
- break;
-
- default:
- printf("COMMAND%c: Unhandled Backup Memory command: %02X FROM %08X\n",(cpu==ARMCPU_ARM9)?'9':'7',val, (cpu==ARMCPU_ARM9)?NDS_ARM9.instruct_adr:NDS_ARM7.instruct_adr);
- break;
- } //switch(val)
-
- //motion control state machine broke, return to ground
- motionInitState = MOTION_INIT_STATE_IDLE;
- }
- return val;
-}*/
-
-//guarantees that the data buffer has room enough for the specified number of bytes
+ memset(&this->info, 0, sizeof(this->info));
+ this->reset_hardware();
+ this->resize(0);
+ this->data_autodetect.resize(0);
+ this->addr_size = 0;
+ this->loadfile();
+
+ // if the user has requested a manual choice for backup type, and we havent imported a raw save file, then apply it now
+ if (this->state == DETECTING && CommonSettings.manualBackupType != MC_TYPE_AUTODETECT)
+ {
+ this->state = RUNNING;
+ int savetype = save_types[CommonSettings.manualBackupType].media_type;
+ int savesize = save_types[CommonSettings.manualBackupType].size;
+ this->ensure(static_cast<uint32_t>(savesize)); // expand properly if necessary
+ this->resize(savesize); // truncate if necessary
+ this->addr_size = this->addr_size_for_old_save_type(savetype);
+ }
+}
+
+// guarantees that the data buffer has room enough for the specified number of bytes
void BackupDevice::ensure(uint32_t Addr)
{
- uint32_t size = data.size();
- if(size<Addr)
- {
- resize(Addr);
- }
+ uint32_t size = this->data.size();
+ if (size < Addr)
+ this->resize(Addr);
}
void BackupDevice::resize(uint32_t size)
{
- size_t old_size = data.size();
- data.resize(size);
- for(uint32_t i=old_size;i<size;i++)
- data[i] = kUninitializedSaveDataValue;
+ size_t old_size = this->data.size();
+ this->data.resize(size);
+ for (uint32_t i = old_size; i < size; ++i)
+ this->data[i] = kUninitializedSaveDataValue;
}
uint32_t BackupDevice::addr_size_for_old_save_size(int bupmem_size)
{
- switch(bupmem_size) {
+ switch (bupmem_size)
+ {
case MC_SIZE_4KBITS:
return 1;
case MC_SIZE_64KBITS:
@@ -712,13 +330,13 @@
uint32_t BackupDevice::addr_size_for_old_save_type(int bupmem_type)
{
- switch(bupmem_type)
+ switch (bupmem_type)
{
case MC_TYPE_EEPROM1:
return 1;
case MC_TYPE_EEPROM2:
case MC_TYPE_FRAM:
- return 2;
+ return 2;
case MC_TYPE_FLASH:
return 3;
default:
@@ -726,72 +344,63 @@
}
}
-
-void BackupDevice::load_old_state(uint32_t addrSize, uint8_t* Data, uint32_t datasize)
-{
- state = RUNNING;
+void BackupDevice::load_old_state(uint32_t addrSize, uint8_t *Data, uint32_t datasize)
+{
+ this->state = RUNNING;
this->addr_size = addrSize;
- resize(datasize);
- memcpy(&this->data[0],Data,datasize);
-
- //dump back out as a dsv, just to keep things sane
- //flush();
-}
-
-//======================================================================= no$GBA
-//=======================================================================
-//=======================================================================
+ this->resize(datasize);
+ memcpy(&this->data[0], Data, datasize);
+}
+
+// ======================================================================= no$GBA
+// =======================================================================
+// =======================================================================
static int no_gba_unpackSAV(void *in_buf, uint32_t fsize, void *out_buf, uint32_t &size)
{
const char no_GBA_HEADER_ID[] = "NocashGbaBackupMediaSavDataFile";
const char no_GBA_HEADER_SRAM_ID[] = "SRAM";
- uint8_t *src = (uint8_t *)in_buf;
- uint8_t *dst = (uint8_t *)out_buf;
+ uint8_t *src = static_cast<uint8_t *>(in_buf);
+ uint8_t *dst = static_cast<uint8_t *>(out_buf);
uint32_t src_pos = 0;
uint32_t dst_pos = 0;
- uint8_t cc = 0;
- uint32_t size_unpacked = 0;
- //uint32_t size_packed = 0;
- uint32_t compressMethod = 0;
-
- if (fsize < 0x50) return 1;
-
- for (int i = 0; i < 0x1F; i++)
- {
- if (src[i] != no_GBA_HEADER_ID[i]) return 2;
- }
- if (src[0x1F] != 0x1A) return 2;
- for (int i = 0; i < 0x4; i++)
- {
- if (src[i+0x40] != no_GBA_HEADER_SRAM_ID[i]) return 2;
- }
-
- compressMethod = *((uint32_t*)(src+0x44));
-
- if (compressMethod == 0) // unpacked
- {
- size_unpacked = *((uint32_t*)(src+0x48));
+ uint32_t size_unpacked = 0;
+ uint32_t compressMethod = 0;
+
+ if (fsize < 0x50)
+ return 1;
+
+ for (int i = 0; i < 0x1F; ++i)
+ if (src[i] != no_GBA_HEADER_ID[i])
+ return 2;
+ if (src[0x1F] != 0x1A)
+ return 2;
+ for (int i = 0; i < 0x4; ++i)
+ if (src[i + 0x40] != no_GBA_HEADER_SRAM_ID[i])
+ return 2;
+
+ compressMethod = *(reinterpret_cast<uint32_t *>(src + 0x44));
+
+ if (!compressMethod) // unpacked
+ {
+ size_unpacked = *(reinterpret_cast<uint32_t *>(src + 0x48));
src_pos = 0x4C;
- for (uint32_t i = 0; i < size_unpacked; i++)
- {
+ for (uint32_t i = 0; i < size_unpacked; ++i)
dst[dst_pos++] = src[src_pos++];
- }
size = dst_pos;
return 0;
}
- if (compressMethod == 1) // packed (method 1)
- {
- //size_packed = *((uint32_t*)(src+0x48));
- size_unpacked = *((uint32_t*)(src+0x4C));
+ if (compressMethod == 1) // packed (method 1)
+ {
+ size_unpacked = *(reinterpret_cast<uint32_t *>(src + 0x4C));
src_pos = 0x50;
while (true)
{
- cc = src[src_pos++];
-
- if (cc == 0)
+ uint8_t cc = src[src_pos++];
+
+ if (!cc)
{
size = dst_pos;
return 0;
@@ -799,23 +408,23 @@
if (cc == 0x80)
{
- uint16_t tsize = *((uint16_t*)(src+src_pos+1));
- for (int t = 0; t < tsize; t++)
+ uint16_t tsize = *(reinterpret_cast<uint16_t *>(src + src_pos + 1));
+ for (int t = 0; t < tsize; ++t)
dst[dst_pos++] = src[src_pos];
src_pos += 3;
continue;
}
- if (cc > 0x80) // repeat
+ if (cc > 0x80) // repeat
{
cc -= 0x80;
- for (int t = 0; t < cc; t++)
+ for (int t = 0; t < cc; ++t)
dst[dst_pos++] = src[src_pos];
- src_pos++;
+ ++src_pos;
continue;
}
// copy
- for (int t = 0; t < cc; t++)
+ for (int t = 0; t < cc; ++t)
dst[dst_pos++] = src[src_pos++];
}
size = dst_pos;
@@ -828,347 +437,180 @@
{
uint32_t rows = size / 16;
uint32_t pos = (size - 16);
- uint8_t *src = (uint8_t*)buf;
-
- for (unsigned int i = 0; i < rows; i++, pos -= 16)
+ uint8_t *src = static_cast<uint8_t *>(buf);
+
+ for (unsigned i = 0; i < rows; ++i, pos -= 16)
{
if (src[pos] == 0xFF)
{
- for (int t = 0; t < 16; t++)
- {
- if (src[pos+t] != 0xFF) return pos+16;
- }
+ for (int t = 0; t < 16; ++t)
+ if (src[pos + t] != 0xFF)
+ return pos + 16;
}
else
- {
- return pos+16;
- }
+ return pos + 16;
}
return size;
}
static uint32_t no_gba_fillLeft(uint32_t size)
{
- for (uint32_t i = 1; i < ARRAY_SIZE(save_types); i++)
- {
- if (size <= (uint32_t)save_types[i][1])
- return size + (save_types[i][1] - size);
- }
+ for (uint32_t i = 1; i < ARRAY_SIZE(save_types); ++i)
+ if (size <= static_cast<uint32_t>(save_types[i].size))
+ return size + (save_types[i].size - size);
return size;
}
bool BackupDevice::load_no_gba(const char *fname)
{
- FILE *fsrc = fopen(fname, "rb");
- uint8_t *in_buf = NULL;
- uint8_t *out_buf = NULL;
+ FILE *fsrc = fopen(fname, "rb");
if (fsrc)
{
- uint32_t fsize = 0;
fseek(fsrc, 0, SEEK_END);
- fsize = ftell(fsrc);
+ uint32_t fsize = ftell(fsrc);
fseek(fsrc, 0, SEEK_SET);
//printf("Open %s file (size %i bytes)\n", fname, fsize);
- in_buf = new uint8_t [fsize];
-
- if (fread(in_buf, 1, fsize, fsrc) == fsize)
- {
- out_buf = new uint8_t [8 * 1024 * 1024 / 8];
+ auto in_buf = std::unique_ptr<uint8_t[]>(new uint8_t[fsize]);
+
+ if (fread(&in_buf[0], 1, fsize, fsrc) == fsize)
+ {
+ auto out_buf = std::unique_ptr<uint8_t[]>(new uint8_t[8 * 1024 * 1024 / 8]);
+
+ memset(&out_buf[0], 0xFF, 8 * 1024 * 1024 / 8);
uint32_t size = 0;
-
- memset(out_buf, 0xFF, 8 * 1024 * 1024 / 8);
- if (no_gba_unpackSAV(in_buf, fsize, out_buf, size) == 0)
+ if (!no_gba_unpackSAV(&in_buf[0], fsize, &out_buf[0], size))
{
//printf("New size %i byte(s)\n", size);
- size = no_gba_savTrim(out_buf, size);
+ size = no_gba_savTrim(&out_buf[0], size);
//printf("--- new size after trim %i byte(s)\n", size);
size = no_gba_fillLeft(size);
//printf("--- new size after fill %i byte(s)\n", size);
raw_applyUserSettings(size);
- data.resize(size);
- for (uint32_t tt = 0; tt < size; tt++)
- data[tt] = out_buf[tt];
+ this->data.resize(size);
+ for (uint32_t tt = 0; tt < size; ++tt)
+ this->data[tt] = out_buf[tt];
//dump back out as a dsv, just to keep things sane
- //flush();
printf("---- Loaded no$GBA save\n");
- if (in_buf) delete [] in_buf;
- if (out_buf) delete [] out_buf;
fclose(fsrc);
return true;
}
- if (out_buf) delete [] out_buf;
- }
- if (in_buf) delete [] in_buf;
+ }
fclose(fsrc);
}
return false;
}
-/*bool BackupDevice::save_no_gba(const char* fname)
-{
- FILE* outf = fopen(fname,"wb");
- if(!outf) return false;
- uint32_t size = data.size();
- uint32_t padSize = pad_up_size(size);
- if(data.size()>0)
- fwrite(&data[0],1,size,outf);
- for(uint32_t i=size;i<padSize;i++)
- fputc(0xFF,outf);
-
- if (padSize < 512 * 1024)
- {
- for(uint32_t i=padSize; i<512 * 1024; i++)
- fputc(0xFF,outf);
- }
- fclose(outf);
- return true;
-}*/
-//======================================================================= end
-//=======================================================================
-//======================================================================= no$GBA
-
+// ======================================================================= end
+// =======================================================================
+// ======================================================================= no$GBA
void BackupDevice::loadfile()
{
- //never use save files if we are in movie mode
- //if(isMovieMode) return;
- if(filename.length() ==0) return; //No sense crashing if no filename supplied
-
- EMUFILE_FILE* inf = new EMUFILE_FILE(filename.c_str(),"rb");
- if(inf->fail())
- {
- delete inf;
- //no dsv found; we need to try auto-importing a file with .sav extension
+ if (this->filename.empty())
+ return; // No sense crashing if no filename supplied
+
+ auto inf = std::unique_ptr<EMUFILE_FILE>(new EMUFILE_FILE(filename.c_str(), "rb"));
+ if (inf->fail())
+ {
+ // no dsv found; we need to try auto-importing a file with .sav extension
printf("DeSmuME .dsv save file not found. Trying to load an old raw .sav file.\n");
- //change extension to sav
+ // change extension to sav
char tmp[MAX_PATH];
- strcpy(tmp,filename.c_str());
- tmp[strlen(tmp)-3] = 0;
- strcat(tmp,"sav");
-
- inf = new EMUFILE_FILE(tmp,"rb");
- if(inf->fail())
- {
- delete inf;
- printf("Missing save file %s\n",filename.c_str());
+ strcpy(tmp, this->filename.c_str());
+ tmp[strlen(tmp) - 3] = 0;
+ strcat(tmp, "sav");
+
+ inf.reset(new EMUFILE_FILE(tmp, "rb"));
+ if (inf->fail())
+ {
+ printf("Missing save file %s\n", this->filename.c_str());
return;
}
- delete inf;
-
- if (!load_no_gba(tmp))
- load_raw(tmp);
+
+ if (!this->load_no_gba(tmp))
+ this->load_raw(tmp);
}
else
{
- //scan for desmume save footer
- const int32_t cookieLen = (int32_t)strlen(kDesmumeSaveCookie);
- char *sigbuf = new char[cookieLen];
+ // scan for desmume save footer
+ int32_t cookieLen = static_cast<int32_t>(strlen(kDesmumeSaveCookie));
+ auto sigbuf = std::unique_ptr<char[]>(new char[cookieLen]);
inf->fseek(-cookieLen, SEEK_END);
- inf->fread(sigbuf,cookieLen);
- int cmp = memcmp(sigbuf,kDesmumeSaveCookie,cookieLen);
- delete[] sigbuf;
- if(cmp)
- {
- //maybe it is a misnamed raw save file. try loading it that way
+ inf->fread(&sigbuf[0], cookieLen);
+ int cmp = memcmp(&sigbuf[0], kDesmumeSaveCookie,cookieLen);
+ if (cmp)
+ {
+ // maybe it is a misnamed raw save file. try loading it that way
printf("Not a DeSmuME .dsv save file. Trying to load as raw.\n");
- delete inf;
- if (!load_no_gba(filename.c_str()))
- load_raw(filename.c_str());
+ if (!this->load_no_gba(this->filename.c_str()))
+ this->load_raw(this->filename.c_str());
return;
}
- //desmume format
+ // desmume format
inf->fseek(-cookieLen, SEEK_END);
inf->fseek(-4, SEEK_CUR);
uint32_t version = 0xFFFFFFFF;
- read32le(&version,inf);
- if(version!=0) {
+ read32le(&version, inf.get());
+ if (version)
+ {
printf("Unknown save file format\n");
return;
}
inf->fseek(-24, SEEK_CUR);
- read32le(&info.size,inf);
- read32le(&info.padSize,inf);
- read32le(&info.type,inf);
- read32le(&info.addr_size,inf);
- read32le(&info.mem_size,inf);
-
- //uint32_t left = 0;
- /*if (CommonSettings.autodetectBackupMethod == 1)
- {
- if (advsc.isLoaded())
- {
- info.type = advsc.getSaveType();
- if (info.type != 0xFF || info.type != 0xFE)
- {
- u32 adv_size = save_types[info.type+1][1];
- if (info.size > adv_size)
- info.size = adv_size;
- else
- if (info.size < adv_size)
- {
- left = adv_size - info.size;
- info.size = adv_size;
- }
- }
- }
- }*/
- //establish the save data
- resize(info.size);
+ read32le(&this->info.size, inf.get());
+ read32le(&this->info.padSize, inf.get());
+ read32le(&this->info.type, inf.get());
+ read32le(&this->info.addr_size, inf.get());
+ read32le(&this->info.mem_size, inf.get());
+
+ // establish the save data
+ this->resize(this->info.size);
inf->fseek(0, SEEK_SET);
- if(info.size>0)
- inf->fread(&data[0],info.size); //read all the raw data we have
- state = RUNNING;
- addr_size = info.addr_size;
- //none of the other fields are used right now
-
- /*if (CommonSettings.autodetectBackupMethod != 1 && info.type == 0)
- {
- info.type = searchFileSaveType(info.size);
- if (info.type == 0xFF) info.type = 0;
- }
- uint32_t ss = info.size * 8 / 1024;
- if (ss >= 1024)
- {
- ss /= 1024;
- printf("Backup size: %i Mbit\n", ss);
- }
- else
- printf("Backup size: %i Kbit\n", ss);*/
-
- delete inf;
- }
-}
-
-/*bool BackupDevice::save_raw(const char* fn)
-{
- FILE* outf = fopen(fn,"wb");
- if(!outf) return false;
- uint32_t size = data.size();
- uint32_t padSize = pad_up_size(size);
- if(data.size()>0)
- fwrite(&data[0],1,size,outf);
- for(uint32_t i=size;i<padSize;i++)
- fputc(kUninitializedSaveDataValue,outf);
- fclose(outf);
- return true;
-}*/
-
-/*uint32_t BackupDevice::pad_up_size(uint32_t startSize)
-{
- uint32_t size = startSize;
- uint32_t ctr=0;
- while(ctr<saveSizes_count && size > saveSizes[ctr]) ctr++;
- uint32_t padSize = saveSizes[ctr];
- if(padSize == 0xFFFFFFFF)
- {
- printf("PANIC! Couldn't pad up save size. Refusing to pad.\n");
- padSize = startSize;
- }
- return padSize;
-}*/
-
-/*void BackupDevice::lazy_flush()
-{
- if(flushPending || lazyFlushPending)
- {
- lazyFlushPending = flushPending = false;
- //flush();
- }
-}*/
-
-/*void BackupDevice::flush()
-{
- //never use save files if we are in movie mode
- if(isMovieMode) return;
-
- EMUFILE* outf = new EMUFILE_FILE(filename.c_str(),"wb");
- if(!outf->fail())
- {
- if(data.size()>0)
- outf->fwrite(&data[0],data.size());
-
- //write the footer. we use a footer so that we can maximize the chance of the
- //save file being recognized as a raw save file by other emulators etc.
-
- //first, pad up to the next largest known save size.
- uint32_t size = data.size();
- uint32_t padSize = pad_up_size(size);
-
- for(uint32_t i=size;i<padSize;i++)
- outf->fputc(kUninitializedSaveDataValue);
-
- //this is just for humans to read
- outf->fprintf("|<--Snip above here to create a raw sav by excluding this DeSmuME savedata footer:");
-
- //and now the actual footer
- write32le(size,outf); //the size of data that has actually been written
- write32le(padSize,outf); //the size we padded it to
- write32le(0,outf); //save memory type
- write32le(addr_size,outf);
- write32le(0,outf); //save memory size
- write32le(0,outf); //version number
- outf->fprintf("%s", kDesmumeSaveCookie); //this is what we'll use to recognize the desmume format save
-
- delete outf;
+ if (this->info.size > 0)
+ inf->fread(&this->data[0], this->info.size); // read all the raw data we have
+ this->state = RUNNING;
+ this->addr_size = this->info.addr_size;
+ // none of the other fields are used right now
+ }
+}
+
+void BackupDevice::raw_applyUserSettings(uint32_t &size, bool manual)
+{
+ // respect the user's choice of backup memory type
+ if (CommonSettings.manualBackupType == MC_TYPE_AUTODETECT && !manual)
+ {
+ this->addr_size = this->addr_size_for_old_save_size(size);
+ this->resize(size);
}
else
{
- delete outf;
- printf("Unable to open savefile %s\n",filename.c_str());
- }
-}*/
-
-void BackupDevice::raw_applyUserSettings(uint32_t& size, bool manual)
-{
- //respect the user's choice of backup memory type
- if(CommonSettings.manualBackupType == MC_TYPE_AUTODETECT && !manual)
- {
- addr_size = addr_size_for_old_save_size(size);
- resize(size);
- }
- else
- {
uint32_t type = CommonSettings.manualBackupType;
- /*if (manual)
- {
- uint32_t res = searchFileSaveType(size);
- if (res != 0xFF) type = (res + 1); // +1 - skip autodetect
- }*/
- int savetype = save_types[type][0];
- int savesize = save_types[type][1];
- addr_size = addr_size_for_old_save_type(savetype);
- if((uint32_t)savesize<size) size = savesize;
- resize(savesize);
- }
-
- state = RUNNING;
-}
-
-/*uint32_t BackupDevice::get_save_raw_size(const char* fname)
-{
- FILE* inf = fopen(fname,"rb");
- if (!inf) return 0xFFFFFFFF;
+ int savetype = save_types[type].media_type;
+ int savesize = save_types[type].size;
+ this->addr_size = this->addr_size_for_old_save_type(savetype);
+ if (static_cast<uint32_t>(savesize) < size)
+ size = savesize;
+ this->resize(savesize);
+ }
+
+ this->state = RUNNING;
+}
+
+bool BackupDevice::load_raw(const char *fn, uint32_t force_size)
+{
+ FILE *inf = fopen(fn,"rb");
+
+ if (!inf)
+ return false;
fseek(inf, 0, SEEK_END);
- uint32_t size = (uint32_t)ftell(inf);
- fclose(inf);
- return size;
-}*/
-
-bool BackupDevice::load_raw(const char* fn, uint32_t force_size)
-{
- FILE* inf = fopen(fn,"rb");
-
- if (!inf) return false;
-
- fseek(inf, 0, SEEK_END);
- uint32_t size = (uint32_t)ftell(inf);
+ uint32_t size = static_cast<uint32_t>(ftell(inf));
uint32_t left = 0;
if (force_size > 0)
@@ -1184,98 +626,11 @@
fseek(inf, 0, SEEK_SET);
- raw_applyUserSettings(size, force_size > 0);
-
- fread(&data[0],1,size - left,inf);
+ this->raw_applyUserSettings(size, force_size > 0);
+
+ fread(&this->data[0], 1, size - left, inf);
fclose(inf);
- //dump back out as a dsv, just to keep things sane
- //flush();
-
return true;
}
-
-/*bool BackupDevice::load_duc(const char* fn)
-{
- uint32_t size;
- char id[16];
- FILE* file = fopen(fn, "rb");
- if(file == NULL)
- return false;
-
- fseek(file, 0, SEEK_END);
- size = (uint32_t)ftell(file) - 500;
- fseek(file, 0, SEEK_SET);
-
- // Make sure we really have the right file
- fread((void *)id, sizeof(char), 16, file);
-
- if (memcmp(id, "ARDS000000000001", 16) != 0)
- {
- printf("Not recognized as a valid DUC file\n");
- fclose(file);
- return false;
- }
- // Skip the rest of the header since we don't need it
- fseek(file, 500, SEEK_SET);
-
- raw_applyUserSettings(size);
-
- ensure((uint32_t)size);
-
- fread(&data[0],1,size,file);
- fclose(file);
-
- //choose
-
- //flush();
-
- return true;
-
-}*/
-
-/*bool BackupDevice::load_movie(EMUFILE* is) {
-
- const int32_t cookieLen = (int32_t)strlen(kDesmumeSaveCookie);
-
- is->fseek(-cookieLen, SEEK_END);
- is->fseek(-4, SEEK_CUR);
-
- uint32_t version = 0xFFFFFFFF;
- is->fread((char*)&version,4);
- if(version!=0) {
- printf("Unknown save file format\n");
- return false;
- }
- is->fseek(-24, SEEK_CUR);
-
- struct{
- uint32_t size,padSize,type,addr_size,mem_size;
- }info;
-
- is->fread((char*)&info.size,4);
- is->fread((char*)&info.padSize,4);
- is->fread((char*)&info.type,4);
- is->fread((char*)&info.addr_size,4);
- is->fread((char*)&info.mem_size,4);
-
- //establish the save data
- data.resize(info.size);
- is->fseek(0, SEEK_SET);
- if(info.size>0)
- is->fread((char*)&data[0],info.size);
-
- state = RUNNING;
- addr_size = info.addr_size;
- //none of the other fields are used right now
-
- return true;
-}*/
-
-/*void BackupDevice::forceManualBackupType()
-{
- addr_size = addr_size_for_old_save_size(save_types[CommonSettings.manualBackupType][1]);
- state = RUNNING;
-}*/
-
--- a/src/in_2sf/desmume/mc.h
+++ b/src/in_2sf/desmume/mc.h
@@ -1,7 +1,7 @@
/*
Copyright (C) 2006 thoduv
Copyright (C) 2006 Theo Berkau
- Copyright (C) 2008-2012 DeSmuME team
+ Copyright (C) 2008-2013 DeSmuME team
This file is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -23,7 +23,6 @@
#include <vector>
#include <string>
#include <cstdio>
-
#include "types.h"
#include "emufile.h"
#include "windowsh_wrapper.h"
@@ -52,17 +51,16 @@
struct memory_chip_t
{
- uint8_t com; //persistent command actually handled
- uint32_t addr; //current address for reading/writing
- uint8_t addr_shift; //shift for address (since addresses are transfered by 3 bytes units)
- uint8_t addr_size; //size of addr when writing/reading
+ uint8_t com; // persistent command actually handled
+ uint32_t addr; // current address for reading/writing
+ uint8_t addr_shift; // shift for address (since addresses are transfered by 3 bytes units)
+ uint8_t addr_size; // size of addr when writing/reading
- bool write_enable; //is write enabled ?
+ bool write_enable; //is write enabled ?
- //uint8_t *data; //memory data
- std::vector<uint8_t> data;
- uint32_t size; //memory size
- bool writeable_buffer; //is "data" writeable ?
+ std::vector<uint8_t> data; //memory data
+ uint32_t size; // memory size
+ bool writeable_buffer; // is "data" writeable ?
int type; //type of Memory
char *filename;
FILE *fp;
@@ -74,115 +72,96 @@
char userfile[MAX_PATH];
};
-//the new backup system by zeromus
+// the new backup system by zeromus
class BackupDevice
{
public:
BackupDevice();
- //signals the save system that we are in our regular mode, loading up a rom. initializes for that case.
- void load_rom(const char* filename);
- //signals the save system that we are in MOVIE mode. doesnt load up a rom, and never saves it. initializes for that case.
- //void movie_mode();
+ // signals the save system that we are in our regular mode, loading up a rom. initializes for that case.
+ void load_rom(const std::string &filename);
void reset();
- //void close_rom();
- //void forceManualBackupType();
void reset_hardware();
std::string getFilename() { return filename; }
- //bool save_state(EMUFILE* os);
- bool load_state(EMUFILE* is);
-
- //commands from mmu
- //void reset_command();
- //uint8_t data_command(uint8_t,int);
std::vector<uint8_t> data;
- //this info was saved before the last reset (used for savestate compatibility)
+ // this info was saved before the last reset (used for savestate compatibility)
struct SavedInfo
{
uint32_t addr_size;
} savedInfo;
- //and these are used by old savestates
- void load_old_state(uint32_t addr_size, uint8_t* data, uint32_t datasize);
+ // and these are used by old savestates
+ void load_old_state(uint32_t addr_size, uint8_t *data, uint32_t datasize);
static uint32_t addr_size_for_old_save_size(int bupmem_size);
static uint32_t addr_size_for_old_save_type(int bupmem_type);
- //static uint32_t pad_up_size(uint32_t startSize);
- void raw_applyUserSettings(uint32_t& size, bool manual = false);
+ void raw_applyUserSettings(uint32_t &size, bool manual = false);
- //bool load_duc(const char* filename);
bool load_no_gba(const char *fname);
- //bool save_no_gba(const char* fname);
bool load_raw(const char* filename, uint32_t force_size = 0);
- //bool save_raw(const char* filename);
- //bool load_movie(EMUFILE* is);
- //call me once a second or so to lazy flush the save data
- //here's the reason for this system: we want to dump save files when theyre READ
- //so that we have a better idea earlier on how large they are. but it slows things down
- //way too much if we flush whenever we read.
- //void lazy_flush();
- //void flush();
-
- struct {
- uint32_t size,padSize,type,addr_size,mem_size;
- } info;
- //bool isMovieMode;
-
+ struct
+ {
+ uint32_t size, padSize, type, addr_size, mem_size;
+ } info;
private:
std::string filename;
- bool write_enable; //is write enabled?
- uint32_t com; //persistent command actually handled
+ bool write_enable; // is write enabled?
+ uint32_t com; // persistent command actually handled
uint32_t addr_size, addr_counter;
uint32_t addr;
std::vector<uint8_t> data_autodetect;
- enum STATE {
- DETECTING = 0, RUNNING = 1
+ enum STATE
+ {
+ DETECTING = 0,
+ RUNNING = 1
} state;
enum MOTION_INIT_STATE
{
- MOTION_INIT_STATE_IDLE, MOTION_INIT_STATE_RECEIVED_4, MOTION_INIT_STATE_RECEIVED_4_B,
- MOTION_INIT_STATE_FE, MOTION_INIT_STATE_FD, MOTION_INIT_STATE_FB
+ MOTION_INIT_STATE_IDLE,
+ MOTION_INIT_STATE_RECEIVED_4,
+ MOTION_INIT_STATE_RECEIVED_4_B,
+ MOTION_INIT_STATE_FE,
+ MOTION_INIT_STATE_FD,
+ MOTION_INIT_STATE_FB
};
enum MOTION_FLAG
{
- MOTION_FLAG_NONE=0,
- MOTION_FLAG_ENABLED=1,
- MOTION_FLAG_SENSORMODE=2
+ MOTION_FLAG_NONE,
+ MOTION_FLAG_ENABLED,
+ MOTION_FLAG_SENSORMODE
};
uint8_t motionInitState, motionFlag;
void loadfile();
- bool _loadfile(const char *fname);
void ensure(uint32_t addr);
bool flushPending, lazyFlushPending;
-private:
void resize(uint32_t size);
};
-#define NDS_FW_SIZE_V1 (256 * 1024) /* size of fw memory on nds v1 */
-#define NDS_FW_SIZE_V2 (512 * 1024) /* size of fw memory on nds v2 */
+#define NDS_FW_SIZE_V1 (256 * 1024) /* size of fw memory on nds v1 */
+#define NDS_FW_SIZE_V2 (512 * 1024) /* size of fw memory on nds v2 */
-void mc_init(memory_chip_t *mc, int type); /* reset and init values for memory struct */
-uint8_t *mc_alloc(memory_chip_t *mc, uint32_t size); /* alloc mc memory */
-//void mc_realloc(memory_chip_t *mc, int type, uint32_t size); /* realloc mc memory */
-//void mc_load_file(memory_chip_t *mc, const char* filename); /* load save file and setup fp */
-void mc_free(memory_chip_t *mc); /* delete mc memory */
-void fw_reset_com(memory_chip_t *mc); /* reset communication with mc */
+void mc_init(memory_chip_t *mc, int type); /* reset and init values for memory struct */
+uint8_t *mc_alloc(memory_chip_t *mc, uint32_t size); /* alloc mc memory */
+void mc_free(memory_chip_t *mc); /* delete mc memory */
+void fw_reset_com(memory_chip_t *mc); /* reset communication with mc */
uint8_t fw_transfer(memory_chip_t *mc, uint8_t data);
-//void backup_setManualBackupType(int type);
-//void backup_forceManualBackupType();
-
-//extern const char *save_names[];
+struct SAVE_TYPE
+{
+ const char *descr;
+ int media_type;
+ int size;
+};
#endif /*__FW_H__*/
--- a/src/in_2sf/desmume/mem.h
+++ b/src/in_2sf/desmume/mem.h
@@ -22,106 +22,100 @@
#include <cstdlib>
#include <cassert>
-
#include "types.h"
-//this was originally declared in MMU.h but we suffered some organizational problems and had to remove it
+// this was originally declared in MMU.h but we suffered some organizational problems and had to remove it
enum MMU_ACCESS_TYPE
{
- MMU_AT_CODE, //used for cpu prefetches
- MMU_AT_DATA, //used for cpu read/write
- MMU_AT_GPU, //used for gpu read/write
- MMU_AT_DMA, //used for dma read/write (blocks access to TCM)
- MMU_AT_DEBUG //used for emulator debugging functions (bypasses some debug handling)
+ MMU_AT_CODE, // used for cpu prefetches
+ MMU_AT_DATA, // used for cpu read/write
+ MMU_AT_GPU, // used for gpu read/write
+ MMU_AT_DMA, // used for dma read/write (blocks access to TCM)
+ MMU_AT_DEBUG // used for emulator debugging functions (bypasses some debug handling)
};
-static inline uint8_t T1ReadByte(uint8_t* const mem, const uint32_t addr)
+inline uint8_t T1ReadByte(const uint8_t *const mem, uint32_t addr)
{
- return mem[addr];
+ return mem[addr];
}
-static inline uint16_t T1ReadWord_guaranteedAligned(void* const mem, const uint32_t addr)
+inline uint16_t T1ReadWord_guaranteedAligned(const uint8_t *const mem, uint32_t addr)
{
- assert((addr&1)==0);
+ assert(!(addr & 1));
#ifdef WORDS_BIGENDIAN
- return (((uint8_t*)mem)[addr + 1] << 8) | ((uint8_t*)mem)[addr];
+ return (static_cast<uint8_t *>(mem)[addr + 1] << 8) | static_cast<uint8_t *>(mem)[addr];
#else
- return *(uint16_t*)((uint8_t*)mem + addr);
+ return *reinterpret_cast<const uint16_t *>(mem + addr);
#endif
}
-static inline uint16_t T1ReadWord(void* const mem, const uint32_t addr)
+inline uint16_t T1ReadWord(const uint8_t *const mem, uint32_t addr)
{
#ifdef WORDS_BIGENDIAN
- return (((uint8_t*)mem)[addr + 1] << 8) | ((uint8_t*)mem)[addr];
+ return (static_cast<uint8_t *>(mem)[addr + 1] << 8) | static_cast<uint8_t *>(mem)[addr];
#else
- return *((uint16_t *) ((uint8_t*)mem + addr));
+ return *reinterpret_cast<const uint16_t *>(mem + addr);
#endif
}
-static inline uint32_t T1ReadLong_guaranteedAligned(uint8_t* const mem, const uint32_t addr)
+inline uint32_t T1ReadLong_guaranteedAligned(const uint8_t *const mem, uint32_t addr)
{
- assert((addr&3)==0);
+ assert(!(addr & 3));
#ifdef WORDS_BIGENDIAN
- return mem[addr + 3] << 24 | mem[addr + 2] << 16 |
- mem[addr + 1] << 8 | mem[addr];
+ return mem[addr + 3] << 24 | mem[addr + 2] << 16 | mem[addr + 1] << 8 | mem[addr];
#else
- return *(uint32_t*)(mem + addr);
+ return *reinterpret_cast<const uint32_t *>(mem + addr);
#endif
}
-
-static inline uint32_t T1ReadLong(uint8_t* const mem, uint32_t addr)
+inline uint32_t T1ReadLong(const uint8_t *const mem, uint32_t addr)
{
- addr &= ~3;
+ addr &= ~3;
#ifdef WORDS_BIGENDIAN
- return mem[addr + 3] << 24 | mem[addr + 2] << 16 |
- mem[addr + 1] << 8 | mem[addr];
+ return mem[addr + 3] << 24 | mem[addr + 2] << 16 | mem[addr + 1] << 8 | mem[addr];
#else
- return *(uint32_t*)(mem + addr);
+ return *reinterpret_cast<const uint32_t *>(mem + addr);
#endif
}
-static inline uint64_t T1ReadQuad(uint8_t* const mem, const uint32_t addr)
+inline uint64_t T1ReadQuad(const uint8_t *const mem, uint32_t addr)
{
#ifdef WORDS_BIGENDIAN
- return uint64_t(mem[addr + 7]) << 56 | uint64_t(mem[addr + 6]) << 48 |
- uint64_t(mem[addr + 5]) << 40 | uint64_t(mem[addr + 4]) << 32 |
- uint64_t(mem[addr + 3]) << 24 | uint64_t(mem[addr + 2]) << 16 |
- uint64_t(mem[addr + 1]) << 8 | uint64_t(mem[addr ]);
+ return uint64_t(mem[addr + 7]) << 56 | uint64_t(mem[addr + 6]) << 48 | uint64_t(mem[addr + 5]) << 40 | uint64_t(mem[addr + 4]) << 32 |
+ uint64_t(mem[addr + 3]) << 24 | uint64_t(mem[addr + 2]) << 16 | uint64_t(mem[addr + 1]) << 8 | uint64_t(mem[addr]);
#else
- return *((uint64_t *) (mem + addr));
+ return *reinterpret_cast<const uint64_t *>(mem + addr);
#endif
}
-static inline void T1WriteByte(uint8_t* const mem, const uint32_t addr, const uint8_t val)
+inline void T1WriteByte(uint8_t *const mem, uint32_t addr, uint8_t val)
{
- mem[addr] = val;
+ mem[addr] = val;
}
-static inline void T1WriteWord(uint8_t* const mem, const uint32_t addr, const uint16_t val)
+inline void T1WriteWord(uint8_t *const mem, uint32_t addr, uint16_t val)
{
#ifdef WORDS_BIGENDIAN
- mem[addr + 1] = val >> 8;
- mem[addr] = val & 0xFF;
+ mem[addr + 1] = val >> 8;
+ mem[addr] = val & 0xFF;
#else
- *((uint16_t *) (mem + addr)) = val;
+ *reinterpret_cast<uint16_t *>(mem + addr) = val;
#endif
}
-static inline void T1WriteLong(uint8_t* const mem, const uint32_t addr, const uint32_t val)
+inline void T1WriteLong(uint8_t *const mem, uint32_t addr, uint32_t val)
{
#ifdef WORDS_BIGENDIAN
- mem[addr + 3] = val >> 24;
- mem[addr + 2] = (val >> 16) & 0xFF;
- mem[addr + 1] = (val >> 8) & 0xFF;
- mem[addr] = val & 0xFF;
+ mem[addr + 3] = val >> 24;
+ mem[addr + 2] = (val >> 16) & 0xFF;
+ mem[addr + 1] = (val >> 8) & 0xFF;
+ mem[addr] = val & 0xFF;
#else
- *((uint32_t *) (mem + addr)) = val;
+ *reinterpret_cast<uint32_t *>(mem + addr) = val;
#endif
}
-static inline void T1WriteQuad(uint8_t* const mem, const uint32_t addr, const uint64_t val)
+inline void T1WriteQuad(uint8_t *const mem, uint32_t addr, uint64_t val)
{
#ifdef WORDS_BIGENDIAN
mem[addr + 7] = (val >> 56);
@@ -129,62 +123,13 @@
mem[addr + 5] = (val >> 40) & 0xFF;
mem[addr + 4] = (val >> 32) & 0xFF;
mem[addr + 3] = (val >> 24) & 0xFF;
- mem[addr + 2] = (val >> 16) & 0xFF;
- mem[addr + 1] = (val >> 8) & 0xFF;
- mem[addr] = val & 0xFF;
+ mem[addr + 2] = (val >> 16) & 0xFF;
+ mem[addr + 1] = (val >> 8) & 0xFF;
+ mem[addr] = val & 0xFF;
#else
- *((uint64_t *) (mem + addr)) = val;
+ *reinterpret_cast<uint64_t *>(mem + addr) = val;
#endif
}
-//static inline uint8_t T2ReadByte(uint8_t* const mem, const uint32_t addr)
-//{
-//#ifdef WORDS_BIGENDIAN
-// return mem[addr ^ 1];
-//#else
-// return mem[addr];
-//#endif
-//}
-//
-
-/*static inline uint16_t HostReadWord(uint8_t* const mem, const uint32_t addr)
-{
- return *((uint16_t *) (mem + addr));
-}*/
-
-//
-//static inline uint32_t T2ReadLong(uint8_t* const mem, const uint32_t addr)
-//{
-//#ifdef WORDS_BIGENDIAN
-// return *((uint16_t *) (mem + addr + 2)) << 16 | *((uint16_t *) (mem + addr));
-//#else
-// return *((uint32_t *) (mem + addr));
-//#endif
-//}
-//
-//static inline void T2WriteByte(uint8_t* const mem, const uint32_t addr, const uint8_t val)
-//{
-//#ifdef WORDS_BIGENDIAN
-// mem[addr ^ 1] = val;
-//#else
-// mem[addr] = val;
-//#endif
-//}
-
-/*static inline void HostWriteWord(uint8_t* const mem, const uint32_t addr, const uint16_t val)
-{
- *((uint16_t *) (mem + addr)) = val;
-}*/
-
-/*static inline void HostWriteTwoWords(uint8_t* const mem, const uint32_t addr, const uint32_t val)
-{
-#ifdef WORDS_BIGENDIAN
- *((uint16_t *) (mem + addr + 2)) = val >> 16;
- *((uint16_t *) (mem + addr)) = val & 0xFFFF;
-#else
- *((uint32_t *) (mem + addr)) = val;
-#endif
-}*/
-
#endif
--- a/src/in_2sf/desmume/metaspu/SndOut.cpp
+++ b/src/in_2sf/desmume/metaspu/SndOut.cpp
@@ -16,8 +16,6 @@
*/
#include <cassert>
-
-//#include "Global.h"
#include "../types.h"
#include "SndOut.h"
@@ -26,119 +24,49 @@
bool timeStretchDisabled = false;
//----------------
-StereoOut32 StereoOut32::Empty( 0, 0 );
-
-StereoOut32::StereoOut32( const StereoOut16& src ) :
- Left( src.Left ),
- Right( src.Right )
-{
-}
-
-StereoOut32::StereoOut32( const StereoOutFloat& src ) :
- Left( (int32_t)(src.Left * 2147483647.0f) ),
- Right( (int32_t)(src.Right * 2147483647.0f) )
+StereoOut32 StereoOut32::Empty;
+
+StereoOut32::StereoOut32(const StereoOut16 &src) : Left(src.Left), Right(src.Right)
+{
+}
+
+StereoOut32::StereoOut32(const StereoOutFloat &src) : Left(static_cast<int32_t>(src.Left * 2147483647.0f)), Right(static_cast<int32_t>(src.Right * 2147483647.0f))
{
}
StereoOut16 StereoOut32::DownSample() const
{
- return StereoOut16(
- static_cast<int16_t>(Left >> SndOutVolumeShift),
- static_cast<int16_t>(Right >> SndOutVolumeShift)
- );
-}
-
-/*StereoOut32 StereoOut16::UpSample() const
-{
- return StereoOut32(
- Left << SndOutVolumeShift,
- Right << SndOutVolumeShift
- );
-
-}*/
-
-//class NullOutModule: public SndOutModule
-//{
-//public:
-// int32_t Init() { return 0; }
-// void Close() { }
-// int32_t Test() const { return 0; }
-// void Configure(uptr parent) { }
-// bool Is51Out() const { return false; }
-// int GetEmptySampleCount() const { return 0; }
-//
-// const wchar_t* GetIdent() const
-// {
-// return L"nullout";
-// }
-//
-// const wchar_t* GetLongName() const
-// {
-// return L"No Sound (Emulate SPU2 only)";
-// }
-//
-// void ReadSettings()
-// {
-// }
-//
-// void WriteSettings() const
-// {
-// }
-//
-//} NullOut;
-//
-//SndOutModule* mods[]=
-//{
-// &NullOut,
-//#ifdef _MSC_VER
-// XAudio2Out,
-// DSoundOut,
-// WaveOut,
-//#endif
-// NULL // signals the end of our list
-//};
-//
-//int FindOutputModuleById( const wchar_t* omodid )
-//{
-// int modcnt = 0;
-// while( mods[modcnt] != NULL )
-// {
-// if( wcscmp( mods[modcnt]->GetIdent(), omodid ) == 0 )
-// break;
-// ++modcnt;
-// }
-// return modcnt;
-//}
-
-StereoOut32 *SndBuffer::m_buffer;
+ return StereoOut16(static_cast<int16_t>(Left >> SndOutVolumeShift), static_cast<int16_t>(Right >> SndOutVolumeShift));
+}
+
+std::unique_ptr<StereoOut32[]> SndBuffer::m_buffer;
int32_t SndBuffer::m_size;
int32_t SndBuffer::m_rpos;
int32_t SndBuffer::m_wpos;
int32_t SndBuffer::m_data;
bool SndBuffer::m_underrun_freeze;
-StereoOut32* SndBuffer::sndTempBuffer = NULL;
-StereoOut16* SndBuffer::sndTempBuffer16 = NULL;
+std::unique_ptr<StereoOut32[]> SndBuffer::sndTempBuffer;
int SndBuffer::sndTempProgress = 0;
-static int GetAlignedBufferSize( int comp )
-{
- return (comp + SndOutPacketSize-1) & ~(SndOutPacketSize-1);
+inline int GetAlignedBufferSize(int comp)
+{
+ return (comp + SndOutPacketSize - 1) & ~(SndOutPacketSize - 1);
}
// Returns true if there is data to be output, or false if no data
// is available to be copied.
-bool SndBuffer::CheckUnderrunStatus( int& nSamples, int& quietSampleCount )
+bool SndBuffer::CheckUnderrunStatus(int &nSamples, int &quietSampleCount)
{
quietSampleCount = 0;
- if( m_underrun_freeze )
- {
- int toFill = (int)(m_size * ( timeStretchDisabled ? 0.50f : 0.1f ) );
- toFill = GetAlignedBufferSize( toFill );
+ if (m_underrun_freeze)
+ {
+ int toFill = static_cast<int>(m_size * (timeStretchDisabled ? 0.50f : 0.1f));
+ toFill = GetAlignedBufferSize(toFill);
// toFill is now aligned to a SndOutPacket
- if( m_data < toFill )
+ if (m_data < toFill)
{
quietSampleCount = nSamples;
return false;
@@ -147,19 +75,19 @@
m_underrun_freeze = false;
//TODO
//if( MsgOverruns() )
- printf(" * SPU2 > Underrun compensation (%d packets buffered)\n", toFill / SndOutPacketSize );
- lastPct = 0.0; // normalize timestretcher
- }
- else if( m_data < nSamples )
+ printf(" * SPU2 > Underrun compensation (%d packets buffered)\n", toFill / SndOutPacketSize);
+ lastPct = 0.0; // normalize timestretcher
+ }
+ else if (m_data < nSamples)
{
nSamples = m_data;
quietSampleCount = SndOutPacketSize - m_data;
m_underrun_freeze = true;
- if( !timeStretchDisabled )
+ if (!timeStretchDisabled)
timeStretchUnderrun();
- return nSamples != 0;
+ return !!nSamples;
}
return true;
@@ -175,10 +103,10 @@
void SndBuffer::_WriteSamples(StereoOut32 *bData, int nSamples)
{
- int free = m_size-m_data;
+ int free = m_size - m_data;
m_predictData = 0;
- assert( m_data <= m_size );
+ assert(m_data <= m_size);
// Problem:
// If the SPU2 gets out of sync with the SndOut device, the writepos of the
@@ -191,7 +119,7 @@
// The older portion of the buffer is discarded rather than incoming data,
// so that the overall audio synchronization is better.
- if( free < nSamples )
+ if (free < nSamples)
{
// Buffer overrun!
// Dump samples from the read portion of the buffer instead of dropping
@@ -199,90 +127,78 @@
int32_t comp;
- if( !timeStretchDisabled )
- {
+ if (!timeStretchDisabled)
comp = timeStretchOverrun();
- }
else
{
// Toss half the buffer plus whatever's being written anew:
- comp = GetAlignedBufferSize( (m_size + nSamples ) / 2 );
- if( comp > (m_size-SndOutPacketSize) ) comp = m_size-SndOutPacketSize;
+ comp = GetAlignedBufferSize((m_size + nSamples) / 2);
+ if (comp > m_size - SndOutPacketSize)
+ comp = m_size - SndOutPacketSize;
}
m_data -= comp;
- m_rpos = (m_rpos+comp) % m_size;
+ m_rpos = (m_rpos + comp) % m_size;
//TODO
//if( MsgOverruns() )
- printf(" * SPU2 > Overrun Compensation (%d packets tossed)\n", comp / SndOutPacketSize );
- lastPct = 0.0; // normalize the timestretcher
+ printf(" * SPU2 > Overrun Compensation (%d packets tossed)\n", comp / SndOutPacketSize);
+ lastPct = 0.0; // normalize the timestretcher
}
// copy in two phases, since there's a chance the packet
// wraps around the buffer (it'd be nice to deal in packets only, but
// the timestretcher and DSP options require flexibility).
- const int endPos = m_wpos + nSamples;
- const int secondCopyLen = endPos - m_size;
- StereoOut32* wposbuffer = &m_buffer[m_wpos];
+ int endPos = m_wpos + nSamples;
+ int secondCopyLen = endPos - m_size;
+ StereoOut32 *wposbuffer = &m_buffer[m_wpos];
m_data += nSamples;
- if( secondCopyLen > 0 )
+ if (secondCopyLen > 0)
{
nSamples -= secondCopyLen;
- memcpy( m_buffer, &bData[nSamples], secondCopyLen * sizeof( *bData ) );
+ memcpy(m_buffer.get(), &bData[nSamples], secondCopyLen * sizeof(*bData));
m_wpos = secondCopyLen;
}
else
m_wpos += nSamples;
- memcpy( wposbuffer, bData, nSamples * sizeof( *bData ) );
+ memcpy(wposbuffer, bData, nSamples * sizeof(*bData));
}
void SndBuffer::Init()
{
- //if( mods[OutputModule] == NULL )
- //{
- // _InitFail();
- // return;
- //}
-
// initialize sound buffer
// Buffer actually attempts to run ~50%, so allocate near double what
// the requested latency is:
-
- m_rpos = 0;
- m_wpos = 0;
- m_data = 0;
+ m_rpos = m_wpos = m_data = 0;
try
{
- const float latencyMS = SndOutLatencyMS * (timeStretchDisabled ? 1.5f : 2.0f );
- m_size = GetAlignedBufferSize( (int)(latencyMS * SampleRate / 1000.0f ) );
- m_buffer = new StereoOut32[m_size];
+ float latencyMS = SndOutLatencyMS * (timeStretchDisabled ? 1.5f : 2.0f);
+ m_size = GetAlignedBufferSize(static_cast<int>(latencyMS * SampleRate / 1000.0f));
+ m_buffer.reset(new StereoOut32[m_size]);
m_underrun_freeze = false;
- sndTempBuffer = new StereoOut32[SndOutPacketSize];
- sndTempBuffer16 = new StereoOut16[SndOutPacketSize];
- }
- catch( std::bad_alloc& )
+ sndTempBuffer.reset(new StereoOut32[SndOutPacketSize]);
+ }
+ catch(const std::bad_alloc &)
{
// out of memory exception (most likely)
- printf( "Out of memory error occurred while initializing SPU2." );
+ printf("Out of memory error occurred while initializing SPU2.");
_InitFail();
return;
}
// clear buffers!
// Fixes loopy sounds on emu resets.
- memset( sndTempBuffer, 0, sizeof(StereoOut32) * SndOutPacketSize );
- memset( sndTempBuffer16, 0, sizeof(StereoOut16) * SndOutPacketSize );
+ memset(sndTempBuffer.get(), 0, sizeof(StereoOut32) * SndOutPacketSize);
sndTempProgress = 0;
- soundtouchInit(); // initializes the timestretching
+ soundtouchInit(); // initializes the timestretching
// some crap
//spdif_set51(mods[OutputModule]->Is51Out());
@@ -291,99 +207,21 @@
//if( mods[OutputModule]->Init() == -1 ) _InitFail();
}
-/*void SndBuffer::Cleanup()
-{
- //mods[OutputModule]->Close();
-
- soundtouchCleanup();
-
- //safe_delete_array( m_buffer );
- //safe_delete_array( sndTempBuffer );
- //safe_delete_array( sndTempBuffer16 );
- delete[] m_buffer;
- delete[] sndTempBuffer;
- delete[] sndTempBuffer16;
-}*/
-
-//int SndBuffer::m_dsp_progress = 0;
-
-//int SndBuffer::m_timestretch_progress = 0;
-//int SndBuffer::ssFreeze = 0;
-
-/*void SndBuffer::ClearContents()
-{
- SndBuffer::soundtouchClearContents();
- SndBuffer::ssFreeze = 30; //Delays sound output for about half a second.
-}*/
-
-void SndBuffer::Write( const StereoOut32& Sample )
-{
- // Log final output to wavefile.
- //WaveDump::WriteCore( 1, CoreSrc_External, Sample.DownSample() );
-
- //RecordWrite( Sample.DownSample() );
-
+void SndBuffer::Write(const StereoOut32 &Sample)
+{
//if(mods[OutputModule] == &NullOut) // null output doesn't need buffering or stretching! :p
// return;
sndTempBuffer[sndTempProgress++] = Sample;
// If we haven't accumulated a full packet yet, do nothing more:
- if(sndTempProgress < SndOutPacketSize) return;
+ if (sndTempProgress < SndOutPacketSize)
+ return;
sndTempProgress = 0;
- //Don't play anything directly after loading a savestate, avoids static killing your speakers.
-// if ( ssFreeze > 0 )
-// {
-// ssFreeze--;
-// return;
-// }
-//#ifndef __LINUX__
-// else if( dspPluginEnabled )
-// {
-// // Convert in, send to winamp DSP, and convert out.
-//
-// for( int i=0; i<SndOutPacketSize; ++i ) { sndTempBuffer16[i] = sndTempBuffer[i].DownSample(); }
-// m_dsp_progress += DspProcess( (s16*)sndTempBuffer16, SndOutPacketSize );
-//
-// // Some ugly code to ensure full packet handling:
-// int ei = 0;
-// while( m_dsp_progress >= SndOutPacketSize )
-// {
-// for( int i=0; i<SndOutPacketSize; ++i, ++ei ) { sndTempBuffer[i] = sndTempBuffer16[ei].UpSample(); }
-//
-// if( !timeStretchDisabled )
-// timeStretchWrite();
-// else
-// _WriteSamples(sndTempBuffer, sndTempProgress);
-//
-// m_dsp_progress -= SndOutPacketSize;
-// }
-//
-// // copy any leftovers to the front of the dsp buffer.
-// if( m_dsp_progress > 0 )
-// {
-// memcpy( &sndTempBuffer16[ei], sndTempBuffer16,
-// sizeof(sndTempBuffer16[0]) * m_dsp_progress
-// );
-// }
-// }
-//#endif
-// else
- {
- if( !timeStretchDisabled )
- timeStretchWrite();
- else
- _WriteSamples(sndTempBuffer, SndOutPacketSize);
- }
-}
-
-/*int32_t SndBuffer::Test()
-{
- //if( mods[OutputModule] == NULL )
- // return -1;
-
- //return mods[OutputModule]->Test();
- return 0;
-}*/
-
+ if( !timeStretchDisabled )
+ timeStretchWrite();
+ else
+ _WriteSamples(sndTempBuffer.get(), SndOutPacketSize);
+}
+
--- a/src/in_2sf/desmume/metaspu/SndOut.h
+++ b/src/in_2sf/desmume/metaspu/SndOut.h
@@ -15,20 +15,21 @@
* along with SPU2-X. If not, see <http://www.gnu.org/licenses/>.
*/
-#pragma once
-
+#ifndef SNDOUT_H
+#define SNDOUT_H
+
+#include <memory>
#include <algorithm>
+#include "../types.h"
struct StereoOut16;
-//struct StereoOut32;
struct StereoOutFloat;
struct StereoOut32
{
static StereoOut32 Empty;
- int32_t Left;
- int32_t Right;
+ int32_t Left, Right;
StereoOut32() : Left(0), Right(0)
{
@@ -45,45 +46,38 @@
StereoOut32 operator+(const StereoOut32 &right) const
{
- return StereoOut32(Left + right.Left, Right + right.Right);
+ return StereoOut32(this->Left + right.Left, this->Right + right.Right);
}
StereoOut32 operator/(int src) const
{
- return StereoOut32(Left / src, Right / src);
+ return StereoOut32(this->Left / src, this->Right / src);
}
};
// Number of stereo samples per SndOut block.
// All drivers must work in units of this size when communicating with
// SndOut.
-static const int SndOutPacketSize = 512;
-
-// Overall master volume shift.
-// Converts the mixer's 32 bit value into a 16 bit value.
-//static const int SndOutVolumeShift = 13;
-
-//edit - zeromus 23-oct-2009
-//this is hardcoded differently for metaspu
-static const int SndOutVolumeShift = 0;
+const int SndOutPacketSize = 512;
+
+// edit - zeromus 23-oct-2009
+// this is hardcoded differently for metaspu
+const int SndOutVolumeShift = 0;
// Samplerate of the SPU2. For accurate playback we need to match this
// exactly. Trying to scale samplerates and maintain SPU2's Ts timing accuracy
// is too problematic. :)
-//this is hardcoded differently for metaspu
-//edit - zeromus 23-oct-2009
-////static const int SampleRate = 48000;
-//static const int SampleRate = 44100;
-//edit - nitsuja: make it use the global sample rate define
+// this is hardcoded differently for metaspu
+// edit - zeromus 23-oct-2009
+//const int SampleRate = 48000;
+//const int SampleRate = 44100;
+// edit - nitsuja: make it use the global sample rate define
#include "../SPU.h"
-static const int SampleRate = DESMUME_SAMPLE_RATE;
-
-//extern int FindOutputModuleById(const wchar_t *omodid);
+const int SampleRate = DESMUME_SAMPLE_RATE;
struct StereoOut16
{
- int16_t Left;
- int16_t Right;
+ int16_t Left, Right;
StereoOut16() : Left(0), Right(0)
{
@@ -96,8 +90,6 @@
StereoOut16(int16_t left, int16_t right) : Left(left), Right(right)
{
}
-
- //StereoOut32 UpSample() const;
void ResampleFrom(const StereoOut32 &src)
{
@@ -108,8 +100,7 @@
struct StereoOutFloat
{
- float Left;
- float Right;
+ float Left, Right;
StereoOutFloat() : Left(0.0f), Right(0.0f)
{
@@ -127,249 +118,6 @@
{
}
};
-
-//struct Stereo21Out16
-//{
-// int16_t Left;
-// int16_t Right;
-// int16_t LFE;
-//
-// void ResampleFrom( const StereoOut32& src )
-// {
-// Left = src.Left >> SndOutVolumeShift;
-// Right = src.Right >> SndOutVolumeShift;
-// LFE = (src.Left + src.Right) >> (SndOutVolumeShift + 1);
-// }
-//};
-//
-//struct StereoQuadOut16
-//{
-// int16_t Left;
-// int16_t Right;
-// int16_t LeftBack;
-// int16_t RightBack;
-//
-// void ResampleFrom( const StereoOut32& src )
-// {
-// Left = src.Left >> SndOutVolumeShift;
-// Right = src.Right >> SndOutVolumeShift;
-// LeftBack = src.Left >> SndOutVolumeShift;
-// RightBack = src.Right >> SndOutVolumeShift;
-// }
-//};
-//
-//struct Stereo41Out16
-//{
-// int16_t Left;
-// int16_t Right;
-// int16_t LFE;
-// int16_t LeftBack;
-// int16_t RightBack;
-//
-// void ResampleFrom( const StereoOut32& src )
-// {
-// Left = src.Left >> SndOutVolumeShift;
-// Right = src.Right >> SndOutVolumeShift;
-// LFE = (src.Left + src.Right) >> (SndOutVolumeShift + 1);
-// LeftBack = src.Left >> SndOutVolumeShift;
-// RightBack = src.Right >> SndOutVolumeShift;
-// }
-//};
-//
-//struct Stereo51Out16
-//{
-// int16_t Left;
-// int16_t Right;
-// int16_t Center;
-// int16_t LFE;
-// int16_t LeftBack;
-// int16_t RightBack;
-//
-// // Implementation Note: Center and Subwoofer/LFE -->
-// // This method is simple and sounds nice. It relies on the speaker/soundcard
-// // systems do to their own low pass / crossover. Manual lowpass is wasted effort
-// // and can't match solid state results anyway.
-//
-// void ResampleFrom( const StereoOut32& src )
-// {
-// Left = src.Left >> SndOutVolumeShift;
-// Right = src.Right >> SndOutVolumeShift;
-// Center = (src.Left + src.Right) >> (SndOutVolumeShift + 1);
-// LFE = Center;
-// LeftBack = src.Left >> SndOutVolumeShift;
-// RightBack = src.Right >> SndOutVolumeShift;
-// }
-//};
-//
-//struct Stereo51Out16DplII
-//{
-// int16_t Left;
-// int16_t Right;
-// int16_t Center;
-// int16_t LFE;
-// int16_t LeftBack;
-// int16_t RightBack;
-//
-// void ResampleFrom( const StereoOut32& src )
-// {
-// static const u8 sLogTable[256] = {
-// 0x00,0x3C,0x60,0x78,0x8C,0x9C,0xA8,0xB4,0xBE,0xC8,0xD0,0xD8,0xDE,0xE4,0xEA,0xF0,
-// 0xF6,0xFA,0xFE,0x04,0x08,0x0C,0x10,0x14,0x16,0x1A,0x1E,0x20,0x24,0x26,0x2A,0x2C,
-// 0x2E,0x32,0x34,0x36,0x38,0x3A,0x3E,0x40,0x42,0x44,0x46,0x48,0x4A,0x4C,0x4E,0x50,
-// 0x50,0x52,0x54,0x56,0x58,0x5A,0x5A,0x5C,0x5E,0x60,0x60,0x62,0x64,0x66,0x66,0x68,
-// 0x6A,0x6A,0x6C,0x6E,0x6E,0x70,0x70,0x72,0x74,0x74,0x76,0x76,0x78,0x7A,0x7A,0x7C,
-// 0x7C,0x7E,0x7E,0x80,0x80,0x82,0x82,0x84,0x84,0x86,0x86,0x88,0x88,0x8A,0x8A,0x8C,
-// 0x8C,0x8C,0x8E,0x8E,0x90,0x90,0x92,0x92,0x92,0x94,0x94,0x96,0x96,0x96,0x98,0x98,
-// 0x9A,0x9A,0x9A,0x9C,0x9C,0x9C,0x9E,0x9E,0xA0,0xA0,0xA0,0xA2,0xA2,0xA2,0xA4,0xA4,
-// 0xA4,0xA6,0xA6,0xA6,0xA8,0xA8,0xA8,0xAA,0xAA,0xAA,0xAC,0xAC,0xAC,0xAC,0xAE,0xAE,
-// 0xAE,0xB0,0xB0,0xB0,0xB2,0xB2,0xB2,0xB2,0xB4,0xB4,0xB4,0xB6,0xB6,0xB6,0xB6,0xB8,
-// 0xB8,0xB8,0xB8,0xBA,0xBA,0xBA,0xBC,0xBC,0xBC,0xBC,0xBE,0xBE,0xBE,0xBE,0xC0,0xC0,
-// 0xC0,0xC0,0xC2,0xC2,0xC2,0xC2,0xC2,0xC4,0xC4,0xC4,0xC4,0xC6,0xC6,0xC6,0xC6,0xC8,
-// 0xC8,0xC8,0xC8,0xC8,0xCA,0xCA,0xCA,0xCA,0xCC,0xCC,0xCC,0xCC,0xCC,0xCE,0xCE,0xCE,
-// 0xCE,0xCE,0xD0,0xD0,0xD0,0xD0,0xD0,0xD2,0xD2,0xD2,0xD2,0xD2,0xD4,0xD4,0xD4,0xD4,
-// 0xD4,0xD6,0xD6,0xD6,0xD6,0xD6,0xD8,0xD8,0xD8,0xD8,0xD8,0xD8,0xDA,0xDA,0xDA,0xDA,
-// 0xDA,0xDC,0xDC,0xDC,0xDC,0xDC,0xDC,0xDE,0xDE,0xDE,0xDE,0xDE,0xDE,0xE0,0xE0,0xE0,
-// };
-//
-// static int32_t Gfl=0,Gfr=0;
-// static int32_t LMax=0,RMax=0;
-//
-// static int32_t LAccum;
-// static int32_t RAccum;
-// static int32_t ANum;
-//
-// int32_t ValL = src.Left >> (SndOutVolumeShift-8);
-// int32_t ValR = src.Right >> (SndOutVolumeShift-8);
-//
-// int32_t XL = abs(ValL>>8);
-// int32_t XR = abs(ValR>>8);
-//
-// if(XL>LMax) LMax = XL;
-// if(XR>RMax) RMax = XR;
-//
-// ANum++;
-// if(ANum>=128)
-// {
-// ANum=0;
-// LAccum = 1+((LAccum * 224 + LMax * 31)>>8);
-// RAccum = 1+((RAccum * 224 + RMax * 31)>>8);
-//
-// LMax = 0;
-// RMax = 0;
-//
-// int32_t Tfl=(RAccum)*255/(LAccum);
-// int32_t Tfr=(LAccum)*255/(RAccum);
-//
-// int gMax = std::max(Tfl,Tfr);
-// Tfl = Tfl*255/gMax;
-// Tfr = Tfr*255/gMax;
-//
-// if(Tfl>255) Tfl=255;
-// if(Tfr>255) Tfr=255;
-// if(Tfl<1) Tfl=1;
-// if(Tfr<1) Tfr=1;
-//
-// Gfl = (Gfl * 200 + Tfl * 56)>>8;
-// Gfr = (Gfr * 200 + Tfr * 56)>>8;
-//
-// }
-//
-// int32_t L,R,C,SUB,SL,SR;
-//
-// C=(ValL+ValR)>>1; //16.8
-//
-// ValL-=C;//16.8
-// ValR-=C;//16.8
-//
-// L=ValL>>8; //16.0
-// R=ValR>>8; //16.0
-// C=C>>8; //16.0
-// SUB = C;
-//
-// {
-// int32_t Cfl = 1+sLogTable[Gfl];
-// int32_t Cfr = 1+sLogTable[Gfr];
-//
-// int32_t VL=(ValL>>4) * Cfl; //16.12
-// int32_t VR=(ValR>>4) * Cfr;
-//
-// //int32_t SC = (VL-VR)>>15;
-//
-// SL = (((VR/148 - VL/209)>>4)*Cfr)>>8;
-// SR = (((VR/209 - VL/148)>>4)*Cfl)>>8;
-//
-// }
-//
-// // Random-ish values to get it to compile
-// int GainL = 200;
-// int GainR = 200;
-// int GainC = 180;
-// int GainSL = 230;
-// int GainSR = 230;
-// int GainLFE = 200;
-// int AddCLR = 55;
-//
-// int AddCX = (C * AddCLR)>>8;
-//
-// Left = (((L * GainL ))>>8) + AddCX;
-// Right = (((R * GainR ))>>8) + AddCX;
-// Center = (((C * GainC ))>>8);
-// LFE = (((SUB * GainLFE))>>8);
-// LeftBack = (((SL * GainSL ))>>8);
-// RightBack = (((SR * GainSR ))>>8);
-// }
-//};
-//
-//struct Stereo71Out16
-//{
-// int16_t Left;
-// int16_t Right;
-// int16_t Center;
-// int16_t LFE;
-// int16_t LeftBack;
-// int16_t RightBack;
-// int16_t LeftSide;
-// int16_t RightSide;
-//
-// void ResampleFrom( const StereoOut32& src )
-// {
-// Left = src.Left >> SndOutVolumeShift;
-// Right = src.Right >> SndOutVolumeShift;
-// Center = (src.Left + src.Right) >> (SndOutVolumeShift + 1);
-// LFE = Center;
-// LeftBack = src.Left >> SndOutVolumeShift;
-// RightBack = src.Right >> SndOutVolumeShift;
-//
-// LeftSide = src.Left >> (SndOutVolumeShift+1);
-// RightSide = src.Right >> (SndOutVolumeShift+1);
-// }
-//};
-//
-//struct Stereo21Out32
-//{
-// int32_t Left;
-// int32_t Right;
-// int32_t LFE;
-//};
-//
-//struct Stereo41Out32
-//{
-// int32_t Left;
-// int32_t Right;
-// int32_t LFE;
-// int32_t LeftBack;
-// int32_t RightBack;
-//};
-//
-//struct Stereo51Out32
-//{
-// int32_t Left;
-// int32_t Right;
-// int32_t Center;
-// int32_t LFE;
-// int32_t LeftBack;
-// int32_t RightBack;
-//};
// Developer Note: This is a static class only (all static members).
class SndBuffer
@@ -379,16 +127,11 @@
static int32_t m_predictData;
static float lastPct;
- static StereoOut32 *sndTempBuffer;
- static StereoOut16 *sndTempBuffer16;
+ static std::unique_ptr<StereoOut32[]> sndTempBuffer;
static int sndTempProgress;
- //static int m_dsp_progress;
-
- //static int m_timestretch_progress;
- static int m_timestretch_writepos;
-
- static StereoOut32 *m_buffer;
+
+ static std::unique_ptr<StereoOut32[]> m_buffer;
static int32_t m_size;
static int32_t m_rpos;
static int32_t m_wpos;
@@ -398,15 +141,12 @@
static float cTempo;
static float eTempo;
static int freezeTempo;
- //static int ssFreeze;
static void _InitFail();
static void _WriteSamples(StereoOut32 *bData, int nSamples);
static bool CheckUnderrunStatus(int &nSamples, int &quietSampleCount);
static void soundtouchInit();
- static void soundtouchClearContents();
- static void soundtouchCleanup();
static void timeStretchWrite();
static void timeStretchUnderrun();
static int32_t timeStretchOverrun();
@@ -417,10 +157,7 @@
public:
static void Init();
- //static void Cleanup();
static void Write(const StereoOut32 &Sample);
- //static int32_t Test();
- //static void ClearContents();
// Note: When using with 32 bit output buffers, the user of this function is responsible
// for shifting the values to where they need to be manually. The fixed point depth of
@@ -450,8 +187,8 @@
// [Air] [TODO]: This loop is probably a candidate for SSE2 optimization.
- const int endPos = m_rpos + nSamples;
- const int secondCopyLen = endPos - m_size;
+ int endPos = m_rpos + nSamples;
+ int secondCopyLen = endPos - m_size;
const StereoOut32 *rposbuffer = &m_buffer[m_rpos];
m_data -= nSamples;
@@ -477,58 +214,5 @@
}
};
-//class SndOutModule
-//{
-//public:
-// // Virtual destructor, because it helps fight C+++ funny-business.
-// virtual ~SndOutModule() {}
-//
-// // Returns a unique identification string for this driver.
-// // (usually just matches the driver's cpp filename)
-// virtual const wchar_t* GetIdent() const=0;
-//
-// // Returns the long name / description for this driver.
-// // (for use in configuration screen)
-// virtual const wchar_t* GetLongName() const=0;
-//
-// virtual int32_t Init()=0;
-// virtual void Close()=0;
-// virtual int32_t Test() const=0;
-//
-// // Gui function: Used to open the configuration box for this driver.
-// virtual void Configure(uptr parent)=0;
-//
-// // Loads settings from the INI file for this driver
-// virtual void ReadSettings()=0;
-//
-// // Saves settings to the INI file for this driver
-// virtual void WriteSettings() const=0;
-//
-// virtual bool Is51Out() const=0;
-//
-// // Returns the number of empty samples in the output buffer.
-// // (which is effectively the amount of data played since the last update)
-// virtual int GetEmptySampleCount() const=0;
-//};
-//
-//
-//#ifdef _MSC_VER
-////internal
-//extern SndOutModule* WaveOut;
-//extern SndOutModule* DSoundOut;
-//extern SndOutModule* XAudio2Out;
-//#endif
-//
-//extern SndOutModule* mods[];
-//
-//// =====================================================================================================
-//
-//extern void RecordStart();
-//extern void RecordStop();
-//extern void RecordWrite( const StereoOut16& sample );
-//
-//extern int32_t DspLoadLibrary(wchar_t *fileName, int modNum);
-//extern void DspCloseLibrary();
-//extern int DspProcess(int16_t *buffer, int samples);
-//extern void DspUpdate(); // to let the Dsp process window messages
-
+#endif
+
--- a/src/in_2sf/desmume/metaspu/SoundTouch/AAFilter.cpp
+++ b/src/in_2sf/desmume/metaspu/SoundTouch/AAFilter.cpp
@@ -42,14 +42,16 @@
#include "XSFCommon.h"
+#include <vector>
#include <cassert>
#include "AAFilter.h"
#include "FIRFilter.h"
using namespace soundtouch;
-#define PI 3.141592655357989
-#define TWOPI (2 * PI)
+#ifndef M_PI
+static const double M_PI = 3.14159265358979323846;
+#endif
/*****************************************************************************
*
@@ -59,14 +61,9 @@
AAFilter::AAFilter(const uint32_t len)
{
- pFIR = FIRFilter::newInstance();
- cutoffFreq = 0.5;
+ this->pFIR.reset(FIRFilter::newInstance());
+ this->cutoffFreq = 0.5;
this->setLength(len);
-}
-
-AAFilter::~AAFilter()
-{
- delete pFIR;
}
// Sets new anti-alias filter cut-off edge frequency, scaled to
@@ -74,43 +71,43 @@
// The filter will cut frequencies higher than the given frequency.
void AAFilter::setCutoffFreq(double newCutoffFreq)
{
- cutoffFreq = newCutoffFreq;
- calculateCoeffs();
+ this->cutoffFreq = newCutoffFreq;
+ this->calculateCoeffs();
}
// Sets number of FIR filter taps
void AAFilter::setLength(uint32_t newLength)
{
- length = newLength;
- calculateCoeffs();
+ this->length = newLength;
+ this->calculateCoeffs();
}
// Calculates coefficients for a low-pass FIR filter using Hamming window
void AAFilter::calculateCoeffs()
{
- assert(length > 0);
- assert(!(length % 4));
- assert(cutoffFreq >= 0);
- assert(cutoffFreq <= 0.5);
+ assert(this->length > 0);
+ assert(!(this->length % 4));
+ assert(this->cutoffFreq >= 0);
+ assert(this->cutoffFreq <= 0.5);
- double *work = new double[length];
- SAMPLETYPE *coeffs = new SAMPLETYPE[length];
+ auto work = std::vector<double>(this->length);
+ auto coeffs = std::vector<SAMPLETYPE>(this->length);
- double fc2 = 2.0 * cutoffFreq;
- double wc = PI * fc2;
- double tempCoeff = TWOPI / length;
+ double fc2 = 2.0 * this->cutoffFreq;
+ double wc = M_PI * fc2;
+ double tempCoeff = 2 * M_PI / this->length;
double sum = 0.0;
- for (uint32_t i = 0; i < length; ++i)
+ for (uint32_t i = 0; i < this->length; ++i)
{
- double cntTemp = i - (length / 2);
+ double cntTemp = i - (this->length / 2);
double temp = cntTemp * wc, h;
if (!fEqual(temp, 0.0))
- h = fc2 * sin(temp) / temp; // sinc function
+ h = fc2 * std::sin(temp) / temp; // sinc function
else
h = 1.0;
- double w = 0.54 + 0.46 * cos(tempCoeff * cntTemp); // hamming window
+ double w = 0.54 + 0.46 * std::cos(tempCoeff * cntTemp); // hamming window
temp = w * h;
work[i] = temp;
@@ -123,15 +120,15 @@
assert(sum > 0);
// ensure we've really designed a lowpass filter...
- assert(work[length / 2] > 0);
- assert(work[length / 2 + 1] > -1e-6);
- assert(work[length / 2 - 1] > -1e-6);
+ assert(work[this->length / 2] > 0);
+ assert(work[this->length / 2 + 1] > -1e-6);
+ assert(work[this->length / 2 - 1] > -1e-6);
// Calculate a scaling coefficient in such a way that the result can be
// divided by 16384
double scaleCoeff = 16384.0 / sum;
- for (uint32_t i = 0; i < length; ++i)
+ for (uint32_t i = 0; i < this->length; ++i)
{
// scale & round to nearest integer
double temp = work[i] * scaleCoeff;
@@ -142,10 +139,7 @@
}
// Set coefficients. Use divide factor 14 => divide result by 2^14 = 16384
- pFIR->setCoefficients(coeffs, length, 14);
-
- delete [] work;
- delete [] coeffs;
+ this->pFIR->setCoefficients(&coeffs[0], length, 14);
}
// Applies the filter to the given sequence of samples.
@@ -153,11 +147,11 @@
// smaller than the amount of input samples.
uint32_t AAFilter::evaluate(SAMPLETYPE *dest, const SAMPLETYPE *src, uint32_t numSamples, uint32_t numChannels) const
{
- return pFIR->evaluate(dest, src, numSamples, numChannels);
+ return this->pFIR->evaluate(dest, src, numSamples, numChannels);
}
uint32_t AAFilter::getLength() const
{
- return pFIR->getLength();
+ return this->pFIR->getLength();
}
--- a/src/in_2sf/desmume/metaspu/SoundTouch/AAFilter.h
+++ b/src/in_2sf/desmume/metaspu/SoundTouch/AAFilter.h
@@ -44,7 +44,7 @@
#ifndef AAFilter_H
#define AAFilter_H
-#include "STTypes.h"
+#include "FIRFilter.h"
namespace soundtouch
{
@@ -52,7 +52,7 @@
class AAFilter
{
protected:
- class FIRFilter *pFIR;
+ std::unique_ptr<FIRFilter> pFIR;
/// Low-pass filter cut-off frequency, negative = invalid
double cutoffFreq;
@@ -65,8 +65,6 @@
public:
AAFilter(uint32_t length);
-
- ~AAFilter();
/// Sets new anti-alias filter cut-off edge frequency, scaled to sampling
/// frequency (nyquist frequency = 0.5). The filter will cut off the
--- a/src/in_2sf/desmume/metaspu/SoundTouch/ConfigSoundtouch.cpp
+++ /dev/null
@@ -1,135 +1,1 @@
-/* SPU2-X, A plugin for Emulating the Sound Processing Unit of the Playstation 2
- * Developed and maintained by the Pcsx2 Development Team.
- *
- * Original portions from SPU2ghz are (c) 2008 by David Quintana [gigaherz]
- *
- * SPU2-X is free software: you can redistribute it and/or modify it under the terms
- * of the GNU Lesser General Public License as published by the Free Software Found-
- * ation, either version 3 of the License, or (at your option) any later version.
- *
- * SPU2-X is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
- * PURPOSE. See the GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with SPU2-X. If not, see <http://www.gnu.org/licenses/>.
- */
-//TODO - need to make a generic way for saving these configs and add in the windows
-//rc configurator
-
-#include "../../types.h"
-//#include "Global.h"
-#include "Dialogs.h"
-
-#include "../metaspu.h"
-
-#include "SoundTouch.h"
-
-static int SequenceLenMS = 63;
-static int SeekWindowMS = 16;
-static int OverlapMS = 7;
-
-// Timestretch Slider Bounds, Min/Max
-static const int SequenceLen_Min = 50;
-static const int SequenceLen_Max = 90;
-
-static const int SeekWindow_Min = 10;
-static const int SeekWindow_Max = 32;
-
-static const int Overlap_Min = 3;
-static const int Overlap_Max = 25;
-
-void SoundtouchCfg::ApplySettings( soundtouch::SoundTouch& sndtouch )
-{
- sndtouch.setSetting( soundtouch::SETTING_SEQUENCE_MS, SequenceLenMS );
- sndtouch.setSetting( soundtouch::SETTING_SEEKWINDOW_MS, SeekWindowMS );
- sndtouch.setSetting( soundtouch::SETTING_OVERLAP_MS, OverlapMS );
-}
-
-/*static void ClampValues()
-{
- Clampify( SequenceLenMS, SequenceLen_Min, SequenceLen_Max );
- Clampify( SeekWindowMS, SeekWindow_Min, SeekWindow_Max );
- Clampify( OverlapMS, Overlap_Min, Overlap_Max );
-}*/
-
-void SoundtouchCfg::ReadSettings()
-{
-/* SequenceLenMS = CfgReadInt( L"SOUNDTOUCH", L"SequenceLengthMS", 50 );
- SeekWindowMS = CfgReadInt( L"SOUNDTOUCH", L"SeekWindowMS", 15 );
- OverlapMS = CfgReadInt( L"SOUNDTOUCH", L"OverlapMS", 25 );
-
- ClampValues(); */
-}
-
-void SoundtouchCfg::WriteSettings()
-{
- //CfgWriteInt( L"SOUNDTOUCH", L"SequenceLengthMS", SequenceLenMS );
- //CfgWriteInt( L"SOUNDTOUCH", L"SeekWindowMS", SeekWindowMS );
- //CfgWriteInt( L"SOUNDTOUCH", L"OverlapMS", OverlapMS );
-}
-
-//BOOL CALLBACK SoundtouchCfg::DialogProc(HWND hWnd,UINT uMsg,WPARAM wParam,LPARAM lParam)
-//{
-// int wmId,wmEvent;
-// wchar_t temp[384]={0};
-//
-// switch(uMsg)
-// {
-// case WM_PAINT:
-// return false;
-//
-// case WM_INITDIALOG:
-// {
-// INIT_SLIDER( IDC_SEQLEN_SLIDER, SequenceLen_Min, SequenceLen_Max, 20, 5, 1 );
-// INIT_SLIDER( IDC_SEEKWIN_SLIDER, SeekWindow_Min, SeekWindow_Max, 5, 2, 1 );
-// INIT_SLIDER( IDC_OVERLAP_SLIDER, Overlap_Min, Overlap_Max, 3, 2, 1 );
-//
-// SendDialogMsg( hWnd, IDC_SEQLEN_SLIDER, TBM_SETPOS, true, SequenceLenMS );
-// SendDialogMsg( hWnd, IDC_SEEKWIN_SLIDER, TBM_SETPOS, true, SeekWindowMS );
-// SendDialogMsg( hWnd, IDC_OVERLAP_SLIDER, TBM_SETPOS, true, OverlapMS );
-// }
-//
-// case WM_COMMAND:
-// wmId = LOWORD(wParam);
-// wmEvent = HIWORD(wParam);
-// // Parse the menu selections:
-// if( wmId == IDOK )
-// {
-// SequenceLenMS = (int)SendDialogMsg( hWnd, IDC_SEQLEN_SLIDER, TBM_GETPOS, 0, 0 );
-// SeekWindowMS = (int)SendDialogMsg( hWnd, IDC_SEEKWIN_SLIDER, TBM_GETPOS, 0, 0 );
-// OverlapMS = (int)SendDialogMsg( hWnd, IDC_OVERLAP_SLIDER, TBM_GETPOS, 0, 0 );
-//
-// ClampValues();
-// WriteSettings();
-// EndDialog(hWnd,0);
-// }
-// else if( wmId == IDCANCEL )
-// {
-// EndDialog(hWnd,0);
-// }
-// break;
-//
-// case WM_HSCROLL:
-// DoHandleScrollMessage( hWnd, wParam, lParam );
-// break;
-//
-// default:
-// return false;
-// }
-// return true;
-//}
-
-void SoundtouchCfg::OpenDialog( HWND hWnd )
-{
- //INT_PTR ret;
- //ret = DialogBox( hInstance, MAKEINTRESOURCE(IDD_CONFIG_SOUNDTOUCH), hWnd, (DLGPROC)DialogProc );
- //if(ret==-1)
- //{
- // MessageBoxEx(GetActiveWindow(), L"Error Opening the Soundtouch advanced dialog.", L"OMG ERROR!", MB_OK, 0);
- // return;
- //}
- //ReadSettings();
-}
-
--- a/src/in_2sf/desmume/metaspu/SoundTouch/Dialogs.h
+++ /dev/null
@@ -1,83 +1,1 @@
-/* SPU2-X, A plugin for Emulating the Sound Processing Unit of the Playstation 2
- * Developed and maintained by the Pcsx2 Development Team.
- *
- * Original portions from SPU2ghz are (c) 2008 by David Quintana [gigaherz]
- *
- * SPU2-X is free software: you can redistribute it and/or modify it under the terms
- * of the GNU Lesser General Public License as published by the Free Software Found-
- * ation, either version 3 of the License, or (at your option) any later version.
- *
- * SPU2-X is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
- * PURPOSE. See the GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with SPU2-X. If not, see <http://www.gnu.org/licenses/>.
- */
-#pragma once
-#ifdef _XBOX
-#include <xtl.h>
-#elif _WIN32
-#include "windowsh_wrapper.h"
-#endif
-
-#include "../SoundTouch/SoundTouch.h"
-
-//#ifdef _WIN32
-//# include "WinConfig.h"
-//#else
-//# include "LnxConfig.h"
-//#endif
-//
-//namespace DebugConfig
-//{
-// extern void ReadSettings();
-// extern void WriteSettings();
-// extern void OpenDialog();
-// extern void EnableControls( HWND hWnd );
-//}
-//
-namespace SoundtouchCfg
-{
- extern void ReadSettings();
- extern void WriteSettings();
- extern void OpenDialog(HWND hWnd);
- extern bool CALLBACK DialogProc(HWND hWnd, UINT uMsg, WPARAM wParam, LPARAM lParam);
- extern void ApplySettings(soundtouch::SoundTouch& sndtouch);
-}
-//
-//extern int SendDialogMsg( HWND hwnd, int dlgId, UINT code, WPARAM wParam, LPARAM lParam);
-//extern HRESULT GUIDFromString( const char *str, LPGUID guid );
-//
-//extern void AssignSliderValue( HWND idcwnd, HWND hwndDisplay, int value );
-//extern void AssignSliderValue( HWND hWnd, int idc, int editbox, int value );
-//extern int GetSliderValue( HWND hWnd, int idc );
-//extern bool DoHandleScrollMessage( HWND hwndDisplay, WPARAM wParam, LPARAM lParam );
-//
-//extern bool CfgFindName( const TCHAR *Section, const TCHAR* Name);
-//
-//extern void CfgWriteBool(const TCHAR* Section, const TCHAR* Name, bool Value);
-//extern void CfgWriteInt(const TCHAR* Section, const TCHAR* Name, int Value);
-//extern void CfgWriteStr(const TCHAR* Section, const TCHAR* Name, const wstring& Data);
-//
-//extern bool CfgReadBool(const TCHAR *Section,const TCHAR* Name, bool Default);
-//extern void CfgReadStr(const TCHAR* Section, const TCHAR* Name, wstring& Data, int DataSize, const TCHAR* Default);
-//extern void CfgReadStr(const TCHAR* Section, const TCHAR* Name, TCHAR* Data, int DataSize, const TCHAR* Default);
-//extern int CfgReadInt(const TCHAR* Section, const TCHAR* Name,int Default);
-//
-//
-//// Items Specific to DirectSound
-//#define STRFY(x) #x
-//#define verifyc(x) Verifyc(x,STRFY(x))
-//
-//extern void Verifyc(HRESULT hr, const char* fn);
-//
-//struct ds_device_data
-//{
-// std::wstring name;
-// GUID guid;
-// bool hasGuid;
-//};
-//
-
--- a/src/in_2sf/desmume/metaspu/SoundTouch/FIFOSampleBuffer.cpp
+++ b/src/in_2sf/desmume/metaspu/SoundTouch/FIFOSampleBuffer.cpp
@@ -15,10 +15,10 @@
///
////////////////////////////////////////////////////////////////////////////////
//
-// Last changed : $Date: 2006/02/05 16:44:06 $
-// File revision : $Revision: 1.11 $
-//
-// $Id: FIFOSampleBuffer.cpp,v 1.11 2006/02/05 16:44:06 Olli Exp $
+// Last changed : $Date: 2012-11-08 16:53:01 -0200 (qui, 08 nov 2012) $
+// File revision : $Revision: 4 $
+//
+// $Id: FIFOSampleBuffer.cpp 160 2012-11-08 18:53:01Z oparviai $
//
////////////////////////////////////////////////////////////////////////////////
//
@@ -45,35 +45,35 @@
#include <stdexcept>
#include <cstring>
-
#include "FIFOSampleBuffer.h"
using namespace soundtouch;
// Constructor
-FIFOSampleBuffer::FIFOSampleBuffer(uint32_t numChannels)
-{
- sizeInBytes = 0; // reasonable initial value
- buffer = NULL; //new SAMPLETYPE[sizeInBytes / sizeof(SAMPLETYPE)];
- bufferUnaligned = NULL;
- samplesInBuffer = 0;
- bufferPos = 0;
- channels = numChannels;
+FIFOSampleBuffer::FIFOSampleBuffer(int32_t numChannels)
+{
+ assert(numChannels > 0);
+ this->sizeInBytes = 0; // reasonable initial value
+ this->buffer = nullptr;
+ this->bufferUnaligned.reset();
+ this->samplesInBuffer = 0;
+ this->bufferPos = 0;
+ this->channels = static_cast<uint32_t>(numChannels);
+ this->ensureCapacity(32); // allocate initial capacity
}
// destructor
FIFOSampleBuffer::~FIFOSampleBuffer()
{
- if (bufferUnaligned)
- delete[] bufferUnaligned;
}
// Sets number of channels, 1 = mono, 2 = stereo
-void FIFOSampleBuffer::setChannels(uint32_t numChannels)
-{
- uint32_t usedBytes = channels * samplesInBuffer;
- channels = numChannels;
- samplesInBuffer = usedBytes / channels;
+void FIFOSampleBuffer::setChannels(int32_t numChannels)
+{
+ assert(numChannels > 0);
+ uint32_t usedBytes = this->channels * this->samplesInBuffer;
+ this->channels = static_cast<uint32_t>(numChannels);
+ this->samplesInBuffer = usedBytes / this->channels;
}
// if output location pointer 'bufferPos' isn't zero, 'rewinds' the buffer and
@@ -81,19 +81,19 @@
// location on to the beginning of the buffer.
void FIFOSampleBuffer::rewind()
{
- if (bufferPos)
+ if (this->buffer && this->bufferPos)
{
- memmove(buffer, ptrBegin(), sizeof(SAMPLETYPE) * channels * samplesInBuffer);
- bufferPos = 0;
+ memmove(this->buffer, this->ptrBegin(), sizeof(SAMPLETYPE) * this->channels * this->samplesInBuffer);
+ this->bufferPos = 0;
}
}
// Adds 'numSamples' pcs of samples from the 'samples' memory position to
// the sample buffer.
-void FIFOSampleBuffer::putSamples(const SAMPLETYPE *samples, uint32_t numsamples)
-{
- memcpy(ptrEnd(numsamples), samples, sizeof(SAMPLETYPE) * numsamples * channels);
- samplesInBuffer += numsamples;
+void FIFOSampleBuffer::putSamples(const SAMPLETYPE *samples, uint32_t nSamples)
+{
+ memcpy(this->ptrEnd(nSamples), samples, sizeof(SAMPLETYPE) * nSamples * this->channels);
+ this->samplesInBuffer += nSamples;
}
// Increases the number of samples in the buffer without copying any actual
@@ -102,11 +102,11 @@
// This function is used to update the number of samples in the sample buffer
// when accessing the buffer directly with 'ptrEnd' function. Please be
// careful though!
-void FIFOSampleBuffer::putSamples(uint32_t numsamples)
-{
- uint32_t req = samplesInBuffer + numsamples;
+void FIFOSampleBuffer::putSamples(uint32_t nSamples)
+{
+ uint32_t req = this->samplesInBuffer + nSamples;
this->ensureCapacity(req);
- samplesInBuffer += numsamples;
+ this->samplesInBuffer += nSamples;
}
// Returns a pointer to the end of the used part of the sample buffer (i.e.
@@ -123,8 +123,8 @@
// 'putSamples(numSamples)' function.
SAMPLETYPE *FIFOSampleBuffer::ptrEnd(uint32_t slackCapacity)
{
- this->ensureCapacity(samplesInBuffer + slackCapacity);
- return buffer + samplesInBuffer * channels;
+ this->ensureCapacity(this->samplesInBuffer + slackCapacity);
+ return &this->buffer[this->samplesInBuffer * this->channels];
}
// Returns a pointer to the beginning of the currently non-outputted samples.
@@ -134,9 +134,10 @@
// When using this function to output samples, also remember to 'remove' the
// outputted samples from the buffer by calling the
// 'receiveSamples(numSamples)' function
-SAMPLETYPE *FIFOSampleBuffer::ptrBegin() const
-{
- return buffer + bufferPos * channels;
+SAMPLETYPE *FIFOSampleBuffer::ptrBegin()
+{
+ assert(this->buffer);
+ return &this->buffer[this->bufferPos * this->channels];
}
// Ensures that the buffer has enought capacity, i.e. space for _at least_
@@ -145,34 +146,35 @@
// as well as to round the buffer size up to the virtual memory page size.
void FIFOSampleBuffer::ensureCapacity(uint32_t capacityRequirement)
{
- if (capacityRequirement > getCapacity())
+ if (capacityRequirement > this->getCapacity())
{
// enlarge the buffer in 4kbyte steps (round up to next 4k boundary)
- sizeInBytes = (capacityRequirement * channels * sizeof(SAMPLETYPE) + 4095) & -4096;
- assert(!(sizeInBytes % 2));
- SAMPLETYPE *tempUnaligned = new SAMPLETYPE[sizeInBytes / sizeof(SAMPLETYPE) + 16 / sizeof(SAMPLETYPE)];
- SAMPLETYPE *temp = reinterpret_cast<SAMPLETYPE *>((reinterpret_cast<intptr_t>(tempUnaligned) + 15) & -16);
- memcpy(temp, ptrBegin(), samplesInBuffer * channels * sizeof(SAMPLETYPE));
- delete[] bufferUnaligned;
- buffer = temp;
- bufferUnaligned = tempUnaligned;
- bufferPos = 0;
+ this->sizeInBytes = (capacityRequirement * this->channels * sizeof(SAMPLETYPE) + 4095) & static_cast<uint32_t>(-4096);
+ assert(!(this->sizeInBytes % 2));
+ auto tempUnaligned = std::unique_ptr<SAMPLETYPE[]>(new SAMPLETYPE[(this->sizeInBytes + 16) / sizeof(SAMPLETYPE)]);
+ // Align the buffer to begin at 16byte cache line boundary for optimal performance
+ SAMPLETYPE *temp = reinterpret_cast<SAMPLETYPE *>(SOUNDTOUCH_ALIGN_POINTER_16(tempUnaligned.get()));
+ if (samplesInBuffer)
+ memcpy(temp, this->ptrBegin(), samplesInBuffer * this->channels * sizeof(SAMPLETYPE));
+ this->buffer = temp;
+ this->bufferUnaligned = std::move(tempUnaligned);
+ this->bufferPos = 0;
}
else
// simply rewind the buffer (if necessary)
- rewind();
+ this->rewind();
}
// Returns the current buffer capacity in terms of samples
uint32_t FIFOSampleBuffer::getCapacity() const
{
- return sizeInBytes / (channels * sizeof(SAMPLETYPE));
+ return this->sizeInBytes / (this->channels * sizeof(SAMPLETYPE));
}
// Returns the number of samples currently in the buffer
uint32_t FIFOSampleBuffer::numSamples() const
{
- return samplesInBuffer;
+ return this->samplesInBuffer;
}
// Output samples from beginning of the sample buffer. Copies demanded number
@@ -182,9 +184,9 @@
// Returns number of samples copied.
uint32_t FIFOSampleBuffer::receiveSamples(SAMPLETYPE *output, uint32_t maxSamples)
{
- uint32_t num = maxSamples > samplesInBuffer ? samplesInBuffer : maxSamples;
-
- memcpy(output, ptrBegin(), channels * sizeof(SAMPLETYPE) * num);
+ uint32_t num = maxSamples > this->samplesInBuffer ? this->samplesInBuffer : maxSamples;
+
+ memcpy(output, this->ptrBegin(), this->channels * sizeof(SAMPLETYPE) * num);
return this->receiveSamples(num);
}
@@ -193,15 +195,15 @@
// the sample buffer with the 'ptrBegin' function.
uint32_t FIFOSampleBuffer::receiveSamples(uint32_t maxSamples)
{
- if (maxSamples >= samplesInBuffer)
+ if (maxSamples >= this->samplesInBuffer)
{
- uint32_t temp = samplesInBuffer;
- samplesInBuffer = 0;
+ uint32_t temp = this->samplesInBuffer;
+ this->samplesInBuffer = 0;
return temp;
}
- samplesInBuffer -= maxSamples;
- bufferPos += maxSamples;
+ this->samplesInBuffer -= maxSamples;
+ this->bufferPos += maxSamples;
return maxSamples;
}
@@ -209,13 +211,22 @@
// Returns nonzero if the sample buffer is empty
bool FIFOSampleBuffer::isEmpty() const
{
- return !samplesInBuffer;
+ return !this->samplesInBuffer;
}
// Clears the sample buffer
void FIFOSampleBuffer::clear()
{
- samplesInBuffer = 0;
- bufferPos = 0;
-}
-
+ this->samplesInBuffer = 0;
+ this->bufferPos = 0;
+}
+
+/// allow trimming (downwards) amount of samples in pipeline.
+/// Returns adjusted amount of samples
+uint32_t FIFOSampleBuffer::adjustAmountOfSamples(uint32_t numSamples)
+{
+ if (numSamples < this->samplesInBuffer)
+ this->samplesInBuffer = numSamples;
+ return this->samplesInBuffer;
+}
+
--- a/src/in_2sf/desmume/metaspu/SoundTouch/FIFOSampleBuffer.h
+++ b/src/in_2sf/desmume/metaspu/SoundTouch/FIFOSampleBuffer.h
@@ -15,10 +15,10 @@
///
////////////////////////////////////////////////////////////////////////////////
//
-// Last changed : $Date: 2006/02/05 16:44:06 $
-// File revision : $Revision: 1.9 $
+// Last changed : $Date: 2012-06-13 16:29:53 -0300 (qua, 13 jun 2012) $
+// File revision : $Revision: 4 $
//
-// $Id: FIFOSampleBuffer.h,v 1.9 2006/02/05 16:44:06 Olli Exp $
+// $Id: FIFOSampleBuffer.h 143 2012-06-13 19:29:53Z oparviai $
//
////////////////////////////////////////////////////////////////////////////////
//
@@ -46,6 +46,7 @@
#ifndef FIFOSampleBuffer_H
#define FIFOSampleBuffer_H
+#include <memory>
#include "FIFOSamplePipe.h"
namespace soundtouch
@@ -64,7 +65,7 @@
// Raw unaligned buffer memory. 'buffer' is made aligned by pointing it to first
// 16-byte aligned location of this buffer
- SAMPLETYPE *bufferUnaligned;
+ std::unique_ptr<SAMPLETYPE[]> bufferUnaligned;
/// Sample buffer size in bytes
uint32_t sizeInBytes;
@@ -85,19 +86,19 @@
void rewind();
/// Ensures that the buffer has capacity for at least this many samples.
- void ensureCapacity(const uint32_t capacityRequirement);
+ void ensureCapacity(uint32_t capacityRequirement);
/// Returns current capacity.
uint32_t getCapacity() const;
public:
/// Constructor
- FIFOSampleBuffer(uint32_t numChannels = 2 ///< Number of channels, 1=mono, 2=stereo.
+ FIFOSampleBuffer(int32_t numChannels = 2 ///< Number of channels, 1=mono, 2=stereo.
///< Default is stereo.
);
/// destructor
- ~FIFOSampleBuffer();
+ virtual ~FIFOSampleBuffer();
/// Returns a pointer to the beginning of the output samples.
/// This function is provided for accessing the output samples directly.
@@ -106,7 +107,7 @@
/// When using this function to output samples, also remember to 'remove' the
/// output samples from the buffer by calling the
/// 'receiveSamples(numSamples)' function
- virtual SAMPLETYPE *ptrBegin() const;
+ virtual SAMPLETYPE *ptrBegin();
/// Returns a pointer to the end of the used part of the sample buffer (i.e.
/// where the new samples are to be inserted). This function may be used for
@@ -159,15 +160,19 @@
virtual uint32_t numSamples() const;
/// Sets number of channels, 1 = mono, 2 = stereo.
- void setChannels(uint32_t numChannels);
+ void setChannels(int32_t numChannels);
/// Returns nonzero if there aren't any samples available for outputting.
virtual bool isEmpty() const;
/// Clears all the samples.
virtual void clear();
+
+ /// allow trimming (downwards) amount of samples in pipeline.
+ /// Returns adjusted amount of samples
+ uint32_t adjustAmountOfSamples(uint32_t numSamples);
};
-
+
}
#endif
--- a/src/in_2sf/desmume/metaspu/SoundTouch/FIFOSamplePipe.h
+++ b/src/in_2sf/desmume/metaspu/SoundTouch/FIFOSamplePipe.h
@@ -17,10 +17,10 @@
///
////////////////////////////////////////////////////////////////////////////////
//
-// Last changed : $Date: 2006/02/05 16:44:06 $
-// File revision : $Revision: 1.8 $
-//
-// $Id: FIFOSamplePipe.h,v 1.8 2006/02/05 16:44:06 Olli Exp $
+// Last changed : $Date: 2012-06-13 16:29:53 -0300 (qua, 13 jun 2012) $
+// File revision : $Revision: 4 $
+//
+// $Id: FIFOSamplePipe.h 143 2012-06-13 19:29:53Z oparviai $
//
////////////////////////////////////////////////////////////////////////////////
//
@@ -49,7 +49,6 @@
#define FIFOSamplePipe_H
#include <cassert>
-#include <cstdlib>
#include "STTypes.h"
namespace soundtouch
@@ -59,6 +58,9 @@
class FIFOSamplePipe
{
public:
+ // virtual default destructor
+ virtual ~FIFOSamplePipe() { }
+
/// Returns a pointer to the beginning of the output samples.
/// This function is provided for accessing the output samples directly.
/// Please be careful for not to corrupt the book-keeping!
@@ -66,12 +68,12 @@
/// When using this function to output samples, also remember to 'remove' the
/// output samples from the buffer by calling the
/// 'receiveSamples(numSamples)' function
- virtual SAMPLETYPE *ptrBegin() const = 0;
+ virtual SAMPLETYPE *ptrBegin() = 0;
/// Adds 'numSamples' pcs of samples from the 'samples' memory position to
/// the sample buffer.
virtual void putSamples(const SAMPLETYPE *samples, ///< Pointer to samples.
- uint32_t numSamples ///< Number of samples to insert.
+ uint32_t numSamples ///< Number of samples to insert.
) = 0;
// Moves samples from the 'other' pipe instance to this instance.
@@ -109,6 +111,10 @@
/// Clears all the samples.
virtual void clear() = 0;
+
+ /// allow trimming (downwards) amount of samples in pipeline.
+ /// Returns adjusted amount of samples
+ virtual uint32_t adjustAmountOfSamples(uint32_t numSamples) = 0;
};
/// Base-class for sound processing routines working in FIFO principle. With this base
@@ -128,23 +134,23 @@
/// Sets output pipe.
void setOutPipe(FIFOSamplePipe *pOutput)
{
- assert(!output);
+ assert(!this->output);
assert(pOutput);
- output = pOutput;
+ this->output = pOutput;
}
/// Constructor. Doesn't define output pipe; it has to be set be
/// 'setOutPipe' function.
FIFOProcessor()
{
- output = NULL;
+ this->output = nullptr;
}
/// Constructor. Configures output pipe.
FIFOProcessor(FIFOSamplePipe *pOutput ///< Output pipe.
)
{
- output = pOutput;
+ this->output = pOutput;
}
/// Destructor.
@@ -159,9 +165,9 @@
/// When using this function to output samples, also remember to 'remove' the
/// output samples from the buffer by calling the
/// 'receiveSamples(numSamples)' function
- virtual SAMPLETYPE *ptrBegin() const
- {
- return output->ptrBegin();
+ virtual SAMPLETYPE *ptrBegin()
+ {
+ return this->output->ptrBegin();
}
public:
@@ -174,7 +180,7 @@
uint32_t maxSamples ///< How many samples to receive at max.
)
{
- return output->receiveSamples(outBuffer, maxSamples);
+ return this->output->receiveSamples(outBuffer, maxSamples);
}
/// Adjusts book-keeping so that given number of samples are removed from beginning of the
@@ -185,19 +191,26 @@
virtual uint32_t receiveSamples(uint32_t maxSamples ///< Remove this many samples from the beginning of pipe.
)
{
- return output->receiveSamples(maxSamples);
+ return this->output->receiveSamples(maxSamples);
}
/// Returns number of samples currently available.
virtual uint32_t numSamples() const
{
- return output->numSamples();
+ return this->output->numSamples();
}
/// Returns nonzero if there aren't any samples available for outputting.
virtual bool isEmpty() const
{
- return output->isEmpty();
+ return this->output->isEmpty();
+ }
+
+ /// allow trimming (downwards) amount of samples in pipeline.
+ /// Returns adjusted amount of samples
+ virtual uint32_t adjustAmountOfSamples(uint32_t numSamples)
+ {
+ return this->output->adjustAmountOfSamples(numSamples);
}
};
--- a/src/in_2sf/desmume/metaspu/SoundTouch/FIRFilter.cpp
+++ b/src/in_2sf/desmume/metaspu/SoundTouch/FIRFilter.cpp
@@ -11,10 +11,10 @@
///
////////////////////////////////////////////////////////////////////////////////
//
-// Last changed : $Date: 2006/02/05 16:44:06 $
-// File revision : $Revision: 1.16 $
-//
-// $Id: FIRFilter.cpp,v 1.16 2006/02/05 16:44:06 Olli Exp $
+// Last changed : $Date: 2011-09-02 15:56:11 -0300 (sex, 02 set 2011) $
+// File revision : $Revision: 4 $
+//
+// $Id: FIRFilter.cpp 131 2011-09-02 18:56:11Z oparviai $
//
////////////////////////////////////////////////////////////////////////////////
//
@@ -43,7 +43,6 @@
#include <cstring>
#include <cassert>
#include <cmath>
-
#include "FIRFilter.h"
#include "cpu_detect.h"
@@ -57,52 +56,48 @@
FIRFilter::FIRFilter()
{
- resultDivFactor = 0;
- length = 0;
- lengthDiv8 = 0;
- filterCoeffs = NULL;
+ this->resultDivFactor = 0;
+ this->resultDivider = 0;
+ this->length = 0;
+ this->lengthDiv8 = 0;
+ this->filterCoeffs.reset();
}
FIRFilter::~FIRFilter()
{
- if (filterCoeffs)
- delete[] filterCoeffs;
}
// Usual C-version of the filter routine for stereo sound
uint32_t FIRFilter::evaluateFilterStereo(SAMPLETYPE *dest, const SAMPLETYPE *src, uint32_t numSamples) const
{
-#ifdef FLOAT_SAMPLES
+#ifdef SOUNDTOUCH_FLOAT_SAMPLES
// when using floating point samples, use a scaler instead of a divider
// because division is much slower operation than multiplying.
- double dScaler = 1.0 / resultDivider;
+ double dScaler = 1.0 / this->resultDivider;
#endif
- assert(length);
-
- uint32_t end = 2 * (numSamples - length);
+ assert(this->length);
+ assert(!!src);
+ assert(!!dest);
+ assert(!!filterCoeffs);
+
+ uint32_t end = 2 * (numSamples - this->length);
for (uint32_t j = 0; j < end; j += 2)
{
LONG_SAMPLETYPE suml = 0, sumr = 0;
- const SAMPLETYPE *ptr = src + j;
+ const SAMPLETYPE *ptr = &src[j];
for (uint32_t i = 0; i < length; i += 4)
{
// loop is unrolled by factor of 4 here for efficiency
- suml += ptr[2 * i] * filterCoeffs[i] +
- ptr[2 * i + 2] * filterCoeffs[i + 1] +
- ptr[2 * i + 4] * filterCoeffs[i + 2] +
- ptr[2 * i + 6] * filterCoeffs[i + 3];
- sumr += ptr[2 * i + 1] * filterCoeffs[i] +
- ptr[2 * i + 3] * filterCoeffs[i + 1] +
- ptr[2 * i + 5] * filterCoeffs[i + 2] +
- ptr[2 * i + 7] * filterCoeffs[i + 3];
+ suml += ptr[2 * i] * filterCoeffs[i] + ptr[2 * i + 2] * filterCoeffs[i + 1] + ptr[2 * i + 4] * filterCoeffs[i + 2] + ptr[2 * i + 6] * filterCoeffs[i + 3];
+ sumr += ptr[2 * i + 1] * filterCoeffs[i] + ptr[2 * i + 3] * filterCoeffs[i + 1] + ptr[2 * i + 5] * filterCoeffs[i + 2] + ptr[2 * i + 7] * filterCoeffs[i + 3];
}
-#ifdef INTEGER_SAMPLES
- suml >>= resultDivFactor;
- sumr >>= resultDivFactor;
+#ifdef SOUNDTOUCH_INTEGER_SAMPLES
+ suml >>= this->resultDivFactor;
+ sumr >>= this->resultDivFactor;
// saturate to 16 bit integer limits
suml = suml < -32768 ? -32768 : (suml > 32767 ? 32767 : suml);
// saturate to 16 bit integer limits
@@ -110,23 +105,23 @@
#else
suml *= dScaler;
sumr *= dScaler;
-#endif // INTEGER_SAMPLES
+#endif // SOUNDTOUCH_INTEGER_SAMPLES
dest[j] = static_cast<SAMPLETYPE>(suml);
dest[j + 1] = static_cast<SAMPLETYPE>(sumr);
}
- return numSamples - length;
+ return numSamples - this->length;
}
// Usual C-version of the filter routine for mono sound
uint32_t FIRFilter::evaluateFilterMono(SAMPLETYPE *dest, const SAMPLETYPE *src, uint32_t numSamples) const
{
-#ifdef FLOAT_SAMPLES
+#ifdef SOUNDTOUCH_FLOAT_SAMPLES
// when using floating point samples, use a scaler instead of a divider
// because division is much slower operation than multiplying.
- double dScaler = 1.0 / resultDivider;
+ double dScaler = 1.0 / this->resultDivider;
#endif
- assert(length);
+ assert(this->length);
uint32_t end = numSamples - length;
for (uint32_t j = 0; j < end; ++j)
@@ -135,18 +130,15 @@
for (uint32_t i = 0; i < length; i += 4)
{
// loop is unrolled by factor of 4 here for efficiency
- sum += src[i] * filterCoeffs[i] +
- src[i + 1] * filterCoeffs[i + 1] +
- src[i + 2] * filterCoeffs[i + 2] +
- src[i + 3] * filterCoeffs[i + 3];
+ sum += src[i] * filterCoeffs[i] + src[i + 1] * filterCoeffs[i + 1] + src[i + 2] * filterCoeffs[i + 2] + src[i + 3] * filterCoeffs[i + 3];
}
-#ifdef INTEGER_SAMPLES
- sum >>= resultDivFactor;
+#ifdef SOUNDTOUCH_INTEGER_SAMPLES
+ sum >>= this->resultDivFactor;
// saturate to 16 bit integer limits
sum = sum < -32768 ? -32768 : (sum > 32767 ? 32767 : sum);
#else
sum *= dScaler;
-#endif // INTEGER_SAMPLES
+#endif // SOUNDTOUCH_INTEGER_SAMPLES
dest[j] = static_cast<SAMPLETYPE>(sum);
++src;
}
@@ -162,25 +154,20 @@
if (newLength % 8)
throw std::runtime_error("FIR filter length not divisible by 8");
- lengthDiv8 = newLength / 8;
- length = lengthDiv8 * 8;
- assert(length == newLength);
-
- resultDivFactor = uResultDivFactor;
-#ifdef INTEGER_SAMPLES
- resultDivider = static_cast<SAMPLETYPE>(1 << resultDivFactor);
-#else
- resultDivider = static_cast<SAMPLETYPE>(pow(2, static_cast<SAMPLETYPE>(resultDivFactor)));
-#endif
-
- delete[] filterCoeffs;
- filterCoeffs = new SAMPLETYPE[length];
- memcpy(filterCoeffs, coeffs, length * sizeof(SAMPLETYPE));
+ this->lengthDiv8 = newLength / 8;
+ this->length = this->lengthDiv8 * 8;
+ assert(this->length == newLength);
+
+ this->resultDivFactor = uResultDivFactor;
+ this->resultDivider = static_cast<SAMPLETYPE>(std::pow(2.0, static_cast<double>(resultDivFactor)));
+
+ this->filterCoeffs.reset(new SAMPLETYPE[this->length]);
+ memcpy(this->filterCoeffs.get(), coeffs, this->length * sizeof(SAMPLETYPE));
}
uint32_t FIRFilter::getLength() const
{
- return length;
+ return this->length;
}
// Applies the filter to the given sequence of samples.
@@ -191,15 +178,14 @@
{
assert(numChannels == 1 || numChannels == 2);
- assert(length > 0);
- assert(lengthDiv8 * 8 == length);
- if (numSamples < length)
+ assert(this->length > 0);
+ assert(this->lengthDiv8 * 8 == this->length);
+ if (numSamples < this->length)
return 0;
- //assert(resultDivFactor >= 0);
if (numChannels == 2)
- return evaluateFilterStereo(dest, src, numSamples);
+ return this->evaluateFilterStereo(dest, src, numSamples);
else
- return evaluateFilterMono(dest, src, numSamples);
+ return this->evaluateFilterMono(dest, src, numSamples);
}
// Operator 'new' is overloaded so that it automatically creates a suitable instance
@@ -212,31 +198,22 @@
FIRFilter *FIRFilter::newInstance()
{
- uint32_t uExtensions = 0;
-
-#if !defined(_MSC_VER) || !defined(__x86_64__)
- uExtensions = detectCPUextensions();
-#endif
- // Check if MMX/SSE/3DNow! instruction set extensions supported by CPU
-
-#ifdef ALLOW_MMX
+ uint32_t uExtensions = detectCPUextensions();
+
+ // Check if MMX/SSE instruction set extensions supported by CPU
+
+#ifdef SOUNDTOUCH_ALLOW_MMX
// MMX routines available only with integer sample types
if (uExtensions & SUPPORT_MMX)
return ::new FIRFilterMMX;
else
-#endif // ALLOW_MMX
-#ifdef __SSE__
+#endif // SOUNDTOUCH_ALLOW_MMX
+#ifdef SOUNDTOUCH_ALLOW_SSE
if (uExtensions & SUPPORT_SSE)
// SSE support
return ::new FIRFilterSSE;
else
-#endif // ALLOW_SSE
-#ifdef ALLOW_3DNOW
- if (uExtensions & SUPPORT_3DNOW)
- // 3DNow! support
- return ::new FIRFilter3DNow;
- else
-#endif // ALLOW_3DNOW
+#endif // SOUNDTOUCH_ALLOW_SSE
// ISA optimizations not supported, use plain C version
return ::new FIRFilter;
}
--- a/src/in_2sf/desmume/metaspu/SoundTouch/FIRFilter.h
+++ b/src/in_2sf/desmume/metaspu/SoundTouch/FIRFilter.h
@@ -11,10 +11,10 @@
///
////////////////////////////////////////////////////////////////////////////////
//
-// Last changed : $Date: 2006/02/05 16:44:06 $
-// File revision : $Revision: 1.17 $
+// Last changed : $Date: 2011-02-13 17:13:57 -0200 (dom, 13 fev 2011) $
+// File revision : $Revision: 4 $
//
-// $Id: FIRFilter.h,v 1.17 2006/02/05 16:44:06 Olli Exp $
+// $Id: FIRFilter.h 104 2011-02-13 19:13:57Z oparviai $
//
////////////////////////////////////////////////////////////////////////////////
//
@@ -42,8 +42,7 @@
#ifndef FIRFilter_H
#define FIRFilter_H
-#include <cstddef>
-
+#include <memory>
#include "STTypes.h"
namespace soundtouch
@@ -64,7 +63,7 @@
SAMPLETYPE resultDivider;
// Memory for filter coefficients
- SAMPLETYPE *filterCoeffs;
+ std::unique_ptr<SAMPLETYPE[]> filterCoeffs;
virtual uint32_t evaluateFilterStereo(SAMPLETYPE *dest, const SAMPLETYPE *src, uint32_t numSamples) const;
virtual uint32_t evaluateFilterMono(SAMPLETYPE *dest, const SAMPLETYPE *src, uint32_t numSamples) const;
@@ -75,7 +74,7 @@
/// Operator 'new' is overloaded so that it automatically creates a suitable instance
/// depending on if we've a MMX-capable CPU available or not.
- void *operator new(size_t s);
+ static void *operator new(size_t s);
static FIRFilter *newInstance();
@@ -93,12 +92,12 @@
// Optional subclasses that implement CPU-specific optimizations:
-#ifdef ALLOW_MMX
+#ifdef SOUNDTOUCH_ALLOW_MMX
/// Class that implements MMX optimized functions exclusive for 16bit integer samples type.
class FIRFilterMMX : public FIRFilter
{
protected:
- short *filterCoeffsUnalign;
+ std::unique_ptr<short[]> filterCoeffsUnalign;
short *filterCoeffsAlign;
virtual uint32_t evaluateFilterStereo(short *dest, const short *src, uint32_t numSamples) const;
@@ -108,31 +107,14 @@
virtual void setCoefficients(const short *coeffs, uint32_t newLength, uint32_t uResultDivFactor);
};
-#endif // ALLOW_MMX
+#endif // SOUNDTOUCH_ALLOW_MMX
-#ifdef ALLOW_3DNOW
-/// Class that implements 3DNow! optimized functions exclusive for floating point samples type.
-class FIRFilter3DNow : public FIRFilter
-{
-protected:
- float *filterCoeffsUnalign;
- float *filterCoeffsAlign;
-
- virtual uint32_t evaluateFilterStereo(float *dest, const float *src, uint32_t numSamples) const;
-public:
- FIRFilter3DNow();
- ~FIRFilter3DNow();
-
- virtual void setCoefficients(const float *coeffs, uint32_t newLength, uint32_t uResultDivFactor);
-};
-#endif // ALLOW_3DNOW
-
-#ifdef __SSE__
+#ifdef SOUNDTOUCH_ALLOW_SSE
/// Class that implements SSE optimized functions exclusive for floating point samples type.
class FIRFilterSSE : public FIRFilter
{
protected:
- float *filterCoeffsUnalign;
+ std::unique_ptr<float[]> filterCoeffsUnalign;
float *filterCoeffsAlign;
virtual uint32_t evaluateFilterStereo(float *dest, const float *src, uint32_t numSamples) const;
@@ -142,7 +124,7 @@
virtual void setCoefficients(const float *coeffs, uint32_t newLength, uint32_t uResultDivFactor);
};
-#endif // ALLOW_SSE
+#endif // SOUNDTOUCH_ALLOW_SSE
}
--- a/src/in_2sf/desmume/metaspu/SoundTouch/RateTransposer.cpp
+++ b/src/in_2sf/desmume/metaspu/SoundTouch/RateTransposer.cpp
@@ -10,10 +10,10 @@
///
////////////////////////////////////////////////////////////////////////////////
//
-// Last changed : $Date: 2006/03/19 10:05:49 $
-// File revision : $Revision: 1.13 $
-//
-// $Id: RateTransposer.cpp,v 1.13 2006/03/19 10:05:49 Olli Exp $
+// Last changed : $Date: 2011-09-02 15:56:11 -0300 (sex, 02 set 2011) $
+// File revision : $Revision: 4 $
+//
+// $Id: RateTransposer.cpp 131 2011-09-02 18:56:11Z oparviai $
//
////////////////////////////////////////////////////////////////////////////////
//
@@ -50,7 +50,7 @@
{
protected:
int iSlopeCount;
- uint32_t uRate;
+ int iRate;
SAMPLETYPE sPrevSampleL, sPrevSampleR;
virtual void resetRegisters();
@@ -73,7 +73,6 @@
{
protected:
float fSlopeCount;
- float fRateStep;
SAMPLETYPE sPrevSampleL, sPrevSampleR;
virtual void resetRegisters();
@@ -86,253 +85,195 @@
virtual ~RateTransposerFloat();
};
-/*#ifndef min
-#define min(a,b) ((a > b) ? b : a)
-#define max(a,b) ((a < b) ? b : a)
-#endif*/
-
-
// Operator 'new' is overloaded so that it automatically creates a suitable instance
// depending on if we've a MMX/SSE/etc-capable CPU available or not.
-void * RateTransposer::operator new(size_t)
-{
- // Notice! don't use "new TDStretch" directly, use "newInstance" to create a new instance instead!
- //assert(false);
- //return NULL;
+void *RateTransposer::operator new(size_t)
+{
+ // Notice! don't use "new TDStretch" directly, use "newInstance" to create a new instance instead!
+ //assert(false);
+ //return NULL;
throw std::runtime_error("Don't use 'new RateTransposer', use 'newInstance' member instead!");
}
-
RateTransposer *RateTransposer::newInstance()
{
-#ifdef INTEGER_SAMPLES
- return ::new RateTransposerInteger;
+#ifdef SOUNDTOUCH_INTEGER_SAMPLES
+ return ::new RateTransposerInteger;
#else
- return ::new RateTransposerFloat;
+ return ::new RateTransposerFloat;
#endif
}
-
// Constructor
RateTransposer::RateTransposer() : FIFOProcessor(&outputBuffer)
{
- uChannels = 2;
- bUseAAFilter = true;
-
- // Instantiates the anti-alias filter with default tap length
- // of 32
- pAAFilter = new AAFilter(32);
-}
-
-
+ this->numChannels = 2;
+ this->bUseAAFilter = true;
+ this->fRate = 0;
+
+ // Instantiates the anti-alias filter with default tap length
+ // of 32
+ this->pAAFilter.reset(new AAFilter(32));
+}
RateTransposer::~RateTransposer()
{
- delete pAAFilter;
-}
-
-
+}
/// Enables/disables the anti-alias filter. Zero to disable, nonzero to enable
-void RateTransposer::enableAAFilter(const bool newMode)
-{
- bUseAAFilter = newMode;
-}
-
+void RateTransposer::enableAAFilter(bool newMode)
+{
+ this->bUseAAFilter = newMode;
+}
/// Returns nonzero if anti-alias filter is enabled.
bool RateTransposer::isAAFilterEnabled() const
{
- return bUseAAFilter;
-}
-
-
-AAFilter *RateTransposer::getAAFilter() const
-{
- return pAAFilter;
-}
-
-
-
-// Sets new target uRate. Normal uRate = 1.0, smaller values represent slower
-// uRate, larger faster uRates.
+ return this->bUseAAFilter;
+}
+
+AAFilter *RateTransposer::getAAFilter()
+{
+ return this->pAAFilter.get();
+}
+
+// Sets new target iRate. Normal iRate = 1.0, smaller values represent slower
+// iRate, larger faster iRates.
void RateTransposer::setRate(float newRate)
{
- float fCutoff;
-
- fRate = newRate;
-
- // design a new anti-alias filter
- if (newRate > 1.0f)
- {
- fCutoff = 0.5f / newRate;
- }
- else
- {
- fCutoff = 0.5f * newRate;
- }
- pAAFilter->setCutoffFreq(fCutoff);
-}
-
-
-// Outputs as many samples of the 'outputBuffer' as possible, and if there's
-// any room left, outputs also as many of the incoming samples as possible.
-// The goal is to drive the outputBuffer empty.
-//
-// It's allowed for 'output' and 'input' parameters to point to the same
-// memory position.
-void RateTransposer::flushStoreBuffer()
-{
- if (storeBuffer.isEmpty())
- return;
-
- outputBuffer.moveSamples(storeBuffer);
-}
-
-
-// Adds 'numSamples' pcs of samples from the 'samples' memory position into
+ double fCutoff;
+
+ this->fRate = newRate;
+
+ // design a new anti-alias filter
+ if (newRate > 1.0f)
+ fCutoff = 0.5f / newRate;
+ else
+ fCutoff = 0.5f * newRate;
+ this->pAAFilter->setCutoffFreq(fCutoff);
+}
+
+// Adds 'nSamples' pcs of samples from the 'samples' memory position into
// the input of the object.
-void RateTransposer::putSamples(const SAMPLETYPE *samples, uint32_t numsamples)
-{
- processSamples(samples, numsamples);
-}
-
-
+void RateTransposer::putSamples(const SAMPLETYPE *samples, uint32_t nSamples)
+{
+ this->processSamples(samples, nSamples);
+}
// Transposes up the sample rate, causing the observed playback 'rate' of the
// sound to decrease
-void RateTransposer::upsample(const SAMPLETYPE *src, uint32_t numsamples)
-{
- int count, sizeTemp, num;
-
- // If the parameter 'uRate' value is smaller than 'SCALE', first transpose
- // the samples and then apply the anti-alias filter to remove aliasing.
-
- // First check that there's enough room in 'storeBuffer'
- // (+16 is to reserve some slack in the destination buffer)
- sizeTemp = (int)((float)numsamples / fRate + 16.0f);
-
- // Transpose the samples, store the result into the end of "storeBuffer"
- count = transpose(storeBuffer.ptrEnd(sizeTemp), src, numsamples);
- storeBuffer.putSamples(count);
-
- // Apply the anti-alias filter to samples in "store output", output the
- // result to "dest"
- num = storeBuffer.numSamples();
- count = pAAFilter->evaluate(outputBuffer.ptrEnd(num),
- storeBuffer.ptrBegin(), num, uChannels);
- outputBuffer.putSamples(count);
-
- // Remove the processed samples from "storeBuffer"
- storeBuffer.receiveSamples(count);
-}
-
+void RateTransposer::upsample(const SAMPLETYPE *src, uint32_t nSamples)
+{
+ // If the parameter 'uRate' value is smaller than 'SCALE', first transpose
+ // the samples and then apply the anti-alias filter to remove aliasing.
+
+ // First check that there's enough room in 'storeBuffer'
+ // (+16 is to reserve some slack in the destination buffer)
+ uint32_t sizeTemp = static_cast<uint32_t>(nSamples / this->fRate + 16.0f);
+
+ // Transpose the samples, store the result into the end of "storeBuffer"
+ uint32_t count = this->transpose(this->storeBuffer.ptrEnd(sizeTemp), src, nSamples);
+ this->storeBuffer.putSamples(count);
+
+ // Apply the anti-alias filter to samples in "store output", output the
+ // result to "dest"
+ uint32_t num = this->storeBuffer.numSamples();
+ count = this->pAAFilter->evaluate(this->outputBuffer.ptrEnd(num), this->storeBuffer.ptrBegin(), num, this->numChannels);
+ this->outputBuffer.putSamples(count);
+
+ // Remove the processed samples from "storeBuffer"
+ this->storeBuffer.receiveSamples(count);
+}
// Transposes down the sample rate, causing the observed playback 'rate' of the
// sound to increase
-void RateTransposer::downsample(const SAMPLETYPE *src, uint32_t numsamples)
-{
- int count, sizeTemp;
-
- // If the parameter 'uRate' value is larger than 'SCALE', first apply the
- // anti-alias filter to remove high frequencies (prevent them from folding
- // over the lover frequencies), then transpose. */
-
- // Add the new samples to the end of the storeBuffer */
- storeBuffer.putSamples(src, numsamples);
-
- // Anti-alias filter the samples to prevent folding and output the filtered
- // data to tempBuffer. Note : because of the FIR filter length, the
- // filtering routine takes in 'filter_length' more samples than it outputs.
- assert(tempBuffer.isEmpty());
- sizeTemp = storeBuffer.numSamples();
-
- count = pAAFilter->evaluate(tempBuffer.ptrEnd(sizeTemp),
- storeBuffer.ptrBegin(), sizeTemp, uChannels);
-
- // Remove the filtered samples from 'storeBuffer'
- storeBuffer.receiveSamples(count);
-
- // Transpose the samples (+16 is to reserve some slack in the destination buffer)
- sizeTemp = (int)((float)numsamples / fRate + 16.0f);
- count = transpose(outputBuffer.ptrEnd(sizeTemp), tempBuffer.ptrBegin(), count);
- outputBuffer.putSamples(count);
-}
-
+void RateTransposer::downsample(const SAMPLETYPE *src, uint32_t nSamples)
+{
+ // If the parameter 'uRate' value is larger than 'SCALE', first apply the
+ // anti-alias filter to remove high frequencies (prevent them from folding
+ // over the lover frequencies), then transpose. */
+
+ // Add the new samples to the end of the storeBuffer */
+ this->storeBuffer.putSamples(src, nSamples);
+
+ // Anti-alias filter the samples to prevent folding and output the filtered
+ // data to tempBuffer. Note : because of the FIR filter length, the
+ // filtering routine takes in 'filter_length' more samples than it outputs.
+ assert(this->tempBuffer.isEmpty());
+ uint32_t sizeTemp = this->storeBuffer.numSamples();
+
+ uint32_t count = this->pAAFilter->evaluate(this->tempBuffer.ptrEnd(sizeTemp), this->storeBuffer.ptrBegin(), sizeTemp, this->numChannels);
+
+ // Remove the filtered samples from 'storeBuffer'
+ this->storeBuffer.receiveSamples(count);
+
+ // Transpose the samples (+16 is to reserve some slack in the destination buffer)
+ sizeTemp = static_cast<uint32_t>(nSamples / this->fRate + 16.0f);
+ count = this->transpose(this->outputBuffer.ptrEnd(sizeTemp), this->tempBuffer.ptrBegin(), count);
+ this->outputBuffer.putSamples(count);
+}
// Transposes sample rate by applying anti-alias filter to prevent folding.
// Returns amount of samples returned in the "dest" buffer.
// The maximum amount of samples that can be returned at a time is set by
// the 'set_returnBuffer_size' function.
-void RateTransposer::processSamples(const SAMPLETYPE *src, uint32_t numsamples)
-{
- uint32_t count;
- uint32_t sizeReq;
-
- if (numsamples == 0) return;
- assert(pAAFilter);
-
- // If anti-alias filter is turned off, simply transpose without applying
- // the filter
- if (bUseAAFilter == false)
- {
- sizeReq = (int)((float)numsamples / fRate + 1.0f);
- count = transpose(outputBuffer.ptrEnd(sizeReq), src, numsamples);
- outputBuffer.putSamples(count);
- return;
- }
-
- // Transpose with anti-alias filter
- if (fRate < 1.0f)
- {
- upsample(src, numsamples);
- }
- else
- {
- downsample(src, numsamples);
- }
-}
-
+void RateTransposer::processSamples(const SAMPLETYPE *src, uint32_t nSamples)
+{
+ if (!nSamples)
+ return;
+ assert(this->pAAFilter.get());
+
+ // If anti-alias filter is turned off, simply transpose without applying
+ // the filter
+ if (!bUseAAFilter)
+ {
+ uint32_t sizeReq = static_cast<uint32_t>(nSamples / this->fRate + 1.0f);
+ uint32_t count = this->transpose(this->outputBuffer.ptrEnd(sizeReq), src, nSamples);
+ this->outputBuffer.putSamples(count);
+ return;
+ }
+
+ // Transpose with anti-alias filter
+ if (this->fRate < 1.0f)
+ this->upsample(src, nSamples);
+ else
+ this->downsample(src, nSamples);
+}
// Transposes the sample rate of the given samples using linear interpolation.
// Returns the number of samples returned in the "dest" buffer
-inline uint32_t RateTransposer::transpose(SAMPLETYPE *dest, const SAMPLETYPE *src, uint32_t numsamples)
-{
- if (uChannels == 2)
- {
- return transposeStereo(dest, src, numsamples);
- }
- else
- {
- return transposeMono(dest, src, numsamples);
- }
-}
-
+uint32_t RateTransposer::transpose(SAMPLETYPE *dest, const SAMPLETYPE *src, uint32_t nSamples)
+{
+ if (this->numChannels == 2)
+ return this->transposeStereo(dest, src, nSamples);
+ else
+ return this->transposeMono(dest, src, nSamples);
+}
// Sets the number of channels, 1 = mono, 2 = stereo
-void RateTransposer::setChannels(uint32_t numchannels)
-{
- if (uChannels == numchannels) return;
-
- assert(numchannels == 1 || numchannels == 2);
- uChannels = numchannels;
-
- storeBuffer.setChannels(uChannels);
- tempBuffer.setChannels(uChannels);
- outputBuffer.setChannels(uChannels);
-
- // Inits the linear interpolation registers
- resetRegisters();
-}
-
+void RateTransposer::setChannels(int32_t nChannels)
+{
+ assert(nChannels > 0);
+ if (this->numChannels == nChannels)
+ return;
+
+ assert(nChannels == 1 || nChannels == 2);
+ this->numChannels = nChannels;
+
+ this->storeBuffer.setChannels(this->numChannels);
+ this->tempBuffer.setChannels(this->numChannels);
+ this->outputBuffer.setChannels(this->numChannels);
+
+ // Inits the linear interpolation registers
+ this->resetRegisters();
+}
// Clears all the samples in the object
void RateTransposer::clear()
{
- outputBuffer.clear();
- storeBuffer.clear();
-}
-
+ this->outputBuffer.clear();
+ this->storeBuffer.clear();
+}
// Returns nonzero if there aren't any samples available for outputting.
bool RateTransposer::isEmpty() const
@@ -340,9 +281,8 @@
bool res = FIFOProcessor::isEmpty();
if (!res)
return false;
- return storeBuffer.isEmpty();
-}
-
+ return this->storeBuffer.isEmpty();
+}
//////////////////////////////////////////////////////////////////////////////
//
@@ -350,141 +290,130 @@
//
/// fixed-point interpolation routine precision
-#define SCALE 65536
+static const int SCALE = 65536;
// Constructor
RateTransposerInteger::RateTransposerInteger() : RateTransposer()
{
- // call these here as these are virtual functions; calling these
- // from the base class constructor wouldn't execute the overloaded
- // versions (<master yoda>peculiar C++ can be</my>).
- resetRegisters();
- setRate(1.0f);
-}
-
+ // Notice: use local function calling syntax for sake of clarity,
+ // to indicate the fact that C++ constructor can't call virtual functions.
+ RateTransposerInteger::resetRegisters();
+ RateTransposerInteger::setRate(1.0f);
+}
RateTransposerInteger::~RateTransposerInteger()
{
}
-
void RateTransposerInteger::resetRegisters()
{
- iSlopeCount = 0;
- sPrevSampleL =
- sPrevSampleR = 0;
-}
-
-
+ this->iSlopeCount = 0;
+ this->sPrevSampleL = this->sPrevSampleR = 0;
+}
// Transposes the sample rate of the given samples using linear interpolation.
// 'Mono' version of the routine. Returns the number of samples returned in
// the "dest" buffer
-uint32_t RateTransposerInteger::transposeMono(SAMPLETYPE *dest, const SAMPLETYPE *src, uint32_t numsamples)
-{
- unsigned int i, used;
- LONG_SAMPLETYPE temp, vol1;
-
- used = 0;
- i = 0;
-
- // Process the last sample saved from the previous call first...
- while (iSlopeCount <= SCALE)
- {
- vol1 = (LONG_SAMPLETYPE)(SCALE - iSlopeCount);
- temp = vol1 * sPrevSampleL + iSlopeCount * src[0];
- dest[i] = (SAMPLETYPE)(temp / SCALE);
- i++;
- iSlopeCount += uRate;
- }
- // now always (iSlopeCount > SCALE)
- iSlopeCount -= SCALE;
-
- while (1)
- {
- while (iSlopeCount > SCALE)
- {
- iSlopeCount -= SCALE;
- used ++;
- if (used >= numsamples - 1) goto end;
- }
- vol1 = (LONG_SAMPLETYPE)(SCALE - iSlopeCount);
- temp = src[used] * vol1 + iSlopeCount * src[used + 1];
- dest[i] = (SAMPLETYPE)(temp / SCALE);
-
- i++;
- iSlopeCount += uRate;
- }
+uint32_t RateTransposerInteger::transposeMono(SAMPLETYPE *dest, const SAMPLETYPE *src, uint32_t nSamples)
+{
+ if (!nSamples)
+ return 0; // no samples, no work
+
+ unsigned used = 0, i = 0;
+
+ // Process the last sample saved from the previous call first...
+ LONG_SAMPLETYPE temp, vol1;
+ while (this->iSlopeCount <= SCALE)
+ {
+ vol1 = static_cast<LONG_SAMPLETYPE>(SCALE - this->iSlopeCount);
+ temp = vol1 * this->sPrevSampleL + this->iSlopeCount * src[0];
+ dest[i] = static_cast<SAMPLETYPE>(temp / SCALE);
+ ++i;
+ this->iSlopeCount += this->iRate;
+ }
+ // now always (iSlopeCount > SCALE)
+ this->iSlopeCount -= SCALE;
+
+ while (1)
+ {
+ while (this->iSlopeCount > SCALE)
+ {
+ this->iSlopeCount -= SCALE;
+ ++used;
+ if (used >= nSamples - 1)
+ goto end;
+ }
+ vol1 = static_cast<LONG_SAMPLETYPE>(SCALE - this->iSlopeCount);
+ temp = src[used] * vol1 + this->iSlopeCount * src[used + 1];
+ dest[i] = static_cast<SAMPLETYPE>(temp / SCALE);
+ ++i;
+ this->iSlopeCount += this->iRate;
+ }
end:
- // Store the last sample for the next round
- sPrevSampleL = src[numsamples - 1];
-
- return i;
-}
-
+ // Store the last sample for the next round
+ this->sPrevSampleL = src[nSamples - 1];
+
+ return i;
+}
// Transposes the sample rate of the given samples using linear interpolation.
// 'Stereo' version of the routine. Returns the number of samples returned in
// the "dest" buffer
-uint32_t RateTransposerInteger::transposeStereo(SAMPLETYPE *dest, const SAMPLETYPE *src, uint32_t numsamples)
-{
- unsigned int srcPos, i, used;
- LONG_SAMPLETYPE temp, vol1;
-
- if (numsamples == 0) return 0; // no samples, no work
-
- used = 0;
- i = 0;
-
- // Process the last sample saved from the sPrevSampleLious call first...
- while (iSlopeCount <= SCALE)
- {
- vol1 = (LONG_SAMPLETYPE)(SCALE - iSlopeCount);
- temp = vol1 * sPrevSampleL + iSlopeCount * src[0];
- dest[2 * i] = (SAMPLETYPE)(temp / SCALE);
- temp = vol1 * sPrevSampleR + iSlopeCount * src[1];
- dest[2 * i + 1] = (SAMPLETYPE)(temp / SCALE);
- i++;
- iSlopeCount += uRate;
- }
- // now always (iSlopeCount > SCALE)
- iSlopeCount -= SCALE;
-
- while (1)
- {
- while (iSlopeCount > SCALE)
- {
- iSlopeCount -= SCALE;
- used ++;
- if (used >= numsamples - 1) goto end;
- }
- srcPos = 2 * used;
- vol1 = (LONG_SAMPLETYPE)(SCALE - iSlopeCount);
- temp = src[srcPos] * vol1 + iSlopeCount * src[srcPos + 2];
- dest[2 * i] = (SAMPLETYPE)(temp / SCALE);
- temp = src[srcPos + 1] * vol1 + iSlopeCount * src[srcPos + 3];
- dest[2 * i + 1] = (SAMPLETYPE)(temp / SCALE);
-
- i++;
- iSlopeCount += uRate;
- }
+uint32_t RateTransposerInteger::transposeStereo(SAMPLETYPE *dest, const SAMPLETYPE *src, uint32_t nSamples)
+{
+ if (!nSamples)
+ return 0; // no samples, no work
+
+ unsigned used = 0, i = 0;
+
+ // Process the last sample saved from the sPrevSampleLious call first...
+ LONG_SAMPLETYPE temp, vol1;
+ while (this->iSlopeCount <= SCALE)
+ {
+ vol1 = static_cast<LONG_SAMPLETYPE>(SCALE - this->iSlopeCount);
+ temp = vol1 * this->sPrevSampleL + this->iSlopeCount * src[0];
+ dest[2 * i] = static_cast<SAMPLETYPE>(temp / SCALE);
+ temp = vol1 * this->sPrevSampleR + this->iSlopeCount * src[1];
+ dest[2 * i + 1] = static_cast<SAMPLETYPE>(temp / SCALE);
+ ++i;
+ this->iSlopeCount += this->iRate;
+ }
+ // now always (iSlopeCount > SCALE)
+ this->iSlopeCount -= SCALE;
+
+ while (1)
+ {
+ while (this->iSlopeCount > SCALE)
+ {
+ this->iSlopeCount -= SCALE;
+ ++used;
+ if (used >= nSamples - 1)
+ goto end;
+ }
+ unsigned srcPos = 2 * used;
+ vol1 = static_cast<LONG_SAMPLETYPE>(SCALE - this->iSlopeCount);
+ temp = src[srcPos] * vol1 + this->iSlopeCount * src[srcPos + 2];
+ dest[2 * i] = static_cast<SAMPLETYPE>(temp / SCALE);
+ temp = src[srcPos + 1] * vol1 + this->iSlopeCount * src[srcPos + 3];
+ dest[2 * i + 1] = static_cast<SAMPLETYPE>(temp / SCALE);
+ ++i;
+ this->iSlopeCount += this->iRate;
+ }
end:
- // Store the last sample for the next round
- sPrevSampleL = src[2 * numsamples - 2];
- sPrevSampleR = src[2 * numsamples - 1];
-
- return i;
-}
-
-
-// Sets new target uRate. Normal uRate = 1.0, smaller values represent slower
-// uRate, larger faster uRates.
+ // Store the last sample for the next round
+ this->sPrevSampleL = src[2 * nSamples - 2];
+ this->sPrevSampleR = src[2 * nSamples - 1];
+
+ return i;
+}
+
+// Sets new target iRate. Normal iRate = 1.0, smaller values represent slower
+// iRate, larger faster iRates.
void RateTransposerInteger::setRate(float newRate)
{
- uRate = (int)(newRate * SCALE + 0.5f);
- RateTransposer::setRate(newRate);
-}
-
+ this->iRate = static_cast<int>(newRate * SCALE + 0.5f);
+ RateTransposer::setRate(newRate);
+}
//////////////////////////////////////////////////////////////////////////////
//
@@ -495,117 +424,106 @@
// Constructor
RateTransposerFloat::RateTransposerFloat() : RateTransposer()
{
- // call these here as these are virtual functions; calling these
- // from the base class constructor wouldn't execute the overloaded
- // versions (<master yoda>peculiar C++ can be</my>).
- resetRegisters();
- setRate(1.0f);
-}
-
+ // Notice: use local function calling syntax for sake of clarity,
+ // to indicate the fact that C++ constructor can't call virtual functions.
+ RateTransposerFloat::resetRegisters();
+ RateTransposerFloat::setRate(1.0f);
+}
RateTransposerFloat::~RateTransposerFloat()
{
}
-
void RateTransposerFloat::resetRegisters()
{
- fSlopeCount = 0;
- sPrevSampleL =
- sPrevSampleR = 0;
-}
-
-
+ this->fSlopeCount = 0;
+ this->sPrevSampleL = this->sPrevSampleR = 0;
+}
// Transposes the sample rate of the given samples using linear interpolation.
// 'Mono' version of the routine. Returns the number of samples returned in
// the "dest" buffer
-uint32_t RateTransposerFloat::transposeMono(SAMPLETYPE *dest, const SAMPLETYPE *src, uint32_t numsamples)
-{
- unsigned int i, used;
-
- used = 0;
- i = 0;
-
- // Process the last sample saved from the previous call first...
- while (fSlopeCount <= 1.0f)
- {
- dest[i] = (SAMPLETYPE)((1.0f - fSlopeCount) * sPrevSampleL + fSlopeCount * src[0]);
- i++;
- fSlopeCount += fRate;
- }
- fSlopeCount -= 1.0f;
-
- if (numsamples == 1) goto end;
-
- while (1)
- {
- while (fSlopeCount > 1.0f)
- {
- fSlopeCount -= 1.0f;
- used ++;
- if (used >= numsamples - 1) goto end;
- }
- dest[i] = (SAMPLETYPE)((1.0f - fSlopeCount) * src[used] + fSlopeCount * src[used + 1]);
- i++;
- fSlopeCount += fRate;
- }
+uint32_t RateTransposerFloat::transposeMono(SAMPLETYPE *dest, const SAMPLETYPE *src, uint32_t nSamples)
+{
+ unsigned used = 0, i = 0;
+
+ // Process the last sample saved from the previous call first...
+ while (this->fSlopeCount <= 1.0f)
+ {
+ dest[i] = static_cast<SAMPLETYPE>((1.0f - this->fSlopeCount) * this->sPrevSampleL + this->fSlopeCount * src[0]);
+ ++i;
+ this->fSlopeCount += this->fRate;
+ }
+ this->fSlopeCount -= 1.0f;
+
+ if (nSamples > 1)
+ {
+ while (1)
+ {
+ while (this->fSlopeCount > 1.0f)
+ {
+ this->fSlopeCount -= 1.0f;
+ ++used;
+ if (used >= nSamples - 1)
+ goto end;
+ }
+ dest[i] = static_cast<SAMPLETYPE>((1.0f - this->fSlopeCount) * src[used] + this->fSlopeCount * src[used + 1]);
+ ++i;
+ this->fSlopeCount += this->fRate;
+ }
+ }
end:
- // Store the last sample for the next round
- sPrevSampleL = src[numsamples - 1];
-
- return i;
-}
-
+ // Store the last sample for the next round
+ this->sPrevSampleL = src[nSamples - 1];
+
+ return i;
+}
// Transposes the sample rate of the given samples using linear interpolation.
// 'Mono' version of the routine. Returns the number of samples returned in
// the "dest" buffer
-uint32_t RateTransposerFloat::transposeStereo(SAMPLETYPE *dest, const SAMPLETYPE *src, uint32_t numsamples)
-{
- unsigned int srcPos, i, used;
-
- if (numsamples == 0) return 0; // no samples, no work
-
- used = 0;
- i = 0;
-
- // Process the last sample saved from the sPrevSampleLious call first...
- while (fSlopeCount <= 1.0f)
- {
- dest[2 * i] = (SAMPLETYPE)((1.0f - fSlopeCount) * sPrevSampleL + fSlopeCount * src[0]);
- dest[2 * i + 1] = (SAMPLETYPE)((1.0f - fSlopeCount) * sPrevSampleR + fSlopeCount * src[1]);
- i++;
- fSlopeCount += fRate;
- }
- // now always (iSlopeCount > 1.0f)
- fSlopeCount -= 1.0f;
-
- if (numsamples == 1) goto end;
-
- while (1)
- {
- while (fSlopeCount > 1.0f)
- {
- fSlopeCount -= 1.0f;
- used ++;
- if (used >= numsamples - 1) goto end;
- }
- srcPos = 2 * used;
-
- dest[2 * i] = (SAMPLETYPE)((1.0f - fSlopeCount) * src[srcPos]
- + fSlopeCount * src[srcPos + 2]);
- dest[2 * i + 1] = (SAMPLETYPE)((1.0f - fSlopeCount) * src[srcPos + 1]
- + fSlopeCount * src[srcPos + 3]);
-
- i++;
- fSlopeCount += fRate;
- }
+uint32_t RateTransposerFloat::transposeStereo(SAMPLETYPE *dest, const SAMPLETYPE *src, uint32_t nSamples)
+{
+ if (!nSamples)
+ return 0; // no samples, no work
+
+ unsigned used = 0, i = 0;
+
+ // Process the last sample saved from the sPrevSampleLious call first...
+ while (this->fSlopeCount <= 1.0f)
+ {
+ dest[2 * i] = static_cast<SAMPLETYPE>((1.0f - this->fSlopeCount) * this->sPrevSampleL + this->fSlopeCount * src[0]);
+ dest[2 * i + 1] = static_cast<SAMPLETYPE>((1.0f - this->fSlopeCount) * this->sPrevSampleR + this->fSlopeCount * src[1]);
+ ++i;
+ this->fSlopeCount += this->fRate;
+ }
+ // now always (iSlopeCount > 1.0f)
+ this->fSlopeCount -= 1.0f;
+
+ if (nSamples > 1)
+ {
+ while (1)
+ {
+ while (this->fSlopeCount > 1.0f)
+ {
+ this->fSlopeCount -= 1.0f;
+ ++used;
+ if (used >= nSamples - 1)
+ goto end;
+ }
+ unsigned srcPos = 2 * used;
+
+ dest[2 * i] = static_cast<SAMPLETYPE>((1.0f - this->fSlopeCount) * src[srcPos] + this->fSlopeCount * src[srcPos + 2]);
+ dest[2 * i + 1] = static_cast<SAMPLETYPE>((1.0f - this->fSlopeCount) * src[srcPos + 1] + this->fSlopeCount * src[srcPos + 3]);
+ ++i;
+ this->fSlopeCount += this->fRate;
+ }
+ }
end:
- // Store the last sample for the next round
- sPrevSampleL = src[2 * numsamples - 2];
- sPrevSampleR = src[2 * numsamples - 1];
-
- return i;
-}
-
+ // Store the last sample for the next round
+ this->sPrevSampleL = src[2 * nSamples - 2];
+ this->sPrevSampleR = src[2 * nSamples - 1];
+
+ return i;
+}
+
--- a/src/in_2sf/desmume/metaspu/SoundTouch/RateTransposer.h
+++ b/src/in_2sf/desmume/metaspu/SoundTouch/RateTransposer.h
@@ -14,10 +14,10 @@
///
////////////////////////////////////////////////////////////////////////////////
//
-// Last changed : $Date: 2006/02/05 16:44:06 $
-// File revision : $Revision: 1.10 $
+// Last changed : $Date: 2009-02-21 13:00:14 -0300 (s�b, 21 fev 2009) $
+// File revision : $Revision: 4 $
//
-// $Id: RateTransposer.h,v 1.10 2006/02/05 16:44:06 Olli Exp $
+// $Id: RateTransposer.h 63 2009-02-21 16:00:14Z oparviai $
//
////////////////////////////////////////////////////////////////////////////////
//
@@ -49,8 +49,6 @@
#include "FIFOSamplePipe.h"
#include "FIFOSampleBuffer.h"
-#include "STTypes.h"
-
namespace soundtouch
{
@@ -64,11 +62,11 @@
{
protected:
/// Anti-alias filter object
- AAFilter *pAAFilter;
+ std::unique_ptr<AAFilter> pAAFilter;
float fRate;
- uint32_t uChannels;
+ int32_t numChannels;
/// Buffer for collecting samples to feed the anti-alias filter between
/// two batches
@@ -82,15 +80,11 @@
bool bUseAAFilter;
- void init();
-
virtual void resetRegisters() = 0;
virtual uint32_t transposeStereo(SAMPLETYPE *dest, const SAMPLETYPE *src, uint32_t numSamples) = 0;
virtual uint32_t transposeMono(SAMPLETYPE *dest, const SAMPLETYPE *src, uint32_t numSamples) = 0;
uint32_t transpose(SAMPLETYPE *dest, const SAMPLETYPE *src, uint32_t numSamples);
-
- void flushStoreBuffer();
void downsample(const SAMPLETYPE *src, uint32_t numSamples);
void upsample(const SAMPLETYPE *src, uint32_t numSamples);
@@ -107,7 +101,7 @@
/// Operator 'new' is overloaded so that it automatically creates a suitable instance
/// depending on if we're to use integer or floating point arithmetics.
- void *operator new(size_t s);
+ static void *operator new(size_t s);
/// Use this function instead of "new" operator to create a new instance of this class.
/// This function automatically chooses a correct implementation, depending on if
@@ -115,13 +109,13 @@
static RateTransposer *newInstance();
/// Returns the output buffer object
- FIFOSamplePipe *getOutput() { return &outputBuffer; };
+ FIFOSamplePipe *getOutput() { return &this->outputBuffer; }
/// Returns the store buffer object
- FIFOSamplePipe *getStore() { return &storeBuffer; };
+ FIFOSamplePipe *getStore() { return &this->storeBuffer; }
/// Return anti-alias filter object
- AAFilter *getAAFilter() const;
+ AAFilter *getAAFilter();
/// Enables/disables the anti-alias filter. Zero to disable, nonzero to enable
void enableAAFilter(bool newMode);
@@ -134,7 +128,7 @@
virtual void setRate(float newRate);
/// Sets the number of channels, 1 = mono, 2 = stereo
- void setChannels(uint32_t channels);
+ void setChannels(int32_t channels);
/// Adds 'numSamples' pcs of samples from the 'samples' memory position into
/// the input of the object.
--- a/src/in_2sf/desmume/metaspu/SoundTouch/STTypes.h
+++ b/src/in_2sf/desmume/metaspu/SoundTouch/STTypes.h
@@ -41,137 +41,94 @@
#include "pstdint.h"
-//#define INTEGER_SAMPLES 1
+namespace soundtouch
+{
-#ifdef __GNUC__
- // In GCC, include soundtouch_config.h made by config scritps
-/* Define to 1 if you have the <inttypes.h> header file. */
-#define HAVE_INTTYPES_H 1
+/// Activate these undef's to overrule the possible sampletype
+/// setting inherited from some other header file:
+//#undef SOUNDTOUCH_INTEGER_SAMPLES
+//#undef SOUNDTOUCH_FLOAT_SAMPLES
-/* Define to 1 if you have the `m' library (-lm). */
-#define HAVE_LIBM 1
-
-/* Define to 1 if your system has a GNU libc compatible `malloc' function, and
- to 0 otherwise. */
-#define HAVE_MALLOC 1
-
-/* Define to 1 if you have the <memory.h> header file. */
-#define HAVE_MEMORY_H 1
-
-/* Define to 1 if you have the <stdint.h> header file. */
-#define HAVE_STDINT_H 1
-
-/* Define to 1 if you have the <stdlib.h> header file. */
-#define HAVE_STDLIB_H 1
-
-/* Define to 1 if you have the <strings.h> header file. */
-#define HAVE_STRINGS_H 1
-
-/* Define to 1 if you have the <string.h> header file. */
-#define HAVE_STRING_H 1
-
-/* Define to 1 if you have the <sys/stat.h> header file. */
-#define HAVE_SYS_STAT_H 1
-
-/* Define to 1 if you have the <sys/types.h> header file. */
-#define HAVE_SYS_TYPES_H 1
-
-/* Define to 1 if you have the <unistd.h> header file. */
-#define HAVE_UNISTD_H 1
-
-/* Use Integer as Sample type */
-//#define INTEGER_SAMPLES 1
-
-/* Define as the return type of signal handlers (`int' or `void'). */
-#define RETSIGTYPE void
-
-/* Define to 1 if you have the ANSI C header files. */
-#define STDC_HEADERS 1
-
+#if !(SOUNDTOUCH_INTEGER_SAMPLES || SOUNDTOUCH_FLOAT_SAMPLES)
+/// Choose either 32bit floating point or 16bit integer sampletype
+/// by choosing one of the following defines, unless this selection
+/// has already been done in some other file.
+////
+/// Notes:
+/// - In Windows environment, choose the sample format with the
+/// following defines.
+/// - In GNU environment, the floating point samples are used by
+/// default, but integer samples can be chosen by giving the
+/// following switch to the configure script:
+/// ./configure --enable-integer-samples
+/// However, if you still prefer to select the sample format here
+/// also in GNU environment, then please #undef the INTEGER_SAMPLE
+/// and FLOAT_SAMPLE defines first as in comments above.
+//# define SOUNDTOUCH_INTEGER_SAMPLES 1 //< 16bit integer samples
+# define SOUNDTOUCH_FLOAT_SAMPLES 1 //< 32bit float samples
#endif
-namespace soundtouch
-{
-/// Activate these undef's to overrule the possible sampletype
-/// setting inherited from some other header file:
-//#undef INTEGER_SAMPLES
-//#undef FLOAT_SAMPLES
+#if (_M_IX86 || __i386__ || __x86_64__ || _M_X64)
+/// Define this to allow X86-specific assembler/intrinsic optimizations.
+/// Notice that library contains also usual C++ versions of each of these
+/// these routines, so if you're having difficulties getting the optimized
+/// routines compiled for whatever reason, you may disable these optimizations
+/// to make the library compile.
+# define SOUNDTOUCH_ALLOW_X86_OPTIMIZATIONS 1
-#if !(INTEGER_SAMPLES || FLOAT_SAMPLES)
+/// In GNU environment, allow the user to override this setting by
+/// giving the following switch to the configure script:
+/// ./configure --disable-x86-optimizations
+/// ./configure --enable-x86-optimizations=no
+# ifdef SOUNDTOUCH_DISABLE_X86_OPTIMIZATIONS
+# undef SOUNDTOUCH_ALLOW_X86_OPTIMIZATIONS
+# endif
+#else
+/// Always disable optimizations when not using a x86 systems.
+# undef SOUNDTOUCH_ALLOW_X86_OPTIMIZATIONS
+#endif
- /// Choose either 32bit floating point or 16bit integer sampletype
- /// by choosing one of the following defines, unless this selection
- /// has already been done in some other file.
- ////
- /// Notes:
- /// - In Windows environment, choose the sample format with the
- /// following defines.
- /// - In GNU environment, the floating point samples are used by
- /// default, but integer samples can be chosen by giving the
- /// following switch to the configure script:
- /// ./configure --enable-integer-samples
- /// However, if you still prefer to select the sample format here
- /// also in GNU environment, then please #undef the INTEGER_SAMPLE
- /// and FLOAT_SAMPLE defines first as in comments above.
- //#define INTEGER_SAMPLES 1 //< 16bit integer samples
- #define FLOAT_SAMPLES 1 //< 32bit float samples
+// If defined, allows the SIMD-optimized routines to take minor shortcuts
+// for improved performance. Undefine to require faithfully similar SIMD
+// calculations as in normal C implementation.
+#define SOUNDTOUCH_ALLOW_NONEXACT_SIMD_OPTIMIZATION 1
- #endif
+#ifdef SOUNDTOUCH_INTEGER_SAMPLES
+// 16bit integer sample type
+typedef short SAMPLETYPE;
+// data type for sample accumulation: Use 32bit integer to prevent overflows
+typedef long LONG_SAMPLETYPE;
- /// Define this to allow CPU-specific assembler optimizations. Notice that
- /// having this enabled on non-x86 platforms doesn't matter; the compiler can
- /// drop unsupported extensions on different platforms automatically.
- /// However, if you're having difficulties getting the optimized routines
- /// compiled with your compler (e.g. some gcc compiler versions may be picky),
- /// you may wish to disable the optimizations to make the library compile.
- #if !defined(_MSC_VER) || !defined(__x86_64__)
- #define ALLOW_OPTIMIZATIONS 1
- #define ALLOW_NONEXACT_SIMD_OPTIMIZATION 1
- #endif
+# ifdef SOUNDTOUCH_FLOAT_SAMPLES
+// check that only one sample type is defined
+# error "conflicting sample types defined"
+# endif // SOUNDTOUCH_FLOAT_SAMPLES
+# ifdef SOUNDTOUCH_ALLOW_X86_OPTIMIZATIONS
+// Allow MMX optimizations
+# define SOUNDTOUCH_ALLOW_MMX 1
+# endif
+#else
+// floating point samples
+typedef float SAMPLETYPE;
+// data type for sample accumulation: Use double to utilize full precision.
+typedef double LONG_SAMPLETYPE;
- // If defined, allows the SIMD-optimized routines to take minor shortcuts
- // for improved performance. Undefine to require faithfully similar SIMD
- // calculations as in normal C implementation.
+# ifdef SOUNDTOUCH_ALLOW_X86_OPTIMIZATIONS
+// Allow SSE optimizations
+# define SOUNDTOUCH_ALLOW_SSE 1
+# endif
+#endif // SOUNDTOUCH_INTEGER_SAMPLES
+// Helper macro for aligning pointer up to next 16-byte boundary
+inline uintptr_t SOUNDTOUCH_ALIGN_POINTER_16(SAMPLETYPE *x) { return (reinterpret_cast<uintptr_t>(x) + 15) & ~static_cast<uintptr_t>(15); }
+// When this #define is active, eliminates a clicking sound when the "rate" or "pitch"
+// parameter setting crosses from value <1 to >=1 or vice versa during processing.
+// Default is off as such crossover is untypical case and involves a slight sound
+// quality compromise.
+//#define SOUNDTOUCH_PREVENT_CLICK_AT_RATE_CROSSOVER 1
- #ifdef INTEGER_SAMPLES
- // 16bit integer sample type
- typedef short SAMPLETYPE;
- // data type for sample accumulation: Use 32bit integer to prevent overflows
- typedef long LONG_SAMPLETYPE;
-
- #ifdef FLOAT_SAMPLES
- // check that only one sample type is defined
- #error "conflicting sample types defined"
- #endif // FLOAT_SAMPLES
-
- #ifdef ALLOW_OPTIMIZATIONS
- #if (_WIN32 || __i386__ || __x86_64__)
- // Allow MMX optimizations
- #define ALLOW_MMX 1
- #endif
- #endif
-
- #else
-
- // floating point samples
- typedef float SAMPLETYPE;
- // data type for sample accumulation: Use double to utilize full precision.
- typedef double LONG_SAMPLETYPE;
-
- #ifdef ALLOW_OPTIMIZATIONS
- // Allow 3DNow! and SSE optimizations
- #if _WIN32
- // #define ALLOW_3DNOW 1
- #endif
- #if (_WIN32 || __i386__ || __x86_64__)
- #define ALLOW_SSE 1
- #endif
- #endif
-
- #endif // INTEGER_SAMPLES
}
#endif
--- a/src/in_2sf/desmume/metaspu/SoundTouch/SoundTouch.cpp
+++ b/src/in_2sf/desmume/metaspu/SoundTouch/SoundTouch.cpp
@@ -41,10 +41,10 @@
///
////////////////////////////////////////////////////////////////////////////////
//
-// Last changed : $Date: 2006/02/05 16:44:06 $
-// File revision : $Revision: 1.13 $
-//
-// $Id: SoundTouch.cpp,v 1.13 2006/02/05 16:44:06 Olli Exp $
+// Last changed : $Date: 2012-06-13 16:29:53 -0300 (qua, 13 jun 2012) $
+// File revision : $Revision: 4 $
+//
+// $Id: SoundTouch.cpp 143 2012-06-13 19:29:53Z oparviai $
//
////////////////////////////////////////////////////////////////////////////////
//
@@ -76,7 +76,6 @@
#include <cstdlib>
#include <cstring>
#include <cstdio>
-
#include "SoundTouch.h"
#include "TDStretch.h"
#include "RateTransposer.h"
@@ -84,252 +83,197 @@
using namespace soundtouch;
-/// Print library version string
-extern "C" void soundtouch_ac_test()
-{
- printf("SoundTouch Version: %s\n",SOUNDTOUCH_VERSION);
-}
-
-
SoundTouch::SoundTouch()
{
- // Initialize rate transposer and tempo changer instances
-
- pRateTransposer = RateTransposer::newInstance();
- pTDStretch = TDStretch::newInstance();
-
- setOutPipe(pTDStretch);
-
- rate = tempo = 0;
-
- virtualPitch =
- virtualRate =
- virtualTempo = 1.0;
-
- calcEffectiveRateAndTempo();
-
- channels = 0;
- bSrateSet = false;
-}
-
-
+ // Initialize rate transposer and tempo changer instances
+
+ this->pRateTransposer.reset(RateTransposer::newInstance());
+ this->pTDStretch.reset(TDStretch::newInstance());
+
+ this->setOutPipe(this->pTDStretch.get());
+
+ this->rate = this->tempo = 0;
+
+ this->virtualPitch = this->virtualRate = this->virtualTempo = 1.0;
+
+ this->calcEffectiveRateAndTempo();
+
+ this->channels = 0;
+ this->bSrateSet = false;
+}
SoundTouch::~SoundTouch()
{
- delete pRateTransposer;
- delete pTDStretch;
-}
-
-
-
-/// Get SoundTouch library version string
-const char *SoundTouch::getVersionString()
-{
- static const char *_version = SOUNDTOUCH_VERSION;
-
- return _version;
-}
-
-
-/// Get SoundTouch library version Id
-uint32_t SoundTouch::getVersionId()
-{
- return SOUNDTOUCH_VERSION_ID;
-}
-
+}
// Sets the number of channels, 1 = mono, 2 = stereo
void SoundTouch::setChannels(uint32_t numChannels)
{
- if (numChannels != 1 && numChannels != 2)
- {
- throw std::runtime_error("Illegal number of channels");
- }
- channels = numChannels;
- pRateTransposer->setChannels(numChannels);
- pTDStretch->setChannels(numChannels);
-}
-
-
+ if (numChannels != 1 && numChannels != 2)
+ throw std::runtime_error("Illegal number of channels");
+ this->channels = numChannels;
+ this->pRateTransposer->setChannels(static_cast<int32_t>(numChannels));
+ this->pTDStretch->setChannels(static_cast<int32_t>(numChannels));
+}
// Sets new rate control value. Normal rate = 1.0, smaller values
// represent slower rate, larger faster rates.
void SoundTouch::setRate(float newRate)
{
- virtualRate = newRate;
- calcEffectiveRateAndTempo();
-}
-
-
+ this->virtualRate = newRate;
+ this->calcEffectiveRateAndTempo();
+}
// Sets new rate control value as a difference in percents compared
// to the original rate (-50 .. +100 %)
void SoundTouch::setRateChange(float newRate)
{
- virtualRate = 1.0f + 0.01f * newRate;
- calcEffectiveRateAndTempo();
-}
-
-
+ this->virtualRate = 1.0f + 0.01f * newRate;
+ this->calcEffectiveRateAndTempo();
+}
// Sets new tempo control value. Normal tempo = 1.0, smaller values
// represent slower tempo, larger faster tempo.
void SoundTouch::setTempo(float newTempo)
{
- virtualTempo = newTempo;
- calcEffectiveRateAndTempo();
-}
-
-
+ this->virtualTempo = newTempo;
+ this->calcEffectiveRateAndTempo();
+}
// Sets new tempo control value as a difference in percents compared
// to the original tempo (-50 .. +100 %)
void SoundTouch::setTempoChange(float newTempo)
{
- virtualTempo = 1.0f + 0.01f * newTempo;
- calcEffectiveRateAndTempo();
-}
-
-
+ this->virtualTempo = 1.0f + 0.01f * newTempo;
+ this->calcEffectiveRateAndTempo();
+}
// Sets new pitch control value. Original pitch = 1.0, smaller values
// represent lower pitches, larger values higher pitch.
void SoundTouch::setPitch(float newPitch)
{
- virtualPitch = newPitch;
- calcEffectiveRateAndTempo();
-}
-
-
+ this->virtualPitch = newPitch;
+ this->calcEffectiveRateAndTempo();
+}
// Sets pitch change in octaves compared to the original pitch
// (-1.00 .. +1.00)
void SoundTouch::setPitchOctaves(float newPitch)
{
- virtualPitch = (float)exp(0.69314718056f * newPitch);
- calcEffectiveRateAndTempo();
-}
-
-
+ this->virtualPitch = std::exp(0.69314718056f * newPitch);
+ this->calcEffectiveRateAndTempo();
+}
// Sets pitch change in semi-tones compared to the original pitch
// (-12 .. +12)
void SoundTouch::setPitchSemiTones(int newPitch)
{
- setPitchOctaves((float)newPitch / 12.0f);
-}
-
-
+ this->setPitchOctaves(newPitch / 12.0f);
+}
void SoundTouch::setPitchSemiTones(float newPitch)
{
- setPitchOctaves(newPitch / 12.0f);
-}
-
+ this->setPitchOctaves(newPitch / 12.0f);
+}
// Calculates 'effective' rate and tempo values from the
// nominal control values.
void SoundTouch::calcEffectiveRateAndTempo()
{
- float oldTempo = tempo;
- float oldRate = rate;
-
- tempo = virtualTempo / virtualPitch;
- rate = virtualPitch * virtualRate;
-
- if (!fEqual(rate, oldRate)) pRateTransposer->setRate(rate);
- if (!fEqual(tempo, oldTempo)) pTDStretch->setTempo(tempo);
-
- if (rate > 1.0f)
- {
- if (output != pRateTransposer)
- {
- FIFOSamplePipe *transOut;
-
- assert(output == pTDStretch);
- // move samples in the current output buffer to the output of pRateTransposer
- transOut = pRateTransposer->getOutput();
- transOut->moveSamples(*output);
- // move samples in tempo changer's input to pitch transposer's input
- pRateTransposer->moveSamples(*pTDStretch->getInput());
-
- output = pRateTransposer;
- }
- }
- else
- {
- if (output != pTDStretch)
- {
- FIFOSamplePipe *tempoOut;
-
- assert(output == pRateTransposer);
- // move samples in the current output buffer to the output of pTDStretch
- tempoOut = pTDStretch->getOutput();
- tempoOut->moveSamples(*output);
- // move samples in pitch transposer's store buffer to tempo changer's input
- pTDStretch->moveSamples(*pRateTransposer->getStore());
-
- output = pTDStretch;
-
- }
- }
-}
-
+ float oldTempo = this->tempo;
+ float oldRate = this->rate;
+
+ this->tempo = this->virtualTempo / this->virtualPitch;
+ this->rate = this->virtualPitch * this->virtualRate;
+
+ if (!fEqual(this->rate, oldRate))
+ this->pRateTransposer->setRate(this->rate);
+ if (!fEqual(this->tempo, oldTempo))
+ this->pTDStretch->setTempo(this->tempo);
+
+#ifndef SOUNDTOUCH_PREVENT_CLICK_AT_RATE_CROSSOVER
+ if (this->rate <= 1.0f)
+ {
+ if (this->output != this->pTDStretch.get())
+ {
+ FIFOSamplePipe *tempoOut;
+
+ assert(this->output == this->pRateTransposer.get());
+ // move samples in the current output buffer to the output of pTDStretch
+ tempoOut = this->pTDStretch->getOutput();
+ tempoOut->moveSamples(*this->output);
+ // move samples in pitch transposer's store buffer to tempo changer's input
+ this->pTDStretch->moveSamples(*this->pRateTransposer->getStore());
+
+ this->output = pTDStretch.get();
+ }
+ }
+ else
+#endif
+ {
+ if (this->output != this->pRateTransposer.get())
+ {
+ assert(this->output == this->pTDStretch.get());
+ // move samples in the current output buffer to the output of pRateTransposer
+ FIFOSamplePipe *transOut = this->pRateTransposer->getOutput();
+ transOut->moveSamples(*this->output);
+ // move samples in tempo changer's input to pitch transposer's input
+ this->pRateTransposer->moveSamples(*this->pTDStretch->getInput());
+
+ this->output = this->pRateTransposer.get();
+ }
+ }
+}
// Sets sample rate.
void SoundTouch::setSampleRate(uint32_t srate)
{
- bSrateSet = true;
- // set sample rate, leave other tempo changer parameters as they are.
- pTDStretch->setParameters(srate);
-}
-
+ this->bSrateSet = true;
+ // set sample rate, leave other tempo changer parameters as they are.
+ this->pTDStretch->setParameters(static_cast<int32_t>(srate));
+}
// Adds 'numSamples' pcs of samples from the 'samples' memory position into
// the input of the object.
-void SoundTouch::putSamples(const SAMPLETYPE *samples, uint32_t numsamples)
-{
- if (bSrateSet == false)
- {
- throw std::runtime_error("SoundTouch : Sample rate not defined");
- }
- else if (channels == 0)
- {
- throw std::runtime_error("SoundTouch : Number of channels not defined");
- }
-
- // Transpose the rate of the new samples if necessary
- /* Bypass the nominal setting - can introduce a click in sound when tempo/pitch control crosses the nominal value...
- if (rate == 1.0f)
- {
- // The rate value is same as the original, simply evaluate the tempo changer.
- assert(output == pTDStretch);
- if (pRateTransposer->isEmpty() == 0)
- {
- // yet flush the last samples in the pitch transposer buffer
- // (may happen if 'rate' changes from a non-zero value to zero)
- pTDStretch->moveSamples(*pRateTransposer);
- }
- pTDStretch->putSamples(samples, numSamples);
- }
- */
- else if (rate <= 1.0f)
- {
- // transpose the rate down, output the transposed sound to tempo changer buffer
- assert(output == pTDStretch);
- pRateTransposer->putSamples(samples, numsamples);
- pTDStretch->moveSamples(*pRateTransposer);
- }
- else
- {
- assert(rate > 1.0f);
- // evaluate the tempo changer, then transpose the rate up,
- assert(output == pRateTransposer);
- pTDStretch->putSamples(samples, numsamples);
- pRateTransposer->moveSamples(*pTDStretch);
- }
-}
-
+void SoundTouch::putSamples(const SAMPLETYPE *samples, uint32_t nSamples)
+{
+ if (!this->bSrateSet)
+ throw std::runtime_error("SoundTouch : Sample rate not defined");
+ else if (!this->channels)
+ throw std::runtime_error("SoundTouch : Number of channels not defined");
+
+ // Transpose the rate of the new samples if necessary
+ /* Bypass the nominal setting - can introduce a click in sound when tempo/pitch control crosses the nominal value...
+ if (this->rate == 1.0f)
+ {
+ // The rate value is same as the original, simply evaluate the tempo changer.
+ assert(this->output == this->pTDStretch.get());
+ if (!this->pRateTransposer->isEmpty())
+ {
+ // yet flush the last samples in the pitch transposer buffer
+ // (may happen if 'rate' changes from a non-zero value to zero)
+ this->pTDStretch->moveSamples(*this->pRateTransposer);
+ }
+ this->pTDStretch->putSamples(samples, nSamples);
+ }*/
+#ifndef SOUNDTOUCH_PREVENT_CLICK_AT_RATE_CROSSOVER
+ else if (this->rate <= 1.0f)
+ {
+ // transpose the rate down, output the transposed sound to tempo changer buffer
+ assert(this->output == this->pTDStretch.get());
+ this->pRateTransposer->putSamples(samples, nSamples);
+ this->pTDStretch->moveSamples(*this->pRateTransposer);
+ }
+ else
+#endif
+ {
+ assert(this->rate > 1.0f);
+ // evaluate the tempo changer, then transpose the rate up,
+ assert(this->output == this->pRateTransposer.get());
+ this->pTDStretch->putSamples(samples, nSamples);
+ this->pRateTransposer->moveSamples(*this->pTDStretch);
+ }
+}
// Flushes the last samples from the processing pipeline to the output.
// Clears also the internal processing buffers.
@@ -340,137 +284,146 @@
// in the middle of a sound stream.
void SoundTouch::flush()
{
- int i;
- uint32_t nOut;
- SAMPLETYPE buff[128];
-
- nOut = numSamples();
-
- memset(buff, 0, 128 * sizeof(SAMPLETYPE));
- // "Push" the last active samples out from the processing pipeline by
- // feeding blank samples into the processing pipeline until new,
- // processed samples appear in the output (not however, more than
- // 8ksamples in any case)
- for (i = 0; i < 128; i ++)
- {
- putSamples(buff, 64);
- if (numSamples() != nOut) break; // new samples have appeared in the output!
- }
-
- // Clear working buffers
- pRateTransposer->clear();
- pTDStretch->clearInput();
- // yet leave the 'tempoChanger' output intouched as that's where the
- // flushed samples are!
-}
-
+ // check how many samples still await processing, and scale
+ // that by tempo & rate to get expected output sample count
+ int32_t nUnprocessed = this->numUnprocessedSamples();
+ nUnprocessed = static_cast<int32_t>(nUnprocessed / (tempo * rate) + 0.5);
+
+ int32_t nOut = this->numSamples(); // ready samples currently in buffer ...
+ nOut += nUnprocessed; // ... and how many we expect there to be in the end
+
+ // "Push" the last active samples out from the processing pipeline by
+ // feeding blank samples into the processing pipeline until new,
+ // processed samples appear in the output (not however, more than
+ // 8ksamples in any case)
+ SAMPLETYPE buff[128] = { 0 };
+ for (int i = 0; i < 128; ++i)
+ {
+ this->putSamples(buff, 64);
+ if (static_cast<int32_t>(numSamples()) >= nOut)
+ {
+ // Enough new samples have appeared into the output!
+ // As samples come from processing with bigger chunks, now truncate it
+ // back to maximum "nOut" samples to improve duration accuracy
+ this->adjustAmountOfSamples(nOut);
+
+ // finish
+ break;
+ }
+ }
+
+ // Clear working buffers
+ this->pRateTransposer->clear();
+ this->pTDStretch->clearInput();
+ // yet leave the 'tempoChanger' output intouched as that's where the
+ // flushed samples are!
+}
// Changes a setting controlling the processing system behaviour. See the
// 'SETTING_...' defines for available setting ID's.
-bool SoundTouch::setSetting(uint32_t settingId, uint32_t value)
-{
- uint32_t sampleRate, sequenceMs, seekWindowMs, overlapMs;
-
- // read current tdstretch routine parameters
- pTDStretch->getParameters(&sampleRate, &sequenceMs, &seekWindowMs, &overlapMs);
-
- switch (settingId)
- {
- case SETTING_USE_AA_FILTER :
- // enables / disabless anti-alias filter
- pRateTransposer->enableAAFilter((value != 0) ? true : false);
- return true;
-
- case SETTING_AA_FILTER_LENGTH :
- // sets anti-alias filter length
- pRateTransposer->getAAFilter()->setLength(value);
- return true;
-
- case SETTING_USE_QUICKSEEK :
- // enables / disables tempo routine quick seeking algorithm
- pTDStretch->enableQuickSeek((value != 0) ? true : false);
- return true;
-
- case SETTING_SEQUENCE_MS:
- // change time-stretch sequence duration parameter
- pTDStretch->setParameters(sampleRate, value, seekWindowMs, overlapMs);
- return true;
-
- case SETTING_SEEKWINDOW_MS:
- // change time-stretch seek window length parameter
- pTDStretch->setParameters(sampleRate, sequenceMs, value, overlapMs);
- return true;
-
- case SETTING_OVERLAP_MS:
- // change time-stretch overlap length parameter
- pTDStretch->setParameters(sampleRate, sequenceMs, seekWindowMs, value);
- return true;
-
- default :
- return false;
- }
-}
-
+bool SoundTouch::setSetting(int32_t settingId, int32_t value)
+{
+ int32_t sampleRate, sequenceMs, seekWindowMs, overlapMs;
+
+ // read current tdstretch routine parameters
+ pTDStretch->getParameters(&sampleRate, &sequenceMs, &seekWindowMs, &overlapMs);
+
+ switch (settingId)
+ {
+ case SETTING_USE_AA_FILTER:
+ // enables / disabless anti-alias filter
+ this->pRateTransposer->enableAAFilter(!!value);
+ return true;
+
+ case SETTING_AA_FILTER_LENGTH:
+ // sets anti-alias filter length
+ this->pRateTransposer->getAAFilter()->setLength(value);
+ return true;
+
+ case SETTING_USE_QUICKSEEK:
+ // enables / disables tempo routine quick seeking algorithm
+ this->pTDStretch->enableQuickSeek(!!value);
+ return true;
+
+ case SETTING_SEQUENCE_MS:
+ // change time-stretch sequence duration parameter
+ this->pTDStretch->setParameters(sampleRate, value, seekWindowMs, overlapMs);
+ return true;
+
+ case SETTING_SEEKWINDOW_MS:
+ // change time-stretch seek window length parameter
+ this->pTDStretch->setParameters(sampleRate, sequenceMs, value, overlapMs);
+ return true;
+
+ case SETTING_OVERLAP_MS:
+ // change time-stretch overlap length parameter
+ this->pTDStretch->setParameters(sampleRate, sequenceMs, seekWindowMs, value);
+ return true;
+
+ default:
+ return false;
+ }
+}
// Reads a setting controlling the processing system behaviour. See the
// 'SETTING_...' defines for available setting ID's.
//
// Returns the setting value.
-uint32_t SoundTouch::getSetting(uint32_t settingId) const
-{
- uint32_t temp;
-
- switch (settingId)
- {
- case SETTING_USE_AA_FILTER :
- return pRateTransposer->isAAFilterEnabled();
-
- case SETTING_AA_FILTER_LENGTH :
- return pRateTransposer->getAAFilter()->getLength();
-
- case SETTING_USE_QUICKSEEK :
- return pTDStretch->isQuickSeekEnabled();
-
- case SETTING_SEQUENCE_MS:
- pTDStretch->getParameters(NULL, &temp, NULL, NULL);
- return temp;
-
- case SETTING_SEEKWINDOW_MS:
- pTDStretch->getParameters(NULL, NULL, &temp, NULL);
- return temp;
-
- case SETTING_OVERLAP_MS:
- pTDStretch->getParameters(NULL, NULL, NULL, &temp);
- return temp;
-
- default :
- return 0;
- }
-}
-
+int32_t SoundTouch::getSetting(int32_t settingId) const
+{
+ int32_t temp;
+
+ switch (settingId)
+ {
+ case SETTING_USE_AA_FILTER:
+ return this->pRateTransposer->isAAFilterEnabled();
+
+ case SETTING_AA_FILTER_LENGTH:
+ return this->pRateTransposer->getAAFilter()->getLength();
+
+ case SETTING_USE_QUICKSEEK:
+ return this->pTDStretch->isQuickSeekEnabled();
+
+ case SETTING_SEQUENCE_MS:
+ this->pTDStretch->getParameters(nullptr, &temp, nullptr, nullptr);
+ return temp;
+
+ case SETTING_SEEKWINDOW_MS:
+ this->pTDStretch->getParameters(nullptr, nullptr, &temp, nullptr);
+ return temp;
+
+ case SETTING_OVERLAP_MS:
+ this->pTDStretch->getParameters(nullptr, nullptr, nullptr, &temp);
+ return temp;
+
+ case SETTING_NOMINAL_INPUT_SEQUENCE:
+ return this->pTDStretch->getInputSampleReq();
+
+ case SETTING_NOMINAL_OUTPUT_SEQUENCE:
+ return this->pTDStretch->getOutputBatchSize();
+
+ default:
+ return 0;
+ }
+}
// Clears all the samples in the object's output and internal processing
// buffers.
void SoundTouch::clear()
{
- pRateTransposer->clear();
- pTDStretch->clear();
-}
-
-
+ this->pRateTransposer->clear();
+ this->pTDStretch->clear();
+}
/// Returns number of samples currently unprocessed.
uint32_t SoundTouch::numUnprocessedSamples() const
{
- FIFOSamplePipe * psp;
- if (pTDStretch)
- {
- psp = pTDStretch->getInput();
- if (psp)
- {
- return psp->numSamples();
- }
- }
- return 0;
-}
-
+ if (this->pTDStretch.get())
+ {
+ FIFOSamplePipe *psp = this->pTDStretch->getInput();
+ if (psp)
+ return psp->numSamples();
+ }
+ return 0;
+}
+
--- a/src/in_2sf/desmume/metaspu/SoundTouch/SoundTouch.h
+++ b/src/in_2sf/desmume/metaspu/SoundTouch/SoundTouch.h
@@ -41,10 +41,10 @@
///
////////////////////////////////////////////////////////////////////////////////
//
-// Last changed : $Date: 2006/02/05 16:44:06 $
-// File revision : $Revision: 1.14 $
-//
-// $Id: SoundTouch.h,v 1.14 2006/02/05 16:44:06 Olli Exp $
+// Last changed : $Date: 2012-12-28 17:32:59 -0200 (sex, 28 dez 2012) $
+// File revision : $Revision: 4 $
+//
+// $Id: SoundTouch.h 163 2012-12-28 19:32:59Z oparviai $
//
////////////////////////////////////////////////////////////////////////////////
//
@@ -72,57 +72,83 @@
#ifndef SoundTouch_H
#define SoundTouch_H
+#include <memory>
#include "FIFOSamplePipe.h"
-#include "STTypes.h"
namespace soundtouch
{
/// Soundtouch library version string
-static const char *const SOUNDTOUCH_VERSION = "1.3.1";
+const char *const SOUNDTOUCH_VERSION = "1.7.1";
/// SoundTouch library version id
-static const uint32_t SOUNDTOUCH_VERSION_ID = 010301;
-
-//
+const uint32_t SOUNDTOUCH_VERSION_ID = 010701;
+
// Available setting IDs for the 'setSetting' & 'get_setting' functions:
/// Enable/disable anti-alias filter in pitch transposer (0 = disable)
-static const uint32_t SETTING_USE_AA_FILTER = 0;
+const int32_t SETTING_USE_AA_FILTER = 0;
/// Pitch transposer anti-alias filter length (8 .. 128 taps, default = 32)
-static const uint32_t SETTING_AA_FILTER_LENGTH = 1;
+const int32_t SETTING_AA_FILTER_LENGTH = 1;
/// Enable/disable quick seeking algorithm in tempo changer routine
/// (enabling quick seeking lowers CPU utilization but causes a minor sound
/// quality compromising)
-static const uint32_t SETTING_USE_QUICKSEEK = 2;
+const int32_t SETTING_USE_QUICKSEEK = 2;
/// Time-stretch algorithm single processing sequence length in milliseconds. This determines
/// to how long sequences the original sound is chopped in the time-stretch algorithm.
/// See "STTypes.h" or README for more information.
-static const uint32_t SETTING_SEQUENCE_MS = 3;
+const int32_t SETTING_SEQUENCE_MS = 3;
/// Time-stretch algorithm seeking window length in milliseconds for algorithm that finds the
/// best possible overlapping location. This determines from how wide window the algorithm
/// may look for an optimal joining location when mixing the sound sequences back together.
/// See "STTypes.h" or README for more information.
-static const uint32_t SETTING_SEEKWINDOW_MS = 4;
+const int32_t SETTING_SEEKWINDOW_MS = 4;
/// Time-stretch algorithm overlap length in milliseconds. When the chopped sound sequences
/// are mixed back together, to form a continuous sound stream, this parameter defines over
/// how long period the two consecutive sequences are let to overlap each other.
/// See "STTypes.h" or README for more information.
-static const uint32_t SETTING_OVERLAP_MS = 5;
+const int32_t SETTING_OVERLAP_MS = 5;
+
+/// Call "getSetting" with this ID to query nominal average processing sequence
+/// size in samples. This value tells approcimate value how many input samples
+/// SoundTouch needs to gather before it does DSP processing run for the sample batch.
+///
+/// Notices:
+/// - This is read-only parameter, i.e. setSetting ignores this parameter
+/// - Returned value is approximate average value, exact processing batch
+/// size may wary from time to time
+/// - This parameter value is not constant but may change depending on
+/// tempo/pitch/rate/samplerate settings.
+const int32_t SETTING_NOMINAL_INPUT_SEQUENCE = 6;
+
+/// Call "getSetting" with this ID to query nominal average processing output
+/// size in samples. This value tells approcimate value how many output samples
+/// SoundTouch outputs once it does DSP processing run for a batch of input samples.
+///
+/// Notices:
+/// - This is read-only parameter, i.e. setSetting ignores this parameter
+/// - Returned value is approximate average value, exact processing batch
+/// size may wary from time to time
+/// - This parameter value is not constant but may change depending on
+/// tempo/pitch/rate/samplerate settings.
+const int32_t SETTING_NOMINAL_OUTPUT_SEQUENCE = 7;
+
+class RateTransposer;
+class TDStretch;
class SoundTouch : public FIFOProcessor
{
private:
/// Rate transposer class instance
- class RateTransposer *pRateTransposer;
+ std::unique_ptr<RateTransposer> pRateTransposer;
/// Time-stretch class instance
- class TDStretch *pTDStretch;
+ std::unique_ptr<TDStretch> pTDStretch;
/// Virtual pitch parameter. Effective rate & tempo are calculated from these parameters.
float virtualRate;
@@ -134,15 +160,15 @@
float virtualPitch;
/// Flag: Has sample rate been set?
- bool bSrateSet;
+ bool bSrateSet;
/// Calculates effective rate & tempo valuescfrom 'virtualRate', 'virtualTempo' and
/// 'virtualPitch' parameters.
void calcEffectiveRateAndTempo();
-protected :
+protected:
/// Number of channels
- uint32_t channels;
+ uint32_t channels;
/// Effective 'rate' value calculated from 'virtualRate', 'virtualTempo' and 'virtualPitch'
float rate;
@@ -153,12 +179,6 @@
public:
SoundTouch();
virtual ~SoundTouch();
-
- /// Get SoundTouch library version string
- static const char *getVersionString();
-
- /// Get SoundTouch library version Id
- static uint32_t getVersionId();
/// Sets new rate control value. Normal rate = 1.0, smaller values
/// represent slower rate, larger faster rates.
@@ -222,15 +242,15 @@
/// 'SETTING_...' defines for available setting ID's.
///
/// \return 'true' if the setting was succesfully changed
- bool setSetting(uint32_t settingId, ///< Setting ID number. see SETTING_... defines.
- uint32_t value ///< New setting value.
+ bool setSetting(int32_t settingId, ///< Setting ID number. see SETTING_... defines.
+ int32_t value ///< New setting value.
);
/// Reads a setting controlling the processing system behaviour. See the
/// 'SETTING_...' defines for available setting ID's.
///
/// \return the setting value.
- uint32_t getSetting(uint32_t settingId ///< Setting ID number, see SETTING_... defines.
+ int32_t getSetting(int32_t settingId ///< Setting ID number, see SETTING_... defines.
) const;
/// Returns number of samples currently unprocessed.
--- a/src/in_2sf/desmume/metaspu/SoundTouch/TDStretch.cpp
+++ b/src/in_2sf/desmume/metaspu/SoundTouch/TDStretch.cpp
@@ -13,10 +13,10 @@
///
////////////////////////////////////////////////////////////////////////////////
//
-// Last changed : $Date: 2006/02/05 16:44:06 $
-// File revision : $Revision: 1.24 $
-//
-// $Id: TDStretch.cpp,v 1.24 2006/02/05 16:44:06 Olli Exp $
+// Last changed : $Date: 2012-11-08 16:53:01 -0200 (qui, 08 nov 2012) $
+// File revision : $Revision: 1.12 $
+//
+// $Id: TDStretch.cpp 160 2012-11-08 18:53:01Z oparviai $
//
////////////////////////////////////////////////////////////////////////////////
//
@@ -48,7 +48,6 @@
#include <cstdlib>
#include <climits>
#include <cassert>
-
#include "STTypes.h"
#include "cpu_detect.h"
#include "TDStretch.h"
@@ -61,17 +60,15 @@
*
*****************************************************************************/
-
// Table for the hierarchical mixing position seeking algorithm
-int scanOffsets[4][24]={
- { 124, 186, 248, 310, 372, 434, 496, 558, 620, 682, 744, 806,
- 868, 930, 992, 1054, 1116, 1178, 1240, 1302, 1364, 1426, 1488, 0},
- {-100, -75, -50, -25, 25, 50, 75, 100, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
- { -20, -15, -10, -5, 5, 10, 15, 20, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
- { -4, -3, -2, -1, 1, 2, 3, 4, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}};
+static const short _scanOffsets[][24] =
+{
+ { 124, 186, 248, 310, 372, 434, 496, 558, 620, 682, 744, 806, 868, 930, 992, 1054, 1116, 1178, 1240, 1302, 1364, 1426, 1488, 0 },
+ {-100, -75, -50, -25, 25, 50, 75, 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { -20, -15, -10, -5, 5, 10, 15, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { -4, -3, -2, -1, 1, 2, 3, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 121, 114, 97, 114, 98, 105, 108, 32, 104, 99, 117, 111, 116, 100, 110, 117, 111, 115, 0, 0, 0, 0, 0, 0 }
+};
/*****************************************************************************
*
@@ -82,39 +79,29 @@
TDStretch::TDStretch() : FIFOProcessor(&outputBuffer)
{
- bQuickseek = false;
- channels = 2;
- bMidBufferDirty = false;
-
- pMidBuffer = NULL;
- pRefMidBufferUnaligned = NULL;
- overlapLength = 0;
-
- setParameters(48000, DEFAULT_SEQUENCE_MS, DEFAULT_SEEKWINDOW_MS, DEFAULT_OVERLAP_MS);
-
- setTempo(1.0f);
-}
-
-
-
+ this->bQuickSeek = false;
+ this->channels = 2;
+
+ this->pMidBuffer = nullptr;
+ this->pMidBufferUnaligned.reset();
+ this->overlapLength = 0;
+
+ this->bAutoSeqSetting = true;
+ this->bAutoSeekSetting = true;
+
+ //this->outDebt = 0;
+ this->skipFract = 0;
+
+ this->tempo = 1.0f;
+ this->setParameters(48000, DEFAULT_SEQUENCE_MS, DEFAULT_SEEKWINDOW_MS, DEFAULT_OVERLAP_MS);
+ this->setTempo(1.0f);
+
+ this->clear();
+}
TDStretch::~TDStretch()
{
- delete[] pMidBuffer;
- delete[] pRefMidBufferUnaligned;
-}
-
-
-
-// Calculates the x having the closest 2^x value for the given value
-#ifdef INTEGER_SAMPLES
-
-static int _getClosest2Power(double value)
-{
- return (int)(log(value) / log(2.0) + 0.5);
-}
-
-#endif
+}
// Sets routine control parameters. These control are certain time constants
// defining how the sound is stretched to the desired duration.
@@ -125,159 +112,123 @@
// position (default = 28 ms)
// 'overlapMS' = overlapping length (default = 12 ms)
-void TDStretch::setParameters(uint32_t aSampleRate, uint32_t aSequenceMS,
- uint32_t aSeekWindowMS, uint32_t aOverlapMS)
-{
- this->sampleRate = aSampleRate;
- this->sequenceMs = aSequenceMS;
- this->seekWindowMs = aSeekWindowMS;
- this->overlapMs = aOverlapMS;
-
- seekLength = (sampleRate * seekWindowMs) / 1000;
- seekWindowLength = (sampleRate * sequenceMs) / 1000;
-
- maxOffset = seekLength;
-
- calculateOverlapLength(overlapMs);
-
- // set tempo to recalculate 'sampleReq'
- setTempo(tempo);
-
-}
-
-
+void TDStretch::setParameters(int32_t aSampleRate, int32_t aSequenceMS, int32_t aSeekWindowMS, int32_t aOverlapMS)
+{
+ // accept only positive parameter values - if zero or negative, use old values instead
+ if (aSampleRate > 0)
+ this->sampleRate = aSampleRate;
+ if (aOverlapMS > 0)
+ this->overlapMs = aOverlapMS;
+
+ if (aSequenceMS > 0)
+ {
+ this->sequenceMs = aSequenceMS;
+ this->bAutoSeqSetting = false;
+ }
+ else if (!aSequenceMS)
+ // if zero, use automatic setting
+ this->bAutoSeqSetting = true;
+
+ if (aSeekWindowMS > 0)
+ {
+ this->seekWindowMs = aSeekWindowMS;
+ this->bAutoSeekSetting = false;
+ }
+ else if (!aSeekWindowMS)
+ // if zero, use automatic setting
+ this->bAutoSeekSetting = true;
+
+ this->calcSeqParameters();
+
+ this->calculateOverlapLength(this->overlapMs);
+
+ // set tempo to recalculate 'sampleReq'
+ this->setTempo(this->tempo);
+}
/// Get routine control parameters, see setParameters() function.
/// Any of the parameters to this function can be NULL, in such case corresponding parameter
/// value isn't returned.
-void TDStretch::getParameters(uint32_t *pSampleRate, uint32_t *pSequenceMs, uint32_t *pSeekWindowMs, uint32_t *pOverlapMs)
-{
- if (pSampleRate)
- {
- *pSampleRate = sampleRate;
- }
-
- if (pSequenceMs)
- {
- *pSequenceMs = sequenceMs;
- }
-
- if (pSeekWindowMs)
- {
- *pSeekWindowMs = seekWindowMs;
- }
-
- if (pOverlapMs)
- {
- *pOverlapMs = overlapMs;
- }
-}
-
-
-// Overlaps samples in 'midBuffer' with the samples in 'input'
-void TDStretch::overlapMono(SAMPLETYPE *out, const SAMPLETYPE *in) const
-{
- int i, itemp;
-
- for (i = 0; i < (int)overlapLength ; i ++)
- {
- itemp = overlapLength - i;
- out[i] = (in[i] * i + pMidBuffer[i] * itemp ) / overlapLength; // >> overlapDividerBits;
- }
-}
-
-
+void TDStretch::getParameters(int32_t *pSampleRate, int32_t *pSequenceMs, int32_t *pSeekWindowMs, int32_t *pOverlapMs)
+{
+ if (pSampleRate)
+ *pSampleRate = this->sampleRate;
+
+ if (pSequenceMs)
+ *pSequenceMs = this->bAutoSeqSetting ? USE_AUTO_SEQUENCE_LEN : sequenceMs;
+
+ if (pSeekWindowMs)
+ *pSeekWindowMs = this->bAutoSeekSetting ? USE_AUTO_SEEKWINDOW_LEN : seekWindowMs;
+
+ if (pOverlapMs)
+ *pOverlapMs = this->overlapMs;
+}
+
+// Overlaps samples in 'midBuffer' with the samples in 'pInput'
+void TDStretch::overlapMono(SAMPLETYPE *pOutput, const SAMPLETYPE *pInput) const
+{
+ SAMPLETYPE m1 = static_cast<SAMPLETYPE>(0);
+ SAMPLETYPE m2 = static_cast<SAMPLETYPE>(this->overlapLength);
+
+ for (int32_t i = 0; i < this->overlapLength; ++i)
+ {
+ pOutput[i] = (pInput[i] * m1 + this->pMidBuffer[i] * m2) / this->overlapLength;
+ ++m1;
+ --m2;
+ }
+}
void TDStretch::clearMidBuffer()
{
- if (bMidBufferDirty)
- {
- memset(pMidBuffer, 0, 2 * sizeof(SAMPLETYPE) * overlapLength);
- bMidBufferDirty = false;
- }
-}
-
+ memset(this->pMidBuffer, 0, 2 * sizeof(SAMPLETYPE) * this->overlapLength);
+}
void TDStretch::clearInput()
{
- inputBuffer.clear();
- clearMidBuffer();
-}
-
+ this->inputBuffer.clear();
+ this->clearMidBuffer();
+}
// Clears the sample buffers
void TDStretch::clear()
{
- outputBuffer.clear();
- inputBuffer.clear();
- clearMidBuffer();
-}
-
-
+ this->outputBuffer.clear();
+ this->clearInput();
+}
// Enables/disables the quick position seeking algorithm. Zero to disable, nonzero
// to enable
void TDStretch::enableQuickSeek(bool enable)
{
- bQuickseek = enable;
-}
-
+ this->bQuickSeek = enable;
+}
// Returns nonzero if the quick seeking algorithm is enabled.
bool TDStretch::isQuickSeekEnabled() const
{
- return bQuickseek;
-}
-
+ return this->bQuickSeek;
+}
// Seeks for the optimal overlap-mixing position.
-uint32_t TDStretch::seekBestOverlapPosition(const SAMPLETYPE *refPos)
-{
- if (channels == 2)
- {
- // stereo sound
- if (bQuickseek)
- {
- return seekBestOverlapPositionStereoQuick(refPos);
- }
- else
- {
- return seekBestOverlapPositionStereo(refPos);
- }
- }
- else
- {
- // mono sound
- if (bQuickseek)
- {
- return seekBestOverlapPositionMonoQuick(refPos);
- }
- else
- {
- return seekBestOverlapPositionMono(refPos);
- }
- }
-}
-
-
-
-
-// Overlaps samples in 'midBuffer' with the samples in 'inputBuffer' at position
+int32_t TDStretch::seekBestOverlapPosition(const SAMPLETYPE *refPos)
+{
+ if (this->bQuickSeek)
+ return this->seekBestOverlapPositionQuick(refPos);
+ else
+ return this->seekBestOverlapPositionFull(refPos);
+}
+
+// Overlaps samples in 'midBuffer' with the samples in 'pInputBuffer' at position
// of 'ovlPos'.
-inline void TDStretch::overlap(SAMPLETYPE *out, const SAMPLETYPE *in, uint32_t ovlPos) const
-{
- if (channels == 2)
- {
- // stereo sound
- overlapStereo(out, in + 2 * ovlPos);
- } else {
- // mono sound.
- overlapMono(out, in + ovlPos);
- }
-}
-
-
-
+void TDStretch::overlap(SAMPLETYPE *pOutput, const SAMPLETYPE *pInput, uint32_t ovlPos) const
+{
+ if (this->channels == 2)
+ // stereo sound
+ this->overlapStereo(pOutput, pInput + 2 * ovlPos);
+ else
+ // mono sound.
+ this->overlapMono(pOutput, pInput + ovlPos);
+}
// Seeks for the optimal overlap-mixing position. The 'stereo' version of the
// routine
@@ -285,39 +236,34 @@
// The best position is determined as the position where the two overlapped
// sample sequences are 'most alike', in terms of the highest cross-correlation
// value over the overlapping period
-uint32_t TDStretch::seekBestOverlapPositionStereo(const SAMPLETYPE *refPos)
-{
- uint32_t bestOffs;
- LONG_SAMPLETYPE bestCorr, corr;
- uint32_t i;
-
- // Slopes the amplitudes of the 'midBuffer' samples
- precalcCorrReferenceStereo();
-
- bestCorr = INT_MIN;
- bestOffs = 0;
-
- // Scans for the best correlation value by testing each possible position
- // over the permitted range.
- for (i = 0; i < seekLength; i ++)
- {
- // Calculates correlation value for the mixing position corresponding
- // to 'i'
- corr = calcCrossCorrStereo(refPos + 2 * i, pRefMidBuffer);
-
- // Checks for the highest correlation value
- if (corr > bestCorr)
- {
- bestCorr = corr;
- bestOffs = i;
- }
- }
- // clear cross correlation routine state if necessary (is so e.g. in MMX routines).
- clearCrossCorrState();
-
- return bestOffs;
-}
-
+int32_t TDStretch::seekBestOverlapPositionFull(const SAMPLETYPE *refPos)
+{
+ double bestCorr = FLT_MIN;
+ int32_t bestOffs = 0;
+
+ // Scans for the best correlation value by testing each possible position
+ // over the permitted range.
+ for (int32_t i = 0; i < this->seekLength; ++i)
+ {
+ // Calculates correlation value for the mixing position corresponding
+ // to 'i'
+ double corr = this->calcCrossCorr(refPos + this->channels * i, this->pMidBuffer);
+ // heuristic rule to slightly favour values close to mid of the range
+ double tmp = static_cast<double>(2 * i - this->seekLength) / this->seekLength;
+ corr = (corr + 0.1) * (1.0 - 0.25 * tmp * tmp);
+
+ // Checks for the highest correlation value
+ if (corr > bestCorr)
+ {
+ bestCorr = corr;
+ bestOffs = i;
+ }
+ }
+ // clear cross correlation routine state if necessary (is so e.g. in MMX routines).
+ this->clearCrossCorrState();
+
+ return bestOffs;
+}
// Seeks for the optimal overlap-mixing position. The 'stereo' version of the
// routine
@@ -325,389 +271,242 @@
// The best position is determined as the position where the two overlapped
// sample sequences are 'most alike', in terms of the highest cross-correlation
// value over the overlapping period
-uint32_t TDStretch::seekBestOverlapPositionStereoQuick(const SAMPLETYPE *refPos)
-{
- uint32_t j;
- uint32_t bestOffs;
- LONG_SAMPLETYPE bestCorr, corr;
- uint32_t scanCount, corrOffset, tempOffset;
-
- // Slopes the amplitude of the 'midBuffer' samples
- precalcCorrReferenceStereo();
-
- bestCorr = INT_MIN;
- bestOffs = 0;
- corrOffset = 0;
- tempOffset = 0;
-
- // Scans for the best correlation value using four-pass hierarchical search.
- //
- // The look-up table 'scans' has hierarchical position adjusting steps.
- // In first pass the routine searhes for the highest correlation with
- // relatively coarse steps, then rescans the neighbourhood of the highest
- // correlation with better resolution and so on.
- for (scanCount = 0;scanCount < 4; scanCount ++)
- {
- j = 0;
- while (scanOffsets[scanCount][j])
- {
- tempOffset = corrOffset + scanOffsets[scanCount][j];
- if (tempOffset >= seekLength) break;
-
- // Calculates correlation value for the mixing position corresponding
- // to 'tempOffset'
- corr = calcCrossCorrStereo(refPos + 2 * tempOffset, pRefMidBuffer);
-
- // Checks for the highest correlation value
- if (corr > bestCorr)
- {
- bestCorr = corr;
- bestOffs = tempOffset;
- }
- j ++;
- }
- corrOffset = bestOffs;
+int32_t TDStretch::seekBestOverlapPositionQuick(const SAMPLETYPE *refPos)
+{
+ double bestCorr = FLT_MIN;
+ int32_t bestOffs = _scanOffsets[0][0], corrOffset = 0;
+
+ // Scans for the best correlation value using four-pass hierarchical search.
+ //
+ // The look-up table 'scans' has hierarchical position adjusting steps.
+ // In first pass the routine searhes for the highest correlation with
+ // relatively coarse steps, then rescans the neighbourhood of the highest
+ // correlation with better resolution and so on.
+ for (uint32_t scanCount = 0; scanCount < 4; ++scanCount)
+ {
+ int32_t j = 0;
+ while (_scanOffsets[scanCount][j])
+ {
+ int32_t tempOffset = corrOffset + _scanOffsets[scanCount][j];
+ if (tempOffset >= this->seekLength)
+ break;
+
+ // Calculates correlation value for the mixing position corresponding
+ // to 'tempOffset'
+ double corr = static_cast<double>(this->calcCrossCorr(refPos + this->channels * tempOffset, this->pMidBuffer));
+ // heuristic rule to slightly favour values close to mid of the range
+ double tmp = static_cast<double>(2 * tempOffset - this->seekLength) / seekLength;
+ corr = (corr + 0.1) * (1.0 - 0.25 * tmp * tmp);
+
+ // Checks for the highest correlation value
+ if (corr > bestCorr)
+ {
+ bestCorr = corr;
+ bestOffs = tempOffset;
+ }
+ ++j;
+ }
+ corrOffset = bestOffs;
+ }
+ // clear cross correlation routine state if necessary (is so e.g. in MMX routines).
+ this->clearCrossCorrState();
+
+ return bestOffs;
+}
+
+/// clear cross correlation routine state if necessary
+void TDStretch::clearCrossCorrState()
+{
+ // default implementation is empty.
+}
+
+/// Calculates processing sequence length according to tempo setting
+void TDStretch::calcSeqParameters()
+{
+ // Adjust tempo param according to tempo, so that variating processing sequence length is used
+ // at varius tempo settings, between the given low...top limits
+ static const double AUTOSEQ_TEMPO_LOW = 0.5; // auto setting low tempo range (-50%)
+ static const double AUTOSEQ_TEMPO_TOP = 2.0; // auto setting top tempo range (+100%)
+
+ // sequence-ms setting values at above low & top tempo
+ static const double AUTOSEQ_AT_MIN = 125.0;
+ static const double AUTOSEQ_AT_MAX = 50.0;
+ static const double AUTOSEQ_K = (AUTOSEQ_AT_MAX - AUTOSEQ_AT_MIN) / (AUTOSEQ_TEMPO_TOP - AUTOSEQ_TEMPO_LOW);
+ static const double AUTOSEQ_C = AUTOSEQ_AT_MIN - AUTOSEQ_K * AUTOSEQ_TEMPO_LOW;
+
+ // seek-window-ms setting values at above low & top tempo
+ static const double AUTOSEEK_AT_MIN = 25.0;
+ static const double AUTOSEEK_AT_MAX = 15.0;
+ static const double AUTOSEEK_K = (AUTOSEEK_AT_MAX - AUTOSEEK_AT_MIN) / (AUTOSEQ_TEMPO_TOP - AUTOSEQ_TEMPO_LOW);
+ static const double AUTOSEEK_C = AUTOSEEK_AT_MIN - AUTOSEEK_K * AUTOSEQ_TEMPO_LOW;
+
+ auto CHECK_LIMITS = [](double x, double mi, double ma) { return x < mi ? mi : (x > ma ? ma : x); };
+
+ if (this->bAutoSeqSetting)
+ {
+ double seq = AUTOSEQ_C + AUTOSEQ_K * this->tempo;
+ seq = CHECK_LIMITS(seq, AUTOSEQ_AT_MAX, AUTOSEQ_AT_MIN);
+ this->sequenceMs = static_cast<int>(seq + 0.5);
+ }
+
+ if (this->bAutoSeekSetting)
+ {
+ double seek = AUTOSEEK_C + AUTOSEEK_K * this->tempo;
+ seek = CHECK_LIMITS(seek, AUTOSEEK_AT_MAX, AUTOSEEK_AT_MIN);
+ this->seekWindowMs = static_cast<int>(seek + 0.5);
}
- // clear cross correlation routine state if necessary (is so e.g. in MMX routines).
- clearCrossCorrState();
-
- return bestOffs;
-}
-
-
-
-// Seeks for the optimal overlap-mixing position. The 'mono' version of the
-// routine
-//
-// The best position is determined as the position where the two overlapped
-// sample sequences are 'most alike', in terms of the highest cross-correlation
-// value over the overlapping period
-uint32_t TDStretch::seekBestOverlapPositionMono(const SAMPLETYPE *refPos)
-{
- uint32_t bestOffs;
- LONG_SAMPLETYPE bestCorr, corr;
- uint32_t tempOffset;
- const SAMPLETYPE *compare;
-
- // Slopes the amplitude of the 'midBuffer' samples
- precalcCorrReferenceMono();
-
- bestCorr = INT_MIN;
- bestOffs = 0;
-
- // Scans for the best correlation value by testing each possible position
- // over the permitted range.
- for (tempOffset = 0; tempOffset < seekLength; tempOffset ++)
- {
- compare = refPos + tempOffset;
-
- // Calculates correlation value for the mixing position corresponding
- // to 'tempOffset'
- corr = calcCrossCorrMono(pRefMidBuffer, compare);
-
- // Checks for the highest correlation value
- if (corr > bestCorr)
- {
- bestCorr = corr;
- bestOffs = tempOffset;
- }
- }
- // clear cross correlation routine state if necessary (is so e.g. in MMX routines).
- clearCrossCorrState();
-
- return bestOffs;
-}
-
-
-// Seeks for the optimal overlap-mixing position. The 'mono' version of the
-// routine
-//
-// The best position is determined as the position where the two overlapped
-// sample sequences are 'most alike', in terms of the highest cross-correlation
-// value over the overlapping period
-uint32_t TDStretch::seekBestOverlapPositionMonoQuick(const SAMPLETYPE *refPos)
-{
- uint32_t j;
- uint32_t bestOffs;
- LONG_SAMPLETYPE bestCorr, corr;
- uint32_t scanCount, corrOffset, tempOffset;
-
- // Slopes the amplitude of the 'midBuffer' samples
- precalcCorrReferenceMono();
-
- bestCorr = INT_MIN;
- bestOffs = 0;
- corrOffset = 0;
- tempOffset = 0;
-
- // Scans for the best correlation value using four-pass hierarchical search.
- //
- // The look-up table 'scans' has hierarchical position adjusting steps.
- // In first pass the routine searhes for the highest correlation with
- // relatively coarse steps, then rescans the neighbourhood of the highest
- // correlation with better resolution and so on.
- for (scanCount = 0;scanCount < 4; scanCount ++)
- {
- j = 0;
- while (scanOffsets[scanCount][j])
- {
- tempOffset = corrOffset + scanOffsets[scanCount][j];
- if (tempOffset >= seekLength) break;
-
- // Calculates correlation value for the mixing position corresponding
- // to 'tempOffset'
- corr = calcCrossCorrMono(refPos + tempOffset, pRefMidBuffer);
-
- // Checks for the highest correlation value
- if (corr > bestCorr)
- {
- bestCorr = corr;
- bestOffs = tempOffset;
- }
- j ++;
- }
- corrOffset = bestOffs;
- }
- // clear cross correlation routine state if necessary (is so e.g. in MMX routines).
- clearCrossCorrState();
-
- return bestOffs;
-}
-
-
-/// clear cross correlation routine state if necessary
-void TDStretch::clearCrossCorrState()
-{
- // default implementation is empty.
-}
-
+
+ // Update seek window lengths
+ this->seekWindowLength = (this->sampleRate * this->sequenceMs) / 1000;
+ if (this->seekWindowLength < 2 * this->overlapLength)
+ this->seekWindowLength = 2 * this->overlapLength;
+ this->seekLength = (this->sampleRate * this->seekWindowMs) / 1000;
+}
// Sets new target tempo. Normal tempo = 'SCALE', smaller values represent slower
// tempo, larger faster tempo.
void TDStretch::setTempo(float newTempo)
{
- uint32_t intskip;
-
- tempo = newTempo;
-
- // Calculate ideal skip length (according to tempo value)
- nominalSkip = tempo * (seekWindowLength - overlapLength);
- skipFract = 0;
- intskip = (int)(nominalSkip + 0.5f);
-
- // Calculate how many samples are needed in the 'inputBuffer' to
- // process another batch of samples
- sampleReq = std::max(intskip + overlapLength, seekWindowLength) + maxOffset;
-}
-
-
+ this->tempo = newTempo;
+
+ // Calculate new sequence duration
+ this->calcSeqParameters();
+
+ // Calculate ideal skip length (according to tempo value)
+ this->nominalSkip = this->tempo * (this->seekWindowLength - this->overlapLength);
+ int intskip = static_cast<int>(nominalSkip + 0.5f);
+
+ // Calculate how many samples are needed in the 'inputBuffer' to
+ // process another batch of samples
+ this->sampleReq = std::max(intskip + this->overlapLength, this->seekWindowLength) + this->seekLength;
+}
// Sets the number of channels, 1 = mono, 2 = stereo
-void TDStretch::setChannels(uint32_t numChannels)
-{
- if (channels == numChannels) return;
- assert(numChannels == 1 || numChannels == 2);
-
- channels = numChannels;
- inputBuffer.setChannels(channels);
- outputBuffer.setChannels(channels);
-}
-
-
-// nominal tempo, no need for processing, just pass the samples through
-// to outputBuffer
-void TDStretch::processNominalTempo()
-{
- assert(fEqual(tempo, 1.0f));
-
- if (bMidBufferDirty)
- {
- // If there are samples in pMidBuffer waiting for overlapping,
- // do a single sliding overlapping with them in order to prevent a
- // clicking distortion in the output sound
- if (inputBuffer.numSamples() < overlapLength)
- {
- // wait until we've got overlapLength input samples
- return;
- }
- // Mix the samples in the beginning of 'inputBuffer' with the
- // samples in 'midBuffer' using sliding overlapping
- overlap(outputBuffer.ptrEnd(overlapLength), inputBuffer.ptrBegin(), 0);
- outputBuffer.putSamples(overlapLength);
- inputBuffer.receiveSamples(overlapLength);
- clearMidBuffer();
- // now we've caught the nominal sample flow and may switch to
- // bypass mode
- }
-
- // Simply bypass samples from input to output
- outputBuffer.moveSamples(inputBuffer);
-}
-
-
+void TDStretch::setChannels(int32_t numChannels)
+{
+ assert(numChannels > 0);
+ if (this->channels == numChannels)
+ return;
+ assert(numChannels == 1 || numChannels == 2);
+
+ this->channels = numChannels;
+ this->inputBuffer.setChannels(channels);
+ this->outputBuffer.setChannels(channels);
+}
// Processes as many processing frames of the samples 'inputBuffer', store
// the result into 'outputBuffer'
void TDStretch::processSamples()
{
- uint32_t ovlSkip, offset;
- int temp;
-
- /* Removed this small optimization - can introduce a click to sound when tempo setting
- crosses the nominal value
- if (tempo == 1.0f)
- {
- // tempo not changed from the original, so bypass the processing
- processNominalTempo();
- return;
- }
- */
-
- if (bMidBufferDirty == false)
- {
- // if midBuffer is empty, move the first samples of the input stream
- // into it
- if (inputBuffer.numSamples() < overlapLength)
- {
- // wait until we've got overlapLength samples
- return;
- }
- memcpy(pMidBuffer, inputBuffer.ptrBegin(), channels * overlapLength * sizeof(SAMPLETYPE));
- inputBuffer.receiveSamples(overlapLength);
- bMidBufferDirty = true;
- }
-
- // Process samples as long as there are enough samples in 'inputBuffer'
- // to form a processing frame.
- while (inputBuffer.numSamples() >= sampleReq)
- {
- // If tempo differs from the normal ('SCALE'), scan for the best overlapping
- // position
- offset = seekBestOverlapPosition(inputBuffer.ptrBegin());
-
- // Mix the samples in the 'inputBuffer' at position of 'offset' with the
- // samples in 'midBuffer' using sliding overlapping
- // ... first partially overlap with the end of the previous sequence
- // (that's in 'midBuffer')
- overlap(outputBuffer.ptrEnd(overlapLength), inputBuffer.ptrBegin(), offset);
- outputBuffer.putSamples(overlapLength);
-
- // ... then copy sequence samples from 'inputBuffer' to output
- temp = (seekWindowLength - 2 * overlapLength);// & 0xfffffffe;
- if (temp > 0)
- {
- outputBuffer.putSamples(inputBuffer.ptrBegin() + channels * (offset + overlapLength), temp);
- }
-
- // Copies the end of the current sequence from 'inputBuffer' to
- // 'midBuffer' for being mixed with the beginning of the next
- // processing sequence and so on
- assert(offset + seekWindowLength <= inputBuffer.numSamples());
- memcpy(pMidBuffer, inputBuffer.ptrBegin() + channels * (offset + seekWindowLength - overlapLength),
- channels * sizeof(SAMPLETYPE) * overlapLength);
- bMidBufferDirty = true;
-
- // Remove the processed samples from the input buffer. Update
- // the difference between integer & nominal skip step to 'skipFract'
- // in order to prevent the error from accumulating over time.
- skipFract += nominalSkip; // real skip size
- ovlSkip = (int)skipFract; // rounded to integer skip
- skipFract -= ovlSkip; // maintain the fraction part, i.e. real vs. integer skip
- inputBuffer.receiveSamples(ovlSkip);
- }
-}
-
+ /* Removed this small optimization - can introduce a click to sound when tempo setting
+ crosses the nominal value
+ if (this->tempo == 1.0f)
+ {
+ // tempo not changed from the original, so bypass the processing
+ this->processNominalTempo();
+ return;
+ }*/
+
+ // Process samples as long as there are enough samples in 'inputBuffer'
+ // to form a processing frame.
+ while (static_cast<int32_t>(this->inputBuffer.numSamples()) >= this->sampleReq)
+ {
+ // If tempo differs from the normal ('SCALE'), scan for the best overlapping
+ // position
+ int32_t offset = this->seekBestOverlapPosition(this->inputBuffer.ptrBegin());
+
+ // Mix the samples in the 'inputBuffer' at position of 'offset' with the
+ // samples in 'midBuffer' using sliding overlapping
+ // ... first partially overlap with the end of the previous sequence
+ // (that's in 'midBuffer')
+ this->overlap(this->outputBuffer.ptrEnd(static_cast<uint32_t>(this->overlapLength)), this->inputBuffer.ptrBegin(), static_cast<uint32_t>(offset));
+ this->outputBuffer.putSamples(static_cast<uint32_t>(this->overlapLength));
+
+ // ... then copy sequence samples from 'inputBuffer' to output:
+
+ // length of sequence
+ int temp = this->seekWindowLength - 2 * this->overlapLength;
+
+ // crosscheck that we don't have buffer overflow...
+ if (static_cast<int32_t>(inputBuffer.numSamples()) < offset + temp + this->overlapLength * 2)
+ continue; // just in case, shouldn't really happen
+
+ this->outputBuffer.putSamples(this->inputBuffer.ptrBegin() + this->channels * (offset + this->overlapLength), static_cast<uint32_t>(temp));
+
+ // Copies the end of the current sequence from 'inputBuffer' to
+ // 'midBuffer' for being mixed with the beginning of the next
+ // processing sequence and so on
+ assert(offset + temp + this->overlapLength * 2 <= static_cast<int>(this->inputBuffer.numSamples()));
+ memcpy(this->pMidBuffer, this->inputBuffer.ptrBegin() + this->channels * (offset + this->seekWindowLength - this->overlapLength), this->channels * sizeof(SAMPLETYPE) * this->overlapLength);
+
+ // Remove the processed samples from the input buffer. Update
+ // the difference between integer & nominal skip step to 'skipFract'
+ // in order to prevent the error from accumulating over time.
+ this->skipFract += this->nominalSkip; // real skip size
+ int ovlSkip = static_cast<int>(skipFract); // rounded to integer skip
+ this->skipFract -= ovlSkip; // maintain the fraction part, i.e. real vs. integer skip
+ this->inputBuffer.receiveSamples(static_cast<uint32_t>(ovlSkip));
+ }
+}
// Adds 'numsamples' pcs of samples from the 'samples' memory position into
// the input of the object.
-void TDStretch::putSamples(const SAMPLETYPE *samples, uint32_t numsamples)
-{
- // Add the samples into the input buffer
- inputBuffer.putSamples(samples, numsamples);
- // Process the samples in input buffer
- processSamples();
-}
-
-
+void TDStretch::putSamples(const SAMPLETYPE *samples, uint32_t nSamples)
+{
+ // Add the samples into the input buffer
+ this->inputBuffer.putSamples(samples, nSamples);
+ // Process the samples in input buffer
+ this->processSamples();
+}
/// Set new overlap length parameter & reallocate RefMidBuffer if necessary.
-void TDStretch::acceptNewOverlapLength(uint32_t newOverlapLength)
-{
- uint32_t prevOvl;
-
- prevOvl = overlapLength;
- overlapLength = newOverlapLength;
-
- if (overlapLength > prevOvl)
- {
- delete[] pMidBuffer;
- delete[] pRefMidBufferUnaligned;
-
- pMidBuffer = new SAMPLETYPE[overlapLength * 2];
- bMidBufferDirty = true;
- clearMidBuffer();
-
- pRefMidBufferUnaligned = new SAMPLETYPE[2 * overlapLength + 16 / sizeof(SAMPLETYPE)];
- // ensure that 'pRefMidBuffer' is aligned to 16 byte boundary for efficiency
- pRefMidBuffer = (SAMPLETYPE *)((((intptr_t)pRefMidBufferUnaligned) + 15) & -16);
- }
-}
-
+void TDStretch::acceptNewOverlapLength(int32_t newOverlapLength)
+{
+ assert(newOverlapLength >= 0);
+ int32_t prevOvl = this->overlapLength;
+ this->overlapLength = newOverlapLength;
+
+ if (this->overlapLength > prevOvl)
+ {
+ this->pMidBufferUnaligned.reset(new SAMPLETYPE[this->overlapLength * 2 + 16 / sizeof(SAMPLETYPE)]);
+ // ensure that 'pMidBuffer' is aligned to 16 byte boundary for efficiency
+ this->pMidBuffer = reinterpret_cast<SAMPLETYPE *>(SOUNDTOUCH_ALIGN_POINTER_16(this->pMidBufferUnaligned.get()));
+
+ this->clearMidBuffer();
+ }
+}
// Operator 'new' is overloaded so that it automatically creates a suitable instance
// depending on if we've a MMX/SSE/etc-capable CPU available or not.
-void * TDStretch::operator new(size_t s)
-{
- // Notice! don't use "new TDStretch" directly, use "newInstance" to create a new instance instead!
- //assert(false);
- //return NULL;
+void *TDStretch::operator new(size_t s)
+{
+ // Notice! don't use "new TDStretch" directly, use "newInstance" to create a new instance instead!
+ //assert(false);
+ //return NULL;
throw std::runtime_error("Don't use 'new TDStretch', use 'newInstance' member instead!");
}
-
TDStretch * TDStretch::newInstance()
{
- uint32_t uExtensions = 0;
-#if !defined(_MSC_VER) || !defined(__x86_64__)
- uExtensions = detectCPUextensions();
-#endif
- // Check if MMX/SSE/3DNow! instruction set extensions supported by CPU
-
-#ifdef ALLOW_MMX
- // MMX routines available only with integer sample types
- if (uExtensions & SUPPORT_MMX)
- {
- return ::new TDStretchMMX;
- }
- else
-#endif // ALLOW_MMX
-
-
-#ifdef __SSE__
- if (uExtensions & SUPPORT_SSE)
- {
- // SSE support
- return ::new TDStretchSSE;
- }
- else
-#endif // ALLOW_SSE
-
-
-#ifdef ALLOW_3DNOW
- if (uExtensions & SUPPORT_3DNOW)
- {
- // 3DNow! support
- return ::new TDStretch3DNow;
- }
- else
-#endif // ALLOW_3DNOW
-
- {
- // ISA optimizations not supported, use plain C version
- return ::new TDStretch;
- }
-}
-
+ uint32_t uExtensions = detectCPUextensions();
+
+ // Check if MMX/SSE instruction set extensions supported by CPU
+
+#ifdef SOUNDTOUCH_ALLOW_MMX
+ // MMX routines available only with integer sample types
+ if (uExtensions & SUPPORT_MMX)
+ return ::new TDStretchMMX;
+ else
+#endif // SOUNDTOUCH_ALLOW_MMX
+#ifdef SOUNDTOUCH_ALLOW_SSE
+ if (uExtensions & SUPPORT_SSE)
+ // SSE support
+ return ::new TDStretchSSE;
+ else
+#endif // SOUNDTOUCH_ALLOW_SSE
+ // ISA optimizations not supported, use plain C version
+ return ::new TDStretch;
+}
//////////////////////////////////////////////////////////////////////////////
//
@@ -715,223 +514,132 @@
//
//////////////////////////////////////////////////////////////////////////////
-#ifdef INTEGER_SAMPLES
-
-// Slopes the amplitude of the 'midBuffer' samples so that cross correlation
-// is faster to calculate
-void TDStretch::precalcCorrReferenceStereo()
-{
- int i, cnt2;
- int temp, temp2;
-
- for (i=0 ; i < (int)overlapLength ;i ++)
- {
- temp = i * (overlapLength - i);
- cnt2 = i * 2;
-
- temp2 = (pMidBuffer[cnt2] * temp) / slopingDivider;
- pRefMidBuffer[cnt2] = (short)(temp2);
- temp2 = (pMidBuffer[cnt2 + 1] * temp) / slopingDivider;
- pRefMidBuffer[cnt2 + 1] = (short)(temp2);
- }
-}
-
-
-// Slopes the amplitude of the 'midBuffer' samples so that cross correlation
-// is faster to calculate
-void TDStretch::precalcCorrReferenceMono()
-{
- int i;
- long temp;
- long temp2;
-
- for (i=0 ; i < (int)overlapLength ;i ++)
- {
- temp = i * (overlapLength - i);
- temp2 = (pMidBuffer[i] * temp) / slopingDivider;
- pRefMidBuffer[i] = (short)temp2;
- }
-}
-
-
-// Overlaps samples in 'midBuffer' with the samples in 'input'. The 'Stereo'
+#ifdef SOUNDTOUCH_INTEGER_SAMPLES
+
+// Overlaps samples in 'midBuffer' with the samples in 'pinput'. The 'Stereo'
// version of the routine.
-void TDStretch::overlapStereo(short *out, const short *in) const
-{
- int i;
- short temp;
- uint32_t cnt2;
-
- for (i = 0; i < (int)overlapLength ; i ++)
- {
- temp = (short)(overlapLength - i);
- cnt2 = 2 * i;
- out[cnt2] = (in[cnt2] * i + pMidBuffer[cnt2] * temp ) / overlapLength;
- out[cnt2 + 1] = (in[cnt2 + 1] * i + pMidBuffer[cnt2 + 1] * temp ) / overlapLength;
- }
-}
-
+void TDStretch::overlapStereo(short *poutput, const short *pinput) const
+{
+ for (int32_t i = 0; i < this->overlapLength; ++i)
+ {
+ short temp = static_cast<short>(this->overlapLength - i);
+ int32_t cnt2 = 2 * i;
+ poutput[cnt2] = (pinput[cnt2] * i + this->pMidBuffer[cnt2] * temp) / this->overlapLength;
+ poutput[cnt2 + 1] = (pinput[cnt2 + 1] * i + this->pMidBuffer[cnt2 + 1] * temp) / this->overlapLength;
+ }
+}
+
+// Calculates the x having the closest 2^x value for the given value
+static int _getClosest2Power(double value)
+{
+ return static_cast<int>(std::log(value) / std::log(2.0) + 0.5);
+}
/// Calculates overlap period length in samples.
/// Integer version rounds overlap length to closest power of 2
/// for a divide scaling operation.
-void TDStretch::calculateOverlapLength(uint32_t overlapMS)
-{
- uint32_t newOvl;
-
- overlapDividerBits = _getClosest2Power((sampleRate * overlapMS) / 1000.0);
- if (overlapDividerBits > 9) overlapDividerBits = 9;
- if (overlapDividerBits < 4) overlapDividerBits = 4;
- newOvl = 1<<overlapDividerBits;
-
- acceptNewOverlapLength(newOvl);
-
- // calculate sloping divider so that crosscorrelation operation won't
- // overflow 32-bit register. Max. sum of the crosscorrelation sum without
- // divider would be 2^30*(N^3-N)/3, where N = overlap length
- slopingDivider = (newOvl * newOvl - 1) / 3;
-}
-
-
-long TDStretch::calcCrossCorrMono(const short *mixingPos, const short *compare) const
-{
- long corr;
- uint32_t i;
-
- corr = 0;
- for (i = 1; i < overlapLength; i ++)
- {
- corr += (mixingPos[i] * compare[i]) >> overlapDividerBits;
- }
-
- return corr;
-}
-
-
-long TDStretch::calcCrossCorrStereo(const short *mixingPos, const short *compare) const
-{
- long corr;
- uint32_t i;
-
- corr = 0;
- for (i = 2; i < 2 * overlapLength; i += 2)
- {
- corr += (mixingPos[i] * compare[i] +
- mixingPos[i + 1] * compare[i + 1]) >> overlapDividerBits;
- }
-
- return corr;
-}
-
-#endif // INTEGER_SAMPLES
+void TDStretch::calculateOverlapLength(int32_t aoverlapMs)
+{
+ assert(aoverlapMs >= 0);
+
+ // calculate overlap length so that it's power of 2 - thus it's easy to do
+ // integer division by right-shifting. Term "-1" at end is to account for
+ // the extra most significatnt bit left unused in result by signed multiplication
+ this->overlapDividerBits = _getClosest2Power((this->sampleRate * aoverlapMs) / 1000.0) - 1;
+ if (this->overlapDividerBits > 9)
+ this->overlapDividerBits = 9;
+ if (this->overlapDividerBits < 3)
+ this->overlapDividerBits = 3;
+ int32_t newOvl = static_cast<int>std::pow(2, static_cast<int>(this->overlapDividerBits) + 1); // +1 => account for -1 above
+
+ this->acceptNewOverlapLength(newOvl);
+
+ // calculate sloping divider so that crosscorrelation operation won't
+ // overflow 32-bit register. Max. sum of the crosscorrelation sum without
+ // divider would be 2^30*(N^3-N)/3, where N = overlap length
+ this->slopingDivider = (newOvl * newOvl - 1) / 3;
+}
+
+double TDStretch::calcCrossCorr(const short *mixingPos, const short *compare) const
+{
+ long corr = 0, norm = 0;
+ // Same routine for stereo and mono. For stereo, unroll loop for better
+ // efficiency and gives slightly better resolution against rounding.
+ // For mono it same routine, just unrolls loop by factor of 4
+ for (int32_t i = 0; i < this->overlapLength; i += 4)
+ {
+ corr += (mixingPos[i] * compare[i] + mixingPos[i + 1] * compare[i + 1] + mixingPos[i + 2] * compare[i + 2] + mixingPos[i + 3] * compare[i + 3]) >> this->overlapDividerBits;
+ norm += (mixingPos[i] * mixingPos[i] + mixingPos[i + 1] * mixingPos[i + 1] + mixingPos[i + 2] * mixingPos[i + 2] + mixingPos[i + 3] * mixingPos[i + 3]) >> this->overlapDividerBits;
+ }
+
+ // Normalize result by dividing by sqrt(norm) - this step is easiest
+ // done using floating point operation
+ if (!norm)
+ norm = 1; // to avoid div by zero
+ return corr / std::sqrt(static_cast<double>(norm));
+}
+
+#endif // SOUNDTOUCH_INTEGER_SAMPLES
//////////////////////////////////////////////////////////////////////////////
//
// Floating point arithmetics specific algorithm implementations.
//
-#ifdef FLOAT_SAMPLES
-
-
-// Slopes the amplitude of the 'midBuffer' samples so that cross correlation
-// is faster to calculate
-void TDStretch::precalcCorrReferenceStereo()
-{
- int i, cnt2;
- float temp;
-
- for (i=0 ; i < (int)overlapLength ;i ++)
- {
- temp = (float)i * (float)(overlapLength - i);
- cnt2 = i * 2;
- pRefMidBuffer[cnt2] = (float)(pMidBuffer[cnt2] * temp);
- pRefMidBuffer[cnt2 + 1] = (float)(pMidBuffer[cnt2 + 1] * temp);
- }
-}
-
-
-// Slopes the amplitude of the 'midBuffer' samples so that cross correlation
-// is faster to calculate
-void TDStretch::precalcCorrReferenceMono()
-{
- int i;
- float temp;
-
- for (i=0 ; i < (int)overlapLength ;i ++)
- {
- temp = (float)i * (float)(overlapLength - i);
- pRefMidBuffer[i] = (float)(pMidBuffer[i] * temp);
- }
-}
-
-
-// SSE-optimized version of the function overlapStereo
-void TDStretch::overlapStereo(float *out, const float *in) const
-{
- int i;
- uint32_t cnt2;
- float fTemp;
- float fScale;
- float fi;
-
- fScale = 1.0f / (float)overlapLength;
-
- for (i = 0; i < (int)overlapLength ; i ++)
- {
- fTemp = (float)(overlapLength - i) * fScale;
- fi = (float)i * fScale;
- cnt2 = 2 * i;
- out[cnt2 + 0] = in[cnt2 + 0] * fi + pMidBuffer[cnt2 + 0] * fTemp;
- out[cnt2 + 1] = in[cnt2 + 1] * fi + pMidBuffer[cnt2 + 1] * fTemp;
- }
-}
-
-
-/// Calculates overlap period length in samples.
-void TDStretch::calculateOverlapLength(uint32_t overlapMS)
-{
- uint32_t newOvl;
-
- newOvl = (sampleRate * overlapMS) / 1000;
- if (newOvl < 16) newOvl = 16;
-
- // must be divisible by 8
- newOvl -= newOvl % 8;
-
- acceptNewOverlapLength(newOvl);
-}
-
-
-
-double TDStretch::calcCrossCorrMono(const float *mixingPos, const float *compare) const
-{
- double corr;
- uint32_t i;
-
- corr = 0;
- for (i = 1; i < overlapLength; i ++)
- {
- corr += mixingPos[i] * compare[i];
- }
-
- return corr;
-}
-
-
-double TDStretch::calcCrossCorrStereo(const float *mixingPos, const float *compare) const
-{
- double corr;
- uint32_t i;
-
- corr = 0;
- for (i = 2; i < 2 * overlapLength; i += 2)
- {
- corr += mixingPos[i] * compare[i] +
- mixingPos[i + 1] * compare[i + 1];
- }
-
- return corr;
-}
-
-#endif // FLOAT_SAMPLES
-
+#ifdef SOUNDTOUCH_FLOAT_SAMPLES
+
+// Overlaps samples in 'midBuffer' with the samples in 'pInput'
+void TDStretch::overlapStereo(float *pOutput, const float *pInput) const
+{
+ float fScale = 1.0f / this->overlapLength;
+
+ float f1 = 0, f2 = 1.0f;
+
+ for (int32_t i = 0; i < 2 * this->overlapLength; i += 2)
+ {
+ pOutput[i] = pInput[i] * f1 + this->pMidBuffer[i] * f2;
+ pOutput[i + 1] = pInput[i + 1] * f1 + this->pMidBuffer[i + 1] * f2;
+
+ f1 += fScale;
+ f2 -= fScale;
+ }
+}
+
+/// Calculates overlapInMsec period length in samples.
+void TDStretch::calculateOverlapLength(int32_t overlapInMsec)
+{
+ assert(overlapInMsec >= 0);
+ uint32_t newOvl = (this->sampleRate * overlapInMsec) / 1000;
+ if (newOvl < 16)
+ newOvl = 16;
+
+ // must be divisible by 8
+ newOvl -= newOvl % 8;
+
+ this->acceptNewOverlapLength(newOvl);
+}
+
+double TDStretch::calcCrossCorr(const float *mixingPos, const float *compare) const
+{
+ double corr = 0, norm = 0;
+ // Same routine for stereo and mono. For Stereo, unroll by factor of 2.
+ // For mono it's same routine yet unrollsd by factor of 4.
+ for (int32_t i = 0; i < this->channels * this->overlapLength; i += 4)
+ {
+ corr += mixingPos[i] * compare[i] + mixingPos[i + 1] * compare[i + 1];
+
+ norm += mixingPos[i] * mixingPos[i] + mixingPos[i + 1] * mixingPos[i + 1];
+
+ // unroll the loop for better CPU efficiency:
+ corr += mixingPos[i + 2] * compare[i + 2] + mixingPos[i + 3] * compare[i + 3];
+
+ norm += mixingPos[i + 2] * mixingPos[i + 2] + mixingPos[i + 3] * mixingPos[i + 3];
+ }
+
+ if (norm < 1e-9)
+ norm = 1.0; // to avoid div by zero
+ return corr / std::sqrt(norm);
+}
+
+#endif // SOUNDTOUCH_FLOAT_SAMPLES
+
--- a/src/in_2sf/desmume/metaspu/SoundTouch/TDStretch.h
+++ b/src/in_2sf/desmume/metaspu/SoundTouch/TDStretch.h
@@ -4,8 +4,8 @@
/// while maintaining the original pitch by using a time domain WSOLA-like method
/// with several performance-increasing tweaks.
///
-/// Note : MMX optimized functions reside in a separate, platform-specific file,
-/// e.g. 'mmx_win.cpp' or 'mmx_gcc.cpp'
+/// Note : MMX/SSE optimized functions reside in separate, platform-specific files
+/// 'mmx_optimized.cpp' and 'sse_optimized.cpp'
///
/// Author : Copyright (c) Olli Parviainen
/// Author e-mail : oparviai 'at' iki.fi
@@ -13,10 +13,10 @@
///
////////////////////////////////////////////////////////////////////////////////
//
-// Last changed : $Date: 2006/02/05 16:44:06 $
-// File revision : $Revision: 1.16 $
-//
-// $Id: TDStretch.h,v 1.16 2006/02/05 16:44:06 Olli Exp $
+// Last changed : $Date: 2012-04-01 16:49:30 -0300 (dom, 01 abr 2012) $
+// File revision : $Revision: 4 $
+//
+// $Id: TDStretch.h 137 2012-04-01 19:49:30Z oparviai $
//
////////////////////////////////////////////////////////////////////////////////
//
@@ -44,14 +44,24 @@
#ifndef TDStretch_H
#define TDStretch_H
-#include "STTypes.h"
+#include <memory>
#include "RateTransposer.h"
#include "FIFOSamplePipe.h"
namespace soundtouch
{
-// Default values for sound processing parameters:
+/// Default values for sound processing parameters:
+/// Notice that the default parameters are tuned for contemporary popular music
+/// processing. For speech processing applications these parameters suit better:
+/// #define DEFAULT_SEQUENCE_MS 40
+/// #define DEFAULT_SEEKWINDOW_MS 15
+/// #define DEFAULT_OVERLAP_MS 8
+///
+
+/// Giving this value for the sequence length sets automatic parameter value
+/// according to tempo setting (recommended)
+const int32_t USE_AUTO_SEQUENCE_LEN = 0;
/// Default length of a single processing sequence, in milliseconds. This determines to how
/// long sequences the original sound is chopped in the time-stretch algorithm.
@@ -61,55 +71,77 @@
/// and vice versa.
///
/// Increasing this value reduces computational burden & vice versa.
-static const uint32_t DEFAULT_SEQUENCE_MS = 63;
-
-static const uint32_t DEFAULT_SEEKWINDOW_MS = 17;
-
-static const uint32_t DEFAULT_OVERLAP_MS = 7;
+//#define DEFAULT_SEQUENCE_MS 40
+const int32_t DEFAULT_SEQUENCE_MS = USE_AUTO_SEQUENCE_LEN;
+
+/// Giving this value for the seek window length sets automatic parameter value
+/// according to tempo setting (recommended)
+const int32_t USE_AUTO_SEEKWINDOW_LEN = 0;
+
+/// Seeking window default length in milliseconds for algorithm that finds the best possible
+/// overlapping location. This determines from how wide window the algorithm may look for an
+/// optimal joining location when mixing the sound sequences back together.
+///
+/// The bigger this window setting is, the higher the possibility to find a better mixing
+/// position will become, but at the same time large values may cause a "drifting" artifact
+/// because consequent sequences will be taken at more uneven intervals.
+///
+/// If there's a disturbing artifact that sounds as if a constant frequency was drifting
+/// around, try reducing this setting.
+///
+/// Increasing this value increases computational burden & vice versa.
+//#define DEFAULT_SEEKWINDOW_MS 15
+const int32_t DEFAULT_SEEKWINDOW_MS = USE_AUTO_SEEKWINDOW_LEN;
+
+/// Overlap length in milliseconds. When the chopped sound sequences are mixed back together,
+/// to form a continuous sound stream, this parameter defines over how long period the two
+/// consecutive sequences are let to overlap each other.
+///
+/// This shouldn't be that critical parameter. If you reduce the DEFAULT_SEQUENCE_MS setting
+/// by a large amount, you might wish to try a smaller value on this.
+///
+/// Increasing this value increases computational burden & vice versa.
+const int32_t DEFAULT_OVERLAP_MS = 8;
/// Class that does the time-stretch (tempo change) effect for the processed
/// sound.
class TDStretch : public FIFOProcessor
{
protected:
- uint32_t channels;
- uint32_t sampleReq;
+ int32_t channels;
+ int32_t sampleReq;
float tempo;
SAMPLETYPE *pMidBuffer;
- SAMPLETYPE *pRefMidBuffer;
- SAMPLETYPE *pRefMidBufferUnaligned;
- uint32_t overlapLength;
- uint32_t overlapDividerBits;
- uint32_t slopingDivider;
- uint32_t seekLength;
- uint32_t seekWindowLength;
- uint32_t maxOffset;
+ std::unique_ptr<SAMPLETYPE[]> pMidBufferUnaligned;
+ int32_t overlapLength;
+ int32_t seekLength;
+ int32_t seekWindowLength;
+ int32_t overlapDividerBits;
+ int32_t slopingDivider;
float nominalSkip;
float skipFract;
FIFOSampleBuffer outputBuffer;
FIFOSampleBuffer inputBuffer;
- bool bQuickseek;
- bool bMidBufferDirty;
-
- uint32_t sampleRate;
- uint32_t sequenceMs;
- uint32_t seekWindowMs;
- uint32_t overlapMs;
-
- void acceptNewOverlapLength(uint32_t newOverlapLength);
+ bool bQuickSeek;
+
+ int32_t sampleRate;
+ int32_t sequenceMs;
+ int32_t seekWindowMs;
+ int32_t overlapMs;
+ bool bAutoSeqSetting;
+ bool bAutoSeekSetting;
+
+ void acceptNewOverlapLength(int32_t newOverlapLength);
virtual void clearCrossCorrState();
- void calculateOverlapLength(uint32_t overlapMs);
-
- virtual LONG_SAMPLETYPE calcCrossCorrStereo(const SAMPLETYPE *mixingPos, const SAMPLETYPE *compare) const;
- virtual LONG_SAMPLETYPE calcCrossCorrMono(const SAMPLETYPE *mixingPos, const SAMPLETYPE *compare) const;
-
- virtual uint32_t seekBestOverlapPositionStereo(const SAMPLETYPE *refPos);
- virtual uint32_t seekBestOverlapPositionStereoQuick(const SAMPLETYPE *refPos);
- virtual uint32_t seekBestOverlapPositionMono(const SAMPLETYPE *refPos);
- virtual uint32_t seekBestOverlapPositionMonoQuick(const SAMPLETYPE *refPos);
- uint32_t seekBestOverlapPosition(const SAMPLETYPE *refPos);
+ void calculateOverlapLength(int32_t overlapMs);
+
+ virtual double calcCrossCorr(const SAMPLETYPE *mixingPos, const SAMPLETYPE *compare) const;
+
+ virtual int seekBestOverlapPositionFull(const SAMPLETYPE *refPos);
+ virtual int seekBestOverlapPositionQuick(const SAMPLETYPE *refPos);
+ int32_t seekBestOverlapPosition(const SAMPLETYPE *refPos);
virtual void overlapStereo(SAMPLETYPE *output, const SAMPLETYPE *input) const;
virtual void overlapMono(SAMPLETYPE *output, const SAMPLETYPE *input) const;
@@ -117,10 +149,7 @@
void clearMidBuffer();
void overlap(SAMPLETYPE *output, const SAMPLETYPE *input, uint32_t ovlPos) const;
- void precalcCorrReferenceMono();
- void precalcCorrReferenceStereo();
-
- void processNominalTempo();
+ void calcSeqParameters();
/// Changes the tempo of the given sound samples.
/// Returns amount of samples returned in the "output" buffer.
@@ -134,7 +163,7 @@
/// Operator 'new' is overloaded so that it automatically creates a suitable instance
/// depending on if we've a MMX/SSE/etc-capable CPU available or not.
- void *operator new(size_t s);
+ static void *operator new(size_t s);
/// Use this function instead of "new" operator to create a new instance of this class.
/// This function automatically chooses a correct feature set depending on if the CPU
@@ -142,10 +171,10 @@
static TDStretch *newInstance();
/// Returns the output buffer object
- FIFOSamplePipe *getOutput() { return &outputBuffer; };
+ FIFOSamplePipe *getOutput() { return &this->outputBuffer; }
/// Returns the input buffer object
- FIFOSamplePipe *getInput() { return &inputBuffer; };
+ FIFOSamplePipe *getInput() { return &this->inputBuffer; }
/// Sets new target tempo. Normal tempo = 'SCALE', smaller values represent slower
/// tempo, larger faster tempo.
@@ -158,7 +187,7 @@
void clearInput();
/// Sets the number of channels, 1 = mono, 2 = stereo
- void setChannels(uint32_t numChannels);
+ void setChannels(int32_t numChannels);
/// Enables/disables the quick position seeking algorithm. Zero to disable,
/// nonzero to enable
@@ -175,16 +204,16 @@
/// 'seekwindowMS' = seeking window length for scanning the best overlapping
/// position
/// 'overlapMS' = overlapping length
- void setParameters(uint32_t sampleRate, ///< Samplerate of sound being processed (Hz)
- uint32_t sequenceMS = DEFAULT_SEQUENCE_MS, ///< Single processing sequence length (ms)
- uint32_t seekwindowMS = DEFAULT_SEEKWINDOW_MS, ///< Offset seeking window length (ms)
- uint32_t overlapMS = DEFAULT_OVERLAP_MS ///< Sequence overlapping length (ms)
+ void setParameters(int32_t sampleRate, ///< Samplerate of sound being processed (Hz)
+ int32_t sequenceMS = -1, ///< Single processing sequence length (ms)
+ int32_t seekwindowMS = -1, ///< Offset seeking window length (ms)
+ int32_t overlapMS = -1 ///< Sequence overlapping length (ms)
);
/// Get routine control parameters, see setParameters() function.
/// Any of the parameters to this function can be NULL, in such case corresponding parameter
/// value isn't returned.
- void getParameters(uint32_t *pSampleRate, uint32_t *pSequenceMs, uint32_t *pSeekWindowMs, uint32_t *pOverlapMs);
+ void getParameters(int32_t *pSampleRate, int32_t *pSequenceMs, int32_t *pSeekWindowMs, int32_t *pOverlapMs);
/// Adds 'numsamples' pcs of samples from the 'samples' memory position into
/// the input of the object.
@@ -193,40 +222,41 @@
uint32_t numSamples ///< Number of samples in 'samples' so that one sample
///< contains both channels if stereo
);
+
+ /// return nominal input sample requirement for triggering a processing batch
+ int32_t getInputSampleReq() const
+ {
+ return static_cast<int32_t>(this->nominalSkip + 0.5);
+ }
+
+ /// return nominal output sample amount when running a processing batch
+ int32_t getOutputBatchSize() const
+ {
+ return this->seekWindowLength - this->overlapLength;
+ }
};
-
// Implementation-specific class declarations:
-//#ifdef ALLOW_MMX
-// /// Class that implements MMX optimized routines for 16bit integer samples type.
-// class TDStretchMMX : public TDStretch
-// {
-// protected:
-// long calcCrossCorrStereo(const short *mixingPos, const short *compare) const;
-// virtual void overlapStereo(short *output, const short *input) const;
-// virtual void clearCrossCorrState();
-// };
-//#endif /// ALLOW_MMX
-//
-//
-//#ifdef ALLOW_3DNOW
-// /// Class that implements 3DNow! optimized routines for floating point samples type.
-// class TDStretch3DNow : public TDStretch
-// {
-// protected:
-// double calcCrossCorrStereo(const float *mixingPos, const float *compare) const;
-// };
-//#endif /// ALLOW_3DNOW
-
-#ifdef __SSE__
+#ifdef SOUNDTOUCH_ALLOW_MMX
+/// Class that implements MMX optimized routines for 16bit integer samples type.
+class TDStretchMMX : public TDStretch
+{
+protected:
+ double calcCrossCorr(const short *mixingPos, const short *compare) const;
+ virtual void overlapStereo(short *output, const short *input) const;
+ virtual void clearCrossCorrState();
+};
+#endif /// SOUNDTOUCH_ALLOW_MMX
+
+#ifdef SOUNDTOUCH_ALLOW_SSE
/// Class that implements SSE optimized routines for floating point samples type.
class TDStretchSSE : public TDStretch
{
protected:
- double calcCrossCorrStereo(const float *mixingPos, const float *compare) const;
+ double calcCrossCorr(const float *mixingPos, const float *compare) const;
};
-#endif /// ALLOW_SSE
+#endif /// SOUNDTOUCH_ALLOW_SSE
}
--- a/src/in_2sf/desmume/metaspu/SoundTouch/cpu_detect.h
+++ b/src/in_2sf/desmume/metaspu/SoundTouch/cpu_detect.h
@@ -45,11 +45,9 @@
#include "STTypes.h"
-#define SUPPORT_MMX 0x0001
-#define SUPPORT_3DNOW 0x0002
-#define SUPPORT_ALTIVEC 0x0004
-#define SUPPORT_SSE 0x0008
-#define SUPPORT_SSE2 0x0010
+const uint32_t SUPPORT_MMX = 0x0001;
+const uint32_t SUPPORT_3DNOW = 0x0002;
+const uint32_t SUPPORT_SSE = 0x0004;
/// Checks which instruction set extensions are supported by the CPU.
///
--- a/src/in_2sf/desmume/metaspu/SoundTouch/cpu_detect_x86_win.cpp
+++ b/src/in_2sf/desmume/metaspu/SoundTouch/cpu_detect_x86_win.cpp
@@ -41,6 +41,9 @@
////////////////////////////////////////////////////////////////////////////////
#include "cpu_detect.h"
+#ifdef _MSC_VER
+#include <intrin.h>
+#endif
#ifndef _WIN32
#error wrong platform - this source code file is exclusively for Win32 platform
@@ -53,78 +56,37 @@
//////////////////////////////////////////////////////////////////////////////
// Flag variable indicating whick ISA extensions are disabled (for debugging)
-static uint32_t _dwDisabledISA = 0x00; // 0xffffffff; //<- use this to disable all extensions
-
+static uint32_t _dwDisabledISA = 0x00; // 0xffffffff; //<- use this to disable all extensions
// Disables given set of instruction extensions. See SUPPORT_... defines.
void disableExtensions(uint32_t dwDisableMask)
{
- _dwDisabledISA = dwDisableMask;
+ _dwDisabledISA = dwDisableMask;
}
/// Checks which instruction set extensions are supported by the CPU.
uint32_t detectCPUextensions()
{
- uint32_t res = 0;
+ uint32_t res = 0;
- if (_dwDisabledISA == 0xffffffff) return 0;
+ if (_dwDisabledISA == 0xffffffff)
+ return 0;
- //zeromus 28-oct-2009 - changed to compile on 64bits msvc
-#if (defined(_MSC_VER) && !defined(_M_X64)) || !defined(_MSC_VER)
+#ifdef _MSC_VER
+ int CPUInfo[4] = { -1 };
+ __cpuid(CPUInfo, 1);
+ res |= (CPUInfo[3] & (1 << 23)) ? SUPPORT_MMX : 0;
+ res |= (CPUInfo[3] & (1 << 25)) ? SUPPORT_SSE : 0;
- _asm
- {
- ; check if 'cpuid' instructions is available by toggling eflags bit 21
- ;
- xor esi, esi ; clear esi = result register
-
- pushfd ; save eflags to stack
- pop eax ; load eax from stack (with eflags)
- mov ecx, eax ; save the original eflags values to ecx
- xor eax, 0x00200000 ; toggle bit 21
- push eax ; store toggled eflags to stack
- popfd ; load eflags from stack
- pushfd ; save updated eflags to stack
- pop eax ; load from stack
- xor edx, edx ; clear edx for defaulting no mmx
- cmp eax, ecx ; compare to original eflags values
- jz end ; jumps to 'end' if cpuid not present
-
- ; cpuid instruction available, test for presence of mmx instructions
- mov eax, 1
- cpuid
- test edx, 0x00800000
- jz end ; branch if MMX not available
-
- or esi, SUPPORT_MMX ; otherwise add MMX support bit
-
- test edx, 0x02000000
- jz test3DNow ; branch if SSE not available
-
- or esi, SUPPORT_SSE ; otherwise add SSE support bit
-
- test3DNow:
- ; test for precense of AMD extensions
- mov eax, 0x80000000
- cpuid
- cmp eax, 0x80000000
- jbe end ; branch if no AMD extensions detected
-
- ; test for precense of 3DNow! extension
- mov eax, 0x80000001
- cpuid
- test edx, 0x80000000
- jz end ; branch if 3DNow! not detected
-
- or esi, SUPPORT_3DNOW ; otherwise add 3DNow support bit
-
- end:
-
- mov res, esi
- }
-
+ // Test 3Dnow
+ __cpuid(CPUInfo, 0x80000000);
+ if (CPUInfo[0] == 0x80000000)
+ {
+ __cpuid(CPUInfo, 0x80000001);
+ res |= (CPUInfo[3] & (1 << 31)) ? SUPPORT_3DNOW : 0;
+ }
#endif
- return res & ~_dwDisabledISA;
+ return res & ~_dwDisabledISA;
}
--- /dev/null
+++ b/src/in_2sf/desmume/metaspu/SoundTouch/mmx_optimized.cpp
@@ -1,1 +1,282 @@
-
+////////////////////////////////////////////////////////////////////////////////
+///
+/// MMX optimized routines. All MMX optimized functions have been gathered into
+/// this single source code file, regardless to their class or original source
+/// code file, in order to ease porting the library to other compiler and
+/// processor platforms.
+///
+/// The MMX-optimizations are programmed using MMX compiler intrinsics that
+/// are supported both by Microsoft Visual C++ and GCC compilers, so this file
+/// should compile with both toolsets.
+///
+/// NOTICE: If using Visual Studio 6.0, you'll need to install the "Visual C++
+/// 6.0 processor pack" update to support compiler intrinsic syntax. The update
+/// is available for download at Microsoft Developers Network, see here:
+/// http://msdn.microsoft.com/en-us/vstudio/aa718349.aspx
+///
+/// Author : Copyright (c) Olli Parviainen
+/// Author e-mail : oparviai 'at' iki.fi
+/// SoundTouch WWW: http://www.surina.net/soundtouch
+///
+////////////////////////////////////////////////////////////////////////////////
+//
+// Last changed : $Date: 2012-11-08 16:53:01 -0200 (qui, 08 nov 2012) $
+// File revision : $Revision: 4 $
+//
+// $Id: mmx_optimized.cpp 160 2012-11-08 18:53:01Z oparviai $
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// License :
+//
+// SoundTouch audio processing library
+// Copyright (c) Olli Parviainen
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public
+// License as published by the Free Software Foundation; either
+// version 2.1 of the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+////////////////////////////////////////////////////////////////////////////////
+
+#include "STTypes.h"
+
+#ifdef SOUNDTOUCH_ALLOW_MMX
+// MMX routines available only with integer sample type
+
+using namespace soundtouch;
+
+//////////////////////////////////////////////////////////////////////////////
+//
+// implementation of MMX optimized functions of class 'TDStretchMMX'
+//
+//////////////////////////////////////////////////////////////////////////////
+
+#include "TDStretch.h"
+#include <mmintrin.h>
+
+// Calculates cross correlation of two buffers
+double TDStretchMMX::calcCrossCorr(const short *pV1, const short *pV2) const
+{
+ const __m64 *pVec1 = reinterpret_cast<__m64 *>(pV1);
+ const __m64 *pVec2 = reinterpret_cast<__m64 *>(pV2);
+
+ __m64 shifter = _m_from_int(this->overlapDividerBits);
+ __m64 normaccu, accu;
+ normaccu = accu = _mm_setzero_si64();
+
+ // Process 4 parallel sets of 2 * stereo samples or 4 * mono samples
+ // during each round for improved CPU-level parallellization.
+ for (int32_t i = 0; i < this->channels * this->overlapLength / 16; ++i)
+ {
+ // dictionary of instructions:
+ // _m_pmaddwd : 4*16bit multiply-add, resulting two 32bits = [a0*b0+a1*b1 ; a2*b2+a3*b3]
+ // _mm_add_pi32 : 2*32bit add
+ // _m_psrad : 32bit right-shift
+
+ __m64 temp = _mm_add_pi32(_mm_madd_pi16(pVec1[0], pVec2[0]), _mm_madd_pi16(pVec1[1], pVec2[1]));
+ __m64 temp2 = _mm_add_pi32(_mm_madd_pi16(pVec1[0], pVec1[0]), _mm_madd_pi16(pVec1[1], pVec1[1]));
+ accu = _mm_add_pi32(accu, _mm_sra_pi32(temp, shifter));
+ normaccu = _mm_add_pi32(normaccu, _mm_sra_pi32(temp2, shifter));
+
+ temp = _mm_add_pi32(_mm_madd_pi16(pVec1[2], pVec2[2]), _mm_madd_pi16(pVec1[3], pVec2[3]));
+ temp2 = _mm_add_pi32(_mm_madd_pi16(pVec1[2], pVec1[2]), _mm_madd_pi16(pVec1[3], pVec1[3]));
+ accu = _mm_add_pi32(accu, _mm_sra_pi32(temp, shifter));
+ normaccu = _mm_add_pi32(normaccu, _mm_sra_pi32(temp2, shifter));
+
+ pVec1 += 4;
+ pVec2 += 4;
+ }
+
+ // copy hi-dword of mm0 to lo-dword of mm1, then sum mmo+mm1
+ // and finally store the result into the variable "corr"
+
+ accu = _mm_add_pi32(accu, _mm_srli_si64(accu, 32));
+ long corr = _m_to_int(accu);
+
+ normaccu = _mm_add_pi32(normaccu, _mm_srli_si64(normaccu, 32));
+ long norm = _m_to_int(normaccu);
+
+ // Clear MMS state
+ _m_empty();
+
+ // Normalize result by dividing by sqrt(norm) - this step is easiest
+ // done using floating point operation
+ if (!norm)
+ norm = 1; // to avoid div by zero
+
+ return corr / std::sqrt(static_cast<double>(norm));
+ // Note: Warning about the missing EMMS instruction is harmless
+ // as it'll be called elsewhere.
+}
+
+void TDStretchMMX::clearCrossCorrState()
+{
+ // Clear MMS state
+ _m_empty();
+ //_asm EMMS;
+}
+
+// MMX-optimized version of the function overlapStereo
+void TDStretchMMX::overlapStereo(short *output, const short *input) const
+{
+ const __m64 *pVinput = reinterpret_cast<const __m64 *>(input);
+ const __m64 *pVMidBuf = reinterpret_cast<const __m64 *>(this->pMidBuffer);
+ __m64 *pVdest = reinterpret_cast<__m64 *>(output);
+
+ // mix1 = mixer values for 1st stereo sample
+ // mix1 = mixer values for 2nd stereo sample
+ // adder = adder for updating mixer values after each round
+
+ __m64 mix1 = _mm_set_pi16(0, this->overlapLength, 0, this->overlapLength);
+ __m64 adder = _mm_set_pi16(1, -1, 1, -1);
+ __m64 mix2 = _mm_add_pi16(mix1, adder);
+ adder = _mm_add_pi16(adder, adder);
+
+ // Overlaplength-division by shifter. "+1" is to account for "-1" deduced in
+ // overlapDividerBits calculation earlier.
+ __m64 shifter = _m_from_int(overlapDividerBits + 1);
+
+ for (int32_t i = 0; i < this->overlapLength / 4; ++i)
+ {
+ // load & shuffle data so that input & mixbuffer data samples are paired
+ __m64 temp1 = _mm_unpacklo_pi16(pVMidBuf[0], pVinput[0]); // = i0l m0l i0r m0r
+ __m64 temp2 = _mm_unpackhi_pi16(pVMidBuf[0], pVinput[0]); // = i1l m1l i1r m1r
+
+ // temp = (temp .* mix) >> shifter
+ temp1 = _mm_sra_pi32(_mm_madd_pi16(temp1, mix1), shifter);
+ temp2 = _mm_sra_pi32(_mm_madd_pi16(temp2, mix2), shifter);
+ pVdest[0] = _mm_packs_pi32(temp1, temp2); // pack 2*2*32bit => 4*16bit
+
+ // update mix += adder
+ mix1 = _mm_add_pi16(mix1, adder);
+ mix2 = _mm_add_pi16(mix2, adder);
+
+ // --- second round begins here ---
+
+ // load & shuffle data so that input & mixbuffer data samples are paired
+ temp1 = _mm_unpacklo_pi16(pVMidBuf[1], pVinput[1]); // = i2l m2l i2r m2r
+ temp2 = _mm_unpackhi_pi16(pVMidBuf[1], pVinput[1]); // = i3l m3l i3r m3r
+
+ // temp = (temp .* mix) >> shifter
+ temp1 = _mm_sra_pi32(_mm_madd_pi16(temp1, mix1), shifter);
+ temp2 = _mm_sra_pi32(_mm_madd_pi16(temp2, mix2), shifter);
+ pVdest[1] = _mm_packs_pi32(temp1, temp2); // pack 2*2*32bit => 4*16bit
+
+ // update mix += adder
+ mix1 = _mm_add_pi16(mix1, adder);
+ mix2 = _mm_add_pi16(mix2, adder);
+
+ pVinput += 2;
+ pVMidBuf += 2;
+ pVdest += 2;
+ }
+
+ _m_empty(); // clear MMS state
+}
+
+//////////////////////////////////////////////////////////////////////////////
+//
+// implementation of MMX optimized functions of class 'FIRFilter'
+//
+//////////////////////////////////////////////////////////////////////////////
+
+#include "FIRFilter.h"
+
+FIRFilterMMX::FIRFilterMMX() : FIRFilter()
+{
+ this->filterCoeffsUnalign.reset();
+}
+
+FIRFilterMMX::~FIRFilterMMX()
+{
+}
+
+// (overloaded) Calculates filter coefficients for MMX routine
+void FIRFilterMMX::setCoefficients(const short *coeffs, uint32_t newLength, uint32_t uResultDivFactor)
+{
+ FIRFilter::setCoefficients(coeffs, newLength, uResultDivFactor);
+
+ // Ensure that filter coeffs array is aligned to 16-byte boundary
+ this->filterCoeffsUnalign.reset(new short[2 * newLength + 8]);
+ this->filterCoeffsAlign = reinterpret_csat<short *>(SOUNDTOUCH_ALIGN_POINTER_16(this->filterCoeffsUnalign.get()));
+
+ // rearrange the filter coefficients for mmx routines
+ for (uint32_t i = 0; i < length; i += 4)
+ {
+ this->filterCoeffsAlign[2 * i ] = coeffs[i];
+ this->filterCoeffsAlign[2 * i + 1] = coeffs[i + 2];
+ this->filterCoeffsAlign[2 * i + 2] = coeffs[i];
+ this->filterCoeffsAlign[2 * i + 3] = coeffs[i + 2];
+
+ this->filterCoeffsAlign[2 * i + 4] = coeffs[i + 1];
+ this->filterCoeffsAlign[2 * i + 5] = coeffs[i + 3];
+ this->filterCoeffsAlign[2 * i + 6] = coeffs[i + 1];
+ this->filterCoeffsAlign[2 * i + 7] = coeffs[i + 3];
+ }
+}
+
+// mmx-optimized version of the filter routine for stereo sound
+uint32_t FIRFilterMMX::evaluateFilterStereo(short *dest, const short *src, uint32_t numSamples) const
+{
+ if (this->length < 2)
+ return 0;
+
+ // Create stack copies of the needed member variables for asm routines :
+ __m64 *pVdest = reinterpret_cast<__m64 *>(dest);
+
+ for (uint32_t i = 0; i < (numSamples - this->length) / 2; ++i)
+ {
+ const __m64 *pVsrc = reinterpret_cast<const __m64 *>(src);
+ const __m64 *pVfilter = reinterpret_cast<const __m64 *>(this->filterCoeffsAlign);
+
+ __m64 accu1, accu2;
+ accu1 = accu2 = _mm_setzero_si64();
+ for (uint32_t j = 0; j < this->lengthDiv8 * 2; ++j)
+ {
+ __m64 temp1 = _mm_unpacklo_pi16(pVsrc[0], pVsrc[1]); // = l2 l0 r2 r0
+ __m64 temp2 = _mm_unpackhi_pi16(pVsrc[0], pVsrc[1]); // = l3 l1 r3 r1
+
+ accu1 = _mm_add_pi32(accu1, _mm_madd_pi16(temp1, pVfilter[0])); // += l2*f2+l0*f0 r2*f2+r0*f0
+ accu1 = _mm_add_pi32(accu1, _mm_madd_pi16(temp2, pVfilter[1])); // += l3*f3+l1*f1 r3*f3+r1*f1
+
+ temp1 = _mm_unpacklo_pi16(pVsrc[1], pVsrc[2]); // = l4 l2 r4 r2
+
+ accu2 = _mm_add_pi32(accu2, _mm_madd_pi16(temp2, pVfilter[0])); // += l3*f2+l1*f0 r3*f2+r1*f0
+ accu2 = _mm_add_pi32(accu2, _mm_madd_pi16(temp1, pVfilter[1])); // += l4*f3+l2*f1 r4*f3+r2*f1
+
+ // accu1 += l2*f2+l0*f0 r2*f2+r0*f0
+ // += l3*f3+l1*f1 r3*f3+r1*f1
+
+ // accu2 += l3*f2+l1*f0 r3*f2+r1*f0
+ // l4*f3+l2*f1 r4*f3+r2*f1
+
+ pVfilter += 2;
+ pVsrc += 2;
+ }
+ // accu >>= resultDivFactor
+ accu1 = _mm_srai_pi32(accu1, resultDivFactor);
+ accu2 = _mm_srai_pi32(accu2, resultDivFactor);
+
+ // pack 2*2*32bits => 4*16 bits
+ pVdest[0] = _mm_packs_pi32(accu1, accu2);
+ src += 4;
+ ++pVdest;
+ }
+
+ _m_empty(); // clear emms state
+
+ return (numSamples & 0xfffffffe) - this->length;
+}
+
+#endif // SOUNDTOUCH_ALLOW_MMX
+
--- a/src/in_2sf/desmume/metaspu/SoundTouch/sse_optimized.cpp
+++ b/src/in_2sf/desmume/metaspu/SoundTouch/sse_optimized.cpp
@@ -12,7 +12,7 @@
/// NOTICE: If using Visual Studio 6.0, you'll need to install the "Visual C++
/// 6.0 processor pack" update to support SSE instruction set. The update is
/// available for download at Microsoft Developers Network, see here:
-/// http://msdn.microsoft.com/vstudio/downloads/tools/ppack/default.aspx
+/// http://msdn.microsoft.com/en-us/vstudio/aa718349.aspx
///
/// If the above URL is expired or removed, go to "http://msdn.microsoft.com" and
/// perform a search with keywords "processor pack".
@@ -23,10 +23,10 @@
///
////////////////////////////////////////////////////////////////////////////////
//
-// Last changed : $Date: 2006/02/05 16:44:06 $
-// File revision : $Revision: 1.2 $
-//
-// $Id: sse_optimized.cpp,v 1.2 2006/02/05 16:44:06 Olli Exp $
+// Last changed : $Date: 2012-11-08 16:53:01 -0200 (qui, 08 nov 2012) $
+// File revision : $Revision: 4 $
+//
+// $Id: sse_optimized.cpp 160 2012-11-08 18:53:01Z oparviai $
//
////////////////////////////////////////////////////////////////////////////////
//
@@ -56,7 +56,7 @@
using namespace soundtouch;
-#ifdef __SSE__
+#ifdef SOUNDTOUCH_ALLOW_SSE
// SSE routines available only with float sample type
@@ -70,164 +70,110 @@
#include <xmmintrin.h>
// Calculates cross correlation of two buffers
-double TDStretchSSE::calcCrossCorrStereo(const float *pV1, const float *pV2) const
-{
- uint32_t i;
- __m128 vSum, *pVec2;
-
- // Note. It means a major slow-down if the routine needs to tolerate
- // unaligned __m128 memory accesses. It's way faster if we can skip
- // unaligned slots and use _mm_load_ps instruction instead of _mm_loadu_ps.
- // This can mean up to ~ 10-fold difference (incl. part of which is
- // due to skipping every second round for stereo sound though).
- //
- // Compile-time define ALLOW_NONEXACT_SIMD_OPTIMIZATION is provided
- // for choosing if this little cheating is allowed.
-
-#ifdef ALLOW_NONEXACT_SIMD_OPTIMIZATION
- // Little cheating allowed, return valid correlation only for
- // aligned locations, meaning every second round for stereo sound.
-
- #define _MM_LOAD _mm_load_ps
-
- if (((uint64_t)pV1) & 15) return -1e50; // skip unaligned locations
-
+double TDStretchSSE::calcCrossCorr(const float *pV1, const float *pV2) const
+{
+ // Note. It means a major slow-down if the routine needs to tolerate
+ // unaligned __m128 memory accesses. It's way faster if we can skip
+ // unaligned slots and use _mm_load_ps instruction instead of _mm_loadu_ps.
+ // This can mean up to ~ 10-fold difference (incl. part of which is
+ // due to skipping every second round for stereo sound though).
+ //
+ // Compile-time define SOUNDTOUCH_ALLOW_NONEXACT_SIMD_OPTIMIZATION is provided
+ // for choosing if this little cheating is allowed.
+
+#ifdef SOUNDTOUCH_ALLOW_NONEXACT_SIMD_OPTIMIZATION
+ // Little cheating allowed, return valid correlation only for
+ // aligned locations, meaning every second round for stereo sound.
+
+ #define _MM_LOAD _mm_load_ps
+
+ if (reinterpret_cast<uintptr_t>(pV1) & 15)
+ return -1e50; // skip unaligned locations
#else
- // No cheating allowed, use unaligned load & take the resulting
- // performance hit.
- #define _MM_LOAD _mm_loadu_ps
+ // No cheating allowed, use unaligned load & take the resulting
+ // performance hit.
+ #define _MM_LOAD _mm_loadu_ps
#endif
- // ensure overlapLength is divisible by 8
- assert((overlapLength % 8) == 0);
-
- // Calculates the cross-correlation value between 'pV1' and 'pV2' vectors
- // Note: pV2 _must_ be aligned to 16-bit boundary, pV1 need not.
- pVec2 = (__m128*)pV2;
- vSum = _mm_setzero_ps();
-
- // Unroll the loop by factor of 4 * 4 operations
- for (i = 0; i < overlapLength / 8; i ++)
- {
- // vSum += pV1[0..3] * pV2[0..3]
- vSum = _mm_add_ps(vSum, _mm_mul_ps(_MM_LOAD(pV1),pVec2[0]));
-
- // vSum += pV1[4..7] * pV2[4..7]
- vSum = _mm_add_ps(vSum, _mm_mul_ps(_MM_LOAD(pV1 + 4), pVec2[1]));
-
- // vSum += pV1[8..11] * pV2[8..11]
- vSum = _mm_add_ps(vSum, _mm_mul_ps(_MM_LOAD(pV1 + 8), pVec2[2]));
-
- // vSum += pV1[12..15] * pV2[12..15]
- vSum = _mm_add_ps(vSum, _mm_mul_ps(_MM_LOAD(pV1 + 12), pVec2[3]));
-
- pV1 += 16;
- pVec2 += 4;
- }
-
- // return value = vSum[0] + vSum[1] + vSum[2] + vSum[3]
- float *pvSum = (float*)&vSum;
- return (double)(pvSum[0] + pvSum[1] + pvSum[2] + pvSum[3]);
-
- /* This is approximately corresponding routine in C-language:
- double corr;
- uint32_t i;
-
- // Calculates the cross-correlation value between 'pV1' and 'pV2' vectors
- corr = 0.0;
- for (i = 0; i < overlapLength / 8; i ++)
- {
- corr += pV1[0] * pV2[0] +
- pV1[1] * pV2[1] +
- pV1[2] * pV2[2] +
- pV1[3] * pV2[3] +
- pV1[4] * pV2[4] +
- pV1[5] * pV2[5] +
- pV1[6] * pV2[6] +
- pV1[7] * pV2[7] +
- pV1[8] * pV2[8] +
- pV1[9] * pV2[9] +
- pV1[10] * pV2[10] +
- pV1[11] * pV2[11] +
- pV1[12] * pV2[12] +
- pV1[13] * pV2[13] +
- pV1[14] * pV2[14] +
- pV1[15] * pV2[15];
-
- pV1 += 16;
- pV2 += 16;
- }
- */
-
- /* This is corresponding routine in assembler. This may be teeny-weeny bit faster
- than intrinsic version, but more difficult to maintain & get compiled on multiple
- platforms.
-
- uint32_t overlapLengthLocal = overlapLength;
- float corr;
-
- _asm
- {
- // Very important note: data in 'pV2' _must_ be aligned to
- // 16-byte boundary!
-
- // give prefetch hints to CPU of what data are to be needed soonish
- // give more aggressive hints on pV1 as that changes while pV2 stays
- // same between runs
- prefetcht0 [pV1]
- prefetcht0 [pV2]
- prefetcht0 [pV1 + 32]
-
- mov eax, dword ptr pV1
- mov ebx, dword ptr pV2
-
- xorps xmm0, xmm0
-
- mov ecx, overlapLengthLocal
- shr ecx, 3 // div by eight
-
- loop1:
- prefetcht0 [eax + 64] // give a prefetch hint to CPU what data are to be needed soonish
- prefetcht0 [ebx + 32] // give a prefetch hint to CPU what data are to be needed soonish
- movups xmm1, [eax]
- mulps xmm1, [ebx]
- addps xmm0, xmm1
-
- movups xmm2, [eax + 16]
- mulps xmm2, [ebx + 16]
- addps xmm0, xmm2
-
- prefetcht0 [eax + 96] // give a prefetch hint to CPU what data are to be needed soonish
- prefetcht0 [ebx + 64] // give a prefetch hint to CPU what data are to be needed soonish
-
- movups xmm3, [eax + 32]
- mulps xmm3, [ebx + 32]
- addps xmm0, xmm3
-
- movups xmm4, [eax + 48]
- mulps xmm4, [ebx + 48]
- addps xmm0, xmm4
-
- add eax, 64
- add ebx, 64
-
- dec ecx
- jnz loop1
-
- // add the four floats of xmm0 together and return the result.
-
- movhlps xmm1, xmm0 // move 3 & 4 of xmm0 to 1 & 2 of xmm1
- addps xmm1, xmm0
- movaps xmm2, xmm1
- shufps xmm2, xmm2, 0x01 // move 2 of xmm2 as 1 of xmm2
- addss xmm2, xmm1
- movss corr, xmm2
- }
-
- return (double)corr;
- */
-}
-
+ // ensure overlapLength is divisible by 8
+ assert(!(overlapLength % 8));
+
+ // Calculates the cross-correlation value between 'pV1' and 'pV2' vectors
+ // Note: pV2 _must_ be aligned to 16-bit boundary, pV1 need not.
+ const float *pVec1 = pV1;
+ const __m128 *pVec2 = reinterpret_cast<const __m128 *>(pV2);
+ __m128 vSum, vNorm;
+ vSum = vNorm = _mm_setzero_ps();
+
+ // Unroll the loop by factor of 4 * 4 operations. Use same routine for
+ // stereo & mono, for mono it just means twice the amount of unrolling.
+ for (int32_t i = 0; i < this->channels * this->overlapLength / 16; ++i)
+ {
+ // vSum += pV1[0..3] * pV2[0..3]
+ __m128 vTemp = _MM_LOAD(pVec1);
+ vSum = _mm_add_ps(vSum, _mm_mul_ps(vTemp, pVec2[0]));
+ vNorm = _mm_add_ps(vNorm, _mm_mul_ps(vTemp, vTemp));
+
+ // vSum += pV1[4..7] * pV2[4..7]
+ vTemp = _MM_LOAD(pVec1 + 4);
+ vSum = _mm_add_ps(vSum, _mm_mul_ps(vTemp, pVec2[1]));
+ vNorm = _mm_add_ps(vNorm, _mm_mul_ps(vTemp, vTemp));
+
+ // vSum += pV1[8..11] * pV2[8..11]
+ vTemp = _MM_LOAD(pVec1 + 8);
+ vSum = _mm_add_ps(vSum, _mm_mul_ps(vTemp, pVec2[2]));
+ vNorm = _mm_add_ps(vNorm, _mm_mul_ps(vTemp, vTemp));
+
+ // vSum += pV1[12..15] * pV2[12..15]
+ vTemp = _MM_LOAD(pVec1 + 12);
+ vSum = _mm_add_ps(vSum, _mm_mul_ps(vTemp, pVec2[3]));
+ vNorm = _mm_add_ps(vNorm, _mm_mul_ps(vTemp, vTemp));
+
+ pVec1 += 16;
+ pVec2 += 4;
+ }
+
+ // return value = vSum[0] + vSum[1] + vSum[2] + vSum[3]
+ float *pvNorm = reinterpret_cast<float *>(&vNorm);
+ double norm = std::sqrt(pvNorm[0] + pvNorm[1] + pvNorm[2] + pvNorm[3]);
+ if (norm < 1e-9)
+ norm = 1.0; // to avoid div by zero
+
+ float *pvSum = reinterpret_cast<float *>(&vSum);
+ return static_cast<double>(pvSum[0] + pvSum[1] + pvSum[2] + pvSum[3]) / norm;
+
+ /* This is approximately corresponding routine in C-language:
+ double corr, norm;
+ uint32_t i;
+
+ // Calculates the cross-correlation value between 'pV1' and 'pV2' vectors
+ corr = norm = 0.0;
+ for (i = 0; i < channels * overlapLength / 16; i ++)
+ {
+ corr += pV1[0] * pV2[0] +
+ pV1[1] * pV2[1] +
+ pV1[2] * pV2[2] +
+ pV1[3] * pV2[3] +
+ pV1[4] * pV2[4] +
+ pV1[5] * pV2[5] +
+ pV1[6] * pV2[6] +
+ pV1[7] * pV2[7] +
+ pV1[8] * pV2[8] +
+ pV1[9] * pV2[9] +
+ pV1[10] * pV2[10] +
+ pV1[11] * pV2[11] +
+ pV1[12] * pV2[12] +
+ pV1[13] * pV2[13] +
+ pV1[14] * pV2[14] +
+ pV1[15] * pV2[15];
+
+ for (j = 0; j < 15; j ++) norm += pV1[j] * pV1[j];
+
+ pV1 += 16;
+ pV2 += 16;
+ }
+ return corr / sqrt(norm);*/
+}
//////////////////////////////////////////////////////////////////////////////
//
@@ -239,247 +185,151 @@
FIRFilterSSE::FIRFilterSSE() : FIRFilter()
{
- filterCoeffsUnalign = NULL;
-}
-
+ this->filterCoeffsAlign = nullptr;
+ this->filterCoeffsUnalign.reset();
+}
FIRFilterSSE::~FIRFilterSSE()
{
- delete[] filterCoeffsUnalign;
-}
-
+}
// (overloaded) Calculates filter coefficients for SSE routine
void FIRFilterSSE::setCoefficients(const float *coeffs, uint32_t newLength, uint32_t uResultDivFactor)
{
- uint32_t i;
- float fDivider;
-
- FIRFilter::setCoefficients(coeffs, newLength, uResultDivFactor);
-
- // Scale the filter coefficients so that it won't be necessary to scale the filtering result
- // also rearrange coefficients suitably for 3DNow!
- // Ensure that filter coeffs array is aligned to 16-byte boundary
- delete[] filterCoeffsUnalign;
- filterCoeffsUnalign = new float[2 * newLength + 4];
- filterCoeffsAlign = (float *)(((unsigned long)filterCoeffsUnalign + 15) & -16);
-
- fDivider = (float)resultDivider;
-
- // rearrange the filter coefficients for mmx routines
- for (i = 0; i < newLength; i ++)
- {
- filterCoeffsAlign[2 * i + 0] =
- filterCoeffsAlign[2 * i + 1] = coeffs[i + 0] / fDivider;
- }
-}
-
-
+ FIRFilter::setCoefficients(coeffs, newLength, uResultDivFactor);
+
+ // Scale the filter coefficients so that it won't be necessary to scale the filtering result
+ // also rearrange coefficients suitably for SSE
+ // Ensure that filter coeffs array is aligned to 16-byte boundary
+ this->filterCoeffsUnalign.reset(new float[2 * newLength + 4]);
+ this->filterCoeffsAlign = reinterpret_cast<float *>(SOUNDTOUCH_ALIGN_POINTER_16(this->filterCoeffsUnalign.get()));
+
+ float fDivider = static_cast<float>(this->resultDivider);
+
+ // rearrange the filter coefficients for mmx routines
+ for (uint32_t i = 0; i < newLength; ++i)
+ this->filterCoeffsAlign[2 * i] = this->filterCoeffsAlign[2 * i + 1] = coeffs[i] / fDivider;
+}
// SSE-optimized version of the filter routine for stereo sound
uint32_t FIRFilterSSE::evaluateFilterStereo(float *dest, const float *source, uint32_t numSamples) const
{
- int count = (numSamples - length) & -2;
- int j;
-
- assert(count % 2 == 0);
-
- if (count < 2) return 0;
-
- assert((length % 8) == 0);
- assert(((unsigned long)filterCoeffsAlign) % 16 == 0);
-
- // filter is evaluated for two stereo samples with each iteration, thus use of 'j += 2'
- for (j = 0; j < count; j += 2)
- {
- const float *pSrc;
- const __m128 *pFil;
- __m128 sum1, sum2;
- uint32_t i;
-
- pSrc = source; // source audio data
- pFil = (__m128*)filterCoeffsAlign; // filter coefficients. NOTE: Assumes coefficients
- // are aligned to 16-byte boundary
- sum1 = sum2 = _mm_setzero_ps();
-
- for (i = 0; i < length / 8; i ++)
- {
- // Unroll loop for efficiency & calculate filter for 2*2 stereo samples
- // at each pass
-
- // sum1 is accu for 2*2 filtered stereo sound data at the primary sound data offset
- // sum2 is accu for 2*2 filtered stereo sound data for the next sound sample offset.
-
- sum1 = _mm_add_ps(sum1, _mm_mul_ps(_mm_loadu_ps(pSrc) , pFil[0]));
- sum2 = _mm_add_ps(sum2, _mm_mul_ps(_mm_loadu_ps(pSrc + 2), pFil[0]));
-
- sum1 = _mm_add_ps(sum1, _mm_mul_ps(_mm_loadu_ps(pSrc + 4), pFil[1]));
- sum2 = _mm_add_ps(sum2, _mm_mul_ps(_mm_loadu_ps(pSrc + 6), pFil[1]));
-
- sum1 = _mm_add_ps(sum1, _mm_mul_ps(_mm_loadu_ps(pSrc + 8) , pFil[2]));
- sum2 = _mm_add_ps(sum2, _mm_mul_ps(_mm_loadu_ps(pSrc + 10), pFil[2]));
-
- sum1 = _mm_add_ps(sum1, _mm_mul_ps(_mm_loadu_ps(pSrc + 12), pFil[3]));
- sum2 = _mm_add_ps(sum2, _mm_mul_ps(_mm_loadu_ps(pSrc + 14), pFil[3]));
-
- pSrc += 16;
- pFil += 4;
- }
-
- // Now sum1 and sum2 both have a filtered 2-channel sample each, but we still need
- // to sum the two hi- and lo-floats of these registers together.
-
- // post-shuffle & add the filtered values and store to dest.
- _mm_storeu_ps(dest, _mm_add_ps(
- _mm_shuffle_ps(sum1, sum2, _MM_SHUFFLE(1,0,3,2)), // s2_1 s2_0 s1_3 s1_2
- _mm_shuffle_ps(sum1, sum2, _MM_SHUFFLE(3,2,1,0)) // s2_3 s2_2 s1_1 s1_0
- ));
- source += 4;
- dest += 4;
- }
-
- // Ideas for further improvement:
- // 1. If it could be guaranteed that 'source' were always aligned to 16-byte
- // boundary, a faster aligned '_mm_load_ps' instruction could be used.
- // 2. If it could be guaranteed that 'dest' were always aligned to 16-byte
- // boundary, a faster '_mm_store_ps' instruction could be used.
-
- return (uint32_t)count;
-
- /* original routine in C-language. please notice the C-version has differently
- organized coefficients though.
- double suml1, suml2;
- double sumr1, sumr2;
- uint32_t i, j;
-
- for (j = 0; j < count; j += 2)
- {
- const float *ptr;
- const float *pFil;
-
- suml1 = sumr1 = 0.0;
- suml2 = sumr2 = 0.0;
- ptr = src;
- pFil = filterCoeffs;
- for (i = 0; i < lengthLocal; i ++)
- {
- // unroll loop for efficiency.
-
- suml1 += ptr[0] * pFil[0] +
- ptr[2] * pFil[2] +
- ptr[4] * pFil[4] +
- ptr[6] * pFil[6];
-
- sumr1 += ptr[1] * pFil[1] +
- ptr[3] * pFil[3] +
- ptr[5] * pFil[5] +
- ptr[7] * pFil[7];
-
- suml2 += ptr[8] * pFil[0] +
- ptr[10] * pFil[2] +
- ptr[12] * pFil[4] +
- ptr[14] * pFil[6];
-
- sumr2 += ptr[9] * pFil[1] +
- ptr[11] * pFil[3] +
- ptr[13] * pFil[5] +
- ptr[15] * pFil[7];
-
- ptr += 16;
- pFil += 8;
- }
- dest[0] = (float)suml1;
- dest[1] = (float)sumr1;
- dest[2] = (float)suml2;
- dest[3] = (float)sumr2;
-
- src += 4;
- dest += 4;
- }
- */
-
-
- /* Similar routine in assembly, again obsoleted due to maintainability
- _asm
- {
- // Very important note: data in 'src' _must_ be aligned to
- // 16-byte boundary!
- mov edx, count
- mov ebx, dword ptr src
- mov eax, dword ptr dest
- shr edx, 1
-
- loop1:
- // "outer loop" : during each round 2*2 output samples are calculated
-
- // give prefetch hints to CPU of what data are to be needed soonish
- prefetcht0 [ebx]
- prefetcht0 [filterCoeffsLocal]
-
- mov esi, ebx
- mov edi, filterCoeffsLocal
- xorps xmm0, xmm0
- xorps xmm1, xmm1
- mov ecx, lengthLocal
-
- loop2:
- // "inner loop" : during each round eight FIR filter taps are evaluated for 2*2 samples
- prefetcht0 [esi + 32] // give a prefetch hint to CPU what data are to be needed soonish
- prefetcht0 [edi + 32] // give a prefetch hint to CPU what data are to be needed soonish
-
- movups xmm2, [esi] // possibly unaligned load
- movups xmm3, [esi + 8] // possibly unaligned load
- mulps xmm2, [edi]
- mulps xmm3, [edi]
- addps xmm0, xmm2
- addps xmm1, xmm3
-
- movups xmm4, [esi + 16] // possibly unaligned load
- movups xmm5, [esi + 24] // possibly unaligned load
- mulps xmm4, [edi + 16]
- mulps xmm5, [edi + 16]
- addps xmm0, xmm4
- addps xmm1, xmm5
-
- prefetcht0 [esi + 64] // give a prefetch hint to CPU what data are to be needed soonish
- prefetcht0 [edi + 64] // give a prefetch hint to CPU what data are to be needed soonish
-
- movups xmm6, [esi + 32] // possibly unaligned load
- movups xmm7, [esi + 40] // possibly unaligned load
- mulps xmm6, [edi + 32]
- mulps xmm7, [edi + 32]
- addps xmm0, xmm6
- addps xmm1, xmm7
-
- movups xmm4, [esi + 48] // possibly unaligned load
- movups xmm5, [esi + 56] // possibly unaligned load
- mulps xmm4, [edi + 48]
- mulps xmm5, [edi + 48]
- addps xmm0, xmm4
- addps xmm1, xmm5
-
- add esi, 64
- add edi, 64
- dec ecx
- jnz loop2
-
- // Now xmm0 and xmm1 both have a filtered 2-channel sample each, but we still need
- // to sum the two hi- and lo-floats of these registers together.
-
- movhlps xmm2, xmm0 // xmm2 = xmm2_3 xmm2_2 xmm0_3 xmm0_2
- movlhps xmm2, xmm1 // xmm2 = xmm1_1 xmm1_0 xmm0_3 xmm0_2
- shufps xmm0, xmm1, 0xe4 // xmm0 = xmm1_3 xmm1_2 xmm0_1 xmm0_0
- addps xmm0, xmm2
-
- movaps [eax], xmm0
- add ebx, 16
- add eax, 16
-
- dec edx
- jnz loop1
- }
- */
-}
-
-#endif // ALLOW_SSE
-
+ int count = static_cast<int>((numSamples - length) & static_cast<uint32_t>(-2));
+
+ assert(!(count % 2));
+
+ if (count < 2)
+ return 0;
+
+ assert(!!source);
+ assert(!!dest);
+ assert(!(length % 8));
+ assert(!!filterCoeffsAlign);
+ assert(!(reinterpret_cast<uintptr_t>(filterCoeffsAlign) % 16));
+
+ // filter is evaluated for two stereo samples with each iteration, thus use of 'j += 2'
+ for (int j = 0; j < count; j += 2)
+ {
+ const float *pSrc = source; // source audio data
+ const __m128 *pFil = reinterpret_cast<const __m128 *>(this->filterCoeffsAlign); // filter coefficients. NOTE: Assumes coefficients are aligned to 16-byte boundary
+ __m128 sum1, sum2;
+ sum1 = sum2 = _mm_setzero_ps();
+
+ for (uint32_t i = 0; i < length / 8; ++i)
+ {
+ // Unroll loop for efficiency & calculate filter for 2*2 stereo samples
+ // at each pass
+
+ // sum1 is accu for 2*2 filtered stereo sound data at the primary sound data offset
+ // sum2 is accu for 2*2 filtered stereo sound data for the next sound sample offset.
+
+ sum1 = _mm_add_ps(sum1, _mm_mul_ps(_mm_loadu_ps(pSrc), pFil[0]));
+ sum2 = _mm_add_ps(sum2, _mm_mul_ps(_mm_loadu_ps(pSrc + 2), pFil[0]));
+
+ sum1 = _mm_add_ps(sum1, _mm_mul_ps(_mm_loadu_ps(pSrc + 4), pFil[1]));
+ sum2 = _mm_add_ps(sum2, _mm_mul_ps(_mm_loadu_ps(pSrc + 6), pFil[1]));
+
+ sum1 = _mm_add_ps(sum1, _mm_mul_ps(_mm_loadu_ps(pSrc + 8) , pFil[2]));
+ sum2 = _mm_add_ps(sum2, _mm_mul_ps(_mm_loadu_ps(pSrc + 10), pFil[2]));
+
+ sum1 = _mm_add_ps(sum1, _mm_mul_ps(_mm_loadu_ps(pSrc + 12), pFil[3]));
+ sum2 = _mm_add_ps(sum2, _mm_mul_ps(_mm_loadu_ps(pSrc + 14), pFil[3]));
+
+ pSrc += 16;
+ pFil += 4;
+ }
+
+ // Now sum1 and sum2 both have a filtered 2-channel sample each, but we still need
+ // to sum the two hi- and lo-floats of these registers together.
+
+ // post-shuffle & add the filtered values and store to dest.
+ _mm_storeu_ps(dest, _mm_add_ps(
+ _mm_shuffle_ps(sum1, sum2, _MM_SHUFFLE(1,0,3,2)), // s2_1 s2_0 s1_3 s1_2
+ _mm_shuffle_ps(sum1, sum2, _MM_SHUFFLE(3,2,1,0)) // s2_3 s2_2 s1_1 s1_0
+ ));
+ source += 4;
+ dest += 4;
+ }
+
+ // Ideas for further improvement:
+ // 1. If it could be guaranteed that 'source' were always aligned to 16-byte
+ // boundary, a faster aligned '_mm_load_ps' instruction could be used.
+ // 2. If it could be guaranteed that 'dest' were always aligned to 16-byte
+ // boundary, a faster '_mm_store_ps' instruction could be used.
+
+ return static_cast<uint32_t>(count);
+
+ /* original routine in C-language. please notice the C-version has differently
+ organized coefficients though.
+ double suml1, suml2;
+ double sumr1, sumr2;
+ uint32_t i, j;
+
+ for (j = 0; j < count; j += 2)
+ {
+ const float *ptr;
+ const float *pFil;
+
+ suml1 = sumr1 = 0.0;
+ suml2 = sumr2 = 0.0;
+ ptr = src;
+ pFil = filterCoeffs;
+ for (i = 0; i < lengthLocal; i ++)
+ {
+ // unroll loop for efficiency.
+
+ suml1 += ptr[0] * pFil[0] +
+ ptr[2] * pFil[2] +
+ ptr[4] * pFil[4] +
+ ptr[6] * pFil[6];
+
+ sumr1 += ptr[1] * pFil[1] +
+ ptr[3] * pFil[3] +
+ ptr[5] * pFil[5] +
+ ptr[7] * pFil[7];
+
+ suml2 += ptr[8] * pFil[0] +
+ ptr[10] * pFil[2] +
+ ptr[12] * pFil[4] +
+ ptr[14] * pFil[6];
+
+ sumr2 += ptr[9] * pFil[1] +
+ ptr[11] * pFil[3] +
+ ptr[13] * pFil[5] +
+ ptr[15] * pFil[7];
+
+ ptr += 16;
+ pFil += 8;
+ }
+ dest[0] = (float)suml1;
+ dest[1] = (float)sumr1;
+ dest[2] = (float)suml2;
+ dest[3] = (float)sumr2;
+
+ src += 4;
+ dest += 4;
+ }*/
+}
+
+#endif // SOUNDTOUCH_ALLOW_SSE
+
--- a/src/in_2sf/desmume/metaspu/Timestretcher.cpp
+++ b/src/in_2sf/desmume/metaspu/Timestretcher.cpp
@@ -17,15 +17,11 @@
#include "XSFCommon.h"
-//#include "Global.h"
#include "../types.h"
#include "SoundTouch/SoundTouch.h"
#include "SndOut.h"
-//#include "SoundTouch/WavFile.h"
-
-#include "SoundTouch/Dialogs.h"
-
-static soundtouch::SoundTouch* pSoundTouch = NULL;
+
+static std::unique_ptr<soundtouch::SoundTouch> pSoundTouch;
static int ts_stats_stretchblocks = 0;
static int ts_stats_normalblocks = 0;
static int ts_stats_logcounter = 0;
@@ -42,7 +38,7 @@
float SndBuffer::eTempo = 1;
int SndBuffer::freezeTempo = 0;
-void SndBuffer::PredictDataWrite( int samples )
+void SndBuffer::PredictDataWrite(int samples)
{
m_predictData += samples;
}
@@ -63,24 +59,22 @@
//ConLog( "Data %d >>> driver: %d predict: %d\n", data, drvempty, predictData );
- float result = (float)(m_data + m_predictData - drvempty) - (m_size/2);
- result /= (m_size/2);
+ float result = static_cast<float>(m_data + m_predictData - drvempty) - (m_size / 2);
+ result /= m_size / 2;
return result;
}
void SndBuffer::UpdateTempoChange()
{
- if( --freezeTempo > 0 )
- {
+ if (--freezeTempo > 0)
return;
- }
float statusPct = GetStatusPct();
float pctChange = statusPct - lastPct;
float tempoChange;
float emergencyAdj = 0;
- float newcee = cTempo; // workspace var. for cTempo
+ float newcee = cTempo; // workspace var. for cTempo
// IMPORTANT!
// If you plan to tweak these values, make sure you're using a release build
@@ -97,14 +91,12 @@
tempoChange = pctChange * 0.75f;
- if( statusPct * tempoChange < 0.0f )
- {
+ if (statusPct * tempoChange < 0.0f)
// only apply tempo change if it is in synch with the buffer status.
// In other words, if the buffer is high (over 0%), and is decreasing,
// ignore it. It'll just muck things up.
tempoChange = 0;
- }
// Sudden spikes in framerate can cause the nominal buffer status
// to go critical, in which case we have to enact an emergency
@@ -125,27 +117,22 @@
// Prediction based on the buffer fill status:
- const float statusWeight = 2.99f;
- const float statusRange = 0.068f;
+ float statusWeight = 2.99f;
+ float statusRange = 0.068f;
// "non-emergency" deadzone: In this area stretching will be strongly discouraged.
// Note: due tot he nature of timestretch latency, it's always a wee bit harder to
// cope with low fps (underruns) than it is high fps (overruns). So to help out a
// little, the low-end portions of this check are less forgiving than the high-sides.
- if( cTempo < 0.965f || cTempo > 1.060f ||
- pctChange < -0.38f || pctChange > 0.54f ||
- statusPct < -0.32f || statusPct > 0.39f ||
- eTempo < 0.89f || eTempo > 1.19f )
- {
- emergencyAdj = ( pow( statusPct*statusWeight, 3.0f ) * statusRange);
- }
+ if (cTempo < 0.965f || cTempo > 1.060f || pctChange < -0.38f || pctChange > 0.54f || statusPct < -0.32f || statusPct > 0.39f || eTempo < 0.89f || eTempo > 1.19f)
+ emergencyAdj = std::pow(statusPct * statusWeight, 3.0f) * statusRange;
// Smooth things out by factoring our previous adjustment into this one.
// It helps make the system 'feel' a little smarter by giving it at least
// one packet worth of history to help work off of:
- emergencyAdj = (emergencyAdj * 0.75f) + (lastEmergencyAdj * 0.25f );
+ emergencyAdj = (emergencyAdj * 0.75f) + (lastEmergencyAdj * 0.25f);
lastEmergencyAdj = emergencyAdj;
lastPct = statusPct;
@@ -157,30 +144,34 @@
// at 100ms latency, which is pretty good (larger buffers normalize even
// quicker).
- newcee += newcee * (tempoChange+emergencyAdj) * 0.03f;
+ newcee += newcee * (tempoChange + emergencyAdj) * 0.03f;
// Apply tempoChange as a scale of cTempo. That way the effect is proportional
// to the current tempo. (otherwise tempos rate of change at the extremes would
// be too drastic)
- float newTempo = newcee + ( emergencyAdj * cTempo );
+ float newTempo = newcee + (emergencyAdj * cTempo);
// ... and as a final optimization, only stretch if the new tempo is outside
// a nominal threshold. Keep this threshold check small, because it could
// cause some serious side effects otherwise. (enlarging the cTempo check above
// is usually better/safer)
- if( newTempo < 0.970f || newTempo > 1.045f )
+ if (newTempo < 0.970f || newTempo > 1.045f)
{
- cTempo = (float)newcee;
-
- if( newTempo < 0.10f ) newTempo = 0.10f;
- else if( newTempo > 10.0f ) newTempo = 10.0f;
-
- if( cTempo < 0.15f ) cTempo = 0.15f;
- else if( cTempo > 7.5f ) cTempo = 7.5f;
-
- pSoundTouch->setTempo( eTempo = (float)newTempo );
- ts_stats_stretchblocks++;
+ cTempo = newcee;
+
+ if (newTempo < 0.10f)
+ newTempo = 0.10f;
+ else if (newTempo > 10.0f)
+ newTempo = 10.0f;
+
+ if (cTempo < 0.15f)
+ cTempo = 0.15f;
+ else if (cTempo > 7.5f)
+ cTempo = 7.5f;
+
+ pSoundTouch->setTempo(eTempo = newTempo);
+ ++ts_stats_stretchblocks;
/*ConLog(" * SPU2: [Nominal %d%%] [Emergency: %d%%] (baseTempo: %d%% ) (newTempo: %d%%) (buffer: %d%%)\n",
//(relation < 0.0) ? "Normalize" : "",
@@ -199,14 +190,14 @@
if (!fEqual(cTempo, 1.0f))
{
cTempo = 1.0f;
- eTempo = ( 1.0f + eTempo ) * 0.5f;
- pSoundTouch->setTempo( eTempo );
+ eTempo = (1.0f + eTempo) * 0.5f;
+ pSoundTouch->setTempo(eTempo);
}
else
{
if (!fEqual(eTempo, cTempo))
- pSoundTouch->setTempo( eTempo=cTempo );
- ts_stats_normalblocks++;
+ pSoundTouch->setTempo(eTempo = cTempo);
+ ++ts_stats_normalblocks;
}
}
}
@@ -215,10 +206,11 @@
{
// timeStretcher failed it's job. We need to slow down the audio some.
- cTempo -= (cTempo * 0.12f);
- eTempo -= (eTempo * 0.30f);
- if( eTempo < 0.1f ) eTempo = 0.1f;
- pSoundTouch->setTempo( eTempo );
+ cTempo -= cTempo * 0.12f;
+ eTempo -= eTempo * 0.30f;
+ if (eTempo < 0.1f)
+ eTempo = 0.1f;
+ pSoundTouch->setTempo(eTempo);
}
int32_t SndBuffer::timeStretchOverrun()
@@ -227,33 +219,34 @@
// up audio playback.
cTempo += cTempo * 0.12f;
eTempo += eTempo * 0.40f;
- if( eTempo > 7.5f ) eTempo = 7.5f;
- pSoundTouch->setTempo( eTempo );
+ if (eTempo > 7.5f)
+ eTempo = 7.5f;
+ pSoundTouch->setTempo(eTempo);
// Throw out just a little bit (two packets worth) to help
// give the TS some room to work:
- return SndOutPacketSize*2;
-}
-
-static void CvtPacketToFloat( StereoOut32* srcdest )
-{
- StereoOutFloat* dest = (StereoOutFloat*)srcdest;
- const StereoOut32* src = (StereoOut32*)srcdest;
- for( int i=0; i<SndOutPacketSize; ++i, ++dest, ++src )
- *dest = (StereoOutFloat)*src;
+ return SndOutPacketSize * 2;
+}
+
+static void CvtPacketToFloat(StereoOut32 *srcdest)
+{
+ StereoOutFloat *dest = reinterpret_cast<StereoOutFloat *>(srcdest);
+ const StereoOut32 *src = srcdest;
+ for (int i = 0; i < SndOutPacketSize; ++i, ++dest, ++src)
+ *dest = static_cast<StereoOutFloat>(*src);
}
// Parameter note: Size should always be a multiple of 128, thanks!
-static void CvtPacketToInt( StereoOut32* srcdest, uint32_t size )
+static void CvtPacketToInt(StereoOut32 *srcdest, uint32_t size)
{
//jASSUME( (size & 127) == 0 );
- const StereoOutFloat* src = (StereoOutFloat*)srcdest;
- StereoOut32* dest = srcdest;
-
- for( uint32_t i=0; i<size; ++i, ++dest, ++src )
- *dest = (StereoOut32)*src;
+ const StereoOutFloat *src = reinterpret_cast<StereoOutFloat *>(srcdest);
+ StereoOut32 *dest = srcdest;
+
+ for (uint32_t i = 0; i < size; ++i, ++dest, ++src)
+ *dest = static_cast<StereoOut32>(*src);
}
void SndBuffer::timeStretchWrite()
@@ -266,20 +259,19 @@
// suddenly we'll get several chunks back at once. Thus we use
// data prediction to make the timestretcher more responsive.
- PredictDataWrite( (int)( SndOutPacketSize / eTempo ) );
- CvtPacketToFloat( sndTempBuffer );
-
- pSoundTouch->putSamples( (float*)sndTempBuffer, SndOutPacketSize );
+ PredictDataWrite(static_cast<int>(SndOutPacketSize / eTempo));
+ CvtPacketToFloat(sndTempBuffer.get());
+
+ pSoundTouch->putSamples(reinterpret_cast<float *>(sndTempBuffer.get()), SndOutPacketSize);
int tempProgress;
- while( tempProgress = pSoundTouch->receiveSamples( (float*)sndTempBuffer, SndOutPacketSize),
- tempProgress != 0 )
+ while (tempProgress = pSoundTouch->receiveSamples(reinterpret_cast<float *>(sndTempBuffer.get()), SndOutPacketSize), !!tempProgress)
{
// Hint: It's assumed that pSoundTouch will return chunks of 128 bytes (it always does as
// long as the SSE optimizations are enabled), which means we can do our own SSE opts here.
- CvtPacketToInt( sndTempBuffer, tempProgress );
- _WriteSamples( sndTempBuffer, tempProgress );
+ CvtPacketToInt(sndTempBuffer.get(), tempProgress);
+ _WriteSamples(sndTempBuffer.get(), tempProgress);
progress = true;
}
@@ -288,15 +280,13 @@
//TODO
//if( MsgOverruns() )
{
- if( progress )
+ if(progress)
{
- if( ++ts_stats_logcounter > 300 )
+ if (++ts_stats_logcounter > 300)
{
ts_stats_logcounter = 0;
- printf( " * SPU2 > Timestretch Stats > %d%% of packets stretched.\n",
- ( ts_stats_stretchblocks * 100 ) / ( ts_stats_normalblocks + ts_stats_stretchblocks ) );
- ts_stats_normalblocks = 0;
- ts_stats_stretchblocks = 0;
+ printf(" * SPU2 > Timestretch Stats > %d%% of packets stretched.\n", (ts_stats_stretchblocks * 100) / (ts_stats_normalblocks + ts_stats_stretchblocks));
+ ts_stats_normalblocks = ts_stats_stretchblocks = 0;
}
}
}
@@ -304,23 +294,19 @@
void SndBuffer::soundtouchInit()
{
- pSoundTouch = new soundtouch::SoundTouch();
+ pSoundTouch.reset(new soundtouch::SoundTouch());
pSoundTouch->setSampleRate(SampleRate);
pSoundTouch->setChannels(2);
- pSoundTouch->setSetting( soundtouch::SETTING_USE_QUICKSEEK, 0 );
- pSoundTouch->setSetting( soundtouch::SETTING_USE_AA_FILTER, 0 );
-
- SoundtouchCfg::ApplySettings( *pSoundTouch );
+ pSoundTouch->setSetting(soundtouch::SETTING_USE_QUICKSEEK, 0);
+ pSoundTouch->setSetting(soundtouch::SETTING_USE_AA_FILTER, 0);
pSoundTouch->setTempo(1);
// some timestretch management vars:
- cTempo = 1.0;
- eTempo = 1.0;
- lastPct = 0;
- lastEmergencyAdj = 0;
+ cTempo = eTempo = 1.0;
+ lastPct = lastEmergencyAdj = 0;
// just freeze tempo changes for a while at startup.
// the driver buffers are bogus anyway.
@@ -328,26 +314,3 @@
m_predictData = 0;
}
-// reset timestretch management vars, and delay updates a bit:
-void SndBuffer::soundtouchClearContents()
-{
- if( pSoundTouch == NULL ) return;
-
- pSoundTouch->clear();
- pSoundTouch->setTempo(1);
-
- cTempo = 1.0;
- eTempo = 1.0;
- lastPct = 0;
- lastEmergencyAdj = 0;
-
- freezeTempo = 16;
- m_predictData = 0;
-}
-
-void SndBuffer::soundtouchCleanup()
-{
- //safe_delete( pSoundTouch );
- delete pSoundTouch;
-}
-
--- a/src/in_2sf/desmume/metaspu/metaspu.cpp
+++ b/src/in_2sf/desmume/metaspu/metaspu.cpp
@@ -20,7 +20,6 @@
#include <queue>
#include <vector>
#include <cassert>
-
#include "../types.h"
#include "metaspu.h"
@@ -30,68 +29,51 @@
#include "SndOut.h"
#endif
-/*template<typename T> inline T _abs(T val)
-{
- if(val<0) return -val;
- else return val;
-}*/
-
-/*template<typename T> inline T moveValueTowards(T val, T target, T incr)
-{
- incr = _abs(incr);
- T delta = _abs(target-val);
- if(val<target) val += incr;
- else if(val>target) val -= incr;
- T newDelta = _abs(target-val);
- if(newDelta >= delta)
- val = target;
- return val;
-}*/
-
class ZeromusSynchronizer : public ISynchronizingAudioBuffer
{
public:
- ZeromusSynchronizer()
- : mixqueue_go(false)
- ,
- #ifdef NDEBUG
- adjustobuf(200,1000)
- #else
- adjustobuf(22000,44000)
- #endif
- {
-
+ ZeromusSynchronizer() : mixqueue_go(false),
+#ifdef NDEBUG
+ adjustobuf(200, 1000)
+#else
+ adjustobuf(22000, 44000)
+#endif
+ {
}
bool mixqueue_go;
- virtual void enqueue_samples(int16_t* buf, int samples_provided)
- {
- for(int i=0;i<samples_provided;i++) {
+ virtual void enqueue_samples(int16_t *buf, int samples_provided)
+ {
+ for (int i = 0; i < samples_provided; ++i)
+ {
int16_t left = *buf++;
int16_t right = *buf++;
- adjustobuf.enqueue(left,right);
- }
- }
-
- //returns the number of samples actually supplied, which may not match the number requested
- virtual int output_samples(int16_t* buf, int samples_requested)
+ this->adjustobuf.enqueue(left, right);
+ }
+ }
+
+ // returns the number of samples actually supplied, which may not match the number requested
+ virtual int output_samples(int16_t *buf, int samples_requested)
{
int done = 0;
- if(!mixqueue_go) {
- if(adjustobuf.size > 200)
- mixqueue_go = true;
+ if (!this->mixqueue_go)
+ {
+ if (this->adjustobuf.size > 200)
+ this->mixqueue_go = true;
}
else
{
- for(int i=0;i<samples_requested;i++) {
- if(adjustobuf.size==0) {
- mixqueue_go = false;
+ for (int i = 0; i < samples_requested; ++i)
+ {
+ if (!this->adjustobuf.size)
+ {
+ this->mixqueue_go = false;
break;
}
- done++;
+ ++done;
int16_t left, right;
- adjustobuf.dequeue(left,right);
+ this->adjustobuf.dequeue(left, right);
*buf++ = left;
*buf++ = right;
}
@@ -104,17 +86,14 @@
class Adjustobuf
{
public:
- Adjustobuf(int _minLatency, int _maxLatency)
- : minLatency(_minLatency)
- , maxLatency(_maxLatency)
- , size(0)
- {
- rollingTotalSize = 0;
- targetLatency = (maxLatency + minLatency)/2;
- rate = 1.0f;
- cursor = 0.0f;
- curr[0] = curr[1] = 0;
- kAverageSize = 80000;
+ Adjustobuf(int _minLatency, int _maxLatency) : minLatency(_minLatency), maxLatency(_maxLatency), size(0)
+ {
+ this->rollingTotalSize = 0;
+ this->targetLatency = (this->maxLatency + this->minLatency) / 2;
+ this->rate = 1.0f;
+ this->cursor = 0.0f;
+ this->curr[0] = this->curr[1] = 0;
+ this->kAverageSize = 80000;
}
float rate, cursor;
@@ -127,9 +106,9 @@
void enqueue(int16_t left, int16_t right)
{
- buffer.push(left);
- buffer.push(right);
- size++;
+ this->buffer.push(left);
+ this->buffer.push(right);
+ ++this->size;
}
int64_t rollingTotalSize;
@@ -138,50 +117,51 @@
void addStatistic()
{
- statsHistory.push(size);
- rollingTotalSize += size;
- if(statsHistory.size()>kAverageSize)
- {
- rollingTotalSize -= statsHistory.front();
- statsHistory.pop();
-
- float averageSize = (float)(rollingTotalSize / kAverageSize);
+ this->statsHistory.push(this->size);
+ this->rollingTotalSize += this->size;
+ if (this->statsHistory.size() > this->kAverageSize)
+ {
+ this->rollingTotalSize -= this->statsHistory.front();
+ this->statsHistory.pop();
+
+ float averageSize = static_cast<float>(rollingTotalSize / kAverageSize);
//static int ctr=0; ctr++; if((ctr&127)==0) printf("avg size: %f curr size: %d rate: %f\n",averageSize,size,rate);
{
float targetRate;
- if(averageSize < targetLatency)
- {
- targetRate = 1.0f - (targetLatency-averageSize)/kAverageSize;
- }
- else if(averageSize > targetLatency) {
- targetRate = 1.0f + (averageSize-targetLatency)/kAverageSize;
- } else targetRate = 1.0f;
+ if (averageSize < this->targetLatency)
+ targetRate = 1.0f - (this->targetLatency - averageSize) / this->kAverageSize;
+ else if (averageSize > this->targetLatency)
+ targetRate = 1.0f + (averageSize - this->targetLatency) / this->kAverageSize;
+ else
+ targetRate = 1.0f;
//rate = moveValueTowards(rate,targetRate,0.001f);
- rate = targetRate;
- }
-
+ this->rate = targetRate;
+ }
}
-
-
- }
-
- void dequeue(int16_t& left, int16_t& right)
+ }
+
+ void dequeue(int16_t &left, int16_t &right)
{
left = right = 0;
- addStatistic();
- if(size==0) { return; }
- cursor += rate;
- while(cursor>1.0f) {
- cursor -= 1.0f;
- if(size>0) {
- curr[0] = buffer.front(); buffer.pop();
- curr[1] = buffer.front(); buffer.pop();
- size--;
+ this->addStatistic();
+ if (!this->size)
+ return;
+ this->cursor += this->rate;
+ while (this->cursor > 1.0f)
+ {
+ this->cursor -= 1.0f;
+ if (this->size > 0)
+ {
+ this->curr[0] = this->buffer.front();
+ this->buffer.pop();
+ this->curr[1] = this->buffer.front();
+ this->buffer.pop();
+ --this->size;
}
}
- left = curr[0];
- right = curr[1];
+ left = this->curr[0];
+ right = this->curr[1];
}
} adjustobuf;
};
@@ -192,18 +172,18 @@
struct ssamp
{
int16_t l, r;
- ssamp() {}
- ssamp(int16_t ll, int16_t rr) : l(ll), r(rr) {}
+ ssamp() { }
+ ssamp(int16_t ll, int16_t rr) : l(ll), r(rr) { }
};
std::vector<ssamp> sampleQueue;
// returns values going between 0 and y-1 in a saw wave pattern, based on x
- static inline int pingpong(int x, int y)
- {
- x %= 2*y;
- if(x >= y)
- x = 2*y - x - 1;
+ static int pingpong(int x, int y)
+ {
+ x %= 2 * y;
+ if (x >= y)
+ x = 2 * y - x - 1;
return x;
// in case we want to switch to odd buffer sizes for more sharpness
@@ -213,11 +193,11 @@
//return x;
}
- static inline ssamp crossfade (ssamp lhs, ssamp rhs, int cur, int start, int end)
- {
- if(cur <= start)
+ static ssamp crossfade(const ssamp &lhs, const ssamp &rhs, int cur, int start, int end)
+ {
+ if (cur <= start)
return lhs;
- if(cur >= end)
+ if (cur >= end)
return rhs;
// in case we want sine wave interpolation instead of linear here
@@ -228,62 +208,61 @@
int outNum = end - cur;
int denom = end - start;
- int lrv = ((int)lhs.l * outNum + (int)rhs.l * inNum) / denom;
- int rrv = ((int)lhs.r * outNum + (int)rhs.r * inNum) / denom;
-
- return ssamp(lrv,rrv);
- }
-
- static inline void emit_sample(int16_t*& outbuf, ssamp sample)
+ int lrv = (static_cast<int>(lhs.l) * outNum + static_cast<int>(rhs.l) * inNum) / denom;
+ int rrv = (static_cast<int>(lhs.r) * outNum + static_cast<int>(rhs.r) * inNum) / denom;
+
+ return ssamp(lrv, rrv);
+ }
+
+ static void emit_sample(int16_t *&outbuf, const ssamp &sample)
{
*outbuf++ = sample.l;
*outbuf++ = sample.r;
}
- static inline void emit_samples(int16_t*& outbuf, const ssamp* samplebuf, int samples)
- {
- for(int i=0;i<samples;i++)
- emit_sample(outbuf,samplebuf[i]);
+ static void emit_samples(int16_t *&outbuf, const ssamp *samplebuf, int samples)
+ {
+ for (int i = 0; i < samples; ++i)
+ NitsujaSynchronizer::emit_sample(outbuf, samplebuf[i]);
}
public:
- NitsujaSynchronizer()
- {}
-
- virtual void enqueue_samples(int16_t* buf, int samples_provided)
- {
- for(int i=0;i<samples_provided;i++)
- {
- sampleQueue.push_back(ssamp(buf[0],buf[1]));
+ NitsujaSynchronizer() { }
+
+ virtual void enqueue_samples(int16_t *buf, int samples_provided)
+ {
+ for (int i = 0; i < samples_provided; ++i)
+ {
+ this->sampleQueue.push_back(ssamp(buf[0], buf[1]));
buf += 2;
}
}
- virtual int output_samples(int16_t* buf, int samples_requested)
+ virtual int output_samples(int16_t *buf, int samples_requested)
{
int audiosize = samples_requested;
- int queued = sampleQueue.size();
+ int queued = this->sampleQueue.size();
// I am too lazy to deal with odd numbers
audiosize &= ~1;
queued &= ~1;
- if(queued > 0x200 && audiosize > 0) // is there any work to do?
+ if (queued > 0x200 && audiosize > 0) // is there any work to do?
{
// are we going at normal speed?
// or more precisely, are the input and output queues/buffers of similar size?
- if(queued > 900 || audiosize > queued * 2)
+ if (queued > 900 || audiosize > queued * 2)
{
// not normal speed. we have to resample it somehow in this case.
- if(audiosize <= queued)
+ if (audiosize <= queued)
{
// fast forward speed
// this is the easy case, just crossfade it and it sounds ok
- for(int i = 0; i < audiosize; i++)
+ for (int i = 0; i < audiosize; ++i)
{
int j = i + queued - audiosize;
- ssamp outsamp = crossfade(sampleQueue[i],sampleQueue[j], i,0,audiosize);
- emit_sample(buf,outsamp);
+ ssamp outsamp = this->crossfade(this->sampleQueue[i], this->sampleQueue[j], i, 0, audiosize);
+ this->emit_sample(buf, outsamp);
}
}
else
@@ -322,19 +301,19 @@
static const int worstdiff = 99999999;
int beststartdiff = worstdiff;
int bestenddiff = worstdiff;
- for(int i = 0; i < 128; i+=2)
+ for(int i = 0; i < 128; i += 2)
{
- int diff = abs(sampleQueue[i].l - sampleQueue[i+1].l) + abs(sampleQueue[i].r - sampleQueue[i+1].r);
- if(diff < beststartdiff)
+ int diff = std::abs(this->sampleQueue[i].l - this->sampleQueue[i + 1].l) + std::abs(this->sampleQueue[i].r - this->sampleQueue[i + 1].r);
+ if (diff < beststartdiff)
{
beststartdiff = diff;
beststart = i;
}
}
- for(int i = queued-3; i > queued-3-128; i-=2)
+ for (int i = queued - 3; i > queued - 3 - 128; i -= 2)
{
- int diff = abs(sampleQueue[i].l - sampleQueue[i+1].l) + abs(sampleQueue[i].r - sampleQueue[i+1].r);
- if(diff < bestenddiff)
+ int diff = std::abs(this->sampleQueue[i].l - this->sampleQueue[i + 1].l) + std::abs(this->sampleQueue[i].r - this->sampleQueue[i + 1].r);
+ if (diff < bestenddiff)
{
bestenddiff = diff;
bestend = i+1;
@@ -345,17 +324,14 @@
queued = bestend - beststart;
int oksize = queued;
- while(oksize + queued*2 + beststart + extraAtEnd <= samples_requested)
- oksize += queued*2;
+ while (oksize + queued * 2 + beststart + extraAtEnd <= samples_requested)
+ oksize += queued * 2;
audiosize = oksize;
- for(int x = 0; x < beststart; x++)
- {
- emit_sample(buf,sampleQueue[x]);
- }
- sampleQueue.erase(sampleQueue.begin(), sampleQueue.begin() + beststart);
- }
-
+ for (int x = 0; x < beststart; ++x)
+ this->emit_sample(buf, this->sampleQueue[x]);
+ this->sampleQueue.erase(this->sampleQueue.begin(), this->sampleQueue.begin() + beststart);
+ }
int midpointX = audiosize >> 1;
int midpointY = queued >> 1;
@@ -367,19 +343,19 @@
// so here's a stupid search for the value for now:
int prevA = 999999;
- int midpointXOffset = queued/2;
- while(true)
- {
- int a = abs(pingpong(midpointX - midpointXOffset, queued) - midpointY) - midpointXOffset;
- if(((a > 0) != (prevA > 0) || (a < 0) != (prevA < 0)) && prevA != 999999)
+ int midpointXOffset = queued / 2;
+ while (true)
+ {
+ int a = std::abs(this->pingpong(midpointX - midpointXOffset, queued) - midpointY) - midpointXOffset;
+ if (((a > 0) != (prevA > 0) || (a < 0) != (prevA < 0)) && prevA != 999999)
{
- if((a + prevA)&1) // there's some sort of off-by-one problem with this search since we're moving diagonally...
- midpointXOffset++; // but this fixes it most of the time...
+ if ((a + prevA) & 1) // there's some sort of off-by-one problem with this search since we're moving diagonally...
+ ++midpointXOffset; // but this fixes it most of the time...
break; // found it
}
prevA = a;
- midpointXOffset--;
- if(midpointXOffset < 0)
+ --midpointXOffset;
+ if (midpointXOffset < 0)
{
midpointXOffset = 0;
break; // failed to find it. the two sides probably meet exactly in the center.
@@ -389,41 +365,41 @@
int leftMidpointX = midpointX - midpointXOffset;
int rightMidpointX = midpointX + midpointXOffset;
int leftMidpointY = pingpong(leftMidpointX, queued);
- int rightMidpointY = (queued-1) - pingpong((int)audiosize-1 - rightMidpointX + queued*2, queued);
+ int rightMidpointY = (queued - 1) - this->pingpong(audiosize - 1 - rightMidpointX + queued * 2, queued);
// output the left almost-half of the sound (section "A")
- for(int x = 0; x < leftMidpointX; x++)
- {
- int i = pingpong(x, queued);
- emit_sample(buf,sampleQueue[i]);
+ for (int x = 0; x < leftMidpointX; ++x)
+ {
+ int i = this->pingpong(x, queued);
+ this->emit_sample(buf, this->sampleQueue[i]);
}
// output the middle stretch (section "B")
int y = leftMidpointY;
- int dyMidLeft = (leftMidpointY < midpointY) ? 1 : -1;
- int dyMidRight = (rightMidpointY > midpointY) ? 1 : -1;
- for(int x = leftMidpointX; x < midpointX; x++, y+=dyMidLeft)
- emit_sample(buf,sampleQueue[y]);
- for(int x = midpointX; x < rightMidpointX; x++, y+=dyMidRight)
- emit_sample(buf,sampleQueue[y]);
+ int dyMidLeft = leftMidpointY < midpointY ? 1 : -1;
+ int dyMidRight = rightMidpointY > midpointY ? 1 : -1;
+ for (int x = leftMidpointX; x < midpointX; ++x, y += dyMidLeft)
+ this->emit_sample(buf, this->sampleQueue[y]);
+ for (int x = midpointX; x < rightMidpointX; ++x, y += dyMidRight)
+ this->emit_sample(buf, this->sampleQueue[y]);
// output the end of the queued sound (section "C")
- for(int x = rightMidpointX; x < audiosize; x++)
- {
- int i = (queued-1) - pingpong((int)audiosize-1 - x + queued*2, queued);
- emit_sample(buf,sampleQueue[i]);
- }
-
- for(int x = 0; x < extraAtEnd; x++)
+ for (int x = rightMidpointX; x < audiosize; ++x)
+ {
+ int i = (queued - 1) - this->pingpong(audiosize - 1 - x + queued * 2, queued);
+ this->emit_sample(buf, sampleQueue[i]);
+ }
+
+ for (int x = 0; x < extraAtEnd; ++x)
{
int i = queued + x;
- emit_sample(buf,sampleQueue[i]);
+ this->emit_sample(buf, this->sampleQueue[i]);
}
queued += extraAtEnd;
audiosize += beststart + extraAtEnd;
} //end else
- sampleQueue.erase(sampleQueue.begin(), sampleQueue.begin() + queued);
+ this->sampleQueue.erase(this->sampleQueue.begin(), this->sampleQueue.begin() + queued);
return audiosize;
}
else
@@ -437,31 +413,23 @@
// but that's ok! because all of these branches sound similar enough that we can get away with it.
// so the two cases actually complement each other.
- if(audiosize >= queued)
- {
- emit_samples(buf,&sampleQueue[0],queued);
- sampleQueue.erase(sampleQueue.begin(), sampleQueue.begin() + queued);
+ if (audiosize >= queued)
+ {
+ this->emit_samples(buf, &this->sampleQueue[0], queued);
+ this->sampleQueue.erase(this->sampleQueue.begin(), this->sampleQueue.begin() + queued);
return queued;
}
else
{
- emit_samples(buf,&sampleQueue[0],audiosize);
- sampleQueue.erase(sampleQueue.begin(), sampleQueue.begin()+audiosize);
+ this->emit_samples(buf, &this->sampleQueue[0], audiosize);
+ this->sampleQueue.erase(this->sampleQueue.begin(), this->sampleQueue.begin() + audiosize);
return audiosize;
}
-
} //end normal speed
-
} //end if there is any work to do
else
- {
return 0;
- }
-
} //output_samples
-
-private:
-
}; //NitsujaSynchronizer
#ifdef _MSC_VER
@@ -473,47 +441,51 @@
{
SndBuffer::Init();
}
- virtual void enqueue_samples(int16_t* buf, int samples_provided)
- {
- for(int i=0;i<samples_provided;i++)
- {
- StereoOut32 so32(buf[0],buf[1]);
+ virtual void enqueue_samples(int16_t *buf, int samples_provided)
+ {
+ for (int i = 0; i < samples_provided; ++i)
+ {
+ auto so32 = StereoOut32(buf[0], buf[1]);
SndBuffer::Write(so32);
- buf++;
- buf++;
- }
- }
-
- virtual int output_samples(int16_t* buf, int samples_requested)
- {
- for(int i=0;i<samples_requested;i++) {
- if(readySamples.size()==0) {
+ buf += 2;
+ }
+ }
+
+ virtual int output_samples(int16_t *buf, int samples_requested)
+ {
+ for (int i = 0; i < samples_requested; ++i)
+ {
+ if (!this->readySamples.size())
+ {
//SndOutPacketSize
- StereoOut16 temp[SndOutPacketSize*2];
- SndBuffer::ReadSamples( temp );
- for(int i=0;i<SndOutPacketSize;i++) {
- readySamples.push(temp[i].Left);
- readySamples.push(temp[i].Right);
+ StereoOut16 temp[SndOutPacketSize * 2];
+ SndBuffer::ReadSamples(temp);
+ for (int i = 0; i < SndOutPacketSize; ++i)
+ {
+ this->readySamples.push(temp[i].Left);
+ this->readySamples.push(temp[i].Right);
}
}
- *buf++ = readySamples.front(); readySamples.pop();
- *buf++ = readySamples.front(); readySamples.pop();
+ *buf++ = this->readySamples.front();
+ this->readySamples.pop();
+ *buf++ = this->readySamples.front();
+ this->readySamples.pop();
}
return samples_requested;
}
};
#endif
-ISynchronizingAudioBuffer* metaspu_construct(ESynchMethod method)
+ISynchronizingAudioBuffer *metaspu_construct(ESynchMethod method)
{
switch(method)
{
- case ESynchMethod_N: return new NitsujaSynchronizer();
- case ESynchMethod_Z: return new ZeromusSynchronizer();
- #ifdef _MSC_VER
- case ESynchMethod_P: return new PCSX2Synchronizer();
- #endif
- default: return NULL;
+ case ESynchMethod_N: return new NitsujaSynchronizer();
+ case ESynchMethod_Z: return new ZeromusSynchronizer();
+#ifdef _MSC_VER
+ case ESynchMethod_P: return new PCSX2Synchronizer();
+#endif
+ default: return nullptr;
}
}
--- a/src/in_2sf/desmume/metaspu/metaspu.h
+++ b/src/in_2sf/desmume/metaspu/metaspu.h
@@ -14,27 +14,16 @@
along with the this software. If not, see <http://www.gnu.org/licenses/>.
*/
-//-------------------------
-//this file contains the METASPU system
-//which is designed to handle the task of audio synchronization
-//and is designed to be as portable between multiple emulators
-//-------------------------
+// -------------------------
+// this file contains the METASPU system
+// which is designed to handle the task of audio synchronization
+// and is designed to be as portable between multiple emulators
+// -------------------------
#ifndef _METASPU_H_
#define _METASPU_H_
-#include <algorithm>
-#include <cmath>
-
-/*template<typename T> static inline void Clampify(T &src, T min, T max)
-{
- src = std::min(std::max(src, min), max);
-}*/
-
-/*template<typename T> static inline T GetClamped(T src, T min, T max)
-{
- return std::min(std::max( src, min ), max);
-}*/
+#include "../types.h"
class ISynchronizingAudioBuffer
{
@@ -53,9 +42,9 @@
enum ESynchMethod
{
- ESynchMethod_N, //nitsuja's
- ESynchMethod_Z, //zero's
- ESynchMethod_P //PCSX2 spu2-x
+ ESynchMethod_N, // nitsuja's
+ ESynchMethod_Z, // zero's
+ ESynchMethod_P // PCSX2 spu2-x
};
ISynchronizingAudioBuffer *metaspu_construct(ESynchMethod method);
--- a/src/in_2sf/desmume/path.cpp
+++ /dev/null
@@ -1,158 +1,1 @@
-/*
- Copyright (C) 2009-2011 DeSmuME team
- This file is free software: you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation, either version 2 of the License, or
- (at your option) any later version.
-
- This file is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with the this software. If not, see <http://www.gnu.org/licenses/>.
-*/
-
-#include "types.h"
-
-#include "path.h"
-#include <cstdio>
-
-//-----------------------------------
-//This is taken from mono Path.cs
-static const char InvalidPathChars[] = {
- '\x22', '\x3C', '\x3E', '\x7C', '\x00', '\x01', '\x02', '\x03', '\x04', '\x05', '\x06', '\x07',
- '\x08', '\x09', '\x0A', '\x0B', '\x0C', '\x0D', '\x0E', '\x0F', '\x10', '\x11', '\x12',
- '\x13', '\x14', '\x15', '\x16', '\x17', '\x18', '\x19', '\x1A', '\x1B', '\x1C', '\x1D',
- '\x1E', '\x1F'
-};
-
-//but it is sort of windows-specific. Does it work in linux? Maybe we'll have to make it smarter
-static const char VolumeSeparatorChar = ':';
-static const char AltDirectorySeparatorChar = '/';
-static bool dirEqualsVolume = (DIRECTORY_DELIMITER_CHAR == VolumeSeparatorChar);
-
-
-bool Path::IsPathRooted (const std::string &pth)
-{
- if (pth.empty()) {
- return false;
- }
-
- if (pth.find_first_of(InvalidPathChars) != std::string::npos) {
- return false;
- }
-
- char c = pth[0];
- return c == DIRECTORY_DELIMITER_CHAR ||
- c == AltDirectorySeparatorChar ||
- (!dirEqualsVolume && pth.size() > 1 && pth[1] == VolumeSeparatorChar);
-}
-
-std::string Path::GetFileDirectoryPath(std::string filePath)
-{
- if (filePath.empty()) {
- return "";
- }
-
- size_t i = filePath.find_last_of(DIRECTORY_DELIMITER_CHAR);
- if (i == std::string::npos) {
- return filePath;
- }
-
- return filePath.substr(0, i);
-}
-
-std::string Path::GetFileNameFromPath(std::string filePath)
-{
- if (filePath.empty()) {
- return "";
- }
-
- size_t i = filePath.find_last_of(DIRECTORY_DELIMITER_CHAR);
- if (i == std::string::npos) {
- return filePath;
- }
-
- return filePath.substr(i + 1);
-}
-
-std::string Path::GetFileNameWithoutExt(std::string fileName)
-{
- if (fileName.empty()) {
- return "";
- }
-
- size_t i = fileName.find_last_of(FILE_EXT_DELIMITER_CHAR);
- if (i == std::string::npos) {
- return fileName;
- }
-
- return fileName.substr(0, i);
-}
-
-std::string Path::GetFileNameFromPathWithoutExt(std::string filePath)
-{
- if (filePath.empty()) {
- return "";
- }
-
- std::string fileName = GetFileNameFromPath(filePath);
-
- return GetFileNameWithoutExt(fileName);
-}
-
-std::string Path::GetFileExt(std::string fileName)
-{
- if (fileName.empty()) {
- return "";
- }
-
- size_t i = fileName.find_last_of(FILE_EXT_DELIMITER_CHAR);
- if (i == std::string::npos) {
- return fileName;
- }
-
- return fileName.substr(i + 1);
-}
-
-//-----------------------------------
-#ifdef _WINDOWS
-void FCEUD_MakePathDirs(const char *fname)
-{
- char Path[MAX_PATH];
- const char* div = fname;
-
- do
- {
- const char* fptr = strchr(div, '\\');
-
- if(!fptr)
- {
- fptr = strchr(div, '/');
- }
-
- if(!fptr)
- {
- break;
- }
-
- int off = fptr - fname;
- strncpy(Path, fname, off);
- Path[off] = '\0';
- mkdir(Path);
-
- div = fptr + 1;
-
- while(div[0] == '\\' || div[0] == '/')
- {
- div++;
- }
-
- } while(1);
-}
-#endif
-//------------------------------
-
--- a/src/in_2sf/desmume/path.h
+++ /dev/null
@@ -1,427 +1,1 @@
-/* Copyright 2009-2010 DeSmuME team
- This file is free software: you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation, either version 2 of the License, or
- (at your option) any later version.
-
- This file is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with the this software. If not, see <http://www.gnu.org/licenses/>.
-*/
-
-#include <string>
-
-#ifdef _MSC_VER
-#define mkdir _mkdir
-#endif
-
-#if defined(_WINDOWS)
-//#define WIN32_LEAN_AND_MEAN
-//#include <WinSock2.h>
-#include "windowsh_wrapper.h"
-#include <direct.h>
-#if !defined(WXPORT)
-#include "resource.h"
-#else
-#include <glib.h>
-#endif /* !WXPORT */
-#else
-#include <glib.h>
-#endif /* _WINDOWS */
-
-#include <cstdlib>
-#include <ctime>
-#include <cstdio>
-#include "utils/xstring.h"
-
-#ifdef _WINDOWS
-#define FILE_EXT_DELIMITER_CHAR '.'
-#define DIRECTORY_DELIMITER_CHAR '\\'
-#else
-#define FILE_EXT_DELIMITER_CHAR '.'
-#define DIRECTORY_DELIMITER_CHAR '/'
-#endif
-
-#ifdef _WINDOWS
-void FCEUD_MakePathDirs(const char *fname);
-#endif
-
-class Path
-{
-public:
- static bool IsPathRooted (const std::string &path);
- static std::string GetFileDirectoryPath(std::string filePath);
- static std::string GetFileNameFromPath(std::string filePath);
- static std::string GetFileNameWithoutExt(std::string fileName);
- static std::string GetFileNameFromPathWithoutExt(std::string filePath);
- static std::string GetFileExt(std::string fileName);
-};
-
-class PathInfo
-{
-public:
-
- std::string path;
- std::string RomName;
- std::string RomDirectory;
-
- #define MAX_FORMAT 20
- #define SECTION "PathSettings"
-
- #define ROMKEY "Roms"
- #define BATTERYKEY "Battery"
- #define STATEKEY "States"
- #define SCREENSHOTKEY "Screenshots"
- #define AVIKEY "AviFiles"
- #define CHEATKEY "Cheats"
- #define SOUNDKEY "SoundSamples"
- #define FIRMWAREKEY "Firmware"
- #define FORMATKEY "format"
- #define DEFAULTFORMATKEY "defaultFormat"
- #define NEEDSSAVINGKEY "needsSaving"
- #define LASTVISITKEY "lastVisit"
- #define LUAKEY "Lua"
- char screenshotFormat[MAX_FORMAT];
- bool savelastromvisit;
-
- enum KnownPath
- {
- FIRSTKNOWNPATH = 0,
- ROMS = 0,
- BATTERY,
- STATES,
- SCREENSHOTS,
- AVI_FILES,
- CHEATS,
- SOUNDS,
- FIRMWARE,
- MODULE,
- MAXKNOWNPATH = MODULE
- };
-
- char pathToRoms[MAX_PATH];
- char pathToBattery[MAX_PATH];
- char pathToStates[MAX_PATH];
- char pathToScreenshots[MAX_PATH];
- char pathToAviFiles[MAX_PATH];
- char pathToCheats[MAX_PATH];
- char pathToSounds[MAX_PATH];
- char pathToFirmware[MAX_PATH];
- char pathToModule[MAX_PATH];
- char pathToLua[MAX_PATH];
-
- void init(const char * filename) {
-
- path = std::string(filename);
-
- //extract the internal part of the logical rom name
- std::vector<std::string> parts = tokenize_str(filename,"|");
- SetRomName(parts[parts.size()-1].c_str());
- LoadModulePath();
-#ifndef WIN32
- //ReadPathSettings();
-#endif
-
- }
-
- void LoadModulePath()
- {
-#if defined(_WINDOWS)
-
- char *p;
- ZeroMemory(pathToModule, sizeof(pathToModule));
-
- GetModuleFileNameA(NULL, pathToModule, sizeof(pathToModule));
- p = pathToModule + strlen(pathToModule);
- while (p >= pathToModule && *p != DIRECTORY_DELIMITER_CHAR) p--;
- if (++p >= pathToModule) *p = 0;
-#else
- char *cwd = g_build_filename(g_get_user_config_dir(), "desmume", NULL);
- g_mkdir_with_parents(cwd, 0755);
- strncpy(pathToModule, cwd, MAX_PATH);
- g_free(cwd);
-#endif
- }
-
- enum Action
- {
- GET,
- SET
- };
-
- void GetDefaultPath(char *pathToDefault, const char *, int maxCount)
- {
-#ifdef _WINDOWS
- std::string temp = (std::string)"." + DIRECTORY_DELIMITER_CHAR + pathToDefault;
- strncpy(pathToDefault, temp.c_str(), maxCount);
-#else
- strncpy(pathToDefault, pathToModule, maxCount);
-#endif
- }
-
- /*void ReadKey(char *pathToRead, const char *key)
- {
-#ifdef _WINDOWS
- GetPrivateProfileString(SECTION, key, key, pathToRead, MAX_PATH, IniName);
- if(strcmp(pathToRead, key) == 0) {
- //since the variables are all intialized in this file they all use MAX_PATH
- GetDefaultPath(pathToRead, key, MAX_PATH);
- }
-#else
- //since the variables are all intialized in this file they all use MAX_PATH
- GetDefaultPath(pathToRead, key, MAX_PATH);
-#endif
- }*/
-
- /*void ReadPathSettings()
- {
- if( ( strcmp(pathToModule, "") == 0) || !pathToModule)
- LoadModulePath();
-
- ReadKey(pathToRoms, ROMKEY);
- ReadKey(pathToBattery, BATTERYKEY);
- ReadKey(pathToStates, STATEKEY);
- ReadKey(pathToScreenshots, SCREENSHOTKEY);
- ReadKey(pathToAviFiles, AVIKEY);
- ReadKey(pathToCheats, CHEATKEY);
- ReadKey(pathToSounds, SOUNDKEY);
- ReadKey(pathToFirmware, FIRMWAREKEY);
- ReadKey(pathToLua, LUAKEY);
-#ifdef _WINDOWS
- GetPrivateProfileString(SECTION, FORMATKEY, "%f_%s_%r", screenshotFormat, MAX_FORMAT, IniName);
- savelastromvisit = GetPrivateProfileBool(SECTION, LASTVISITKEY, true, IniName);
- currentimageformat = (ImageFormat)GetPrivateProfileInt(SECTION, DEFAULTFORMATKEY, PNG, IniName);
-#endif*/
- /*
- needsSaving = GetPrivateProfileInt(SECTION, NEEDSSAVINGKEY, true, IniName);
- if(needsSaving)
- {
- needsSaving = false;
- WritePathSettings();
- }*/
- /*}*/
-
- void SwitchPath(Action action, KnownPath knownPath, char * buffer)
- {
- char *pathToCopy = 0;
- switch(knownPath)
- {
- case ROMS:
- pathToCopy = pathToRoms;
- break;
- case BATTERY:
- pathToCopy = pathToBattery;
- break;
- case STATES:
- pathToCopy = pathToStates;
- break;
- case SCREENSHOTS:
- pathToCopy = pathToScreenshots;
- break;
- case AVI_FILES:
- pathToCopy = pathToAviFiles;
- break;
- case CHEATS:
- pathToCopy = pathToCheats;
- break;
- case SOUNDS:
- pathToCopy = pathToSounds;
- break;
- case FIRMWARE:
- pathToCopy = pathToFirmware;
- break;
- case MODULE:
- pathToCopy = pathToModule;
- break;
- }
-
- if(action == GET)
- {
- std::string thePath = pathToCopy;
- std::string relativePath = (std::string)"." + DIRECTORY_DELIMITER_CHAR;
-
- int len = (int)thePath.size()-1;
-
- if(len == -1)
- thePath = relativePath;
- else
- if(thePath[len] != DIRECTORY_DELIMITER_CHAR)
- thePath += DIRECTORY_DELIMITER_CHAR;
-
- if(!Path::IsPathRooted(thePath))
- {
- thePath = (std::string)pathToModule + thePath;
- }
-
- strncpy(buffer, thePath.c_str(), MAX_PATH);
- #ifdef _WINDOWS
- FCEUD_MakePathDirs(buffer);
- #endif
- }
- else if(action == SET)
- {
- int len = strlen(buffer)-1;
- if(buffer[len] == DIRECTORY_DELIMITER_CHAR)
- buffer[len] = '\0';
-
- strncpy(pathToCopy, buffer, MAX_PATH);
- }
- }
-
- std::string getpath(KnownPath knownPath)
- {
- char temp[MAX_PATH];
- SwitchPath(GET, knownPath, temp);
- return temp;
- }
-
- void getpath(KnownPath knownPath, char *buffer)
- {
- SwitchPath(GET, knownPath, buffer);
- }
-
- void setpath(KnownPath knownPath, char *buffer)
- {
- SwitchPath(SET, knownPath, buffer);
- }
-
- void getfilename(char *buffer, int)
- {
- strcpy(buffer,noextension().c_str());
- }
-
- void getpathnoext(KnownPath knownPath, char *buffer)
- {
- getpath(knownPath, buffer);
- strcat(buffer, GetRomNameWithoutExtension().c_str());
- }
-
- std::string extension()
- {
- return Path::GetFileExt(path);
- }
-
- std::string noextension()
- {
- std::string romNameWithPath = Path::GetFileDirectoryPath(path) + DIRECTORY_DELIMITER_CHAR + Path::GetFileNameWithoutExt(RomName);
-
- return romNameWithPath;
- }
-
- void formatname(char *output)
- {
- std::string file;
- time_t now = time(NULL);
- tm *time_struct = localtime(&now);
- srand((unsigned int)now);
-
- for(int i = 0; i < MAX_FORMAT;i++)
- {
- char *c = &screenshotFormat[i];
- char tmp[MAX_PATH] = {0};
-
- if(*c == '%')
- {
- c = &screenshotFormat[++i];
- switch(*c)
- {
- case 'f':
-
- strcat(tmp, GetRomNameWithoutExtension().c_str());
- break;
- case 'D':
- strftime(tmp, MAX_PATH, "%d", time_struct);
- break;
- case 'M':
- strftime(tmp, MAX_PATH, "%m", time_struct);
- break;
- case 'Y':
- strftime(tmp, MAX_PATH, "%Y", time_struct);
- break;
- case 'h':
- strftime(tmp, MAX_PATH, "%H", time_struct);
- break;
- case 'm':
- strftime(tmp, MAX_PATH, "%M", time_struct);
- break;
- case 's':
- strftime(tmp, MAX_PATH, "%S", time_struct);
- break;
- case 'r':
- sprintf(tmp, "%d", rand() % RAND_MAX);
- break;
- }
- }
- else
- {
- int j;
- for(j=i;j<MAX_FORMAT-i;j++)
- if(screenshotFormat[j] != '%')
- tmp[j-i]=screenshotFormat[j];
- else
- break;
- tmp[j-i]='\0';
- }
- file += tmp;
- }
- strncpy(output, file.c_str(), MAX_PATH);
- }
-
- enum ImageFormat
- {
-#if defined(_WINDOWS) && !defined(WXPORT)
- PNG = IDC_PNG,
- BMP = IDC_BMP
-#else
- PNG,
- BMP
-#endif
- };
-
- ImageFormat currentimageformat;
-
- ImageFormat imageformat() {
- return currentimageformat;
- }
-
- void SetRomName(const char *filename)
- {
- std::string romPath = filename;
-
- RomName = Path::GetFileNameFromPath(romPath);
- RomDirectory = Path::GetFileDirectoryPath(romPath);
- }
-
- const char *GetRomName()
- {
- return RomName.c_str();
- }
-
- std::string GetRomNameWithoutExtension()
- {
- return Path::GetFileNameWithoutExt(RomName);
- }
-
- bool isdsgba(std::string fileName)
- {
- size_t i = fileName.find_last_of(FILE_EXT_DELIMITER_CHAR);
-
- if (i != std::string::npos) {
- fileName = fileName.substr(i - 2);
- }
-
- if(fileName == "ds.gba") {
- return true;
- }
-
- return false;
- }
-};
-
-extern PathInfo path;
-
--- a/src/in_2sf/desmume/pathsettings.h
+++ /dev/null
@@ -1,30 +1,1 @@
-/*
- Copyright (C) 2007 Hicoder
- This file is part of DeSmuME
-
- DeSmuME is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- DeSmuME is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with DeSmuME; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-
-#ifndef _PATHSETTINGS_H_
-#define _PATHSETTINGS_H_
-
-void WritePathSettings();
-//void ReadPathSettings();
-
-LRESULT CALLBACK PathSettingsDlgProc(HWND hDlg, UINT uMsg, WPARAM wParam, LPARAM lParam);
-
-#endif
-
--- a/src/in_2sf/desmume/readwrite.cpp
+++ b/src/in_2sf/desmume/readwrite.cpp
@@ -18,71 +18,22 @@
#include "readwrite.h"
#include "types.h"
-//well. just for the sake of consistency
-/*int write8le(uint8_t b, EMUFILE*os)
+int read8le(uint8_t *Bufo, EMUFILE *is)
{
- os->fwrite((char*)&b,1);
- return 1;
-}*/
-
-//well. just for the sake of consistency
-int read8le(uint8_t *Bufo, EMUFILE*is)
-{
- if(is->_fread((char*)Bufo,1) != 1)
+ if (is->_fread(Bufo, 1) != 1)
return 0;
return 1;
}
-///writes a little endian 16bit value to the specified file
-/*int write16le(uint16_t b, EMUFILE *fp)
-{
- uint8_t s[2];
- s[0]=(uint8_t)b;
- s[1]=(uint8_t)(b>>8);
- fp->fwrite(s,2);
- return 2;
-}*/
-
-
-///writes a little endian 32bit value to the specified file
-/*int write32le(uint32_t b, EMUFILE *fp)
-{
- uint8_t s[4];
- s[0]=(uint8_t)b;
- s[1]=(uint8_t)(b>>8);
- s[2]=(uint8_t)(b>>16);
- s[3]=(uint8_t)(b>>24);
- fp->fwrite(s,4);
- return 4;
-}*/
-
-//void writebool(bool b, EMUFILE* os) { write32le(b?1:0,os); }
-
-/*int write64le(uint64_t b, EMUFILE* os)
-{
- uint8_t s[8];
- s[0]=(uint8_t)b;
- s[1]=(uint8_t)(b>>8);
- s[2]=(uint8_t)(b>>16);
- s[3]=(uint8_t)(b>>24);
- s[4]=(uint8_t)(b>>32);
- s[5]=(uint8_t)(b>>40);
- s[6]=(uint8_t)(b>>48);
- s[7]=(uint8_t)(b>>56);
- os->fwrite((char*)&s,8);
- return 8;
-}*/
-
-
int read32le(uint32_t *Bufo, EMUFILE *fp)
{
uint32_t buf;
- if(fp->_fread(&buf,4)<4)
+ if (fp->_fread(&buf, 4) < 4)
return 0;
#ifdef LOCAL_LE
- *(uint32_t*)Bufo=buf;
+ *Bufo = buf;
#else
- *(uint32_t*)Bufo=((buf&0xFF)<<24)|((buf&0xFF00)<<8)|((buf&0xFF0000)>>8)|((buf&0xFF000000)>>24);
+ *Bufo = ((buf & 0xFF) << 24) | ((buf & 0xFF00) << 8) | ((buf & 0xFF0000) >> 8) | ((buf & 0xFF000000) >> 24);
#endif
return 1;
}
@@ -90,10 +41,10 @@
int read16le(uint16_t *Bufo, EMUFILE *is)
{
uint16_t buf;
- if(is->_fread((char*)&buf,2) != 2)
+ if (is->_fread(&buf, 2) != 2)
return 0;
#ifdef LOCAL_LE
- *Bufo=buf;
+ *Bufo = buf;
#else
*Bufo = LE_TO_LOCAL_16(buf);
#endif
@@ -103,51 +54,32 @@
int read64le(uint64_t *Bufo, EMUFILE *is)
{
uint64_t buf;
- if(is->_fread((char*)&buf,8) != 8)
+ if (is->_fread(&buf, 8) != 8)
return 0;
#ifdef LOCAL_LE
- *Bufo=buf;
+ *Bufo = buf;
#else
*Bufo = LE_TO_LOCAL_64(buf);
#endif
return 1;
}
-/*static int read32le(uint32_t *Bufo, std::istream *is)
-{
- uint32_t buf;
- if(is->read((char*)&buf,4).gcount() != 4)
- return 0;
-#ifdef LOCAL_LE
- *(uint32_t*)Bufo=buf;
-#else
- *(uint32_t*)Bufo=((buf&0xFF)<<24)|((buf&0xFF00)<<8)|((buf&0xFF0000)>>8)|((buf&0xFF000000)>>24);
-#endif
- return 1;
-}*/
-
-int readbool(bool *b, EMUFILE* is)
+int readbool(bool *b, EMUFILE *is)
{
uint32_t temp = 0;
- int ret = read32le(&temp,is);
- *b = temp!=0;
+ int ret = read32le(&temp, is);
+ *b = !!temp;
return ret;
}
-int readbuffer(std::vector<uint8_t> &vec, EMUFILE* is)
+int readbuffer(std::vector<uint8_t> &vec, EMUFILE *is)
{
uint32_t size;
- if(read32le(&size,is) != 1) return 0;
+ if (read32le(&size, is) != 1)
+ return 0;
vec.resize(size);
- if(size>0) is->fread((char*)&vec[0],size);
+ if (size > 0)
+ is->fread(&vec[0], size);
return 1;
}
-/*int writebuffer(std::vector<uint8_t>& vec, EMUFILE* os)
-{
- uint32_t size = vec.size();
- write32le(size,os);
- if(size>0) os->fwrite((char*)&vec[0],size);
- return 1;
-}*/
-
--- a/src/in_2sf/desmume/readwrite.h
+++ b/src/in_2sf/desmume/readwrite.h
@@ -21,47 +21,27 @@
#include <iostream>
#include <vector>
#include <cstdio>
-
#include "types.h"
#include "emufile.h"
-//well. just for the sake of consistency
-//int write8le(uint8_t b, EMUFILE *fp);
-//inline int write8le(uint8_t* b, EMUFILE *fp) { return write8le(*b,fp); }
-//int write16le(uint16_t b, EMUFILE* os);
-//int write32le(uint32_t b, EMUFILE* os);
-//int write64le(uint64_t b, EMUFILE* os);
-//inline int write_double_le(double b, EMUFILE*is) { uint64_t temp = double_to_u64(b); int ret = write64le(temp,is); return ret; }
-
-int read8le(uint8_t *Bufo, EMUFILE*is);
-int read16le(uint16_t *Bufo, EMUFILE*is);
-inline int read16le(int16_t *Bufo, EMUFILE*is) { return read16le((uint16_t*)Bufo,is); }
-int read32le(uint32_t *Bufo, EMUFILE*is);
-inline int read32le(int32_t *Bufo, EMUFILE*is) { return read32le((uint32_t*)Bufo,is); }
-int read64le(uint64_t *Bufo, EMUFILE*is);
-inline int read_double_le(double *Bufo, EMUFILE*is) { uint64_t temp; int ret = read64le(&temp,is); *Bufo = u64_to_double(temp); return ret; }
+int read8le(uint8_t *Bufo, EMUFILE *is);
+int read16le(uint16_t *Bufo, EMUFILE *is);
+inline int read16le(int16_t *Bufo, EMUFILE *is) { return read16le(reinterpret_cast<uint16_t *>(Bufo), is); }
+int read32le(uint32_t *Bufo, EMUFILE *is);
+inline int read32le(int32_t *Bufo, EMUFILE *is) { return read32le(reinterpret_cast<uint32_t *>(Bufo), is); }
+int read64le(uint64_t *Bufo, EMUFILE *is);
+inline int read_double_le(double *Bufo, EMUFILE *is)
+{
+ uint64_t temp;
+ int ret = read64le(&temp,is);
+ *Bufo = u64_to_double(temp);
+ return ret;
+}
int read16le(uint16_t *Bufo, std::istream *is);
+int readbool(bool *b, EMUFILE *is);
-/*template<typename T>
-int readle(T *Bufo, EMUFILE*is)
-{
- CTASSERT(sizeof(T)==1||sizeof(T)==2||sizeof(T)==4||sizeof(T)==8);
- switch(sizeof(T)) {
- case 1: return read8le((uint8_t*)Bufo,is);
- case 2: return read16le((uint16_t*)Bufo,is);
- case 4: return read32le((uint32_t*)Bufo,is);
- case 8: return read64le((uint64_t*)Bufo,is);
- default:
- return 0;
- }
-}*/
-
-int readbool(bool *b, EMUFILE* is);
-//void writebool(bool b, EMUFILE* os);
-
-int readbuffer(std::vector<uint8_t> &vec, EMUFILE* is);
-//int writebuffer(std::vector<uint8_t>& vec, EMUFILE* os);
+int readbuffer(std::vector<uint8_t> &vec, EMUFILE *is);
#endif
--- a/src/in_2sf/desmume/resource.h
+++ /dev/null
@@ -1,962 +1,1 @@
-//{{NO_DEPENDENCIES}}
-// Microsoft Visual C++ generated include file.
-// Used by resources.rc
-//
-#define IDD_RECORDMOVIE 101
-#define IDM_OPEN 101
-#define IDM_QUIT 102
-#define IDC_FERMER 103
-#define IDD_DESASSEMBLEUR_VIEWER7 103
-#define IDC_STEP 104
-#define IDC_SETPNUM 105
-#define IDC_SCROLLER 106
-#define IDD_SOUNDSETTINGS 106
-#define IDB_FRAMEADVANCE 106
-#define IDC_GO 107
-#define IDC_AUTO_UPDATE 108
-#define IDB_OPEN 108
-#define IDM_MEMORY 109
-#define IDC_CONTINUE 109
-#define IDM_DISASSEMBLER 110
-#define IDB_PAUSE 110
-#define IDD_3DSETTINGS 111
-#define IDM_GAME_INFO 111
-#define IDB_PLAY 112
-#define IDD_GBASLOT 113
-#define IDM_PAUSE 113
-#define IDD_GBASLOT_CFLASH 114
-#define IDM_RESET 114
-#define IDB_RESET 114
-#define IDD_CHEAT_SEARCH_VIEW 115
-#define IDM_IOREG 115
-#define IDD_CHEAT_LIST 116
-#define IDB_STOP 116
-#define IDD_CHEAT_ADD 117
-#define IDM_PAL 117
-#define IDM_TILE 118
-#define IDM_MAP 119
-#define IDB_ROTATECCW 119
-#define IDM_MBG0 120
-#define IDB_BITMAP2 120
-#define IDB_ROTATECW 120
-#define IDM_MBG1 121
-#define IDM_MBG2 122
-#define IDD_CHEAT_EXPORT 122
-#define IDM_MBG3 123
-#define IDM_SBG0 124
-#define IDM_SBG1 125
-#define IDM_SBG2 126
-#define IDM_SBG3 127
-#define IDM_OAM 128
-#define IDM_PRINTSCREEN 129
-#define IDM_QUICK_PRINTSCREEN 130
-#define IDM_SOUNDSETTINGS 131
-#define IDM_WEBSITE 132
-#define IDM_FORUM 133
-#define IDM_SUBMITBUGREPORT 134
-#define IDM_STATE_LOAD 135
-#define IDM_STATE_SAVE 136
-#define IDM_STATE_SAVE_F10 139
-#define IDM_STATE_SAVE_F1 140
-#define IDM_STATE_SAVE_F2 141
-#define IDM_STATE_SAVE_F3 142
-#define IDM_STATE_SAVE_F4 143
-#define IDM_STATE_SAVE_F5 144
-#define IDM_STATE_SAVE_F6 145
-#define IDM_STATE_SAVE_F7 146
-#define IDM_STATE_SAVE_F8 147
-#define IDM_STATE_SAVE_F9 148
-#define IDM_STATE_LOAD_F10 149
-#define IDM_STATE_LOAD_F1 150
-#define IDM_STATE_LOAD_F2 151
-#define IDM_STATE_LOAD_F3 152
-#define IDM_STATE_LOAD_F4 153
-#define IDM_STATE_LOAD_F5 154
-#define IDM_STATE_LOAD_F6 155
-#define IDM_STATE_LOAD_F7 156
-#define IDM_STATE_LOAD_F8 157
-#define IDM_STATE_LOAD_F9 158
-#define IDC_COMBO1 160
-#define IDC_COMBO2 161
-#define IDC_COMBO3 162
-#define IDC_COMBO4 163
-#define IDM_CONFIG 180
-#define IDC_FRAMESKIP0 191
-#define IDC_FRAMESKIP1 192
-#define IDC_FRAMESKIP2 193
-#define IDC_FRAMESKIP3 194
-#define IDC_FRAMESKIP4 195
-#define IDC_FRAMESKIP5 196
-#define IDC_FRAMESKIP6 197
-#define IDC_FRAMESKIP7 198
-#define IDC_FRAMESKIP8 199
-#define IDC_EDIT_FILENAME 200
-#define IDC_FRAMESKIP9 200
-#define IDC_BUTTON_BROWSEFILE 201
-#define IDC_CHECK_READONLY 201
-#define IDM_IMPORTBACKUPMEMORY 201
-#define IDC_LANGENGLISH 210
-#define IDC_LANGFRENCH 211
-#define IDC_LANG_CHINESE_SIMPLIFIED 213
-#define IDC_LANGITALIAN 214
-#define IDC_LANGJAPANESE 215
-#define IDM_MGPU 219
-#define IDM_SGPU 220
-#define IDC_FRAMESKIPAUTO 221
-#define IDC_8_BIT 302
-#define IDC_16_BIT 303
-#define IDC_32_BIT 304
-#define IDC_BACKGROUNDPAUSE 305
-#define IDC_BACKGROUNDINPUT 306
-#define IDC_LUACONSOLE 309
-#define IDC_EDIT_LUAPATH 310
-#define IDC_BUTTON_LUARUN 311
-#define IDC_BUTTON_LUASTOP 312
-#define IDC_BUTTON_LUABROWSE 313
-#define IDC_BUTTON_LUAEDIT 314
-#define IDC_NOTIFY_SUBSERVIENT 315
-#define IDD_ARCHIVEFILECHOOSER 316
-#define IDD_LUA 317
-#define IDC_NEW_LUA_SCRIPT 318
-#define IDC_PATHEDIT 319
-#define IDC_BROWSE 320
-#define IDC_USELASTVISIT 321
-#define IDC_FORMATEDIT 322
-#define IDC_PATHLIST 323
-#define IDC_SAVEAS 324
-#define IDC_PNG 325
-#define IDC_BMP 326
-#define IDC_FORMATSTATIC 327
-#define IDM_CLOSEROM 328
-#define IDM_PATHSETTINGS 350
-#define IDC_ROMPATHEDIT 351
-#define IDC_BROWSEROMS 352
-#define IDC_PATHDEFAULTS 353
-#define IDC_SAVERAMPATHEDIT 354
-#define IDC_BROWSESRAM 355
-#define IDC_STATEPATHEDIT 356
-#define IDC_BROWSESTATES 357
-#define IDC_SCREENSHOTPATHEDIT 358
-#define IDC_BROWSESCREENSHOTS 359
-#define IDC_AVIPATHEDIT 360
-#define IDC_BROWSEAVI 361
-#define IDC_CHEATPATHEDIT 362
-#define IDC_BROWSECHEATS 363
-#define IDC_LUAPATHEDIT 364
-#define IDC_BROWSELUA 365
-#define IDD_PATHSETTINGS 366
-#define IDC_STATEREWINDING 367
-#define IDC_CLOSE_LUA_SCRIPTS 368
-#define IDC_DES_BOX 402
-#define IDC_R0 403
-#define IDC_R1 404
-#define IDC_R2 405
-#define IDC_R3 406
-#define IDC_R4 407
-#define IDC_R5 408
-#define IDC_R6 409
-#define IDC_R7 410
-#define IDC_R8 411
-#define IDC_R9 412
-#define IDC_R10 413
-#define IDC_R11 414
-#define IDC_R12 415
-#define IDC_R13 416
-#define IDC_R14 417
-#define IDC_R15 418
-#define IDC_MODE 419
-#define IDC_AUTO_DES 420
-#define IDC_ARM 421
-#define IDC_THUMB 422
-#define IDC_GOTODES 423
-#define IDC_TMP 424
-#define IDD_GAME_INFO 501
-#define ID_RAM_WATCH 550
-#define IDM_RENDER_NORMAL 551
-#define IDM_RENDER_HQ2X 552
-#define IDM_RENDER_2XSAI 553
-#define IDM_RENDER_SUPER2XSAI 554
-#define IDM_RENDER_SUPEREAGLE 555
-#define IDM_RENDER_SCANLINE 556
-#define IDM_RENDER_BILINEAR 557
-#define IDM_RENDER_NEAREST2X 558
-#define IDM_RENDER_EPX 559
-#define IDM_RENDER_EPXPLUS 560
-#define IDM_RENDER_EPX1POINT5 561
-#define IDM_RENDER_EPXPLUS1POINT5 562
-#define IDM_RENDER_NEAREST1POINT5 563
-#define IDM_RENDER_NEARESTPLUS1POINT5 564
-#define IDD_IO_REG 601
-#define IDM_RECORD_MOVIE 602
-#define IDM_PLAY_MOVIE 603
-#define IDD_PAL 703
-#define IDD_TILE 704
-#define IDC_PAL_SELECT 705
-#define IDC_PALNUM 706
-#define IDC_MEM_SELECT 707
-#define IDC_Tile_BOX 708
-#define IDC_BITMAP 709
-#define IDC_256COUL 710
-#define IDC_16COUL 711
-#define IDC_MINI_TILE 712
-#define IDC_TILENUM 713
-#define IDD_MAP 800
-#define IDC_BG_SELECT 801
-#define IDC_PAL 803
-#define IDC_PRIO 804
-#define IDC_CHAR 805
-#define IDC_SCR 806
-#define IDC_MSIZE 807
-#define IDC_SCROLL 808
-#define IDD_OAM 900
-#define IDC_SCR_SELECT 901
-#define IDC_TILE 902
-#define IDC_OAMNUM 903
-#define IDC_COOR 904
-#define IDC_DIM 905
-#define IDC_ROT 906
-#define IDC_MOS 907
-#define IDC_PROP0 908
-#define IDC_PROP1 909
-#define IDD_EMULATIONSETTINGS 916
-#define IDD_WIFISETTINGS 918
-#define IDD_MEM_VIEW 920
-#define IDC_DIFFERENTFROM 921
-#define IDC_DIFFERENTBY 922
-#define IDC_MODULO 923
-#define IDC_EDIT_DIFFBY 924
-#define IDC_EDIT_MODBY 925
-#define IDC_PREVIOUSVALUE 926
-#define IDC_SPECIFICVALUE 927
-#define IDC_NUMBEROFCHANGES 928
-#define IDC_EDIT_COMPAREVALUE 929
-#define IDC_EDIT_COMPARECHANGES 930
-#define IDC_C_AUTOSEARCH 931
-#define IDC_MISALIGN 932
-#define IDC_C_RESET_CHANGES 933
-#define IDC_C_UNDO 934
-#define ID_RAM_SEARCH 935
-#define IDD_RAMSEARCH 945
-#define IDC_SPECIFICADDRESS 950
-#define IDC_EDIT_COMPAREADDRESS 951
-#define IDC_PROMPT_TEXT 952
-#define IDC_PROMPT_EDIT 953
-#define IDC_SIGNED 954
-#define IDC_UNSIGNED 955
-#define IDC_HEX 956
-#define IDC_1_BYTE 957
-#define IDC_2_BYTES 958
-#define IDC_4_BYTES 959
-#define IDC_WATCHLIST 960
-#define IDC_HEX2 960
-#define IDC_C_WATCH_EDIT 961
-#define IDC_C_WATCH_REMOVE 962
-#define IDC_C_WATCH 963
-#define IDC_C_WATCH_DUPLICATE 964
-#define IDC_C_ADDCHEAT 965
-#define ID_WATCHES_UPDOWN 966
-#define IDD_RAMWATCH 967
-#define IDC_C_WATCH_DUPLICATE2 967
-#define IDC_C_WATCH_SEPARATE 967
-#define IDR_ACCELERATOR1 968
-#define IDD_PROMPT 969
-#define ID_VIEW_DISPLAYGRAPHICALINPUT 971
-#define IDD_SOUND_VIEW 977
-#define IDC_START_FROM_SRAM 978
-#define IDC_EDIT_SRAMFILENAME 979
-#define IDC_BUTTON_BROWSESRAM 980
-#define IDC_C_WATCH_UP 980
-#define IDD_EDITWATCH 980
-#define IDC_C_WATCH_DOWN 981
-#define RAMMENU_FILE_AUTOLOAD 982
-#define RAMMENU_FILE_SAVEWINDOW 983
-#define RAMMENU_FILE_SAVE 984
-#define RAMMENU_FILE_SAVEAS 985
-#define RAMMENU_FILE_OPEN 986
-#define RAMMENU_FILE_APPEND 987
-#define RAMMENU_FILE_NEW 988
-#define RAMMENU_FILE_RECENT 990
-#define IDC_RAMLIST 991
-#define IDC_C_SEARCH 992
-#define IDC_C_RESET 993
-#define IDC_C_ELIMINATE 994
-#define IDC_LESSTHAN 995
-#define IDC_MORETHAN 996
-#define IDC_NOMORETHAN 997
-#define IDC_NOLESSTHAN 998
-#define IDC_EQUALTO 999
-#define IDC_BRIDGEADAPTER 1000
-#define IDC_SOUNDCORECB 1000
-#define IDC_USEEXTBIOS 1000
-#define ID_BROWSE 1000
-#define IDC_CHECKBOX_DEBUGGERMODE 1001
-#define IDC_SOUNDBUFFERET 1001
-#define IDC_SOUNDVIEW_CHANSWITCH 1001
-#define PM_FILENAME 1001
-#define IDC_ARM9BIOS 1002
-#define IDC_MLENGTH 1002
-#define IDC_SLVOLUME 1002
-#define IDC_GI_GAMETITLE 1003
-#define IDC_MFRAMES 1003
-#define IDC_ROTATE0 1003
-#define IDC_BUTTON2 1003
-#define IDC_CHECKBOX_ENSATAEMULATION 1003
-#define IDC_ARM9BIOSBROWSE 1004
-#define IDC_GI_GAMECODE 1004
-#define IDC_MRERECORDCOUNT 1004
-#define IDC_ROTATE90 1004
-#define IDC_SPU_INTERPOLATION_CB 1004
-#define IDC_BUTTON_VOLMODE 1004
-#define IDC_ARM7BIOS 1005
-#define IDC_MROM 1005
-#define IDC_ROTATE180 1005
-#define IDC_GGREEN 1005
-#define IDC_ROTATE270 1006
-#define IDC_GRED 1006
-#define IDC_WIFIMODE0 1006
-#define IDC_ARM7BIOSBROWSE 1007
-#define IDC_GYELLOW 1007
-#define IDC_WIFIMODE1 1007
-#define IDC_MEMVIEWBOX 1008
-#define IDC_GBLUE 1008
-#define IDC_ADHOC_SERVER 1008
-#define IDC_ADDRESS 1009
-#define IDC_BIOSSWIS 1009
-#define IDC_FORCERATIO 1009
-#define IDC_ADHOC_CLIENT 1009
-#define IDC_AUTO_UPDATE_SPIN 1010
-#define IDC_TEXTDUMP 1010
-#define IDC_WINDOW1X 1010
-#define IDC_ADHOC_SERVERNAME 1010
-#define IDC_AUTO_UPDATE_SECS 1011
-#define IDC_USEEXTFIRMWARE 1011
-#define IDC_WINDOW2X 1011
-#define IDC_FIRMWARE 1012
-#define IDC_RAWDUMP 1012
-#define IDC_REFRESH 1012
-#define IDC_WINDOW3X 1012
-#define IDC_SYNCHMODE_DUAL 1012
-#define IDC_WINDOW4X 1013
-#define IDC_VIEWMODE 1013
-#define IDC_SYNCHMODE_SYNCH 1013
-#define IDC_FIRMWAREBROWSE 1014
-#define IDC_VOLUME 1014
-#define IDC_DUMPALL 1014
-#define IDC_SYNCHMETHOD_N 1015
-#define IDC_FIRMWAREBOOT 1016
-#define IDC_SYNCHMETHOD_Z 1016
-#define IDC_GROUP_SYNCHMETHOD 1017
-#define IDC_AUTOUPDATE_ASM 1018
-#define IDC_SYNCHMETHOD_P 1018
-#define IDC_VISIBLE 1019
-#define IDC_USEPHYSICAL 1019
-#define IDC_SPLIT1 1021
-#define IDC_PATCHSWI3 1022
-#define IDC_CAP0_ADD 1023
-#define IDC_CAP0_CURDAD 1024
-#define IDC_CAP1_ADD 1025
-#define IDC_SPU_ADVANCED 1025
-#define IDC_CAP1_CURDAD 1026
-#define IDC_CHECBOX_ADVANCEDTIMING 1026
-#define IDC_DEFAULT 1027
-#define IDC_DTP_DATE 1027
-#define IDC_3DCORE 1028
-#define IDC_SNDCTRL_ENABLE 1028
-#define IDC_DTP_TIME 1028
-#define IDC_TXT_COMPILED 1029
-#define IDC_SNDCTRL_CH1NOMIX 1029
-#define IDC_TXT_VERSION 1030
-#define IDC_SNDCTRL_CH3NOMIX 1030
-#define IDC_SOUND_CAPTURE_MUTED 1031
-#define IDC_SOUND_ANALYZE_CAP 1032
-#define IDC_ADDONS_LIST 1033
-#define IDC_BUTTON3 1033
-#define IDC_SOUND_UNMUTE_ALL 1033
-#define IDC_PIANO_C 1033
-#define IDC_ADDONS_INFO 1034
-#define IDC_BORDER 1034
-#define IDC_PIANO_CS 1034
-#define IDC_BBROWSE 1035
-#define IDC_PIANO_D 1035
-#define IDC_PATHIMG 1036
-#define IDC_PIANO_DS 1036
-#define IDC_PATH 1037
-#define IDC_PATHGAME 1037
-#define IDC_PIANO_E 1037
-#define IDC_LIST_CHEATS 1037
-#define IDC_RFILE 1038
-#define IDC_EXPORT 1038
-#define IDC_RFOLDER 1039
-#define IDC_2012 1039
-#define IDC_BBROWSE2 1040
-#define IDC_PATHDESMUME 1041
-#define IDC_BRESTART 1042
-#define IDC_BVIEW 1043
-#define IDC_BSEARCH 1044
-#define IDC_PIANO_F 1044
-#define IDC_RADIO1 1045
-#define IDC_PIANO_FS 1045
-#define IDC_RADIO2 1046
-#define IDC_PIANO_GS 1046
-#define IDC_RADIO3 1047
-#define IDC_PIANO_B 1047
-#define IDC_RADIO4 1048
-#define IDC_PIANO_A 1048
-#define IDC_RADIO5 1049
-#define IDC_PIANO_AS 1049
-#define IDC_RADIO6 1050
-#define IDC_PIANO_G 1050
-#define IDC_RADIO7 1051
-#define IDC_PIANO_DS3 1051
-#define IDC_PIANO_HIC 1051
-#define IDC_RADIO8 1052
-#define IDC_LIST1 1056
-#define IDC_BADD_AR 1057
-#define IDC_BADD_CB 1058
-#define IDC_BREMOVE 1060
-#define IDC_BEDIT 1061
-#define IDC_STATIC_S1 1061
-#define IDC_STATIC_S2 1062
-#define IDC_STATIC_S3 1063
-#define IDC_STATIC_S4 1064
-#define IDC_EVALUE 1065
-#define IDC_STATIC_RANGE 1066
-#define IDC_BADD 1068
-#define IDC_LIST 1069
-#define IDC_SNUMBER 1071
-#define IDC_CHECK1 1074
-#define IDC_CHECK2 1075
-#define IDC_CAP0_SRC 1075
-#define IDC_CHECK3 1076
-#define IDC_CAP0_ONESHOT 1076
-#define IDC_CHECK4 1077
-#define IDC_CAP0_TYPE 1077
-#define IDC_CAP0_ACTIVE 1078
-#define IDC_CHECK10 1079
-#define IDC_CAP0_RUNNING 1079
-#define IDC_CHECK6 1080
-#define IDC_CAP1_SRC 1080
-#define IDC_CAP1_ONESHOT 1081
-#define IDC_CHECK7 1082
-#define IDC_CAP1_TYPE 1082
-#define IDC_CHECK8 1083
-#define IDC_CAP1_ACTIVE 1083
-#define IDC_CAP1_RUNNING 1084
-#define IDC_CHECK9 1088
-#define IDC_S2X 1090
-#define IDC_S4X 1091
-#define IDC_S8X 1092
-#define IDC_S16X 1093
-#define IDM_FIRMSETTINGS 1100
-#define IDD_FIRMSETTINGS 1101
-#define IDC_EDIT1 1102
-#define IDC_EDIT2 1103
-#define IDC_EDIT3 1104
-#define IDC_EDIT_AUTHOR 1180
-#define IDD_MATRIX_VIEWER 1200
-#define IDM_MATRIX_VIEWER 1200
-#define IDC_MATRIX_VIEWER_COORD_GROUP 1201
-#define IDC_MATRIX_VIEWER_COORD_COMBO 1202
-#define IDC_MATRIX_VIEWER_COORD_11_EDIT 1203
-#define IDC_MATRIX_VIEWER_COORD_12_EDIT 1204
-#define IDC_MATRIX_VIEWER_COORD_13_EDIT 1205
-#define IDC_MATRIX_VIEWER_COORD_14_EDIT 1206
-#define IDC_MATRIX_VIEWER_COORD_21_EDIT 1207
-#define IDC_MATRIX_VIEWER_COORD_22_EDIT 1208
-#define IDC_MATRIX_VIEWER_COORD_23_EDIT 1209
-#define IDC_MATRIX_VIEWER_COORD_24_EDIT 1210
-#define IDC_MATRIX_VIEWER_COORD_31_EDIT 1211
-#define IDC_MATRIX_VIEWER_COORD_32_EDIT 1212
-#define IDC_MATRIX_VIEWER_COORD_33_EDIT 1213
-#define IDC_MATRIX_VIEWER_COORD_34_EDIT 1214
-#define IDC_MATRIX_VIEWER_COORD_41_EDIT 1215
-#define IDC_MATRIX_VIEWER_COORD_42_EDIT 1216
-#define IDC_MATRIX_VIEWER_COORD_43_EDIT 1217
-#define IDC_MATRIX_VIEWER_COORD_44_EDIT 1218
-#define IDC_MATRIX_VIEWER_DIR_GROUP 1221
-#define IDC_MATRIX_VIEWER_DIR_COMBO 1222
-#define IDC_MATRIX_VIEWER_DIR_11_EDIT 1223
-#define IDC_MATRIX_VIEWER_DIR_12_EDIT 1224
-#define IDC_MATRIX_VIEWER_DIR_13_EDIT 1225
-#define IDC_MATRIX_VIEWER_DIR_14_EDIT 1226
-#define IDC_MATRIX_VIEWER_DIR_21_EDIT 1227
-#define IDC_MATRIX_VIEWER_DIR_22_EDIT 1228
-#define IDC_MATRIX_VIEWER_DIR_23_EDIT 1229
-#define IDC_MATRIX_VIEWER_DIR_24_EDIT 1230
-#define IDC_MATRIX_VIEWER_DIR_31_EDIT 1231
-#define IDC_MATRIX_VIEWER_DIR_32_EDIT 1232
-#define IDC_MATRIX_VIEWER_DIR_33_EDIT 1233
-#define IDC_MATRIX_VIEWER_DIR_34_EDIT 1234
-#define IDC_MATRIX_VIEWER_DIR_41_EDIT 1235
-#define IDC_MATRIX_VIEWER_DIR_42_EDIT 1236
-#define IDC_MATRIX_VIEWER_DIR_43_EDIT 1237
-#define IDC_MATRIX_VIEWER_DIR_44_EDIT 1238
-#define IDC_MATRIX_VIEWER_PROJ_GROUP 1241
-#define IDC_MATRIX_VIEWER_PROJ_11_EDIT 1243
-#define IDC_MATRIX_VIEWER_PROJ_12_EDIT 1244
-#define IDC_MATRIX_VIEWER_PROJ_13_EDIT 1245
-#define IDC_MATRIX_VIEWER_PROJ_14_EDIT 1246
-#define IDC_MATRIX_VIEWER_PROJ_21_EDIT 1247
-#define IDC_MATRIX_VIEWER_PROJ_22_EDIT 1248
-#define IDC_MATRIX_VIEWER_PROJ_23_EDIT 1249
-#define IDC_MATRIX_VIEWER_PROJ_24_EDIT 1250
-#define IDC_MATRIX_VIEWER_PROJ_31_EDIT 1251
-#define IDC_MATRIX_VIEWER_PROJ_32_EDIT 1252
-#define IDC_MATRIX_VIEWER_PROJ_33_EDIT 1253
-#define IDC_MATRIX_VIEWER_PROJ_34_EDIT 1254
-#define IDC_MATRIX_VIEWER_PROJ_41_EDIT 1255
-#define IDC_MATRIX_VIEWER_PROJ_42_EDIT 1256
-#define IDC_MATRIX_VIEWER_PROJ_43_EDIT 1257
-#define IDC_MATRIX_VIEWER_PROJ_44_EDIT 1258
-#define IDC_MATRIX_VIEWER_TEX_GROUP 1261
-#define IDC_MATRIX_VIEWER_TEX_11_EDIT 1263
-#define IDC_MATRIX_VIEWER_TEX_12_EDIT 1264
-#define IDC_MATRIX_VIEWER_TEX_13_EDIT 1265
-#define IDC_MATRIX_VIEWER_TEX_14_EDIT 1266
-#define IDC_MATRIX_VIEWER_TEX_21_EDIT 1267
-#define IDC_MATRIX_VIEWER_TEX_22_EDIT 1268
-#define IDC_MATRIX_VIEWER_TEX_23_EDIT 1269
-#define IDC_MATRIX_VIEWER_TEX_24_EDIT 1270
-#define IDC_MATRIX_VIEWER_TEX_31_EDIT 1271
-#define IDC_MATRIX_VIEWER_TEX_32_EDIT 1272
-#define IDC_MATRIX_VIEWER_TEX_33_EDIT 1273
-#define IDC_MATRIX_VIEWER_TEX_34_EDIT 1274
-#define IDC_MATRIX_VIEWER_TEX_41_EDIT 1275
-#define IDC_MATRIX_VIEWER_TEX_42_EDIT 1276
-#define IDC_MATRIX_VIEWER_TEX_43_EDIT 1277
-#define IDC_MATRIX_VIEWER_TEX_44_EDIT 1278
-#define IDD_LIGHT_VIEWER 1300
-#define IDM_LIGHT_VIEWER 1300
-#define IDC_LIGHT_VIWER_LIGHT0_GROUP 1301
-#define IDD_ABOUT_BOX 1301
-#define IDC_AUTHORS_LIST 1302
-#define IDC_LIGHT_VIEWER_LIGHT0COLOR_COLORCTRL 1302
-#define IDD_DESASSEMBLEUR_VIEWER9 1302
-#define IDC_LIGHT_VIEWER_LIGHT0COLOR_EDIT 1303
-#define IDC_LIGHT_VIEWER_LIGHT0VECTOR_EDIT 1304
-#define IDD_GBASLOT_NONE 1304
-#define IDD_GBASLOT_RUMBLEPAK 1305
-#define IDD_GBASLOT_GBAGAME 1306
-#define IDD_CHEAT_SEARCH_COMP 1307
-#define IDD_CHEAT_SEARCH_MAIN 1308
-#define IDD_CHEAT_SEARCH_RESULT 1310
-#define IDC_LIGHT_VIWER_LIGHT1_GROUP 1311
-#define IDD_CHEAT_SEARCH_EXACT 1311
-#define IDC_LIGHT_VIEWER_LIGHT1COLOR_COLORCTRL 1312
-#define IDD_CHEAT_SEARCH 1312
-#define IDC_LIGHT_VIEWER_LIGHT1COLOR_EDIT 1313
-#define IDC_LIGHT_VIEWER_LIGHT1VECTOR_EDIT 1314
-#define IDC_LIGHT_VIWER_LIGHT2_GROUP 1321
-#define IDC_LIGHT_VIEWER_LIGHT2COLOR_COLORCTRL 1322
-#define IDC_LIGHT_VIEWER_LIGHT2COLOR_EDIT 1323
-#define IDC_LIGHT_VIEWER_LIGHT2VECTOR_EDIT 1324
-#define IDC_LIGHT_VIWER_LIGHT3_GROUP 1331
-#define IDC_LIGHT_VIEWER_LIGHT3COLOR_COLORCTRL 1332
-#define IDC_LIGHT_VIEWER_LIGHT3COLOR_EDIT 1333
-#define IDC_LIGHT_VIEWER_LIGHT3VECTOR_EDIT 1334
-#define IDC_SOUND0ID 1350
-#define IDC_SOUND1ID 1351
-#define IDC_SOUND2ID 1352
-#define IDC_SOUND3ID 1353
-#define IDC_SOUND4ID 1354
-#define IDC_SOUND5ID 1355
-#define IDC_SOUND6ID 1356
-#define IDC_SOUND7ID 1357
-#define IDC_SOUND0VOL 1358
-#define IDC_SOUND1VOL 1359
-#define IDC_SOUND2VOL 1360
-#define IDC_SOUND3VOL 1361
-#define IDC_SOUND4VOL 1362
-#define IDC_SOUND5VOL 1363
-#define IDC_SOUND6VOL 1364
-#define IDC_SOUND7VOL 1365
-#define IDC_SOUND0VOLBAR 1366
-#define IDC_SOUND1VOLBAR 1367
-#define IDC_SOUND2VOLBAR 1368
-#define IDC_SOUND3VOLBAR 1369
-#define IDC_SOUND4VOLBAR 1370
-#define IDC_SOUND5VOLBAR 1371
-#define IDC_SOUND6VOLBAR 1372
-#define IDC_SOUND7VOLBAR 1373
-#define IDC_SOUND0PAN 1374
-#define IDC_SOUND1PAN 1375
-#define IDC_SOUND2PAN 1376
-#define IDC_SOUND3PAN 1377
-#define IDC_SOUND4PAN 1378
-#define IDC_SOUND5PAN 1379
-#define IDC_SOUND6PAN 1380
-#define IDC_SOUND7PAN 1381
-#define IDC_SOUND0PANBAR 1382
-#define IDC_SOUND1PANBAR 1383
-#define IDC_SOUND2PANBAR 1384
-#define IDC_SOUND3PANBAR 1385
-#define IDC_SOUND4PANBAR 1386
-#define IDC_SOUND5PANBAR 1387
-#define IDC_SOUND6PANBAR 1388
-#define IDC_SOUND7PANBAR 1389
-#define IDC_SOUND0HOLD 1390
-#define IDC_SOUND1HOLD 1391
-#define IDC_SOUND2HOLD 1392
-#define IDC_SOUND3HOLD 1393
-#define IDC_SOUND4HOLD 1394
-#define IDC_SOUND5HOLD 1395
-#define IDC_SOUND6HOLD 1396
-#define IDC_SOUND7HOLD 1397
-#define IDC_SOUND0BUSY 1398
-#define IDC_SOUND1BUSY 1399
-#define IDC_SOUND2BUSY 1400
-#define IDC_SOUND3BUSY 1401
-#define IDC_SOUND4BUSY 1402
-#define IDC_SOUND5BUSY 1403
-#define IDC_SOUND6BUSY 1404
-#define IDC_SOUND7BUSY 1405
-#define IDC_SOUND0REPEATMODE 1406
-#define IDC_SOUND1REPEATMODE 1407
-#define IDC_SOUND2REPEATMODE 1408
-#define IDC_SOUND3REPEATMODE 1409
-#define IDC_SOUND4REPEATMODE 1410
-#define IDC_SOUND5REPEATMODE 1411
-#define IDC_SOUND6REPEATMODE 1412
-#define IDC_SOUND7REPEATMODE 1413
-#define IDC_SOUND0FORMAT 1414
-#define IDC_SOUND1FORMAT 1415
-#define IDC_SOUND2FORMAT 1416
-#define IDC_SOUND3FORMAT 1417
-#define IDC_SOUND4FORMAT 1418
-#define IDC_SOUND5FORMAT 1419
-#define IDC_SOUND6FORMAT 1420
-#define IDC_SOUND7FORMAT 1421
-#define IDC_SOUND0SAD 1422
-#define IDC_SOUND1SAD 1423
-#define IDC_SOUND2SAD 1424
-#define IDC_SOUND3SAD 1425
-#define IDC_SOUND4SAD 1426
-#define IDC_SOUND5SAD 1427
-#define IDC_SOUND6SAD 1428
-#define IDC_SOUND7SAD 1429
-#define IDC_SOUND0PNT 1430
-#define IDC_SOUND1PNT 1431
-#define IDC_SOUND2PNT 1432
-#define IDC_SOUND3PNT 1433
-#define IDC_SOUND4PNT 1434
-#define IDC_SOUND5PNT 1435
-#define IDC_SOUND6PNT 1436
-#define IDC_SOUND7PNT 1437
-#define IDC_SOUND0TMR 1438
-#define IDC_SOUND1TMR 1439
-#define IDC_SOUND2TMR 1440
-#define IDC_SOUND3TMR 1441
-#define IDC_SOUND4TMR 1442
-#define IDC_SOUND5TMR 1443
-#define IDC_SOUND6TMR 1444
-#define IDC_SOUND7TMR 1445
-#define IDC_SOUND0POSLEN 1446
-#define IDC_SOUND1POSLEN 1447
-#define IDC_SOUND2POSLEN 1448
-#define IDC_SOUND3POSLEN 1449
-#define IDC_SOUND4POSLEN 1450
-#define IDC_SOUND5POSLEN 1451
-#define IDC_SOUND6POSLEN 1452
-#define IDC_SOUND7POSLEN 1453
-#define IDC_CAP0_DAD 1454
-#define IDC_CAP0_CTRL 1455
-#define IDC_CAP0_SRCTEXT 1456
-#define IDC_CAP0_TYPETEXT 1457
-#define IDC_CAP0_LEN 1458
-#define IDC_SOUND0POSLEN7 1459
-#define IDC_CAP1_DAD 1459
-#define IDC_CAP1_CTRL 1460
-#define IDC_CAP1_SRCTEXT 1461
-#define IDC_CAP1_TYPETEXT 1462
-#define IDC_CAP1_LEN 1463
-#define IDC_SNDCTRL_CTRL 1464
-#define IDC_SNDCTRL_VOL 1465
-#define IDC_SNDCTRL_BIAS 1466
-#define IDC_SNDCTRL_LEFTOUT 1467
-#define IDC_SNDCTRL_LEFTOUTTEXT 1468
-#define IDC_SNDCTRL_RIGHTOUT 1469
-#define IDC_SNDCTRL_RIGHTOUTTEXT 1470
-#define IDC_SOUND0MUTE 2001
-#define IDC_SOUND1MUTE 2002
-#define IDC_SOUND2MUTE 2003
-#define IDC_SOUND3MUTE 2004
-#define IDC_SOUND4MUTE 2005
-#define IDC_SOUND5MUTE 2006
-#define IDC_SOUND6MUTE 2007
-#define IDC_SOUND7MUTE 2008
-#define ICONDESMUME 2009
-#define IDD_REPLAYINP 2010
-#define IDD_REPLAY_METADATA 2011
-#define MENU_PRINCIPAL 2012
-#define RAMWATCH_MENU 2013
-#define RECENTROMS 2014
-#define IDC_GI_FATOFS 4464
-#define IDC_INTERPOLATECOLOR 4464
-#define IDC_GI_FATSIZE 4465
-#define IDC_3DSETTINGS_EDGEMARK 4465
-#define ID_LABEL_HK1 4465
-#define IDC_GI_ICONTITLEOFS 4466
-#define IDC_3DSETTINGS_FOG 4466
-#define ID_LABEL_HK2 4466
-#define IDC_GI_USEDROMSIZE 4467
-#define ID_LABEL_HK3 4467
-#define IDC_3DSETTINGS_FOG2 4467
-#define IDC_3DSETTINGS_TEXTURE 4467
-#define ID_LABEL_HK4 4468
-#define IDC_GI_ICON 4469
-#define ID_LABEL_HK5 4469
-#define IDC_GI_TITLE 4470
-#define ID_LABEL_HK6 4470
-#define IDC_GI_TITLEEN 4471
-#define ID_LABEL_HK7 4471
-#define IDC_GI_TITLEFR 4472
-#define ID_LABEL_HK8 4472
-#define IDC_GI_TITLEGE 4473
-#define ID_LABEL_HK9 4473
-#define IDC_GI_TITLEIT 4474
-#define ID_LABEL_HK10 4474
-#define IDC_GI_TITLESP 4475
-#define ID_LABEL_HK11 4475
-#define IDC_GI_MAKERCODE 4476
-#define ID_LABEL_HK12 4476
-#define IDC_GI_TITLEJP 4477
-#define ID_LABEL_HK13 4477
-#define IDC_GI_CHIPSIZE 4478
-#define ID_LABEL_HK14 4478
-#define IDC_GI_ARM9START 4479
-#define ID_LABEL_HK15 4479
-#define IDC_GI_ARM9ENTRY 4480
-#define ID_LABEL_HK16 4480
-#define IDC_GI_ARM9ROM 4481
-#define ID_LABEL_HK17 4481
-#define IDC_GI_ARM9SIZE 4482
-#define ID_LABEL_HK18 4482
-#define IDC_GI_ARM7ROM 4483
-#define ID_LABEL_HK19 4483
-#define IDC_GI_ARM7ENTRY 4484
-#define ID_LABEL_HK20 4484
-#define IDC_GI_ARM7START 4485
-#define ID_LABEL_HK21 4485
-#define IDC_GI_ARM7SIZE 4486
-#define ID_LABEL_HK22 4486
-#define IDC_GI_FNTOFS 4487
-#define ID_LABEL_HK23 4487
-#define IDC_GI_FNTSIZE 4488
-#define ID_LABEL_HK24 4488
-#define ID_LABEL_HK25 4489
-#define ID_LABEL_HK26 4490
-#define ID_LABEL_HK27 4491
-#define ID_LABEL_HK28 4492
-#define ID_LABEL_HK29 4493
-#define ID_LABEL_HK30 4494
-#define ID_LABEL_HK31 4495
-#define ID_LABEL_HK32 4496
-#define ID_LABEL_HK33 4497
-#define ID_LABEL_HK34 4498
-#define ID_LABEL_HK35 4499
-#define ID_LABEL_HK36 4500
-#define ID_LABEL_HK37 4501
-#define ID_LABEL_HK38 4502
-#define ID_LABEL_HK39 4503
-#define ID_LABEL_HK40 4504
-#define ID_LABEL_HK41 4505
-#define ID_LABEL_HK42 4506
-#define ID_LABEL_HK43 4507
-#define ID_LABEL_HK44 4508
-#define ID_LABEL_HK45 4509
-#define ID_LABEL_HK46 4510
-#define ID_LABEL_HK47 4511
-#define ID_LABEL_HK48 4512
-#define ID_LABEL_HK49 4513
-#define ID_LABEL_HK50 4514
-#define ID_LABEL_HK51 4515
-#define ID_LABEL_HK52 4516
-#define ID_LABEL_HK53 4517
-#define ID_LABEL_HK13b 4518
-#define ID_LABEL_HK54 4519
-#define IDD_MICROPHONE 5000
-#define IDM_MICROPHONESETTINGS 5001
-#define IDC_MICSAMPLEBROWSE 5003
-#define IDC_MICSAMPLE 5004
-#define IDC_USEMICSAMPLE 5005
-#define IDC_USEMICRAND 5009
-#define IDC_USENOISE 5010
-#define IDC_CPU 6000
-#define IDC_IOREG 6001
-#define ID_LABEL_ZELDA_SHADOW_DEPTH_HACK 9000
-#define IDC_ZELDA_SHADOW_DEPTH_HACK 9001
-#define IDD_CHEAT_ADD_XX_CODE 10005
-#define IDD_GBASLOT_GUITARGRIP 10009
-#define IDD_GBASLOT_PIANO 10010
-#define IDM_FILE_STOPAVI 40000
-#define IDM_SCREENSEP_NONE 40000
-#define IDM_FILE_STOPWAV 40001
-#define IDM_SCREENSEP_BORDER 40001
-#define IDM_SCREENSEP_NDSGAP 40002
-#define IDM_ABOUT 40003
-#define IDM_EMULATIONSETTINGS 40004
-#define IDC_FRAMELIMIT 40005
-#define ID_CONFIG_PAUSEWHENFOCUSLOST 40005
-#define IDC_WINDOW1_5X 40006
-#define IDM_WIFISETTINGS 40007
-#define IDM_ALWAYS_ON_TOP 40008
-#define ID_VIEW_FRAMECOUNTER 40009
-#define ID_VIEW_DISPLAYFPS 40010
-#define ID_VIEW_DISPLAYINPUT 40011
-#define ID_VIEW_DISPLAYLAG 40012
-#define ID_VIEW_HUDEDITOR 40013
-#define ID_VIEW_DISPLAYMICROPHONE 40014
-#define IDM_FILE_RECORDAVI 40015
-#define IDM_SOUND_VIEW 40016
-#define IDM_FILE_RECORDWAV 40017
-#define IDM_EXPORTBACKUPMEMORY 40018
-#define IDM_STOPMOVIE 40019
-#define IDM_SCREENSEP_NDSGAP2 40021
-#define IDM_SCREENSEP_DRAGEDIT 40022
-#define IDM_SCREENSEP_COLORWHITE 40023
-#define IDM_SCREENSEP_COLORGRAY 40024
-#define IDM_SCREENSEP_COLORBLACK 40025
-#define IDM_FILE_RECORDUSERSPUWAV 40026
-#define ID_FILE_RECENTROM 40034
-#define IDM_DEFSIZE 40038
-#define IDM_3DCONFIG 40040
-#define IDM_GBASLOT 40042
-#define IDM_CHEATS_LIST 40050
-#define IDM_SHUT_UP 40053
-#define IDC_WINDOW2_5X 40054
-#define ID_LCDS_VERTICAL 40055
-#define ID_LCDS_HORIZONTAL 40056
-#define ID_LCDS_ONE 40057
-#define ID_LCDS_SWAP 40058
-#define ID_LCDS_NOSWAP 40059
-#define ID_LCDS_MAINGPU 40060
-#define ID_LCDS_SUBGPU 40061
-#define IDM_CHEATS_DISABLE 40062
-#define IDM_CHEATS_SEARCH 40063
-#define ID_RAMSEARCH_CAPTIONTEXT 40064
-#define IDM_VIEW3D 40065
-#define IDM_LOCKDOWN 40066
-#define IDM_EJECTCARD 40068
-#define IDM_SHOWTOOLBAR 40069
-#define ID_CONFIG_DISPLAYMETHOD 40070
-#define ID_DISPLAYMETHOD_DIRECTDRAWHW 40071
-#define ID_DISPLAYMETHOD_DIRECTDRAWSW 40072
-#define ID_HOTKEYS_TITLE 40073
-#define ID_VIEWLAYERS_SUBOBJ 40074
-#define ID_VIEWLAYERS_MAINOBJ 40075
-#define IDM_MOBJ 40076
-#define IDM_SOBJ 40077
-#define ID_VIEW_DISPLAYRTC 40078
-#define ID_CONFIG_ADVANCED 40079
-#define ID_ADVANCED_ADVANCED 40080
-#define ID_ADVANCED 40081
-#define ID_SAVETYPE_FORCEASCURRENT 40082
-#define IDC_SAVETYPE_FORCE 40083
-#define ID_DISPLAYMETHOD_VSYNC 40084
-#define IDC_LABEL_UP 50000
-#define IDC_LABEL_RIGHT 50001
-#define IDC_LABEL_LEFT 50002
-#define IDC_LABEL_DOWN 50003
-#define IDC_LABEL_A 50004
-#define IDC_LABEL_X 50005
-#define IDC_LABEL_B 50006
-#define IDC_LABEL_Y 50007
-#define IDC_LABEL_L 50008
-#define IDC_LABEL_START 50009
-#define IDC_LABEL_R 50010
-#define IDC_LABEL_SELECT 50011
-#define IDC_LABEL_UPLEFT 50012
-#define IDC_LABEL_DOWNRIGHT 50013
-#define IDC_LABEL_UPRIGHT 50014
-#define IDC_LABEL_DOWNLEFT 50015
-#define IDC_ALLOWLEFTRIGHT 50016
-#define IDC_LABEL_X3 50017
-#define IDC_LABEL_X2 50018
-#define IDC_DEBUG 50019
-#define IDC_UP 50020
-#define IDC_LEFT 50021
-#define IDC_DOWN 50022
-#define IDC_RIGHT 50023
-#define IDC_B 50024
-#define IDC_A 50025
-#define IDC_Y 50026
-#define IDC_X 50027
-#define IDC_START 50028
-#define IDC_SELECT 50029
-#define IDC_L 50030
-#define IDC_R 50031
-#define IDC_UPLEFT 50032
-#define IDC_UPRIGHT 50033
-#define IDC_DWNRIGHT 50034
-#define IDC_DWNLEFT 50035
-#define IDC_LABEL_BLUE 50036
-#define IDC_LID 50037
-#define IDD_INPUTCONFIG 50038
-#define IDC_LABEL_BLUE1 50039
-#define IDC_LUASCRIPT_RESERVE_START 58000
-#define IDC_LUASCRIPT_RESERVE_END 58099
-#define IDD_LUARECENT_RESERVE_START 58100
-#define IDD_LUARECENT_RESERVE_END 58199
-#define IDC_LUAMENU_RESERVE_START 58200
-#define IDC_LUAMENU_RESERVE_END 58399
-#define IDC_FRAMEADVANCE 58400
-#define IDC_LABEL_HK1 60001
-#define IDC_LABEL_HK2 60002
-#define IDC_LABEL_HK3 60003
-#define IDC_LABEL_HK4 60004
-#define IDC_LABEL_HK5 60005
-#define IDC_LABEL_HK6 60006
-#define IDC_LABEL_HK7 60007
-#define IDC_LABEL_HK8 60008
-#define IDC_LABEL_HK9 60009
-#define IDC_HOTKEY1 60011
-#define IDC_HOTKEY2 60012
-#define IDC_HOTKEY3 60013
-#define IDC_HOTKEY4 60014
-#define IDC_HOTKEY5 60015
-#define IDC_HOTKEY6 60016
-#define IDC_HOTKEY7 60017
-#define IDC_HOTKEY8 60018
-#define IDC_HOTKEY9 60019
-#define IDC_HOTKEY10 60020
-#define IDC_HOTKEY11 60021
-#define IDC_HOTKEY12 60022
-#define IDC_HOTKEY13 60023
-#define IDC_HOTKEY14 60024
-#define IDC_HOTKEY15 60025
-#define IDC_HOTKEY16 60026
-#define IDC_HOTKEY17 60027
-#define IDC_HOTKEY18 60028
-#define IDC_HOTKEY19 60029
-#define IDC_HOTKEY20 60030
-#define IDC_LABEL_HK10 60031
-#define IDC_LABEL_HK11 60032
-#define IDC_LABEL_HK12 60033
-#define IDC_LABEL_HK13 60034
-#define IDC_LABEL_HK14 60035
-#define IDC_LABEL_HK15 60036
-#define IDC_LABEL_HK16 60037
-#define IDC_LABEL_HK17 60038
-#define IDC_LABEL_HK19 60040
-#define IDC_LABEL_HK20 60041
-#define IDC_LABEL_HK18 60049
-#define IDC_HKCOMBO 60077
-#define IDD_KEYCUSTOM 60078
-#define IDM_HOTKEY_CONFIG 60079
-#define IDM_RENDER_HQ2XS 60081
-#define IDM_RENDER_LQ2X 60082
-#define IDM_RENDER_LQ2XS 60083
-#define IDC_SAVETYPE 64000
-
-// Next default values for new objects
-//
-#ifdef APSTUDIO_INVOKED
-#ifndef APSTUDIO_READONLY_SYMBOLS
-#define _APS_NEXT_RESOURCE_VALUE 123
-#define _APS_NEXT_COMMAND_VALUE 40085
-#define _APS_NEXT_CONTROL_VALUE 1040
-#define _APS_NEXT_SYMED_VALUE 101
-#endif
-#endif
-
--- a/src/in_2sf/desmume/saves.cpp
+++ /dev/null
@@ -1,1857 +1,1 @@
-/*
- Copyright (C) 2006 Normmatt
- Copyright (C) 2006 Theo Berkau
- Copyright (C) 2007 Pascal Giard
- Copyright (C) 2008-2012 DeSmuME team
- This file is free software: you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation, either version 2 of the License, or
- (at your option) any later version.
-
- This file is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with the this software. If not, see <http://www.gnu.org/licenses/>.
-*/
-
-#include <stack>
-#include <set>
-#include <fstream>
-#include <cstdio>
-#include <cstring>
-#include <ctime>
-#include <sys/stat.h>
-#ifdef HAVE_LIBZ
-#include <zlib.h>
-#endif
-#include "saves.h"
-#include "MMU.h"
-#include "NDSSystem.h"
-//#include "render3D.h"
-#include "cp15.h"
-//#include "GPU_osd.h"
-#include "version.h"
-
-#include "readwrite.h"
-//#include "gfx3d.h"
-//#include "movie.h"
-//#include "mic.h"
-#include "MMU_timing.h"
-
-#include "path.h"
-
-#ifdef _WINDOWS
-//#include "main.h"
-#endif
-
-//int lastSaveState = 0; //Keeps track of last savestate used for quick save/load functions
-
-//void*v is actually a void** which will be indirected before reading
-//since this isnt supported right now, it is declared in here to make things compile
-//#define SS_INDIRECT 0x80000000
-
-//savestates_t savestates[NB_STATES];
-
-#define SAVESTATE_VERSION 12
-static const char* magic = "DeSmuME SState\0";
-
-//a savestate chunk loader can set this if it wants to permit a silent failure (for compatibility)
-static bool SAV_silent_fail_flag;
-
-SFORMAT SF_ARM7[]={
- { "7INS", 4, 1, &NDS_ARM7.instruction },
- { "7INA", 4, 1, &NDS_ARM7.instruct_adr },
- { "7INN", 4, 1, &NDS_ARM7.next_instruction },
- { "7REG", 4,16, NDS_ARM7.R },
- { "7CPS", 4, 1, &NDS_ARM7.CPSR },
- { "7SPS", 4, 1, &NDS_ARM7.SPSR },
- { "7DUS", 4, 1, &NDS_ARM7.R13_usr },
- { "7EUS", 4, 1, &NDS_ARM7.R14_usr },
- { "7DSV", 4, 1, &NDS_ARM7.R13_svc },
- { "7ESV", 4, 1, &NDS_ARM7.R14_svc },
- { "7DAB", 4, 1, &NDS_ARM7.R13_abt },
- { "7EAB", 4, 1, &NDS_ARM7.R14_abt },
- { "7DUN", 4, 1, &NDS_ARM7.R13_und },
- { "7EUN", 4, 1, &NDS_ARM7.R14_und },
- { "7DIR", 4, 1, &NDS_ARM7.R13_irq },
- { "7EIR", 4, 1, &NDS_ARM7.R14_irq },
- { "78FI", 4, 1, &NDS_ARM7.R8_fiq },
- { "79FI", 4, 1, &NDS_ARM7.R9_fiq },
- { "7AFI", 4, 1, &NDS_ARM7.R10_fiq },
- { "7BFI", 4, 1, &NDS_ARM7.R11_fiq },
- { "7CFI", 4, 1, &NDS_ARM7.R12_fiq },
- { "7DFI", 4, 1, &NDS_ARM7.R13_fiq },
- { "7EFI", 4, 1, &NDS_ARM7.R14_fiq },
- { "7SVC", 4, 1, &NDS_ARM7.SPSR_svc },
- { "7ABT", 4, 1, &NDS_ARM7.SPSR_abt },
- { "7UND", 4, 1, &NDS_ARM7.SPSR_und },
- { "7IRQ", 4, 1, &NDS_ARM7.SPSR_irq },
- { "7FIQ", 4, 1, &NDS_ARM7.SPSR_fiq },
- { "7int", 4, 1, &NDS_ARM7.intVector },
- { "7LDT", 1, 1, &NDS_ARM7.LDTBit },
- { "7Wai", 4, 1, &NDS_ARM7.waitIRQ },
- { "7hef", 4, 1, &NDS_ARM7.halt_IE_and_IF },
- { "7iws", 1, 1, &NDS_ARM7.intrWaitARM_state },
- { NULL, 0, 0, NULL }
-};
-
-SFORMAT SF_ARM9[]={
- { "9INS", 4, 1, &NDS_ARM9.instruction},
- { "9INA", 4, 1, &NDS_ARM9.instruct_adr},
- { "9INN", 4, 1, &NDS_ARM9.next_instruction},
- { "9REG", 4,16, NDS_ARM9.R},
- { "9CPS", 4, 1, &NDS_ARM9.CPSR},
- { "9SPS", 4, 1, &NDS_ARM9.SPSR},
- { "9DUS", 4, 1, &NDS_ARM9.R13_usr},
- { "9EUS", 4, 1, &NDS_ARM9.R14_usr},
- { "9DSV", 4, 1, &NDS_ARM9.R13_svc},
- { "9ESV", 4, 1, &NDS_ARM9.R14_svc},
- { "9DAB", 4, 1, &NDS_ARM9.R13_abt},
- { "9EAB", 4, 1, &NDS_ARM9.R14_abt},
- { "9DUN", 4, 1, &NDS_ARM9.R13_und},
- { "9EUN", 4, 1, &NDS_ARM9.R14_und},
- { "9DIR", 4, 1, &NDS_ARM9.R13_irq},
- { "9EIR", 4, 1, &NDS_ARM9.R14_irq},
- { "98FI", 4, 1, &NDS_ARM9.R8_fiq},
- { "99FI", 4, 1, &NDS_ARM9.R9_fiq},
- { "9AFI", 4, 1, &NDS_ARM9.R10_fiq},
- { "9BFI", 4, 1, &NDS_ARM9.R11_fiq},
- { "9CFI", 4, 1, &NDS_ARM9.R12_fiq},
- { "9DFI", 4, 1, &NDS_ARM9.R13_fiq},
- { "9EFI", 4, 1, &NDS_ARM9.R14_fiq},
- { "9SVC", 4, 1, &NDS_ARM9.SPSR_svc},
- { "9ABT", 4, 1, &NDS_ARM9.SPSR_abt},
- { "9UND", 4, 1, &NDS_ARM9.SPSR_und},
- { "9IRQ", 4, 1, &NDS_ARM9.SPSR_irq},
- { "9FIQ", 4, 1, &NDS_ARM9.SPSR_fiq},
- { "9int", 4, 1, &NDS_ARM9.intVector},
- { "9LDT", 1, 1, &NDS_ARM9.LDTBit},
- { "9Wai", 4, 1, &NDS_ARM9.waitIRQ},
- { "9hef", 4, 1, &NDS_ARM9.halt_IE_and_IF },
- { "9iws", 1, 1, &NDS_ARM7.intrWaitARM_state },
- { NULL, 0, 0, NULL }
-};
-
-SFORMAT SF_MEM[]={
- { "ITCM", 1, sizeof(MMU.ARM9_ITCM), MMU.ARM9_ITCM},
- { "DTCM", 1, sizeof(MMU.ARM9_DTCM), MMU.ARM9_DTCM},
-
- //for legacy purposes, WRAX is a separate variable. shouldnt be a problem.
- { "WRAM", 1, 0x400000, MMU.MAIN_MEM},
- { "WRAX", 1, 0x400000, MMU.MAIN_MEM+0x400000},
-
- //NOTE - this is not as large as the allocated memory.
- //the memory is overlarge due to the way our memory map system is setup
- //but there are actually no more registers than this
- { "9REG", 1, 0x2000, MMU.ARM9_REG},
-
- { "VMEM", 1, sizeof(MMU.ARM9_VMEM), MMU.ARM9_VMEM},
- { "OAMS", 1, sizeof(MMU.ARM9_OAM), MMU.ARM9_OAM},
-
- //this size is specially chosen to avoid saving the blank space at the end
- { "LCDM", 1, 0xA4000, MMU.ARM9_LCD},
- { NULL, 0, 0, NULL }
-};
-
-SFORMAT SF_NDS[]={
- //{ "_WCY", 4, 1, &nds.wifiCycle},
- { "_TCY", 8, 8, nds.timerCycle},
- { "_VCT", 4, 1, &nds.VCount},
- { "_OLD", 4, 1, &nds.old},
- { "_TPX", 2, 1, NULL},
- { "_TPY", 2, 1, NULL},
- { "_TPB", 4, 1, NULL},
- { "_DBG", 4, 1, NULL},
- { "_ENS", 4, 1, NULL},
- { "_ENH", 4, 1, NULL},
- { "_ENI", 4, 1, NULL},
- { "_SLP", 4, 1, &nds.sleeping},
- { "_FBS", 4, 1, &nds.freezeBus},
- { "_CEJ", 4, 1, &nds.cardEjected},
- { "_P00", 1, 1, NULL},
- { "_P01", 1, 1, NULL},
- //{ "_P02", 1, 1, &nds.power1.gfx3d_render},
- //{ "_P03", 1, 1, &nds.power1.gfx3d_geometry},
- { "_P04", 1, 1, NULL},
- { "_P05", 1, 1, NULL},
- { "_P06", 1, 1, NULL},
- //{ "_P07", 1, 1, &nds.power2.wifi},
- { NULL, 0, 0, NULL }
-};
-
-SFORMAT SF_MMU[]={
- { "M7BI", 1, sizeof(MMU.ARM7_BIOS), MMU.ARM7_BIOS},
- { "M7ER", 1, sizeof(MMU.ARM7_ERAM), MMU.ARM7_ERAM},
- { "M7RG", 1, sizeof(MMU.ARM7_REG), MMU.ARM7_REG},
- { "M7WI", 1, sizeof(MMU.ARM7_WIRAM), MMU.ARM7_WIRAM},
- { "MSWI", 1, sizeof(MMU.SWIRAM), MMU.SWIRAM},
- { "M9RW", 1, 1, &MMU.ARM9_RW_MODE},
- { "MDTC", 4, 1, &MMU.DTCMRegion},
- { "MITC", 4, 1, &MMU.ITCMRegion},
- { "MTIM", 2, 8, MMU.timer},
- { "MTMO", 4, 8, MMU.timerMODE},
- { "MTON", 4, 8, MMU.timerON},
- { "MTRN", 4, 8, MMU.timerRUN},
- { "MTRL", 2, 8, MMU.timerReload},
- { "MIME", 4, 2, MMU.reg_IME},
- { "MIE_", 4, 2, MMU.reg_IE},
- { "MIF_", 4, 2, MMU.reg_IF_bits},
-
- //{ "MGXC", 8, 1, &MMU.gfx3dCycles},
-
- { "M_SX", 1, 2, &MMU.SPI_CNT},
- { "M_SC", 1, 2, &MMU.SPI_CMD},
- { "MASX", 1, 2, &MMU.AUX_SPI_CNT},
- { "MASC", 1, 2, &MMU.AUX_SPI_CMD},
-
- { "MDV1", 4, 1, &MMU.divRunning},
- { "MDV2", 8, 1, &MMU.divResult},
- { "MDV3", 8, 1, &MMU.divMod},
- { "MDV5", 8, 1, &MMU.divCycles},
-
- { "MSQ1", 4, 1, &MMU.sqrtRunning},
- { "MSQ2", 4, 1, &MMU.sqrtResult},
- { "MSQ4", 8, 1, &MMU.sqrtCycles},
-
- //begin memory chips
- { "BUCO", 1, 1, &MMU.fw.com},
- { "BUAD", 4, 1, &MMU.fw.addr},
- { "BUAS", 1, 1, &MMU.fw.addr_shift},
- { "BUAZ", 1, 1, &MMU.fw.addr_size},
- { "BUWE", 4, 1, &MMU.fw.write_enable},
- { "BUWR", 4, 1, &MMU.fw.writeable_buffer},
- //end memory chips
-
- { "MC0A", 4, 1, &MMU.dscard[0].address},
- { "MC0T", 4, 1, &MMU.dscard[0].transfer_count},
- { "MC1A", 4, 1, &MMU.dscard[1].address},
- { "MC1T", 4, 1, &MMU.dscard[1].transfer_count},
- //{ "MCHT", 4, 1, &MMU.CheckTimers},
- //{ "MCHD", 4, 1, &MMU.CheckDMAs},
-
- //fifos
- { "F0TH", 1, 1, &ipc_fifo[0].head},
- { "F0TL", 1, 1, &ipc_fifo[0].tail},
- { "F0SZ", 1, 1, &ipc_fifo[0].size},
- { "F0BF", 4, 16, ipc_fifo[0].buf},
- { "F1TH", 1, 1, &ipc_fifo[1].head},
- { "F1TL", 1, 1, &ipc_fifo[1].tail},
- { "F1SZ", 1, 1, &ipc_fifo[1].size},
- { "F1BF", 4, 16, ipc_fifo[1].buf},
-
- { "FDHD", 4, 1, NULL},
- { "FDTL", 4, 1, NULL},
- { "FDBF", 4, 0x6000, NULL},
-
- { "PMCN", 1, 1, &MMU.powerMan_CntReg},
- { "PMCW", 4, 1, &MMU.powerMan_CntRegWritten},
- { "PMCR", 1, 5, &MMU.powerMan_Reg},
-
- { "MR3D", 4, 1, NULL},
-
- { NULL, 0, 0, NULL }
-};
-
-/*static uint32_t tmpu32;
-SFORMAT SF_MOVIE[]={
- { "FRAC", 4, 1, &tmpu32},
- { "LAGC", 4, 1, &tmpu32},
- { NULL, 0, 0, NULL }
-};*/
-
-/*static void mmu_savestate(EMUFILE* os)
-{
- uint32_t version = 5;
- write32le(version,os);
-
- //version 2:
- MMU_new.backupDevice.save_state(os);
-
- //version 3:
- MMU_new.gxstat.savestate(os);
- for(int i=0;i<2;i++)
- for(int j=0;j<4;j++)
- MMU_new.dma[i][j].savestate(os);
-
- MMU_timing.arm9codeFetch.savestate(os, version);
- MMU_timing.arm9dataFetch.savestate(os, version);
- MMU_timing.arm7codeFetch.savestate(os, version);
- MMU_timing.arm7dataFetch.savestate(os, version);
- MMU_timing.arm9codeCache.savestate(os, version);
- MMU_timing.arm9dataCache.savestate(os, version);
-
- //version 4:
- MMU_new.sqrt.savestate(os);
- MMU_new.div.savestate(os);
-}*/
-
-/*static uint16_t tmpu16;
-static uint16_t tmpu16_array3[3];
-static uint8_t tmpu8;
-static uint8_t tmpu8_array3[3];
-static uint32_t tmpu32_array3[3];
-static uint8_t tmpu8_array6[6];
-static uint64_t tmpu64;
-static uint8_t tmpu8_array105[105];
-static uint16_t tmpu16_array4096[0x1000];
-static uint16_t tmpu16_array2048[0x800];
-static uint8_t tmpu8_array4096[4096];
-SFORMAT SF_WIFI[]={
- { "W000", 4, 1, &tmpu32},
- { "W010", 4, 1, &tmpu32},
-
- { "W020", 2, 1, &tmpu16},
- { "W030", 2, 1, &tmpu16},
-
- { "W040", 2, 1, &tmpu16},
- { "W050", 2, 1, &tmpu16},
-
- { "W060", 2, 1, &tmpu16},
- { "W070", 2, 1, &tmpu16},
- { "W080", 4, 1, &tmpu32},
-
- { "W090", 2, 3, tmpu16_array3},
- { "W100", 2, 1, &tmpu16},
- { "W110", 2, 1, &tmpu16},
- { "W120", 2, 1, &tmpu16},
- { "W130", 2, 1, &tmpu16},
- { "W140", 4, 1, &tmpu32},
- { "W150", 1, 1, &tmpu8},
- { "W160", 1, 3, tmpu8_array3},
- { "W170", 4, 3, tmpu32_array3},
- { "W180", 4, 3, tmpu32_array3},
- { "W190", 4, 3, tmpu32_array3},
-
- { "W200", 2, 1, &tmpu16},
- { "W210", 2, 1, &tmpu16},
-
- { "W220", 1, 6, tmpu8_array6},
- { "W230", 1, 6, tmpu8_array6},
-
- { "W240", 2, 1, &tmpu16},
- { "W250", 2, 1, &tmpu16},
- { "W260", 2, 1, &tmpu16},
-
- { "W270", 4, 1, &tmpu32},
- { "W280", 8, 1, &tmpu64},
- { "W290", 4, 1, &tmpu32},
- { "W300", 8, 1, &tmpu64},
- { "W310", 4, 1, &tmpu32},
- { "W320", 2, 1, &tmpu16},
- { "W330", 4, 1, &tmpu32},
-
- { "WR00", 4, 1, &tmpu32},
- { "WR01", 4, 1, &tmpu32},
- { "WR02", 4, 1, &tmpu32},
- { "WR03", 4, 1, &tmpu32},
- { "WR04", 4, 1, &tmpu32},
- { "WR05", 4, 1, &tmpu32},
- { "WR06", 4, 1, &tmpu32},
- { "WR07", 4, 1, &tmpu32},
- { "WR08", 4, 1, &tmpu32},
- { "WR09", 4, 1, &tmpu32},
- { "WR10", 4, 1, &tmpu32},
- { "WR11", 4, 1, &tmpu32},
- { "WR12", 4, 1, &tmpu32},
-
- { "W340", 1, 105, tmpu8_array105},
-
- { "W350", 2, 1, &tmpu16},
- { "W360", 2, 1, &tmpu16},
- { "W370", 4, 1, &tmpu32},
- { "W380", 2, 1, &tmpu16},
-
- { "W400", 2, 0x1000, tmpu16_array4096},
- { "W410", 2, 1, &tmpu16},
- { "W420", 2, 1, &tmpu16},
- { "W430", 2, 1, &tmpu16},
- { "W460", 2, 1, &tmpu16},
- { "W470", 2, 1, &tmpu16},
- { "W480", 2, 1, &tmpu16},
- { "W490", 2, 1, &tmpu16},
- { "W500", 2, 1, &tmpu16},
- { "W510", 2, 1, &tmpu16},
- { "W520", 2, 1, &tmpu16},
- { "W530", 2, 1, &tmpu16},
- { "W540", 2, 1, &tmpu16},
-
- { "W550", 4, 1, &tmpu32},
- { "W560", 4, 1, &tmpu32},
- { "W570", 4, 1, &tmpu32},
-
- { "W580", 2, 0x800, tmpu16_array2048},
- { "W590", 2, 1, &tmpu16},
-
- { "WX00", 8, 1, &tmpu64},
- { "WX10", 1, 4096, tmpu8_array4096},
- { "WX20", 4, 1, &tmpu32},
- { "WX30", 4, 1, &tmpu32},
- { "WX40", 4, 1, &tmpu32},
-
- { NULL, 0, 0, NULL }
-};*/
-
-static bool mmu_loadstate(EMUFILE* is, int)
-{
- //read version
- uint32_t version;
- if(read32le(&version,is) != 1) return false;
-
- if(version == 0 || version == 1)
- {
- uint32_t bupmem_size = 0;
- uint32_t addr_size = 0xFFFFFFFF;
-
- if(version == 0)
- {
- //version 0 was buggy and didnt save the type.
- //it would silently fail if there was a size mismatch
- SAV_silent_fail_flag = true;
- if(read32le(&bupmem_size,is) != 1) return false;
- //if(bupmem_size != MMU.bupmem.size) return false; //mismatch between current initialized and saved size
- addr_size = BackupDevice::addr_size_for_old_save_size(bupmem_size);
- }
- else if(version == 1)
- {
- //version 1 reinitializes the save system with the type that was saved
- uint32_t bupmem_type;
- if(read32le(&bupmem_type,is) != 1) return false;
- if(read32le(&bupmem_size,is) != 1) return false;
- addr_size = BackupDevice::addr_size_for_old_save_type(bupmem_type);
- if(addr_size == 0xFFFFFFFF)
- addr_size = BackupDevice::addr_size_for_old_save_size(bupmem_size);
- }
-
- if(addr_size == 0xFFFFFFFF)
- return false;
-
- uint8_t* temp = new uint8_t[bupmem_size];
- is->fread((char*)temp,bupmem_size);
- MMU_new.backupDevice.load_old_state(addr_size,temp,bupmem_size);
- delete[] temp;
- if(is->fail()) return false;
- }
-
- if(version < 2) return true;
-
- bool ok = MMU_new.backupDevice.load_state(is);
-
- if(version < 3) return true;
-
- ok &= MMU_new.gxstat.loadstate(is);
-
- for(int i=0;i<2;i++)
- for(int j=0;j<4;j++)
- ok &= MMU_new.dma[i][j].loadstate(is);
-
- ok &= MMU_timing.arm9codeFetch.loadstate(is, version);
- ok &= MMU_timing.arm9dataFetch.loadstate(is, version);
- ok &= MMU_timing.arm7codeFetch.loadstate(is, version);
- ok &= MMU_timing.arm7dataFetch.loadstate(is, version);
- ok &= MMU_timing.arm9codeCache.loadstate(is, version);
- ok &= MMU_timing.arm9dataCache.loadstate(is, version);
-
- if(version < 4) return true;
-
- ok &= MMU_new.sqrt.loadstate(is,version);
- ok &= MMU_new.div.loadstate(is,version);
-
- //to prevent old savestates from confusing IF bits, mask out ones which had been stored but should have been generated
- MMU.reg_IF_bits[0] &= ~0x00200000;
- MMU.reg_IF_bits[1] &= ~0x00000000;
-
- //MMU_new.gxstat.fifo_low = gxFIFO.size <= 127;
- //MMU_new.gxstat.fifo_empty = gxFIFO.size == 0;
-
- /*if(version < 5)
- MMU.reg_DISP3DCNT_bits = T1ReadWord(MMU.ARM9_REG,0x60);*/
-
- return ok;
-}
-
-/*static void cp15_saveone(armcp15_t *cp15, EMUFILE* os)
-{
- write32le(cp15->IDCode,os);
- write32le(cp15->cacheType,os);
- write32le(cp15->TCMSize,os);
- write32le(cp15->ctrl,os);
- write32le(cp15->DCConfig,os);
- write32le(cp15->ICConfig,os);
- write32le(cp15->writeBuffCtrl,os);
- write32le(cp15->und,os);
- write32le(cp15->DaccessPerm,os);
- write32le(cp15->IaccessPerm,os);
- write32le(cp15->protectBaseSize0,os);
- write32le(cp15->protectBaseSize1,os);
- write32le(cp15->protectBaseSize2,os);
- write32le(cp15->protectBaseSize3,os);
- write32le(cp15->protectBaseSize4,os);
- write32le(cp15->protectBaseSize5,os);
- write32le(cp15->protectBaseSize6,os);
- write32le(cp15->protectBaseSize7,os);
- write32le(cp15->cacheOp,os);
- write32le(cp15->DcacheLock,os);
- write32le(cp15->IcacheLock,os);
- write32le(cp15->ITCMRegion,os);
- write32le(cp15->DTCMRegion,os);
- write32le(cp15->processID,os);
- write32le(cp15->RAM_TAG,os);
- write32le(cp15->testState,os);
- write32le(cp15->cacheDbg,os);
- for(int i=0;i<8;i++) write32le(cp15->regionWriteMask_USR[i],os);
- for(int i=0;i<8;i++) write32le(cp15->regionWriteMask_SYS[i],os);
- for(int i=0;i<8;i++) write32le(cp15->regionReadMask_USR[i],os);
- for(int i=0;i<8;i++) write32le(cp15->regionReadMask_SYS[i],os);
- for(int i=0;i<8;i++) write32le(cp15->regionExecuteMask_USR[i],os);
- for(int i=0;i<8;i++) write32le(cp15->regionExecuteMask_SYS[i],os);
- for(int i=0;i<8;i++) write32le(cp15->regionWriteSet_USR[i],os);
- for(int i=0;i<8;i++) write32le(cp15->regionWriteSet_SYS[i],os);
- for(int i=0;i<8;i++) write32le(cp15->regionReadSet_USR[i],os);
- for(int i=0;i<8;i++) write32le(cp15->regionReadSet_SYS[i],os);
- for(int i=0;i<8;i++) write32le(cp15->regionExecuteSet_USR[i],os);
- for(int i=0;i<8;i++) write32le(cp15->regionExecuteSet_SYS[i],os);
-}*/
-
-/*static void cp15_savestate(EMUFILE* os)
-{
- //version
- write32le(1,os);
-
- cp15_saveone((armcp15_t *)NDS_ARM9.coproc[15],os);
- //ARM7 not have coprocessor
- //cp15_saveone((armcp15_t *)NDS_ARM7.coproc[15],os);
-}*/
-
-static bool cp15_loadone(armcp15_t *cp15, EMUFILE* is)
-{
- if(!read32le(&cp15->IDCode,is)) return false;
- if(!read32le(&cp15->cacheType,is)) return false;
- if(!read32le(&cp15->TCMSize,is)) return false;
- if(!read32le(&cp15->ctrl,is)) return false;
- if(!read32le(&cp15->DCConfig,is)) return false;
- if(!read32le(&cp15->ICConfig,is)) return false;
- if(!read32le(&cp15->writeBuffCtrl,is)) return false;
- if(!read32le(&cp15->und,is)) return false;
- if(!read32le(&cp15->DaccessPerm,is)) return false;
- if(!read32le(&cp15->IaccessPerm,is)) return false;
- if(!read32le(&cp15->protectBaseSize0,is)) return false;
- if(!read32le(&cp15->protectBaseSize1,is)) return false;
- if(!read32le(&cp15->protectBaseSize2,is)) return false;
- if(!read32le(&cp15->protectBaseSize3,is)) return false;
- if(!read32le(&cp15->protectBaseSize4,is)) return false;
- if(!read32le(&cp15->protectBaseSize5,is)) return false;
- if(!read32le(&cp15->protectBaseSize6,is)) return false;
- if(!read32le(&cp15->protectBaseSize7,is)) return false;
- if(!read32le(&cp15->cacheOp,is)) return false;
- if(!read32le(&cp15->DcacheLock,is)) return false;
- if(!read32le(&cp15->IcacheLock,is)) return false;
- if(!read32le(&cp15->ITCMRegion,is)) return false;
- if(!read32le(&cp15->DTCMRegion,is)) return false;
- if(!read32le(&cp15->processID,is)) return false;
- if(!read32le(&cp15->RAM_TAG,is)) return false;
- if(!read32le(&cp15->testState,is)) return false;
- if(!read32le(&cp15->cacheDbg,is)) return false;
- for(int i=0;i<8;i++) if(!read32le(&cp15->regionWriteMask_USR[i],is)) return false;
- for(int i=0;i<8;i++) if(!read32le(&cp15->regionWriteMask_SYS[i],is)) return false;
- for(int i=0;i<8;i++) if(!read32le(&cp15->regionReadMask_USR[i],is)) return false;
- for(int i=0;i<8;i++) if(!read32le(&cp15->regionReadMask_SYS[i],is)) return false;
- for(int i=0;i<8;i++) if(!read32le(&cp15->regionExecuteMask_USR[i],is)) return false;
- for(int i=0;i<8;i++) if(!read32le(&cp15->regionExecuteMask_SYS[i],is)) return false;
- for(int i=0;i<8;i++) if(!read32le(&cp15->regionWriteSet_USR[i],is)) return false;
- for(int i=0;i<8;i++) if(!read32le(&cp15->regionWriteSet_SYS[i],is)) return false;
- for(int i=0;i<8;i++) if(!read32le(&cp15->regionReadSet_USR[i],is)) return false;
- for(int i=0;i<8;i++) if(!read32le(&cp15->regionReadSet_SYS[i],is)) return false;
- for(int i=0;i<8;i++) if(!read32le(&cp15->regionExecuteSet_USR[i],is)) return false;
- for(int i=0;i<8;i++) if(!read32le(&cp15->regionExecuteSet_SYS[i],is)) return false;
-
- return true;
-}
-
-static bool cp15_loadstate(EMUFILE* is, int)
-{
- //read version
- uint32_t version;
- if(read32le(&version,is) != 1) return false;
- if(version > 1) return false;
-
- if(!cp15_loadone((armcp15_t *)NDS_ARM9.coproc[15],is)) return false;
-
- if(version == 0)
- {
- //ARM7 not have coprocessor
- uint8_t *tmp_buf = new uint8_t [sizeof(armcp15_t)];
- if (!tmp_buf) return false;
- if(!cp15_loadone((armcp15_t *)tmp_buf,is)) return false;
- delete [] tmp_buf;
- tmp_buf = NULL;
- }
-
- return true;
-}
-
-
-
-/* Format time and convert to string */
-/*static char * format_time(time_t cal_time)
-{
- struct tm *time_struct;
- static char str[64];
-
- time_struct=localtime(&cal_time);
- strftime(str, sizeof str, "%d-%b-%Y %H:%M:%S", time_struct);
-
- return str;
-}*/
-
-/*void clear_savestates()
-{
- uint8_t i;
- for( i = 0; i < NB_STATES; i++ )
- savestates[i].exists = false;
-}*/
-
-// Scan for existing savestates and update struct
-/*void scan_savestates()
-{
- struct stat sbuf;
- char filename[MAX_PATH+1];
-
- clear_savestates();
-
- for(int i = 0; i < NB_STATES; i++ )
- {
- path.getpathnoext(path.STATES, filename);
-
- if (strlen(filename) + strlen(".dst") + strlen("-2147483648")*/ /* = biggest string for i */ /*>MAX_PATH) return ;
- sprintf(filename+strlen(filename), ".ds%d", i);
- if( stat(filename,&sbuf) == -1 ) continue;
- savestates[i].exists = true;
- strncpy(savestates[i].date, format_time(sbuf.st_mtime),40);
- savestates[i].date[40-1] = '\0';
- }
-
- return ;
-}*/
-
-/*void savestate_slot(int num)
-{
- struct stat sbuf;
- char filename[MAX_PATH+1];
-
- lastSaveState = num; //Set last savestate used
-
- path.getpathnoext(path.STATES, filename);
-
- if (strlen(filename) + strlen(".dsx") + strlen("-2147483648")*/ /* = biggest string for num *//* >MAX_PATH) return ;
- sprintf(filename+strlen(filename), ".ds%d", num);*/
-
- /*if (savestate_save(filename))
- {
- osd->setLineColor(255, 255, 255);
- osd->addLine("Saved to %i slot", num);
- }
- else
- {
- osd->setLineColor(255, 0, 0);
- osd->addLine("Error saving %i slot", num);
- return;
- }*/
-
- /*if (num >= 0 && num < NB_STATES)
- {
- if (stat(filename,&sbuf) != -1)
- {
- savestates[num].exists = true;
- strncpy(savestates[num].date, format_time(sbuf.st_mtime),40);
- savestates[num].date[40-1] = '\0';
- }
- }
-}*/
-
-/*void loadstate_slot(int num)
-{
- char filename[MAX_PATH];
-
- lastSaveState = num; //Set last savestate used
-
- path.getpathnoext(path.STATES, filename);
-
- if (strlen(filename) + strlen(".dsx") + strlen("-2147483648")*/ /* = biggest string for num *//* >MAX_PATH) return ;
- sprintf(filename+strlen(filename), ".ds%d", num);*/
- /*if (savestate_load(filename))
- {
- osd->setLineColor(255, 255, 255);
- osd->addLine("Loaded from %i slot", num);
- }
- else
- {
- osd->setLineColor(255, 0, 0);
- osd->addLine("Error loading %i slot", num);
- }*/
-//}
-
-
-// note: guessSF is so we don't have to do a linear search through the SFORMAT array every time
-// in the (most common) case that we already know where the next entry is.
-static const SFORMAT *CheckS(const SFORMAT *guessSF, const SFORMAT *firstSF, uint32_t size, uint32_t count, char *desc)
-{
- const SFORMAT *sf = guessSF ? guessSF : firstSF;
- while(sf->v)
- {
- //NOT SUPPORTED RIGHT NOW
- //if(sf->size==~0) // Link to another SFORMAT structure.
- //{
- // SFORMAT *tmp;
- // if((tmp= CheckS((SFORMAT *)sf->v, tsize, desc) ))
- // return tmp;
- // sf++;
- // continue;
- //}
- if(!memcmp(desc,sf->desc,4))
- {
- if(sf->size != size || sf->count != count)
- return 0;
- return sf;
- }
-
- // failed to find it, have to keep iterating
- if(guessSF)
- {
- sf = firstSF;
- guessSF = NULL;
- }
- else
- {
- sf++;
- }
- }
- return 0;
-}
-
-
-static bool ReadStateChunk(EMUFILE* is, const SFORMAT *sf, int size)
-{
- const SFORMAT *tmp = NULL;
- const SFORMAT *guessSF = NULL;
- size_t temp = is->ftell();
-
- while(is->ftell()<temp+size)
- {
- uint32_t sz, count;
-
- char toa[4];
- is->fread(toa,4);
- if(is->fail())
- return false;
-
- if(!read32le(&sz,is)) return false;
- if(!read32le(&count,is)) return false;
-
- if((tmp=CheckS(guessSF,sf,sz,count,toa)))
- {
- #ifdef LOCAL_LE
- // no need to ever loop one at a time if not flipping byte order
- is->fread((char *)tmp->v,sz*count);
- #else
- if(sz == 1) {
- //special case: read a huge byte array
- is->fread((char *)tmp->v,count);
- } else {
- for(unsigned int i=0;i<count;i++)
- {
- is->fread((char *)tmp->v + i*sz,sz);
- FlipByteOrder((uint8_t*)tmp->v + i*sz,sz);
- }
- }
- #endif
- guessSF = tmp + 1;
- }
- else
- {
- is->fseek(sz*count,SEEK_CUR);
- guessSF = NULL;
- }
- } // while(...)
- return true;
-}
-
-
-
-/*static int SubWrite(EMUFILE* os, const SFORMAT *sf)
-{
- uint32_t acc=0;
-
-#ifdef DEBUG
- std::set<std::string> keyset;
-#endif
-
- const SFORMAT* temp = sf;
- while(temp->v) {
- const SFORMAT* seek = sf;
- while(seek->v && seek != temp) {
- if(!strcmp(seek->desc,temp->desc)) {
- printf("ERROR! duplicated chunk name: %s\n", temp->desc);
- }
- seek++;
- }
- temp++;
- }
-
- while(sf->v)
- {
- //not supported right now
- //if(sf->size==~0) //Link to another struct
- //{
- // uint32_t tmp;
-
- // if(!(tmp=SubWrite(os,(SFORMAT *)sf->v)))
- // return 0;
- // acc+=tmp;
- // sf++;
- // continue;
- //}
-
- int count = sf->count;
- int size = sf->size;
-
- //add size of current node to the accumulator
- acc += 4 + sizeof(sf->size) + sizeof(sf->count);
- acc += count * size;
-
- if(os) //Are we writing or calculating the size of this block?
- {
- os->fwrite(sf->desc,4);
- write32le(sf->size,os);
- write32le(sf->count,os);
-
- #ifdef DEBUG
- //make sure we dont dup any keys
- if(keyset.find(sf->desc) != keyset.end())
- {
- printf("duplicate save key!\n");
- assert(false);
- }
- keyset.insert(sf->desc);
- #endif
-
-
- #ifdef LOCAL_LE
- // no need to ever loop one at a time if not flipping byte order
- os->fwrite((char *)sf->v,size*count);
- #else
- if(size == 1) {
- //special case: write a huge byte array
- os->fwrite((char *)sf->v,count);
- } else {
- for(int i=0;i<count;i++) {
- FlipByteOrder((uint8_t*)sf->v + i*size, size);
- os->fwrite((char*)sf->v + i*size,size);
- //Now restore the original byte order.
- FlipByteOrder((uint8_t*)sf->v + i*size, size);
- }
- }
- #endif
- }
- sf++;
- }
-
- return acc;
-}*/
-
-/*static int savestate_WriteChunk(EMUFILE* os, int type, const SFORMAT *sf)
-{
- write32le(type,os);
- if(!sf) return 4;
- int bsize = SubWrite((EMUFILE*)0,sf);
- write32le(bsize,os);
-
- if(!SubWrite(os,sf))
- {
- return 8;
- }
- return bsize+8;
-}*/
-
-/*static void savestate_WriteChunk(EMUFILE* os, int type, void (*saveproc)(EMUFILE* os))
-{
- uint32_t pos1 = os->ftell();
-
- //write the type, size(placeholder), and data
- write32le(type,os);
- os->fseek(4, SEEK_CUR); // skip the size, we write that later
- saveproc(os);
-
- //get the size
- uint32_t pos2 = os->ftell();
- assert(pos2 != (uint32_t)-1); // if this assert fails, saveproc did something bad
- uint32_t size = (pos2 - pos1) - (2 * sizeof(uint32_t));
-
- //fill in the actual size
- os->fseek(pos1 + sizeof(uint32_t),SEEK_SET);
- write32le(size,os);
- os->fseek(pos2,SEEK_SET);*/
-
-/*
-// old version of this function,
-// for reference in case the new one above starts misbehaving somehow:
-
- // - this is retarded. why not write placeholders for size and then write directly to the stream
- //and then go back and fill them in
-
- //get the size
- memorystream mstemp;
- saveproc(&mstemp);
- mstemp.flush();
- uint32_t size = mstemp.size();
-
- //write the type, size, and data
- write32le(type,os);
- write32le(size,os);
- os->write(mstemp.buf(),size);
-*/
-//}
-
-//static void writechunks(EMUFILE* os);
-
-/*bool savestate_save(EMUFILE* outstream, int compressionLevel)
-{
- #ifndef HAVE_LIBZ
- compressionLevel = Z_NO_COMPRESSION;
- #endif
-
- EMUFILE_MEMORY ms;
- EMUFILE* os;
-
- if(compressionLevel != Z_NO_COMPRESSION)
- {
- //generate the savestate in memory first
- os = (EMUFILE*)&ms;
- writechunks(os);
- }
- else
- {
- os = outstream;
- os->fseek(32,SEEK_SET); //skip the header
- writechunks(os);
- }
-
- //save the length of the file
- uint32_t len = os->ftell();
-
- uint32_t comprlen = 0xFFFFFFFF;
- uint8_t* cbuf;
-
- //compress the data
- int error = Z_OK;
- if(compressionLevel != Z_NO_COMPRESSION)
- {
- cbuf = ms.buf();
- uLongf comprlen2;
- //worst case compression.
- //zlib says "0.1% larger than sourceLen plus 12 bytes"
- comprlen = (len>>9)+12 + len;
- cbuf = new uint8_t[comprlen];
- // Workaround to make it compile under linux 64bit
- comprlen2 = comprlen;
- //error = compress2(cbuf,&comprlen2,ms.buf(),len,compressionLevel);
- comprlen = (uint32_t)comprlen2;
- }
-
- //dump the header
- outstream->fseek(0,SEEK_SET);
- outstream->fwrite(magic,16);
- write32le(SAVESTATE_VERSION,outstream);
- write32le(EMU_DESMUME_VERSION_NUMERIC(),outstream); //desmume version
- write32le(len,outstream); //uncompressed length
- write32le(comprlen,outstream); //compressed length (-1 if it is not compressed)
-
- if(compressionLevel != Z_NO_COMPRESSION)
- {
- outstream->fwrite((char*)cbuf,comprlen==(uint32_t)-1?len:comprlen);
- delete[] cbuf;
- }
-
- return error == Z_OK;
-}*/
-
-/*bool savestate_save (const char *file_name)
-{
- EMUFILE_MEMORY ms;
- size_t elems_written;
-#ifdef HAVE_LIBZ
- if(!savestate_save(&ms, Z_DEFAULT_COMPRESSION))
-#else
- if(!savestate_save(&ms, 0))
-#endif
- return false;
- FILE* file = fopen(file_name,"wb");
- if(file)
- {
- elems_written = fwrite(ms.buf(),1,ms.size(),file);
- fclose(file);
- return elems_written == ms.size();
- } else return false;
-}*/
-
-//extern SFORMAT SF_RTC[];
-
-/*static void writechunks(EMUFILE* os) {
- savestate_WriteChunk(os,1,SF_ARM9);
- savestate_WriteChunk(os,2,SF_ARM7);
- savestate_WriteChunk(os,3,cp15_savestate);
- savestate_WriteChunk(os,4,SF_MEM);
- savestate_WriteChunk(os,5,SF_NDS);
- savestate_WriteChunk(os,51,nds_savestate);
- savestate_WriteChunk(os,60,SF_MMU);
- savestate_WriteChunk(os,61,mmu_savestate);
- //savestate_WriteChunk(os,7,gpu_savestate);
- savestate_WriteChunk(os,8,spu_savestate);
- //savestate_WriteChunk(os,81,mic_savestate);
- //savestate_WriteChunk(os,90,SF_GFX3D);
- //savestate_WriteChunk(os,91,gfx3d_savestate);
- //savestate_WriteChunk(os,100,SF_MOVIE);
- //savestate_WriteChunk(os,101,mov_savestate);
- //savestate_WriteChunk(os,110,SF_WIFI);
- //savestate_WriteChunk(os,120,SF_RTC);
- savestate_WriteChunk(os,0xFFFFFFFF,(SFORMAT*)0);
-}*/
-
-/*static bool fake_gpu_loadstate(EMUFILE* is, int size)
-{
- //read version
- uint32_t version;
-
- //sigh.. shouldve used a new version number
- if(size == 256*192*2*2)
- version = 0;
- else if(size== 0x30024)
- {
- read32le(&version,is);
- version = 1;
- }
- else
- if(read32le(&version,is) != 1) return false;
-
-
- if(version<0||version>1) return false;
-
- uint8_t tmpu8_array[4*256*192];
- is->fread((char*)tmpu8_array,sizeof(tmpu8_array));
-
- if(version==1)
- {
- uint32_t tmpu32;
- for (int i = 0; i < 8; ++i)
- read32le(&tmpu32, is);*/
- /*read32le(&MainScreen.gpu->affineInfo[0].x,is);
- read32le(&MainScreen.gpu->affineInfo[0].y,is);
- read32le(&MainScreen.gpu->affineInfo[1].x,is);
- read32le(&MainScreen.gpu->affineInfo[1].y,is);
- read32le(&SubScreen.gpu->affineInfo[0].x,is);
- read32le(&SubScreen.gpu->affineInfo[0].y,is);
- read32le(&SubScreen.gpu->affineInfo[1].x,is);
- read32le(&SubScreen.gpu->affineInfo[1].y,is);*/
- //removed per nitsuja feedback. anyway, this same thing will happen almost immediately in gpu line=0
- //MainScreen.gpu->refreshAffineStartRegs(-1,-1);
- //SubScreen.gpu->refreshAffineStartRegs(-1,-1);
- /*}
-
- //MainScreen.gpu->updateBLDALPHA();
- //SubScreen.gpu->updateBLDALPHA();
- return !is->fail();
-}*/
-
-/*static bool fake_mic_loadstate(EMUFILE* is, int size)
-{
- uint32_t version;
- if(read32le(&version,is) != 1) return false;
- if(version > 1 || version == 0) { is->fseek(size-4, SEEK_CUR); return true; }
-
- uint8_t tmpu8_Array[2][4096];
- is->fread((char*)tmpu8_Array[0], 4096);
- is->fread((char*)tmpu8_Array[1], 4096);
- uint16_t tmpu16;
- read16le(&tmpu16,is);
- uint8_t tmpu8;
- read8le(&tmpu8,is);
- read8le(&tmpu8,is);
- uint32_t tmpu32;
- read32le(&tmpu32,is);
- return true;
-}*/
-
-/*static uint32_t tmpu32_array16[16];
-static uint32_t tmpu32_array64[64];
-static uint32_t tmpu32_array4[4];
-static uint16_t tmpu16_array6[6];
-static uint8_t tmpu8_array4[4];
-static uint16_t tmpu16_array32[32];
-static uint8_t tmpu8_array128[128];
-static uint8_t tmpu8_arrayAlot[4*256*192];
-SFORMAT SF_GFX3D[]={
- { "GCTL", 4, 1, &tmpu32}, // no longer regenerated indirectly, see comment in loadstate()
- { "GPAT", 4, 1, &tmpu32},
- { "GPAP", 4, 1, &tmpu32},
- { "GINB", 4, 1, &tmpu32},
- { "GTFM", 4, 1, &tmpu32},
- { "GTPA", 4, 1, &tmpu32},
- { "GMOD", 4, 1, &tmpu32},
- { "GMTM", 4,16, tmpu32_array16},
- { "GMCU", 4,64, tmpu32_array64},
- { "ML4I", 1, 1, &tmpu8},
- { "ML3I", 1, 1, &tmpu8},
- { "MM4I", 1, 1, &tmpu8},
- { "MM3I", 1, 1, &tmpu8},
- { "MMxI", 1, 1, &tmpu8},
- { "GSCO", 4, 1, tmpu32_array4},
- { "GCOI", 1, 1, &tmpu8},
- { "GVFM", 4, 1, &tmpu32},
- { "GTRN", 4, 4, tmpu32_array4},
- { "GTRI", 1, 1, &tmpu8},
- { "GSCA", 4, 4, tmpu32_array4},
- { "GSCI", 1, 1, &tmpu8},
- { "G_T_", 4, 1, &tmpu32},
- { "G_S_", 4, 1, &tmpu32},
- { "GL_T", 4, 1, &tmpu32},
- { "GL_S", 4, 1, &tmpu32},
- { "GLCM", 4, 1, &tmpu32},
- { "GLIN", 4, 1, &tmpu32},
- { "GLI2", 4, 1, &tmpu32},
- { "GLSB", 4, 1, &tmpu32},
- { "GLBT", 4, 1, &tmpu32},
- { "GLPT", 4, 1, &tmpu32},
- { "GLPC", 4, 4, tmpu32_array4},
- { "GBTC", 2, 6, tmpu16_array6},
- { "GFHE", 4, 1, &gxFIFO.head},
- { "GFTA", 4, 1, &gxFIFO.tail},
- { "GFSZ", 4, 1, &gxFIFO.size},
- { "GFCM", 1, HACK_GXIFO_SIZE, &gxFIFO.cmd[0]},
- { "GFPM", 4, HACK_GXIFO_SIZE, &gxFIFO.param[0]},
- { "GPHE", 1, 1, &gxPIPE.head},
- { "GPTA", 1, 1, &gxPIPE.tail},
- { "GPSZ", 1, 1, &gxPIPE.size},
- { "GPCM", 1, 4, &gxPIPE.cmd[0]},
- { "GPPM", 4, 4, &gxPIPE.param[0]},
- { "GCOL", 1, 4, &tmpu8_array4},
- { "GLCO", 4, 4, tmpu32_array4},
- { "GLDI", 4, 4, tmpu32_array4},
- { "GMDI", 2, 1, &tmpu16},
- { "GMAM", 2, 1, &tmpu16},
- { "GMSP", 2, 1, &tmpu16},
- { "GMEM", 2, 1, &tmpu16},
- { "GFLP", 4, 1, &tmpu32},
- { "GDRP", 4, 1, &tmpu32},
- { "GSET", 4, 1, &tmpu32},
- { "GSEA", 4, 1, &tmpu32},
- { "GSEB", 4, 1, &tmpu32},
- { "GSEX", 4, 1, &tmpu32},
- { "GSEE", 4, 1, &tmpu32},
- { "GSEC", 4, 1, &tmpu32},
- { "GSEF", 4, 1, &tmpu32},
- { "GSEO", 4, 1, &tmpu32},
- { "GFSH", 4, 1, &tmpu32},
- { "GSSH", 4, 1, &tmpu32},
- { "GSWB", 4, 1, &tmpu32},
- { "GSSM", 4, 1, &tmpu32},
- { "GSAR", 1, 1, &tmpu8},
- { "GSVP", 4, 1, &tmpu32},
- { "GSCC", 4, 1, &tmpu32},
- { "GSCD", 4, 1, &tmpu32},
- { "GSFC", 4, 4, tmpu32_array4},
- { "GSFO", 4, 1, &tmpu32},
- { "GST4", 2, 32, tmpu16_array32},
- { "GSSU", 1, 128, tmpu8_array128},
- { "GSSI", 4, 1, &tmpu32},
- { "GSAF", 4, 1, &tmpu32},
- { "GSPF", 4, 1, &tmpu32},
- //------------------------
- { "GTST", 4, 1, &tmpu32},
- { "GTVC", 4, 1, &tmpu32},
- { "GTVM", 4, 4, tmpu32_array4},
- { "GTVF", 4, 1, &tmpu32},
- { "G3CX", 1, 4*256*192, tmpu8_arrayAlot},
- { 0 }
-};*/
-
-/*static uint8_t tmpu8_array8[8];
-static SFORMAT SF_RTC[]={
- { "R000", 1, 1, &tmpu8},
- { "R010", 1, 1, &tmpu8},
- { "R020", 1, 1, &tmpu8},
- { "R030", 1, 1, &tmpu8},
-
- { "R040", 1, 1, &tmpu8},
- { "R050", 1, 1, &tmpu8},
- { "R060", 1, 1, &tmpu8},
- { "R070", 1, 1, &tmpu8},
- { "R080", 1, 1, &tmpu8},
- { "R090", 1, 1, &tmpu8},
- { "R100", 1, 1, &tmpu8},
- { "R110", 2, 1, &tmpu16},
-
- { "R120", 1, 1, &tmpu8},
- { "R130", 1, 1, &tmpu8},
- { "R140", 1, 1, &tmpu8},
- { "R150", 1, 8, tmpu8_array8},
-
- { "R160", 1, 8, tmpu8_array8},
-
- { NULL, 0, 0, NULL }
-};*/
-
-/*static bool fake_gfx_hardware_loadstate(EMUFILE *f)
-{
- uint32_t version;
- if(read32le(&version,f) != 1) return false;
- if(version != 0) return false;
-
- uint32_t tempsize;
- read32le(&tempsize,f);
- uint32_t commandCursor = 4-tempsize;
- //for(uint32_t i=0;i<commandCursor;i++) commandsPending[i].command = 0;
- uint8_t tmpu8;
- for(uint32_t i=commandCursor;i<4;i++) read8le(&commandsPending[i].command&tmpu8,f);
- read32le(&tempsize,f);
- //for(uint32_t i=0;i<commandCursor;i++) commandsPending[i].countdown = 0;
- for(uint32_t i=commandCursor;i<4;i++) read8le(&commandsPending[i].countdown&tmpu8,f);
-
- read8le(&countdown&tmpu8,f);
-
- return true;
-}*/
-
-/*static bool fake_gfx3d_loadstate(EMUFILE* is, int size)
-{
- int version;
- if(read32le(&version,is) != 1) return false;
- if(size==8) version = 0;
-
-
- //gfx3d_glPolygonAttrib_cache();
- //gfx3d_glTexImage_cache();
- //gfx3d_glLightDirection_cache(0);
- //gfx3d_glLightDirection_cache(1);
- //gfx3d_glLightDirection_cache(2);
- //gfx3d_glLightDirection_cache(3);
-
- //jiggle the lists. and also wipe them. this is clearly not the best thing to be doing.
- //listTwiddle = 0;
- //polylist = &polylists[listTwiddle];
- //vertlist = &vertlists[listTwiddle];
-
-#define OSREAD(x) is->fread((char*)&(x),sizeof((x)));
- if(version>=1)
- {
- int tmpint;
- //OSREAD(vertlist->count);
- //OSREAD(tmpint);
- is->fread(&tmpint, sizeof(int));
- //for(int i=0;i<vertlist->count;i++)
- for (int i = 0; i < tmpint; ++i)
- {
- //vertlist->list[i].load(is);
- float tmpfloat;
- uint8_t tmpu8;
- for (int j = 0; j < 6; ++j)
- //OSREAD(tmpfloat);
- is->fread(&tmpfloat, sizeof(float));
- for (int j = 0; j < 3; ++j)
- //OSREAD(tmpu8);
- is->fread(&tmpu8, sizeof(uint8_t));
- for (int j = 0; j < 3; ++j)
- //OSREAD(tmpfloat);
- is->fread(&tmpfloat, sizeof(float));
- }
- //OSREAD(polylist->count);
- //OSREAD(tmpint);
- is->fread(&tmpint, sizeof(int));
- //for(int i=0;i<polylist->count;i++)
- for (int i = 0; i < tmpint; ++i)
- {
- //polylist->list[i].load(is);
- int tmpint2;
- uint16_t tmpu16;
- uint32_t tmpu32;
- float tmpfloat;
- //OSREAD(tmpint2);
- is->fread(&tmpint2, sizeof(int));
- for (int j = 0; j < 4; ++j)
- //OSREAD(tmpu16);
- is->fread(&tmpu16, sizeof(uint16_t));
- for (int j = 0; j < 4; ++j)
- //OSREAD(tmpu32);
- is->fread(&tmpu32, sizeof(uint32_t));
- for (int j = 0; j < 2; ++j)
- //OSREAD(tmpfloat);
- is->fread(&tmpfloat, sizeof(float));
- }
- }
-
- if(version>=2)
- {
- for(int i=0;i<4;i++)
- {
- uint32_t tmpu32;
- //OSREAD(mtxStack[i].position);
- //OSREAD(tmpu32);
- is->fread(&tmpu32, sizeof(uint32_t));*/
- /*for(int j=0;j<mtxStack[i].size*16;j++)
- OSREAD(mtxStack[i].matrix[j]);*/
- //if (!i || i == 3)
- /*for (int j = 0; j < (!i || i == 3 ? 1 : 31) * 16; ++j)
- //OSREAD(tmpu32)
- is->fread(&tmpu32, sizeof(uint32_t));
- //else
- //for (int j = 0; j < 31 * 16; ++j)
- //OSREAD(tmpu32);
- }
- }
-
- if(version>=3) {
- fake_gfx_hardware_loadstate(is);
- }*/
-
- /*gfx3d.polylist = &polylists[listTwiddle^1];
- gfx3d.vertlist = &vertlists[listTwiddle^1];
- gfx3d.polylist->count=0;
- gfx3d.vertlist->count=0;*/
-
- /*if(version >= 4)
- {
- uint32_t tmpu32_array16[16];
- //OSREAD(cacheLightDirection);
- //OSREAD(tmpu32_array16);
- is->fread(tmpu32_array16, sizeof(tmpu32_array16));
- //OSREAD(cacheHalfVector);
- //OSREAD(tmpu32_array16);
- is->fread(tmpu32_array16, sizeof(tmpu32_array16));
- }
-
- return true;
-}*/
-
-//static void fake_MovieRecord_parsePad(EMUFILE* fp/*, uint16_t& pad*/)
-/*{
-
- char buf[13];
- fp->fread(buf,13);*/
- /*pad = 0;
- for(int i=0;i<13;i++)
- {
- pad <<= 1;
- pad |= ((buf[i]=='.'||buf[i]==' ')?0:1);
- }*/
-//}
-
-/*static void fake_MovieRecord_parse(MovieData* md, EMUFILE* fp)
-{
- //by the time we get in here, the initial pipe has already been extracted
-
- //extract the commands
- uint8_t tmpu8 = u32DecFromIstream(fp);
-
- fp->fgetc(); //eat the pipe
-
- fake_MovieRecord_parsePad(fp*//*, pad*///);
- /*touch.x*///tmpu8 = u32DecFromIstream(fp);
- /*touch.y*///tmpu8 = u32DecFromIstream(fp);
- /*touch.touch*///tmpu8 = u32DecFromIstream(fp);
-
- /*fp->fgetc(); //eat the pipe
-
- //should be left at a newline
-}*/
-
-/*static bool fake_LoadFM2(MovieData& movieData, EMUFILE* fp, int size, bool stopAfterHeader)
-{
- //TODO - start with something different. like 'desmume movie version 1"
- int curr = fp->ftell();
-
- //movie must start with "version 1"
- char buf[9];
- curr = fp->ftell();
- fp->fread(buf,9);
- fp->fseek(curr, SEEK_SET);
-// if(fp->fail()) return false;
- if(memcmp(buf,"version 1",9))
- return false;
-
- std::string key,value;
- enum {
- NEWLINE, KEY, SEPARATOR, VALUE, RECORD, COMMENT
- } state = NEWLINE;
- bool bail = false;
- for(;;)
- {
- bool iswhitespace, isrecchar, isnewline;
- int c;
- if(size--<=0) goto bail;
- c = fp->fgetc();
- if(c == -1)
- goto bail;
- iswhitespace = (c==' '||c=='\t');
- isrecchar = (c=='|');
- isnewline = (c==10||c==13);
- if(isrecchar && movieData.binaryFlag && !stopAfterHeader)
- {
- LoadFM2_binarychunk(movieData, fp, size);
- return true;
- }
- switch(state)
- {
- case NEWLINE:
- if(isnewline) goto done;
- if(iswhitespace) goto done;
- if(isrecchar)
- goto dorecord;
- //must be a key
- key = "";
- value = "";
- goto dokey;
- break;
- case RECORD:
- {
- dorecord:
- if (stopAfterHeader) return true;
- //int currcount = movieData.records.size();
- //movieData.records.resize(currcount+1);
- int preparse = fp->ftell();
- //movieData.records[currcount].parse(&movieData, fp);
- fake_MovieRecord_parse(fp);
- int postparse = fp->ftell();
- size -= (postparse-preparse);
- state = NEWLINE;
- break;
- }
-
- case KEY:
- dokey: //dookie
- state = KEY;
- if(iswhitespace) goto doseparator;
- if(isnewline) goto commit;
- key += c;
- break;
- case SEPARATOR:
- doseparator:
- state = SEPARATOR;
- if(isnewline) goto commit;
- if(!iswhitespace) goto dovalue;
- break;
- case VALUE:
- dovalue:
- state = VALUE;
- if(isnewline) goto commit;
- value += c;
- break;
- case COMMENT:
- default:
- break;
- }
- goto done;
-
- bail:
- bail = true;
- if(state == VALUE) goto commit;
- goto done;
- commit:
- //movieData.installValue(key,value);
- state = NEWLINE;
- done: ;
- if(bail) break;
- }
-
- return true;
-}*/
-
-/*static bool fake_mov_loadstate(EMUFILE* fp, int size)
-{
- //load_successful = false;
- static const int kMOVI = 0x49564F4D;
- static const int kNOMO = 0x4F4D4F4E;
-
- uint32_t cookie;
- if(read32le(&cookie,fp) != 1) return false;
- if(cookie == kNOMO)
- {*/
- /*if(movieMode == MOVIEMODE_RECORD || movieMode == MOVIEMODE_PLAY)
- FinishPlayback();*/
- /*return true;
- }
- else if(cookie != kMOVI)
- return false;
-
- size -= 4;*/
-
- /*if (!movie_readonly && autoMovieBackup && freshMovie) //If auto-backup is on, movie has not been altered this session and the movie is in read+write mode
- {
- FCEUI_MakeBackupMovie(false); //Backup the movie before the contents get altered, but do not display messages
- }*/
-
- //a little rule: cant load states in read+write mode with a movie from an archive.
- //so we are going to switch it to readonly mode in that case
-// if(!movie_readonly
-// //*&& FCEU_isFileInArchive(curMovieFilename)*/
-// ) {
-// FCEU_PrintError("Cannot loadstate in Read+Write with movie from archive. Movie is now Read-Only.");
-// movie_readonly = true;
-// }
-
- //MovieData tempMovieData = MovieData();
- //int curr = fp->ftell();
- //if(!LoadFM2(tempMovieData, fp, size, false)) {
- /*if (!fake_LoadFM2(fp, size, false)) {*/
-
- // is->seekg((uint32_t)curr+size);
- /* extern bool FCEU_state_loading_old_format;
- if(FCEU_state_loading_old_format) {
- if(movieMode == MOVIEMODE_PLAY || movieMode == MOVIEMODE_RECORD) {
- FCEUI_StopMovie();
- FCEU_PrintError("You have tried to use an old savestate while playing a movie. This is unsupported (since the old savestate has old-format movie data in it which can't be converted on the fly)");
- }
- }*/
- /*return false;
- }*/
-
- //complex TAS logic for when a savestate is loaded:
- //----------------
- //if we are playing or recording and toggled read-only:
- // then, the movie we are playing must match the guid of the one stored in the savestate or else error.
- // the savestate is assumed to be in the same timeline as the current movie.
- // if the current movie is not long enough to get to the savestate's frame#, then it is an error.
- // the movie contained in the savestate will be discarded.
- // the emulator will be put into play mode.
- //if we are playing or recording and toggled read+write
- // then, the movie we are playing must match the guid of the one stored in the savestate or else error.
- // the movie contained in the savestate will be loaded into memory
- // the frames in the movie after the savestate frame will be discarded
- // the in-memory movie will have its rerecord count incremented
- // the in-memory movie will be dumped to disk as fcm.
- // the emulator will be put into record mode.
- //if we are doing neither:
- // then, we must discard this movie and just load the savestate
-
-
- /*if(movieMode != MOVIEMODE_INACTIVE)
- {
- //handle moviefile mismatch
- if(tempMovieData.guid != currMovieData.guid)
- {
- //mbg 8/18/08 - this code can be used to turn the error message into an OK/CANCEL
- #ifdef WIN32
- //std::string msg = "There is a mismatch between savestate's movie and current movie.\ncurrent: " + currMovieData.guid.toString() + "\nsavestate: " + tempMovieData.guid.toString() + "\n\nThis means that you have loaded a savestate belonging to a different movie than the one you are playing now.\n\nContinue loading this savestate anyway?";
- //extern HWND pwindow;
- //int result = MessageBox(pwindow,msg.c_str(),"Error loading savestate",MB_OKCANCEL);
- //if(result == IDCANCEL)
- // return false;
- #else
- FCEU_PrintError("Mismatch between savestate's movie and current movie.\ncurrent: %s\nsavestate: %s\n",currMovieData.guid.toString().c_str(),tempMovieData.guid.toString().c_str());
- return false;
- #endif
- }
-
- closeRecordingMovie();
-
- if(!movie_readonly)
- {
- currMovieData = tempMovieData;
- currMovieData.rerecordCount = currRerecordCount;
- }
-
- if(currFrameCounter > (int)currMovieData.records.size())
- {
- // if the frame counter is longer than our current movie,
- // switch to "finished" mode.
- // this is a mode that behaves like "inactive"
- // except it permits switching to play/record by loading an earlier savestate.
- // (and we continue to store the finished movie in savestates made while finished)
- osd->setLineColor(255,0,0); // let's make the text red too to hopefully catch the user's attention a bit.
- FinishPlayback();
- osd->setLineColor(255,255,255);
-
- //FCEU_PrintError("Savestate is from a frame (%d) after the final frame in the movie (%d). This is not permitted.", currFrameCounter, currMovieData.records.size()-1);
- //return false;
- }
- else if(movie_readonly)
- {
- //-------------------------------------------------------------
- //this code would reload the movie from disk. allegedly it is helpful to hexers, but
- //it is way too slow with dsm format. so it is only here as a reminder, and in case someone
- //wants to play with it
- //-------------------------------------------------------------
- //{
- // fstream fs (curMovieFilename);
- // if(!LoadFM2(tempMovieData, &fs, INT_MAX, false))
- // {
- // FCEU_PrintError("Failed to reload DSM after loading savestate");
- // }
- // fs.close();
- // currMovieData = tempMovieData;
- //}
- //-------------------------------------------------------------
-
- movieMode = MOVIEMODE_PLAY;
- }
- else
- {
- // #ifdef _S9XLUA_H
- // if(!FCEU_LuaRerecordCountSkip())
- currRerecordCount++;
- // #endif
-
- currMovieData.rerecordCount = currRerecordCount;
- currMovieData.truncateAt(currFrameCounter);
-
- openRecordingMovie(curMovieFilename);
- if(!osRecordingMovie)
- {
- osd->setLineColor(255, 0, 0);
- osd->addLine("Can't save movie file!");
- }
-
- //printf("DUMPING MOVIE: %d FRAMES\n",currMovieData.records.size());
- currMovieData.dump(osRecordingMovie, false);
- movieMode = MOVIEMODE_RECORD;
- }
- }
-
- load_successful = true;
- freshMovie = false;*/
-
- //// Maximus: Show the last input combination entered from the
- //// movie within the state
- //if(current!=0) // <- mz: only if playing or recording a movie
- // memcpy(&cur_input_display, joop, 4);
-
- /*return true;
-}*/
-
-static bool ReadStateChunks(EMUFILE* is, int32_t totalsize)
-{
- bool ret = true;
- while(totalsize > 0)
- {
- uint32_t size;
- uint32_t t;
- if(!read32le(&t,is)) { ret=false; break; }
- if(t == 0xFFFFFFFF) goto done;
- if(!read32le(&size,is)) { ret=false; break; }
- switch(t)
- {
- case 1: if(!ReadStateChunk(is,SF_ARM9,size)) ret=false; break;
- case 2: if(!ReadStateChunk(is,SF_ARM7,size)) ret=false; break;
- case 3: if(!cp15_loadstate(is,size)) ret=false; break;
- case 4: if(!ReadStateChunk(is,SF_MEM,size)) ret=false; break;
- case 5: if(!ReadStateChunk(is,SF_NDS,size)) ret=false; break;
- case 51: if(!nds_loadstate(is,size)) ret=false; break;
- case 60: if(!ReadStateChunk(is,SF_MMU,size)) ret=false; break;
- case 61: if(!mmu_loadstate(is,size)) ret=false; break;
- case 7: /*if(!fake_gpu_loadstate(is,size)) ret=false;*/ break;
- case 8: if(!spu_loadstate(is,size)) ret=false; break;
- case 81:/* if(!fake_mic_loadstate(is,size)) ret=false; break;*/
- case 90:/* if(!ReadStateChunk(is,SF_GFX3D,size)) ret=false; break;*/
- case 91:/* if(!fake_gfx3d_loadstate(is,size)) ret=false; break;*/
- case 100:/* if(!ReadStateChunk(is,SF_MOVIE, size)) ret=false; break;*/
- case 101:/* if(!fake_mov_loadstate(is, size)) ret=false; break;*/
- case 110:/* if(!ReadStateChunk(is,SF_WIFI,size)) ret=false; break;*/
- case 120:/* if(!ReadStateChunk(is,SF_RTC,size)) ret=false;*/ break;
- default:
- ret=false;
- break;
- }
- if(!ret)
- return false;
- }
-done:
-
- return ret;
-}
-
-void loadstate()
-{
- // This should regenerate the vram banks
- for (int i = 0; i < 0xA; i++)
- _MMU_write08<ARMCPU_ARM9>(0x04000240+i, _MMU_read08<ARMCPU_ARM9>(0x04000240+i));
-
- // This should regenerate the graphics power control register
- _MMU_write16<ARMCPU_ARM9>(0x04000304, _MMU_read16<ARMCPU_ARM9>(0x04000304));
-
- // This should regenerate the graphics configuration
- //zero 27-jul-09 : was formerly up to 7F but that wrote to dispfifo which is dumb (one of nitsuja's desynch bugs [that he found, not caused])
- //so then i brought it down to 66 but this resulted in a conceptual bug with affine start registers, which shouldnt get regenerated
- //so then i just made this exhaustive list
- // for (int i = REG_BASE_DISPA; i<=REG_BASE_DISPA + 0x66; i+=2)
- //_MMU_write16<ARMCPU_ARM9>(i, _MMU_read16<ARMCPU_ARM9>(i));
- // for (int i = REG_BASE_DISPB; i<=REG_BASE_DISPB + 0x7F; i+=2)
- //_MMU_write16<ARMCPU_ARM9>(i, _MMU_read16<ARMCPU_ARM9>(i));
- static const uint8_t mainRegenAddr[] = {0x00,0x02,0x08,0x0a,0x0c,0x0e,0x40,0x42,0x44,0x46,0x48,0x4a,0x4c,0x50,0x52,0x54,0x64,0x66,0x6c};
- static const uint8_t subRegenAddr[] = {0x00,0x02,0x08,0x0a,0x0c,0x0e,0x40,0x42,0x44,0x46,0x48,0x4a,0x4c,0x50,0x52,0x54,0x6c};
- for(uint32_t i=0;i<ARRAY_SIZE(mainRegenAddr);i++)
- _MMU_write16<ARMCPU_ARM9>(REG_BASE_DISPA+mainRegenAddr[i], _MMU_read16<ARMCPU_ARM9>(REG_BASE_DISPA+mainRegenAddr[i]));
- for(uint32_t i=0;i<ARRAY_SIZE(subRegenAddr);i++)
- _MMU_write16<ARMCPU_ARM9>(REG_BASE_DISPB+subRegenAddr[i], _MMU_read16<ARMCPU_ARM9>(REG_BASE_DISPB+subRegenAddr[i]));
- // no need to restore 0x60 since control and MMU.ARM9_REG are both in the savestates, and restoring it could mess up the ack bits anyway
-
- SetupMMU(/*nds.Is_DebugConsole()*/false,nds.Is_DSI());
-
- //execute = !driver->EMU_IsEmulationPaused();
- execute = true;
-}
-
-bool savestate_load(EMUFILE* is)
-{
- SAV_silent_fail_flag = false;
- char header[16];
- is->fread(header,16);
- if(is->fail() || memcmp(header,magic,16))
- return false;
-
- uint32_t ssversion,dversion,len,comprlen;
- if(!read32le(&ssversion,is)) return false;
- if(!read32le(&dversion,is)) return false;
- if(!read32le(&len,is)) return false;
- if(!read32le(&comprlen,is)) return false;
-
- if(ssversion != SAVESTATE_VERSION) return false;
-
- std::vector<uint8_t> buf(len);
-
- if(comprlen != 0xFFFFFFFF) {
-#ifndef HAVE_LIBZ
- //without libz, we can't decompress this savestate
- return false;
-#endif
- std::vector<char> cbuf(comprlen);
- is->fread(&cbuf[0],comprlen);
- if(is->fail()) return false;
-
-#ifdef HAVE_LIBZ
- uLongf uncomprlen = len;
- int error = uncompress((uint8_t*)&buf[0],&uncomprlen,(uint8_t*)&cbuf[0],comprlen);
- if(error != Z_OK || uncomprlen != len)
- return false;
-#endif
- } else {
- is->fread((char*)&buf[0],len-32);
- }
-
- //GO!! READ THE SAVESTATE
- //THERE IS NO GOING BACK NOW
- //reset the emulator first to clean out the host's state
-
- //while the series of resets below should work,
- //we are testing the robustness of the savestate system with this full reset.
- //the full reset wipes more things, so we can make sure that they are being restored correctly
- //extern bool _HACK_DONT_STOPMOVIE;
- //_HACK_DONT_STOPMOVIE = true;
- NDS_Reset();
- //_HACK_DONT_STOPMOVIE = false;
-
- //reset some options to their old defaults which werent saved
- //nds.debugConsole = false;
-
- //GPU_Reset(MainScreen.gpu, 0);
- //GPU_Reset(SubScreen.gpu, 1);
- //gfx3d_reset();
- //gpu3D->NDS_3D_Reset();
- //SPU_Reset();
-
- EMUFILE_MEMORY mstemp(&buf);
- bool x = ReadStateChunks(&mstemp,(int32_t)len);
-
- if(!x && !SAV_silent_fail_flag)
- {
- printf("Error loading savestate. It failed halfway through;\nSince there is no savestate backup system, your current game session is wrecked");
-#ifdef _WINDOWS
- //HACK! we really need a better way to handle this kind of feedback
- MessageBoxA(0,"Error loading savestate. It failed halfway through;\nSince there is no savestate backup system, your current game session is wrecked",0,0);
-#endif
- return false;
- }
-
- loadstate();
-
- /*if((nds.debugConsole!=0) != CommonSettings.DebugConsole) {
- printf("WARNING: forcing console debug mode to: debugmode=%s\n",nds.debugConsole?"true":"false");
- }*/
-
- return true;
-}
-
-/*bool savestate_load(const char *file_name)
-{
- EMUFILE_FILE f(file_name,"rb");
- if(f.fail()) return false;
-
- return savestate_load(&f);
-}*/
-
-//static std::stack<EMUFILE_MEMORY*> rewindFreeList;
-//static std::vector<EMUFILE_MEMORY*> rewindbuffer;
-
-//int rewindstates = 16;
-//int rewindinterval = 4;
-
-/*void rewindsave () {*/
-
- /*if(currFrameCounter % rewindinterval)
- return;*/
-
- //printf("rewindsave"); printf("%d%s", currFrameCounter, "\n");
-
-
- /*EMUFILE_MEMORY *ms;
- if(!rewindFreeList.empty()) {
- ms = rewindFreeList.top();
- rewindFreeList.pop();
- } else {
- ms = new EMUFILE_MEMORY(1024*1024*12);
- }
-
- if(!savestate_save(ms, Z_NO_COMPRESSION))
- return;
-
- rewindbuffer.push_back(ms);
-
- if((int)rewindbuffer.size() > rewindstates) {
- delete *rewindbuffer.begin();
- rewindbuffer.erase(rewindbuffer.begin());
- }
-}*/
-
-/*void dorewind()
-{*/
-
- /*if(currFrameCounter % rewindinterval)
- return;*/
-
- //printf("rewind\n");
-
- /*nds.debugConsole = false;
-
- int size = rewindbuffer.size();
-
- if(size < 1) {
- printf("rewind buffer empty\n");
- return;
- }
-
- printf("%d", size);
-
- EMUFILE_MEMORY* loadms = rewindbuffer[size-1];
- loadms->fseek(32, SEEK_SET);
-
- ReadStateChunks(loadms,loadms->size()-32);
- loadstate();
-
- if(rewindbuffer.size()>1)
- {
- rewindFreeList.push(loadms);
- rewindbuffer.pop_back();
- }
-
-}*/
-
--- a/src/in_2sf/desmume/saves.h
+++ /dev/null
@@ -1,76 +1,1 @@
-/*
- Copyright (C) 2006 Normmatt
- Copyright (C) 2007 Pascal Giard
- Copyright (C) 2007-2012 DeSmuME team
- This file is free software: you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation, either version 2 of the License, or
- (at your option) any later version.
-
- This file is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with the this software. If not, see <http://www.gnu.org/licenses/>.
-*/
-
-#ifndef _SRAM_H
-#define _SRAM_H
-
-#include "types.h"
-
-#define SRAM_ADDRESS 0x0A000000
-#define SRAM_SIZE 0x10000
-#define NB_STATES 10
-
-//extern int lastSaveState;
-
-/*typedef struct
-{
- bool exists;
- char date[40];
-} savestates_t;*/
-
-
-struct SFORMAT
-{
- //a string description of the element
- const char *desc;
-
- //the size of each element
- uint32_t size;
-
- //the number of each element
- uint32_t count;
-
- //a void* to the data or a void** to the data
- void *v;
-};
-
-//extern savestates_t savestates[NB_STATES];
-
-//void clear_savestates();
-//void scan_savestates();
-uint8_t sram_read (uint32_t address);
-void sram_write (uint32_t address, uint8_t value);
-int sram_load (const char *file_name);
-int sram_save (const char *file_name);
-
-//bool savestate_load (const char *file_name);
-//bool savestate_save (const char *file_name);
-
-//void savestate_slot(int num);
-//void loadstate_slot(int num);
-
-void loadstate();
-bool savestate_load(class EMUFILE* is);
-//bool savestate_save(class EMUFILE* outstream, int compressionLevel);
-
-//void dorewind();
-//void rewindsave();
-
-#endif
-
--- a/src/in_2sf/desmume/slot1.cpp
+++ b/src/in_2sf/desmume/slot1.cpp
@@ -15,45 +15,9 @@
along with the this software. If not, see <http://www.gnu.org/licenses/>.
*/
-//#include <string>
-
#include "slot1.h"
-//extern SLOT1INTERFACE slot1None;
extern SLOT1INTERFACE slot1Retail;
-//extern SLOT1INTERFACE slot1R4;
-SLOT1INTERFACE slot1List[NDS_SLOT1_COUNT] = {
- //slot1None,
- slot1Retail,
- //slot1R4
-};
+SLOT1INTERFACE slot1_device = slot1Retail; // default for frontends that dont even configure this
-SLOT1INTERFACE slot1_device = slot1Retail; //default for frontends that dont even configure this
-//uint8_t slot1_device_type = NDS_SLOT1_RETAIL;
-
-/*bool slot1Init()
-{
- return slot1_device.init();
-}*/
-
-/*void slot1Close()
-{
- slot1_device.close();
-}*/
-
-/*void slot1Reset()
-{
- slot1_device.reset();
-}*/
-
-/*bool slot1Change(NDS_SLOT1_TYPE changeToType)
-{
- printf("slot1Change to: %d\n", changeToType);
- if (changeToType > NDS_SLOT1_COUNT || changeToType < 0) return false;
- slot1_device.close();
- slot1_device_type = changeToType;
- slot1_device = slot1List[slot1_device_type];
- return slot1_device.init();
-}*/
-
--- a/src/in_2sf/desmume/slot1.h
+++ b/src/in_2sf/desmume/slot1.h
@@ -18,55 +18,46 @@
#ifndef __SLOT1_H__
#define __SLOT1_H__
-#include "common.h"
#include "types.h"
-//#include "debug.h"
struct SLOT1INTERFACE
{
// The name of the plugin, this name will appear in the plugins list
- const char * name;
+ const char *name;
- //called once when the plugin starts up
+ // called once when the plugin starts up
bool (*init)();
- //called when the emulator resets
+ // called when the emulator resets
void (*reset)();
- //called when the plugin shuts down
+ // called when the plugin shuts down
void (*close)();
- //called when the user configurating plugin
+ // called when the user configurating plugin
void (*config)();
- //called when the emulator write to addon
+ // called when the emulator write to addon
void (*write08)(uint8_t PROCNUM, uint32_t adr, uint8_t val);
void (*write16)(uint8_t PROCNUM, uint32_t adr, uint16_t val);
void (*write32)(uint8_t PROCNUM, uint32_t adr, uint32_t val);
- //called when the emulator read from addon
+ // called when the emulator read from addon
uint8_t (*read08)(uint8_t PROCNUM, uint32_t adr);
uint16_t (*read16)(uint8_t PROCNUM, uint32_t adr);
uint32_t (*read32)(uint8_t PROCNUM, uint32_t adr);
- //called when the user get info about addon pak (description)
+ // called when the user get info about addon pak (description)
void (*info)(char *info);
};
-extern SLOT1INTERFACE slot1_device; // current slot1 device
+extern SLOT1INTERFACE slot1_device; // current slot1 device
enum NDS_SLOT1_TYPE
{
- //NDS_SLOT1_NONE,
NDS_SLOT1_RETAIL,
- //NDS_SLOT1_R4,
- NDS_SLOT1_COUNT // use for counter addons - MUST TO BE LAST!!!
+ NDS_SLOT1_COUNT // use for counter addons - MUST TO BE LAST!!!
};
-//extern bool slot1Init();
-//extern void slot1Close();
-//extern void slot1Reset();
-//extern bool slot1Change(NDS_SLOT1_TYPE type); // change current adddon
+#endif // __ADDONS_H__
-#endif //__ADDONS_H__
-
--- a/src/in_2sf/desmume/thumb_instructions.cpp
+++ b/src/in_2sf/desmume/thumb_instructions.cpp
@@ -1,7 +1,7 @@
/*
Copyright (C) 2006 yopyop
Copyright (C) 2008 shash
- Copyright (C) 2008-2012 DeSmuME team
+ Copyright (C) 2008-2013 DeSmuME team
This file is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -20,22 +20,19 @@
#include <cassert>
#include "bios.h"
-//#include "debug.h"
#include "MMU.h"
#include "NDSSystem.h"
-#include "thumb_instructions.h"
#include "MMU_timing.h"
#define cpu (&ARMPROC)
#define TEMPLATE template<int PROCNUM>
-//#define REG_NUM(i, n) (((i)>>n)&0x7)
static inline uint32_t REG_NUM(uint32_t i, uint32_t n) { return (i >> n) & 0x7; }
//-----------------------------------------------------------------------------
// Undefined instruction
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_UND_THUMB(const uint32_t)
+TEMPLATE static uint32_t FASTCALL OP_UND_THUMB(uint32_t)
{
//INFO("THUMB%c: Undefined instruction: 0x%08X (%s) PC=0x%08X\n", cpu->proc_ID?'7':'9', cpu->instruction, decodeIntruction(true, cpu->instruction), cpu->instruct_adr);
TRAPUNDEF(cpu);
@@ -46,45 +43,45 @@
// LSL
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_LSL_0(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LSL_0(uint32_t i)
{
cpu->R[REG_NUM(i, 0)] = cpu->R[REG_NUM(i, 3)];
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
-
- return 1;
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LSL(const uint32_t i)
-{
- uint32_t v = (i>>6) & 0x1F;
- cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 3)], 32-v);
- cpu->R[REG_NUM(i, 0)] = (cpu->R[REG_NUM(i, 3)] << v);
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
-
- return 1;
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LSL_REG(const uint32_t i)
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
+
+ return 1;
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LSL(uint32_t i)
+{
+ uint32_t v = (i >> 6) & 0x1F;
+ cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 3)], 32 - v);
+ cpu->R[REG_NUM(i, 0)] = cpu->R[REG_NUM(i, 3)] << v;
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
+
+ return 1;
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LSL_REG(uint32_t i)
{
uint32_t v = cpu->R[REG_NUM(i, 3)] & 0xFF;
- if(v == 0)
+ if (!v)
{
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
return 2;
}
- if(v<32)
- {
- cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 0)], 32-v);
+ if (v < 32)
+ {
+ cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 0)], 32 - v);
cpu->R[REG_NUM(i, 0)] <<= v;
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
return 2;
}
- if(v==32)
+ if (v == 32)
cpu->CPSR.bits.C = BIT0(cpu->R[REG_NUM(i, 0)]);
else
cpu->CPSR.bits.C = 0;
@@ -100,7 +97,7 @@
// LSR
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_LSR_0(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LSR_0(uint32_t i)
{
cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 3)]);
cpu->R[REG_NUM(i, 0)] = 0;
@@ -110,39 +107,40 @@
return 1;
}
-TEMPLATE static uint32_t FASTCALL OP_LSR(const uint32_t i)
-{
- uint32_t v = (i>>6) & 0x1F;
- cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 3)], v-1);
- cpu->R[REG_NUM(i, 0)] = (cpu->R[REG_NUM(i, 3)] >> v);
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
-
- return 1;
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LSR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LSR(uint32_t i)
+{
+ uint32_t v = (i >> 6) & 0x1F;
+ cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 3)], v - 1);
+ cpu->R[REG_NUM(i, 0)] = cpu->R[REG_NUM(i, 3)] >> v;
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
+
+ return 1;
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LSR_REG(uint32_t i)
{
uint32_t v = cpu->R[REG_NUM(i, 3)] & 0xFF;
- if(v == 0)
+ if (!v)
{
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
return 2;
}
- if(v<32)
- {
- cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 0)], v-1);
+ if (v < 32)
+ {
+ cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 0)], v - 1);
cpu->R[REG_NUM(i, 0)] >>= v;
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
return 2;
}
- if(v==32)
+ if (v == 32)
cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 0)]);
else
cpu->CPSR.bits.C = 0;
+
cpu->R[REG_NUM(i, 0)] = 0;
cpu->CPSR.bits.N = 0;
cpu->CPSR.bits.Z = 1;
@@ -154,50 +152,50 @@
// ASR
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_ASR_0(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ASR_0(uint32_t i)
{
cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 3)]);
- cpu->R[REG_NUM(i, 0)] = BIT31(cpu->R[REG_NUM(i, 3)])*0xFFFFFFFF;
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
-
- return 1;
-}
-
-TEMPLATE static uint32_t FASTCALL OP_ASR(const uint32_t i)
-{
- uint32_t v = (i>>6) & 0x1F;
+ cpu->R[REG_NUM(i, 0)] = BIT31(cpu->R[REG_NUM(i, 3)]) * 0xFFFFFFFF;
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
+
+ return 1;
+}
+
+TEMPLATE static uint32_t FASTCALL OP_ASR(uint32_t i)
+{
+ uint32_t v = (i >> 6) & 0x1F;
cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 3)], v-1);
- cpu->R[REG_NUM(i, 0)] = (uint32_t)(((int32_t)cpu->R[REG_NUM(i, 3)]) >> v);
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
-
- return 1;
-}
-
-TEMPLATE static uint32_t FASTCALL OP_ASR_REG(const uint32_t i)
+ cpu->R[REG_NUM(i, 0)] = static_cast<uint32_t>(static_cast<int32_t>(cpu->R[REG_NUM(i, 3)]) >> v);
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
+
+ return 1;
+}
+
+TEMPLATE static uint32_t FASTCALL OP_ASR_REG(uint32_t i)
{
uint32_t v = cpu->R[REG_NUM(i, 3)] & 0xFF;
- if(v == 0)
+ if (!v)
{
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
return 2;
}
- if(v<32)
- {
- cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 0)], v-1);
- cpu->R[REG_NUM(i, 0)] = (uint32_t)(((int32_t)cpu->R[REG_NUM(i, 0)]) >> v);
+ if (v < 32)
+ {
+ cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 0)], v - 1);
+ cpu->R[REG_NUM(i, 0)] = static_cast<uint32_t>(static_cast<int32_t>(cpu->R[REG_NUM(i, 0)]) >> v);
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
return 2;
}
cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->R[REG_NUM(i, 0)] = BIT31(cpu->R[REG_NUM(i, 0)])*0xFFFFFFFF;
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
+ cpu->R[REG_NUM(i, 0)] = BIT31(cpu->R[REG_NUM(i, 0)]) * 0xFFFFFFFF;
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
return 2;
}
@@ -206,66 +204,65 @@
// ADD
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_ADD_IMM3(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADD_IMM3(uint32_t i)
{
uint32_t imm3 = (i >> 6) & 0x07;
uint32_t Rn = cpu->R[REG_NUM(i, 3)];
- if (imm3 == 0) // mov 2
+ if (!imm3) // mov 2
{
cpu->R[REG_NUM(i, 0)] = Rn;
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
- cpu->CPSR.bits.C = 0;
- cpu->CPSR.bits.V = 0;
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
+ cpu->CPSR.bits.C = cpu->CPSR.bits.V = 0;
return 1;
}
cpu->R[REG_NUM(i, 0)] = Rn + imm3;
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
cpu->CPSR.bits.C = CarryFrom(Rn, imm3);
cpu->CPSR.bits.V = OverflowFromADD(cpu->R[REG_NUM(i, 0)], Rn, imm3);
return 1;
}
-TEMPLATE static uint32_t FASTCALL OP_ADD_IMM8(const uint32_t i)
-{
- uint32_t imm8 = (i & 0xFF);
+TEMPLATE static uint32_t FASTCALL OP_ADD_IMM8(uint32_t i)
+{
+ uint32_t imm8 = i & 0xFF;
uint32_t Rd = cpu->R[REG_NUM(i, 8)];
cpu->R[REG_NUM(i, 8)] = Rd + imm8;
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 8)]);
- cpu->CPSR.bits.Z = (cpu->R[REG_NUM(i, 8)] == 0);
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 8)];
cpu->CPSR.bits.C = CarryFrom(Rd, imm8);
cpu->CPSR.bits.V = OverflowFromADD(cpu->R[REG_NUM(i, 8)], Rd, imm8);
return 1;
}
-TEMPLATE static uint32_t FASTCALL OP_ADD_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADD_REG(uint32_t i)
{
uint32_t Rn = cpu->R[REG_NUM(i, 3)];
uint32_t Rm = cpu->R[REG_NUM(i, 6)];
cpu->R[REG_NUM(i, 0)] = Rn + Rm;
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
cpu->CPSR.bits.C = CarryFrom(Rn, Rm);
cpu->CPSR.bits.V = OverflowFromADD(cpu->R[REG_NUM(i, 0)], Rn, Rm);
return 1;
}
-TEMPLATE static uint32_t FASTCALL OP_ADD_SPE(const uint32_t i)
-{
- uint32_t Rd = REG_NUM(i, 0) | ((i>>4)&8);
+TEMPLATE static uint32_t FASTCALL OP_ADD_SPE(uint32_t i)
+{
+ uint32_t Rd = REG_NUM(i, 0) | ((i >> 4) & 8);
cpu->R[Rd] += cpu->R[REG_POS(i, 3)];
- if(Rd==15)
+ if (Rd == 15)
{
cpu->next_instruction = cpu->R[15];
return 3;
@@ -274,16 +271,16 @@
return 1;
}
-TEMPLATE static uint32_t FASTCALL OP_ADD_2PC(const uint32_t i)
-{
- cpu->R[REG_NUM(i, 8)] = (cpu->R[15]&0xFFFFFFFC) + ((i&0xFF)<<2);
-
- return 1;
-}
-
-TEMPLATE static uint32_t FASTCALL OP_ADD_2SP(const uint32_t i)
-{
- cpu->R[REG_NUM(i, 8)] = cpu->R[13] + ((i&0xFF)<<2);
+TEMPLATE static uint32_t FASTCALL OP_ADD_2PC(uint32_t i)
+{
+ cpu->R[REG_NUM(i, 8)] = (cpu->R[15] & 0xFFFFFFFC) + ((i & 0xFF) << 2);
+
+ return 1;
+}
+
+TEMPLATE static uint32_t FASTCALL OP_ADD_2SP(uint32_t i)
+{
+ cpu->R[REG_NUM(i, 8)] = cpu->R[13] + ((i & 0xFF) << 2);
return 1;
}
@@ -292,37 +289,37 @@
// SUB
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_SUB_IMM3(const uint32_t i)
-{
- uint32_t imm3 = (i>>6) & 0x07;
+TEMPLATE static uint32_t FASTCALL OP_SUB_IMM3(uint32_t i)
+{
+ uint32_t imm3 = (i >> 6) & 0x07;
uint32_t Rn = cpu->R[REG_NUM(i, 3)];
uint32_t tmp = Rn - imm3;
cpu->R[REG_NUM(i, 0)] = tmp;
cpu->CPSR.bits.N = BIT31(tmp);
- cpu->CPSR.bits.Z = (tmp == 0);
+ cpu->CPSR.bits.Z = !tmp;
cpu->CPSR.bits.C = !BorrowFrom(Rn, imm3);
cpu->CPSR.bits.V = OverflowFromSUB(tmp, Rn, imm3);
return 1;
}
-TEMPLATE static uint32_t FASTCALL OP_SUB_IMM8(const uint32_t i)
-{
- uint32_t imm8 = (i & 0xFF);
+TEMPLATE static uint32_t FASTCALL OP_SUB_IMM8(uint32_t i)
+{
+ uint32_t imm8 = i & 0xFF;
uint32_t Rd = cpu->R[REG_NUM(i, 8)];
uint32_t tmp = Rd - imm8;
cpu->R[REG_NUM(i, 8)] = tmp;
cpu->CPSR.bits.N = BIT31(tmp);
- cpu->CPSR.bits.Z = (tmp == 0);
+ cpu->CPSR.bits.Z = !tmp;
cpu->CPSR.bits.C = !BorrowFrom(Rd, imm8);
cpu->CPSR.bits.V = OverflowFromSUB(tmp, Rd, imm8);
return 1;
}
-TEMPLATE static uint32_t FASTCALL OP_SUB_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_SUB_REG(uint32_t i)
{
uint32_t Rn = cpu->R[REG_NUM(i, 3)];
uint32_t Rm = cpu->R[REG_NUM(i, 6)];
@@ -330,7 +327,7 @@
cpu->R[REG_NUM(i, 0)] = tmp;
cpu->CPSR.bits.N = BIT31(tmp);
- cpu->CPSR.bits.Z = (tmp == 0);
+ cpu->CPSR.bits.Z = !tmp;
cpu->CPSR.bits.C = !BorrowFrom(Rn, Rm);
cpu->CPSR.bits.V = OverflowFromSUB(tmp, Rn, Rm);
@@ -341,22 +338,22 @@
// MOV
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_MOV_IMM8(const uint32_t i)
-{
- cpu->R[REG_NUM(i, 8)] = (i & 0xFF);
+TEMPLATE static uint32_t FASTCALL OP_MOV_IMM8(uint32_t i)
+{
+ cpu->R[REG_NUM(i, 8)] = i & 0xFF;
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 8)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 8)] == 0;
-
- return 1;
-}
-
-TEMPLATE static uint32_t FASTCALL OP_MOV_SPE(const uint32_t i)
-{
- uint32_t Rd = REG_NUM(i, 0) | ((i>>4)&8);
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 8)];
+
+ return 1;
+}
+
+TEMPLATE static uint32_t FASTCALL OP_MOV_SPE(uint32_t i)
+{
+ uint32_t Rd = REG_NUM(i, 0) | ((i >> 4) & 8);
cpu->R[Rd] = cpu->R[REG_POS(i, 3)];
- if(Rd==15)
+ if (Rd == 15)
{
cpu->next_instruction = cpu->R[15];
return 3;
@@ -368,38 +365,38 @@
//-----------------------------------------------------------------------------
// CMP
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_CMP_IMM8(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_CMP_IMM8(uint32_t i)
{
uint32_t tmp = cpu->R[REG_NUM(i, 8)] - (i & 0xFF);
cpu->CPSR.bits.N = BIT31(tmp);
- cpu->CPSR.bits.Z = tmp == 0;
- cpu->CPSR.bits.C = !BorrowFrom(cpu->R[REG_NUM(i, 8)], (i & 0xFF));
- cpu->CPSR.bits.V = OverflowFromSUB(tmp, cpu->R[REG_NUM(i, 8)], (i & 0xFF));
-
- return 1;
-}
-
-TEMPLATE static uint32_t FASTCALL OP_CMP(const uint32_t i)
+ cpu->CPSR.bits.Z = !tmp;
+ cpu->CPSR.bits.C = !BorrowFrom(cpu->R[REG_NUM(i, 8)], i & 0xFF);
+ cpu->CPSR.bits.V = OverflowFromSUB(tmp, cpu->R[REG_NUM(i, 8)], i & 0xFF);
+
+ return 1;
+}
+
+TEMPLATE static uint32_t FASTCALL OP_CMP(uint32_t i)
{
uint32_t tmp = cpu->R[REG_NUM(i, 0)] - cpu->R[REG_NUM(i, 3)];
cpu->CPSR.bits.N = BIT31(tmp);
- cpu->CPSR.bits.Z = tmp == 0;
+ cpu->CPSR.bits.Z = !tmp;
cpu->CPSR.bits.C = !BorrowFrom(cpu->R[REG_NUM(i, 0)], cpu->R[REG_NUM(i, 3)]);
cpu->CPSR.bits.V = OverflowFromSUB(tmp, cpu->R[REG_NUM(i, 0)], cpu->R[REG_NUM(i, 3)]);
return 1;
}
-TEMPLATE static uint32_t FASTCALL OP_CMP_SPE(const uint32_t i)
-{
- uint32_t Rn = (i&7) | ((i>>4)&8);
+TEMPLATE static uint32_t FASTCALL OP_CMP_SPE(uint32_t i)
+{
+ uint32_t Rn = (i & 7) | ((i >> 4) & 8);
uint32_t tmp = cpu->R[Rn] - cpu->R[REG_POS(i, 3)];
cpu->CPSR.bits.N = BIT31(tmp);
- cpu->CPSR.bits.Z = tmp == 0;
+ cpu->CPSR.bits.Z = !tmp;
cpu->CPSR.bits.C = !BorrowFrom(cpu->R[Rn], cpu->R[REG_POS(i, 3)]);
cpu->CPSR.bits.V = OverflowFromSUB(tmp, cpu->R[Rn], cpu->R[REG_POS(i, 3)]);
@@ -410,11 +407,11 @@
// AND
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_AND(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_AND(uint32_t i)
{
cpu->R[REG_NUM(i, 0)] &= cpu->R[REG_NUM(i, 3)];
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
return 1;
}
@@ -422,11 +419,11 @@
// EOR
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_EOR(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_EOR(uint32_t i)
{
cpu->R[REG_NUM(i, 0)] ^= cpu->R[REG_NUM(i, 3)];
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
return 1;
}
@@ -435,7 +432,7 @@
// ADC
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_ADC_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ADC_REG(uint32_t i)
{
uint32_t Rd = cpu->R[REG_NUM(i, 0)];
uint32_t Rm = cpu->R[REG_NUM(i, 3)];
@@ -451,7 +448,7 @@
cpu->CPSR.bits.C = cpu->R[REG_NUM(i, 0)] <= Rm;
}
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = (cpu->R[REG_NUM(i, 0)] == 0);
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
cpu->CPSR.bits.V = BIT31((Rd ^ Rm ^ -1) & (Rd ^ cpu->R[REG_NUM(i, 0)]));
return 1;
@@ -460,7 +457,8 @@
//-----------------------------------------------------------------------------
// SBC
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_SBC_REG(const uint32_t i)
+
+TEMPLATE static uint32_t FASTCALL OP_SBC_REG(uint32_t i)
{
uint32_t Rd = cpu->R[REG_NUM(i, 0)];
uint32_t Rm = cpu->R[REG_NUM(i, 3)];
@@ -477,7 +475,7 @@
}
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = (cpu->R[REG_NUM(i, 0)] == 0);
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
cpu->CPSR.bits.V = BIT31((Rd ^ Rm) & (Rd ^ cpu->R[REG_NUM(i, 0)]));
return 1;
@@ -487,29 +485,30 @@
// ROR
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_ROR_REG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ROR_REG(uint32_t i)
{
uint32_t v = cpu->R[REG_NUM(i, 3)] & 0xFF;
- if(v == 0)
- {
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
- return 2;
+ if (!v)
+ {
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
+ return 2;
}
v &= 0x1F;
- if(v == 0)
- {
- cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
- return 2;
- }
- cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 0)], v-1);
+ if (!v)
+ {
+ cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 0)]);
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
+ return 2;
+ }
+
+ cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 0)], v - 1);
cpu->R[REG_NUM(i, 0)] = ROR(cpu->R[REG_NUM(i, 0)], v);
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
return 2;
}
@@ -518,11 +517,11 @@
// TST
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_TST(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_TST(uint32_t i)
{
uint32_t tmp = cpu->R[REG_NUM(i, 0)] & cpu->R[REG_NUM(i, 3)];
cpu->CPSR.bits.N = BIT31(tmp);
- cpu->CPSR.bits.Z = (tmp == 0);
+ cpu->CPSR.bits.Z = !tmp;
return 1;
}
@@ -531,14 +530,14 @@
// NEG
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_NEG(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_NEG(uint32_t i)
{
uint32_t Rm = cpu->R[REG_NUM(i, 3)];
- cpu->R[REG_NUM(i, 0)] = (uint32_t)((int32_t)0 - (int32_t)Rm);
-
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = (cpu->R[REG_NUM(i, 0)] == 0);
+ cpu->R[REG_NUM(i, 0)] = static_cast<uint32_t>(-static_cast<int32_t>(Rm));
+
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
cpu->CPSR.bits.C = !BorrowFrom(0, Rm);
cpu->CPSR.bits.V = OverflowFromSUB(cpu->R[REG_NUM(i, 0)], 0, Rm);
@@ -549,12 +548,12 @@
// CMN
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_CMN(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_CMN(uint32_t i)
{
uint32_t tmp = cpu->R[REG_NUM(i, 0)] + cpu->R[REG_NUM(i, 3)];
cpu->CPSR.bits.N = BIT31(tmp);
- cpu->CPSR.bits.Z = tmp == 0;
+ cpu->CPSR.bits.Z = !tmp;
cpu->CPSR.bits.C = CarryFrom(cpu->R[REG_NUM(i, 0)], cpu->R[REG_NUM(i, 3)]);
cpu->CPSR.bits.V = OverflowFromADD(tmp, cpu->R[REG_NUM(i, 0)], cpu->R[REG_NUM(i, 3)]);
@@ -565,12 +564,12 @@
// ORR
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_ORR(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_ORR(uint32_t i)
{
cpu->R[REG_NUM(i, 0)] |= cpu->R[REG_NUM(i, 3)];
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = (cpu->R[REG_NUM(i, 0)] == 0);
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
return 1;
}
@@ -579,12 +578,12 @@
// BIC
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_BIC(const uint32_t i)
-{
- cpu->R[REG_NUM(i, 0)] &= (~cpu->R[REG_NUM(i, 3)]);
-
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = (cpu->R[REG_NUM(i, 0)] == 0);
+TEMPLATE static uint32_t FASTCALL OP_BIC(uint32_t i)
+{
+ cpu->R[REG_NUM(i, 0)] &= ~cpu->R[REG_NUM(i, 3)];
+
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
return 1;
}
@@ -593,12 +592,12 @@
// MVN
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_MVN(const uint32_t i)
-{
- cpu->R[REG_NUM(i, 0)] = (~cpu->R[REG_NUM(i, 3)]);
-
- cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
+TEMPLATE static uint32_t FASTCALL OP_MVN(uint32_t i)
+{
+ cpu->R[REG_NUM(i, 0)] = ~cpu->R[REG_NUM(i, 3)];
+
+ cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
return 1;
}
@@ -609,17 +608,17 @@
#define MUL_Mxx_END_THUMB(c) \
v >>= 8; \
- if((v==0)||(v==0xFFFFFF)) \
- return c+1; \
+ if (!v || v == 0xFFFFFF) \
+ return c + 1; \
v >>= 8; \
- if((v==0)||(v==0xFFFF)) \
- return c+2; \
+ if (!v || v == 0xFFFF) \
+ return c + 2; \
v >>= 8; \
- if((v==0)||(v==0xFF)) \
- return c+3; \
- return c+4; \
-
-TEMPLATE static uint32_t FASTCALL OP_MUL_REG(const uint32_t i)
+ if (!v || v == 0xFF) \
+ return c + 3; \
+ return c + 4;
+
+TEMPLATE static uint32_t FASTCALL OP_MUL_REG(uint32_t i)
{
uint32_t v = cpu->R[REG_NUM(i, 3)];
@@ -631,12 +630,12 @@
cpu->R[REG_NUM(i, 0)] *= v;
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
- cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
+ cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)];
//The MUL instruction is defined to leave the C flag unchanged in ARMv5 and above.
//In earlier versions of the architecture, the value of the C flag was UNPREDICTABLE
//after a MUL instruction.
- if (!cpu->LDTBit) // ARM4T 1S + mI, m = 3
+ if (PROCNUM == 1) // ARM4T 1S + mI, m = 3
return 4;
MUL_Mxx_END_THUMB(1);
@@ -646,182 +645,179 @@
// STRB / LDRB
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_STRB_IMM_OFF(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_STRB_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_NUM(i, 3)] + ((i >> 6) & 0x1F);
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_NUM(i, 0)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_IMM_OFF(uint32_t i)
{
uint32_t adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F);
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_NUM(i, 0)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2, adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F);
- cpu->R[REG_NUM(i, 0)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3, adr);
-}
-
-
-TEMPLATE static uint32_t FASTCALL OP_STRB_REG_OFF(const uint32_t i)
+ cpu->R[REG_NUM(i, 0)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRB_REG_OFF(uint32_t i)
{
uint32_t adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
- WRITE8(cpu->mem_if->data, adr, (uint8_t)cpu->R[REG_NUM(i, 0)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2, adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRB_REG_OFF(const uint32_t i)
+ WRITE8(cpu->mem_if->data, adr, static_cast<uint8_t>(cpu->R[REG_NUM(i, 0)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRB_REG_OFF(uint32_t i)
{
uint32_t adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
- cpu->R[REG_NUM(i, 0)] = (uint32_t)READ8(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3, adr);
+ cpu->R[REG_NUM(i, 0)] = static_cast<uint32_t>(READ8(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
}
//-----------------------------------------------------------------------------
// LDRSB
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_LDRSB_REG_OFF(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDRSB_REG_OFF(uint32_t i)
{
uint32_t adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
- cpu->R[REG_NUM(i, 0)] = (uint32_t)((int8_t)READ8(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3, adr);
+ cpu->R[REG_NUM(i, 0)] = static_cast<uint32_t>(static_cast<int8_t>(READ8(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 8, MMU_AD_READ>(3, adr);
}
//-----------------------------------------------------------------------------
// STRH / LDRH
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_STRH_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E);
- WRITE16(cpu->mem_if->data, adr, (uint16_t)cpu->R[REG_NUM(i, 0)]);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_WRITE>(2, adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRH_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E);
- cpu->R[REG_NUM(i, 0)] = (uint32_t)READ16(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3, adr);
-}
-
-
-TEMPLATE static uint32_t FASTCALL OP_STRH_REG_OFF(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_STRH_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_NUM(i, 3)] + ((i >> 5) & 0x3E);
+ WRITE16(cpu->mem_if->data, adr, static_cast<uint16_t>(cpu->R[REG_NUM(i, 0)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRH_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_NUM(i, 3)] + ((i >> 5) & 0x3E);
+ cpu->R[REG_NUM(i, 0)] = static_cast<uint32_t>(READ16(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STRH_REG_OFF(uint32_t i)
{
uint32_t adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
- WRITE16(cpu->mem_if->data, adr, ((uint16_t)cpu->R[REG_NUM(i, 0)]));
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_WRITE>(2, adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDRH_REG_OFF(const uint32_t i)
+ WRITE16(cpu->mem_if->data, adr, static_cast<uint16_t>(cpu->R[REG_NUM(i, 0)]));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDRH_REG_OFF(uint32_t i)
{
uint32_t adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
- cpu->R[REG_NUM(i, 0)] = (uint32_t)READ16(cpu->mem_if->data, adr);
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3, adr);
+ cpu->R[REG_NUM(i, 0)] = static_cast<uint32_t>(READ16(cpu->mem_if->data, adr));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
}
//-----------------------------------------------------------------------------
// LDRSH
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_LDRSH_REG_OFF(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDRSH_REG_OFF(uint32_t i)
{
uint32_t adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
- cpu->R[REG_NUM(i, 0)] = (uint32_t)((int16_t)READ16(cpu->mem_if->data, adr));
-
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3, adr);
+ cpu->R[REG_NUM(i, 0)] = static_cast<uint32_t>(static_cast<int16_t>(READ16(cpu->mem_if->data, adr)));
+
+ return MMU_aluMemAccessCycles<PROCNUM, 16, MMU_AD_READ>(3, adr);
}
//-----------------------------------------------------------------------------
// STR / LDR
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_STR_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C);
+TEMPLATE static uint32_t FASTCALL OP_STR_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_NUM(i, 3)] + ((i >> 4) & 0x7C);
WRITE32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 0)]);
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2, adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDR_IMM_OFF(const uint32_t i)
-{
- uint32_t adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C);
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDR_IMM_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_NUM(i, 3)] + ((i >> 4) & 0x7C);
uint32_t tempValue = READ32(cpu->mem_if->data, adr);
- adr = (adr&3)*8;
- tempValue = (tempValue>>adr) | (tempValue<<(32-adr));
+ adr = (adr & 3) * 8;
+ tempValue = (tempValue >> adr) | (tempValue << (32 - adr));
cpu->R[REG_NUM(i, 0)] = tempValue;
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_READ>(3, adr);
-}
-
-
-TEMPLATE static uint32_t FASTCALL OP_STR_REG_OFF(const uint32_t i)
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_REG_OFF(uint32_t i)
{
uint32_t adr = cpu->R[REG_NUM(i, 6)] + cpu->R[REG_NUM(i, 3)];
WRITE32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 0)]);
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2, adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDR_REG_OFF(const uint32_t i)
-{
- uint32_t adr = (cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]);
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDR_REG_OFF(uint32_t i)
+{
+ uint32_t adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
uint32_t tempValue = READ32(cpu->mem_if->data, adr);
- adr = (adr&3)*8;
- tempValue = (tempValue>>adr) | (tempValue<<(32-adr));
+ adr = (adr & 3) * 8;
+ tempValue = (tempValue >> adr) | (tempValue << (32 - adr));
cpu->R[REG_NUM(i, 0)] = tempValue;
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_READ>(3, adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_STR_SPREL(const uint32_t i)
-{
- uint32_t adr = cpu->R[13] + ((i&0xFF)<<2);
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_STR_SPREL(uint32_t i)
+{
+ uint32_t adr = cpu->R[13] + ((i & 0xFF) << 2);
WRITE32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 8)]);
- return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_WRITE>(2, adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDR_SPREL(const uint32_t i)
-{
- uint32_t adr = cpu->R[13] + ((i&0xFF)<<2);
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(2, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDR_SPREL(uint32_t i)
+{
+ uint32_t adr = cpu->R[13] + ((i & 0xFF) << 2);
cpu->R[REG_NUM(i, 8)] = READ32(cpu->mem_if->data, adr);
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_READ>(3, adr);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_LDR_PCREL(const uint32_t i)
-{
- uint32_t adr = (cpu->R[15]&0xFFFFFFFC) + ((i&0xFF)<<2);
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_READ>(3, adr);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_LDR_PCREL(uint32_t i)
+{
+ uint32_t adr = (cpu->R[15] & 0xFFFFFFFC) + ((i & 0xFF) << 2);
cpu->R[REG_NUM(i, 8)] = READ32(cpu->mem_if->data, adr);
- return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_READ>(3, adr);
+ return MMU_aluMemAccessCycles<PROCNUM, 32, MMU_AD_READ>(3, adr);
}
//-----------------------------------------------------------------------------
// Adjust SP
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_ADJUST_P_SP(const uint32_t i)
-{
- cpu->R[13] += ((i&0x7F)<<2);
-
- return 1;
-}
-
-TEMPLATE static uint32_t FASTCALL OP_ADJUST_M_SP(const uint32_t i)
-{
- cpu->R[13] -= ((i&0x7F)<<2);
+TEMPLATE static uint32_t FASTCALL OP_ADJUST_P_SP(uint32_t i)
+{
+ cpu->R[13] += (i & 0x7F) << 2;
+
+ return 1;
+}
+
+TEMPLATE static uint32_t FASTCALL OP_ADJUST_M_SP(uint32_t i)
+{
+ cpu->R[13] -= (i & 0x7F) << 2;
return 1;
}
@@ -830,59 +826,59 @@
// PUSH / POP
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_PUSH(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_PUSH(uint32_t i)
{
uint32_t adr = cpu->R[13] - 4;
- uint32_t c = 0, j;
-
- for(j = 0; j<8; j++)
- if(BIT_N(i, 7-j))
+ uint32_t c = 0;
+
+ for (uint32_t j = 0; j < 8; ++j)
+ if (BIT_N(i, 7 - j))
{
- WRITE32(cpu->mem_if->data, adr, cpu->R[7-j]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(adr);
+ WRITE32(cpu->mem_if->data, adr, cpu->R[7 - j]);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(adr);
adr -= 4;
}
cpu->R[13] = adr + 4;
- return MMU_aluMemCycles<PROCNUM>(3, c);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_PUSH_LR(const uint32_t i)
+ return MMU_aluMemCycles<PROCNUM>(3, c);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_PUSH_LR(uint32_t i)
{
uint32_t adr = cpu->R[13] - 4;
- uint32_t c = 0, j;
+ uint32_t c = 0;
WRITE32(cpu->mem_if->data, adr, cpu->R[14]);
c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(adr);
adr -= 4;
- for(j = 0; j<8; j++)
- if(BIT_N(i, 7-j))
+ for (uint32_t j = 0; j < 8; ++j)
+ if (BIT_N(i, 7 - j))
{
- WRITE32(cpu->mem_if->data, adr, cpu->R[7-j]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(adr);
+ WRITE32(cpu->mem_if->data, adr, cpu->R[7 - j]);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(adr);
adr -= 4;
}
cpu->R[13] = adr + 4;
- return MMU_aluMemCycles<PROCNUM>(4, c);
-}
-
-TEMPLATE static uint32_t FASTCALL OP_POP(const uint32_t i)
+ return MMU_aluMemCycles<PROCNUM>(4, c);
+}
+
+TEMPLATE static uint32_t FASTCALL OP_POP(uint32_t i)
{
uint32_t adr = cpu->R[13];
- uint32_t c = 0, j;
-
- for(j = 0; j<8; j++)
- if(BIT_N(i, j))
+ uint32_t c = 0;
+
+ for (uint32_t j = 0; j < 8; ++j)
+ if (BIT_N(i, j))
{
cpu->R[j] = READ32(cpu->mem_if->data, adr);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(adr);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(adr);
adr += 4;
}
cpu->R[13] = adr;
- return MMU_aluMemCycles<PROCNUM>(2, c);
+ return MMU_aluMemCycles<PROCNUM>(2, c);
}
// In ARMv5 and above, bit[0] of the loaded value
@@ -892,41 +888,40 @@
// In T variants of ARMv4, bit[0] of the loaded value is ignored and execution continues in Thumb state, as
// though the following instruction had been executed:
// MOV PC,(loaded_value)
-TEMPLATE static uint32_t FASTCALL OP_POP_PC(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_POP_PC(uint32_t i)
{
uint32_t adr = cpu->R[13];
- uint32_t c = 0, j;
- uint32_t v = 0;
-
- for(j = 0; j<8; j++)
- if(BIT_N(i, j))
+ uint32_t c = 0;
+
+ for (uint32_t j = 0; j < 8; ++j)
+ if (BIT_N(i, j))
{
cpu->R[j] = READ32(cpu->mem_if->data, adr);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(adr);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(adr);
adr += 4;
}
- v = READ32(cpu->mem_if->data, adr);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(adr);
- if(cpu->LDTBit)
+ uint32_t v = READ32(cpu->mem_if->data, adr);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(adr);
+ if (!PROCNUM)
cpu->CPSR.bits.T = BIT0(v);
cpu->R[15] = v & 0xFFFFFFFE;
cpu->next_instruction = cpu->R[15];
cpu->R[13] = adr + 4;
- return MMU_aluMemCycles<PROCNUM>(5, c);
+ return MMU_aluMemCycles<PROCNUM>(5, c);
}
//-----------------------------------------------------------------------------
// STMIA / LDMIA
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_STMIA_THUMB(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_STMIA_THUMB(uint32_t i)
{
uint32_t adr = cpu->R[REG_NUM(i, 8)];
- uint32_t c = 0, j;
- uint32_t erList = 1; //Empty Register List
+ uint32_t c = 0;
+ bool erList = true; //Empty Register List
// ------ ARM_REF:
// ------ If <Rn> is specified in <registers>:
@@ -935,16 +930,14 @@
if (BIT_N(i, REG_NUM(i, 8)))
printf("STMIA with Rb in Rlist\n");
- for(j = 0; j<8; j++)
- {
- if(BIT_N(i, j))
+ for (uint32_t j = 0; j < 8; ++j)
+ if (BIT_N(i, j))
{
WRITE32(cpu->mem_if->data, adr, cpu->R[j]);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(adr);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_WRITE>(adr);
adr += 4;
- erList = 0; //Register List isnt empty
+ erList = false; //Register List isnt empty
}
- }
if (erList)
printf("STMIA with Empty Rlist\n");
@@ -953,26 +946,24 @@
return MMU_aluMemCycles<PROCNUM>(2, c);
}
-TEMPLATE static uint32_t FASTCALL OP_LDMIA_THUMB(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_LDMIA_THUMB(uint32_t i)
{
uint32_t regIndex = REG_NUM(i, 8);
uint32_t adr = cpu->R[regIndex];
- uint32_t c = 0, j;
- uint32_t erList = 1; //Empty Register List
+ uint32_t c = 0;
+ bool erList = true; //Empty Register List
//if (BIT_N(i, regIndex))
// printf("LDMIA with Rb in Rlist at %08X\n",cpu->instruct_adr);
- for(j = 0; j<8; j++)
- {
- if(BIT_N(i, j))
+ for (uint32_t j = 0; j < 8; ++j)
+ if (BIT_N(i, j))
{
cpu->R[j] = READ32(cpu->mem_if->data, adr);
- c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(adr);
+ c += MMU_memAccessCycles<PROCNUM, 32, MMU_AD_READ>(adr);
adr += 4;
- erList = 0; //Register List isnt empty
+ erList = false; //Register List isnt empty
}
- }
if (erList)
printf("LDMIA with Empty Rlist\n");
@@ -990,10 +981,18 @@
// BKPT
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_BKPT_THUMB(const uint32_t)
-{
- // TODO
- printf("THUMB%c: Unimplemented opcode BKPT\n", PROCNUM?'7':'9');
+TEMPLATE static uint32_t FASTCALL OP_BKPT_THUMB(uint32_t)
+{
+ printf("THUMB%c: OP_BKPT triggered\n", PROCNUM?'7':'9');
+ Status_Reg tmp = cpu->CPSR;
+ armcpu_switchMode(cpu, ABT); // enter abt mode
+ cpu->R[14] = cpu->instruct_adr + 4;
+ cpu->SPSR = tmp; // save old CPSR as new SPSR
+ cpu->CPSR.bits.T = 0; // handle as ARM32 code
+ cpu->CPSR.bits.I = 1;
+ cpu->changeCPSR();
+ cpu->R[15] = cpu->intVector + 0x0C;
+ cpu->next_instruction = cpu->R[15];
return 1;
}
@@ -1001,12 +1000,13 @@
// SWI
//-----------------------------------------------------------------------------
-TEMPLATE static uint32_t FASTCALL OP_SWI_THUMB(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_SWI_THUMB(uint32_t i)
{
uint32_t swinum = i & 0xFF;
//ideas-style debug prints (execute this SWI with the null terminated string address in R0)
- if(swinum==0xFC) {
+ if (swinum == 0xFC)
+ {
//IdeasLog(cpu);
return 0;
}
@@ -1014,32 +1014,32 @@
//if the user has changed the intVector to point away from the nds bioses,
//then it doesn't really make any sense to use the builtin SWI's since
//the bios ones aren't getting called anyway
- bool bypassBuiltinSWI =
- (cpu->intVector == 0x00000000 && PROCNUM==0)
- || (cpu->intVector == 0xFFFF0000 && PROCNUM==1);
-
- if(cpu->swi_tab && !bypassBuiltinSWI) {
- //zero 25-dec-2008 - in arm, we were masking to 0x1F.
- //this is probably safer since an invalid opcode could crash the emu
- //zero 30-jun-2009 - but they say that the ideas 0xFF should crash the device...
- //uint32_t swinum = cpu->instruction & 0xFF;
+ bool bypassBuiltinSWI = (cpu->intVector == 0x00000000 && !PROCNUM) || (cpu->intVector == 0xFFFF0000 && PROCNUM == 1);
+
+ if (cpu->swi_tab && !bypassBuiltinSWI)
+ {
+ //zero 25-dec-2008 - in arm, we were masking to 0x1F.
+ //this is probably safer since an invalid opcode could crash the emu
+ //zero 30-jun-2009 - but they say that the ideas 0xFF should crash the device...
+ //uint32_t swinum = cpu->instruction & 0xFF;
swinum &= 0x1F;
//printf("%d ARM SWI %d\n",PROCNUM,swinum);
- return cpu->swi_tab[swinum]() + 3;
- }
- else {
- /* we use an irq thats not in the irq tab, as
- it was replaced due to a changed intVector */
- Status_Reg tmp = cpu->CPSR;
- armcpu_switchMode(cpu, SVC); /* enter svc mode */
- cpu->R[14] = cpu->next_instruction; /* jump to swi Vector */
- cpu->SPSR = tmp; /* save old CPSR as new SPSR */
- cpu->CPSR.bits.T = 0; /* handle as ARM32 code */
- cpu->CPSR.bits.I = 1;
- cpu->changeCPSR();
- cpu->R[15] = cpu->intVector + 0x08;
- cpu->next_instruction = cpu->R[15];
- return 3;
+ return cpu->swi_tab[swinum]() + 3;
+ }
+ else
+ {
+ /* we use an irq thats not in the irq tab, as
+ it was replaced due to a changed intVector */
+ Status_Reg tmp = cpu->CPSR;
+ armcpu_switchMode(cpu, SVC); /* enter svc mode */
+ cpu->R[14] = cpu->next_instruction; /* jump to swi Vector */
+ cpu->SPSR = tmp; /* save old CPSR as new SPSR */
+ cpu->CPSR.bits.T = 0; /* handle as ARM32 code */
+ cpu->CPSR.bits.I = 1;
+ cpu->changeCPSR();
+ cpu->R[15] = cpu->intVector + 0x08;
+ cpu->next_instruction = cpu->R[15];
+ return 3;
}
}
@@ -1047,49 +1047,50 @@
// Branch
//-----------------------------------------------------------------------------
-#define SIGNEEXT_IMM11(i) (((i)&0x7FF) | (BIT10(i) * 0xFFFFF800))
-
-TEMPLATE static uint32_t FASTCALL OP_B_COND(const uint32_t i)
-{
- if(!TEST_COND((i>>8)&0xF, 0, cpu->CPSR))
+static inline uint32_t SIGNEEXT_IMM11(uint32_t i) { return (i & 0x7FF) | (BIT10(i) * 0xFFFFF800); }
+static inline uint32_t SIGNEXTEND_11(uint32_t i) { return static_cast<uint32_t>((static_cast<int32_t>(i) << 21) >> 21); }
+
+TEMPLATE static uint32_t FASTCALL OP_B_COND(uint32_t i)
+{
+ if (!TEST_COND((i >> 8) & 0xF, 0, cpu->CPSR))
return 1;
- cpu->R[15] += (uint32_t)((int8_t)(i&0xFF))<<1;
+ cpu->R[15] += static_cast<uint32_t>(static_cast<int8_t>(i & 0xFF)) << 1;
cpu->next_instruction = cpu->R[15];
return 3;
}
-TEMPLATE static uint32_t FASTCALL OP_B_UNCOND(const uint32_t i)
-{
- cpu->R[15] += (SIGNEEXT_IMM11(i)<<1);
+TEMPLATE static uint32_t FASTCALL OP_B_UNCOND(uint32_t i)
+{
+ cpu->R[15] += SIGNEEXT_IMM11(i) << 1;
cpu->next_instruction = cpu->R[15];
return 1;
}
-TEMPLATE static uint32_t FASTCALL OP_BLX(const uint32_t i)
-{
- cpu->R[15] = (cpu->R[14] + ((i&0x7FF)<<1))&0xFFFFFFFC;
+TEMPLATE static uint32_t FASTCALL OP_BLX(uint32_t i)
+{
+ cpu->R[15] = (cpu->R[14] + ((i & 0x7FF) << 1)) & 0xFFFFFFFC;
cpu->R[14] = cpu->next_instruction | 1;
cpu->next_instruction = cpu->R[15];
cpu->CPSR.bits.T = 0;
return 3;
}
-TEMPLATE static uint32_t FASTCALL OP_BL_10(const uint32_t i)
-{
- cpu->R[14] = cpu->R[15] + (SIGNEEXT_IMM11(i)<<12);
- return 1;
-}
-
-TEMPLATE static uint32_t FASTCALL OP_BL_11(const uint32_t i)
-{
- cpu->R[15] = (cpu->R[14] + ((i&0x7FF)<<1));
+TEMPLATE static uint32_t FASTCALL OP_BL_10(uint32_t i)
+{
+ cpu->R[14] = cpu->R[15] + (SIGNEXTEND_11(i) << 12);
+ return 1;
+}
+
+TEMPLATE static uint32_t FASTCALL OP_BL_11(uint32_t i)
+{
+ cpu->R[15] = (cpu->R[14] + ((i & 0x7FF) << 1));
cpu->R[14] = cpu->next_instruction | 1;
cpu->next_instruction = cpu->R[15];
return 4;
}
-TEMPLATE static uint32_t FASTCALL OP_BX_THUMB(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BX_THUMB(uint32_t i)
{
// When using PC as operand with BX opcode, switch to ARM state and jump to (instruct_adr+4)
// Reference: http://nocash.emubase.de/gbatek.htm#thumb5hiregisteroperationsbranchexchange
@@ -1097,9 +1098,9 @@
#if 0
if (REG_POS(i, 3) == 15)
{
- cpu->CPSR.bits.T = 0;
- cpu->R[15] &= 0xFFFFFFFC;
- cpu->next_instruction = cpu->R[15];
+ cpu->CPSR.bits.T = 0;
+ cpu->R[15] &= 0xFFFFFFFC;
+ cpu->next_instruction = cpu->R[15];
}
else
{
@@ -1123,18 +1124,16 @@
//emu_halt();
}
cpu->CPSR.bits.T = BIT0(Rm);
- cpu->R[15] = (Rm & (0xFFFFFFFC|(1<<cpu->CPSR.bits.T)));
+ cpu->R[15] = Rm & (0xFFFFFFFC | (1 << cpu->CPSR.bits.T));
cpu->next_instruction = cpu->R[15];
#endif
return 3;
}
-TEMPLATE static uint32_t FASTCALL OP_BLX_THUMB(const uint32_t i)
+TEMPLATE static uint32_t FASTCALL OP_BLX_THUMB(uint32_t i)
{
uint32_t Rm = cpu->R[REG_POS(i, 3)];
-
cpu->CPSR.bits.T = BIT0(Rm);
- //cpu->R[15] = (Rm & (0xFFFFFFFC|(1<<cpu->CPSR.bits.T)));
cpu->R[15] = Rm & 0xFFFFFFFE;
cpu->R[14] = cpu->next_instruction | 1;
cpu->next_instruction = cpu->R[15];
@@ -1146,21 +1145,16 @@
// The End
//-----------------------------------------------------------------------------
+const OpFunc thumb_instructions_set[2][1024] =
+{
+ {
#define TABDECL(x) x<0>
-const ThumbOpFunc thumb_instructions_set_0[1024] = {
#include "thumb_tabdef.inc"
+#undef TABDECL
+ }, {
+#define TABDECL(x) x<1>
+#include "thumb_tabdef.inc"
+#undef TABDECL
+ }
};
-#undef TABDECL
-
-#define TABDECL(x) x<1>
-const ThumbOpFunc thumb_instructions_set_1[1024] = {
-#include "thumb_tabdef.inc"
-};
-#undef TABDECL
-
-/*#define TABDECL(x) #x
-const char* thumb_instruction_names[1024] = {
-#include "thumb_tabdef.inc"
-};
-#undef TABDECL*/
-
+
--- a/src/in_2sf/desmume/thumb_instructions.h
+++ /dev/null
@@ -1,32 +1,1 @@
-/*
- Copyright (C) 2006 yopyop
- Copyright (C) 2006-2009 DeSmuME team
- This file is free software: you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation, either version 2 of the License, or
- (at your option) any later version.
-
- This file is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with the this software. If not, see <http://www.gnu.org/licenses/>.
-*/
-
-#ifndef THUMB_INSTRUCTIONS_H
-#define THUMB_INSTRUCTIONS_H
-
-#include "armcpu.h"
-
-typedef uint32_t (FASTCALL* ThumbOpFunc)(const uint32_t i);
-
-extern const ThumbOpFunc thumb_instructions_set_0[1024];
-extern const ThumbOpFunc thumb_instructions_set_1[1024];
-
-//extern const char* thumb_instruction_names[1024];
-
-#endif
-
--- a/src/in_2sf/desmume/thumb_tabdef.inc
+++ b/src/in_2sf/desmume/thumb_tabdef.inc
@@ -1,7 +1,6 @@
/*
Copyright (C) 2006 yopyop
- Copyright (C) 2006-2010 DeSmuME team
-
+ Copyright (C) 2007-2012 DeSmuME team
This file is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
@@ -16,1091 +15,1092 @@
along with the this software. If not, see <http://www.gnu.org/licenses/>.
*/
-TABDECL( OP_LSL_0), //00 0000 0000
-TABDECL( OP_LSL), //00 0000 0001
-TABDECL( OP_LSL), //00 0000 0010
-TABDECL( OP_LSL), //00 0000 0011
-TABDECL( OP_LSL), //00 0000 0100
-TABDECL( OP_LSL), //00 0000 0101
-TABDECL( OP_LSL), //00 0000 0110
-TABDECL( OP_LSL), //00 0000 0111
-TABDECL( OP_LSL), //00 0000 1000
-TABDECL( OP_LSL), //00 0000 1001
-TABDECL( OP_LSL), //00 0000 1010
-TABDECL( OP_LSL), //00 0000 1011
-TABDECL( OP_LSL), //00 0000 1100
-TABDECL( OP_LSL), //00 0000 1101
-TABDECL( OP_LSL), //00 0000 1110
-TABDECL( OP_LSL), //00 0000 1111
-
-TABDECL( OP_LSL), //00 0001 0000
-TABDECL( OP_LSL), //00 0001 0001
-TABDECL( OP_LSL), //00 0001 0010
-TABDECL( OP_LSL), //00 0001 0011
-TABDECL( OP_LSL), //00 0001 0100
-TABDECL( OP_LSL), //00 0001 0101
-TABDECL( OP_LSL), //00 0001 0110
-TABDECL( OP_LSL), //00 0001 0111
-TABDECL( OP_LSL), //00 0001 1000
-TABDECL( OP_LSL), //00 0001 1001
-TABDECL( OP_LSL), //00 0001 1010
-TABDECL( OP_LSL), //00 0001 1011
-TABDECL( OP_LSL), //00 0001 1100
-TABDECL( OP_LSL), //00 0001 1101
-TABDECL( OP_LSL), //00 0001 1110
-TABDECL( OP_LSL), //00 0001 1111
-
-TABDECL( OP_LSR_0), //00 0010 0000
-TABDECL( OP_LSR), //00 0010 0001
-TABDECL( OP_LSR), //00 0010 0010
-TABDECL( OP_LSR), //00 0010 0011
-TABDECL( OP_LSR), //00 0010 0100
-TABDECL( OP_LSR), //00 0010 0101
-TABDECL( OP_LSR), //00 0010 0110
-TABDECL( OP_LSR), //00 0010 0111
-TABDECL( OP_LSR), //00 0010 1000
-TABDECL( OP_LSR), //00 0010 1001
-TABDECL( OP_LSR), //00 0010 1010
-TABDECL( OP_LSR), //00 0010 1011
-TABDECL( OP_LSR), //00 0010 1100
-TABDECL( OP_LSR), //00 0010 1101
-TABDECL( OP_LSR), //00 0010 1110
-TABDECL( OP_LSR), //00 0010 1111
-
-TABDECL( OP_LSR), //00 0011 0000
-TABDECL( OP_LSR), //00 0011 0001
-TABDECL( OP_LSR), //00 0011 0010
-TABDECL( OP_LSR), //00 0011 0011
-TABDECL( OP_LSR), //00 0011 0100
-TABDECL( OP_LSR), //00 0011 0101
-TABDECL( OP_LSR), //00 0011 0110
-TABDECL( OP_LSR), //00 0011 0111
-TABDECL( OP_LSR), //00 0011 1000
-TABDECL( OP_LSR), //00 0011 1001
-TABDECL( OP_LSR), //00 0011 1010
-TABDECL( OP_LSR), //00 0011 1011
-TABDECL( OP_LSR), //00 0011 1100
-TABDECL( OP_LSR), //00 0011 1101
-TABDECL( OP_LSR), //00 0011 1110
-TABDECL( OP_LSR), //00 0011 1111
-
-TABDECL( OP_ASR_0), //00 0100 0000
-TABDECL( OP_ASR), //00 0100 0001
-TABDECL( OP_ASR), //00 0100 0010
-TABDECL( OP_ASR), //00 0100 0011
-TABDECL( OP_ASR), //00 0100 0100
-TABDECL( OP_ASR), //00 0100 0101
-TABDECL( OP_ASR), //00 0100 0110
-TABDECL( OP_ASR), //00 0100 0111
-TABDECL( OP_ASR), //00 0100 1000
-TABDECL( OP_ASR), //00 0100 1001
-TABDECL( OP_ASR), //00 0100 1010
-TABDECL( OP_ASR), //00 0100 1011
-TABDECL( OP_ASR), //00 0100 1100
-TABDECL( OP_ASR), //00 0100 1101
-TABDECL( OP_ASR), //00 0100 1110
-TABDECL( OP_ASR), //00 0100 1111
-
-TABDECL( OP_ASR), //00 0101 0000
-TABDECL( OP_ASR), //00 0101 0001
-TABDECL( OP_ASR), //00 0101 0010
-TABDECL( OP_ASR), //00 0101 0011
-TABDECL( OP_ASR), //00 0101 0100
-TABDECL( OP_ASR), //00 0101 0101
-TABDECL( OP_ASR), //00 0101 0110
-TABDECL( OP_ASR), //00 0101 0111
-TABDECL( OP_ASR), //00 0101 1000
-TABDECL( OP_ASR), //00 0101 1001
-TABDECL( OP_ASR), //00 0101 1010
-TABDECL( OP_ASR), //00 0101 1011
-TABDECL( OP_ASR), //00 0101 1100
-TABDECL( OP_ASR), //00 0101 1101
-TABDECL( OP_ASR), //00 0101 1110
-TABDECL( OP_ASR), //00 0101 1111
-
-TABDECL( OP_ADD_REG), //00 0110 0000
-TABDECL( OP_ADD_REG), //00 0110 0001
-TABDECL( OP_ADD_REG), //00 0110 0010
-TABDECL( OP_ADD_REG), //00 0110 0011
-TABDECL( OP_ADD_REG), //00 0110 0100
-TABDECL( OP_ADD_REG), //00 0110 0101
-TABDECL( OP_ADD_REG), //00 0110 0110
-TABDECL( OP_ADD_REG), //00 0110 0111
-TABDECL( OP_SUB_REG), //00 0110 1000
-TABDECL( OP_SUB_REG), //00 0110 1001
-TABDECL( OP_SUB_REG), //00 0110 1010
-TABDECL( OP_SUB_REG), //00 0110 1011
-TABDECL( OP_SUB_REG), //00 0110 1100
-TABDECL( OP_SUB_REG), //00 0110 1101
-TABDECL( OP_SUB_REG), //00 0110 1110
-TABDECL( OP_SUB_REG), //00 0110 1111
-
-TABDECL( OP_ADD_IMM3), //00 0111 0000
-TABDECL( OP_ADD_IMM3), //00 0111 0001
-TABDECL( OP_ADD_IMM3), //00 0111 0010
-TABDECL( OP_ADD_IMM3), //00 0111 0011
-TABDECL( OP_ADD_IMM3), //00 0111 0100
-TABDECL( OP_ADD_IMM3), //00 0111 0101
-TABDECL( OP_ADD_IMM3), //00 0111 0110
-TABDECL( OP_ADD_IMM3), //00 0111 0111
-TABDECL( OP_SUB_IMM3), //00 0111 1000
-TABDECL( OP_SUB_IMM3), //00 0111 1001
-TABDECL( OP_SUB_IMM3), //00 0111 1010
-TABDECL( OP_SUB_IMM3), //00 0111 1011
-TABDECL( OP_SUB_IMM3), //00 0111 1100
-TABDECL( OP_SUB_IMM3), //00 0111 1101
-TABDECL( OP_SUB_IMM3), //00 0111 1110
-TABDECL( OP_SUB_IMM3), //00 0111 1111
-
-TABDECL( OP_MOV_IMM8), //00 1000 0000
-TABDECL( OP_MOV_IMM8), //00 1000 0001
-TABDECL( OP_MOV_IMM8), //00 1000 0010
-TABDECL( OP_MOV_IMM8), //00 1000 0011
-TABDECL( OP_MOV_IMM8), //00 1000 0100
-TABDECL( OP_MOV_IMM8), //00 1000 0101
-TABDECL( OP_MOV_IMM8), //00 1000 0110
-TABDECL( OP_MOV_IMM8), //00 1000 0111
-TABDECL( OP_MOV_IMM8), //00 1000 1000
-TABDECL( OP_MOV_IMM8), //00 1000 1001
-TABDECL( OP_MOV_IMM8), //00 1000 1010
-TABDECL( OP_MOV_IMM8), //00 1000 1011
-TABDECL( OP_MOV_IMM8), //00 1000 1100
-TABDECL( OP_MOV_IMM8), //00 1000 1101
-TABDECL( OP_MOV_IMM8), //00 1000 1110
-TABDECL( OP_MOV_IMM8), //00 1000 1111
-
-TABDECL( OP_MOV_IMM8), //00 1001 0000
-TABDECL( OP_MOV_IMM8), //00 1001 0001
-TABDECL( OP_MOV_IMM8), //00 1001 0010
-TABDECL( OP_MOV_IMM8), //00 1001 0011
-TABDECL( OP_MOV_IMM8), //00 1001 0100
-TABDECL( OP_MOV_IMM8), //00 1001 0101
-TABDECL( OP_MOV_IMM8), //00 1001 0110
-TABDECL( OP_MOV_IMM8), //00 1001 0111
-TABDECL( OP_MOV_IMM8), //00 1001 1000
-TABDECL( OP_MOV_IMM8), //00 1001 1001
-TABDECL( OP_MOV_IMM8), //00 1001 1010
-TABDECL( OP_MOV_IMM8), //00 1001 1011
-TABDECL( OP_MOV_IMM8), //00 1001 1100
-TABDECL( OP_MOV_IMM8), //00 1001 1101
-TABDECL( OP_MOV_IMM8), //00 1001 1110
-TABDECL( OP_MOV_IMM8), //00 1001 1111
-
-TABDECL( OP_CMP_IMM8), //00 1010 0000
-TABDECL( OP_CMP_IMM8), //00 1010 0001
-TABDECL( OP_CMP_IMM8), //00 1010 0010
-TABDECL( OP_CMP_IMM8), //00 1010 0011
-TABDECL( OP_CMP_IMM8), //00 1010 0100
-TABDECL( OP_CMP_IMM8), //00 1010 0101
-TABDECL( OP_CMP_IMM8), //00 1010 0110
-TABDECL( OP_CMP_IMM8), //00 1010 0111
-TABDECL( OP_CMP_IMM8), //00 1010 1000
-TABDECL( OP_CMP_IMM8), //00 1010 1001
-TABDECL( OP_CMP_IMM8), //00 1010 1010
-TABDECL( OP_CMP_IMM8), //00 1010 1011
-TABDECL( OP_CMP_IMM8), //00 1010 1100
-TABDECL( OP_CMP_IMM8), //00 1010 1101
-TABDECL( OP_CMP_IMM8), //00 1010 1110
-TABDECL( OP_CMP_IMM8), //00 1010 1111
-
-TABDECL( OP_CMP_IMM8), //00 1011 0000
-TABDECL( OP_CMP_IMM8), //00 1011 0001
-TABDECL( OP_CMP_IMM8), //00 1011 0010
-TABDECL( OP_CMP_IMM8), //00 1011 0011
-TABDECL( OP_CMP_IMM8), //00 1011 0100
-TABDECL( OP_CMP_IMM8), //00 1011 0101
-TABDECL( OP_CMP_IMM8), //00 1011 0110
-TABDECL( OP_CMP_IMM8), //00 1011 0111
-TABDECL( OP_CMP_IMM8), //00 1011 1000
-TABDECL( OP_CMP_IMM8), //00 1011 1001
-TABDECL( OP_CMP_IMM8), //00 1011 1010
-TABDECL( OP_CMP_IMM8), //00 1011 1011
-TABDECL( OP_CMP_IMM8), //00 1011 1100
-TABDECL( OP_CMP_IMM8), //00 1011 1101
-TABDECL( OP_CMP_IMM8), //00 1011 1110
-TABDECL( OP_CMP_IMM8), //00 1011 1111
-
-TABDECL( OP_ADD_IMM8), //00 1100 0000
-TABDECL( OP_ADD_IMM8), //00 1100 0001
-TABDECL( OP_ADD_IMM8), //00 1100 0010
-TABDECL( OP_ADD_IMM8), //00 1100 0011
-TABDECL( OP_ADD_IMM8), //00 1100 0100
-TABDECL( OP_ADD_IMM8), //00 1100 0101
-TABDECL( OP_ADD_IMM8), //00 1100 0110
-TABDECL( OP_ADD_IMM8), //00 1100 0111
-TABDECL( OP_ADD_IMM8), //00 1100 1000
-TABDECL( OP_ADD_IMM8), //00 1100 1001
-TABDECL( OP_ADD_IMM8), //00 1100 1010
-TABDECL( OP_ADD_IMM8), //00 1100 1011
-TABDECL( OP_ADD_IMM8), //00 1100 1100
-TABDECL( OP_ADD_IMM8), //00 1100 1101
-TABDECL( OP_ADD_IMM8), //00 1100 1110
-TABDECL( OP_ADD_IMM8), //00 1100 1111
-
-TABDECL( OP_ADD_IMM8), //00 1101 0000
-TABDECL( OP_ADD_IMM8), //00 1101 0001
-TABDECL( OP_ADD_IMM8), //00 1101 0010
-TABDECL( OP_ADD_IMM8), //00 1101 0011
-TABDECL( OP_ADD_IMM8), //00 1101 0100
-TABDECL( OP_ADD_IMM8), //00 1101 0101
-TABDECL( OP_ADD_IMM8), //00 1101 0110
-TABDECL( OP_ADD_IMM8), //00 1101 0111
-TABDECL( OP_ADD_IMM8), //00 1101 1000
-TABDECL( OP_ADD_IMM8), //00 1101 1001
-TABDECL( OP_ADD_IMM8), //00 1101 1010
-TABDECL( OP_ADD_IMM8), //00 1101 1011
-TABDECL( OP_ADD_IMM8), //00 1101 1100
-TABDECL( OP_ADD_IMM8), //00 1101 1101
-TABDECL( OP_ADD_IMM8), //00 1101 1110
-TABDECL( OP_ADD_IMM8), //00 1101 1111
-
-TABDECL( OP_SUB_IMM8), //00 1110 0000
-TABDECL( OP_SUB_IMM8), //00 1110 0001
-TABDECL( OP_SUB_IMM8), //00 1110 0010
-TABDECL( OP_SUB_IMM8), //00 1110 0011
-TABDECL( OP_SUB_IMM8), //00 1110 0100
-TABDECL( OP_SUB_IMM8), //00 1110 0101
-TABDECL( OP_SUB_IMM8), //00 1110 0110
-TABDECL( OP_SUB_IMM8), //00 1110 0111
-TABDECL( OP_SUB_IMM8), //00 1110 1000
-TABDECL( OP_SUB_IMM8), //00 1110 1001
-TABDECL( OP_SUB_IMM8), //00 1110 1010
-TABDECL( OP_SUB_IMM8), //00 1110 1011
-TABDECL( OP_SUB_IMM8), //00 1110 1100
-TABDECL( OP_SUB_IMM8), //00 1110 1101
-TABDECL( OP_SUB_IMM8), //00 1110 1110
-TABDECL( OP_SUB_IMM8), //00 1110 1111
-
-TABDECL( OP_SUB_IMM8), //00 1111 0000
-TABDECL( OP_SUB_IMM8), //00 1111 0001
-TABDECL( OP_SUB_IMM8), //00 1111 0010
-TABDECL( OP_SUB_IMM8), //00 1111 0011
-TABDECL( OP_SUB_IMM8), //00 1111 0100
-TABDECL( OP_SUB_IMM8), //00 1111 0101
-TABDECL( OP_SUB_IMM8), //00 1111 0110
-TABDECL( OP_SUB_IMM8), //00 1111 0111
-TABDECL( OP_SUB_IMM8), //00 1111 1000
-TABDECL( OP_SUB_IMM8), //00 1111 1001
-TABDECL( OP_SUB_IMM8), //00 1111 1010
-TABDECL( OP_SUB_IMM8), //00 1111 1011
-TABDECL( OP_SUB_IMM8), //00 1111 1100
-TABDECL( OP_SUB_IMM8), //00 1111 1101
-TABDECL( OP_SUB_IMM8), //00 1111 1110
-TABDECL( OP_SUB_IMM8), //00 1111 1111
-
-TABDECL( OP_AND), //01 0000 0000
-TABDECL( OP_EOR), //01 0000 0001
-TABDECL( OP_LSL_REG), //01 0000 0010
-TABDECL( OP_LSR_REG), //01 0000 0011
-TABDECL( OP_ASR_REG), //01 0000 0100
-TABDECL( OP_ADC_REG), //01 0000 0101
-TABDECL( OP_SBC_REG), //01 0000 0110
-TABDECL( OP_ROR_REG), //01 0000 0111
-TABDECL( OP_TST), //01 0000 1000
-TABDECL( OP_NEG), //01 0000 1001
-TABDECL( OP_CMP), //01 0000 1010
-TABDECL( OP_CMN), //01 0000 1011
-TABDECL( OP_ORR), //01 0000 1100
-TABDECL( OP_MUL_REG), //01 0000 1101
-TABDECL( OP_BIC), //01 0000 1110
-TABDECL( OP_MVN), //01 0000 1111
-
-TABDECL( OP_ADD_SPE), //01 0001 0000
-TABDECL( OP_ADD_SPE), //01 0001 0001
-TABDECL( OP_ADD_SPE), //01 0001 0010
-TABDECL( OP_ADD_SPE), //01 0001 0011
-TABDECL( OP_CMP_SPE), //01 0001 0100
-TABDECL( OP_CMP_SPE), //01 0001 0101
-TABDECL( OP_CMP_SPE), //01 0001 0110
-TABDECL( OP_CMP_SPE), //01 0001 0111
-TABDECL( OP_MOV_SPE), //01 0001 1000
-TABDECL( OP_MOV_SPE), //01 0001 1001
-TABDECL( OP_MOV_SPE), //01 0001 1010
-TABDECL( OP_MOV_SPE), //01 0001 1011
-TABDECL( OP_BX_THUMB), //01 0001 1100
-TABDECL( OP_BX_THUMB), //01 0001 1101
-TABDECL( OP_BLX_THUMB), //01 0001 1110
-TABDECL( OP_BLX_THUMB), //01 0001 1111
-
-TABDECL( OP_LDR_PCREL), //01 0010 0000
-TABDECL( OP_LDR_PCREL), //01 0010 0001
-TABDECL( OP_LDR_PCREL), //01 0010 0010
-TABDECL( OP_LDR_PCREL), //01 0010 0011
-TABDECL( OP_LDR_PCREL), //01 0010 0100
-TABDECL( OP_LDR_PCREL), //01 0010 0101
-TABDECL( OP_LDR_PCREL), //01 0010 0110
-TABDECL( OP_LDR_PCREL), //01 0010 0111
-TABDECL( OP_LDR_PCREL), //01 0010 1000
-TABDECL( OP_LDR_PCREL), //01 0010 1001
-TABDECL( OP_LDR_PCREL), //01 0010 1010
-TABDECL( OP_LDR_PCREL), //01 0010 1011
-TABDECL( OP_LDR_PCREL), //01 0010 1100
-TABDECL( OP_LDR_PCREL), //01 0010 1101
-TABDECL( OP_LDR_PCREL), //01 0010 1110
-TABDECL( OP_LDR_PCREL), //01 0010 1111
-
-TABDECL( OP_LDR_PCREL), //01 0011 0000
-TABDECL( OP_LDR_PCREL), //01 0011 0001
-TABDECL( OP_LDR_PCREL), //01 0011 0010
-TABDECL( OP_LDR_PCREL), //01 0011 0011
-TABDECL( OP_LDR_PCREL), //01 0011 0100
-TABDECL( OP_LDR_PCREL), //01 0011 0101
-TABDECL( OP_LDR_PCREL), //01 0011 0110
-TABDECL( OP_LDR_PCREL), //01 0011 0111
-TABDECL( OP_LDR_PCREL), //01 0011 1000
-TABDECL( OP_LDR_PCREL), //01 0011 1001
-TABDECL( OP_LDR_PCREL), //01 0011 1010
-TABDECL( OP_LDR_PCREL), //01 0011 1011
-TABDECL( OP_LDR_PCREL), //01 0011 1100
-TABDECL( OP_LDR_PCREL), //01 0011 1101
-TABDECL( OP_LDR_PCREL), //01 0011 1110
-TABDECL( OP_LDR_PCREL), //01 0011 1111
-
-TABDECL( OP_STR_REG_OFF), //01 0100 0000
-TABDECL( OP_STR_REG_OFF), //01 0100 0001
-TABDECL( OP_STR_REG_OFF), //01 0100 0010
-TABDECL( OP_STR_REG_OFF), //01 0100 0011
-TABDECL( OP_STR_REG_OFF), //01 0100 0100
-TABDECL( OP_STR_REG_OFF), //01 0100 0101
-TABDECL( OP_STR_REG_OFF), //01 0100 0110
-TABDECL( OP_STR_REG_OFF), //01 0100 0111
-TABDECL( OP_STRH_REG_OFF), //01 0100 1000
-TABDECL( OP_STRH_REG_OFF), //01 0100 1001
-TABDECL( OP_STRH_REG_OFF), //01 0100 1010
-TABDECL( OP_STRH_REG_OFF), //01 0100 1011
-TABDECL( OP_STRH_REG_OFF), //01 0100 1100
-TABDECL( OP_STRH_REG_OFF), //01 0100 1101
-TABDECL( OP_STRH_REG_OFF), //01 0100 1110
-TABDECL( OP_STRH_REG_OFF), //01 0100 1111
-
-TABDECL( OP_STRB_REG_OFF), //01 0101 0000
-TABDECL( OP_STRB_REG_OFF), //01 0101 0001
-TABDECL( OP_STRB_REG_OFF), //01 0101 0010
-TABDECL( OP_STRB_REG_OFF), //01 0101 0011
-TABDECL( OP_STRB_REG_OFF), //01 0101 0100
-TABDECL( OP_STRB_REG_OFF), //01 0101 0101
-TABDECL( OP_STRB_REG_OFF), //01 0101 0110
-TABDECL( OP_STRB_REG_OFF), //01 0101 0111
-TABDECL( OP_LDRSB_REG_OFF), //01 0101 1000
-TABDECL( OP_LDRSB_REG_OFF), //01 0101 1001
-TABDECL( OP_LDRSB_REG_OFF), //01 0101 1010
-TABDECL( OP_LDRSB_REG_OFF), //01 0101 1011
-TABDECL( OP_LDRSB_REG_OFF), //01 0101 1100
-TABDECL( OP_LDRSB_REG_OFF), //01 0101 1101
-TABDECL( OP_LDRSB_REG_OFF), //01 0101 1110
-TABDECL( OP_LDRSB_REG_OFF), //01 0101 1111
-
-TABDECL( OP_LDR_REG_OFF), //01 0110 0000
-TABDECL( OP_LDR_REG_OFF), //01 0110 0001
-TABDECL( OP_LDR_REG_OFF), //01 0110 0010
-TABDECL( OP_LDR_REG_OFF), //01 0110 0011
-TABDECL( OP_LDR_REG_OFF), //01 0110 0100
-TABDECL( OP_LDR_REG_OFF), //01 0110 0101
-TABDECL( OP_LDR_REG_OFF), //01 0110 0110
-TABDECL( OP_LDR_REG_OFF), //01 0110 0111
-TABDECL( OP_LDRH_REG_OFF), //01 0110 1000
-TABDECL( OP_LDRH_REG_OFF), //01 0110 1001
-TABDECL( OP_LDRH_REG_OFF), //01 0110 1010
-TABDECL( OP_LDRH_REG_OFF), //01 0110 1011
-TABDECL( OP_LDRH_REG_OFF), //01 0110 1100
-TABDECL( OP_LDRH_REG_OFF), //01 0110 1101
-TABDECL( OP_LDRH_REG_OFF), //01 0110 1110
-TABDECL( OP_LDRH_REG_OFF), //01 0110 1111
-
-TABDECL( OP_LDRB_REG_OFF), //01 0111 0000
-TABDECL( OP_LDRB_REG_OFF), //01 0111 0001
-TABDECL( OP_LDRB_REG_OFF), //01 0111 0010
-TABDECL( OP_LDRB_REG_OFF), //01 0111 0011
-TABDECL( OP_LDRB_REG_OFF), //01 0111 0100
-TABDECL( OP_LDRB_REG_OFF), //01 0111 0101
-TABDECL( OP_LDRB_REG_OFF), //01 0111 0110
-TABDECL( OP_LDRB_REG_OFF), //01 0111 0111
-TABDECL( OP_LDRSH_REG_OFF), //01 0111 1000
-TABDECL( OP_LDRSH_REG_OFF), //01 0111 1001
-TABDECL( OP_LDRSH_REG_OFF), //01 0111 1010
-TABDECL( OP_LDRSH_REG_OFF), //01 0111 1011
-TABDECL( OP_LDRSH_REG_OFF), //01 0111 1100
-TABDECL( OP_LDRSH_REG_OFF), //01 0111 1101
-TABDECL( OP_LDRSH_REG_OFF), //01 0111 1110
-TABDECL( OP_LDRSH_REG_OFF), //01 0111 1111
-
-TABDECL( OP_STR_IMM_OFF), //01 1000 0000
-TABDECL( OP_STR_IMM_OFF), //01 1000 0001
-TABDECL( OP_STR_IMM_OFF), //01 1000 0010
-TABDECL( OP_STR_IMM_OFF), //01 1000 0011
-TABDECL( OP_STR_IMM_OFF), //01 1000 0100
-TABDECL( OP_STR_IMM_OFF), //01 1000 0101
-TABDECL( OP_STR_IMM_OFF), //01 1000 0110
-TABDECL( OP_STR_IMM_OFF), //01 1000 0111
-TABDECL( OP_STR_IMM_OFF), //01 1000 1000
-TABDECL( OP_STR_IMM_OFF), //01 1000 1001
-TABDECL( OP_STR_IMM_OFF), //01 1000 1010
-TABDECL( OP_STR_IMM_OFF), //01 1000 1011
-TABDECL( OP_STR_IMM_OFF), //01 1000 1100
-TABDECL( OP_STR_IMM_OFF), //01 1000 1101
-TABDECL( OP_STR_IMM_OFF), //01 1000 1110
-TABDECL( OP_STR_IMM_OFF), //01 1000 1111
-
-TABDECL( OP_STR_IMM_OFF), //01 1001 0000
-TABDECL( OP_STR_IMM_OFF), //01 1001 0001
-TABDECL( OP_STR_IMM_OFF), //01 1001 0010
-TABDECL( OP_STR_IMM_OFF), //01 1001 0011
-TABDECL( OP_STR_IMM_OFF), //01 1001 0100
-TABDECL( OP_STR_IMM_OFF), //01 1001 0101
-TABDECL( OP_STR_IMM_OFF), //01 1001 0110
-TABDECL( OP_STR_IMM_OFF), //01 1001 0111
-TABDECL( OP_STR_IMM_OFF), //01 1001 1000
-TABDECL( OP_STR_IMM_OFF), //01 1001 1001
-TABDECL( OP_STR_IMM_OFF), //01 1001 1010
-TABDECL( OP_STR_IMM_OFF), //01 1001 1011
-TABDECL( OP_STR_IMM_OFF), //01 1001 1100
-TABDECL( OP_STR_IMM_OFF), //01 1001 1101
-TABDECL( OP_STR_IMM_OFF), //01 1001 1110
-TABDECL( OP_STR_IMM_OFF), //01 1001 1111
-
-TABDECL( OP_LDR_IMM_OFF), //01 1010 0000
-TABDECL( OP_LDR_IMM_OFF), //01 1010 0001
-TABDECL( OP_LDR_IMM_OFF), //01 1010 0010
-TABDECL( OP_LDR_IMM_OFF), //01 1010 0011
-TABDECL( OP_LDR_IMM_OFF), //01 1010 0100
-TABDECL( OP_LDR_IMM_OFF), //01 1010 0101
-TABDECL( OP_LDR_IMM_OFF), //01 1010 0110
-TABDECL( OP_LDR_IMM_OFF), //01 1010 0111
-TABDECL( OP_LDR_IMM_OFF), //01 1010 1000
-TABDECL( OP_LDR_IMM_OFF), //01 1010 1001
-TABDECL( OP_LDR_IMM_OFF), //01 1010 1010
-TABDECL( OP_LDR_IMM_OFF), //01 1010 1011
-TABDECL( OP_LDR_IMM_OFF), //01 1010 1100
-TABDECL( OP_LDR_IMM_OFF), //01 1010 1101
-TABDECL( OP_LDR_IMM_OFF), //01 1010 1110
-TABDECL( OP_LDR_IMM_OFF), //01 1010 1111
-
-TABDECL( OP_LDR_IMM_OFF), //01 1011 0000
-TABDECL( OP_LDR_IMM_OFF), //01 1011 0001
-TABDECL( OP_LDR_IMM_OFF), //01 1011 0010
-TABDECL( OP_LDR_IMM_OFF), //01 1011 0011
-TABDECL( OP_LDR_IMM_OFF), //01 1011 0100
-TABDECL( OP_LDR_IMM_OFF), //01 1011 0101
-TABDECL( OP_LDR_IMM_OFF), //01 1011 0110
-TABDECL( OP_LDR_IMM_OFF), //01 1011 0111
-TABDECL( OP_LDR_IMM_OFF), //01 1011 1000
-TABDECL( OP_LDR_IMM_OFF), //01 1011 1001
-TABDECL( OP_LDR_IMM_OFF), //01 1011 1010
-TABDECL( OP_LDR_IMM_OFF), //01 1011 1011
-TABDECL( OP_LDR_IMM_OFF), //01 1011 1100
-TABDECL( OP_LDR_IMM_OFF), //01 1011 1101
-TABDECL( OP_LDR_IMM_OFF), //01 1011 1110
-TABDECL( OP_LDR_IMM_OFF), //01 1011 1111
-
-TABDECL( OP_STRB_IMM_OFF), //01 1100 0000
-TABDECL( OP_STRB_IMM_OFF), //01 1100 0001
-TABDECL( OP_STRB_IMM_OFF), //01 1100 0010
-TABDECL( OP_STRB_IMM_OFF), //01 1100 0011
-TABDECL( OP_STRB_IMM_OFF), //01 1100 0100
-TABDECL( OP_STRB_IMM_OFF), //01 1100 0101
-TABDECL( OP_STRB_IMM_OFF), //01 1100 0110
-TABDECL( OP_STRB_IMM_OFF), //01 1100 0111
-TABDECL( OP_STRB_IMM_OFF), //01 1100 1000
-TABDECL( OP_STRB_IMM_OFF), //01 1100 1001
-TABDECL( OP_STRB_IMM_OFF), //01 1100 1010
-TABDECL( OP_STRB_IMM_OFF), //01 1100 1011
-TABDECL( OP_STRB_IMM_OFF), //01 1100 1100
-TABDECL( OP_STRB_IMM_OFF), //01 1100 1101
-TABDECL( OP_STRB_IMM_OFF), //01 1100 1110
-TABDECL( OP_STRB_IMM_OFF), //01 1100 1111
-
-TABDECL( OP_STRB_IMM_OFF), //01 1101 0000
-TABDECL( OP_STRB_IMM_OFF), //01 1101 0001
-TABDECL( OP_STRB_IMM_OFF), //01 1101 0010
-TABDECL( OP_STRB_IMM_OFF), //01 1101 0011
-TABDECL( OP_STRB_IMM_OFF), //01 1101 0100
-TABDECL( OP_STRB_IMM_OFF), //01 1101 0101
-TABDECL( OP_STRB_IMM_OFF), //01 1101 0110
-TABDECL( OP_STRB_IMM_OFF), //01 1101 0111
-TABDECL( OP_STRB_IMM_OFF), //01 1101 1000
-TABDECL( OP_STRB_IMM_OFF), //01 1101 1001
-TABDECL( OP_STRB_IMM_OFF), //01 1101 1010
-TABDECL( OP_STRB_IMM_OFF), //01 1101 1011
-TABDECL( OP_STRB_IMM_OFF), //01 1101 1100
-TABDECL( OP_STRB_IMM_OFF), //01 1101 1101
-TABDECL( OP_STRB_IMM_OFF), //01 1101 1110
-TABDECL( OP_STRB_IMM_OFF), //01 1101 1111
-
-TABDECL( OP_LDRB_IMM_OFF), //01 1110 0000
-TABDECL( OP_LDRB_IMM_OFF), //01 1110 0001
-TABDECL( OP_LDRB_IMM_OFF), //01 1110 0010
-TABDECL( OP_LDRB_IMM_OFF), //01 1110 0011
-TABDECL( OP_LDRB_IMM_OFF), //01 1110 0100
-TABDECL( OP_LDRB_IMM_OFF), //01 1110 0101
-TABDECL( OP_LDRB_IMM_OFF), //01 1110 0110
-TABDECL( OP_LDRB_IMM_OFF), //01 1110 0111
-TABDECL( OP_LDRB_IMM_OFF), //01 1110 1000
-TABDECL( OP_LDRB_IMM_OFF), //01 1110 1001
-TABDECL( OP_LDRB_IMM_OFF), //01 1110 1010
-TABDECL( OP_LDRB_IMM_OFF), //01 1110 1011
-TABDECL( OP_LDRB_IMM_OFF), //01 1110 1100
-TABDECL( OP_LDRB_IMM_OFF), //01 1110 1101
-TABDECL( OP_LDRB_IMM_OFF), //01 1110 1110
-TABDECL( OP_LDRB_IMM_OFF), //01 1110 1111
-
-TABDECL( OP_LDRB_IMM_OFF), //01 1111 0000
-TABDECL( OP_LDRB_IMM_OFF), //01 1111 0001
-TABDECL( OP_LDRB_IMM_OFF), //01 1111 0010
-TABDECL( OP_LDRB_IMM_OFF), //01 1111 0011
-TABDECL( OP_LDRB_IMM_OFF), //01 1111 0100
-TABDECL( OP_LDRB_IMM_OFF), //01 1111 0101
-TABDECL( OP_LDRB_IMM_OFF), //01 1111 0110
-TABDECL( OP_LDRB_IMM_OFF), //01 1111 0111
-TABDECL( OP_LDRB_IMM_OFF), //01 1111 1000
-TABDECL( OP_LDRB_IMM_OFF), //01 1111 1001
-TABDECL( OP_LDRB_IMM_OFF), //01 1111 1010
-TABDECL( OP_LDRB_IMM_OFF), //01 1111 1011
-TABDECL( OP_LDRB_IMM_OFF), //01 1111 1100
-TABDECL( OP_LDRB_IMM_OFF), //01 1111 1101
-TABDECL( OP_LDRB_IMM_OFF), //01 1111 1110
-TABDECL( OP_LDRB_IMM_OFF), //01 1111 1111
-
-TABDECL( OP_STRH_IMM_OFF), //10 0000 0000
-TABDECL( OP_STRH_IMM_OFF), //10 0000 0001
-TABDECL( OP_STRH_IMM_OFF), //10 0000 0010
-TABDECL( OP_STRH_IMM_OFF), //10 0000 0011
-TABDECL( OP_STRH_IMM_OFF), //10 0000 0100
-TABDECL( OP_STRH_IMM_OFF), //10 0000 0101
-TABDECL( OP_STRH_IMM_OFF), //10 0000 0110
-TABDECL( OP_STRH_IMM_OFF), //10 0000 0111
-TABDECL( OP_STRH_IMM_OFF), //10 0000 1000
-TABDECL( OP_STRH_IMM_OFF), //10 0000 1001
-TABDECL( OP_STRH_IMM_OFF), //10 0000 1010
-TABDECL( OP_STRH_IMM_OFF), //10 0000 1011
-TABDECL( OP_STRH_IMM_OFF), //10 0000 1100
-TABDECL( OP_STRH_IMM_OFF), //10 0000 1101
-TABDECL( OP_STRH_IMM_OFF), //10 0000 1110
-TABDECL( OP_STRH_IMM_OFF), //10 0000 1111
-
-TABDECL( OP_STRH_IMM_OFF), //10 0001 0000
-TABDECL( OP_STRH_IMM_OFF), //10 0001 0001
-TABDECL( OP_STRH_IMM_OFF), //10 0001 0010
-TABDECL( OP_STRH_IMM_OFF), //10 0001 0011
-TABDECL( OP_STRH_IMM_OFF), //10 0001 0100
-TABDECL( OP_STRH_IMM_OFF), //10 0001 0101
-TABDECL( OP_STRH_IMM_OFF), //10 0001 0110
-TABDECL( OP_STRH_IMM_OFF), //10 0001 0111
-TABDECL( OP_STRH_IMM_OFF), //10 0001 1000
-TABDECL( OP_STRH_IMM_OFF), //10 0001 1001
-TABDECL( OP_STRH_IMM_OFF), //10 0001 1010
-TABDECL( OP_STRH_IMM_OFF), //10 0001 1011
-TABDECL( OP_STRH_IMM_OFF), //10 0001 1100
-TABDECL( OP_STRH_IMM_OFF), //10 0001 1101
-TABDECL( OP_STRH_IMM_OFF), //10 0001 1110
-TABDECL( OP_STRH_IMM_OFF), //10 0001 1111
-
-TABDECL( OP_LDRH_IMM_OFF), //10 0010 0000
-TABDECL( OP_LDRH_IMM_OFF), //10 0010 0001
-TABDECL( OP_LDRH_IMM_OFF), //10 0010 0010
-TABDECL( OP_LDRH_IMM_OFF), //10 0010 0011
-TABDECL( OP_LDRH_IMM_OFF), //10 0010 0100
-TABDECL( OP_LDRH_IMM_OFF), //10 0010 0101
-TABDECL( OP_LDRH_IMM_OFF), //10 0010 0110
-TABDECL( OP_LDRH_IMM_OFF), //10 0010 0111
-TABDECL( OP_LDRH_IMM_OFF), //10 0010 1000
-TABDECL( OP_LDRH_IMM_OFF), //10 0010 1001
-TABDECL( OP_LDRH_IMM_OFF), //10 0010 1010
-TABDECL( OP_LDRH_IMM_OFF), //10 0010 1011
-TABDECL( OP_LDRH_IMM_OFF), //10 0010 1100
-TABDECL( OP_LDRH_IMM_OFF), //10 0010 1101
-TABDECL( OP_LDRH_IMM_OFF), //10 0010 1110
-TABDECL( OP_LDRH_IMM_OFF), //10 0010 1111
-
-TABDECL( OP_LDRH_IMM_OFF), //10 0011 0000
-TABDECL( OP_LDRH_IMM_OFF), //10 0011 0001
-TABDECL( OP_LDRH_IMM_OFF), //10 0011 0010
-TABDECL( OP_LDRH_IMM_OFF), //10 0011 0011
-TABDECL( OP_LDRH_IMM_OFF), //10 0011 0100
-TABDECL( OP_LDRH_IMM_OFF), //10 0011 0101
-TABDECL( OP_LDRH_IMM_OFF), //10 0011 0110
-TABDECL( OP_LDRH_IMM_OFF), //10 0011 0111
-TABDECL( OP_LDRH_IMM_OFF), //10 0011 1000
-TABDECL( OP_LDRH_IMM_OFF), //10 0011 1001
-TABDECL( OP_LDRH_IMM_OFF), //10 0011 1010
-TABDECL( OP_LDRH_IMM_OFF), //10 0011 1011
-TABDECL( OP_LDRH_IMM_OFF), //10 0011 1100
-TABDECL( OP_LDRH_IMM_OFF), //10 0011 1101
-TABDECL( OP_LDRH_IMM_OFF), //10 0011 1110
-TABDECL( OP_LDRH_IMM_OFF), //10 0011 1111
-
-TABDECL( OP_STR_SPREL), //10 0100 0000
-TABDECL( OP_STR_SPREL), //10 0100 0001
-TABDECL( OP_STR_SPREL), //10 0100 0010
-TABDECL( OP_STR_SPREL), //10 0100 0011
-TABDECL( OP_STR_SPREL), //10 0100 0100
-TABDECL( OP_STR_SPREL), //10 0100 0101
-TABDECL( OP_STR_SPREL), //10 0100 0110
-TABDECL( OP_STR_SPREL), //10 0100 0111
-TABDECL( OP_STR_SPREL), //10 0100 1000
-TABDECL( OP_STR_SPREL), //10 0100 1001
-TABDECL( OP_STR_SPREL), //10 0100 1010
-TABDECL( OP_STR_SPREL), //10 0100 1011
-TABDECL( OP_STR_SPREL), //10 0100 1100
-TABDECL( OP_STR_SPREL), //10 0100 1101
-TABDECL( OP_STR_SPREL), //10 0100 1110
-TABDECL( OP_STR_SPREL), //10 0100 1111
-
-TABDECL( OP_STR_SPREL), //10 0101 0000
-TABDECL( OP_STR_SPREL), //10 0101 0001
-TABDECL( OP_STR_SPREL), //10 0101 0010
-TABDECL( OP_STR_SPREL), //10 0101 0011
-TABDECL( OP_STR_SPREL), //10 0101 0100
-TABDECL( OP_STR_SPREL), //10 0101 0101
-TABDECL( OP_STR_SPREL), //10 0101 0110
-TABDECL( OP_STR_SPREL), //10 0101 0111
-TABDECL( OP_STR_SPREL), //10 0101 1000
-TABDECL( OP_STR_SPREL), //10 0101 1001
-TABDECL( OP_STR_SPREL), //10 0101 1010
-TABDECL( OP_STR_SPREL), //10 0101 1011
-TABDECL( OP_STR_SPREL), //10 0101 1100
-TABDECL( OP_STR_SPREL), //10 0101 1101
-TABDECL( OP_STR_SPREL), //10 0101 1110
-TABDECL( OP_STR_SPREL), //10 0101 1111
-
-TABDECL( OP_LDR_SPREL), //10 0110 0000
-TABDECL( OP_LDR_SPREL), //10 0110 0001
-TABDECL( OP_LDR_SPREL), //10 0110 0010
-TABDECL( OP_LDR_SPREL), //10 0110 0011
-TABDECL( OP_LDR_SPREL), //10 0110 0100
-TABDECL( OP_LDR_SPREL), //10 0110 0101
-TABDECL( OP_LDR_SPREL), //10 0110 0110
-TABDECL( OP_LDR_SPREL), //10 0110 0111
-TABDECL( OP_LDR_SPREL), //10 0110 1000
-TABDECL( OP_LDR_SPREL), //10 0110 1001
-TABDECL( OP_LDR_SPREL), //10 0110 1010
-TABDECL( OP_LDR_SPREL), //10 0110 1011
-TABDECL( OP_LDR_SPREL), //10 0110 1100
-TABDECL( OP_LDR_SPREL), //10 0110 1101
-TABDECL( OP_LDR_SPREL), //10 0110 1110
-TABDECL( OP_LDR_SPREL), //10 0110 1111
-
-TABDECL( OP_LDR_SPREL), //10 0111 0000
-TABDECL( OP_LDR_SPREL), //10 0111 0001
-TABDECL( OP_LDR_SPREL), //10 0111 0010
-TABDECL( OP_LDR_SPREL), //10 0111 0011
-TABDECL( OP_LDR_SPREL), //10 0111 0100
-TABDECL( OP_LDR_SPREL), //10 0111 0101
-TABDECL( OP_LDR_SPREL), //10 0111 0110
-TABDECL( OP_LDR_SPREL), //10 0111 0111
-TABDECL( OP_LDR_SPREL), //10 0111 1000
-TABDECL( OP_LDR_SPREL), //10 0111 1001
-TABDECL( OP_LDR_SPREL), //10 0111 1010
-TABDECL( OP_LDR_SPREL), //10 0111 1011
-TABDECL( OP_LDR_SPREL), //10 0111 1100
-TABDECL( OP_LDR_SPREL), //10 0111 1101
-TABDECL( OP_LDR_SPREL), //10 0111 1110
-TABDECL( OP_LDR_SPREL), //10 0111 1111
-
-TABDECL( OP_ADD_2PC), //10 1000 0000
-TABDECL( OP_ADD_2PC), //10 1000 0001
-TABDECL( OP_ADD_2PC), //10 1000 0010
-TABDECL( OP_ADD_2PC), //10 1000 0011
-TABDECL( OP_ADD_2PC), //10 1000 0100
-TABDECL( OP_ADD_2PC), //10 1000 0101
-TABDECL( OP_ADD_2PC), //10 1000 0110
-TABDECL( OP_ADD_2PC), //10 1000 0111
-TABDECL( OP_ADD_2PC), //10 1000 1000
-TABDECL( OP_ADD_2PC), //10 1000 1001
-TABDECL( OP_ADD_2PC), //10 1000 1010
-TABDECL( OP_ADD_2PC), //10 1000 1011
-TABDECL( OP_ADD_2PC), //10 1000 1100
-TABDECL( OP_ADD_2PC), //10 1000 1101
-TABDECL( OP_ADD_2PC), //10 1000 1110
-TABDECL( OP_ADD_2PC), //10 1000 1111
-
-TABDECL( OP_ADD_2PC), //10 1001 0000
-TABDECL( OP_ADD_2PC), //10 1001 0001
-TABDECL( OP_ADD_2PC), //10 1001 0010
-TABDECL( OP_ADD_2PC), //10 1001 0011
-TABDECL( OP_ADD_2PC), //10 1001 0100
-TABDECL( OP_ADD_2PC), //10 1001 0101
-TABDECL( OP_ADD_2PC), //10 1001 0110
-TABDECL( OP_ADD_2PC), //10 1001 0111
-TABDECL( OP_ADD_2PC), //10 1001 1000
-TABDECL( OP_ADD_2PC), //10 1001 1001
-TABDECL( OP_ADD_2PC), //10 1001 1010
-TABDECL( OP_ADD_2PC), //10 1001 1011
-TABDECL( OP_ADD_2PC), //10 1001 1100
-TABDECL( OP_ADD_2PC), //10 1001 1101
-TABDECL( OP_ADD_2PC), //10 1001 1110
-TABDECL( OP_ADD_2PC), //10 1001 1111
-
-TABDECL( OP_ADD_2SP), //10 1010 0000
-TABDECL( OP_ADD_2SP), //10 1010 0001
-TABDECL( OP_ADD_2SP), //10 1010 0010
-TABDECL( OP_ADD_2SP), //10 1010 0011
-TABDECL( OP_ADD_2SP), //10 1010 0100
-TABDECL( OP_ADD_2SP), //10 1010 0101
-TABDECL( OP_ADD_2SP), //10 1010 0110
-TABDECL( OP_ADD_2SP), //10 1010 0111
-TABDECL( OP_ADD_2SP), //10 1010 1000
-TABDECL( OP_ADD_2SP), //10 1010 1001
-TABDECL( OP_ADD_2SP), //10 1010 1010
-TABDECL( OP_ADD_2SP), //10 1010 1011
-TABDECL( OP_ADD_2SP), //10 1010 1100
-TABDECL( OP_ADD_2SP), //10 1010 1101
-TABDECL( OP_ADD_2SP), //10 1010 1110
-TABDECL( OP_ADD_2SP), //10 1010 1111
-
-TABDECL( OP_ADD_2SP), //10 1011 0000
-TABDECL( OP_ADD_2SP), //10 1011 0001
-TABDECL( OP_ADD_2SP), //10 1011 0010
-TABDECL( OP_ADD_2SP), //10 1011 0011
-TABDECL( OP_ADD_2SP), //10 1011 0100
-TABDECL( OP_ADD_2SP), //10 1011 0101
-TABDECL( OP_ADD_2SP), //10 1011 0110
-TABDECL( OP_ADD_2SP), //10 1011 0111
-TABDECL( OP_ADD_2SP), //10 1011 1000
-TABDECL( OP_ADD_2SP), //10 1011 1001
-TABDECL( OP_ADD_2SP), //10 1011 1010
-TABDECL( OP_ADD_2SP), //10 1011 1011
-TABDECL( OP_ADD_2SP), //10 1011 1100
-TABDECL( OP_ADD_2SP), //10 1011 1101
-TABDECL( OP_ADD_2SP), //10 1011 1110
-TABDECL( OP_ADD_2SP), //10 1011 1111
-
-TABDECL( OP_ADJUST_P_SP), //10 1100 0000
-TABDECL( OP_ADJUST_P_SP), //10 1100 0001
-TABDECL( OP_ADJUST_M_SP), //10 1100 0010
-TABDECL( OP_ADJUST_M_SP), //10 1100 0011
-TABDECL( OP_UND_THUMB), //10 1100 0100
-TABDECL( OP_UND_THUMB), //10 1100 0101
-TABDECL( OP_UND_THUMB), //10 1100 0110
-TABDECL( OP_UND_THUMB), //10 1100 0111
-TABDECL( OP_UND_THUMB), //10 1100 1000
-TABDECL( OP_UND_THUMB), //10 1100 1001
-TABDECL( OP_UND_THUMB), //10 1100 1010
-TABDECL( OP_UND_THUMB), //10 1100 1011
-TABDECL( OP_UND_THUMB), //10 1100 1100
-TABDECL( OP_UND_THUMB), //10 1100 1101
-TABDECL( OP_UND_THUMB), //10 1100 1110
-TABDECL( OP_UND_THUMB), //10 1100 1111
-
-TABDECL( OP_PUSH), //10 1101 0000
-TABDECL( OP_PUSH), //10 1101 0001
-TABDECL( OP_PUSH), //10 1101 0010
-TABDECL( OP_PUSH), //10 1101 0011
-TABDECL( OP_PUSH_LR), //10 1101 0100
-TABDECL( OP_PUSH_LR), //10 1101 0101
-TABDECL( OP_PUSH_LR), //10 1101 0110
-TABDECL( OP_PUSH_LR), //10 1101 0111
-TABDECL( OP_UND_THUMB), //10 1101 1000
-TABDECL( OP_UND_THUMB), //10 1101 1001
-TABDECL( OP_UND_THUMB), //10 1101 1010
-TABDECL( OP_UND_THUMB), //10 1101 1011
-TABDECL( OP_UND_THUMB), //10 1101 1100
-TABDECL( OP_UND_THUMB), //10 1101 1101
-TABDECL( OP_UND_THUMB), //10 1101 1110
-TABDECL( OP_UND_THUMB), //10 1101 1111
-
-TABDECL( OP_UND_THUMB), //10 1110 0000
-TABDECL( OP_UND_THUMB), //10 1110 0001
-TABDECL( OP_UND_THUMB), //10 1110 0010
-TABDECL( OP_UND_THUMB), //10 1110 0011
-TABDECL( OP_UND_THUMB), //10 1110 0100
-TABDECL( OP_UND_THUMB), //10 1110 0101
-TABDECL( OP_UND_THUMB), //10 1110 0110
-TABDECL( OP_UND_THUMB), //10 1110 0111
-TABDECL( OP_UND_THUMB), //10 1110 1000
-TABDECL( OP_UND_THUMB), //10 1110 1001
-TABDECL( OP_UND_THUMB), //10 1110 1010
-TABDECL( OP_UND_THUMB), //10 1110 1011
-TABDECL( OP_UND_THUMB), //10 1110 1100
-TABDECL( OP_UND_THUMB), //10 1110 1101
-TABDECL( OP_UND_THUMB), //10 1110 1110
-TABDECL( OP_UND_THUMB), //10 1110 1111
-
-TABDECL( OP_POP), //10 1111 0000
-TABDECL( OP_POP), //10 1111 0001
-TABDECL( OP_POP), //10 1111 0010
-TABDECL( OP_POP), //10 1111 0011
-TABDECL( OP_POP_PC), //10 1111 0100
-TABDECL( OP_POP_PC), //10 1111 0101
-TABDECL( OP_POP_PC), //10 1111 0110
-TABDECL( OP_POP_PC), //10 1111 0111
-TABDECL( OP_BKPT_THUMB), //10 1111 1000
-TABDECL( OP_BKPT_THUMB), //10 1111 1001
-TABDECL( OP_BKPT_THUMB), //10 1111 1010
-TABDECL( OP_BKPT_THUMB), //10 1111 1011
-TABDECL( OP_UND_THUMB), //10 1111 1100
-TABDECL( OP_UND_THUMB), //10 1111 1101
-TABDECL( OP_UND_THUMB), //10 1111 1110
-TABDECL( OP_UND_THUMB), //10 1111 1111
-
-TABDECL( OP_STMIA_THUMB), //11 0000 0000
-TABDECL( OP_STMIA_THUMB), //11 0000 0001
-TABDECL( OP_STMIA_THUMB), //11 0000 0010
-TABDECL( OP_STMIA_THUMB), //11 0000 0011
-TABDECL( OP_STMIA_THUMB), //11 0000 0100
-TABDECL( OP_STMIA_THUMB), //11 0000 0101
-TABDECL( OP_STMIA_THUMB), //11 0000 0110
-TABDECL( OP_STMIA_THUMB), //11 0000 0111
-TABDECL( OP_STMIA_THUMB), //11 0000 1000
-TABDECL( OP_STMIA_THUMB), //11 0000 1001
-TABDECL( OP_STMIA_THUMB), //11 0000 1010
-TABDECL( OP_STMIA_THUMB), //11 0000 1011
-TABDECL( OP_STMIA_THUMB), //11 0000 1100
-TABDECL( OP_STMIA_THUMB), //11 0000 1101
-TABDECL( OP_STMIA_THUMB), //11 0000 1110
-TABDECL( OP_STMIA_THUMB), //11 0000 1111
-
-TABDECL( OP_STMIA_THUMB), //11 0001 0000
-TABDECL( OP_STMIA_THUMB), //11 0001 0001
-TABDECL( OP_STMIA_THUMB), //11 0001 0010
-TABDECL( OP_STMIA_THUMB), //11 0001 0011
-TABDECL( OP_STMIA_THUMB), //11 0001 0100
-TABDECL( OP_STMIA_THUMB), //11 0001 0101
-TABDECL( OP_STMIA_THUMB), //11 0001 0110
-TABDECL( OP_STMIA_THUMB), //11 0001 0111
-TABDECL( OP_STMIA_THUMB), //11 0001 1000
-TABDECL( OP_STMIA_THUMB), //11 0001 1001
-TABDECL( OP_STMIA_THUMB), //11 0001 1010
-TABDECL( OP_STMIA_THUMB), //11 0001 1011
-TABDECL( OP_STMIA_THUMB), //11 0001 1100
-TABDECL( OP_STMIA_THUMB), //11 0001 1101
-TABDECL( OP_STMIA_THUMB), //11 0001 1110
-TABDECL( OP_STMIA_THUMB), //11 0001 1111
-
-TABDECL( OP_LDMIA_THUMB), //11 0010 0000
-TABDECL( OP_LDMIA_THUMB), //11 0010 0001
-TABDECL( OP_LDMIA_THUMB), //11 0010 0010
-TABDECL( OP_LDMIA_THUMB), //11 0010 0011
-TABDECL( OP_LDMIA_THUMB), //11 0010 0100
-TABDECL( OP_LDMIA_THUMB), //11 0010 0101
-TABDECL( OP_LDMIA_THUMB), //11 0010 0110
-TABDECL( OP_LDMIA_THUMB), //11 0010 0111
-TABDECL( OP_LDMIA_THUMB), //11 0010 1000
-TABDECL( OP_LDMIA_THUMB), //11 0010 1001
-TABDECL( OP_LDMIA_THUMB), //11 0010 1010
-TABDECL( OP_LDMIA_THUMB), //11 0010 1011
-TABDECL( OP_LDMIA_THUMB), //11 0010 1100
-TABDECL( OP_LDMIA_THUMB), //11 0010 1101
-TABDECL( OP_LDMIA_THUMB), //11 0010 1110
-TABDECL( OP_LDMIA_THUMB), //11 0010 1111
-
-TABDECL( OP_LDMIA_THUMB), //11 0011 0000
-TABDECL( OP_LDMIA_THUMB), //11 0011 0001
-TABDECL( OP_LDMIA_THUMB), //11 0011 0010
-TABDECL( OP_LDMIA_THUMB), //11 0011 0011
-TABDECL( OP_LDMIA_THUMB), //11 0011 0100
-TABDECL( OP_LDMIA_THUMB), //11 0011 0101
-TABDECL( OP_LDMIA_THUMB), //11 0011 0110
-TABDECL( OP_LDMIA_THUMB), //11 0011 0111
-TABDECL( OP_LDMIA_THUMB), //11 0011 1000
-TABDECL( OP_LDMIA_THUMB), //11 0011 1001
-TABDECL( OP_LDMIA_THUMB), //11 0011 1010
-TABDECL( OP_LDMIA_THUMB), //11 0011 1011
-TABDECL( OP_LDMIA_THUMB), //11 0011 1100
-TABDECL( OP_LDMIA_THUMB), //11 0011 1101
-TABDECL( OP_LDMIA_THUMB), //11 0011 1110
-TABDECL( OP_LDMIA_THUMB), //11 0011 1111
-
-TABDECL( OP_B_COND), //11 0100 0000
-TABDECL( OP_B_COND), //11 0100 0001
-TABDECL( OP_B_COND), //11 0100 0010
-TABDECL( OP_B_COND), //11 0100 0011
-TABDECL( OP_B_COND), //11 0100 0100
-TABDECL( OP_B_COND), //11 0100 0101
-TABDECL( OP_B_COND), //11 0100 0110
-TABDECL( OP_B_COND), //11 0100 0111
-TABDECL( OP_B_COND), //11 0100 1000
-TABDECL( OP_B_COND), //11 0100 1001
-TABDECL( OP_B_COND), //11 0100 1010
-TABDECL( OP_B_COND), //11 0100 1011
-TABDECL( OP_B_COND), //11 0100 1100
-TABDECL( OP_B_COND), //11 0100 1101
-TABDECL( OP_B_COND), //11 0100 1110
-TABDECL( OP_B_COND), //11 0100 1111
-
-TABDECL( OP_B_COND), //11 0101 0000
-TABDECL( OP_B_COND), //11 0101 0001
-TABDECL( OP_B_COND), //11 0101 0010
-TABDECL( OP_B_COND), //11 0101 0011
-TABDECL( OP_B_COND), //11 0101 0100
-TABDECL( OP_B_COND), //11 0101 0101
-TABDECL( OP_B_COND), //11 0101 0110
-TABDECL( OP_B_COND), //11 0101 0111
-TABDECL( OP_B_COND), //11 0101 1000
-TABDECL( OP_B_COND), //11 0101 1001
-TABDECL( OP_B_COND), //11 0101 1010
-TABDECL( OP_B_COND), //11 0101 1011
-TABDECL( OP_B_COND), //11 0101 1100
-TABDECL( OP_B_COND), //11 0101 1101
-TABDECL( OP_B_COND), //11 0101 1110
-TABDECL( OP_B_COND), //11 0101 1111
-
-TABDECL( OP_B_COND), //11 0110 0000
-TABDECL( OP_B_COND), //11 0110 0001
-TABDECL( OP_B_COND), //11 0110 0010
-TABDECL( OP_B_COND), //11 0110 0011
-TABDECL( OP_B_COND), //11 0110 0100
-TABDECL( OP_B_COND), //11 0110 0101
-TABDECL( OP_B_COND), //11 0110 0110
-TABDECL( OP_B_COND), //11 0110 0111
-TABDECL( OP_B_COND), //11 0110 1000
-TABDECL( OP_B_COND), //11 0110 1001
-TABDECL( OP_B_COND), //11 0110 1010
-TABDECL( OP_B_COND), //11 0110 1011
-TABDECL( OP_B_COND), //11 0110 1100
-TABDECL( OP_B_COND), //11 0110 1101
-TABDECL( OP_B_COND), //11 0110 1110
-TABDECL( OP_B_COND), //11 0110 1111
-
-TABDECL( OP_B_COND), //11 0111 0000
-TABDECL( OP_B_COND), //11 0111 0001
-TABDECL( OP_B_COND), //11 0111 0010
-TABDECL( OP_B_COND), //11 0111 0011
-TABDECL( OP_B_COND), //11 0111 0100
-TABDECL( OP_B_COND), //11 0111 0101
-TABDECL( OP_B_COND), //11 0111 0110
-TABDECL( OP_B_COND), //11 0111 0111
-TABDECL( OP_B_COND), //11 0111 1000
-TABDECL( OP_B_COND), //11 0111 1001
-TABDECL( OP_B_COND), //11 0111 1010
-TABDECL( OP_B_COND), //11 0111 1011
-TABDECL( OP_SWI_THUMB), //11 0111 1100
-TABDECL( OP_SWI_THUMB), //11 0111 1101
-TABDECL( OP_SWI_THUMB), //11 0111 1110
-TABDECL( OP_SWI_THUMB), //11 0111 1111
-
-TABDECL( OP_B_UNCOND), //11 1000 0000
-TABDECL( OP_B_UNCOND), //11 1000 0001
-TABDECL( OP_B_UNCOND), //11 1000 0010
-TABDECL( OP_B_UNCOND), //11 1000 0011
-TABDECL( OP_B_UNCOND), //11 1000 0100
-TABDECL( OP_B_UNCOND), //11 1000 0101
-TABDECL( OP_B_UNCOND), //11 1000 0110
-TABDECL( OP_B_UNCOND), //11 1000 0111
-TABDECL( OP_B_UNCOND), //11 1000 1000
-TABDECL( OP_B_UNCOND), //11 1000 1001
-TABDECL( OP_B_UNCOND), //11 1000 1010
-TABDECL( OP_B_UNCOND), //11 1000 1011
-TABDECL( OP_B_UNCOND), //11 1000 1100
-TABDECL( OP_B_UNCOND), //11 1000 1101
-TABDECL( OP_B_UNCOND), //11 1000 1110
-TABDECL( OP_B_UNCOND), //11 1000 1111
-
-TABDECL( OP_B_UNCOND), //11 1001 0000
-TABDECL( OP_B_UNCOND), //11 1001 0001
-TABDECL( OP_B_UNCOND), //11 1001 0010
-TABDECL( OP_B_UNCOND), //11 1001 0011
-TABDECL( OP_B_UNCOND), //11 1001 0100
-TABDECL( OP_B_UNCOND), //11 1001 0101
-TABDECL( OP_B_UNCOND), //11 1001 0110
-TABDECL( OP_B_UNCOND), //11 1001 0111
-TABDECL( OP_B_UNCOND), //11 1001 1000
-TABDECL( OP_B_UNCOND), //11 1001 1001
-TABDECL( OP_B_UNCOND), //11 1001 1010
-TABDECL( OP_B_UNCOND), //11 1001 1011
-TABDECL( OP_B_UNCOND), //11 1001 1100
-TABDECL( OP_B_UNCOND), //11 1001 1101
-TABDECL( OP_B_UNCOND), //11 1001 1110
-TABDECL( OP_B_UNCOND), //11 1001 1111
-
-TABDECL( OP_BLX), //11 1010 0000
-TABDECL( OP_BLX), //11 1010 0001
-TABDECL( OP_BLX), //11 1010 0010
-TABDECL( OP_BLX), //11 1010 0011
-TABDECL( OP_BLX), //11 1010 0100
-TABDECL( OP_BLX), //11 1010 0101
-TABDECL( OP_BLX), //11 1010 0110
-TABDECL( OP_BLX), //11 1010 0111
-TABDECL( OP_BLX), //11 1010 1000
-TABDECL( OP_BLX), //11 1010 1001
-TABDECL( OP_BLX), //11 1010 1010
-TABDECL( OP_BLX), //11 1010 1011
-TABDECL( OP_BLX), //11 1010 1100
-TABDECL( OP_BLX), //11 1010 1101
-TABDECL( OP_BLX), //11 1010 1110
-TABDECL( OP_BLX), //11 1010 1111
-
-TABDECL( OP_BLX), //11 1011 0000
-TABDECL( OP_BLX), //11 1011 0001
-TABDECL( OP_BLX), //11 1011 0010
-TABDECL( OP_BLX), //11 1011 0011
-TABDECL( OP_BLX), //11 1011 0100
-TABDECL( OP_BLX), //11 1011 0101
-TABDECL( OP_BLX), //11 1011 0110
-TABDECL( OP_BLX), //11 1011 0111
-TABDECL( OP_BLX), //11 1011 1000
-TABDECL( OP_BLX), //11 1011 1001
-TABDECL( OP_BLX), //11 1011 1010
-TABDECL( OP_BLX), //11 1011 1011
-TABDECL( OP_BLX), //11 1011 1100
-TABDECL( OP_BLX), //11 1011 1101
-TABDECL( OP_BLX), //11 1011 1110
-TABDECL( OP_BLX), //11 1011 1111
-
-TABDECL( OP_BL_10), //11 1100 0000
-TABDECL( OP_BL_10), //11 1100 0001
-TABDECL( OP_BL_10), //11 1100 0010
-TABDECL( OP_BL_10), //11 1100 0011
-TABDECL( OP_BL_10), //11 1100 0100
-TABDECL( OP_BL_10), //11 1100 0101
-TABDECL( OP_BL_10), //11 1100 0110
-TABDECL( OP_BL_10), //11 1100 0111
-TABDECL( OP_BL_10), //11 1100 1000
-TABDECL( OP_BL_10), //11 1100 1001
-TABDECL( OP_BL_10), //11 1100 1010
-TABDECL( OP_BL_10), //11 1100 1011
-TABDECL( OP_BL_10), //11 1100 1100
-TABDECL( OP_BL_10), //11 1100 1101
-TABDECL( OP_BL_10), //11 1100 1110
-TABDECL( OP_BL_10), //11 1100 1111
-
-TABDECL( OP_BL_10), //11 1101 0000
-TABDECL( OP_BL_10), //11 1101 0001
-TABDECL( OP_BL_10), //11 1101 0010
-TABDECL( OP_BL_10), //11 1101 0011
-TABDECL( OP_BL_10), //11 1101 0100
-TABDECL( OP_BL_10), //11 1101 0101
-TABDECL( OP_BL_10), //11 1101 0110
-TABDECL( OP_BL_10), //11 1101 0111
-TABDECL( OP_BL_10), //11 1101 1000
-TABDECL( OP_BL_10), //11 1101 1001
-TABDECL( OP_BL_10), //11 1101 1010
-TABDECL( OP_BL_10), //11 1101 1011
-TABDECL( OP_BL_10), //11 1101 1100
-TABDECL( OP_BL_10), //11 1101 1101
-TABDECL( OP_BL_10), //11 1101 1110
-TABDECL( OP_BL_10), //11 1101 1111
-
-TABDECL( OP_BL_11), //11 1110 0000
-TABDECL( OP_BL_11), //11 1110 0001
-TABDECL( OP_BL_11), //11 1110 0010
-TABDECL( OP_BL_11), //11 1110 0011
-TABDECL( OP_BL_11), //11 1110 0100
-TABDECL( OP_BL_11), //11 1110 0101
-TABDECL( OP_BL_11), //11 1110 0110
-TABDECL( OP_BL_11), //11 1110 0111
-TABDECL( OP_BL_11), //11 1110 1000
-TABDECL( OP_BL_11), //11 1110 1001
-TABDECL( OP_BL_11), //11 1110 1010
-TABDECL( OP_BL_11), //11 1110 1011
-TABDECL( OP_BL_11), //11 1110 1100
-TABDECL( OP_BL_11), //11 1110 1101
-TABDECL( OP_BL_11), //11 1110 1110
-TABDECL( OP_BL_11), //11 1110 1111
-
-TABDECL( OP_BL_11), //11 1111 0000
-TABDECL( OP_BL_11), //11 1111 0001
-TABDECL( OP_BL_11), //11 1111 0010
-TABDECL( OP_BL_11), //11 1111 0011
-TABDECL( OP_BL_11), //11 1111 0100
-TABDECL( OP_BL_11), //11 1111 0101
-TABDECL( OP_BL_11), //11 1111 0110
-TABDECL( OP_BL_11), //11 1111 0111
-TABDECL( OP_BL_11), //11 1111 1000
-TABDECL( OP_BL_11), //11 1111 1001
-TABDECL( OP_BL_11), //11 1111 1010
-TABDECL( OP_BL_11), //11 1111 1011
-TABDECL( OP_BL_11), //11 1111 1100
-TABDECL( OP_BL_11), //11 1111 1101
-TABDECL( OP_BL_11), //11 1111 1110
-TABDECL( OP_BL_11), //11 1111 1111
-
+/* 00 0000 0000 */ TABDECL(OP_LSL_0), // OP_LSL_0
+/* 00 0000 0001 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0000 0010 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0000 0011 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0000 0100 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0000 0101 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0000 0110 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0000 0111 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0000 1000 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0000 1001 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0000 1010 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0000 1011 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0000 1100 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0000 1101 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0000 1110 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0000 1111 */ TABDECL(OP_LSL), // OP_LSL
+
+/* 00 0001 0000 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0001 0001 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0001 0010 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0001 0011 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0001 0100 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0001 0101 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0001 0110 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0001 0111 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0001 1000 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0001 1001 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0001 1010 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0001 1011 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0001 1100 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0001 1101 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0001 1110 */ TABDECL(OP_LSL), // OP_LSL
+/* 00 0001 1111 */ TABDECL(OP_LSL), // OP_LSL
+
+/* 00 0010 0000 */ TABDECL(OP_LSR_0), // OP_LSR_0
+/* 00 0010 0001 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0010 0010 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0010 0011 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0010 0100 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0010 0101 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0010 0110 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0010 0111 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0010 1000 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0010 1001 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0010 1010 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0010 1011 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0010 1100 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0010 1101 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0010 1110 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0010 1111 */ TABDECL(OP_LSR), // OP_LSR
+
+/* 00 0011 0000 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0011 0001 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0011 0010 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0011 0011 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0011 0100 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0011 0101 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0011 0110 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0011 0111 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0011 1000 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0011 1001 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0011 1010 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0011 1011 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0011 1100 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0011 1101 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0011 1110 */ TABDECL(OP_LSR), // OP_LSR
+/* 00 0011 1111 */ TABDECL(OP_LSR), // OP_LSR
+
+/* 00 0100 0000 */ TABDECL(OP_ASR_0), // OP_ASR_0
+/* 00 0100 0001 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0100 0010 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0100 0011 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0100 0100 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0100 0101 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0100 0110 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0100 0111 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0100 1000 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0100 1001 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0100 1010 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0100 1011 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0100 1100 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0100 1101 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0100 1110 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0100 1111 */ TABDECL(OP_ASR), // OP_ASR
+
+/* 00 0101 0000 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0101 0001 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0101 0010 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0101 0011 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0101 0100 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0101 0101 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0101 0110 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0101 0111 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0101 1000 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0101 1001 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0101 1010 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0101 1011 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0101 1100 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0101 1101 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0101 1110 */ TABDECL(OP_ASR), // OP_ASR
+/* 00 0101 1111 */ TABDECL(OP_ASR), // OP_ASR
+
+/* 00 0110 0000 */ TABDECL(OP_ADD_REG), // OP_ADD_REG
+/* 00 0110 0001 */ TABDECL(OP_ADD_REG), // OP_ADD_REG
+/* 00 0110 0010 */ TABDECL(OP_ADD_REG), // OP_ADD_REG
+/* 00 0110 0011 */ TABDECL(OP_ADD_REG), // OP_ADD_REG
+/* 00 0110 0100 */ TABDECL(OP_ADD_REG), // OP_ADD_REG
+/* 00 0110 0101 */ TABDECL(OP_ADD_REG), // OP_ADD_REG
+/* 00 0110 0110 */ TABDECL(OP_ADD_REG), // OP_ADD_REG
+/* 00 0110 0111 */ TABDECL(OP_ADD_REG), // OP_ADD_REG
+/* 00 0110 1000 */ TABDECL(OP_SUB_REG), // OP_SUB_REG
+/* 00 0110 1001 */ TABDECL(OP_SUB_REG), // OP_SUB_REG
+/* 00 0110 1010 */ TABDECL(OP_SUB_REG), // OP_SUB_REG
+/* 00 0110 1011 */ TABDECL(OP_SUB_REG), // OP_SUB_REG
+/* 00 0110 1100 */ TABDECL(OP_SUB_REG), // OP_SUB_REG
+/* 00 0110 1101 */ TABDECL(OP_SUB_REG), // OP_SUB_REG
+/* 00 0110 1110 */ TABDECL(OP_SUB_REG), // OP_SUB_REG
+/* 00 0110 1111 */ TABDECL(OP_SUB_REG), // OP_SUB_REG
+
+/* 00 0111 0000 */ TABDECL(OP_ADD_IMM3), // OP_ADD_IMM3
+/* 00 0111 0001 */ TABDECL(OP_ADD_IMM3), // OP_ADD_IMM3
+/* 00 0111 0010 */ TABDECL(OP_ADD_IMM3), // OP_ADD_IMM3
+/* 00 0111 0011 */ TABDECL(OP_ADD_IMM3), // OP_ADD_IMM3
+/* 00 0111 0100 */ TABDECL(OP_ADD_IMM3), // OP_ADD_IMM3
+/* 00 0111 0101 */ TABDECL(OP_ADD_IMM3), // OP_ADD_IMM3
+/* 00 0111 0110 */ TABDECL(OP_ADD_IMM3), // OP_ADD_IMM3
+/* 00 0111 0111 */ TABDECL(OP_ADD_IMM3), // OP_ADD_IMM3
+/* 00 0111 1000 */ TABDECL(OP_SUB_IMM3), // OP_SUB_IMM3
+/* 00 0111 1001 */ TABDECL(OP_SUB_IMM3), // OP_SUB_IMM3
+/* 00 0111 1010 */ TABDECL(OP_SUB_IMM3), // OP_SUB_IMM3
+/* 00 0111 1011 */ TABDECL(OP_SUB_IMM3), // OP_SUB_IMM3
+/* 00 0111 1100 */ TABDECL(OP_SUB_IMM3), // OP_SUB_IMM3
+/* 00 0111 1101 */ TABDECL(OP_SUB_IMM3), // OP_SUB_IMM3
+/* 00 0111 1110 */ TABDECL(OP_SUB_IMM3), // OP_SUB_IMM3
+/* 00 0111 1111 */ TABDECL(OP_SUB_IMM3), // OP_SUB_IMM3
+
+/* 00 1000 0000 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1000 0001 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1000 0010 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1000 0011 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1000 0100 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1000 0101 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1000 0110 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1000 0111 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1000 1000 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1000 1001 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1000 1010 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1000 1011 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1000 1100 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1000 1101 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1000 1110 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1000 1111 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+
+/* 00 1001 0000 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1001 0001 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1001 0010 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1001 0011 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1001 0100 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1001 0101 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1001 0110 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1001 0111 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1001 1000 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1001 1001 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1001 1010 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1001 1011 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1001 1100 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1001 1101 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1001 1110 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+/* 00 1001 1111 */ TABDECL(OP_MOV_IMM8), // OP_MOV_IMM8
+
+/* 00 1010 0000 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1010 0001 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1010 0010 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1010 0011 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1010 0100 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1010 0101 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1010 0110 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1010 0111 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1010 1000 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1010 1001 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1010 1010 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1010 1011 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1010 1100 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1010 1101 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1010 1110 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1010 1111 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+
+/* 00 1011 0000 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1011 0001 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1011 0010 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1011 0011 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1011 0100 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1011 0101 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1011 0110 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1011 0111 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1011 1000 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1011 1001 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1011 1010 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1011 1011 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1011 1100 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1011 1101 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1011 1110 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+/* 00 1011 1111 */ TABDECL(OP_CMP_IMM8), // OP_CMP_IMM8
+
+/* 00 1100 0000 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1100 0001 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1100 0010 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1100 0011 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1100 0100 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1100 0101 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1100 0110 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1100 0111 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1100 1000 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1100 1001 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1100 1010 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1100 1011 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1100 1100 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1100 1101 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1100 1110 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1100 1111 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+
+/* 00 1101 0000 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1101 0001 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1101 0010 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1101 0011 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1101 0100 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1101 0101 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1101 0110 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1101 0111 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1101 1000 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1101 1001 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1101 1010 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1101 1011 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1101 1100 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1101 1101 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1101 1110 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+/* 00 1101 1111 */ TABDECL(OP_ADD_IMM8), // OP_ADD_IMM8
+
+/* 00 1110 0000 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1110 0001 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1110 0010 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1110 0011 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1110 0100 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1110 0101 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1110 0110 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1110 0111 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1110 1000 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1110 1001 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1110 1010 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1110 1011 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1110 1100 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1110 1101 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1110 1110 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1110 1111 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+
+/* 00 1111 0000 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1111 0001 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1111 0010 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1111 0011 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1111 0100 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1111 0101 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1111 0110 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1111 0111 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1111 1000 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1111 1001 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1111 1010 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1111 1011 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1111 1100 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1111 1101 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1111 1110 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+/* 00 1111 1111 */ TABDECL(OP_SUB_IMM8), // OP_SUB_IMM8
+
+/* 01 0000 0000 */ TABDECL(OP_AND), // OP_AND
+/* 01 0000 0001 */ TABDECL(OP_EOR), // OP_EOR
+/* 01 0000 0010 */ TABDECL(OP_LSL_REG), // OP_LSL_REG
+/* 01 0000 0011 */ TABDECL(OP_LSR_REG), // OP_LSR_REG
+/* 01 0000 0100 */ TABDECL(OP_ASR_REG), // OP_ASR_REG
+/* 01 0000 0101 */ TABDECL(OP_ADC_REG), // OP_ADC_REG
+/* 01 0000 0110 */ TABDECL(OP_SBC_REG), // OP_SBC_REG
+/* 01 0000 0111 */ TABDECL(OP_ROR_REG), // OP_ROR_REG
+/* 01 0000 1000 */ TABDECL(OP_TST), // OP_TST
+/* 01 0000 1001 */ TABDECL(OP_NEG), // OP_NEG
+/* 01 0000 1010 */ TABDECL(OP_CMP), // OP_CMP
+/* 01 0000 1011 */ TABDECL(OP_CMN), // OP_CMN
+/* 01 0000 1100 */ TABDECL(OP_ORR), // OP_ORR
+/* 01 0000 1101 */ TABDECL(OP_MUL_REG), // OP_MUL_REG
+/* 01 0000 1110 */ TABDECL(OP_BIC), // OP_BIC
+/* 01 0000 1111 */ TABDECL(OP_MVN), // OP_MVN
+
+/* 01 0001 0000 */ TABDECL(OP_ADD_SPE), // OP_ADD_SPE
+/* 01 0001 0001 */ TABDECL(OP_ADD_SPE), // OP_ADD_SPE
+/* 01 0001 0010 */ TABDECL(OP_ADD_SPE), // OP_ADD_SPE
+/* 01 0001 0011 */ TABDECL(OP_ADD_SPE), // OP_ADD_SPE
+/* 01 0001 0100 */ TABDECL(OP_CMP_SPE), // OP_CMP_SPE
+/* 01 0001 0101 */ TABDECL(OP_CMP_SPE), // OP_CMP_SPE
+/* 01 0001 0110 */ TABDECL(OP_CMP_SPE), // OP_CMP_SPE
+/* 01 0001 0111 */ TABDECL(OP_CMP_SPE), // OP_CMP_SPE
+/* 01 0001 1000 */ TABDECL(OP_MOV_SPE), // OP_MOV_SPE
+/* 01 0001 1001 */ TABDECL(OP_MOV_SPE), // OP_MOV_SPE
+/* 01 0001 1010 */ TABDECL(OP_MOV_SPE), // OP_MOV_SPE
+/* 01 0001 1011 */ TABDECL(OP_MOV_SPE), // OP_MOV_SPE
+/* 01 0001 1100 */ TABDECL(OP_BX_THUMB), // OP_BX_THUMB
+/* 01 0001 1101 */ TABDECL(OP_BX_THUMB), // OP_BX_THUMB
+/* 01 0001 1110 */ TABDECL(OP_BLX_THUMB), // OP_BLX_THUMB
+/* 01 0001 1111 */ TABDECL(OP_BLX_THUMB), // OP_BLX_THUMB
+
+/* 01 0010 0000 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0010 0001 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0010 0010 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0010 0011 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0010 0100 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0010 0101 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0010 0110 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0010 0111 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0010 1000 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0010 1001 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0010 1010 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0010 1011 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0010 1100 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0010 1101 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0010 1110 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0010 1111 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+
+/* 01 0011 0000 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0011 0001 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0011 0010 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0011 0011 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0011 0100 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0011 0101 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0011 0110 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0011 0111 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0011 1000 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0011 1001 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0011 1010 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0011 1011 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0011 1100 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0011 1101 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0011 1110 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+/* 01 0011 1111 */ TABDECL(OP_LDR_PCREL), // OP_LDR_PCREL
+
+/* 01 0100 0000 */ TABDECL(OP_STR_REG_OFF), // OP_STR_REG_OFF
+/* 01 0100 0001 */ TABDECL(OP_STR_REG_OFF), // OP_STR_REG_OFF
+/* 01 0100 0010 */ TABDECL(OP_STR_REG_OFF), // OP_STR_REG_OFF
+/* 01 0100 0011 */ TABDECL(OP_STR_REG_OFF), // OP_STR_REG_OFF
+/* 01 0100 0100 */ TABDECL(OP_STR_REG_OFF), // OP_STR_REG_OFF
+/* 01 0100 0101 */ TABDECL(OP_STR_REG_OFF), // OP_STR_REG_OFF
+/* 01 0100 0110 */ TABDECL(OP_STR_REG_OFF), // OP_STR_REG_OFF
+/* 01 0100 0111 */ TABDECL(OP_STR_REG_OFF), // OP_STR_REG_OFF
+/* 01 0100 1000 */ TABDECL(OP_STRH_REG_OFF), // OP_STRH_REG_OFF
+/* 01 0100 1001 */ TABDECL(OP_STRH_REG_OFF), // OP_STRH_REG_OFF
+/* 01 0100 1010 */ TABDECL(OP_STRH_REG_OFF), // OP_STRH_REG_OFF
+/* 01 0100 1011 */ TABDECL(OP_STRH_REG_OFF), // OP_STRH_REG_OFF
+/* 01 0100 1100 */ TABDECL(OP_STRH_REG_OFF), // OP_STRH_REG_OFF
+/* 01 0100 1101 */ TABDECL(OP_STRH_REG_OFF), // OP_STRH_REG_OFF
+/* 01 0100 1110 */ TABDECL(OP_STRH_REG_OFF), // OP_STRH_REG_OFF
+/* 01 0100 1111 */ TABDECL(OP_STRH_REG_OFF), // OP_STRH_REG_OFF
+
+/* 01 0101 0000 */ TABDECL(OP_STRB_REG_OFF), // OP_STRB_REG_OFF
+/* 01 0101 0001 */ TABDECL(OP_STRB_REG_OFF), // OP_STRB_REG_OFF
+/* 01 0101 0010 */ TABDECL(OP_STRB_REG_OFF), // OP_STRB_REG_OFF
+/* 01 0101 0011 */ TABDECL(OP_STRB_REG_OFF), // OP_STRB_REG_OFF
+/* 01 0101 0100 */ TABDECL(OP_STRB_REG_OFF), // OP_STRB_REG_OFF
+/* 01 0101 0101 */ TABDECL(OP_STRB_REG_OFF), // OP_STRB_REG_OFF
+/* 01 0101 0110 */ TABDECL(OP_STRB_REG_OFF), // OP_STRB_REG_OFF
+/* 01 0101 0111 */ TABDECL(OP_STRB_REG_OFF), // OP_STRB_REG_OFF
+/* 01 0101 1000 */ TABDECL(OP_LDRSB_REG_OFF), // OP_LDRSB_REG_OFF
+/* 01 0101 1001 */ TABDECL(OP_LDRSB_REG_OFF), // OP_LDRSB_REG_OFF
+/* 01 0101 1010 */ TABDECL(OP_LDRSB_REG_OFF), // OP_LDRSB_REG_OFF
+/* 01 0101 1011 */ TABDECL(OP_LDRSB_REG_OFF), // OP_LDRSB_REG_OFF
+/* 01 0101 1100 */ TABDECL(OP_LDRSB_REG_OFF), // OP_LDRSB_REG_OFF
+/* 01 0101 1101 */ TABDECL(OP_LDRSB_REG_OFF), // OP_LDRSB_REG_OFF
+/* 01 0101 1110 */ TABDECL(OP_LDRSB_REG_OFF), // OP_LDRSB_REG_OFF
+/* 01 0101 1111 */ TABDECL(OP_LDRSB_REG_OFF), // OP_LDRSB_REG_OFF
+
+/* 01 0110 0000 */ TABDECL(OP_LDR_REG_OFF), // OP_LDR_REG_OFF
+/* 01 0110 0001 */ TABDECL(OP_LDR_REG_OFF), // OP_LDR_REG_OFF
+/* 01 0110 0010 */ TABDECL(OP_LDR_REG_OFF), // OP_LDR_REG_OFF
+/* 01 0110 0011 */ TABDECL(OP_LDR_REG_OFF), // OP_LDR_REG_OFF
+/* 01 0110 0100 */ TABDECL(OP_LDR_REG_OFF), // OP_LDR_REG_OFF
+/* 01 0110 0101 */ TABDECL(OP_LDR_REG_OFF), // OP_LDR_REG_OFF
+/* 01 0110 0110 */ TABDECL(OP_LDR_REG_OFF), // OP_LDR_REG_OFF
+/* 01 0110 0111 */ TABDECL(OP_LDR_REG_OFF), // OP_LDR_REG_OFF
+/* 01 0110 1000 */ TABDECL(OP_LDRH_REG_OFF), // OP_LDRH_REG_OFF
+/* 01 0110 1001 */ TABDECL(OP_LDRH_REG_OFF), // OP_LDRH_REG_OFF
+/* 01 0110 1010 */ TABDECL(OP_LDRH_REG_OFF), // OP_LDRH_REG_OFF
+/* 01 0110 1011 */ TABDECL(OP_LDRH_REG_OFF), // OP_LDRH_REG_OFF
+/* 01 0110 1100 */ TABDECL(OP_LDRH_REG_OFF), // OP_LDRH_REG_OFF
+/* 01 0110 1101 */ TABDECL(OP_LDRH_REG_OFF), // OP_LDRH_REG_OFF
+/* 01 0110 1110 */ TABDECL(OP_LDRH_REG_OFF), // OP_LDRH_REG_OFF
+/* 01 0110 1111 */ TABDECL(OP_LDRH_REG_OFF), // OP_LDRH_REG_OFF
+
+/* 01 0111 0000 */ TABDECL(OP_LDRB_REG_OFF), // OP_LDRB_REG_OFF
+/* 01 0111 0001 */ TABDECL(OP_LDRB_REG_OFF), // OP_LDRB_REG_OFF
+/* 01 0111 0010 */ TABDECL(OP_LDRB_REG_OFF), // OP_LDRB_REG_OFF
+/* 01 0111 0011 */ TABDECL(OP_LDRB_REG_OFF), // OP_LDRB_REG_OFF
+/* 01 0111 0100 */ TABDECL(OP_LDRB_REG_OFF), // OP_LDRB_REG_OFF
+/* 01 0111 0101 */ TABDECL(OP_LDRB_REG_OFF), // OP_LDRB_REG_OFF
+/* 01 0111 0110 */ TABDECL(OP_LDRB_REG_OFF), // OP_LDRB_REG_OFF
+/* 01 0111 0111 */ TABDECL(OP_LDRB_REG_OFF), // OP_LDRB_REG_OFF
+/* 01 0111 1000 */ TABDECL(OP_LDRSH_REG_OFF), // OP_LDRSH_REG_OFF
+/* 01 0111 1001 */ TABDECL(OP_LDRSH_REG_OFF), // OP_LDRSH_REG_OFF
+/* 01 0111 1010 */ TABDECL(OP_LDRSH_REG_OFF), // OP_LDRSH_REG_OFF
+/* 01 0111 1011 */ TABDECL(OP_LDRSH_REG_OFF), // OP_LDRSH_REG_OFF
+/* 01 0111 1100 */ TABDECL(OP_LDRSH_REG_OFF), // OP_LDRSH_REG_OFF
+/* 01 0111 1101 */ TABDECL(OP_LDRSH_REG_OFF), // OP_LDRSH_REG_OFF
+/* 01 0111 1110 */ TABDECL(OP_LDRSH_REG_OFF), // OP_LDRSH_REG_OFF
+/* 01 0111 1111 */ TABDECL(OP_LDRSH_REG_OFF), // OP_LDRSH_REG_OFF
+
+/* 01 1000 0000 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1000 0001 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1000 0010 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1000 0011 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1000 0100 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1000 0101 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1000 0110 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1000 0111 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1000 1000 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1000 1001 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1000 1010 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1000 1011 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1000 1100 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1000 1101 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1000 1110 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1000 1111 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+
+/* 01 1001 0000 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1001 0001 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1001 0010 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1001 0011 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1001 0100 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1001 0101 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1001 0110 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1001 0111 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1001 1000 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1001 1001 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1001 1010 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1001 1011 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1001 1100 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1001 1101 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1001 1110 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+/* 01 1001 1111 */ TABDECL(OP_STR_IMM_OFF), // OP_STR_IMM_OFF
+
+/* 01 1010 0000 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1010 0001 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1010 0010 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1010 0011 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1010 0100 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1010 0101 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1010 0110 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1010 0111 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1010 1000 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1010 1001 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1010 1010 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1010 1011 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1010 1100 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1010 1101 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1010 1110 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1010 1111 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+
+/* 01 1011 0000 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1011 0001 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1011 0010 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1011 0011 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1011 0100 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1011 0101 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1011 0110 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1011 0111 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1011 1000 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1011 1001 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1011 1010 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1011 1011 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1011 1100 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1011 1101 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1011 1110 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+/* 01 1011 1111 */ TABDECL(OP_LDR_IMM_OFF), // OP_LDR_IMM_OFF
+
+/* 01 1100 0000 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1100 0001 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1100 0010 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1100 0011 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1100 0100 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1100 0101 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1100 0110 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1100 0111 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1100 1000 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1100 1001 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1100 1010 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1100 1011 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1100 1100 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1100 1101 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1100 1110 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1100 1111 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+
+/* 01 1101 0000 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1101 0001 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1101 0010 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1101 0011 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1101 0100 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1101 0101 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1101 0110 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1101 0111 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1101 1000 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1101 1001 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1101 1010 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1101 1011 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1101 1100 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1101 1101 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1101 1110 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+/* 01 1101 1111 */ TABDECL(OP_STRB_IMM_OFF), // OP_STRB_IMM_OFF
+
+/* 01 1110 0000 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1110 0001 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1110 0010 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1110 0011 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1110 0100 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1110 0101 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1110 0110 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1110 0111 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1110 1000 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1110 1001 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1110 1010 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1110 1011 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1110 1100 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1110 1101 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1110 1110 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1110 1111 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+
+/* 01 1111 0000 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1111 0001 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1111 0010 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1111 0011 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1111 0100 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1111 0101 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1111 0110 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1111 0111 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1111 1000 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1111 1001 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1111 1010 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1111 1011 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1111 1100 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1111 1101 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1111 1110 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+/* 01 1111 1111 */ TABDECL(OP_LDRB_IMM_OFF), // OP_LDRB_IMM_OFF
+
+/* 10 0000 0000 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0000 0001 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0000 0010 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0000 0011 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0000 0100 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0000 0101 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0000 0110 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0000 0111 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0000 1000 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0000 1001 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0000 1010 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0000 1011 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0000 1100 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0000 1101 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0000 1110 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0000 1111 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+
+/* 10 0001 0000 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0001 0001 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0001 0010 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0001 0011 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0001 0100 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0001 0101 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0001 0110 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0001 0111 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0001 1000 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0001 1001 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0001 1010 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0001 1011 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0001 1100 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0001 1101 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0001 1110 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+/* 10 0001 1111 */ TABDECL(OP_STRH_IMM_OFF), // OP_STRH_IMM_OFF
+
+/* 10 0010 0000 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0010 0001 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0010 0010 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0010 0011 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0010 0100 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0010 0101 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0010 0110 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0010 0111 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0010 1000 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0010 1001 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0010 1010 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0010 1011 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0010 1100 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0010 1101 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0010 1110 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0010 1111 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+
+/* 10 0011 0000 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0011 0001 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0011 0010 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0011 0011 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0011 0100 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0011 0101 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0011 0110 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0011 0111 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0011 1000 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0011 1001 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0011 1010 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0011 1011 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0011 1100 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0011 1101 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0011 1110 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+/* 10 0011 1111 */ TABDECL(OP_LDRH_IMM_OFF), // OP_LDRH_IMM_OFF
+
+/* 10 0100 0000 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0100 0001 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0100 0010 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0100 0011 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0100 0100 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0100 0101 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0100 0110 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0100 0111 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0100 1000 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0100 1001 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0100 1010 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0100 1011 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0100 1100 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0100 1101 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0100 1110 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0100 1111 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+
+/* 10 0101 0000 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0101 0001 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0101 0010 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0101 0011 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0101 0100 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0101 0101 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0101 0110 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0101 0111 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0101 1000 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0101 1001 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0101 1010 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0101 1011 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0101 1100 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0101 1101 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0101 1110 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+/* 10 0101 1111 */ TABDECL(OP_STR_SPREL), // OP_STR_SPREL
+
+/* 10 0110 0000 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0110 0001 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0110 0010 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0110 0011 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0110 0100 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0110 0101 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0110 0110 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0110 0111 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0110 1000 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0110 1001 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0110 1010 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0110 1011 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0110 1100 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0110 1101 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0110 1110 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0110 1111 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+
+/* 10 0111 0000 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0111 0001 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0111 0010 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0111 0011 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0111 0100 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0111 0101 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0111 0110 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0111 0111 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0111 1000 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0111 1001 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0111 1010 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0111 1011 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0111 1100 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0111 1101 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0111 1110 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+/* 10 0111 1111 */ TABDECL(OP_LDR_SPREL), // OP_LDR_SPREL
+
+/* 10 1000 0000 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1000 0001 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1000 0010 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1000 0011 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1000 0100 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1000 0101 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1000 0110 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1000 0111 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1000 1000 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1000 1001 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1000 1010 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1000 1011 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1000 1100 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1000 1101 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1000 1110 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1000 1111 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+
+/* 10 1001 0000 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1001 0001 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1001 0010 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1001 0011 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1001 0100 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1001 0101 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1001 0110 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1001 0111 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1001 1000 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1001 1001 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1001 1010 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1001 1011 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1001 1100 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1001 1101 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1001 1110 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+/* 10 1001 1111 */ TABDECL(OP_ADD_2PC), // OP_ADD_2PC
+
+/* 10 1010 0000 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1010 0001 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1010 0010 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1010 0011 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1010 0100 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1010 0101 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1010 0110 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1010 0111 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1010 1000 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1010 1001 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1010 1010 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1010 1011 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1010 1100 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1010 1101 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1010 1110 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1010 1111 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+
+/* 10 1011 0000 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1011 0001 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1011 0010 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1011 0011 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1011 0100 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1011 0101 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1011 0110 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1011 0111 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1011 1000 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1011 1001 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1011 1010 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1011 1011 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1011 1100 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1011 1101 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1011 1110 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+/* 10 1011 1111 */ TABDECL(OP_ADD_2SP), // OP_ADD_2SP
+
+/* 10 1100 0000 */ TABDECL(OP_ADJUST_P_SP), // OP_ADJUST_P_SP
+/* 10 1100 0001 */ TABDECL(OP_ADJUST_P_SP), // OP_ADJUST_P_SP
+/* 10 1100 0010 */ TABDECL(OP_ADJUST_M_SP), // OP_ADJUST_M_SP
+/* 10 1100 0011 */ TABDECL(OP_ADJUST_M_SP), // OP_ADJUST_M_SP
+/* 10 1100 0100 */ TABDECL(OP_UND_THUMB),
+/* 10 1100 0101 */ TABDECL(OP_UND_THUMB),
+/* 10 1100 0110 */ TABDECL(OP_UND_THUMB),
+/* 10 1100 0111 */ TABDECL(OP_UND_THUMB),
+/* 10 1100 1000 */ TABDECL(OP_UND_THUMB),
+/* 10 1100 1001 */ TABDECL(OP_UND_THUMB),
+/* 10 1100 1010 */ TABDECL(OP_UND_THUMB),
+/* 10 1100 1011 */ TABDECL(OP_UND_THUMB),
+/* 10 1100 1100 */ TABDECL(OP_UND_THUMB),
+/* 10 1100 1101 */ TABDECL(OP_UND_THUMB),
+/* 10 1100 1110 */ TABDECL(OP_UND_THUMB),
+/* 10 1100 1111 */ TABDECL(OP_UND_THUMB),
+
+/* 10 1101 0000 */ TABDECL(OP_PUSH), // OP_PUSH
+/* 10 1101 0001 */ TABDECL(OP_PUSH), // OP_PUSH
+/* 10 1101 0010 */ TABDECL(OP_PUSH), // OP_PUSH
+/* 10 1101 0011 */ TABDECL(OP_PUSH), // OP_PUSH
+/* 10 1101 0100 */ TABDECL(OP_PUSH_LR), // OP_PUSH_LR
+/* 10 1101 0101 */ TABDECL(OP_PUSH_LR), // OP_PUSH_LR
+/* 10 1101 0110 */ TABDECL(OP_PUSH_LR), // OP_PUSH_LR
+/* 10 1101 0111 */ TABDECL(OP_PUSH_LR), // OP_PUSH_LR
+/* 10 1101 1000 */ TABDECL(OP_UND_THUMB),
+/* 10 1101 1001 */ TABDECL(OP_UND_THUMB),
+/* 10 1101 1010 */ TABDECL(OP_UND_THUMB),
+/* 10 1101 1011 */ TABDECL(OP_UND_THUMB),
+/* 10 1101 1100 */ TABDECL(OP_UND_THUMB),
+/* 10 1101 1101 */ TABDECL(OP_UND_THUMB),
+/* 10 1101 1110 */ TABDECL(OP_UND_THUMB),
+/* 10 1101 1111 */ TABDECL(OP_UND_THUMB),
+
+/* 10 1110 0000 */ TABDECL(OP_UND_THUMB),
+/* 10 1110 0001 */ TABDECL(OP_UND_THUMB),
+/* 10 1110 0010 */ TABDECL(OP_UND_THUMB),
+/* 10 1110 0011 */ TABDECL(OP_UND_THUMB),
+/* 10 1110 0100 */ TABDECL(OP_UND_THUMB),
+/* 10 1110 0101 */ TABDECL(OP_UND_THUMB),
+/* 10 1110 0110 */ TABDECL(OP_UND_THUMB),
+/* 10 1110 0111 */ TABDECL(OP_UND_THUMB),
+/* 10 1110 1000 */ TABDECL(OP_UND_THUMB),
+/* 10 1110 1001 */ TABDECL(OP_UND_THUMB),
+/* 10 1110 1010 */ TABDECL(OP_UND_THUMB),
+/* 10 1110 1011 */ TABDECL(OP_UND_THUMB),
+/* 10 1110 1100 */ TABDECL(OP_UND_THUMB),
+/* 10 1110 1101 */ TABDECL(OP_UND_THUMB),
+/* 10 1110 1110 */ TABDECL(OP_UND_THUMB),
+/* 10 1110 1111 */ TABDECL(OP_UND_THUMB),
+
+/* 10 1111 0000 */ TABDECL(OP_POP), // OP_POP
+/* 10 1111 0001 */ TABDECL(OP_POP), // OP_POP
+/* 10 1111 0010 */ TABDECL(OP_POP), // OP_POP
+/* 10 1111 0011 */ TABDECL(OP_POP), // OP_POP
+/* 10 1111 0100 */ TABDECL(OP_POP_PC), // OP_POP_PC
+/* 10 1111 0101 */ TABDECL(OP_POP_PC), // OP_POP_PC
+/* 10 1111 0110 */ TABDECL(OP_POP_PC), // OP_POP_PC
+/* 10 1111 0111 */ TABDECL(OP_POP_PC), // OP_POP_PC
+/* 10 1111 1000 */ TABDECL(OP_BKPT_THUMB), // OP_BKPT_THUMB
+/* 10 1111 1001 */ TABDECL(OP_BKPT_THUMB), // OP_BKPT_THUMB
+/* 10 1111 1010 */ TABDECL(OP_BKPT_THUMB), // OP_BKPT_THUMB
+/* 10 1111 1011 */ TABDECL(OP_BKPT_THUMB), // OP_BKPT_THUMB
+/* 10 1111 1100 */ TABDECL(OP_UND_THUMB),
+/* 10 1111 1101 */ TABDECL(OP_UND_THUMB),
+/* 10 1111 1110 */ TABDECL(OP_UND_THUMB),
+/* 10 1111 1111 */ TABDECL(OP_UND_THUMB),
+
+/* 11 0000 0000 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0000 0001 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0000 0010 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0000 0011 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0000 0100 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0000 0101 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0000 0110 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0000 0111 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0000 1000 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0000 1001 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0000 1010 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0000 1011 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0000 1100 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0000 1101 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0000 1110 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0000 1111 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+
+/* 11 0001 0000 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0001 0001 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0001 0010 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0001 0011 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0001 0100 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0001 0101 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0001 0110 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0001 0111 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0001 1000 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0001 1001 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0001 1010 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0001 1011 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0001 1100 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0001 1101 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0001 1110 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+/* 11 0001 1111 */ TABDECL(OP_STMIA_THUMB), // OP_STMIA_THUMB
+
+/* 11 0010 0000 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0010 0001 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0010 0010 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0010 0011 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0010 0100 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0010 0101 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0010 0110 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0010 0111 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0010 1000 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0010 1001 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0010 1010 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0010 1011 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0010 1100 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0010 1101 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0010 1110 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0010 1111 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+
+/* 11 0011 0000 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0011 0001 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0011 0010 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0011 0011 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0011 0100 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0011 0101 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0011 0110 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0011 0111 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0011 1000 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0011 1001 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0011 1010 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0011 1011 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0011 1100 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0011 1101 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0011 1110 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+/* 11 0011 1111 */ TABDECL(OP_LDMIA_THUMB), // OP_LDMIA_THUMB
+
+/* 11 0100 0000 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0100 0001 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0100 0010 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0100 0011 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0100 0100 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0100 0101 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0100 0110 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0100 0111 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0100 1000 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0100 1001 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0100 1010 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0100 1011 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0100 1100 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0100 1101 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0100 1110 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0100 1111 */ TABDECL(OP_B_COND), // OP_B_COND
+
+/* 11 0101 0000 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0101 0001 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0101 0010 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0101 0011 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0101 0100 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0101 0101 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0101 0110 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0101 0111 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0101 1000 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0101 1001 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0101 1010 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0101 1011 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0101 1100 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0101 1101 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0101 1110 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0101 1111 */ TABDECL(OP_B_COND), // OP_B_COND
+
+/* 11 0110 0000 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0110 0001 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0110 0010 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0110 0011 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0110 0100 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0110 0101 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0110 0110 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0110 0111 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0110 1000 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0110 1001 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0110 1010 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0110 1011 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0110 1100 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0110 1101 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0110 1110 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0110 1111 */ TABDECL(OP_B_COND), // OP_B_COND
+
+/* 11 0111 0000 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0111 0001 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0111 0010 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0111 0011 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0111 0100 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0111 0101 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0111 0110 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0111 0111 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0111 1000 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0111 1001 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0111 1010 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0111 1011 */ TABDECL(OP_B_COND), // OP_B_COND
+/* 11 0111 1100 */ TABDECL(OP_SWI_THUMB), // OP_SWI_THUMB
+/* 11 0111 1101 */ TABDECL(OP_SWI_THUMB), // OP_SWI_THUMB
+/* 11 0111 1110 */ TABDECL(OP_SWI_THUMB), // OP_SWI_THUMB
+/* 11 0111 1111 */ TABDECL(OP_SWI_THUMB), // OP_SWI_THUMB
+
+/* 11 1000 0000 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1000 0001 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1000 0010 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1000 0011 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1000 0100 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1000 0101 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1000 0110 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1000 0111 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1000 1000 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1000 1001 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1000 1010 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1000 1011 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1000 1100 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1000 1101 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1000 1110 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1000 1111 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+
+/* 11 1001 0000 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1001 0001 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1001 0010 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1001 0011 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1001 0100 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1001 0101 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1001 0110 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1001 0111 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1001 1000 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1001 1001 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1001 1010 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1001 1011 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1001 1100 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1001 1101 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1001 1110 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+/* 11 1001 1111 */ TABDECL(OP_B_UNCOND), // OP_B_UNCOND
+
+/* 11 1010 0000 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1010 0001 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1010 0010 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1010 0011 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1010 0100 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1010 0101 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1010 0110 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1010 0111 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1010 1000 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1010 1001 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1010 1010 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1010 1011 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1010 1100 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1010 1101 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1010 1110 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1010 1111 */ TABDECL(OP_BLX), // OP_BLX
+
+/* 11 1011 0000 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1011 0001 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1011 0010 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1011 0011 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1011 0100 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1011 0101 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1011 0110 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1011 0111 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1011 1000 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1011 1001 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1011 1010 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1011 1011 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1011 1100 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1011 1101 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1011 1110 */ TABDECL(OP_BLX), // OP_BLX
+/* 11 1011 1111 */ TABDECL(OP_BLX), // OP_BLX
+
+/* 11 1100 0000 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1100 0001 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1100 0010 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1100 0011 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1100 0100 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1100 0101 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1100 0110 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1100 0111 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1100 1000 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1100 1001 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1100 1010 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1100 1011 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1100 1100 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1100 1101 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1100 1110 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1100 1111 */ TABDECL(OP_BL_10), // OP_BL_10
+
+/* 11 1101 0000 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1101 0001 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1101 0010 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1101 0011 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1101 0100 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1101 0101 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1101 0110 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1101 0111 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1101 1000 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1101 1001 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1101 1010 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1101 1011 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1101 1100 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1101 1101 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1101 1110 */ TABDECL(OP_BL_10), // OP_BL_10
+/* 11 1101 1111 */ TABDECL(OP_BL_10), // OP_BL_10
+
+/* 11 1110 0000 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1110 0001 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1110 0010 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1110 0011 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1110 0100 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1110 0101 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1110 0110 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1110 0111 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1110 1000 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1110 1001 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1110 1010 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1110 1011 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1110 1100 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1110 1101 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1110 1110 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1110 1111 */ TABDECL(OP_BL_11), // OP_BL_11
+
+/* 11 1111 0000 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1111 0001 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1111 0010 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1111 0011 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1111 0100 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1111 0101 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1111 0110 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1111 0111 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1111 1000 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1111 1001 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1111 1010 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1111 1011 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1111 1100 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1111 1101 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1111 1110 */ TABDECL(OP_BL_11), // OP_BL_11
+/* 11 1111 1111 */ TABDECL(OP_BL_11), // OP_BL_11
+
+
--- a/src/in_2sf/desmume/types.h
+++ b/src/in_2sf/desmume/types.h
@@ -1,6 +1,6 @@
/*
Copyright (C) 2005 Guillaume Duhamel
- Copyright (C) 2008-2011 DeSmuME team
+ Copyright (C) 2008-2012 DeSmuME team
This file is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -21,138 +21,77 @@
#include "pstdint.h"
-//analyze microsoft compilers
-#ifdef _MSC_VER
- //#define _WINDOWS
- #ifdef _M_X64
- //#define _WIN64 //already defined in x64 compiler
- #else
- //#define _WIN32 //already defined
- #endif
-#endif
-
-//todo - everyone will want to support this eventually, i suppose
#ifdef _WINDOWS
-//#include "config.h"
-#endif
-
-//enforce a constraint: gdb stub requires developer
-#if defined(GDB_STUB) && !defined(DEVELOPER)
-#define DEVELOPER
-#endif
-
-#ifdef DEVELOPER
-#define IF_DEVELOPER(X) X
-#else
-#define IF_DEVELOPER(X)
-#endif
-
-#ifdef _WINDOWS
- //#define HAVE_WX //not useful yet....
- #define HAVE_LIBAGG
- #define ENABLE_SSE
- #define ENABLE_SSE2
- #ifdef DEVELOPER
- #define HAVE_LUA
- #endif
+# define HAVE_LIBAGG
+# define ENABLE_SSE
+# define ENABLE_SSE2
+# define HAVE_JIT
#endif
#ifdef __GNUC__
-#ifdef __SSE__
-#define ENABLE_SSE
-#endif
-#ifdef __SSE2__
-#define ENABLE_SSE2
-#endif
+# ifdef __SSE__
+# define ENABLE_SSE
+# endif
+# ifdef __SSE2__
+# define ENABLE_SSE2
+# endif
#endif
#ifdef NOSSE
-#undef ENABLE_SSE
+# undef ENABLE_SSE
#endif
#ifdef NOSSE2
-#undef ENABLE_SSE2
+# undef ENABLE_SSE2
#endif
#ifdef _MSC_VER
-#define strcasecmp(x,y) _stricmp(x,y)
-#define strncasecmp(x, y, l) strnicmp(x, y, l)
-#define snprintf _snprintf
-#else
-//#define WINAPI
+# define strcasecmp(x, y) _stricmp(x, y)
+# define strncasecmp(x, y, l) strnicmp(x, y, l)
+# define snprintf _snprintf
#endif
#ifndef MAX_PATH
-#ifdef __GNUC__
-#include <climits>
-#ifndef PATH_MAX
-#define MAX_PATH 1024
-#else
-#define MAX_PATH PATH_MAX
-#endif
-#endif
+# ifdef __GNUC__
+# include <climits>
+# ifndef PATH_MAX
+# define MAX_PATH 1024
+# else
+# define MAX_PATH PATH_MAX
+# endif
+# endif
#endif
#if defined(_MSC_VER) || defined(__INTEL_COMPILER)
-#define DS_ALIGN(X) __declspec(align(X))
+# define DS_ALIGN(X) __declspec(align(X))
#elif defined(__GNUC__)
-#define DS_ALIGN(X) __attribute__ ((aligned (X)))
+# define DS_ALIGN(X) __attribute__ ((aligned (X)))
#else
-#define DS_ALIGN(X)
+# define DS_ALIGN(X)
#endif
#define CACHE_ALIGN DS_ALIGN(32)
-//use this for example when you want a byte value to be better-aligned
-#define FAST_ALIGN DS_ALIGN(4)
-
-#ifndef FASTCALL
#ifdef __MINGW32__
-#define FASTCALL __attribute__((fastcall))
+# define FASTCALL __attribute__((fastcall))
+# define ASMJIT_CALL_CONV kX86FuncConvGccFastCall
#elif defined (__i386__) && !defined(__clang__)
-#define FASTCALL __attribute__((regparm(3)))
+# define FASTCALL __attribute__((regparm(3)))
+# define ASMJIT_CALL_CONV kX86FuncConvGccRegParm3
#elif defined(_MSC_VER) || defined(__INTEL_COMPILER)
-#define FASTCALL
+# define FASTCALL
+# define ASMJIT_CALL_CONV kX86FuncConvDefault
#else
-#define FASTCALL
+# define FASTCALL
+# define ASMJIT_CALL_CONV kX86FuncConvDefault
#endif
-#endif
-
-/*---------- GPU3D fixed-points types -----------*/
-
-typedef int32_t f32;
-#define inttof32(n) ((n) << 12)
-#define f32toint(n) ((n) >> 12)
-#define floattof32(n) ((int32_t)((n) * (1 << 12)))
-#define f32tofloat(n) (((float)(n)) / (float)(1<<12))
-
-typedef int16_t t16;
-#define f32tot16(n) ((t16)(n >> 8))
-#define inttot16(n) ((n) << 4)
-#define t16toint(n) ((n) >> 4)
-#define floattot16(n) ((t16)((n) * (1 << 4)))
-#define t16ofloat(n) (((float)(n)) / (float)(1<<4))
-
-typedef int16_t v16;
-#define inttov16(n) ((n) << 12)
-#define f32tov16(n) (n)
-#define floattov16(n) ((v16)((n) * (1 << 12)))
-#define v16toint(n) ((n) >> 12)
-#define v16tofloat(n) (((float)(n)) / (float)(1<<12))
-
-typedef int16_t v10;
-#define inttov10(n) ((n) << 9)
-#define f32tov10(n) ((v10)(n >> 3))
-#define v10toint(n) ((n) >> 9)
-#define floattov10(n) ((v10)((n) * (1 << 9)))
-#define v10tofloat(n) (((float)(n)) / (float)(1<<9))
/*----------------------*/
#ifdef __BIG_ENDIAN__
-#ifndef WORDS_BIGENDIAN
-#define WORDS_BIGENDIAN
-#endif
+# ifndef WORDS_BIGENDIAN
+# define WORDS_BIGENDIAN
+# endif
#endif
#ifdef WORDS_BIGENDIAN
@@ -162,68 +101,26 @@
#endif
/* little endian (ds' endianess) to local endianess convert macros */
-#ifdef LOCAL_BE /* local arch is big endian */
-# define LE_TO_LOCAL_16(x) ((((x)&0xff)<<8)|(((x)>>8)&0xff))
-# define LE_TO_LOCAL_32(x) ((((x)&0xff)<<24)|(((x)&0xff00)<<8)|(((x)>>8)&0xff00)|(((x)>>24)&0xff))
-# define LE_TO_LOCAL_64(x) ((((x)&0xff)<<56)|(((x)&0xff00)<<40)|(((x)&0xff0000)<<24)|(((x)&0xff000000)<<8)|(((x)>>8)&0xff000000)|(((x)>>24)&0xff00)|(((x)>>40)&0xff00)|(((x)>>56)&0xff))
-# define LOCAL_TO_LE_16(x) ((((x)&0xff)<<8)|(((x)>>8)&0xff))
-# define LOCAL_TO_LE_32(x) ((((x)&0xff)<<24)|(((x)&0xff00)<<8)|(((x)>>8)&0xff00)|(((x)>>24)&0xff))
-# define LOCAL_TO_LE_64(x) ((((x)&0xff)<<56)|(((x)&0xff00)<<40)|(((x)&0xff0000)<<24)|(((x)&0xff000000)<<8)|(((x)>>8)&0xff000000)|(((x)>>24)&0xff00)|(((x)>>40)&0xff00)|(((x)>>56)&0xff))
-#else /* local arch is little endian */
-# define LE_TO_LOCAL_16(x) (x)
-# define LE_TO_LOCAL_32(x) (x)
-# define LE_TO_LOCAL_64(x) (x)
-# define LOCAL_TO_LE_16(x) (x)
-# define LOCAL_TO_LE_32(x) (x)
-# define LOCAL_TO_LE_64(x) (x)
+#ifdef LOCAL_BE /* local arch is big endian */
+inline uint16_t LE_TO_LOCAL_16(uint16_t x) { return ((x & 0xff) << 8) | ((x >> 8) & 0xff); }
+inline uint32_t LE_TO_LOCAL_32(uint32_t x) { return ((x & 0xff) << 24) | ((x & 0xff00) << 8) | ((x >> 8) & 0xff00) | ((x >> 24) & 0xff); }
+inline uint64_t LE_TO_LOCAL_64(uint64_t x)
+{
+ return ((x & 0xff) << 56) | ((x & 0xff00) << 40) | ((x & 0xff0000) << 24) | ((x & 0xff000000) << 8) |
+ ((x >> 8) & 0xff000000) | ((x >> 24) & 0xff00) | ((x >> 40) & 0xff00) | ((x >> 56) & 0xff);
+}
+#else /* local arch is little endian */
+inline uint16_t LE_TO_LOCAL_16(uint16_t x) { return x; }
+inline uint32_t LE_TO_LOCAL_32(uint32_t x) { return x; }
+inline uint64_t LE_TO_LOCAL_64(uint64_t x) { return x; }
#endif
-// kilobytes and megabytes macro
-#define MB(x) ((x)*1024*1024)
-#define KB(x) ((x)*1024)
+template<typename T, size_t N> inline size_t ARRAY_SIZE(T (&)[N]) { return N; }
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-
-#define CPU_STR(c) ((c==ARM9)?"ARM9":"ARM7")
-typedef enum
+inline double u64_to_double(uint64_t u)
{
- ARM9 = 0,
- ARM7 = 1
-} cpu_id_t;
-
-///endian-flips count bytes. count should be even and nonzero.
-inline void FlipByteOrder(uint8_t *src, uint32_t count)
-{
- uint8_t *start=src;
- uint8_t *end=src+count-1;
-
- if((count&1) || !count) return; /* This shouldn't happen. */
-
- while(count--)
+ union
{
- uint8_t tmp;
-
- tmp=*end;
- *end=*start;
- *start=tmp;
- end--;
- start++;
- }
-}
-
-
-
-inline uint64_t double_to_u64(double d) {
- union {
- uint64_t a;
- double b;
- } fuxor;
- fuxor.b = d;
- return fuxor.a;
-}
-
-inline double u64_to_double(uint64_t u) {
- union {
uint64_t a;
double b;
} fuxor;
@@ -231,174 +128,16 @@
return fuxor.b;
}
-/*inline uint32_t float_to_u32(float f) {
- union {
- uint32_t a;
- float b;
- } fuxor;
- fuxor.b = f;
- return fuxor.a;
-}*/
+// fairly standard for loop macros
+#define MACRODO1(TRICK, TODO) { int X = TRICK; TODO; }
+#define MACRODO2(X, TODO) { MACRODO1((X), TODO) MACRODO1(((X) + 1), TODO) }
+#define MACRODO4(X, TODO) { MACRODO2((X), TODO) MACRODO2(((X) + 2), TODO) }
-/*inline float u32_to_float(uint32_t u) {
- union {
- uint32_t a;
- float b;
- } fuxor;
- fuxor.a = u;
- return fuxor.b;
-}*/
-
-
-///stores a 32bit value into the provided byte array in guaranteed little endian form
-/*inline void en32lsb(uint8_t *buf, uint32_t morp)
+template<typename T> inline void reconstruct(T *t)
{
- buf[0]=(uint8_t)(morp);
- buf[1]=(uint8_t)(morp>>8);
- buf[2]=(uint8_t)(morp>>16);
- buf[3]=(uint8_t)(morp>>24);
-}*/
-
-/*inline void en16lsb(uint8_t* buf, uint16_t morp)
-{
- buf[0]=(uint8_t)morp;
- buf[1]=(uint8_t)(morp>>8);
-}*/
-
-///unpacks a 64bit little endian value from the provided byte array into host byte order
-/*inline uint64_t de64lsb(uint8_t *morp)
-{
- return morp[0]|(morp[1]<<8)|(morp[2]<<16)|(morp[3]<<24)|((uint64_t)morp[4]<<32)|((uint64_t)morp[5]<<40)|((uint64_t)morp[6]<<48)|((uint64_t)morp[7]<<56);
-}*/
-
-///unpacks a 32bit little endian value from the provided byte array into host byte order
-/*inline uint32_t de32lsb(uint8_t *morp)
-{
- return morp[0]|(morp[1]<<8)|(morp[2]<<16)|(morp[3]<<24);
-}*/
-
-///unpacks a 16bit little endian value from the provided byte array into host byte order
-/*inline uint16_t de16lsb(uint8_t *morp)
-{
- return morp[0]|(morp[1]<<8);
-}*/
-
-#ifndef ARRAY_SIZE
-//taken from winnt.h
-extern "C++" // templates cannot be declared to have 'C' linkage
-template <typename T, size_t N>
-char (*BLAHBLAHBLAH( UNALIGNED T (&)[N] ))[N];
-
-#define ARRAY_SIZE(A) (sizeof(*BLAHBLAHBLAH(A)))
-#endif
-
-
-//fairly standard for loop macros
-#define MACRODO1(TRICK,TODO) { const int X = TRICK; TODO; }
-#define MACRODO2(X,TODO) { MACRODO1((X),TODO) MACRODO1(((X)+1),TODO) }
-#define MACRODO4(X,TODO) { MACRODO2((X),TODO) MACRODO2(((X)+2),TODO) }
-#define MACRODO8(X,TODO) { MACRODO4((X),TODO) MACRODO4(((X)+4),TODO) }
-#define MACRODO16(X,TODO) { MACRODO8((X),TODO) MACRODO8(((X)+8),TODO) }
-#define MACRODO32(X,TODO) { MACRODO16((X),TODO) MACRODO16(((X)+16),TODO) }
-#define MACRODO64(X,TODO) { MACRODO32((X),TODO) MACRODO32(((X)+32),TODO) }
-#define MACRODO128(X,TODO) { MACRODO64((X),TODO) MACRODO64(((X)+64),TODO) }
-#define MACRODO256(X,TODO) { MACRODO128((X),TODO) MACRODO128(((X)+128),TODO) }
-
-//this one lets you loop any number of times (as long as N<256)
-#define MACRODO_N(N,TODO) {\
- if((N)&0x100) MACRODO256(0,TODO); \
- if((N)&0x080) MACRODO128((N)&(0x100),TODO); \
- if((N)&0x040) MACRODO64((N)&(0x100|0x080),TODO); \
- if((N)&0x020) MACRODO32((N)&(0x100|0x080|0x040),TODO); \
- if((N)&0x010) MACRODO16((N)&(0x100|0x080|0x040|0x020),TODO); \
- if((N)&0x008) MACRODO8((N)&(0x100|0x080|0x040|0x020|0x010),TODO); \
- if((N)&0x004) MACRODO4((N)&(0x100|0x080|0x040|0x020|0x010|0x008),TODO); \
- if((N)&0x002) MACRODO2((N)&(0x100|0x080|0x040|0x020|0x010|0x008|0x004),TODO); \
- if((N)&0x001) MACRODO1((N)&(0x100|0x080|0x040|0x020|0x010|0x008|0x004|0x002),TODO); \
-}
-
-//---------------------------
-//Binary constant generator macro By Tom Torfs - donated to the public domain
-
-//turn a numeric literal into a hex constant
-//(avoids problems with leading zeroes)
-//8-bit constants max value 0x11111111, always fits in unsigned long
-#define HEX__(n) 0x##n##LU
-
-//8-bit conversion function
-#define B8__(x) ((x&0x0000000FLU)?1:0) \
-+((x&0x000000F0LU)?2:0) \
-+((x&0x00000F00LU)?4:0) \
-+((x&0x0000F000LU)?8:0) \
-+((x&0x000F0000LU)?16:0) \
-+((x&0x00F00000LU)?32:0) \
-+((x&0x0F000000LU)?64:0) \
-+((x&0xF0000000LU)?128:0)
-
-//for upto 8-bit binary constants
-#define B8(d) ((unsigned char)B8__(HEX__(d)))
-
-// for upto 16-bit binary constants, MSB first
-#define B16(dmsb,dlsb) (((unsigned short)B8(dmsb)<<8) \
-+ B8(dlsb))
-
-// for upto 32-bit binary constants, MSB first */
-#define B32(dmsb,db2,db3,dlsb) (((unsigned long)B8(dmsb)<<24) \
-+ ((unsigned long)B8(db2)<<16) \
-+ ((unsigned long)B8(db3)<<8) \
-+ B8(dlsb))
-
-//Sample usage:
-//B8(01010101) = 85
-//B16(10101010,01010101) = 43605
-//B32(10000000,11111111,10101010,01010101) = 2164238933
-//---------------------------
-
-#ifndef CTASSERT
-#define CTASSERT(x) typedef char __assert ## y[(x) ? 1 : -1]
-#endif
-
-//static const char hexValid[23] = {"0123456789ABCDEFabcdef"};
-
-
-template<typename T> inline void reconstruct(T* t) {
t->~T();
new(t) T();
}
-//-------------fixed point speedup macros
-
-/*#if defined(_WIN32) && !defined(__MINGW32__)
-#define WIN32_LEAN_AND_MEAN
-#include <intrin.h>
-#endif*/
-
-/*inline int64_t fx32_mul(const int32_t a, const int32_t b)
-{
-#if defined(_WIN32) && !defined(__MINGW32__)
- return __emul(a,b);
-#else
- return ((int64_t)a)*((int64_t)b);
-#endif
-}*/
-
-/*inline int32_t fx32_shiftdown(const int64_t a)
-{
-#if defined(_WIN32) && !defined(__MINGW32__)
- return (int32_t)__ll_rshift(a,12);
-#else
- return (int32_t)(a>>12);
-#endif
-}*/
-
-/*inline int64_t fx32_shiftup(const int32_t a)
-{
-#if defined(_WIN32) && !defined(__MINGW32__)
- return __ll_lshift(a,12);
-#else
- return ((int64_t)a)<<12;
-#endif
-}*/
-
#endif
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/AsmJit.h
@@ -1,1 +1,343 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_ASMJIT_H
+#define _ASMJIT_ASMJIT_H
+
+//! @mainpage
+//!
+//! @brief AsmJit is a complete x86/x64 JIT Assembler for C++ language.
+//!
+//! It supports FPU, MMX, 3dNow, SSE, SSE2, SSE3 and SSE4 intrinsics, powerful
+//! compiler that helps to write portable functions for 32-bit (x86) and 64-bit
+//! (x64) architectures. AsmJit can be used to create functions at runtime that
+//! can be called from existing (but also generated) C/C++ code.
+//!
+//! AsmJit is a cross-platform library that supports various compilers and
+//! operating systems. Currently only limitation is x86 (32-bit) or x64 (64-bit)
+//! processor. Currently tested operating systems are Windows (32-bit and 64-bit),
+//! Linux (32-bit and 64-bit) and MacOSX (32-bit and 64-bit).
+//!
+//! @section AsmJit_Main_Introduction Introduction
+//!
+//! AsmJit library contains two main classes for code generation with different
+//! goals. First main code generation class is called @c AsmJit::Assembler and
+//! contains low level API that can be used to generate JIT binary code. It
+//! directly emits binary stream that represents encoded x86/x64 assembler
+//! opcodes. Together with operands and labels it can be used to generate
+//! complete code. For details look to @ref AsmJit_Core and @ref AsmJit_Compiler
+//! sections.
+//!
+//! There is also class named @c AsmJit::Compiler that allows to develop
+//! cross-platform assembler code without worring about function calling
+//! conventions and registers allocation. It can be also used to write 32-bit
+//! and 64-bit portable code. Compiler is recommended class to use for code
+//! generation.
+//!
+//! Everything in AsmJit library is in @c AsmJit namespace.
+//!
+//! @section AsmJit_Main_CodeGeneration Code Generation
+//!
+//! - @ref AsmJit_Core "Assembler core" - Operands, intrinsics and low-level assembler.
+//! - @ref AsmJit_Compiler "Compiler" - High level code generation.
+//! - @ref AsmJit_CpuInfo "Cpu Information" - Get information about host processor.
+//! - @ref AsmJit_Logging "Logging" - Logging and error handling.
+//! - @ref AsmJit_MemoryManagement "Memory Management" - Virtual memory management.
+//!
+//! @section AsmJit_Main_Configuration Configuration, Definitions and Utilities
+//!
+//! - @ref AsmJit_Config "Configuration" - Macros used to configure AsmJit.
+//!
+//! @section AsmJit_Main_HomePage AsmJit Homepage
+//!
+//! - http://code.google.com/p/asmjit/
+//!
+//! @section AsmJit_Main_ResourcesX86 External X86/X64 Assembler Resources
+//! - http://www.agner.org/optimize/
+//! - http://www.mark.masmcode.com/ (Assembler Tips)
+//! - http://avisynth.org/mediawiki/Filter_SDK/Assembler_optimizing (Optimizing)
+//! - http://www.ragestorm.net/distorm/ (Disassembling)
+//!
+//! @section AsmJit_Main_Terminology Terminology
+//!
+//! - <b>Non-volatile (preserved) register</b> - Register that can't be changed
+//! by callee (callee must save and restore it if it want to use it inside).
+//!
+//! - <b>Volatile (non-preserved) register</b> - The opossite. Register that can
+//! be freely used by callee. The caller must free all registers before calling
+//! other function.
+
+
+//! @defgroup AsmJit_Core Assembler core (operands, intrinsics and low-level assembler).
+//!
+//! Contains classes related to @c AsmJit::Assembler that're directly used
+//! to generate machine code stream. It's one of oldest and fastest method
+//! to generate machine code using AsmJit library.
+//!
+//! - See @c AsmJit::Assembler class for low level code generation
+//! documentation.
+//! - See @c AsmJit::Operand for AsmJit operand's overview.
+//!
+//! @section AsmJit_Core_Registers Registers
+//!
+//! There are static objects that represents X86 and X64 registers. They can
+//! be used directly (like @c eax, @c mm, @c xmm, ...) or created through
+//! these functions:
+//!
+//! - @c AsmJit::mk_gpb() - make general purpose byte register
+//! - @c AsmJit::mk_gpw() - make general purpose word register
+//! - @c AsmJit::mk_gpd() - make general purpose dword register
+//! - @c AsmJit::mk_gpq() - make general purpose qword register
+//! - @c AsmJit::mk_mm() - make mmx register
+//! - @c AsmJit::mk_xmm() - make sse register
+//! - @c AsmJit::st() - make x87 register
+//!
+//! @section AsmJit_Core_Addressing Addressing
+//!
+//! X86 and x64 architectures contains several addressing modes and most ones
+//! are possible with AsmJit library. Memory represents are represented by
+//! @c AsmJit::Mem class. These functions are used to make operands that
+//! represents memory addresses:
+//!
+//! - @c AsmJit::ptr()
+//! - @c AsmJit::byte_ptr()
+//! - @c AsmJit::word_ptr()
+//! - @c AsmJit::dword_ptr()
+//! - @c AsmJit::qword_ptr()
+//! - @c AsmJit::tword_ptr()
+//! - @c AsmJit::dqword_ptr()
+//! - @c AsmJit::mmword_ptr()
+//! - @c AsmJit::xmmword_ptr()
+//! - @c AsmJit::sysint_ptr()
+//!
+//! Most useful function to make pointer should be @c AsmJit::ptr(). It creates
+//! pointer to the target with unspecified size. Unspecified size works in all
+//! intrinsics where are used registers (this means that size is specified by
+//! register operand or by instruction itself). For example @c AsmJit::ptr()
+//! can't be used with @c AsmJit::Assembler::inc() instruction. In this case
+//! size must be specified and it's also reason to make difference between
+//! pointer sizes.
+//!
+//! Supported are simple address forms (register + displacement) and complex
+//! address forms (register + (register << shift) + displacement).
+//!
+//! @section AsmJit_Core_Immediates Immediates
+//!
+//! Immediate values are constants thats passed directly after instruction
+//! opcode. To create such value use @c AsmJit::imm() or @c AsmJit::uimm()
+//! methods to create signed or unsigned immediate value.
+//!
+//! @sa @c AsmJit::Compiler.
+
+
+//! @defgroup AsmJit_Compiler Compiler (high-level code generation).
+//!
+//! Contains classes related to @c AsmJit::Compiler that can be used
+//! to generate code using high-level constructs.
+//!
+//! - See @c Compiler class for high level code generation
+//! documentation - calling conventions, function declaration
+//! and variables management.
+
+//! @defgroup AsmJit_Config Configuration.
+//!
+//! Contains macros that can be redefined to fit into any project.
+
+
+//! @defgroup AsmJit_CpuInfo CPU information.
+//!
+//! X86 or x64 cpuid instruction allows to get information about processor
+//! vendor and it's features. It's always used to detect features like MMX,
+//! SSE and other newer ones.
+//!
+//! AsmJit library supports low level cpuid call implemented internally as
+//! C++ function using inline assembler or intrinsics and also higher level
+//! CPU features detection. The low level function (also used by higher level
+//! one) is @c AsmJit::cpuid().
+//!
+//! AsmJit library also contains higher level function @c AsmJit::getCpuInfo()
+//! that returns features detected by the library. The detection process is
+//! done only once and it's cached for all next calls. @c AsmJit::CpuInfo
+//! structure not contains only information through @c AsmJit::cpuid(), but
+//! there is also small multiplatform code to detect number of processors
+//! (or cores) through operating system API.
+//!
+//! It's recommended to use @c AsmJit::cpuInfo to detect and check for
+//! host processor features.
+//!
+//! Example how to use AsmJit::cpuid():
+//!
+//! @code
+//! // All functions and structures are in AsmJit namesapce.
+//! using namespace AsmJit;
+//!
+//! // Here will be retrieved result of cpuid call.
+//! CpuId out;
+//!
+//! // Use cpuid function to do the job.
+//! cpuid(0 /* eax */, &out /* eax, ebx, ecx, edx */);
+//!
+//! // Id eax argument to cpuid is 0, ebx, ecx and edx registers
+//! // are filled with cpu vendor.
+//! char vendor[13];
+//! memcpy(i->vendor, &out.ebx, 4);
+//! memcpy(i->vendor + 4, &out.edx, 4);
+//! memcpy(i->vendor + 8, &out.ecx, 4);
+//! vendor[12] = '\0';
+//!
+//! // Print vendor
+//! puts(vendor);
+//! @endcode
+//!
+//! If you want to use AsmJit::cpuid() function instead of higher level
+//! @c AsmJit::getCpuInfo(), please read processor manuals provided by Intel,
+//! AMD or other manufacturers for cpuid instruction details.
+//!
+//! Example of using @c AsmJit::getCpuInfo():
+//!
+//! @code
+//! // All functions and structures are in AsmJit namesapce.
+//! using namespace AsmJit;
+//!
+//! // Call to cpuInfo return CpuInfo structure that shouldn't be modified.
+//! // Make it const by default.
+//! const CpuInfo *i = getCpuInfo();
+//!
+//! // Now you are able to get specific features.
+//!
+//! // Processor has SSE2
+//! if (i->features & kX86FeatureSse2)
+//! {
+//! // your code...
+//! }
+//! // Processor has MMX
+//! else if (i->features & kX86Feature_MMX)
+//! {
+//! // your code...
+//! }
+//! // Processor is old, no SSE2 or MMX support.
+//! else
+//! {
+//! // your code...
+//! }
+//! @endcode
+//!
+//! Better example is in AsmJit/Test/testcpu.cpp file.
+//!
+//! @sa AsmJit::cpuid, @c AsmJit::cpuInfo.
+
+
+//! @defgroup AsmJit_Logging Logging and error handling.
+//!
+//! Contains classes related to loging assembler output. Currently logging
+//! is implemented in @c AsmJit::Logger class.You can override
+//! @c AsmJit::Logger::log() to log messages into your stream. There is also
+//! @c FILE based logger implemented in @c AsmJit::FileLogger class.
+//!
+//! To log your assembler output to FILE stream use this code:
+//!
+//! @code
+//! // Create assembler
+//! Assembler a;
+//!
+//! // Create and set file based logger
+//! FileLogger logger(stderr);
+//! a.setLogger(&logger);
+//! @endcode
+//!
+//! You can see that logging goes through @c Assembler. If you are using
+//! @c Compiler and you want to log messages in correct assembler order,
+//! you should look at @ref Compiler::comment() method. It allows you to
+//! insert text message into items stream so the @c Compiler is able to
+//! send messages to @ref Assembler in correct order.
+//!
+//! @sa @c AsmJit::Logger, @c AsmJit::FileLogger.
+
+
+//! @defgroup AsmJit_MemoryManagement Virtual memory management.
+//!
+//! Using @c AsmJit::Assembler or @c AsmJit::Compiler to generate machine
+//! code is not final step. Each generated code needs to run in memory
+//! that is not protected against code execution. To alloc this code it's
+//! needed to use operating system functions provided to enable execution
+//! code in specified memory block or to allocate memory that is not
+//! protected. The solution is always to use @c See AsmJit::Assembler::make()
+//! and @c AsmJit::Compiler::make() functions that can allocate memory and
+//! relocate code for you. But AsmJit also contains classes for manual memory
+//! management thats internally used by AsmJit but can be used by programmers
+//! too.
+//!
+//! Memory management contains low level and high level classes related to
+//! allocating and freeing virtual memory. Low level class is
+//! @c AsmJit::VirtualMemory that can allocate and free full pages of
+//! virtual memory provided by operating system. Higher level class is
+//! @c AsmJit::MemoryManager that is able to manage complete allocation and
+//! free mechanism. It internally uses larger chunks of memory to make
+//! allocation fast and effective.
+//!
+//! Using @c AsmJit::VirtualMemory::alloc() is cross-platform way how to
+//! allocate this kind of memory without worrying about operating system
+//! and it's API. Each memory block that is no longer needed should be
+//! freed by @c AsmJit::VirtualMemory::free() method. If you want better
+//! comfort and malloc()/free() interface, look at the
+//! @c AsmJit::MemoryManager class.
+//!
+//! @sa @c AsmJit::VirtualMemory, @ AsmJit::MemoryManager.
+
+
+//! @addtogroup AsmJit_Config
+//! @{
+
+//! @def ASMJIT_WINDOWS
+//! @brief Macro that is declared if AsmJit is compiled for Windows.
+
+//! @def ASMJIT_POSIX
+//! @brief Macro that is declared if AsmJit is compiled for unix like
+//! operating system.
+
+//! @def ASMJIT_API
+//! @brief Attribute that's added to classes that can be exported if AsmJit
+//! is compiled as a dll library.
+
+//! @def ASMJIT_MALLOC
+//! @brief Function to call to allocate dynamic memory.
+
+//! @def ASMJIT_REALLOC
+//! @brief Function to call to reallocate dynamic memory.
+
+//! @def ASMJIT_FREE
+//! @brief Function to call to free dynamic memory.
+
+//! @def ASMJIT_ASSERT
+//! @brief Assertion macro. Default implementation calls
+//! @c AsmJit::assertionFailure() function.
+
+//! @}
+
+
+//! @namespace AsmJit
+//! @brief Main AsmJit library namespace.
+//!
+//! There are not other namespaces used in AsmJit library.
+
+// ----------------------------------------------------------------------------
+// [Dependencies - Core]
+// ----------------------------------------------------------------------------
+
+#include "core.h"
+
+// ----------------------------------------------------------------------------
+// [Dependencies - X86 / X64]
+// ----------------------------------------------------------------------------
+
+#if defined(ASMJIT_X86) || defined(ASMJIT_X64)
+#include "x86.h"
+#endif // ASMJIT_X86 || ASMJIT_X64
+
+// [Guard]
+#endif // _ASMJIT_ASMJIT_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/COPYING.txt
@@ -1,1 +1,18 @@
+Copyright (c) 2008-2012, Petr Kobalicek <kobalicek.petr@gmail.com>
+This software is provided 'as-is', without any express or implied
+warranty. In no event will the authors be held liable for any damages
+arising from the use of this software.
+
+Permission is granted to anyone to use this software for any purpose,
+including commercial applications, and to alter it and redistribute it
+freely, subject to the following restrictions:
+
+1. The origin of this software must not be misrepresented; you must not
+ claim that you wrote the original software. If you use this software
+ in a product, an acknowledgment in the product documentation would be
+ appreciated but is not required.
+2. Altered source versions must be plainly marked as such, and must not be
+ misrepresented as being the original software.
+3. This notice may not be removed or altered from any source distribution.
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/Config.h
@@ -1,1 +1,66 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+// [Guard]
+#ifndef _ASMJIT_CONFIG_H
+#define _ASMJIT_CONFIG_H
+
+// This file is designed to be modifyable. Platform specific changes should
+// be applied to this file so it's guaranteed that never versions of AsmJit
+// library will never overwrite generated config files.
+//
+// So modify this file by your build system or by hand.
+
+// ============================================================================
+// [AsmJit - OS]
+// ============================================================================
+
+// Provides definitions about your operating system. It's detected by default,
+// so override it if you have problems with automatic detection.
+//
+// #define ASMJIT_WINDOWS
+// #define ASMJIT_POSIX
+
+// ============================================================================
+// [AsmJit - Architecture]
+// ============================================================================
+
+// Provides definitions about your cpu architecture. It's detected by default,
+// so override it if you have problems with automatic detection.
+
+// #define ASMJIT_X86
+// #define ASMJIT_X64
+
+// ============================================================================
+// [AsmJit - API]
+// ============================================================================
+
+// If you are embedding AsmJit library into your project (statically), undef
+// ASMJIT_API macro.
+#define ASMJIT_API
+
+// ============================================================================
+// [AsmJit - Memory Management]
+// ============================================================================
+
+// #define ASMJIT_MALLOC ::malloc
+// #define ASMJIT_REALLOC ::realloc
+// #define ASMJIT_FREE ::free
+
+// ============================================================================
+// [AsmJit - Debug]
+// ============================================================================
+
+// Turn debug on/off (to bypass autodetection)
+// #define ASMJIT_DEBUG
+// #define ASMJIT_NO_DEBUG
+
+// Setup custom assertion code.
+// #define ASMJIT_ASSERT(exp) do { if (!(exp)) ::AsmJit::assertionFailure(__FILE__, __LINE__, #exp); } while(0)
+
+// [Guard]
+#endif // _ASMJIT_CONFIG_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core.h
@@ -1,1 +1,38 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+// [Guard]
+#ifndef _ASMJIT_CORE_H
+#define _ASMJIT_CORE_H
+
+// [Dependencies - AsmJit]
+#include "core/build.h"
+
+#include "core/assembler.h"
+#include "core/assert.h"
+#include "core/buffer.h"
+#include "core/compiler.h"
+#include "core/compilercontext.h"
+#include "core/compilerfunc.h"
+#include "core/compileritem.h"
+#include "core/cpuinfo.h"
+#include "core/defs.h"
+#include "core/func.h"
+#include "core/intutil.h"
+#include "core/lock.h"
+#include "core/logger.h"
+#include "core/memorymanager.h"
+#include "core/memorymarker.h"
+#include "core/operand.h"
+#include "core/podvector.h"
+#include "core/stringbuilder.h"
+#include "core/stringutil.h"
+#include "core/virtualmemory.h"
+#include "core/zonememory.h"
+
+// [Guard]
+#endif // _ASMJIT_CORE_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/apibegin.h
@@ -1,1 +1,34 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+// [MSVC]
+#ifdef _MSC_VER
+
+// Disable some warnings we know about
+#pragma warning(push)
+#pragma warning(disable: 4127) // conditional expression is constant
+#pragma warning(disable: 4251) // struct needs to have dll-interface to be used
+ // by clients of struct ...
+#pragma warning(disable: 4275) // non dll-interface struct ... used as base for
+ // dll-interface struct
+#pragma warning(disable: 4355) // this used in base member initializer list
+#pragma warning(disable: 4800) // forcing value to bool 'true' or 'false'
+
+// Rename symbols.
+#define vsnprintf _vsnprintf
+#define snprintf _snprintf
+
+#endif // _MSC_VER
+
+// [GNUC]
+#ifdef __GNUC__
+// GCC warnings fix: I can't understand why GCC has no interface to push/pop
+// specific warnings.
+// # if (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__) >= 402001
+// # pragma GCC diagnostic ignored "-w"
+// # endif
+#endif // __GNUC__
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/apiend.h
@@ -1,1 +1,22 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+// [MSVC]
+#ifdef _MSC_VER
+
+// Pop disabled warnings by ApiBegin.h
+#pragma warning(pop)
+
+// Rename symbols back.
+#undef vsnprintf
+#undef snprintf
+
+#endif // _MSC_VER
+
+// [GNUC]
+#ifdef __GNUC__
+#endif // __GNUC__
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/assembler.cpp
@@ -1,1 +1,203 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/assembler.h"
+#include "../core/memorymanager.h"
+#include "../core/intutil.h"
+
+// [Dependenceis - C]
+#include <stdarg.h>
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [AsmJit::Assembler - Construction / Destruction]
+// ============================================================================
+
+Assembler::Assembler(Context *context) : _zoneMemory(16384 - sizeof(ZoneChunk) - 32), _buffer(), _context(context ? context : static_cast<Context *>(JitContext::getGlobal())), _logger(nullptr), _error(kErrorOk),
+ _properties(0), _emitOptions(0), _trampolineSize(0), _inlineComment(nullptr), _unusedLinks(nullptr)
+{
+}
+
+Assembler::~Assembler()
+{
+}
+
+// ============================================================================
+// [AsmJit::Assembler - Logging]
+// ============================================================================
+
+void Assembler::setLogger(Logger *logger)
+{
+ this->_logger = logger;
+}
+
+// ============================================================================
+// [AsmJit::Assembler - Error Handling]
+// ============================================================================
+
+void Assembler::setError(uint32_t error)
+{
+ this->_error = error;
+ if (this->_error == kErrorOk)
+ return;
+
+ if (this->_logger)
+ this->_logger->logFormat("*** ASSEMBLER ERROR: %s (%u).\n", getErrorString(error), static_cast<unsigned>(error));
+}
+
+// ============================================================================
+// [AsmJit::Assembler - Properties]
+// ============================================================================
+
+uint32_t Assembler::getProperty(uint32_t propertyId) const
+{
+ if (propertyId > 31)
+ return 0;
+
+ return !!(this->_properties & IntUtil::maskFromIndex(propertyId));
+}
+
+void Assembler::setProperty(uint32_t propertyId, uint32_t value)
+{
+ if (propertyId > 31)
+ return;
+
+ if (value)
+ this->_properties |= IntUtil::maskFromIndex(propertyId);
+ else
+ this->_properties &= ~IntUtil::maskFromIndex(propertyId);
+}
+
+// ============================================================================
+// [AsmJit::Assembler - TakeCode]
+// ============================================================================
+
+uint8_t *Assembler::takeCode()
+{
+ uint8_t *code = this->_buffer.take();
+ this->_relocData.clear();
+ this->_zoneMemory.clear();
+
+ if (this->_error != kErrorOk)
+ this->setError(kErrorOk);
+
+ return code;
+}
+
+// ============================================================================
+// [AsmJit::Assembler - Clear / Reset]
+// ============================================================================
+
+void Assembler::clear()
+{
+ this->_purge();
+
+ if (this->_error != kErrorOk)
+ this->setError(kErrorOk);
+}
+
+void Assembler::reset()
+{
+ this->_purge();
+
+ this->_zoneMemory.reset();
+ this->_buffer.reset();
+
+ this->_labels.reset();
+ this->_relocData.reset();
+
+ if (this->_error != kErrorOk)
+ this->setError(kErrorOk);
+}
+
+void Assembler::_purge()
+{
+ this->_zoneMemory.clear();
+ this->_buffer.clear();
+
+ this->_emitOptions = 0;
+ this->_trampolineSize = 0;
+
+ this->_inlineComment = nullptr;
+ this->_unusedLinks = nullptr;
+
+ this->_labels.clear();
+ this->_relocData.clear();
+}
+
+// ============================================================================
+// [AsmJit::Assembler - Emit]
+// ============================================================================
+
+void Assembler::embed(const void *data, size_t len)
+{
+ if (!this->canEmit())
+ return;
+
+ if (this->_logger)
+ {
+ char buf[128];
+ const char dot[] = ".data ";
+
+ memcpy(buf, dot, ASMJIT_ARRAY_SIZE(dot) - 1);
+
+ for (size_t i = 0; i < len; i += 16)
+ {
+ size_t max = len - i < 16 ? len - i : 16;
+ char *p = buf + ASMJIT_ARRAY_SIZE(dot) - 1;
+
+ for (size_t j = 0; j < max; ++j)
+ p += sprintf(p, "%02X", reinterpret_cast<const uint8_t *>(data)[i + j]);
+
+ *p++ = '\n';
+ *p = '\0';
+
+ this->_logger->logString(buf);
+ }
+ }
+
+ this->_buffer.emitData(data, len);
+}
+
+// ============================================================================
+// [AsmJit::Assembler - Helpers]
+// ============================================================================
+
+auto Assembler::_newLabelLink() -> LabelLink *
+{
+ LabelLink *link = this->_unusedLinks;
+
+ if (link)
+ this->_unusedLinks = link->prev;
+ else
+ {
+ link = static_cast<LabelLink *>(this->_zoneMemory.alloc(sizeof(LabelLink)));
+ if (!link)
+ return nullptr;
+ }
+
+ // clean link
+ link->prev = nullptr;
+ link->offset = 0;
+ link->displacement = 0;
+ link->relocId = -1;
+
+ return link;
+}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/assembler.h
@@ -1,1 +1,463 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_CORE_ASSEMBLER_H
+#define _ASMJIT_CORE_ASSEMBLER_H
+
+// [Dependencies - AsmJit]
+#include "../core/buffer.h"
+#include "../core/context.h"
+#include "../core/defs.h"
+#include "../core/logger.h"
+#include "../core/podvector.h"
+#include "../core/zonememory.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+//! @addtogroup AsmJit_Core
+//! @{
+
+// ============================================================================
+// [AsmJit::Assembler]
+// ============================================================================
+
+//! @brief Base class for @ref Assembler.
+//!
+//! This class implements core setialization API only. The platform specific
+//! methods and intrinsics is implemented by derived classes.
+//!
+//! @sa @c Assembler.
+struct Assembler
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Creates Assembler instance.
+ ASMJIT_API Assembler(Context *context);
+ //! @brief Destroys Assembler instance
+ ASMJIT_API virtual ~Assembler();
+
+ // --------------------------------------------------------------------------
+ // [LabelLink]
+ // --------------------------------------------------------------------------
+
+ //! @brief Data structure used to link linked-labels.
+ struct LabelLink
+ {
+ //! @brief Previous link.
+ LabelLink *prev;
+ //! @brief Offset.
+ sysint_t offset;
+ //! @brief Inlined displacement.
+ sysint_t displacement;
+ //! @brief RelocId if link must be absolute when relocated.
+ sysint_t relocId;
+ };
+
+ // --------------------------------------------------------------------------
+ // [LabelData]
+ // --------------------------------------------------------------------------
+
+ //! @brief Label data.
+ struct LabelData
+ {
+ //! @brief Label offset.
+ sysint_t offset;
+ //! @brief Label links chain.
+ LabelLink *links;
+ };
+
+ // --------------------------------------------------------------------------
+ // [RelocData]
+ // --------------------------------------------------------------------------
+
+ // X86 architecture uses 32-bit absolute addressing model by memory operands,
+ // but 64-bit mode uses relative addressing model (RIP + displacement). In
+ // code we are always using relative addressing model for referencing labels
+ // and embedded data. In 32-bit mode we must patch all references to absolute
+ // address before we can call generated function. We are patching only memory
+ // operands.
+
+ //! @brief Code relocation data (relative vs absolute addresses).
+ struct RelocData
+ {
+ //! @brief Type of relocation.
+ uint32_t type;
+ //! @brief Size of relocation (4 or 8 bytes).
+ uint32_t size;
+ //! @brief Offset from code begin address.
+ sysint_t offset;
+
+ //! @brief Relative displacement or absolute address.
+ union
+ {
+ //! @brief Relative displacement from code begin address (not to @c offset).
+ sysint_t destination;
+ //! @brief Absolute address where to jump;
+ void *address;
+ };
+ };
+
+ // --------------------------------------------------------------------------
+ // [Context]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get code generator.
+ Context *getContext() const { return this->_context; }
+
+ // --------------------------------------------------------------------------
+ // [Memory Management]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get zone memory manager.
+ ZoneMemory *getZoneMemory() const { return const_cast<ZoneMemory *>(&this->_zoneMemory); }
+
+ // --------------------------------------------------------------------------
+ // [Logging]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get logger.
+ Logger *getLogger() const { return this->_logger; }
+
+ //! @brief Set logger to @a logger.
+ ASMJIT_API virtual void setLogger(Logger *logger);
+
+ // --------------------------------------------------------------------------
+ // [Error Handling]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get error code.
+ uint32_t getError() const { return this->_error; }
+
+ //! @brief Set error code.
+ //!
+ //! This method is virtual, because higher classes can use it to catch all
+ //! errors.
+ ASMJIT_API virtual void setError(uint32_t error);
+
+ // --------------------------------------------------------------------------
+ // [Properties]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get assembler property.
+ ASMJIT_API virtual uint32_t getProperty(uint32_t propertyId) const;
+
+ //! @brief Set assembler property.
+ ASMJIT_API virtual void setProperty(uint32_t propertyId, uint32_t value);
+
+ // --------------------------------------------------------------------------
+ // [Capacity]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get capacity of internal code buffer.
+ size_t getCapacity() const { return this->_buffer.getCapacity(); }
+
+ // --------------------------------------------------------------------------
+ // [Offset]
+ // --------------------------------------------------------------------------
+
+ //! @brief Return current offset in buffer.
+ size_t getOffset() const { return this->_buffer.getOffset(); }
+
+ //! @brief Set offset to @a o and returns previous offset.
+ //!
+ //! This method can be used to truncate code (previous offset is not
+ //! recorded) or to overwrite instruction stream at position @a o.
+ //!
+ //! @return Previous offset value that can be uset to set offset back later.
+ size_t toOffset(size_t o) { return this->_buffer.toOffset(o); }
+
+ // --------------------------------------------------------------------------
+ // [GetCode / GetCodeSize]
+ // --------------------------------------------------------------------------
+
+ //! @brief Return start of assembler code buffer.
+ //!
+ //! Note that buffer address can change if you emit instruction or something
+ //! else. Use this pointer only when you finished or make sure you do not
+ //! use returned pointer after emitting.
+ uint8_t *getCode() const { return this->_buffer.getData(); }
+
+ //! @brief Return current offset in buffer (same as <code>getOffset() + getTramplineSize()</code>).
+ size_t getCodeSize() const { return this->_buffer.getOffset() + this->getTrampolineSize(); }
+
+ // --------------------------------------------------------------------------
+ // [TakeCode]
+ // --------------------------------------------------------------------------
+
+ //! @brief Take internal code buffer and NULL all pointers (you take the ownership).
+ ASMJIT_API uint8_t *takeCode();
+
+ // --------------------------------------------------------------------------
+ // [Clear / Reset]
+ // --------------------------------------------------------------------------
+
+ //! @brief Clear everything, but not deallocate buffers.
+ ASMJIT_API void clear();
+
+ //! @brief Reset everything (means also to free all buffers).
+ ASMJIT_API void reset();
+
+ //! @brief Called by clear() and reset() to clear all data related to derived
+ //! class implementation.
+ ASMJIT_API virtual void _purge();
+
+ // --------------------------------------------------------------------------
+ // [EnsureSpace]
+ // --------------------------------------------------------------------------
+
+ //! @brief Ensure space for next instruction.
+ //!
+ //! Note that this method can return false. It's rare and probably you never
+ //! get this, but in some situations it's still possible.
+ bool ensureSpace() { return this->_buffer.ensureSpace(); }
+
+ // --------------------------------------------------------------------------
+ // [GetTrampolineSize]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get size of all possible trampolines needed to successfuly generate
+ //! relative jumps to absolute addresses. This value is only non-zero if jmp
+ //! of call instructions were used with immediate operand (this means jump or
+ //! call absolute address directly).
+ //!
+ //! Currently only _emitJmpOrCallReloc() method can increase trampoline size
+ //! value.
+ size_t getTrampolineSize() const { return this->_trampolineSize; }
+
+ // --------------------------------------------------------------------------
+ // [Buffer - Getters]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get byte at position @a pos.
+ uint8_t getByteAt(size_t pos) const { return this->_buffer.getByteAt(pos); }
+
+ //! @brief Get word at position @a pos.
+ uint16_t getWordAt(size_t pos) const { return this->_buffer.getWordAt(pos); }
+
+ //! @brief Get dword at position @a pos.
+ uint32_t getDWordAt(size_t pos) const { return this->_buffer.getDWordAt(pos); }
+
+ //! @brief Get qword at position @a pos.
+ uint64_t getQWordAt(size_t pos) const { return this->_buffer.getQWordAt(pos); }
+
+ //! @brief Get int32_t at position @a pos.
+ int32_t getInt32At(size_t pos) const { return static_cast<int32_t>(this->_buffer.getDWordAt(pos)); }
+
+ //! @brief Get int64_t at position @a pos.
+ int64_t getInt64At(size_t pos) const { return static_cast<int64_t>(this->_buffer.getQWordAt(pos)); }
+
+ //! @brief Get intptr_t at position @a pos.
+ intptr_t getIntPtrTAt(size_t pos) const { return this->_buffer.getIntPtrTAt(pos); }
+
+ //! @brief Get uintptr_t at position @a pos.
+ uintptr_t getUIntPtrTAt(size_t pos) const { return this->_buffer.getUIntPtrTAt(pos); }
+
+ //! @brief Get uintptr_t at position @a pos.
+ size_t getSizeTAt(size_t pos) const { return this->_buffer.getSizeTAt(pos); }
+
+ // --------------------------------------------------------------------------
+ // [Buffer - Setters]
+ // --------------------------------------------------------------------------
+
+ //! @brief Set byte at position @a pos.
+ void setByteAt(size_t pos, uint8_t x) { this->_buffer.setByteAt(pos, x); }
+
+ //! @brief Set word at position @a pos.
+ void setWordAt(size_t pos, uint16_t x) { this->_buffer.setWordAt(pos, x); }
+
+ //! @brief Set dword at position @a pos.
+ void setDWordAt(size_t pos, uint32_t x) { this->_buffer.setDWordAt(pos, x); }
+
+ //! @brief Set qword at position @a pos.
+ void setQWordAt(size_t pos, uint64_t x) { this->_buffer.setQWordAt(pos, x); }
+
+ //! @brief Set int32_t at position @a pos.
+ void setInt32At(size_t pos, int32_t x) { this->_buffer.setDWordAt(pos, static_cast<uint32_t>(x)); }
+
+ //! @brief Set int64_t at position @a pos.
+ void setInt64At(size_t pos, int64_t x) { this->_buffer.setQWordAt(pos, static_cast<uint64_t>(x)); }
+
+ //! @brief Set intptr_t at position @a pos.
+ void setIntPtrTAt(size_t pos, intptr_t x) { this->_buffer.setIntPtrTAt(pos, x); }
+
+ //! @brief Set uintptr_t at position @a pos.
+ void setUInt64At(size_t pos, uintptr_t x) { this->_buffer.setUIntPtrTAt(pos, x); }
+
+ //! @brief Set size_t at position @a pos.
+ void setSizeTAt(size_t pos, size_t x) { this->_buffer.setSizeTAt(pos, x); }
+
+ // --------------------------------------------------------------------------
+ // [CanEmit]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get whether the instruction can be emitted.
+ //!
+ //! This function behaves like @c ensureSpace(), but it also checks if
+ //! assembler is in error state and in that case it returns @c false.
+ //! Assembler internally always uses this function before new instruction is
+ //! emitted.
+ //!
+ //! It's implemented like:
+ //! <code>return ensureSpace() && !getError();</code>
+ bool canEmit()
+ {
+ // If there is an error, we can't emit another instruction until last error
+ // is cleared by calling @c setError(kErrorOk). If something caused the
+ // error while generating code it's probably fatal in all cases. You can't
+ // use generated code anymore, because you are not sure about the status.
+ if (this->_error)
+ return false;
+
+ // The ensureSpace() method returns true on success and false on failure. We
+ // are catching return value and setting error code here.
+ if (this->ensureSpace())
+ return true;
+
+ // If we are here, there is memory allocation error. Note that this is HEAP
+ // allocation error, virtual allocation error can be caused only by
+ // AsmJit::VirtualMemory class!
+ this->setError(kErrorNoHeapMemory);
+ return false;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Emit]
+ //
+ // These functions are not protected against buffer overrun. Each place of
+ // code which calls these functions ensures that there is some space using
+ // canEmit() method. Emitters are internally protected in AsmJit::Buffer,
+ // but only in debug builds.
+ // --------------------------------------------------------------------------
+
+ //! @brief Emit Byte to internal buffer.
+ void _emitByte(uint8_t x) { this->_buffer.emitByte(x); }
+
+ //! @brief Emit word (2 bytes) to internal buffer.
+ void _emitWord(uint16_t x) { this->_buffer.emitWord(x); }
+
+ //! @brief Emit dword (4 bytes) to internal buffer.
+ void _emitDWord(uint32_t x) { this->_buffer.emitDWord(x); }
+
+ //! @brief Emit qword (8 bytes) to internal buffer.
+ void _emitQWord(uint64_t x) { this->_buffer.emitQWord(x); }
+
+ //! @brief Emit Int32 (4 bytes) to internal buffer.
+ void _emitInt32(int32_t x) { this->_buffer.emitDWord(static_cast<uint32_t>(x)); }
+
+ //! @brief Emit Int64 (8 bytes) to internal buffer.
+ void _emitInt64(int64_t x) { this->_buffer.emitQWord(static_cast<uint64_t>(x)); }
+
+ //! @brief Emit intptr_t (4 or 8 bytes) to internal buffer.
+ void _emitIntPtrT(intptr_t x) { this->_buffer.emitIntPtrT(x); }
+
+ //! @brief Emit uintptr_t (4 or 8 bytes) to internal buffer.
+ void _emitUIntPtrT(uintptr_t x) { this->_buffer.emitUIntPtrT(x); }
+
+ //! @brief Emit size_t (4 or 8 bytes) to internal buffer.
+ void _emitSizeT(size_t x) { this->_buffer.emitSizeT(x); }
+
+ //! @brief Embed data into instruction stream.
+ ASMJIT_API void embed(const void *data, size_t len);
+
+ // --------------------------------------------------------------------------
+ // [Reloc]
+ // --------------------------------------------------------------------------
+
+ //! @brief Relocate code to a given address @a dst.
+ //!
+ //! @param dst Where the relocated code should me stored. The pointer can be
+ //! address returned by virtual memory allocator or your own address if you
+ //! want only to store the code for later reuse (or load, etc...).
+ //! @param addressBase Base address used for relocation. When using JIT code
+ //! generation, this will be the same as @a dst, only casted to system
+ //! integer type. But when generating code for remote process then the value
+ //! can be different.
+ //!
+ //! @retval The bytes used. Code-generator can create trampolines which are
+ //! used when calling other functions inside the JIT code. However, these
+ //! trampolines can be unused so the relocCode() returns the exact size needed
+ //! for the function.
+ //!
+ //! A given buffer will be overwritten, to get number of bytes required use
+ //! @c getCodeSize().
+ virtual size_t relocCode(void *dst, sysuint_t addressBase) const = 0;
+
+ //! @brief Simplifed version of @c relocCode() method designed for JIT.
+ //!
+ //! @overload
+ size_t relocCode(void *dst) const { return this->relocCode(dst, reinterpret_cast<uintptr_t>(dst)); }
+
+ // --------------------------------------------------------------------------
+ // [Make]
+ // --------------------------------------------------------------------------
+
+ //! @brief Make is convenience method to make currently serialized code and
+ //! return pointer to generated function.
+ //!
+ //! What you need is only to cast this pointer to your function type and call
+ //! it. Note that if there was an error and calling @c getError() method not
+ //! returns @c kErrorOk (zero) then this function always return @c NULL and
+ //! error value remains the same.
+ virtual void *make() = 0;
+
+ // --------------------------------------------------------------------------
+ // [Helpers]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API LabelLink *_newLabelLink();
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief ZoneMemory management.
+ ZoneMemory _zoneMemory;
+ //! @brief Binary code buffer.
+ Buffer _buffer;
+
+ //! @brief Context (for example @ref JitContext).
+ Context *_context;
+ //! @brief Logger.
+ Logger *_logger;
+
+ //! @brief Error code.
+ uint32_t _error;
+ //! @brief Properties.
+ uint32_t _properties;
+ //! @brief Emit flags for next instruction (cleared after emit).
+ uint32_t _emitOptions;
+ //! @brief Size of possible trampolines.
+ uint32_t _trampolineSize;
+
+ //! @brief Inline comment that will be logged by the next instruction and
+ //! set to NULL.
+ const char *_inlineComment;
+ //! @brief Linked list of unused links (@c LabelLink* structures)
+ LabelLink *_unusedLinks;
+
+ //! @brief Labels data.
+ PodVector<LabelData> _labels;
+ //! @brief Relocations data.
+ PodVector<RelocData> _relocData;
+};
+
+//! @}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_CORE_ASSEMBLER_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/assert.cpp
@@ -1,1 +1,34 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/assert.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+// helpers
+namespace AsmJit
+{
+
+// ============================================================================
+// [AsmJit::Assert]
+// ============================================================================
+
+void assertionFailure(const char *file, int line, const char *exp)
+{
+ fprintf(stderr, "*** ASSERTION FAILURE at %s (line %d)\n" "*** %s\n", file, line, exp);
+
+ exit(1);
+}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/assert.h
@@ -1,1 +1,69 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+// [Guard]
+#ifndef _ASMJIT_CORE_ASSERT_H
+#define _ASMJIT_CORE_ASSERT_H
+
+// [Dependencies - AsmJit]
+#include "../core/build.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+//! @addtogroup AsmJit_Core
+//! @{
+
+// ============================================================================
+// [AsmJit::Assert]
+// ============================================================================
+
+//! @brief Called in debug build on assertion failure.
+//! @param file Source file name where it happened.
+//! @param line Line in the source file.
+//! @param exp Expression what failed.
+//!
+//! If you have problems with assertions simply put a breakpoint into
+//! AsmJit::assertionFailure() method (AsmJit/Core/Assert.cpp file) and examine
+//! call stack.
+ASMJIT_API void assertionFailure(const char *file, int line, const char *exp);
+
+// ============================================================================
+// [ASMJIT_ASSERT]
+// ============================================================================
+
+#ifdef ASMJIT_DEBUG
+
+#ifndef ASMJIT_ASSERT
+#define ASMJIT_ASSERT(exp) \
+ do \
+ { \
+ if (!(exp)) \
+ ::AsmJit::assertionFailure(__FILE__, __LINE__, #exp); \
+ } while (0)
+#endif
+
+#else
+
+#ifndef ASMJIT_ASSERT
+#define ASMJIT_ASSERT(exp) ASMJIT_NOP()
+#endif
+
+#endif // DEBUG
+
+//! @}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_CORE_ASSERT_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/buffer.cpp
@@ -1,1 +1,102 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/buffer.h"
+#include "../core/defs.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [AsmJit::Buffer]
+// ============================================================================
+
+void Buffer::emitData(const void *ptr, size_t len)
+{
+ size_t max = this->getCapacity() - this->getOffset();
+
+ if (max < len && !this->realloc(this->getOffset() + len))
+ return;
+
+ memcpy(this->_cur, ptr, len);
+ this->_cur += len;
+}
+
+bool Buffer::realloc(size_t to)
+{
+ if (this->getCapacity() < to)
+ {
+ size_t len = this->getOffset();
+ uint8_t *newdata;
+
+ if (this->_data)
+ newdata = static_cast<uint8_t *>(ASMJIT_REALLOC(this->_data, to));
+ else
+ newdata = static_cast<uint8_t *>(ASMJIT_MALLOC(to));
+
+ if (!newdata)
+ return false;
+
+ this->_data = newdata;
+ this->_cur = newdata + len;
+ this->_max = newdata + to;
+ this->_max -= to >= kBufferGrow ? kBufferGrow : to;
+
+ this->_capacity = to;
+ }
+
+ return true;
+}
+
+bool Buffer::grow()
+{
+ size_t to = this->_capacity;
+
+ if (to < 512)
+ to = 1024;
+ else if (to > 65536)
+ to += 65536;
+ else
+ to <<= 1;
+
+ return this->realloc(to);
+}
+
+void Buffer::reset()
+{
+ if (!this->_data)
+ return;
+ ASMJIT_FREE(this->_data);
+
+ this->_data = nullptr;
+ this->_cur = nullptr;
+ this->_max = nullptr;
+ this->_capacity = 0;
+}
+
+uint8_t *Buffer::take()
+{
+ uint8_t *data = this->_data;
+
+ this->_data = nullptr;
+ this->_cur = nullptr;
+ this->_max = nullptr;
+ this->_capacity = 0;
+
+ return data;
+}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/buffer.h
@@ -1,1 +1,339 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_CORE_BUFFER_H
+#define _ASMJIT_CORE_BUFFER_H
+
+// [Dependencies - AsmJit]
+#include "../core/assert.h"
+#include "../core/build.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+//! @addtogroup AsmJit_Core
+//! @{
+
+// ============================================================================
+// [AsmJit::Buffer]
+// ============================================================================
+
+//! @brief Buffer used to store instruction stream in AsmJit.
+//!
+//! This class can be dangerous, if you don't know how it works. Assembler
+//! instruction stream is usually constructed by multiple calls of emit
+//! functions that emits bytes, words, dwords or qwords. But to decrease
+//! AsmJit library size and improve performance, we are not checking for
+//! buffer overflow for each emit operation, but only once in highler level
+//! emit instruction.
+//!
+//! So, if you want to use this class, you need to do buffer checking yourself
+//! by using @c ensureSpace() method. It's designed to grow buffer if needed.
+//! Threshold for growing is named @c growThreshold() and it means count of
+//! bytes for emitting single operation. Default size is set to 16 bytes,
+//! because x86 and x64 instruction can't be larger (so it's space to hold 1
+//! instruction).
+//!
+//! Example using Buffer:
+//!
+//! @code
+//! // Buffer instance, growThreshold == 16
+//! // (no memory allocated in constructor).
+//! AsmJit::Buffer buf(16);
+//!
+//! // Begin of emit stream, ensure space can fail on out of memory error.
+//! if (buf.ensureSpace())
+//! {
+//! // here, you can emit up to 16 (growThreshold) bytes
+//! buf.emitByte(0x00);
+//! buf.emitByte(0x01);
+//! buf.emitByte(0x02);
+//! buf.emitByte(0x03);
+//! ...
+//! }
+//! @endcode
+struct Buffer
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ Buffer() : _data(nullptr), _cur(nullptr), _max(nullptr), _capacity(0) { }
+
+ ~Buffer()
+ {
+ if (this->_data)
+ ASMJIT_FREE(this->_data);
+ }
+
+ //! @brief Get start of buffer.
+ uint8_t *getData() const { return this->_data; }
+
+ //! @brief Get current pointer in code buffer.
+ uint8_t *getCur() const { return this->_cur; }
+
+ //! @brief Get maximum pointer in code buffer for growing.
+ uint8_t *getMax() const { return this->_max; }
+
+ //! @brief Get current offset in buffer.
+ size_t getOffset() const { return static_cast<size_t>(this->_cur - this->_data); }
+
+ //! @brief Get capacity of buffer.
+ size_t getCapacity() const { return this->_capacity; }
+
+ //! @brief Ensure space for next instruction
+ bool ensureSpace() { return this->_cur >= this->_max ? this->grow() : true; }
+
+ //! @brief Sets offset to @a o and returns previous offset.
+ //!
+ //! This method can be used to truncate buffer or it's used to
+ //! overwrite specific position in buffer by Assembler.
+ size_t toOffset(size_t offset)
+ {
+ ASMJIT_ASSERT(offset < this->_capacity);
+
+ size_t prev = static_cast<size_t>(this->_cur - this->_data);
+ this->_cur = this->_data + offset;
+ return prev;
+ }
+
+ //! @brief Reallocate buffer.
+ //!
+ //! It's only used for growing, buffer is never reallocated to smaller
+ //! number than current capacity() is.
+ ASMJIT_API bool realloc(size_t to);
+
+ //! @brief Used to grow the buffer.
+ //!
+ //! It will typically realloc to twice size of capacity(), but if capacity()
+ //! is large, it will use smaller steps.
+ ASMJIT_API bool grow();
+
+ //! @brief Clear everything, but not deallocate buffer.
+ void clear() { this->_cur = this->_data; }
+
+ //! @brief Free buffer and NULL all pointers.
+ ASMJIT_API void reset();
+
+ //! @brief Take ownership of the buffer data and purge @c Buffer instance.
+ ASMJIT_API uint8_t *take();
+
+ // --------------------------------------------------------------------------
+ // [Emit]
+ // --------------------------------------------------------------------------
+
+ //! @brief Emit Byte.
+ void emitByte(uint8_t x)
+ {
+ ASMJIT_ASSERT(this->getOffset() + 1 <= this->_capacity);
+
+ *this->_cur++ = x;
+ }
+
+ //! @brief Emit Word (2 bytes).
+ void emitWord(uint16_t x)
+ {
+ ASMJIT_ASSERT(this->getOffset() + 2 <= this->_capacity);
+
+ *reinterpret_cast<uint16_t *>(this->_cur) = x;
+ this->_cur += 2;
+ }
+
+ //! @brief Emit DWord (4 bytes).
+ void emitDWord(uint32_t x)
+ {
+ ASMJIT_ASSERT(this->getOffset() + 4 <= this->_capacity);
+
+ *reinterpret_cast<uint32_t *>(this->_cur) = x;
+ this->_cur += 4;
+ }
+
+ //! @brief Emit QWord (8 bytes).
+ void emitQWord(uint64_t x)
+ {
+ ASMJIT_ASSERT(this->getOffset() + 8 <= this->_capacity);
+
+ *reinterpret_cast<uint64_t *>(this->_cur) = x;
+ this->_cur += 8;
+ }
+
+ //! @brief Emit intptr_t (4 or 8 bytes).
+ void emitIntPtrT(intptr_t x)
+ {
+ ASMJIT_ASSERT(this->getOffset() + sizeof(intptr_t) <= this->_capacity);
+
+ *reinterpret_cast<intptr_t *>(this->_cur) = x;
+ this->_cur += sizeof(intptr_t);
+ }
+
+ //! @brief Emit uintptr_t (4 or 8 bytes).
+ void emitUIntPtrT(uintptr_t x)
+ {
+ ASMJIT_ASSERT(this->getOffset() + sizeof(uintptr_t) <= this->_capacity);
+
+ *reinterpret_cast<uintptr_t *>(this->_cur) = x;
+ this->_cur += sizeof(uintptr_t);
+ }
+
+ //! @brief Emit size_t (4 or 8 bytes).
+ void emitSizeT(size_t x)
+ {
+ ASMJIT_ASSERT(this->getOffset() + sizeof(size_t) <= this->_capacity);
+
+ *reinterpret_cast<size_t *>(this->_cur) = x;
+ this->_cur += sizeof(size_t);
+ }
+
+ //! @brief Emit custom data.
+ ASMJIT_API void emitData(const void *ptr, size_t len);
+
+ // --------------------------------------------------------------------------
+ // [Get / Set]
+ // --------------------------------------------------------------------------
+
+ //! @brief Set byte at position @a pos.
+ uint8_t getByteAt(size_t pos) const
+ {
+ ASMJIT_ASSERT(pos + 1 <= this->_capacity);
+
+ return *(this->_data + pos);
+ }
+
+ //! @brief Set word at position @a pos.
+ uint16_t getWordAt(size_t pos) const
+ {
+ ASMJIT_ASSERT(pos + 2 <= this->_capacity);
+
+ return *reinterpret_cast<const uint16_t *>(this->_data + pos);
+ }
+
+ //! @brief Set dword at position @a pos.
+ uint32_t getDWordAt(size_t pos) const
+ {
+ ASMJIT_ASSERT(pos + 4 <= this->_capacity);
+
+ return *reinterpret_cast<const uint32_t *>(this->_data + pos);
+ }
+
+ //! @brief Set qword at position @a pos.
+ uint64_t getQWordAt(size_t pos) const
+ {
+ ASMJIT_ASSERT(pos + 8 <= this->_capacity);
+
+ return *reinterpret_cast<const uint64_t *>(this->_data + pos);
+ }
+
+ //! @brief Set intptr_t at position @a pos.
+ intptr_t getIntPtrTAt(size_t pos) const
+ {
+ ASMJIT_ASSERT(pos + sizeof(intptr_t) <= this->_capacity);
+
+ return *reinterpret_cast<const intptr_t *>(this->_data + pos);
+ }
+
+ //! @brief Set uintptr_t at position @a pos.
+ uintptr_t getUIntPtrTAt(size_t pos) const
+ {
+ ASMJIT_ASSERT(pos + sizeof(uintptr_t) <= this->_capacity);
+
+ return *reinterpret_cast<const uintptr_t *>(this->_data + pos);
+ }
+
+ //! @brief Set size_t at position @a pos.
+ uintptr_t getSizeTAt(size_t pos) const
+ {
+ ASMJIT_ASSERT(pos + sizeof(size_t) <= this->_capacity);
+
+ return *reinterpret_cast<const size_t *>(this->_data + pos);
+ }
+
+ //! @brief Set byte at position @a pos.
+ void setByteAt(size_t pos, uint8_t x)
+ {
+ ASMJIT_ASSERT(pos + 1 <= this->_capacity);
+
+ *(this->_data + pos) = x;
+ }
+
+ //! @brief Set word at position @a pos.
+ void setWordAt(size_t pos, uint16_t x)
+ {
+ ASMJIT_ASSERT(pos + 2 <= this->_capacity);
+
+ *reinterpret_cast<uint16_t *>(this->_data + pos) = x;
+ }
+
+ //! @brief Set dword at position @a pos.
+ void setDWordAt(size_t pos, uint32_t x)
+ {
+ ASMJIT_ASSERT(pos + 4 <= this->_capacity);
+
+ *reinterpret_cast<uint32_t *>(this->_data + pos) = x;
+ }
+
+ //! @brief Set qword at position @a pos.
+ void setQWordAt(size_t pos, uint64_t x)
+ {
+ ASMJIT_ASSERT(pos + 8 <= this->_capacity);
+
+ *reinterpret_cast<uint64_t *>(this->_data + pos) = x;
+ }
+
+ //! @brief Set intptr_t at position @a pos.
+ void setIntPtrTAt(size_t pos, intptr_t x)
+ {
+ ASMJIT_ASSERT(pos + sizeof(intptr_t) <= this->_capacity);
+
+ *reinterpret_cast<intptr_t *>(this->_data + pos) = x;
+ }
+
+ //! @brief Set uintptr_t at position @a pos.
+ void setUIntPtrTAt(size_t pos, uintptr_t x)
+ {
+ ASMJIT_ASSERT(pos + sizeof(uintptr_t) <= this->_capacity);
+
+ *reinterpret_cast<uintptr_t *>(this->_data + pos) = x;
+ }
+
+ //! @brief Set size_t at position @a pos.
+ void setSizeTAt(size_t pos, size_t x)
+ {
+ ASMJIT_ASSERT(pos + sizeof(size_t) <= this->_capacity);
+
+ *reinterpret_cast<size_t *>(this->_data + pos) = x;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ // All members are public, because they can be accessed and modified by
+ // Assembler/Compiler directly.
+
+ //! @brief Beginning position of buffer.
+ uint8_t *_data;
+ //! @brief Current position in buffer.
+ uint8_t *_cur;
+ //! @brief Maximum position in buffer for realloc.
+ uint8_t *_max;
+
+ //! @brief Buffer capacity (in bytes).
+ size_t _capacity;
+};
+
+//! @}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+#endif // _ASMJIT_CORE_BUFFER_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/build.h
@@ -1,1 +1,232 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_CORE_BUILD_H
+#define _ASMJIT_CORE_BUILD_H
+
+// [Include]
+#include "../Config.h"
+
+#ifdef ASMJIT_EXPORTS
+# if defined(_MSC_VER) && !defined(_CRT_SECURE_NO_WARNINGS)
+# define _CRT_SECURE_NO_WARNINGS
+# endif // _MSC_VER
+#endif // ASMJIT_EXPORTS
+
+// Here should be optional include files that's needed fo successfuly
+// use macros defined here. Remember, AsmJit uses only AsmJit namespace
+// and all macros are used within it.
+#include <cstdio>
+#include <cstdlib>
+#include <cstring>
+
+#include <new>
+
+// ============================================================================
+// [AsmJit - OS]
+// ============================================================================
+
+#if defined(WINDOWS) || defined(_WINDOWS) || defined(__WINDOWS__) || defined(_WIN32) || defined(_WIN64)
+# define ASMJIT_WINDOWS
+#elif defined(__linux__) || defined(__unix__) || defined(__OpenBSD__) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__BSD__) || defined(__FREEBSD__) || defined(__APPLE__)
+# define ASMJIT_POSIX
+#else
+# warning "AsmJit - Can't match operating system, using ASMJIT_POSIX"
+# define ASMJIT_POSIX
+#endif
+
+// ============================================================================
+// [AsmJit - Architecture]
+// ============================================================================
+
+// define it only if it's not defined. In some systems we can
+// use -D command in compiler to bypass this autodetection.
+#if !defined(ASMJIT_X86) && !defined(ASMJIT_X64)
+# if defined(__x86_64__) || defined(__LP64) || defined(__IA64__) || defined(_M_X64) || defined(_WIN64)
+# define ASMJIT_X64 // x86-64
+# else
+// _M_IX86, __INTEL__, __i386__
+# define ASMJIT_X86
+# endif
+#endif
+
+// ============================================================================
+// [AsmJit - API]
+// ============================================================================
+
+// Make AsmJit as shared library by default.
+#ifndef ASMJIT_API
+# ifdef ASMJIT_WINDOWS
+# ifdef __GNUC__
+# ifdef ASMJIT_EXPORTS
+# define ASMJIT_API __attribute__((dllexport))
+# else
+# define ASMJIT_API __attribute__((dllimport))
+# endif // ASMJIT_EXPORTS
+# else
+# ifdef ASMJIT_EXPORTS
+# define ASMJIT_API __declspec(dllexport)
+# else
+# define ASMJIT_API __declspec(dllimport)
+# endif // ASMJIT_EXPORTS
+# endif // __GNUC__
+# else
+# ifdef (__GNUC__
+# if __GNUC__ >= 4
+# define ASMJIT_API __attribute__((visibility("default")))
+# define ASMJIT_VAR extern ASMJIT_API
+# endif // __GNUC__ >= 4
+# endif // __GNUC__
+# endif
+#endif // ASMJIT_API
+
+#ifndef ASMJIT_VAR
+# ifdef ASMJIT_API
+# define ASMJIT_VAR extern ASMJIT_API
+# else
+# define ASMJIT_VAR
+# endif // ASMJIT_API
+#endif // !ASMJIT_VAR
+
+// [AsmJit - Memory Management]
+#ifndef ASMJIT_MALLOC
+# define ASMJIT_MALLOC ::malloc
+#endif // ASMJIT_MALLOC
+
+#ifndef ASMJIT_REALLOC
+# define ASMJIT_REALLOC ::realloc
+#endif // ASMJIT_REALLOC
+
+#ifndef ASMJIT_FREE
+# define ASMJIT_FREE ::free
+#endif // ASMJIT_FREE
+
+// ============================================================================
+// [AsmJit - Calling Conventions]
+// ============================================================================
+
+#ifdef ASMJIT_X86
+# ifdef __GNUC__
+# define ASMJIT_REGPARM_1 __attribute__((regparm(1)))
+# define ASMJIT_REGPARM_2 __attribute__((regparm(2)))
+# define ASMJIT_REGPARM_3 __attribute__((regparm(3)))
+# define ASMJIT_FASTCALL __attribute__((fastcall))
+# define ASMJIT_STDCALL __attribute__((stdcall))
+# define ASMJIT_CDECL __attribute__((cdecl))
+# else
+# define ASMJIT_FASTCALL __fastcall
+# define ASMJIT_STDCALL __stdcall
+# define ASMJIT_CDECL __cdecl
+# endif
+#else
+# define ASMJIT_FASTCALL
+# define ASMJIT_STDCALL
+# define ASMJIT_CDECL
+#endif // ASMJIT_X86
+
+#ifndef ASMJIT_UNUSED
+# define ASMJIT_UNUSED(var) ((void)var)
+#endif // ASMJIT_UNUSED
+
+#ifndef ASMJIT_NOP
+# define ASMJIT_NOP() ((void)0)
+#endif // ASMJIT_NOP
+
+// [AsmJit - C++ Compiler Support]
+#define ASMJIT_TYPE_TO_TYPE(_Type_) _Type_
+#define ASMJIT_HAS_STANDARD_DEFINE_OPTIONS
+#define ASMJIT_HAS_PARTIAL_TEMPLATE_SPECIALIZATION
+
+// Support for VC6
+#if defined(_MSC_VER) && _MSC_VER < 1400
+
+namespace AsmJit
+{
+ template<typename T> struct _Type2Type
+ {
+ typedef T Type;
+ };
+}
+
+#undef ASMJIT_TYPE_TO_TYPE
+#define ASMJIT_TYPE_TO_TYPE(_Type_) ::AsmJit::_Type2Type<_Type_>::Type
+
+#undef ASMJIT_HAS_STANDARD_DEFINE_OPTIONS
+#undef ASMJIT_HAS_PARTIAL_TEMPLATE_SPECIALIZATION
+
+#endif
+
+// ============================================================================
+// [AsmJit - Types]
+// ============================================================================
+
+#include "pstdint.h"
+
+#ifdef ASMJIT_X86
+typedef int32_t sysint_t;
+typedef uint32_t sysuint_t;
+#else
+typedef int64_t sysint_t;
+typedef uint64_t sysuint_t;
+#endif
+
+#ifdef _MSC_VER
+# define ASMJIT_INT64_C(num) num##i64
+# define ASMJIT_UINT64_C(num) num##ui64
+#else
+# define ASMJIT_INT64_C(num) num##LL
+# define ASMJIT_UINT64_C(num) num##ULL
+#endif
+
+// ============================================================================
+// [AsmJit - C++ Macros]
+// ============================================================================
+
+template<typename T, size_t N> inline size_t ASMJIT_ARRAY_SIZE(T (&)[N]) { return N; }
+
+#define ASMJIT_NO_COPY(__type__) \
+private: \
+ __type__(const __type__ &other); \
+ __type__& operator=(const __type__ &other); \
+public:
+
+// ============================================================================
+// [AsmJit - Debug]
+// ============================================================================
+
+// If ASMJIT_DEBUG and ASMJIT_NO_DEBUG is not defined then ASMJIT_DEBUG will be
+// detected using the compiler specific macros. This enables to set the build
+// type using IDE.
+#if !defined(ASMJIT_DEBUG) && !defined(ASMJIT_NO_DEBUG)
+# ifdef _DEBUG
+# define ASMJIT_DEBUG
+# endif // _DEBUG
+#endif // !ASMJIT_DEBUG && !ASMJIT_NO_DEBUG
+
+// ============================================================================
+// [AsmJit - Initialize/DontInitialize]
+// ============================================================================
+
+// TODO: This should be moved to AsmJit namespace!
+
+// Skip documenting this.
+#ifndef ASMJIT_NODOC
+struct _Initialize {};
+struct _DontInitialize {};
+#endif // !ASMJIT_NODOC
+
+// ============================================================================
+// [AsmJit - OS Support]
+// ============================================================================
+
+#ifdef ASMJIT_WINDOWS
+# include "windowsh_wrapper.h"
+#endif // ASMJIT_WINDOWS
+
+// [Guard]
+#endif // _ASMJIT_CORE_BUILD_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/compiler.cpp
@@ -1,1 +1,269 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/assembler.h"
+#include "../core/compiler.h"
+#include "../core/compilercontext.h"
+#include "../core/compilerfunc.h"
+#include "../core/compileritem.h"
+#include "../core/cpuinfo.h"
+#include "../core/intutil.h"
+#include "../core/logger.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [AsmJit::Compiler - Construction / Destruction]
+// ============================================================================
+
+Compiler::Compiler(Context *context) : _zoneMemory(16384 - sizeof(ZoneChunk) - 32), _linkMemory(1024 - 32), _context(context ? context : static_cast<Context *>(JitContext::getGlobal())), _logger(nullptr), _error(0),
+ _properties(0), _emitOptions(0), _finished(false), _first(nullptr), _last(nullptr), _current(nullptr), _cc(nullptr), _varNameId(0)
+{
+}
+
+Compiler::~Compiler()
+{
+ this->reset();
+}
+
+// ============================================================================
+// [AsmJit::Compiler - Logging]
+// ============================================================================
+
+void Compiler::setLogger(Logger *logger)
+{
+ this->_logger = logger;
+}
+
+// ============================================================================
+// [AsmJit::Compiler - Error Handling]
+// ============================================================================
+
+void Compiler::setError(uint32_t error)
+{
+ this->_error = error;
+ if (this->_error == kErrorOk)
+ return;
+
+ if (this->_logger)
+ this->_logger->logFormat("*** COMPILER ERROR: %s (%u).\n", getErrorString(error), static_cast<unsigned>(error));
+}
+
+// ============================================================================
+// [AsmJit::Compiler - Properties]
+// ============================================================================
+
+uint32_t Compiler::getProperty(uint32_t propertyId)
+{
+ if (propertyId > 31)
+ return 0;
+
+ return !!(this->_properties & IntUtil::maskFromIndex(propertyId));
+}
+
+void Compiler::setProperty(uint32_t propertyId, uint32_t value)
+{
+ if (propertyId > 31)
+ return;
+
+ if (value)
+ this->_properties |= IntUtil::maskFromIndex(propertyId);
+ else
+ this->_properties &= ~IntUtil::maskFromIndex(propertyId);
+}
+
+// ============================================================================
+// [AsmJit::Compiler - Clear / Reset]
+// ============================================================================
+
+void Compiler::clear()
+{
+ this->_purge();
+
+ if (this->_error != kErrorOk)
+ this->setError(kErrorOk);
+}
+
+void Compiler::reset()
+{
+ this->_purge();
+
+ this->_zoneMemory.reset();
+ this->_linkMemory.reset();
+
+ this->_targets.reset();
+ this->_vars.reset();
+
+ if (this->_error != kErrorOk)
+ this->setError(kErrorOk);
+}
+
+void Compiler::_purge()
+{
+ this->_zoneMemory.clear();
+ this->_linkMemory.clear();
+
+ this->_emitOptions = 0;
+ this->_finished = false;
+
+ this->_first = nullptr;
+ this->_last = nullptr;
+ this->_current = nullptr;
+ this->_func = nullptr;
+
+ this->_targets.clear();
+ this->_vars.clear();
+
+ this->_cc = nullptr;
+ this->_varNameId = 0;
+}
+
+// ============================================================================
+// [AsmJit::Compiler - Item Management]
+// ============================================================================
+
+CompilerItem *Compiler::setCurrentItem(CompilerItem *item)
+{
+ CompilerItem *old = this->_current;
+ this->_current = item;
+ return old;
+}
+
+void Compiler::addItem(CompilerItem *item)
+{
+ ASMJIT_ASSERT(item);
+ ASMJIT_ASSERT(!item->_prev);
+ ASMJIT_ASSERT(!item->_next);
+
+ if (!this->_current)
+ {
+ if (!this->_first)
+ {
+ this->_first = item;
+ this->_last = item;
+ }
+ else
+ {
+ item->_next = this->_first;
+ this->_first->_prev = item;
+ this->_first = item;
+ }
+ }
+ else
+ {
+ CompilerItem *prev = this->_current;
+ CompilerItem *next = this->_current->_next;
+
+ item->_prev = prev;
+ item->_next = next;
+
+ prev->_next = item;
+ if (next)
+ next->_prev = item;
+ else
+ this->_last = item;
+ }
+
+ this->_current = item;
+}
+
+void Compiler::addItemAfter(CompilerItem *item, CompilerItem *ref)
+{
+ ASMJIT_ASSERT(item);
+ ASMJIT_ASSERT(!item->_prev);
+ ASMJIT_ASSERT(!item->_next);
+ ASMJIT_ASSERT(ref);
+
+ CompilerItem *prev = ref;
+ CompilerItem *next = ref->_next;
+
+ item->_prev = prev;
+ item->_next = next;
+
+ prev->_next = item;
+ if (next)
+ next->_prev = item;
+ else
+ this->_last = item;
+}
+
+void Compiler::removeItem(CompilerItem *item)
+{
+ CompilerItem *prev = item->_prev;
+ CompilerItem *next = item->_next;
+
+ if (this->_first == item)
+ this->_first = next;
+ else
+ prev->_next = next;
+ if (this->_last == item)
+ this->_last = prev;
+ else
+ next->_prev = prev;
+
+ item->_prev = nullptr;
+ item->_next = nullptr;
+
+ if (this->_current == item)
+ this->_current = prev;
+}
+
+// ============================================================================
+// [AsmJit::Compiler - Comment]
+// ============================================================================
+
+void Compiler::comment(const char *fmt, ...)
+{
+ char buf[128];
+ char *p = buf;
+
+ if (fmt)
+ {
+ *p++ = ';';
+ *p++ = ' ';
+
+ va_list ap;
+ va_start(ap, fmt);
+ p += vsnprintf(p, 100, fmt, ap);
+ va_end(ap);
+ }
+
+ *p++ = '\n';
+ *p = '\0';
+
+ CompilerComment *item = Compiler_newItem<CompilerComment>(this, buf);
+ this->addItem(item);
+}
+
+// ============================================================================
+// [AsmJit::Compiler - Embed]
+// ============================================================================
+
+void Compiler::embed(const void *data, size_t len)
+{
+ // Align length to 16 bytes.
+ size_t alignedSize = IntUtil::align(len, sizeof(uintptr_t));
+ void *p = this->_zoneMemory.alloc(sizeof(CompilerEmbed) - sizeof(void *) + alignedSize);
+
+ if (!p)
+ return;
+
+ CompilerEmbed *item = new(p) CompilerEmbed(this, data, len);
+ this->addItem(item);
+}
+
+} // AsmJit namespace
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/compiler.h
@@ -1,1 +1,338 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_CORE_COMPILER_H
+#define _ASMJIT_CORE_COMPILER_H
+
+// [Dependencies - AsmJit]
+#include "../core/assembler.h"
+#include "../core/context.h"
+#include "../core/func.h"
+#include "../core/operand.h"
+#include "../core/podvector.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [Forward Declarations]
+// ============================================================================
+
+struct CompilerContext;
+struct CompilerFuncDecl;
+struct CompilerFuncEnd;
+struct CompilerInst;
+struct CompilerItem;
+struct CompilerTarget;
+
+// ============================================================================
+// [AsmJit::CompilerState]
+// ============================================================================
+
+//! @brief Compiler state base.
+struct CompilerState
+{
+};
+
+// ============================================================================
+// [AsmJit::CompilerVar]
+// ============================================================================
+
+//! @brief Compiler variable base.
+struct CompilerVar
+{
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get variable name.
+ const char *getName() const { return this->_name; }
+ //! @brief Get variable id.
+ uint32_t getId() const { return this->_id; }
+
+ //! @brief Get variable type.
+ uint32_t getType() const { return this->_type; }
+ //! @brief Get variable class.
+ uint32_t getClass() const { return this->_class; }
+ //! @brief Get variable priority.
+ uint32_t getPriority() const { return this->_priority; }
+ //! @brief Get variable size.
+ uint32_t getSize() const { return this->_size; }
+
+ //! @brief Get whether the variable is a function argument.
+ bool isArgument() const { return !!(this->_isRegArgument | this->_isMemArgument); }
+ //! @brief Get whether the variable is a function argument passed through register.
+ bool isRegArgument() const { return !!this->_isRegArgument; }
+ //! @brief Get whether the variable is a function argument passed through memory.
+ bool isMemArgument() const { return !!this->_isMemArgument; }
+
+ //! @brief Get variable content can be calculated by a simple instruction.
+ bool isCalculated() const { return !!this->_isCalculated; }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Variable name.
+ const char *_name;
+ //! @brief Variable id.
+ uint32_t _id;
+
+ //! @brief Variable type.
+ uint8_t _type;
+ //! @brief Variable class.
+ uint8_t _class;
+ //! @brief Variable priority.
+ uint8_t _priority;
+
+ //! @brief Whether the variable is a function argument passed through register.
+ uint8_t _isRegArgument : 1;
+ //! @brief Whether the variable is a function argument passed through memory.
+ uint8_t _isMemArgument : 1;
+ //! @brief Whether variable content can be calculated by a simple instruction.
+ //!
+ //! This is used mainly by MMX and SSE2 code. This flag indicates that
+ //! register allocator should never reserve memory for this variable, because
+ //! the content can be generated by a single instruction (for example PXOR).
+ uint8_t _isCalculated : 1;
+ //! @internal.
+ uint8_t _unused : 5;
+
+ //! @brief Variable size.
+ uint32_t _size;
+};
+
+// ============================================================================
+// [AsmJit::Compiler]
+// ============================================================================
+
+//! @brief Compiler.
+//!
+//! @sa @ref Assembler.
+struct Compiler
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref Compiler instance.
+ ASMJIT_API Compiler(Context *context);
+ //! @brief Destroy the @ref Compiler instance.
+ ASMJIT_API virtual ~Compiler();
+
+ // --------------------------------------------------------------------------
+ // [Context]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get code generator.
+ Context *getContext() const { return this->_context; }
+
+ // --------------------------------------------------------------------------
+ // [Memory Management]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get zone memory manager.
+ ZoneMemory &getZoneMemory() { return this->_zoneMemory; }
+
+ //! @brief Get link memory manager.
+ ZoneMemory &getLinkMemory() { return this->_linkMemory; }
+
+ // --------------------------------------------------------------------------
+ // [Logging]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get logger.
+ Logger *getLogger() const { return this->_logger; }
+
+ //! @brief Set logger to @a logger.
+ ASMJIT_API virtual void setLogger(Logger *logger);
+
+ // --------------------------------------------------------------------------
+ // [Error Handling]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get error code.
+ uint32_t getError() const { return this->_error; }
+
+ //! @brief Set error code.
+ //!
+ //! This method is virtual, because higher classes can use it to catch all
+ //! errors.
+ ASMJIT_API virtual void setError(uint32_t error);
+
+ // --------------------------------------------------------------------------
+ // [Properties]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get compiler property.
+ ASMJIT_API virtual uint32_t getProperty(uint32_t propertyId);
+ //! @brief Set compiler property.
+ ASMJIT_API virtual void setProperty(uint32_t propertyId, uint32_t value);
+
+ // --------------------------------------------------------------------------
+ // [Clear / Reset]
+ // --------------------------------------------------------------------------
+
+ //! @brief Clear everything, but not deallocate buffers.
+ //!
+ //! @note This method will destroy your code.
+ ASMJIT_API void clear();
+
+ //! @brief Free internal buffer, all emitters and NULL all pointers.
+ //!
+ //! @note This method will destroy your code.
+ ASMJIT_API void reset();
+
+ //! @brief Called by clear() and reset() to clear all data related to derived
+ //! class implementation.
+ ASMJIT_API virtual void _purge();
+
+ // --------------------------------------------------------------------------
+ // [Item Management]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get first item.
+ CompilerItem *getFirstItem() const { return this->_first; }
+
+ //! @brief Get last item.
+ CompilerItem *getLastItem() const { return this->_last; }
+
+ //! @brief Get current item.
+ //!
+ //! @note If this method returns @c NULL it means that nothing has been
+ //! emitted yet.
+ CompilerItem *getCurrentItem() const { return this->_current; }
+
+ //! @brief Get current function.
+ CompilerFuncDecl *getFunc() const { return this->_func; }
+
+ //! @brief Set current item to @a item and return the previous current one.
+ ASMJIT_API CompilerItem *setCurrentItem(CompilerItem *item);
+
+ //! @brief Add item after current item to @a item and set current item to
+ //! @a item.
+ ASMJIT_API void addItem(CompilerItem *item);
+
+ //! @brief Add item after @a ref.
+ ASMJIT_API void addItemAfter(CompilerItem *item, CompilerItem *ref);
+
+ //! @brief Remove item @a item.
+ ASMJIT_API void removeItem(CompilerItem *item);
+
+ // --------------------------------------------------------------------------
+ // [Comment]
+ // --------------------------------------------------------------------------
+
+ //! @brief Emit a single comment line.
+ //!
+ //! @note Comment is not directly sent to logger, but instead it's stored as
+ //! @ref CompilerComment item emitted when @c serialize() method is called.
+ ASMJIT_API void comment(const char *fmt, ...);
+
+ // --------------------------------------------------------------------------
+ // [Embed]
+ // --------------------------------------------------------------------------
+
+ //! @brief Embed data.
+ ASMJIT_API void embed(const void *data, size_t len);
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief ZoneMemory allocator, used to allocate compiler items.
+ ZoneMemory _zoneMemory;
+ //! @brief ZoneMemory allocator, used to alloc small data structures like
+ //! linked lists.
+ ZoneMemory _linkMemory;
+
+ //! @brief Context.
+ Context *_context;
+ //! @brief Logger.
+ Logger *_logger;
+
+ //! @brief Error code.
+ uint32_t _error;
+ //! @brief Properties.
+ uint32_t _properties;
+ //! @brief Contains options for next emitted instruction, clear after each emit.
+ uint32_t _emitOptions;
+ //! @brief Whether compiler was finished the job (register allocator, etc...).
+ uint32_t _finished;
+
+ //! @brief First item.
+ CompilerItem *_first;
+ //! @brief Last item.
+ CompilerItem *_last;
+ //! @brief Current item.
+ CompilerItem *_current;
+ //! @brief Current function.
+ CompilerFuncDecl *_func;
+
+ //! @brief Targets.
+ PodVector<CompilerTarget *> _targets;
+ //! @brief Variables.
+ PodVector<CompilerVar *> _vars;
+
+ //! @brief Compiler context instance, only available after prepare().
+ CompilerContext *_cc;
+
+ //! @brief Variable name id (used to generate unique names per function).
+ int _varNameId;
+};
+
+// ============================================================================
+// [AsmJit::Compiler - Helpers]
+// ============================================================================
+
+template<typename T, typename Compiler> inline T *Compiler_newItem(Compiler *self)
+{
+ void *addr = self->getZoneMemory().alloc(sizeof(T));
+ return new(addr) T(self);
+}
+
+template<typename T, typename Compiler, typename P1> inline T *Compiler_newItem(Compiler *self, P1 p1)
+{
+ void *addr = self->getZoneMemory().alloc(sizeof(T));
+ return new(addr) T(self, p1);
+}
+
+template<typename T, typename Compiler, typename P1, typename P2> inline T *Compiler_newItem(Compiler *self, P1 p1, P2 p2)
+{
+ void *addr = self->getZoneMemory().alloc(sizeof(T));
+ return new(addr) T(self, p1, p2);
+}
+
+template<typename T, typename Compiler, typename P1, typename P2, typename P3> inline T *Compiler_newItem(Compiler *self, P1 p1, P2 p2, P3 p3)
+{
+ void* addr = self->getZoneMemory().alloc(sizeof(T));
+ return new(addr) T(self, p1, p2, p3);
+}
+
+template<typename T, typename Compiler, typename P1, typename P2, typename P3, typename P4> inline T *Compiler_newItem(Compiler *self, P1 p1, P2 p2, P3 p3, P4 p4)
+{
+ void *addr = self->getZoneMemory().alloc(sizeof(T));
+ return new(addr) T(self, p1, p2, p3, p4);
+}
+
+template<typename T, typename Compiler, typename P1, typename P2, typename P3, typename P4, typename P5> inline T *Compiler_newItem(Compiler *self, P1 p1, P2 p2, P3 p3, P4 p4, P5 p5)
+{
+ void *addr = self->getZoneMemory().alloc(sizeof(T));
+ return new(addr) T(self, p1, p2, p3, p4, p5);
+}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_CORE_COMPILER_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/compilercontext.cpp
@@ -1,1 +1,35 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/compilercontext.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [AsmJit::CompilerContext - Construction / Destruction]
+// ============================================================================
+
+CompilerContext::CompilerContext(Compiler *compiler) : _zoneMemory(8192 - sizeof(ZoneChunk) - 32), _compiler(compiler), _func(nullptr), _start(nullptr), _stop(nullptr), _extraBlock(nullptr), _state(nullptr),
+ _active(nullptr), _currentOffset(0), _isUnreachable(0)
+{
+}
+
+CompilerContext::~CompilerContext()
+{
+}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/compilercontext.h
@@ -1,1 +1,88 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+// [Guard]
+#ifndef _ASMJIT_CORE_COMPILERCONTEXT_H
+#define _ASMJIT_CORE_COMPILERCONTEXT_H
+
+// [Dependencies - AsmJit]
+#include "../core/compiler.h"
+#include "../core/compilerfunc.h"
+#include "../core/compileritem.h"
+#include "../core/zonememory.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [AsmJit::CompilerContext]
+// ============================================================================
+
+struct CompilerContext
+{
+ ASMJIT_NO_COPY(CompilerContext)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API CompilerContext(Compiler *compiler);
+ ASMJIT_API virtual ~CompilerContext();
+
+ // --------------------------------------------------------------------------
+ // [Accessor]
+ // --------------------------------------------------------------------------
+
+ Compiler *getCompiler() const { return this->_compiler; }
+
+ CompilerFuncDecl *getFunc() const { return this->_func; }
+
+ CompilerItem *getExtraBlock() const { return this->_extraBlock; }
+
+ void setExtraBlock(CompilerItem *item) { this->_extraBlock = item; }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief ZoneMemory manager.
+ ZoneMemory _zoneMemory;
+
+ //! @brief Compiler.
+ Compiler *_compiler;
+ //! @brief Function.
+ CompilerFuncDecl *_func;
+
+ //! @brief Start of the current active scope.
+ CompilerItem *_start;
+ //! @brief End of the current active scope.
+ CompilerItem *_stop;
+ //! @brief Item that is used to insert some code after the function body.
+ CompilerItem *_extraBlock;
+
+ //! @brief Current state (used by register allocator).
+ CompilerState *_state;
+ //! @brief Link to circular double-linked list containing all active variables
+ //! of the current state.
+ CompilerVar *_active;
+
+ //! @brief Current offset, used in prepare() stage. Each item should increment it.
+ uint32_t _currentOffset;
+ //! @brief Whether current code is unreachable.
+ uint32_t _isUnreachable;
+};
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_CORE_COMPILERCONTEXT_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/compilerfunc.cpp
@@ -1,1 +1,163 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/assembler.h"
+#include "../core/compiler.h"
+#include "../core/compilerfunc.h"
+#include "../core/compileritem.h"
+#include "../core/intutil.h"
+#include "../core/logger.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit {
+
+// ============================================================================
+// [AsmJit::CompilerFuncDecl - Construction / Destruction]
+// ============================================================================
+
+CompilerFuncDecl::CompilerFuncDecl(Compiler *compiler) : CompilerItem(compiler, kCompilerItemFuncDecl), _entryTarget(nullptr), _exitTarget(nullptr), _end(nullptr), _decl(nullptr), _vars(nullptr), _funcHints(0),
+ _funcFlags(0), _funcCallStackSize(0)
+{
+}
+
+CompilerFuncDecl::~CompilerFuncDecl()
+{
+}
+
+// ============================================================================
+// [AsmJit::CompilerFuncDecl - Hints]
+// ============================================================================
+
+void CompilerFuncDecl::setHint(uint32_t hint, uint32_t value)
+{
+ if (hint > 31)
+ return;
+
+ if (value)
+ this->_funcHints |= IntUtil::maskFromIndex(hint);
+ else
+ this->_funcHints &= ~IntUtil::maskFromIndex(hint);
+}
+
+uint32_t CompilerFuncDecl::getHint(uint32_t hint) const
+{
+ if (hint > 31)
+ return 0;
+
+ return !!(this->_funcHints & IntUtil::maskFromIndex(hint));
+}
+
+// ============================================================================
+// [AsmJit::CompilerFuncEnd - Construction / Destruction]
+// ============================================================================
+
+CompilerFuncEnd::CompilerFuncEnd(Compiler *compiler, CompilerFuncDecl *func) : CompilerItem(compiler, kCompilerItemFuncEnd), _func(func)
+{
+}
+
+CompilerFuncEnd::~CompilerFuncEnd()
+{
+}
+
+// ============================================================================
+// [AsmJit::CompilerFuncEnd - Interface]
+// ============================================================================
+
+CompilerItem *CompilerFuncEnd::translate(CompilerContext &cc)
+{
+ this->_isTranslated = true;
+ return nullptr;
+}
+
+// ============================================================================
+// [AsmJit::CompilerFuncRet - Construction / Destruction]
+// ============================================================================
+
+CompilerFuncRet::CompilerFuncRet(Compiler *compiler, CompilerFuncDecl *func, const Operand *first, const Operand *second) : CompilerItem(compiler, kCompilerItemFuncRet), _func(func)
+{
+ if (first)
+ this->_ret[0] = *first;
+
+ if (second)
+ this->_ret[1] = *second;
+}
+
+CompilerFuncRet::~CompilerFuncRet()
+{
+}
+
+// ============================================================================
+// [AsmJit::CompilerFuncRet - Misc]
+// ============================================================================
+
+bool CompilerFuncRet::mustEmitJump() const
+{
+ // Iterate over next items until we found an item which emits a real instruction.
+ CompilerItem *item = this->getNext();
+
+ while (item)
+ {
+ switch (item->getType())
+ {
+ // Interesting item.
+ case kCompilerItemEmbed:
+ case kCompilerItemInst:
+ case kCompilerItemFuncCall:
+ case kCompilerItemFuncRet:
+ return true;
+
+ // Non-interesting item.
+ case kCompilerItemComment:
+ case kCompilerItemMark:
+ case kCompilerItemAlign:
+ case kCompilerItemHint:
+ break;
+
+ case kCompilerItemTarget:
+ if (static_cast<CompilerTarget *>(item)->getLabel().getId() == this->getFunc()->getExitLabel().getId())
+ return false;
+ break;
+
+ // Invalid items - these items shouldn't be here. We are inside the
+ // function, after prolog.
+ case kCompilerItemFuncDecl:
+ break;
+
+ // We can't go forward from here.
+ case kCompilerItemFuncEnd:
+ return false;
+ }
+
+ item = item->getNext();
+ }
+
+ return false;
+}
+
+// ============================================================================
+// [AsmJit::CompilerFuncCall - Construction / Destruction]
+// ============================================================================
+
+CompilerFuncCall::CompilerFuncCall(Compiler *compiler, CompilerFuncDecl *caller, const Operand *target) : CompilerItem(compiler, kCompilerItemFuncCall), _caller(caller), _decl(nullptr), _args(nullptr)
+{
+ if (target)
+ this->_target = *target;
+}
+
+CompilerFuncCall::~CompilerFuncCall()
+{
+}
+
+} // AsmJit namespace
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/compilerfunc.h
@@ -1,1 +1,327 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_CORE_COMPILERFUNC_H
+#define _ASMJIT_CORE_COMPILERFUNC_H
+
+// [Dependencies - AsmJit]
+#include "../core/compiler.h"
+#include "../core/compileritem.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [AsmJit::CompilerFuncDecl]
+// ============================================================================
+
+//! @brief Compiler function declaration item.
+//!
+//! Functions are base blocks for generating assembler output. Each generated
+//! assembler stream needs standard entry and leave sequences thats compatible
+//! with the operating system conventions (ABI).
+//!
+//! Function class can be used to generate function prolog) and epilog sequences
+//! that are compatible with the demanded calling convention and to allocate and
+//! manage variables that can be allocated/spilled during compilation time.
+//!
+//! @note To create a function use @c Compiler::newFunc() method, do not
+//! create any form of compiler function items using new operator.
+//!
+//! @sa @ref CompilerState, @ref CompilerVar.
+struct CompilerFuncDecl : public CompilerItem
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @c CompilerFuncDecl instance.
+ //!
+ //! @note Always use @c AsmJit::Compiler::newFunc() to create @c Function
+ //! instance.
+ ASMJIT_API CompilerFuncDecl(Compiler *compiler);
+ //! @brief Destroy the @c CompilerFuncDecl instance.
+ ASMJIT_API virtual ~CompilerFuncDecl();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get function entry label.
+ //!
+ //! Entry label can be used to call this function from another code that's
+ //! being generated.
+ const Label &getEntryLabel() const { return this->_entryLabel; }
+
+ //! @brief Get function exit label.
+ //!
+ //! Use exit label to jump to function epilog.
+ const Label &getExitLabel() const { return this->_exitLabel; }
+
+ //! @brief Get function entry target.
+ CompilerTarget *getEntryTarget() const { return this->_entryTarget; }
+
+ //! @brief Get function exit target.
+ CompilerTarget *getExitTarget() const { return this->_exitTarget; }
+
+ //! @brief Get function end item.
+ CompilerFuncEnd *getEnd() const { return this->_end; }
+
+ //! @brief Get function declaration.
+ FuncDecl *getDecl() const { return this->_decl; }
+
+ //! @brief Get function arguments as variables.
+ CompilerVar **getVars() const { return this->_vars; }
+
+ //! @brief Get function argument at @a index.
+ CompilerVar *getVar(uint32_t index) const
+ {
+ ASMJIT_ASSERT(index < this->_decl->getArgumentsCount());
+ return this->_vars[index];
+ }
+
+ //! @brief Get function hints.
+ uint32_t getFuncHints() const { return this->_funcHints; }
+
+ //! @brief Get function flags.
+ uint32_t getFuncFlags() const { return this->_funcFlags; }
+
+ //! @brief Get whether the _funcFlags has @a flag
+ bool hasFuncFlag(uint32_t flag) const { return !!(this->_funcFlags & flag); }
+
+ //! @brief Set function @a flag.
+ void setFuncFlag(uint32_t flag) { this->_funcFlags |= flag; }
+
+ //! @brief Clear function @a flag.
+ void clearFuncFlag(uint32_t flag) { this->_funcFlags &= ~flag; }
+
+ //! @brief Get whether the function is also a caller.
+ bool isCaller() const { return this->hasFuncFlag(kFuncFlagIsCaller); }
+
+ //! @brief Get whether the function is finished.
+ bool isFinished() const { return this->hasFuncFlag(kFuncFlagIsFinished); }
+
+ //! @brief Get whether the function is naked.
+ bool isNaked() const { return this->hasFuncFlag(kFuncFlagIsNaked); }
+
+ //! @brief Get stack size needed to call other functions.
+ int32_t getFuncCallStackSize() const { return this->_funcCallStackSize; }
+
+ // --------------------------------------------------------------------------
+ // [Hints]
+ // --------------------------------------------------------------------------
+
+ //! @brief Set function hint.
+ ASMJIT_API virtual void setHint(uint32_t hint, uint32_t value);
+ //! @brief Get function hint.
+ ASMJIT_API virtual uint32_t getHint(uint32_t hint) const;
+
+ // --------------------------------------------------------------------------
+ // [Prototype]
+ // --------------------------------------------------------------------------
+
+ virtual void setPrototype(uint32_t convention, uint32_t returnType, const uint32_t *arguments, uint32_t argumentsCount) = 0;
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Function entry label.
+ Label _entryLabel;
+ //! @brief Function exit label.
+ Label _exitLabel;
+
+ //! @brief Function entry target.
+ CompilerTarget *_entryTarget;
+ //! @brief Function exit target.
+ CompilerTarget *_exitTarget;
+
+ //! @brief Function end item.
+ CompilerFuncEnd *_end;
+
+ //! @brief Function declaration.
+ FuncDecl *_decl;
+ //! @brief Function arguments as compiler variables.
+ CompilerVar **_vars;
+
+ //! @brief Function hints;
+ uint32_t _funcHints;
+ //! @brief Function flags.
+ uint32_t _funcFlags;
+
+ //! @brief Stack size needed to call other functions.
+ int32_t _funcCallStackSize;
+};
+
+// ============================================================================
+// [AsmJit::CompilerFuncEnd]
+// ============================================================================
+
+//! @brief Compiler function end item.
+//!
+//! This item does nothing; it's only used by @ref Compiler to mark specific
+//! location in the code. The @c CompilerFuncEnd is similar to @c CompilerMark,
+//! except that it overrides @c translate() to return @c NULL.
+struct CompilerFuncEnd : public CompilerItem
+{
+ ASMJIT_NO_COPY(CompilerFuncEnd)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref CompilerMark instance.
+ ASMJIT_API CompilerFuncEnd(Compiler *compiler, CompilerFuncDecl *func);
+ //! @brief Destroy the @ref CompilerMark instance.
+ ASMJIT_API virtual ~CompilerFuncEnd();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get related function.
+ CompilerFuncDecl *getFunc() const { return this->_func; }
+
+ // --------------------------------------------------------------------------
+ // [Interface]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual CompilerItem* translate(CompilerContext &cc);
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Related function.
+ CompilerFuncDecl *_func;
+};
+
+// ============================================================================
+// [AsmJit::CompilerFuncRet]
+// ============================================================================
+
+//! @brief Compiler return from function item.
+struct CompilerFuncRet : public CompilerItem
+{
+ ASMJIT_NO_COPY(CompilerFuncRet)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref CompilerFuncRet instance.
+ ASMJIT_API CompilerFuncRet(Compiler *compiler, CompilerFuncDecl *func, const Operand *first, const Operand *second);
+ //! @brief Destroy the @ref CompilerFuncRet instance.
+ ASMJIT_API virtual ~CompilerFuncRet();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @Brief Get the related function.
+ CompilerFuncDecl *getFunc() const { return this->_func; }
+
+ //! @brief Get the first return operand.
+ Operand &getFirst() { return this->_ret[0]; }
+
+ //! @overload
+ const Operand &getFirst() const { return this->_ret[0]; }
+
+ //! @brief Get the second return operand.
+ Operand &getSecond() { return this->_ret[1]; }
+
+ //! @overload
+ const Operand &getSecond() const { return this->_ret[1]; }
+
+ // --------------------------------------------------------------------------
+ // [Misc]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get whether jump to epilog has to be emitted.
+ ASMJIT_API bool mustEmitJump() const;
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Related function.
+ CompilerFuncDecl *_func;
+ //! @brief Return operand(s).
+ Operand _ret[2];
+};
+
+// ============================================================================
+// [AsmJit::CompilerFuncCall]
+// ============================================================================
+
+//! @brief Compiler function call item.
+struct CompilerFuncCall : public CompilerItem
+{
+ ASMJIT_NO_COPY(CompilerFuncCall)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref CompilerFuncCall instance.
+ ASMJIT_API CompilerFuncCall(Compiler *compiler, CompilerFuncDecl *caller, const Operand *target);
+ //! @brief Destroy the @ref CompilerFuncCall instance.
+ ASMJIT_API virtual ~CompilerFuncCall();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get caller.
+ CompilerFuncDecl *getCaller() const { return this->_caller; }
+
+ //! @brief Get function declaration.
+ FuncDecl *getDecl() const { return this->_decl; }
+
+ //! @brief Get target operand.
+ Operand &getTarget() { return this->_target; }
+
+ //! @overload
+ const Operand &getTarget() const { return this->_target; }
+
+ // --------------------------------------------------------------------------
+ // [Prototype]
+ // --------------------------------------------------------------------------
+
+ virtual void setPrototype(uint32_t convention, uint32_t returnType, const uint32_t *arguments, uint32_t argumentsCount) = 0;
+
+ //! @brief Set function prototype.
+ void setPrototype(uint32_t convention, const FuncPrototype &func) { this->setPrototype(convention, func.getReturnType(), func.getArguments(), func.getArgumentsCount()); }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Caller (the function which does the call).
+ CompilerFuncDecl *_caller;
+ //! @brief Function declaration.
+ FuncDecl *_decl;
+
+ //! @brief Operand (address of function, register, label, ...).
+ Operand _target;
+ //! @brief Return operands.
+ Operand _ret[2];
+ //! @brief Arguments operands.
+ Operand *_args;
+};
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_CORE_COMPILERFUNC_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/compileritem.cpp
@@ -1,1 +1,274 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/assembler.h"
+#include "../core/compiler.h"
+#include "../core/compilercontext.h"
+#include "../core/compilerfunc.h"
+#include "../core/compileritem.h"
+#include "../core/intutil.h"
+#include "../core/logger.h"
+
+// [Dependencies - C]
+#include <stdarg.h>
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [AsmJit::CompilerItem - Construction / Destruction]
+// ============================================================================
+
+CompilerItem::CompilerItem(Compiler *compiler, uint32_t type) : _compiler(compiler), _prev(nullptr), _next(nullptr), _comment(nullptr), _type(static_cast<uint8_t>(type)), _isTranslated(false), _isUnreachable(false),
+ _reserved(0), _offset(kInvalidValue)
+{
+}
+
+CompilerItem::~CompilerItem()
+{
+}
+
+// ============================================================================
+// [AsmJit::CompilerItem - Interface]
+// ============================================================================
+
+void CompilerItem::prepare(CompilerContext &cc)
+{
+ this->_offset = cc._currentOffset;
+}
+
+CompilerItem *CompilerItem::translate(CompilerContext &cc)
+{
+ return this->translated();
+}
+
+void CompilerItem::emit(Assembler &a) { }
+void CompilerItem::post(Assembler &a) { }
+
+// ============================================================================
+// [AsmJit::CompilerItem - Misc]
+// ============================================================================
+
+int CompilerItem::getMaxSize() const
+{
+ // Default maximum size is -1 which means that it's not known.
+ return -1;
+}
+
+bool CompilerItem::_tryUnuseVar(CompilerVar *v)
+{
+ return false;
+}
+
+// ============================================================================
+// [AsmJit::CompilerItem - Comment]
+// ============================================================================
+
+void CompilerItem::setComment(const char *str)
+{
+ this->_comment = this->_compiler->getZoneMemory().sdup(str);
+}
+
+void CompilerItem::formatComment(const char *fmt, ...)
+{
+ // The capacity should be large enough.
+ char buf[128];
+
+ va_list ap;
+ va_start(ap, fmt);
+ vsnprintf(buf, ASMJIT_ARRAY_SIZE(buf), fmt, ap);
+ va_end(ap);
+
+ // I don't know if vsnprintf can produce non-null terminated string, in case
+ // it can, we terminate it here.
+ buf[ASMJIT_ARRAY_SIZE(buf) - 1] = '\0';
+
+ this->setComment(buf);
+}
+
+// ============================================================================
+// [AsmJit::CompilerMark - Construction / Destruction]
+// ============================================================================
+
+CompilerMark::CompilerMark(Compiler *compiler) : CompilerItem(compiler, kCompilerItemMark)
+{
+}
+
+CompilerMark::~CompilerMark()
+{
+}
+
+// ============================================================================
+// [AsmJit::CompilerMark - Misc]
+// ============================================================================
+
+int CompilerMark::getMaxSize() const
+{
+ return 0;
+}
+
+// ============================================================================
+// [AsmJit::CompilerComment - Construction / Destruction]
+// ============================================================================
+
+CompilerComment::CompilerComment(Compiler *compiler, const char *str) : CompilerItem(compiler, kCompilerItemComment)
+{
+ if (str)
+ this->setComment(str);
+}
+
+CompilerComment::~CompilerComment()
+{
+}
+
+// ============================================================================
+// [AsmJit::CompilerComment - Interface]
+// ============================================================================
+
+void CompilerComment::emit(Assembler &a)
+{
+ Logger *logger = a.getLogger();
+ if (!logger || !logger->isUsed())
+ return;
+
+ logger->logString(logger->getInstructionPrefix());
+ logger->logString(this->getComment());
+}
+
+// ============================================================================
+// [AsmJit::CompilerComment - Misc]
+// ============================================================================
+
+int CompilerComment::getMaxSize() const
+{
+ return 0;
+}
+
+// ============================================================================
+// [AsmJit::CompilerEmbed - Construction / Destruction]
+// ============================================================================
+
+CompilerEmbed::CompilerEmbed(Compiler *compiler, const void *data, size_t length) : CompilerItem(compiler, kCompilerItemEmbed)
+{
+ this->_length = length;
+ memcpy(this->_data, data, length);
+}
+
+CompilerEmbed::~CompilerEmbed()
+{
+}
+
+// ============================================================================
+// [AsmJit::CompilerEmbed - Interface]
+// ============================================================================
+
+void CompilerEmbed::emit(Assembler &a)
+{
+ a.embed(this->_data, this->_length);
+}
+
+// ============================================================================
+// [AsmJit::CompilerEmbed - Misc]
+// ============================================================================
+
+int CompilerEmbed::getMaxSize() const
+{
+ return static_cast<int>(_length);
+}
+
+// ============================================================================
+// [AsmJit::CompilerAlign - Construction / Destruction]
+// ============================================================================
+
+CompilerAlign::CompilerAlign(Compiler *compiler, uint32_t size) : CompilerItem(compiler, kCompilerItemAlign), _size(size)
+{
+}
+
+CompilerAlign::~CompilerAlign()
+{
+}
+
+// ============================================================================
+// [AsmJit::CompilerAlign - Misc]
+// ============================================================================
+
+int CompilerAlign::getMaxSize() const
+{
+ if (!this->_size)
+ return 0;
+ else
+ return static_cast<int>(this->_size - 1);
+}
+
+// ============================================================================
+// [AsmJit::CompilerHint - Construction / Destruction]
+// ============================================================================
+
+CompilerHint::CompilerHint(Compiler *compiler, CompilerVar *var, uint32_t hintId, uint32_t hintValue) : CompilerItem(compiler, kCompilerItemHint), _var(var), _hintId(hintId), _hintValue(hintValue)
+{
+ ASMJIT_ASSERT(var);
+}
+
+CompilerHint::~CompilerHint()
+{
+}
+
+// ============================================================================
+// [AsmJit::CompilerTarget - Construction / Destruction]
+// ============================================================================
+
+CompilerTarget::CompilerTarget(Compiler *compiler, const Label &label) : CompilerItem(compiler, kCompilerItemTarget), _label(label), _from(nullptr), _state(nullptr), _jumpsCount(0)
+{
+}
+
+CompilerTarget::~CompilerTarget()
+{
+}
+
+// ============================================================================
+// [AsmJit::CompilerTarget - Misc]
+// ============================================================================
+
+int CompilerTarget::getMaxSize() const
+{
+ return 0;
+}
+
+// ============================================================================
+// [AsmJit::CompilerInst - Construction / Destruction]
+// ============================================================================
+
+CompilerInst::CompilerInst(Compiler *compiler, uint32_t code, Operand *opData, uint32_t opCount) : CompilerItem(compiler, kCompilerItemInst), _code(code), _emitOptions(static_cast<uint8_t>(compiler->_emitOptions)),
+ _instFlags(0), _operandsCount(static_cast<uint8_t>(opCount)), _variablesCount(0), _operands(opData)
+{
+ // Each created instruction takes emit options and clears it.
+ compiler->_emitOptions = 0;
+}
+
+CompilerInst::~CompilerInst()
+{
+}
+
+// ============================================================================
+// [AsmJit::CompilerInst - GetJumpTarget]
+// ============================================================================
+
+CompilerTarget *CompilerInst::getJumpTarget() const
+{
+ return nullptr;
+}
+
+} // AsmJit namespace
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/compileritem.h
@@ -1,1 +1,518 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_CORE_COMPILERITEM_H
+#define _ASMJIT_CORE_COMPILERITEM_H
+
+// [Dependencies - AsmJit]
+#include "../core/compiler.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [AsmJit::CompilerItem]
+// ============================================================================
+
+//! @brief Compiler item.
+//!
+//! @ref CompilerItem represents items generated by compiler by calling its
+//! methods to build functions, instruction stream, bind labels, etc... Each
+//! item contains its type information and virtual methods which are called at
+//! various compilation steps.
+struct CompilerItem
+{
+ ASMJIT_NO_COPY(CompilerItem)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create new @ref CompilerItem.
+ //!
+ //! @note Always use @ref Compiler to create an item!
+ ASMJIT_API CompilerItem(Compiler *compiler, uint32_t type);
+
+ //! @brief Destroy @ref CompilerItem.
+ //!
+ //! @note @ref Compiler keeps links into all items so it can destroy them
+ //! when code generation finished or in the case that @ref Compiler was
+ //! destroyed early (for example if an error happened). Never destroy items
+ //! manually!
+ ASMJIT_API virtual ~CompilerItem();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get associated compiler instance.
+ Compiler *getCompiler() const { return this->_compiler; }
+
+ //! @brief Get previous item in the compiler stream.
+ CompilerItem *getPrev() const { return this->_prev; }
+
+ //! @brief Get next item in the compiler stream.
+ CompilerItem *getNext() const { return this->_next; }
+
+ //! @brief Get comment string.
+ const char *getComment() const { return this->_comment; }
+
+ //! @brief Get type of item, see @ref kCompilerItem.
+ uint32_t getType() const { return this->_type; }
+
+ //! @brief Get whether the item was translated.
+ bool isTranslated() const { return this->_isTranslated; }
+
+ //! @brief Get whether the item is unreachable.
+ bool isUnreachable() const { return this->_isUnreachable; }
+
+ //! @brief Get the item offset in the compiler stream.
+ //!
+ //! The offset is not byte offset, each item increments offset by 1 and this
+ //! value is then used by register allocator. The offset is set by compiler
+ //! by the register allocator, don't use it in your code.
+ uint32_t getOffset() const { return this->_offset; }
+
+ // --------------------------------------------------------------------------
+ // [Interface]
+ // --------------------------------------------------------------------------
+
+ //! @brief Step 1. Extract item variables, update statistics, ...
+ ASMJIT_API virtual void prepare(CompilerContext &cc);
+ //! @brief Step 2. Translate instruction, alloc variables, ...
+ ASMJIT_API virtual CompilerItem *translate(CompilerContext &cc);
+ //! @brief Step 3. Emit to @c Assembler.
+ ASMJIT_API virtual void emit(Assembler &a);
+ //! @brief Step 4. Last post step (verify, add data, etc).
+ ASMJIT_API virtual void post(Assembler &a);
+
+ // --------------------------------------------------------------------------
+ // [Misc]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get maximum size of of this when serialized into @ref Assembler
+ //! item in bytes.
+ ASMJIT_API virtual int getMaxSize() const;
+
+ //! @brief Try to unuse the variable @a.
+ //!
+ //! Returns @c true only if the variable will be unused by the instruction,
+ //! otherwise @c false is returned.
+ ASMJIT_API virtual bool _tryUnuseVar(CompilerVar *v);
+
+ // --------------------------------------------------------------------------
+ // [Comment]
+ // --------------------------------------------------------------------------
+
+ //! @brief Set comment string to @a str.
+ ASMJIT_API void setComment(const char *str);
+
+ //! @brief Format comment string using @a fmt string and variable argument list.
+ ASMJIT_API void formatComment(const char *fmt, ...);
+
+ // --------------------------------------------------------------------------
+ // [Protected]
+ // --------------------------------------------------------------------------
+
+protected:
+ //! @brief Mark item as translated and return next.
+ CompilerItem *translated()
+ {
+ ASMJIT_ASSERT(!this->_isTranslated);
+
+ this->_isTranslated = true;
+ return this->_next;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+public:
+ //! @brief Compiler which owns this item.
+ Compiler *_compiler;
+ //! @brief Previous item.
+ CompilerItem *_prev;
+ //! @brief Next item.
+ CompilerItem *_next;
+ //! @brief Inline comment string, initially set to NULL.
+ const char *_comment;
+
+ //! @brief Type of the item, see @ref kCompilerItem.
+ uint32_t _type : 8;
+ //! @brief Whether the item was translated, see @c translate().
+ uint32_t _isTranslated : 1;
+ //! @brief Whether the item is unreachable.
+ uint32_t _isUnreachable : 1;
+ //! @brief Reserved for future use.
+ uint32_t _reserved : 22;
+
+ //! @brief Stream offset (not byte-offset).
+ uint32_t _offset;
+};
+
+// ============================================================================
+// [AsmJit::CompilerMark]
+// ============================================================================
+
+//! @brief Compiler mark item.
+//!
+//! This item does nothing and it's only used by @ref Compiler to mark some
+//! specific location in the compiler stream.
+struct CompilerMark : public CompilerItem
+{
+ ASMJIT_NO_COPY(CompilerMark)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref CompilerMark instance.
+ ASMJIT_API CompilerMark(Compiler *compiler);
+ //! @brief Destroy the @ref CompilerMark instance.
+ ASMJIT_API virtual ~CompilerMark();
+
+ // --------------------------------------------------------------------------
+ // [Misc]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual int getMaxSize() const;
+};
+
+// ============================================================================
+// [AsmJit::CompilerComment]
+// ============================================================================
+
+//! @brief Compiler comment item.
+//!
+//! Comments allows to comment your assembler stream for better debugging
+//! and visualization. Comments are usually ignored in release builds unless
+//! the logger is present.
+struct CompilerComment : public CompilerItem
+{
+ ASMJIT_NO_COPY(CompilerComment)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref CompilerComment instance.
+ ASMJIT_API CompilerComment(Compiler *compiler, const char *comment = nullptr);
+ //! @brief Destroy the @ref CompilerComment instance.
+ ASMJIT_API virtual ~CompilerComment();
+
+ // --------------------------------------------------------------------------
+ // [Interface]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual void emit(Assembler &a);
+
+ // --------------------------------------------------------------------------
+ // [Misc]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual int getMaxSize() const;
+};
+
+// ============================================================================
+// [AsmJit::CompilerEmbed]
+// ============================================================================
+
+//! @brief Compiler embed item.
+//!
+//! Embed item is used to embed data into final assembler stream. The data is
+//! considered to be RAW, there is no analysis.
+struct CompilerEmbed : public CompilerItem
+{
+ ASMJIT_NO_COPY(CompilerEmbed)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref CompilerEmbed instance.
+ ASMJIT_API CompilerEmbed(Compiler *compiler, const void *data, size_t length);
+ //! @brief Destroy the @ref CompilerEmbed instance.
+ ASMJIT_API virtual ~CompilerEmbed();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get pointer to embedded data.
+ uint8_t *getData() const { return const_cast<uint8_t *>(this->_data); }
+
+ //! @brief Get length of embedded data.
+ size_t getLength() const { return this->_length; }
+
+ // --------------------------------------------------------------------------
+ // [Interface]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual void emit(Assembler &a);
+
+ // --------------------------------------------------------------------------
+ // [Misc]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual int getMaxSize() const;
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Data length.
+ size_t _length;
+ //! @brief Data buffer (that will be embedded to the assembler stream).
+ uint8_t _data[sizeof(void *)];
+};
+
+// ============================================================================
+// [AsmJit::CompilerAlign]
+// ============================================================================
+
+//! @brief Compiler align item.
+struct CompilerAlign : public CompilerItem
+{
+ ASMJIT_NO_COPY(CompilerAlign)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref CompilerAlign instance.
+ ASMJIT_API CompilerAlign(Compiler *compiler, uint32_t size = 0);
+ //! @brief Destroy the @ref CompilerAlign instance.
+ ASMJIT_API virtual ~CompilerAlign();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get align size in bytes.
+ uint32_t getSize() const { return this->_size; }
+
+ //! @brief Set align size in bytes to @a size.
+ void setSize(uint32_t size) { this->_size = size; }
+
+ // --------------------------------------------------------------------------
+ // [Misc]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual int getMaxSize() const;
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Align size.
+ uint32_t _size;
+};
+
+// ============================================================================
+// [AsmJit::CompilerHint]
+// ============================================================================
+
+//! @brief Compiler variable hint item.
+struct CompilerHint : public CompilerItem
+{
+ ASMJIT_NO_COPY(CompilerHint)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref CompilerHint instance.
+ ASMJIT_API CompilerHint(Compiler *compiler, CompilerVar *var, uint32_t hintId, uint32_t hintValue);
+ //! @brief Destroy the @ref CompilerHint instance.
+ ASMJIT_API virtual ~CompilerHint();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get variable.
+ CompilerVar *getVar() const { return this->_var; }
+
+ //! @brief Get hint it (see @ref kVarHint).
+ uint32_t getHintId() const { return this->_hintId; }
+
+ //! @brief Set hint it (see @ref kVarHint).
+ void setHintId(uint32_t hintId) { this->_hintId = hintId; }
+
+ //! @brief Get hint value.
+ uint32_t getHintValue() const { return this->_hintValue; }
+
+ //! @brief Set hint value.
+ void setHintValue(uint32_t hintValue) { this->_hintValue = hintValue; }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Variable.
+ CompilerVar *_var;
+ //! @brief Variable hint id.
+ uint32_t _hintId;
+ //! @brief Variable hint value.
+ uint32_t _hintValue;
+};
+
+// ============================================================================
+// [AsmJit::CompilerTarget]
+// ============================================================================
+
+//! @brief Compiler target item.
+struct CompilerTarget : public CompilerItem
+{
+ ASMJIT_NO_COPY(CompilerTarget)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref CompilerTarget instance.
+ ASMJIT_API CompilerTarget(Compiler *compiler, const Label &target);
+ //! @brief Destroy the @ref CompilerTarget instance.
+ ASMJIT_API virtual ~CompilerTarget();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Return label bound to this target.
+ const Label &getLabel() const { return this->_label; }
+
+ //! @brief Get first jmp instruction.
+ CompilerInst *getFrom() const { return this->_from; }
+
+ //! @brief Get register allocator state for this target.
+ CompilerState *getState() const { return this->_state; }
+
+ //! @brief Get number of jumps to this target.
+ uint32_t getJumpsCount() const { return this->_jumpsCount; }
+
+ // --------------------------------------------------------------------------
+ // [Misc]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual int getMaxSize() const;
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Label.
+ Label _label;
+ //! @brief First jump instruction that points to this target (label).
+ CompilerInst *_from;
+ //! @brief State at this location.
+ CompilerState *_state;
+ //! @brief Count of jumps here.
+ uint32_t _jumpsCount;
+};
+
+// ============================================================================
+// [AsmJit::CompilerInst]
+// ============================================================================
+
+//! @brief Compiler instruction item.
+struct CompilerInst : public CompilerItem
+{
+ ASMJIT_NO_COPY(CompilerInst)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref CompilerInst instance.
+ ASMJIT_API CompilerInst(Compiler *compiler, uint32_t code, Operand *opData, uint32_t opCount);
+ //! @brief Destroy the @ref CompilerInst instance.
+ ASMJIT_API virtual ~CompilerInst();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get instruction code, see @c kInstCode.
+ uint32_t getCode() const { return this->_code; }
+
+ //! @brief Set instruction code to @a code.
+ //!
+ //! Please do not modify instruction code if you are not know what you are
+ //! doing. Incorrect instruction code or operands can raise assertion() at
+ //! runtime.
+ void setCode(uint32_t code) { this->_code = code; }
+
+ //! @brief Get emit options (compiler specific).
+ uint32_t getEmitOptions() const { return this->_emitOptions; }
+
+ //! @brief Get instruction flags (compiler specific).
+ uint32_t getInstFlags() const { return this->_instFlags; }
+
+ //! @brief Get whether the instruction has flag @a flag.
+ bool hasInstFlag(uint8_t flag) const { return !!(this->_instFlags & flag); }
+
+ //! @brief Set instruction @a flag.
+ void setInstFlag(uint8_t flag) { this->_instFlags |= flag; }
+
+ //! @brief Clear instruction @a flag.
+ void clearInstFlag(uint8_t flag) { this->_instFlags &= ~flag; }
+
+ //! @brief Get count of operands in operands array.
+ uint32_t getOperandsCount() const { return this->_operandsCount; }
+
+ //! @brief Get count of variables in variables array.
+ uint32_t getVariablesCount() const { return this->_variablesCount; }
+
+ //! @brief Get operands array (3 operands total).
+ Operand *getOperands() { return this->_operands; }
+ //! @brief Get operands array (3 operands total).
+ const Operand *getOperands() const { return this->_operands; }
+
+ // --------------------------------------------------------------------------
+ // [GetJumpTarget]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get possible jump target.
+ //!
+ //! If this instruction is conditional or normal jump then return value is
+ //! the label location (@ref CompilerTarget), otherwise the return value is
+ //! @c NULL.
+ ASMJIT_API virtual CompilerTarget *getJumpTarget() const;
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Instruction code, see @c kInstCode.
+ uint32_t _code;
+
+ //! @brief Emit options.
+ uint8_t _emitOptions;
+ //! @brief Instruction flags.
+ uint8_t _instFlags;
+ //! @brief Operands count.
+ uint8_t _operandsCount;
+ //! @brief Variables count.
+ uint8_t _variablesCount;
+
+ //! @brief Operands.
+ Operand *_operands;
+};
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_CORE_COMPILERITEM_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/context.cpp
@@ -1,1 +1,92 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/assembler.h"
+#include "../core/context.h"
+#include "../core/defs.h"
+#include "../core/memorymanager.h"
+#include "../core/memorymarker.h"
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [AsmJit::Context - Construction / Destruction]
+// ============================================================================
+
+Context::Context() { }
+Context::~Context() { }
+
+// ============================================================================
+// [AsmJit::JitContext - Construction / Destruction]
+// ============================================================================
+
+JitContext::JitContext() : _memoryManager(nullptr), _memoryMarker(nullptr), _allocType(kMemAllocFreeable)
+{
+}
+
+JitContext::~JitContext()
+{
+}
+
+// ============================================================================
+// [AsmJit::JitContext - Generate]
+// ============================================================================
+
+uint32_t JitContext::generate(void **dest, Assembler *assembler)
+{
+ // Disallow empty code generation.
+ size_t codeSize = assembler->getCodeSize();
+ if (!codeSize)
+ {
+ *dest = nullptr;
+ return kErrorNoFunction;
+ }
+
+ // Switch to global memory manager if not provided.
+ MemoryManager *memmgr = this->getMemoryManager();
+
+ if (!memmgr)
+ memmgr = MemoryManager::getGlobal();
+
+ void *p = memmgr->alloc(codeSize, getAllocType());
+ if (!p)
+ {
+ *dest = nullptr;
+ return kErrorNoVirtualMemory;
+ }
+
+ // Relocate the code.
+ size_t relocatedSize = assembler->relocCode(p);
+
+ // Return unused memory to MemoryManager.
+ if (relocatedSize < codeSize)
+ memmgr->shrink(p, relocatedSize);
+
+ // Mark memory if MemoryMarker provided.
+ if (this->_memoryMarker)
+ this->_memoryMarker->mark(p, relocatedSize);
+
+ // Return the code.
+ *dest = p;
+ return kErrorOk;
+}
+
+// ============================================================================
+// [AsmJit::JitContext - GetGlobal]
+// ============================================================================
+
+JitContext *JitContext::getGlobal()
+{
+ static JitContext global;
+ return &global;
+}
+
+} // AsmJit namespace
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/context.h
@@ -1,1 +1,141 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+// [Guard]
+#ifndef _ASMJIT_CORE_CONTEXT_H
+#define _ASMJIT_CORE_CONTEXT_H
+
+// [Dependencies - AsmJit]
+#include "../core/build.h"
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [Forward Declarations]
+// ============================================================================
+
+struct Assembler;
+struct MemoryManager;
+struct MemoryMarker;
+
+// ============================================================================
+// [AsmJit::Context]
+// ============================================================================
+
+//! @brief Class for changing behavior of code generated by @ref Assembler and
+//! @ref Compiler.
+struct Context
+{
+ ASMJIT_NO_COPY(Context)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a @c Context instance.
+ ASMJIT_API Context();
+ //! @brief Destroy the @c Context instance.
+ ASMJIT_API virtual ~Context();
+
+ // --------------------------------------------------------------------------
+ // [Interface]
+ // --------------------------------------------------------------------------
+
+ //! @brief Allocate memory for code generated in @a assembler and reloc it
+ //! to target location.
+ //!
+ //! This method is universal allowing any pre-process / post-process work
+ //! with code generated by @c Assembler or @c Compiler. Because @c Compiler
+ //! always uses @c Assembler it's allowed to access only the @c Assembler
+ //! instance.
+ //!
+ //! This method is always last step when using code generation. You can use
+ //! it to allocate memory for JIT code, saving code to remote process or a
+ //! shared library.
+ //!
+ //! @retrurn Error value, see @c kError.
+ virtual uint32_t generate(void **dest, Assembler *assembler) = 0;
+};
+
+// ============================================================================
+// [AsmJit::JitContext]
+// ============================================================================
+
+struct JitContext : public Context
+{
+ ASMJIT_NO_COPY(JitContext)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a @c JitContext instance.
+ ASMJIT_API JitContext();
+ //! @brief Destroy the @c JitContext instance.
+ ASMJIT_API virtual ~JitContext();
+
+ // --------------------------------------------------------------------------
+ // [Memory Manager and Alloc Type]
+ // --------------------------------------------------------------------------
+
+ // Note: These members can be ignored by all derived classes. They are here
+ // only to privide default implementation. All other implementations (remote
+ // code patching or making dynamic loadable libraries/executables) ignore
+ // members accessed by these accessors.
+
+ //! @brief Get the @c MemoryManager instance.
+ MemoryManager *getMemoryManager() const { return this->_memoryManager; }
+
+ //! @brief Set the @c MemoryManager instance.
+ void setMemoryManager(MemoryManager *memoryManager) { this->_memoryManager = memoryManager; }
+
+ //! @brief Get the type of allocation.
+ uint32_t getAllocType() const { return this->_allocType; }
+
+ //! @brief Set the type of allocation.
+ void setAllocType(uint32_t allocType) { this->_allocType = allocType; }
+
+ // --------------------------------------------------------------------------
+ // [Memory Marker]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get the @c MemoryMarker instance.
+ MemoryMarker *getMemoryMarker() const { return this->_memoryMarker; }
+
+ //! @brief Set the @c MemoryMarker instance.
+ void setMemoryMarker(MemoryMarker *memoryMarker) { this->_memoryMarker = memoryMarker; }
+
+ // --------------------------------------------------------------------------
+ // [Interface]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual uint32_t generate(void **dest, Assembler *assembler);
+
+ // --------------------------------------------------------------------------
+ // [Statics]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API static JitContext *getGlobal();
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Memory manager.
+ MemoryManager *_memoryManager;
+ //! @brief Memory marker.
+ MemoryMarker *_memoryMarker;
+
+ //! @brief Type of allocation.
+ uint32_t _allocType;
+};
+
+} // AsmJit namespace
+
+// [Guard]
+#endif // _ASMJIT_CORE_CONTEXT_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/cpuinfo.cpp
@@ -1,1 +1,90 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/cpuinfo.h"
+
+#if defined(ASMJIT_X86) || defined(ASMJIT_X64)
+# include "../x86/x86cpuinfo.h"
+#else
+// ?
+#endif // ASMJIT_X86 || ASMJIT_X64
+
+// [Dependencies - Windows]
+#ifdef ASMJIT_WINDOWS
+# include "windowsh_wrapper.h"
+#endif // ASMJIT_WINDOWS
+
+// [Dependencies - Posix]
+#ifdef ASMJIT_POSIX
+# include <errno.h>
+# include <sys/statvfs.h>
+# include <sys/utsname.h>
+# include <unistd.h>
+#endif // ASMJIT_POSIX
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [AsmJit::CpuInfo - DetectNumberOfProcessors]
+// ============================================================================
+
+uint32_t CpuInfo::detectNumberOfProcessors()
+{
+#ifdef ASMJIT_WINDOWS
+ SYSTEM_INFO info;
+ ::GetSystemInfo(&info);
+ return info.dwNumberOfProcessors;
+#elif defined(ASMJIT_POSIX) && defined(_SC_NPROCESSORS_ONLN)
+ // It seems that sysconf returns the number of "logical" processors on both
+ // mac and linux. So we get the number of "online logical" processors.
+ long res = ::sysconf(_SC_NPROCESSORS_ONLN);
+ if (res == -1)
+ return 1;
+
+ return static_cast<uint32_t>(res);
+#else
+ return 1;
+#endif
+}
+
+// ============================================================================
+// [AsmJit::CpuInfo - GetGlobal]
+// ============================================================================
+
+#if defined(ASMJIT_X86) || defined(ASMJIT_X64)
+struct InitializedCpuInfo : public X86CpuInfo
+{
+ InitializedCpuInfo() : X86CpuInfo()
+ {
+ x86CpuDetect(this);
+ }
+};
+#else
+# error "AsmJit::CpuInfo - Unsupported CPU or compiler."
+#endif // ASMJIT_X86 || ASMJIT_X64
+
+const CpuInfo *CpuInfo::getGlobal()
+{
+#if defined(ASMJIT_X86) || defined(ASMJIT_X64)
+ static InitializedCpuInfo cpuInfo;
+#else
+# error "AsmJit::CpuInfo - Unsupported CPU or compiler."
+#endif // ASMJIT_X86 || ASMJIT_X64
+ return &cpuInfo;
+}
+
+} // AsmJit
+
+// [Api-End]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/cpuinfo.h
@@ -1,1 +1,112 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+// [Guard]
+#ifndef _ASMJIT_CORE_CPUINFO_H
+#define _ASMJIT_CORE_CPUINFO_H
+
+// [Dependencies - AsmJit]
+#include "../core/build.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+//! @addtogroup AsmJit_Core
+//! @{
+
+// ============================================================================
+// [AsmJit::CpuInfo]
+// ============================================================================
+
+//! @brief Informations about host cpu.
+struct CpuInfo
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ CpuInfo(uint32_t size = sizeof(CpuInfo)) : _size(size) { }
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get CPU vendor string.
+ const char *getVendorString() const { return this->_vendorString; }
+ //! @brief Get CPU brand string.
+ const char *getBrandString() const { return this->_brandString; }
+
+ //! @brief Get CPU vendor ID.
+ uint32_t getVendorId() const { return this->_vendorId; }
+ //! @brief Get CPU family ID.
+ uint32_t getFamily() const { return this->_family; }
+ //! @brief Get CPU model ID.
+ uint32_t getModel() const { return this->_model; }
+ //! @brief Get CPU stepping.
+ uint32_t getStepping() const { return this->_stepping; }
+ //! @brief Get CPU count.
+ uint32_t getNumberOfProcessors() const { return this->_numberOfProcessors; }
+ //! @brief Get CPU features.
+ uint32_t getFeatures() const { return this->_features; }
+ //! @brief Get CPU bugs.
+ uint32_t getBugs() const { return this->_bugs; }
+
+ //! @brief Get whether CPU has feature @a feature.
+ bool hasFeature(uint32_t feature) { return !!(this->_features & feature); }
+ //! @brief Get whether CPU has bug @a bug.
+ bool hasBug(uint32_t bug) { return !!(this->_bugs & bug); }
+
+ // --------------------------------------------------------------------------
+ // [Statics]
+ // --------------------------------------------------------------------------
+
+ //! @brief Detect number of processors.
+ ASMJIT_API static uint32_t detectNumberOfProcessors();
+
+ //! @brief Get global instance of @ref CpuInfo.
+ ASMJIT_API static const CpuInfo *getGlobal();
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Size of CpuInfo structure (in bytes).
+ uint32_t _size;
+
+ //! @brief Cpu short vendor string.
+ char _vendorString[16];
+ //! @brief Cpu long vendor string (brand).
+ char _brandString[64];
+
+ //! @brief Cpu vendor id (see @c AsmJit::CpuInfo::VendorId enum).
+ uint32_t _vendorId;
+ //! @brief Cpu family ID.
+ uint32_t _family;
+ //! @brief Cpu model ID.
+ uint32_t _model;
+ //! @brief Cpu stepping.
+ uint32_t _stepping;
+ //! @brief Number of processors or cores.
+ uint32_t _numberOfProcessors;
+ //! @brief Cpu features bitfield, see @c AsmJit::CpuInfo::Feature enum).
+ uint32_t _features;
+ //! @brief Cpu bugs bitfield, see @c AsmJit::CpuInfo::Bug enum).
+ uint32_t _bugs;
+};
+
+//! @}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_CORE_CPUINFO_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/defs.cpp
@@ -1,1 +1,59 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/defs.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [AsmJit::getErrorString]
+// ============================================================================
+
+const char *getErrorString(uint32_t error)
+{
+ static const char *errorMessage[] =
+ {
+ "No error",
+
+ "No heap memory",
+ "No virtual memory",
+
+ "Unknown instruction",
+ "Illegal instruction",
+ "Illegal addressing",
+ "Illegal short jump",
+
+ "No function defined",
+ "Incomplete function",
+
+ "Not enough registers",
+ "Registers overlap",
+
+ "Incompatible argument",
+ "Incompatible return value",
+
+ "Unknown error"
+ };
+
+ // Saturate error code to be able to use errorMessage[].
+ if (error > kErrorCount)
+ error = kErrorCount;
+
+ return errorMessage[error];
+}
+
+} // AsmJit
+
+// [Api-End]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/defs.h
@@ -1,1 +1,600 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_CORE_DEFS_H
+#define _ASMJIT_CORE_DEFS_H
+
+// [Dependencies - AsmJit]
+#include "../core/build.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+//! @addtogroup AsmJit_Core
+//! @{
+
+// ============================================================================
+// [AsmJit::Global]
+// ============================================================================
+
+enum
+{
+ //! @brief Invalid operand identifier.
+ kInvalidValue = 0xFFFFFFFFU,
+ //! @brief Minimum reserved bytes in @ref Buffer.
+ kBufferGrow = 32U
+};
+
+const size_t kInvalidSize = static_cast<size_t>(-1);
+
+// ============================================================================
+// [AsmJit::kStringBuilderOpType]
+// ============================================================================
+
+//! @brief String builder operation.
+enum kStringBuilderOpType
+{
+ //! @brief Replace the current content by a given content.
+ kStringBuilderOpSet = 0,
+ //! @brief Append a given content to the current content.
+ kStringBuilderOpAppend = 1
+};
+
+// ============================================================================
+// [AsmJit::kStringBuilderNumType]
+// ============================================================================
+
+enum kStringBuilderNumFlags
+{
+ kStringBuilderNumShowSign = 1U,
+ kStringBuilderNumShowSpace = 1U << 1,
+ kStringBuilderNumAlternate = 1U << 2,
+ kStringBuilderNumSigned = 1U << 31
+};
+
+// ============================================================================
+// [AsmJit::kLoggerOption]
+// ============================================================================
+
+enum kLoggerFlag
+{
+ //! @brief Whether logger is enabled or disabled.
+ //!
+ //! Default @c true.
+ kLoggerIsEnabled = 0x00000001,
+
+ //! @brief Whether logger is enabled and can be used.
+ //!
+ //! This value can be set by inherited classes to inform @c Logger that
+ //! assigned stream (or something that can log output) is invalid. If
+ //! @c _used is false it means that there is no logging output and AsmJit
+ //! shouldn't use this logger (because all messages will be lost).
+ //!
+ //! This is designed only to optimize cases that logger exists, but its
+ //! configured not to output messages. The API inside Logging and AsmJit
+ //! should only check this value when needed. The API outside AsmJit should
+ //! check only whether logging is @c _enabled.
+ //!
+ //! Default @c true.
+ kLoggerIsUsed = 0x00000002,
+
+ //! @brief Whether to output instructions also in binary form.
+ kLoggerOutputBinary = 0x00000010,
+ //! @brief Whether to output immediates as hexadecimal numbers.
+ kLoggerOutputHexImmediate = 0x00000020,
+ //! @brief Whether to output displacements as hexadecimal numbers.
+ kLoggerOutputHexDisplacement = 0x00000040
+};
+
+// ============================================================================
+// [AsmJit::kCpu]
+// ============================================================================
+
+//! @brief Cpu vendor IDs.
+//!
+//! Cpu vendor IDs are specific for AsmJit library. Vendor ID is not directly
+//! read from cpuid result, instead it's based on CPU vendor string.
+enum kCpu
+{
+ //! @brief Unknown CPU vendor.
+ kCpuUnknown = 0,
+
+ //! @brief Intel CPU vendor.
+ kCpuIntel = 1,
+ //! @brief AMD CPU vendor.
+ kCpuAmd = 2,
+ //! @brief National Semiconductor CPU vendor (applies also to Cyrix processors).
+ kCpuNSM = 3,
+ //! @brief Transmeta CPU vendor.
+ kCpuTransmeta = 4,
+ //! @brief VIA CPU vendor.
+ kCpuVia = 5
+};
+
+// ============================================================================
+// [AsmJit::kMemAllocType]
+// ============================================================================
+
+//! @brief Types of allocation used by @c AsmJit::MemoryManager::alloc() method.
+enum kMemAllocType
+{
+ //! @brief Allocate memory that can be freed by @c AsmJit::MemoryManager::free()
+ //! method.
+ kMemAllocFreeable = 0,
+ //! @brief Allocate permanent memory that will be never freed.
+ kMemAllocPermanent = 1
+};
+
+// ============================================================================
+// [AsmJit::kOperandType]
+// ============================================================================
+
+//! @brief Operand types that can be encoded in @c Op operand.
+enum kOperandType
+{
+ //! @brief Operand is none, used only internally (not initialized Operand).
+ //!
+ //! This operand is not valid.
+ kOperandNone = 0x00,
+ //! @brief Operand is label.
+ kOperandLabel = 0x01,
+ //! @brief Operand is register.
+ kOperandReg = 0x02,
+ //! @brief Operand is variable.
+ kOperandVar = 0x04,
+ //! @brief Operand is memory.
+ kOperandMem = 0x08,
+ //! @brief Operand is immediate.
+ kOperandImm = 0x10
+};
+
+// ============================================================================
+// [AsmJit::kOperandMemType]
+// ============================================================================
+
+//! @brief Type of memory operand.
+enum kOperandMemType
+{
+ //! @brief Operand is combination of register(s) and displacement (native).
+ kOperandMemNative = 0,
+ //! @brief Operand is label.
+ kOperandMemLabel = 1,
+ //! @brief Operand is absolute memory location (supported mainly in 32-bit mode)
+ kOperandMemAbsolute = 2,
+};
+
+// ============================================================================
+// [AsmJit::kOperandId]
+// ============================================================================
+
+//! @brief Operand ID masks used to determine the operand type.
+enum kOperandId
+{
+ //! @brief Operand id type mask (part used for operand type).
+ kOperandIdTypeMask = 0xC0000000,
+ //! @brief Label operand mark id.
+ kOperandIdTypeLabel = 0x40000000,
+ //! @brief Variable operand mark id.
+ kOperandIdTypeVar = 0x80000000,
+
+ //! @brief Operand id value mask (part used for IDs).
+ kOperandIdValueMask = 0x3FFFFFFF
+};
+
+// ============================================================================
+// [AsmJit::kRegType / kRegIndex]
+// ============================================================================
+
+enum
+{
+ //! @brief Mask for register type.
+ kRegTypeMask = 0xFF00,
+
+ //! @brief Mask for register code (index).
+ kRegIndexMask = 0xFF,
+ //! @brief Invalid register index.
+ kRegIndexInvalid = 0xFF
+};
+
+// ============================================================================
+// [AsmJit::kCondHint]
+// ============================================================================
+
+//! @brief Condition hint.
+enum kCondHint
+{
+ //! @brief No hint.
+ kCondHintNone = 0x00,
+ //! @brief Condition is likely to be taken.
+ kCondHintLikely = 0x01,
+ //! @brief Condition is unlikely to be taken.
+ kCondHintUnlikely = 0x02
+};
+
+// ============================================================================
+// [AsmJit::kFuncAnonymous]
+// ============================================================================
+
+enum
+{
+ //! @brief Maximum allowed arguments per function declaration / call.
+ kFuncArgsMax = 32,
+ //! @brief Invalid stack offset in function or function parameter.
+ kFuncStackInvalid = -1
+};
+
+// ============================================================================
+// [AsmJit::kFuncConv]
+// ============================================================================
+
+enum kFuncConv
+{
+ //! @brief Calling convention is invalid (can't be used).
+ kFuncConvNone = 0
+};
+
+// ============================================================================
+// [AsmJit::kFuncHint]
+// ============================================================================
+
+//! @brief Function hints.
+enum kFuncHint
+{
+ //! @brief Make naked function (without using ebp/erp in prolog / epilog).
+ kFuncHintNaked = 0
+};
+
+// ============================================================================
+// [AsmJit::kFuncFlags]
+// ============================================================================
+
+//! @brief Function flags.
+enum kFuncFlags
+{
+ //! @brief Whether another function is called from this function.
+ //!
+ //! If another function is called from this function, it's needed to prepare
+ //! stack for it. If this member is true then it's likely that true will be
+ //! also @c _isEspAdjusted one.
+ kFuncFlagIsCaller = 1U,
+
+ //! @brief Whether the function is finished using @c Compiler::endFunc().
+ kFuncFlagIsFinished = 1U << 1,
+
+ //! @brief Whether the function is using naked (minimal) prolog / epilog.
+ kFuncFlagIsNaked = 1U << 2
+};
+
+// ============================================================================
+// [AsmJit::kFuncArgsDirection]
+// ============================================================================
+
+//! @brief Function arguments direction.
+enum kFuncArgsDirection
+{
+ //! @brief Arguments are passed left to right.
+ //!
+ //! This arguments direction is unusual to C programming, it's used by pascal
+ //! compilers and in some calling conventions by Borland compiler).
+ kFuncArgsLTR = 0,
+ //! @brief Arguments are passed right ro left
+ //!
+ //! This is default argument direction in C programming.
+ kFuncArgsRTL = 1
+};
+
+// ============================================================================
+// [AsmJit::kInstCode]
+// ============================================================================
+
+enum kInstCode
+{
+ //! @brief No instruction.
+ kInstNone = 0
+};
+
+// ============================================================================
+// [AsmJit::kVarAllocFlags]
+// ============================================================================
+
+//! @brief Variable alloc mode.
+enum kVarAllocFlags
+{
+ //! @brief Allocating variable to read only.
+ //!
+ //! Read only variables are used to optimize variable spilling. If variable
+ //! is some time ago deallocated and it's not marked as changed (so it was
+ //! all the life time read only) then spill is simply NOP (no mov instruction
+ //! is generated to move it to it's home memory location).
+ kVarAllocRead = 0x01,
+ //! @brief Allocating variable to write only (overwrite).
+ //!
+ //! Overwriting means that if variable is in memory, there is no generated
+ //! instruction to move variable from memory to register, because that
+ //! register will be overwritten by next instruction. This is used as a
+ //! simple optimization to improve generated code by @c Compiler.
+ kVarAllocWrite = 0x02,
+ //! @brief Allocating variable to read / write.
+ //!
+ //! Variable allocated for read / write is marked as changed. This means that
+ //! if variable must be later spilled into memory, mov (or similar)
+ //! instruction will be generated.
+ kVarAllocReadWrite = 0x03,
+
+ //! @brief Variable can be allocated in register.
+ kVarAllocRegister = 0x04,
+ //! @brief Variable can be allocated only to a special register.
+ kVarAllocSpecial = 0x08,
+
+ //! @brief Variable can be allocated in memory.
+ kVarAllocMem = 0x10,
+
+ //! @brief Unuse the variable after use.
+ kVarAllocUnuseAfterUse = 0x20
+};
+
+// ============================================================================
+// [AsmJit::kVarHint]
+// ============================================================================
+
+//! @brief Variable hint (used by @ref Compiler).
+//!
+//! @sa @ref Compiler.
+enum kVarHint
+{
+ //! @brief Alloc variable.
+ kVarHintAlloc = 0,
+ //! @brief Spill variable.
+ kVarHintSpill = 1,
+ //! @brief Save variable if modified.
+ kVarHintSave = 2,
+ //! @brief Save variable if modified and mark it as unused.
+ kVarHintSaveAndUnuse = 3,
+ //! @brief Mark variable as unused.
+ kVarHintUnuse = 4
+};
+
+// ============================================================================
+// [AsmJit::kVarPolicy]
+// ============================================================================
+
+//! @brief Variable allocation method.
+//!
+//! Variable allocation method is used by compiler and it means if compiler
+//! should first allocate preserved registers or not. Preserved registers are
+//! registers that must be saved / restored by generated function.
+//!
+//! This option is for people who are calling C/C++ functions from JIT code so
+//! Compiler can recude generating push/pop sequences before and after call,
+//! respectively.
+enum kVarPolicy
+{
+ //! @brief Allocate preserved registers first.
+ kVarPolicyPreservedFirst = 0,
+ //! @brief Allocate preserved registers last (default).
+ kVarPolicyPreservedLast = 1
+};
+
+// ============================================================================
+// [AsmJit::kVarState]
+// ============================================================================
+
+//! @brief State of variable.
+//!
+//! @note State of variable is used only during make process and it's not
+//! visible to the developer.
+enum kVarState
+{
+ //! @brief Variable is currently not used.
+ kVarStateUnused = 0,
+ //! @brief Variable is in register.
+ //!
+ //! Variable is currently allocated in register.
+ kVarStateReg = 1,
+ //! @brief Variable is in memory location or spilled.
+ //!
+ //! Variable was spilled from register to memory or variable is used for
+ //! memory only storage.
+ kVarStateMem = 2
+};
+
+// ============================================================================
+// [AsmJit::kVarType]
+// ============================================================================
+
+enum kVarType
+{
+ //! @brief Invalid variable type.
+ kVarTypeInvalid = 0xFF
+};
+
+// ============================================================================
+// [AsmJit::kScale]
+// ============================================================================
+
+//! @brief Scale which can be used for addressing (it the target instruction
+//! supports it).
+//!
+//! See @c Op and addressing methods like @c byte_ptr(), @c word_ptr(),
+//! @c dword_ptr(), etc...
+enum kScale
+{
+ //! @brief No scale.
+ kScaleNone = 0,
+ //! @brief Scale 2 times (same as shifting to left by 1).
+ kScale2Times = 1,
+ //! @brief Scale 4 times (same as shifting to left by 2).
+ kScale4Times = 2,
+ //! @brief Scale 8 times (same as shifting to left by 3).
+ kScale8Times = 3
+};
+
+// ============================================================================
+// [AsmJit::kSize]
+// ============================================================================
+
+//! @brief Size of registers and pointers.
+enum kSize
+{
+ //! @brief 1 byte size.
+ kSizeByte = 1,
+ //! @brief 2 bytes size.
+ kSizeWord = 2,
+ //! @brief 4 bytes size.
+ kSizeDWord = 4,
+ //! @brief 8 bytes size.
+ kSizeQWord = 8,
+ //! @brief 10 bytes size.
+ kSizeTWord = 10,
+ //! @brief 16 bytes size.
+ kSizeDQWord = 16
+};
+
+// ============================================================================
+// [AsmJit::kRelocMode]
+// ============================================================================
+
+enum kRelocMode
+{
+ kRelocAbsToAbs = 0,
+ kRelocRelToAbs = 1,
+ kRelocAbsToRel = 2,
+ kRelocTrampoline = 3
+};
+
+// ============================================================================
+// [AsmJit::kCompilerItem]
+// ============================================================================
+
+//! @brief Type of @ref CompilerItem.
+//!
+//! Each @c CompilerItem contains information about its type. Compiler can
+//! optimize instruction stream by analyzing items and each type is hint
+//! for it. The most used/serialized items are instructions
+//! (@c kCompilerItemInst).
+enum kCompilerItem
+{
+ //! @brief Invalid item (can't be used).
+ kCompilerItemNone = 0,
+ //! @brief Item is mark, see @ref CompilerMark.
+ kCompilerItemMark,
+ //! @brief Item is comment, see @ref CompilerComment.
+ kCompilerItemComment,
+ //! @brief Item is embedded data, see @ref CompilerEmbed.
+ kCompilerItemEmbed,
+ //! @brief Item is .align directive, see @ref CompilerAlign.
+ kCompilerItemAlign,
+ //! @brief Item is variable hint (alloc, spill, use, unuse), see @ref CompilerHint.
+ kCompilerItemHint,
+ //! @brief Item is instruction, see @ref CompilerInst.
+ kCompilerItemInst,
+ //! @brief Item is target, see @ref CompilerTarget.
+ kCompilerItemTarget,
+ //! @brief Item is function call, see @ref CompilerFuncCall.
+ kCompilerItemFuncCall,
+ //! @brief Item is function declaration, see @ref CompilerFuncDecl.
+ kCompilerItemFuncDecl,
+ //! @brief Item is an end of the function, see @ref CompilerFuncEnd.
+ kCompilerItemFuncEnd,
+ //! @brief Item is function return, see @ref CompilerFuncRet.
+ kCompilerItemFuncRet
+};
+
+// ============================================================================
+// [AsmJit::kError]
+// ============================================================================
+
+//! @brief Error codes.
+enum kError
+{
+ //! @brief No error (success).
+ //!
+ //! This is default state and state you want.
+ kErrorOk = 0,
+
+ //! @brief Memory allocation error (@c ASMJIT_MALLOC returned @c NULL).
+ kErrorNoHeapMemory = 1,
+ //! @brief Virtual memory allocation error (@c VirtualMemory returned @c NULL).
+ kErrorNoVirtualMemory = 2,
+
+ //! @brief Unknown instruction. This happens only if instruction code is
+ //! out of bounds. Shouldn't happen.
+ kErrorUnknownInstruction = 3,
+ //! @brief Illegal instruction, usually generated by AsmJit::Assembler
+ //! class when emitting instruction opcode. If this error is generated the
+ //! target buffer is not affected by this invalid instruction.
+ //!
+ //! You can also get this error code if you are under x64 (64-bit x86) and
+ //! you tried to decode instruction using AH, BH, CH or DH register with REX
+ //! prefix. These registers can't be accessed if REX prefix is used and AsmJit
+ //! didn't check for this situation in intrinsics (@c Compiler takes care of
+ //! this and rearrange registers if needed).
+ //!
+ //! Examples that will raise @c kErrorIllegalInstruction error (a is
+ //! @c Assembler instance):
+ //!
+ //! @code
+ //! a.mov(dword_ptr(eax), al); // Invalid address size.
+ //! a.mov(byte_ptr(r10), ah); // Undecodable instruction (AH used with r10
+ //! // which can be encoded only using REX prefix)
+ //! @endcode
+ //!
+ //! @note In debug mode you get assertion failure instead of setting error
+ //! code.
+ kErrorIllegalInstruction = 4,
+ //! @brief Illegal addressing used (unencodable).
+ kErrorIllegalAddressing = 5,
+ //! @brief Short jump instruction used, but displacement is out of bounds.
+ kErrorIllegalShortJump = 6,
+
+ //! @brief No function defined.
+ kErrorNoFunction = 7,
+ //! @brief Function generation is not finished by using @c Compiler::endFunc()
+ //! or something bad happened during generation related to function. This can
+ //! be missing compiler item, etc...
+ kErrorIncompleteFunction = 8,
+
+ //! @brief Compiler can't allocate registers, because all of them are used.
+ //!
+ //! @note AsmJit is able to spill registers so this error really shouldn't
+ //! happen unless all registers have priority 0 (which means never spill).
+ kErrorNoRegisters = 9,
+ //! @brief Compiler can't allocate one register to multiple destinations.
+ //!
+ //! This error can only happen using special instructions like cmpxchg8b and
+ //! others where there are more destination operands (implicit).
+ kErrorOverlappedRegisters = 10,
+
+ //! @brief Tried to call function using incompatible argument.
+ kErrorIncompatibleArgumentType = 11,
+ //! @brief Incompatible return value.
+ kErrorIncompatibleReturnType = 12,
+
+ //! @brief Count of error codes by AsmJit. Can grow in future.
+ kErrorCount
+};
+
+// ============================================================================
+// [AsmJit::API]
+// ============================================================================
+
+//! @brief Translates error code (see @c kError) into text representation.
+ASMJIT_API const char *getErrorString(uint32_t error);
+
+//! @}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_CORE_DEFS_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/func.h
@@ -1,1 +1,455 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_CORE_FUNC_H
+#define _ASMJIT_CORE_FUNC_H
+
+// [Dependencies - AsmJit]
+#include "../core/assert.h"
+#include "../core/defs.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [AsmJit::TypeId]
+// ============================================================================
+
+#ifdef ASMJIT_HAS_PARTIAL_TEMPLATE_SPECIALIZATION
+#define ASMJIT_DECLARE_TYPE_CORE(_PtrId_) \
+ template<typename T> struct TypeId \
+ { \
+ enum \
+ { \
+ Id = static_cast<int>(::AsmJit::kVarTypeInvalid) \
+ }; \
+ }; \
+ \
+ template<typename T> struct TypeId<T *> { enum { Id = _PtrId_ }; }
+#else
+// Code without partial template specialization is a bit complex. We need to
+// determine whether the size of the return value of this function is equal
+// to sizeof(char) or sizeof(void*). Any sizeof() can be used to distinguish
+// between these two, but these are commonly used in other libraries as well.
+template<typename T> char TypeId_NoPtiHelper(T *(*)());
+// And specialization.
+void *TypeId_NoPtiHelper(...);
+
+#define ASMJIT_DECLARE_TYPE_CORE(_PtrId_) \
+ template<typename T> struct TypeId \
+ { \
+ enum \
+ { \
+ Id = (sizeof(::AsmJit::TypeId_NoPtiHelper((T (*)())0) ) == sizeof(char) ? static_cast<int>(_PtrId_) : static_cast<int>(::AsmJit::kVarTypeInvalid)) \
+ }; \
+ }
+#endif // ASMJIT_HAS_PARTIAL_TEMPLATE_SPECIALIZATION
+
+//! @brief Declare C/C++ type-id mapped to @c AsmJit::kX86VarType.
+#define ASMJIT_DECLARE_TYPE_ID(_T_, _Id_) template<> struct TypeId<_T_> { enum { Id = _Id_ }; }
+
+// ============================================================================
+// [AsmJit::FuncArg]
+// ============================================================================
+
+//! @brief Function argument translated from @ref FuncPrototype.
+struct FuncArg
+{
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ uint32_t getVarType() const { return this->_varType; }
+
+ uint32_t getRegIndex() const { return this->_regIndex; }
+
+ bool hasRegIndex() const { return this->_regIndex != kRegIndexInvalid; }
+
+ int32_t getStackOffset() const { return static_cast<int32_t>(this->_stackOffset); }
+
+ bool hasStackOffset() const { return this->_stackOffset != kFuncStackInvalid; }
+
+ //! @brief Get whether the argument is assigned, for private use only.
+ bool isAssigned() const { return (this->_regIndex != kRegIndexInvalid) | (this->_stackOffset != kFuncStackInvalid); }
+
+ // --------------------------------------------------------------------------
+ // [Reset]
+ // --------------------------------------------------------------------------
+
+ //! @brief Reset the function argument to "unassigned state".
+ void reset() { this->_packed = 0xFFFFFFFF; }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ union
+ {
+ struct
+ {
+ //! @brief Variable type, see @c kVarType.
+ uint8_t _varType;
+ //! @brief Register index is argument is passed through register.
+ uint8_t _regIndex;
+ //! @brief Stack offset if argument is passed through stack.
+ int16_t _stackOffset;
+ };
+
+ //! @brief All members packed into single 32-bit integer.
+ uint32_t _packed;
+ };
+};
+
+// ============================================================================
+// [AsmJit::FuncPrototype]
+// ============================================================================
+
+//! @brief Function prototype.
+//!
+//! Function prototype contains information about function return type, count
+//! of arguments and their types. Function definition is low level structure
+//! which doesn't contain platform or calling convention specific information.
+struct FuncPrototype
+{
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get function return value.
+ uint32_t getReturnType() const { return this->_returnType; }
+
+ //! @brief Get count of function arguments.
+ uint32_t getArgumentsCount() const { return this->_argumentsCount; }
+
+ //! @brief Get argument at index @a id.
+ uint32_t getArgument(uint32_t id) const
+ {
+ ASMJIT_ASSERT(id < this->_argumentsCount);
+ return this->_arguments[id];
+ }
+
+ //! @brief Get function arguments' IDs.
+ const uint32_t *getArguments() const { return this->_arguments; }
+
+ //! @brief Set function definition - return type and arguments.
+ void _setPrototype(uint32_t returnType, const uint32_t *arguments, uint32_t argumentsCount)
+ {
+ this->_returnType = returnType;
+ this->_arguments = arguments;
+ this->_argumentsCount = argumentsCount;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ uint32_t _returnType;
+ uint32_t _argumentsCount;
+ const uint32_t *_arguments;
+};
+
+// ============================================================================
+// [AsmJit::FuncDecl]
+// ============================================================================
+
+//! @brief Function declaration.
+struct FuncDecl
+{
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get function return value or @ref kInvalidValue if it's void.
+ uint32_t getReturnType() const { return this->_returnType; }
+
+ //! @brief Get count of function arguments.
+ uint32_t getArgumentsCount() const { return this->_argumentsCount; }
+
+ //! @brief Get function arguments array.
+ FuncArg *getArguments() { return this->_arguments; }
+
+ //! @brief Get function arguments array (const).
+ const FuncArg *getArguments() const { return this->_arguments; }
+
+ //! @brief Get function argument at index @a index.
+ FuncArg &getArgument(size_t index)
+ {
+ ASMJIT_ASSERT(index < static_cast<size_t>(this->_argumentsCount));
+ return this->_arguments[index];
+ }
+
+ //! @brief Get function argument at index @a index.
+ const FuncArg &getArgument(size_t index) const
+ {
+ ASMJIT_ASSERT(index < static_cast<size_t>(this->_argumentsCount));
+ return this->_arguments[index];
+ }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Function return type.
+ uint8_t _returnType;
+ //! @brief Count of arguments (in @c _argumentsList).
+ uint8_t _argumentsCount;
+ //! @brief Reserved for future use (alignment).
+ uint8_t _reserved0[2];
+
+ //! @brief Function arguments array.
+ FuncArg _arguments[kFuncArgsMax];
+};
+
+// ============================================================================
+// [AsmJit::FuncBuilderX]
+// ============================================================================
+
+//! @brief Custom function builder for up to 32 function arguments.
+struct FuncBuilderX : public FuncPrototype
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ FuncBuilderX() { this->_setPrototype(kVarTypeInvalid, this->_argumentsData, 0); }
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ template<typename T> void setReturnTypeT() { this->setReturnTypeRaw(TypeId<ASMJIT_TYPE_TO_TYPE(T)>::Id); }
+
+ template<typename T> void setArgumentT(uint32_t id) { this->setArgumentRaw(id, TypeId<ASMJIT_TYPE_TO_TYPE(T)>::Id); }
+
+ template<typename T> void addArgumentT() { this->addArgumentRaw(TypeId<ASMJIT_TYPE_TO_TYPE(T)>::Id); }
+
+ void setReturnTypeRaw(uint32_t returnType) { this->_returnType = returnType; }
+
+ void setArgumentRaw(uint32_t id, uint32_t type)
+ {
+ ASMJIT_ASSERT(id < this->_argumentsCount);
+ this->_argumentsData[id] = type;
+ }
+
+ void addArgumentRaw(uint32_t type)
+ {
+ ASMJIT_ASSERT(this->_argumentsCount < kFuncArgsMax);
+ this->_argumentsData[this->_argumentsCount++] = type;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ uint32_t _argumentsData[kFuncArgsMax];
+};
+
+//! @brief Class used to build function without arguments.
+template<typename RET> struct FuncBuilder0 : public FuncPrototype
+{
+ FuncBuilder0()
+ {
+ this->_setPrototype(TypeId<ASMJIT_TYPE_TO_TYPE(RET)>::Id, nullptr, 0);
+ }
+};
+
+//! @brief Class used to build function with 1 argument.
+template<typename RET, typename P0> struct FuncBuilder1 : public FuncPrototype
+{
+ FuncBuilder1()
+ {
+ static const uint32_t arguments[] =
+ {
+ TypeId<ASMJIT_TYPE_TO_TYPE(P0)>::Id
+ };
+
+ this->_setPrototype(TypeId<ASMJIT_TYPE_TO_TYPE(RET)>::Id, arguments, ASMJIT_ARRAY_SIZE(arguments));
+ }
+};
+
+//! @brief Class used to build function with 2 arguments.
+template<typename RET, typename P0, typename P1> struct FuncBuilder2 : public FuncPrototype
+{
+ FuncBuilder2()
+ {
+ static const uint32_t arguments[] =
+ {
+ TypeId<ASMJIT_TYPE_TO_TYPE(P0)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P1)>::Id
+ };
+
+ this->_setPrototype(TypeId<ASMJIT_TYPE_TO_TYPE(RET)>::Id, arguments, ASMJIT_ARRAY_SIZE(arguments));
+ }
+};
+
+//! @brief Class used to build function with 3 arguments.
+template<typename RET, typename P0, typename P1, typename P2> struct FuncBuilder3 : public FuncPrototype
+{
+ FuncBuilder3()
+ {
+ static const uint32_t arguments[] =
+ {
+ TypeId<ASMJIT_TYPE_TO_TYPE(P0)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P1)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P2)>::Id
+ };
+
+ this->_setPrototype(TypeId<ASMJIT_TYPE_TO_TYPE(RET)>::Id, arguments, ASMJIT_ARRAY_SIZE(arguments));
+ }
+};
+
+//! @brief Class used to build function with 4 arguments.
+template<typename RET, typename P0, typename P1, typename P2, typename P3> struct FuncBuilder4 : public FuncPrototype
+{
+ FuncBuilder4()
+ {
+ static const uint32_t arguments[] =
+ {
+ TypeId<ASMJIT_TYPE_TO_TYPE(P0)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P1)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P2)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P3)>::Id
+ };
+
+ this->_setPrototype(TypeId<ASMJIT_TYPE_TO_TYPE(RET)>::Id, arguments, ASMJIT_ARRAY_SIZE(arguments));
+ }
+};
+
+//! @brief Class used to build function with 5 arguments.
+template<typename RET, typename P0, typename P1, typename P2, typename P3, typename P4> struct FuncBuilder5 : public FuncPrototype
+{
+ FuncBuilder5()
+ {
+ static const uint32_t arguments[] =
+ {
+ TypeId<ASMJIT_TYPE_TO_TYPE(P0)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P1)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P2)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P3)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P4)>::Id
+ };
+
+ this->_setPrototype(TypeId<ASMJIT_TYPE_TO_TYPE(RET)>::Id, arguments, ASMJIT_ARRAY_SIZE(arguments));
+ }
+};
+
+//! @brief Class used to build function with 6 arguments.
+template<typename RET, typename P0, typename P1, typename P2, typename P3, typename P4, typename P5> struct FuncBuilder6 : public FuncPrototype
+{
+ FuncBuilder6()
+ {
+ static const uint32_t arguments[] =
+ {
+ TypeId<ASMJIT_TYPE_TO_TYPE(P0)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P1)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P2)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P3)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P4)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P5)>::Id
+ };
+
+ this->_setPrototype(TypeId<ASMJIT_TYPE_TO_TYPE(RET)>::Id, arguments, ASMJIT_ARRAY_SIZE(arguments));
+ }
+};
+
+//! @brief Class used to build function with 7 arguments.
+template<typename RET, typename P0, typename P1, typename P2, typename P3, typename P4, typename P5, typename P6> struct FuncBuilder7 : public FuncPrototype
+{
+ FuncBuilder7()
+ {
+ static const uint32_t arguments[] =
+ {
+ TypeId<ASMJIT_TYPE_TO_TYPE(P0)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P1)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P2)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P3)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P4)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P5)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P6)>::Id
+ };
+
+ this->_setPrototype(TypeId<ASMJIT_TYPE_TO_TYPE(RET)>::Id, arguments, ASMJIT_ARRAY_SIZE(arguments));
+ }
+};
+
+//! @brief Class used to build function with 8 arguments.
+template<typename RET, typename P0, typename P1, typename P2, typename P3, typename P4, typename P5, typename P6, typename P7> struct FuncBuilder8 : public FuncPrototype
+{
+ FuncBuilder8()
+ {
+ static const uint32_t arguments[] =
+ {
+ TypeId<ASMJIT_TYPE_TO_TYPE(P0)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P1)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P2)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P3)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P4)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P5)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P6)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P7)>::Id
+ };
+
+ this->_setPrototype(TypeId<ASMJIT_TYPE_TO_TYPE(RET)>::Id, arguments, ASMJIT_ARRAY_SIZE(arguments));
+ }
+};
+
+//! @brief Class used to build function with 9 arguments.
+template<typename RET, typename P0, typename P1, typename P2, typename P3, typename P4, typename P5, typename P6, typename P7, typename P8> struct FuncBuilder9 : public FuncPrototype
+{
+ FuncBuilder9()
+ {
+ static const uint32_t arguments[] =
+ {
+ TypeId<ASMJIT_TYPE_TO_TYPE(P0)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P1)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P2)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P3)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P4)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P5)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P6)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P7)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P8)>::Id
+ };
+
+ this->_setPrototype(TypeId<ASMJIT_TYPE_TO_TYPE(RET)>::Id, arguments, ASMJIT_ARRAY_SIZE(arguments));
+ }
+};
+
+//! @brief Class used to build function with 10 arguments.
+template<typename RET, typename P0, typename P1, typename P2, typename P3, typename P4, typename P5, typename P6, typename P7, typename P8, typename P9> struct FuncBuilder10 : public FuncPrototype
+{
+ FuncBuilder10()
+ {
+ static const uint32_t arguments[] =
+ {
+ TypeId<ASMJIT_TYPE_TO_TYPE(P0)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P1)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P2)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P3)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P4)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P5)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P6)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P7)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P8)>::Id,
+ TypeId<ASMJIT_TYPE_TO_TYPE(P9)>::Id
+ };
+
+ this->_setPrototype(TypeId<ASMJIT_TYPE_TO_TYPE(RET)>::Id, arguments, ASMJIT_ARRAY_SIZE(arguments));
+ }
+};
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_CORE_FUNC_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/intutil.h
@@ -1,1 +1,257 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_CORE_INTUTIL_H
+#define _ASMJIT_CORE_INTUTIL_H
+
+// [Dependencies - AsmJit]
+#include "../core/assert.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+//! @addtogroup AsmJit_Core
+//! @{
+
+// ============================================================================
+// [AsmJit::I32FPUnion]
+// ============================================================================
+
+//! @internal
+//!
+//! @brief used to cast from float to 32-bit integer and vica versa.
+union I32FPUnion
+{
+ //! @brief 32-bit signed integer value.
+ int32_t i;
+ //! @brief 32-bit SP-FP value.
+ float f;
+};
+
+// ============================================================================
+// [AsmJit::I64FPUnion]
+// ============================================================================
+
+//! @internal
+//!
+//! @brief used to cast from double to 64-bit integer and vica versa.
+union I64FPUnion
+{
+ //! @brief 64-bit signed integer value.
+ int64_t i;
+ //! @brief 64-bit DP-FP value.
+ double f;
+};
+
+// ============================================================================
+// [AsmJit::IntUtil]
+// ============================================================================
+
+namespace IntUtil
+{
+ // --------------------------------------------------------------------------
+ // [Min/Max]
+ // --------------------------------------------------------------------------
+
+ // NOTE: Because some environments declare min() and max() as macros, we
+ // decided to use different name so we never collide.
+
+ template<typename T> inline T _min(const T &a, const T &b) { return a < b ? a : b; }
+ template<typename T> inline T _max(const T &a, const T &b) { return a > b ? a : b; }
+
+ // --------------------------------------------------------------------------
+ // [Limits]
+ // --------------------------------------------------------------------------
+
+ template<typename T> inline T maxValue() { return ~T(0); }
+
+ // --------------------------------------------------------------------------
+ // [IsInt / IsUInt]
+ // --------------------------------------------------------------------------
+
+ //! @brief Returns @c true if a given integer @a x is signed 8-bit integer
+ inline bool isInt8(intptr_t x) { return x >= -128 && x <= 127; }
+ //! @brief Returns @c true if a given integer @a x is unsigned 8-bit integer
+ inline bool isUInt8(intptr_t x) { return x >= 0 && x <= 255; }
+
+ //! @brief Returns @c true if a given integer @a x is signed 16-bit integer
+ inline bool isInt16(intptr_t x) { return x >= -32768 && x <= 32767; }
+ //! @brief Returns @c true if a given integer @a x is unsigned 16-bit integer
+ inline bool isUInt16(intptr_t x) { return x >= 0 && x <= 65535; }
+
+ //! @brief Returns @c true if a given integer @a x is signed 16-bit integer
+ inline bool isInt32(intptr_t x)
+ {
+#ifdef ASMJIT_X86
+ return true;
+#else
+ return x >= ASMJIT_INT64_C(-2147483648) && x <= ASMJIT_INT64_C(2147483647);
+#endif
+ }
+ //! @brief Returns @c true if a given integer @a x is unsigned 16-bit integer
+ inline bool isUInt32(intptr_t x)
+ {
+#ifdef ASMJIT_X86
+ return x >= 0;
+#else
+ return x >= 0 && x <= ASMJIT_INT64_C(4294967295);
+#endif
+ }
+
+ // --------------------------------------------------------------------------
+ // [Masking]
+ // --------------------------------------------------------------------------
+
+ inline uint32_t maskFromIndex(uint32_t x)
+ {
+ ASMJIT_ASSERT(x < 32);
+ return 1U << x;
+ }
+
+ inline uint32_t maskUpToIndex(uint32_t x)
+ {
+ if (x >= 32)
+ return 0xFFFFFFFF;
+ else
+ return (1U << x) - 1;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Bits]
+ // --------------------------------------------------------------------------
+
+ // From http://graphics.stanford.edu/~seander/bithacks.html .
+ inline uint32_t bitCount(uint32_t x)
+ {
+ x -= (x >> 1) & 0x55555555U;
+ x = (x & 0x33333333U) + ((x >> 2) & 0x33333333U);
+ return (((x + (x >> 4)) & 0x0F0F0F0FU) * 0x01010101U) >> 24;
+ }
+
+ inline uint32_t findFirstBit(uint32_t mask)
+ {
+ for (uint32_t i = 0; i < sizeof(uint32_t) * 8; ++i, mask >>= 1)
+ if (mask & 0x1)
+ return i;
+
+ // kInvalidValue.
+ return 0xFFFFFFFF;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Alignment]
+ // --------------------------------------------------------------------------
+
+ template<typename T> inline bool isAligned(T base, T alignment)
+ {
+ return !(base % alignment);
+ }
+
+ //! @brief Align @a base to @a alignment.
+ template<typename T> inline T align(T base, T alignment)
+ {
+ return (base + (alignment - 1)) & ~(alignment - 1);
+ }
+
+ //! @brief Get delta required to align @a base to @a alignment.
+ template<typename T> inline T delta(T base, T alignment)
+ {
+ return align(base, alignment) - base;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Round]
+ // --------------------------------------------------------------------------
+
+ template<typename T> inline T roundUp(T base, T alignment)
+ {
+ T over = base % alignment;
+ return base + (over > 0 ? alignment - over : 0);
+ }
+
+ template<typename T> inline T roundUpToPowerOf2(T base)
+ {
+ // Implementation is from "Hacker's Delight" by Henry S. Warren, Jr.,
+ // figure 3-3, page 48, where the function is called clp2.
+ base -= 1;
+
+ // I'm trying to make this portable and MSVC strikes me the warning C4293:
+ // "Shift count negative or too big, undefined behavior"
+ // Fixing...
+#ifdef _MSC_VER
+# pragma warning(push)
+# pragma warning(disable: 4293)
+#endif // _MSC_VER
+
+ base |= base >> 1;
+ base |= base >> 2;
+ base |= base >> 4;
+
+ if (sizeof(T) >= 2)
+ base |= base >> 8;
+ if (sizeof(T) >= 4)
+ base |= base >> 16;
+ if (sizeof(T) >= 8)
+ base |= base >> 32;
+
+#ifdef _MSC_VER
+# pragma warning(pop)
+#endif // _MSC_VER
+
+ return base + 1;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Cast]
+ // --------------------------------------------------------------------------
+
+ //! @brief Binary cast from 32-bit integer to SP-FP value (@c float).
+ inline float int32AsFloat(int32_t i)
+ {
+ I32FPUnion u;
+ u.i = i;
+ return u.f;
+ }
+
+ //! @brief Binary cast SP-FP value (@c float) to 32-bit integer.
+ inline int32_t floatAsInt32(float f)
+ {
+ I32FPUnion u;
+ u.f = f;
+ return u.i;
+ }
+
+ //! @brief Binary cast from 64-bit integer to DP-FP value (@c double).
+ inline double int64AsDouble(int64_t i)
+ {
+ I64FPUnion u;
+ u.i = i;
+ return u.f;
+ }
+
+ //! @brief Binary cast from DP-FP value (@c double) to 64-bit integer.
+ inline int64_t doubleAsInt64(double f)
+ {
+ I64FPUnion u;
+ u.f = f;
+ return u.i;
+ }
+};
+
+//! @}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_CORE_INTUTIL_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/lock.h
@@ -1,1 +1,137 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+// [Guard]
+#ifndef _ASMJIT_CORE_LOCK_H
+#define _ASMJIT_CORE_LOCK_H
+
+// [Dependencies - AsmJit]
+#include "../core/build.h"
+
+// [Dependencies - Windows]
+#ifdef ASMJIT_WINDOWS
+# include "windowsh_wrapper.h"
+#endif // ASMJIT_WINDOWS
+
+// [Dependencies - Posix]
+#ifdef ASMJIT_POSIX
+# include <pthread.h>
+#endif // ASMJIT_POSIX
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+//! @addtogroup AsmJit_Core
+//! @{
+
+// ============================================================================
+// [AsmJit::Lock]
+// ============================================================================
+
+//! @brief Lock - used in thread-safe code for locking.
+struct Lock
+{
+ ASMJIT_NO_COPY(Lock)
+
+ // --------------------------------------------------------------------------
+ // [Windows]
+ // --------------------------------------------------------------------------
+
+#ifdef ASMJIT_WINDOWS
+ typedef CRITICAL_SECTION Handle;
+
+ //! @brief Create a new @ref Lock instance.
+ Lock() { InitializeCriticalSection(&this->_handle); }
+ //! @brief Destroy the @ref Lock instance.
+ ~Lock() { DeleteCriticalSection(&this->_handle); }
+
+ //! @brief Lock.
+ void lock() { EnterCriticalSection(&this->_handle); }
+ //! @brief Unlock.
+ void unlock() { LeaveCriticalSection(&this->_handle); }
+#endif // ASMJIT_WINDOWS
+
+ // --------------------------------------------------------------------------
+ // [Posix]
+ // --------------------------------------------------------------------------
+
+#ifdef ASMJIT_POSIX
+ typedef pthread_mutex_t Handle;
+
+ //! @brief Create a new @ref Lock instance.
+ Lock() { pthread_mutex_init(&this->_handle, nullptr); }
+ //! @brief Destroy the @ref Lock instance.
+ ~Lock() { pthread_mutex_destroy(&this->_handle); }
+
+ //! @brief Lock.
+ void lock() { pthread_mutex_lock(&this->_handle); }
+ //! @brief Unlock.
+ void unlock() { pthread_mutex_unlock(&this->_handle); }
+#endif // ASMJIT_POSIX
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get handle.
+ Handle &getHandle() { return this->_handle; }
+ //! @overload
+ const Handle &getHandle() const { return this->_handle; }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Handle.
+ Handle _handle;
+};
+
+// ============================================================================
+// [AsmJit::AutoLock]
+// ============================================================================
+
+//! @brief Scope auto locker.
+struct AutoLock
+{
+ ASMJIT_NO_COPY(AutoLock)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Locks @a target.
+ AutoLock(Lock &target) : _target(target)
+ {
+ this->_target.lock();
+ }
+
+ //! @brief Unlocks target.
+ ~AutoLock()
+ {
+ this->_target.unlock();
+ }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Pointer to target (lock).
+ Lock &_target;
+};
+
+//! @}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_CORE_LOCK_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/logger.cpp
@@ -1,1 +1,195 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/logger.h"
+
+// [Dependencies - C]
+#include <stdarg.h>
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [AsmJit::Logger - Construction / Destruction]
+// ============================================================================
+
+Logger::Logger() : _flags(kLoggerIsEnabled | kLoggerIsUsed)
+{
+ memset(this->_instructionPrefix, 0, ASMJIT_ARRAY_SIZE(this->_instructionPrefix));
+}
+
+Logger::~Logger()
+{
+}
+
+// ============================================================================
+// [AsmJit::Logger - Logging]
+// ============================================================================
+
+void Logger::logFormat(const char *fmt, ...)
+{
+ char buf[1024];
+
+ va_list ap;
+ va_start(ap, fmt);
+ size_t len = vsnprintf(buf, 1023, fmt, ap);
+ va_end(ap);
+
+ this->logString(buf, len);
+}
+
+// ============================================================================
+// [AsmJit::Logger - Enabled]
+// ============================================================================
+
+void Logger::setEnabled(bool enabled)
+{
+ if (enabled)
+ this->_flags |= kLoggerIsEnabled | kLoggerIsUsed;
+ else
+ this->_flags &= ~(kLoggerIsEnabled | kLoggerIsUsed);
+}
+
+// ============================================================================
+// [AsmJit::Logger - LogBinary]
+// ============================================================================
+
+void Logger::setLogBinary(bool value)
+{
+ if (value)
+ this->_flags |= kLoggerOutputBinary;
+ else
+ this->_flags &= ~kLoggerOutputBinary;
+}
+
+// ============================================================================
+// [AsmJit::Logger - HexImmediate]
+// ============================================================================
+
+void Logger::setHexImmediate(bool value)
+{
+ if (value)
+ this->_flags |= kLoggerOutputHexImmediate;
+ else
+ this->_flags &= ~kLoggerOutputHexImmediate;
+}
+
+// ============================================================================
+// [AsmJit::Logger - HexDisplacement]
+// ============================================================================
+
+void Logger::setHexDisplacement(bool value)
+{
+ if (value)
+ this->_flags |= kLoggerOutputHexDisplacement;
+ else
+ this->_flags &= ~kLoggerOutputHexDisplacement;
+}
+
+// ============================================================================
+// [AsmJit::Logger - InstructionPrefix]
+// ============================================================================
+
+void Logger::setInstructionPrefix(const char *prefix)
+{
+ memset(this->_instructionPrefix, 0, ASMJIT_ARRAY_SIZE(this->_instructionPrefix));
+
+ if (!prefix)
+ return;
+
+ size_t length = strnlen(prefix, ASMJIT_ARRAY_SIZE(this->_instructionPrefix) - 1);
+ memcpy(this->_instructionPrefix, prefix, length);
+}
+
+// ============================================================================
+// [AsmJit::FileLogger - Construction / Destruction]
+// ============================================================================
+
+FileLogger::FileLogger(FILE *stream) : _stream(nullptr)
+{
+ this->setStream(stream);
+}
+
+FileLogger::~FileLogger()
+{
+}
+
+// ============================================================================
+// [AsmJit::FileLogger - Accessors]
+// ============================================================================
+
+//! @brief Set file stream.
+void FileLogger::setStream(FILE *stream)
+{
+ this->_stream = stream;
+
+ if (this->isEnabled() && this->_stream)
+ this->_flags |= kLoggerIsUsed;
+ else
+ this->_flags &= ~kLoggerIsUsed;
+}
+
+// ============================================================================
+// [AsmJit::FileLogger - Logging]
+// ============================================================================
+
+void FileLogger::logString(const char *buf, size_t len)
+{
+ if (!this->isUsed())
+ return;
+
+ if (len == kInvalidSize)
+ len = strlen(buf);
+
+ fwrite(buf, 1, len, this->_stream);
+}
+
+// ============================================================================
+// [AsmJit::FileLogger - Enabled]
+// ============================================================================
+
+void FileLogger::setEnabled(bool enabled)
+{
+ if (enabled)
+ this->_flags |= kLoggerIsEnabled | (this->_stream ? kLoggerIsUsed : 0);
+ else
+ this->_flags &= ~(kLoggerIsEnabled | kLoggerIsUsed);
+}
+
+// ============================================================================
+// [AsmJit::StringLogger - Construction / Destruction]
+// ============================================================================
+
+StringLogger::StringLogger()
+{
+}
+
+StringLogger::~StringLogger()
+{
+}
+
+// ============================================================================
+// [AsmJit::StringLogger - Logging]
+// ============================================================================
+
+void StringLogger::logString(const char *buf, size_t len)
+{
+ if (!this->isUsed())
+ return;
+ this->_stringBuilder.appendString(buf, len);
+}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/logger.h
@@ -1,1 +1,246 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_CORE_LOGGER_H
+#define _ASMJIT_CORE_LOGGER_H
+
+// [Dependencies - AsmJit]
+#include "../core/build.h"
+#include "../core/defs.h"
+#include "../core/stringbuilder.h"
+
+// [Dependencies - C]
+#include <cstdarg>
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+//! @addtogroup AsmJit_Logging
+//! @{
+
+// ============================================================================
+// [AsmJit::Logger]
+// ============================================================================
+
+//! @brief Abstract logging class.
+//!
+//! This class can be inherited and reimplemented to fit into your logging
+//! subsystem. When reimplementing use @c AsmJit::Logger::log() method to
+//! log into your stream.
+//!
+//! This class also contain @c _enabled member that can be used to enable
+//! or disable logging.
+struct Logger
+{
+ ASMJIT_NO_COPY(Logger)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create logger.
+ ASMJIT_API Logger();
+ //! @brief Destroy logger.
+ ASMJIT_API virtual ~Logger();
+
+ // --------------------------------------------------------------------------
+ // [Logging]
+ // --------------------------------------------------------------------------
+
+ //! @brief Abstract method to log output.
+ //!
+ //! Default implementation that is in @c AsmJit::Logger is to do nothing.
+ //! It's virtual to fit to your logging system.
+ virtual void logString(const char *buf, size_t len = kInvalidSize) = 0;
+
+ //! @brief Log formatter message (like sprintf) sending output to @c logString() method.
+ ASMJIT_API virtual void logFormat(const char *fmt, ...);
+
+ // --------------------------------------------------------------------------
+ // [Flags]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get logger flags (used internally by Assembler/Compiler).
+ uint32_t getFlags() const { return this->_flags; }
+
+ // --------------------------------------------------------------------------
+ // [Enabled]
+ // --------------------------------------------------------------------------
+
+ //! @brief Return @c true if logging is enabled.
+ bool isEnabled() const { return !!(this->_flags & kLoggerIsEnabled); }
+
+ //! @brief Set logging to enabled or disabled.
+ ASMJIT_API virtual void setEnabled(bool enabled);
+
+ // --------------------------------------------------------------------------
+ // [Used]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get whether the logger should be used.
+ bool isUsed() const { return !!(this->_flags & kLoggerIsUsed); }
+
+ // --------------------------------------------------------------------------
+ // [LogBinary]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get whether logging of binary output is enabled.
+ bool getLogBinary() const { return !!(this->_flags & kLoggerOutputBinary); }
+ //! @brief Enable or disable binary output logging.
+ ASMJIT_API void setLogBinary(bool value);
+
+ // --------------------------------------------------------------------------
+ // [HexImmediate]
+ // --------------------------------------------------------------------------
+
+ bool getHexImmediate() const { return !!(this->_flags & kLoggerOutputHexImmediate); }
+ ASMJIT_API void setHexImmediate(bool value);
+
+ // --------------------------------------------------------------------------
+ // [HexDisplacement]
+ // --------------------------------------------------------------------------
+
+ bool getHexDisplacement() const { return !!(this->_flags & kLoggerOutputHexDisplacement); }
+ ASMJIT_API void setHexDisplacement(bool value);
+
+ // --------------------------------------------------------------------------
+ // [InstructionPrefix]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get instruction prefix.
+ const char *getInstructionPrefix() const { return this->_instructionPrefix; }
+ //! @brief Set instruction prefix.
+ ASMJIT_API void setInstructionPrefix(const char *prefix);
+ //! @brief Reset instruction prefix.
+ void resetInstructionPrefix() { this->setInstructionPrefix(nullptr); }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Flags, see @ref kLoggerFlag.
+ uint32_t _flags;
+
+ //! @brief Instrictions and macro-instructions prefix.
+ char _instructionPrefix[12];
+};
+
+// ============================================================================
+// [AsmJit::FileLogger]
+// ============================================================================
+
+//! @brief Logger that can log to standard C @c FILE* stream.
+struct FileLogger : public Logger
+{
+ ASMJIT_NO_COPY(FileLogger)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @c FileLogger.
+ //! @param stream FILE stream where logging will be sent (can be @c NULL
+ //! to disable logging).
+ ASMJIT_API FileLogger(FILE *stream = nullptr);
+
+ //! @brief Destroy the @ref FileLogger.
+ ASMJIT_API virtual ~FileLogger();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get @c FILE* stream.
+ //!
+ //! @note Return value can be @c NULL.
+ FILE *getStream() const { return this->_stream; }
+
+ //! @brief Set @c FILE* stream.
+ //!
+ //! @param stream @c FILE stream where to log output (can be @c NULL to
+ //! disable logging).
+ ASMJIT_API void setStream(FILE *stream);
+
+ // --------------------------------------------------------------------------
+ // [Logging]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual void logString(const char *buf, size_t len = kInvalidSize);
+
+ // --------------------------------------------------------------------------
+ // [Enabled]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual void setEnabled(bool enabled);
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief C file stream.
+ FILE *_stream;
+};
+
+// ============================================================================
+// [AsmJit::StringLogger]
+// ============================================================================
+
+//! @brief String logger.
+struct StringLogger : public Logger
+{
+ ASMJIT_NO_COPY(StringLogger)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create new @ref StringLogger.
+ ASMJIT_API StringLogger();
+
+ //! @brief Destroy the @ref StringLogger.
+ ASMJIT_API virtual ~StringLogger();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get <code>char*</code> pointer which represents the serialized
+ //! string.
+ //!
+ //! The pointer is owned by @ref StringLogger, it can't be modified or freed.
+ const char *getString() const { return this->_stringBuilder.getData(); }
+
+ //! @brief Clear the serialized string.
+ void clearString() { this->_stringBuilder.clear(); }
+
+ // --------------------------------------------------------------------------
+ // [Logging]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual void logString(const char *buf, size_t len = kInvalidSize);
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Output.
+ StringBuilder _stringBuilder;
+};
+
+//! @}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_CORE_LOGGER_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/memorymanager.cpp
@@ -1,1 +1,1187 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/assert.h"
+#include "../core/lock.h"
+#include "../core/memorymanager.h"
+#include "../core/virtualmemory.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+// This file contains implementation of virtual memory management for AsmJit
+// library. The initial concept is to keep this implementation simple but
+// efficient. There are several goals I decided to write implementation myself.
+//
+// Goals:
+// - We need usually to allocate blocks of 64 bytes long and more.
+// - Alignment of allocated blocks is large - 32 bytes or 64 bytes.
+// - Keep memory manager information outside allocated virtual memory pages
+// (these pages allows execution of code).
+// - Keep implementation small.
+//
+// I think that implementation is not small and probably not too much readable,
+// so there is small know how.
+//
+// - Implementation is based on bit arrays and binary trees. Bit arrays
+// contains information about allocated and unused blocks of memory. Each
+// block size describes MemNode::density member. Count of blocks are
+// stored in MemNode::blocks member. For example if density is 64 and
+// count of blocks is 20, memory node contains 64*20 bytes of memory and
+// smallest possible allocation (and also alignment) is 64 bytes. So density
+// describes also memory alignment. Binary trees are used to enable fast
+// lookup into all addresses allocated by memory manager instance. This is
+// used mainly in MemoryManagerPrivate::free().
+//
+// Bit array looks like this (empty = unused, X = used) - Size of block 64
+// -------------------------------------------------------------------------
+// | |X|X| | | | | |X|X|X|X|X|X| | | | | | | | | | | | |X| | | | |X|X|X| | |
+// -------------------------------------------------------------------------
+// Bits array shows that there are 12 allocated blocks of 64 bytes, so total
+// allocated size is 768 bytes. Maximum count of continuous blocks is 12
+// (see largest gap).
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [Bits Manipulation]
+// ============================================================================
+
+static const size_t BITS_PER_ENTITY = sizeof(size_t) * 8;
+
+static void _SetBits(size_t *buf, size_t index, size_t len)
+{
+ if (!len)
+ return;
+
+ size_t i = index / BITS_PER_ENTITY; // size_t[]
+ size_t j = index % BITS_PER_ENTITY; // size_t[][] bit index
+
+ // How many bytes process in the first group.
+ size_t c = BITS_PER_ENTITY - j;
+ if (c > len)
+ c = len;
+
+ // Offset.
+ buf += i;
+
+ *buf++ |= (~static_cast<size_t>(0) >> (BITS_PER_ENTITY - c)) << j;
+ len -= c;
+
+ while (len >= BITS_PER_ENTITY)
+ {
+ *buf++ = ~static_cast<size_t>(0);
+ len -= BITS_PER_ENTITY;
+ }
+
+ if (len)
+ *buf |= ~static_cast<size_t>(0) >> (BITS_PER_ENTITY - len);
+}
+
+// ============================================================================
+// [AsmJit::MemNode]
+// ============================================================================
+
+template<typename T> static inline T M_DIV(T x, T y) { return x / y; }
+template<typename T> static inline T M_MOD(T x, T y) { return x % y; }
+
+template<typename T> struct RbNode
+{
+ // --------------------------------------------------------------------------
+ // [Node red-black tree tree, key is mem pointer].
+ // --------------------------------------------------------------------------
+
+ // Implementation is based on article by Julienne Walker (Public Domain),
+ // including C code and original comments. Thanks for the excellent article.
+
+ // Left[0] and right[1] nodes.
+ T *node[2];
+ // Whether the node is RED.
+ uint32_t red;
+
+ // --------------------------------------------------------------------------
+ // [Chunk Memory]
+ // --------------------------------------------------------------------------
+
+ // Virtual memory address.
+ uint8_t *mem;
+};
+
+// Get whether the node is red (NULL or node with red flag).
+template<typename T> static inline bool isRed(RbNode<T> *node)
+{
+ return node && node->red;
+}
+
+struct MemNode : public RbNode<MemNode>
+{
+ // --------------------------------------------------------------------------
+ // [Node double-linked list]
+ // --------------------------------------------------------------------------
+
+ MemNode *prev; // Prev node in list.
+ MemNode *next; // Next node in list.
+
+ // --------------------------------------------------------------------------
+ // [Chunk Data]
+ // --------------------------------------------------------------------------
+
+ size_t size; // How many bytes contain this node.
+ size_t blocks; // How many blocks are here.
+ size_t density; // Minimum count of allocated bytes in this node (also alignment).
+ size_t used; // How many bytes are used in this node.
+ size_t largestBlock; // Contains largest block that can be allocated.
+
+ size_t *baUsed; // Contains bits about used blocks. (0 = unused, 1 = used).
+ size_t *baCont; // Contains bits about continuous blocks. (0 = stop, 1 = continue).
+
+ // --------------------------------------------------------------------------
+ // [Methods]
+ // --------------------------------------------------------------------------
+
+ // Get available space.
+ size_t getAvailable() const { return this->size - this->used; }
+
+ void fillData(MemNode *other)
+ {
+ this->mem = other->mem;
+
+ this->size = other->size;
+ this->blocks = other->blocks;
+ this->density = other->density;
+ this->used = other->used;
+ this->largestBlock = other->largestBlock;
+ this->baUsed = other->baUsed;
+ this->baCont = other->baCont;
+ }
+};
+
+// ============================================================================
+// [AsmJit::M_Permanent]
+// ============================================================================
+
+//! @brief Permanent node.
+struct PermanentNode
+{
+ uint8_t *mem; // Base pointer (virtual memory address).
+ size_t size; // Count of bytes allocated.
+ size_t used; // Count of bytes used.
+ PermanentNode *prev; // Pointer to prev chunk or NULL.
+
+ // Get available space.
+ size_t getAvailable() const { return this->size - this->used; }
+};
+
+// ============================================================================
+// [AsmJit::MemoryManagerPrivate]
+// ============================================================================
+
+struct MemoryManagerPrivate
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+#ifndef ASMJIT_WINDOWS
+ MemoryManagerPrivate();
+#else
+ MemoryManagerPrivate(HANDLE hProcess);
+#endif // ASMJIT_WINDOWS
+ ~MemoryManagerPrivate();
+
+ // --------------------------------------------------------------------------
+ // [Allocation]
+ // --------------------------------------------------------------------------
+
+ MemNode *createNode(size_t size, size_t density);
+
+ void *allocPermanent(size_t vsize);
+ void *allocFreeable(size_t vsize);
+
+ bool free(void *address);
+ bool shrink(void *address, size_t used);
+ void freeAll(bool keepVirtualMemory);
+
+ // Helpers to avoid ifdefs in the code.
+ uint8_t *allocVirtualMemory(size_t size, size_t *vsize)
+ {
+#ifndef ASMJIT_WINDOWS
+ return static_cast<uint8_t *>(VirtualMemory::alloc(size, vsize, true));
+#else
+ return static_cast<uint8_t *>(VirtualMemory::allocProcessMemory(this->_hProcess, size, vsize, true));
+#endif
+ }
+
+ void freeVirtualMemory(void *vmem, size_t vsize)
+ {
+#ifndef ASMJIT_WINDOWS
+ VirtualMemory::free(vmem, vsize);
+#else
+ VirtualMemory::freeProcessMemory(this->_hProcess, vmem, vsize);
+#endif
+ }
+
+ // --------------------------------------------------------------------------
+ // [NodeList RB-Tree]
+ // --------------------------------------------------------------------------
+
+ bool checkTree();
+
+ void insertNode(MemNode *node);
+ MemNode *removeNode(MemNode *node);
+ MemNode *findPtr(uint8_t *mem);
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+#ifdef ASMJIT_WINDOWS
+ HANDLE _hProcess; // Process where to allocate memory.
+#endif // ASMJIT_WINDOWS
+ Lock _lock; // Lock for thread safety.
+
+ size_t _newChunkSize; // Default node size.
+ size_t _newChunkDensity; // Default node density.
+ size_t _allocated; // How many bytes are allocated.
+ size_t _used; // How many bytes are used.
+
+ // Memory nodes list.
+ MemNode *_first;
+ MemNode *_last;
+ MemNode *_optimal;
+
+ // Memory nodes tree.
+ MemNode *_root;
+
+ // Permanent memory.
+ PermanentNode *_permanent;
+
+ // Whether to keep virtual memory after destroy.
+ bool _keepVirtualMemory;
+};
+
+// ============================================================================
+// [AsmJit::MemoryManagerPrivate - Construction / Destruction]
+// ============================================================================
+
+#ifndef ASMJIT_WINDOWS
+MemoryManagerPrivate::MemoryManagerPrivate() :
+#else
+MemoryManagerPrivate::MemoryManagerPrivate(HANDLE hProcess) : _hProcess(hProcess),
+#endif
+ _newChunkSize(65536), _newChunkDensity(64), _allocated(0), _used(0), _root(nullptr), _first(nullptr), _last(nullptr), _optimal(nullptr), _permanent(nullptr), _keepVirtualMemory(false)
+{
+}
+
+MemoryManagerPrivate::~MemoryManagerPrivate()
+{
+ // Freeable memory cleanup - Also frees the virtual memory if configured to.
+ this->freeAll(this->_keepVirtualMemory);
+
+ // Permanent memory cleanup - Never frees the virtual memory.
+ PermanentNode *node = this->_permanent;
+ while (node)
+ {
+ PermanentNode *prev = node->prev;
+ ASMJIT_FREE(node);
+ node = prev;
+ }
+}
+
+// ============================================================================
+// [AsmJit::MemoryManagerPrivate - Allocation]
+// ============================================================================
+
+// Allocates virtual memory node and MemNode structure.
+//
+// Returns MemNode* on success, otherwise NULL.
+MemNode *MemoryManagerPrivate::createNode(size_t size, size_t density)
+{
+ size_t vsize;
+ uint8_t *vmem = this->allocVirtualMemory(size, &vsize);
+
+ // Out of memory.
+ if (!vmem)
+ return nullptr;
+
+ size_t blocks = vsize / density;
+ size_t bsize = (((blocks + 7) >> 3) + sizeof(size_t) - 1) & ~static_cast<size_t>(sizeof(size_t) - 1);
+
+ MemNode *node = reinterpret_cast<MemNode *>(ASMJIT_MALLOC(sizeof(MemNode)));
+ uint8_t *data = reinterpret_cast<uint8_t *>(ASMJIT_MALLOC(bsize * 2));
+
+ // Out of memory.
+ if (!node || !data)
+ {
+ this->freeVirtualMemory(vmem, vsize);
+ if (node)
+ ASMJIT_FREE(node);
+ if (data)
+ ASMJIT_FREE(data);
+ return nullptr;
+ }
+
+ // Initialize RbNode data.
+ node->node[0] = nullptr;
+ node->node[1] = nullptr;
+ node->red = 1;
+ node->mem = vmem;
+
+ // Initialize MemNode data.
+ node->prev = nullptr;
+ node->next = nullptr;
+
+ node->size = vsize;
+ node->blocks = blocks;
+ node->density = density;
+ node->used = 0;
+ node->largestBlock = vsize;
+
+ memset(data, 0, bsize * 2);
+ node->baUsed = reinterpret_cast<size_t *>(data);
+ node->baCont = reinterpret_cast<size_t *>(data + bsize);
+
+ return node;
+}
+
+void *MemoryManagerPrivate::allocPermanent(size_t vsize)
+{
+ static const size_t permanentAlignment = 32;
+ static const size_t permanentNodeSize = 32768;
+
+ size_t over = vsize % permanentAlignment;
+ if (over)
+ over = permanentAlignment - over;
+
+ size_t alignedSize = vsize + over;
+ AutoLock locked(this->_lock);
+
+ PermanentNode *node = this->_permanent;
+
+ // Try to find space in allocated chunks.
+ while (node && alignedSize > node->getAvailable())
+ node = node->prev;
+
+ // Or allocate new node.
+ if (!node)
+ {
+ size_t nodeSize = permanentNodeSize;
+ if (vsize > nodeSize)
+ nodeSize = vsize;
+
+ node = static_cast<PermanentNode *>(ASMJIT_MALLOC(sizeof(PermanentNode)));
+ // Out of memory.
+ if (!node)
+ return nullptr;
+
+ node->mem = this->allocVirtualMemory(nodeSize, &node->size);
+ // Out of memory.
+ if (!node->mem)
+ {
+ ASMJIT_FREE(node);
+ return nullptr;
+ }
+
+ node->used = 0;
+ node->prev = this->_permanent;
+ this->_permanent = node;
+ }
+
+ // Finally, copy function code to our space we reserved for.
+ uint8_t *result = node->mem + node->used;
+
+ // Update Statistics.
+ node->used += alignedSize;
+ this->_used += alignedSize;
+
+ // Code can be null to only reserve space for code.
+ return static_cast<void *>(result);
+}
+
+void *MemoryManagerPrivate::allocFreeable(size_t vsize)
+{
+ size_t i; // Current index.
+ size_t need; // How many we need to be freed.
+
+ // Align to 32 bytes (our default alignment).
+ vsize = (vsize + 31) & ~static_cast<size_t>(31);
+ if (!vsize)
+ return nullptr;
+
+ AutoLock locked(this->_lock);
+ MemNode *node = this->_optimal;
+
+ size_t minVSize = this->_newChunkSize;
+
+ // Try to find memory block in existing nodes.
+ while (node)
+ {
+ // Skip this node?
+ if (node->getAvailable() < vsize || (node->largestBlock < vsize && node->largestBlock))
+ {
+ MemNode *next = node->next;
+ if (node->getAvailable() < minVSize && node == _optimal && next)
+ this->_optimal = next;
+ node = next;
+ continue;
+ }
+
+ size_t *up = node->baUsed; // Current ubits address.
+ size_t ubits; // Current ubits[0] value.
+ size_t bit; // Current bit mask.
+ size_t blocks = node->blocks; // Count of blocks in node.
+ size_t cont = 0; // How many bits are currently freed in find loop.
+ size_t maxCont = 0; // Largest continuous block (bits count).
+ size_t j;
+
+ need = M_DIV(vsize + node->density - 1, node->density);
+ i = 0;
+
+ // Try to find node that is large enough.
+ while (i < blocks)
+ {
+ ubits = *up++;
+
+ // Fast skip used blocks.
+ if (ubits == ~static_cast<size_t>(0))
+ {
+ if (cont > maxCont)
+ maxCont = cont;
+ cont = 0;
+
+ i += BITS_PER_ENTITY;
+ continue;
+ }
+
+ size_t max = BITS_PER_ENTITY;
+ if (i + max > blocks)
+ max = blocks - i;
+
+ for (j = 0, bit = 1; j < max; bit <<= 1)
+ {
+ ++j;
+ if (!(ubits & bit))
+ {
+ if (++cont == need)
+ {
+ i += j;
+ i -= cont;
+ goto _Found;
+ }
+ continue;
+ }
+
+ if (cont > maxCont)
+ maxCont = cont;
+ cont = 0;
+ }
+
+ i += BITS_PER_ENTITY;
+ }
+
+ // Because we traversed entire node, we can set largest node size that
+ // will be used to cache next traversing..
+ node->largestBlock = maxCont * node->density;
+
+ node = node->next;
+ }
+
+ // If we are here, we failed to find existing memory block and we must
+ // allocate new.
+ size_t chunkSize = this->_newChunkSize;
+ if (chunkSize < vsize)
+ chunkSize = vsize;
+
+ node = this->createNode(chunkSize, this->_newChunkDensity);
+ if (!node)
+ return nullptr;
+
+ // Update binary tree.
+ this->insertNode(node);
+ ASMJIT_ASSERT(this->checkTree());
+
+ // Alloc first node at start.
+ i = 0;
+ need = (vsize + node->density - 1) / node->density;
+
+ // Update statistics.
+ this->_allocated += node->size;
+
+_Found:
+ // Update bits.
+ _SetBits(node->baUsed, i, need);
+ _SetBits(node->baCont, i, need - 1);
+
+ // Update statistics.
+ size_t u = need * node->density;
+ node->used += u;
+ node->largestBlock = 0;
+ this->_used += u;
+
+ // And return pointer to allocated memory.
+ uint8_t *result = node->mem + i * node->density;
+ ASMJIT_ASSERT(result >= node->mem && result <= node->mem + node->size - vsize);
+ return result;
+}
+
+bool MemoryManagerPrivate::free(void *address)
+{
+ if (!address)
+ return true;
+
+ AutoLock locked(this->_lock);
+
+ MemNode *node = this->findPtr(static_cast<uint8_t *>(address));
+ if (!node)
+ return false;
+
+ size_t offset = static_cast<size_t>(static_cast<uint8_t *>(address) - node->mem);
+ size_t bitpos = M_DIV(offset, node->density);
+ size_t i = bitpos / BITS_PER_ENTITY;
+
+ size_t *up = node->baUsed + i; // Current ubits address.
+ size_t *cp = node->baCont + i; // Current cbits address.
+ size_t ubits = *up; // Current ubits[0] value.
+ size_t cbits = *cp; // Current cbits[0] value.
+ size_t bit = static_cast<size_t>(1) << (bitpos % BITS_PER_ENTITY);
+
+ size_t cont = 0;
+
+ for (;;)
+ {
+ bool stop = !(cbits & bit);
+ ubits &= ~bit;
+ cbits &= ~bit;
+
+ bit <<= 1;
+ ++cont;
+
+ if (stop || !bit)
+ {
+ *up = ubits;
+ *cp = cbits;
+ if (stop)
+ break;
+
+ ubits = *++up;
+ cbits = *++cp;
+ bit = 1;
+ }
+ }
+
+ // If the freed block is fully allocated node then it's needed to
+ // update 'optimal' pointer in memory manager.
+ if (node->used == node->size)
+ {
+ MemNode *cur = this->_optimal;
+
+ do
+ {
+ cur = cur->prev;
+ if (cur == node)
+ {
+ this->_optimal = node;
+ break;
+ }
+ } while (cur);
+ }
+
+ // Statistics.
+ cont *= node->density;
+ if (node->largestBlock < cont)
+ node->largestBlock = cont;
+ node->used -= cont;
+ this->_used -= cont;
+
+ // If page is empty, we can free it.
+ if (!node->used)
+ {
+ // Free memory associated with node (this memory is not accessed
+ // anymore so it's safe).
+ this->freeVirtualMemory(node->mem, node->size);
+ ASMJIT_FREE(node->baUsed);
+
+ node->baUsed = nullptr;
+ node->baCont = nullptr;
+
+ // Statistics.
+ this->_allocated -= node->size;
+
+ // Remove node. This function can return different node than
+ // passed into, but data is copied into previous node if needed.
+ ASMJIT_FREE(this->removeNode(node));
+ ASMJIT_ASSERT(this->checkTree());
+ }
+
+ return true;
+}
+
+bool MemoryManagerPrivate::shrink(void *address, size_t used)
+{
+ if (!address)
+ return false;
+ if (!used)
+ return free(address);
+
+ AutoLock locked(this->_lock);
+
+ MemNode *node = this->findPtr(static_cast<uint8_t *>(address));
+ if (!node)
+ return false;
+
+ size_t offset = static_cast<size_t>(static_cast<uint8_t *>(address) - node->mem);
+ size_t bitpos = M_DIV(offset, node->density);
+ size_t i = bitpos / BITS_PER_ENTITY;
+
+ size_t *up = node->baUsed + i; // Current ubits address.
+ size_t *cp = node->baCont + i; // Current cbits address.
+ size_t ubits = *up; // Current ubits[0] value.
+ size_t cbits = *cp; // Current cbits[0] value.
+ size_t bit = static_cast<size_t>(1) << (bitpos % BITS_PER_ENTITY);
+
+ size_t cont = 0;
+ size_t usedBlocks = (used + node->density - 1) / node->density;
+
+ bool stop;
+ // Find the first block we can mark as free.
+ for (;;)
+ {
+ stop = !(cbits & bit);
+ if (stop)
+ return true;
+
+ if (++cont == usedBlocks)
+ break;
+
+ bit <<= 1;
+ if (!bit)
+ {
+ ubits = *++up;
+ cbits = *++cp;
+ bit = 1;
+ }
+ }
+
+ // Free the tail blocks.
+ cont = ~static_cast<size_t>(0);
+ goto _EnterFreeLoop;
+
+ for (;;)
+ {
+ stop = !(cbits & bit);
+ ubits &= ~bit;
+ _EnterFreeLoop:
+ cbits &= ~bit;
+
+ bit <<= 1;
+ ++cont;
+
+ if (stop || !bit)
+ {
+ *up = ubits;
+ *cp = cbits;
+ if (stop)
+ break;
+
+ ubits = *++up;
+ cbits = *++cp;
+ bit = 1;
+ }
+ }
+
+ // Statistics.
+ cont *= node->density;
+ if (node->largestBlock < cont)
+ node->largestBlock = cont;
+ node->used -= cont;
+ this->_used -= cont;
+
+ return true;
+}
+
+void MemoryManagerPrivate::freeAll(bool keepVirtualMemory)
+{
+ MemNode *node = this->_first;
+
+ while (node)
+ {
+ MemNode *next = node->next;
+
+ if (!keepVirtualMemory)
+ this->freeVirtualMemory(node->mem, node->size);
+
+ ASMJIT_FREE(node->baUsed);
+ ASMJIT_FREE(node);
+
+ node = next;
+ }
+
+ this->_allocated = 0;
+ this->_used = 0;
+
+ this->_root = nullptr;
+ this->_first = nullptr;
+ this->_last = nullptr;
+ this->_optimal = nullptr;
+}
+
+// ============================================================================
+// [AsmJit::MemoryManagerPrivate - NodeList RB-Tree]
+// ============================================================================
+
+static int rbAssert(MemNode *root)
+{
+ if (!root)
+ return 1;
+
+ MemNode *ln = root->node[0];
+ MemNode *rn = root->node[1];
+
+ // Red violation.
+ //ASMJIT_ASSERT(!(isRed(root) && (isRed(ln) || isRed(rn))));
+
+ int lh = rbAssert(ln);
+ int rh = rbAssert(rn);
+
+ // Invalid btree.
+ //ASMJIT_ASSERT(ln || ln->mem < root->mem);
+ //ASMJIT_ASSERT(rn || rn->mem > root->mem);
+
+ // Black violation.
+ //ASMJIT_ASSERT(!(lh && rh && lh != rh));
+
+ // Only count black links.
+ if (lh && rh)
+ return isRed(root) ? lh : lh + 1;
+ else
+ return 0;
+}
+
+static inline MemNode *rbRotateSingle(MemNode *root, int dir)
+{
+ MemNode *save = root->node[!dir];
+
+ root->node[!dir] = save->node[dir];
+ save->node[dir] = root;
+
+ root->red = 1;
+ save->red = 0;
+
+ return save;
+}
+
+static inline MemNode *rbRotateDouble(MemNode *root, int dir)
+{
+ root->node[!dir] = rbRotateSingle(root->node[!dir], !dir);
+ return rbRotateSingle(root, dir);
+}
+
+bool MemoryManagerPrivate::checkTree()
+{
+ return rbAssert(_root) > 0;
+}
+
+void MemoryManagerPrivate::insertNode(MemNode *node)
+{
+ if (!this->_root)
+ // Empty tree case.
+ this->_root = node;
+ else
+ {
+ // False tree root.
+ RbNode<MemNode> head = { 0 };
+
+ // Grandparent & parent.
+ MemNode *g = nullptr;
+ MemNode *t = reinterpret_cast<MemNode *>(&head);
+
+ // Iterator & parent.
+ MemNode *p = nullptr;
+ MemNode *q = t->node[1] = this->_root;
+
+ int dir = 0, last = 0;
+
+ // Search down the tree.
+ for (;;)
+ {
+ if (!q)
+ {
+ // Insert new node at the bottom.
+ q = node;
+ p->node[dir] = node;
+ }
+ else if (isRed(q->node[0]) && isRed(q->node[1]))
+ {
+ // Color flip.
+ q->red = 1;
+ q->node[0]->red = 0;
+ q->node[1]->red = 0;
+ }
+
+ // Fix red violation.
+ if (isRed(q) && isRed(p))
+ {
+ int dir2 = t->node[1] == g;
+ t->node[dir2] = q == p->node[last] ? rbRotateSingle(g, !last) : rbRotateDouble(g, !last);
+ }
+
+ // Stop if found.
+ if (q == node)
+ break;
+
+ last = dir;
+ dir = q->mem < node->mem;
+
+ // Update helpers.
+ if (g)
+ t = g;
+ g = p;
+ p = q;
+ q = q->node[dir];
+ }
+
+ // Update root.
+ this->_root = head.node[1];
+ }
+
+ // Make root black.
+ this->_root->red = 0;
+
+ // Link with others.
+ node->prev = this->_last;
+
+ if (!this->_first)
+ {
+ this->_first = node;
+ this->_last = node;
+ this->_optimal = node;
+ }
+ else
+ {
+ node->prev = this->_last;
+ this->_last->next = node;
+ this->_last = node;
+ }
+}
+
+MemNode *MemoryManagerPrivate::removeNode(MemNode *node)
+{
+ // False tree root.
+ RbNode<MemNode> head = { 0 };
+
+ // Helpers.
+ MemNode *q = reinterpret_cast<MemNode *>(&head);
+ MemNode *p = nullptr;
+ MemNode *g = nullptr;
+ // Found item.
+ MemNode *f = nullptr;
+ int dir = 1;
+
+ // Set up.
+ q->node[1] = this->_root;
+
+ // Search and push a red down.
+ while (q->node[dir])
+ {
+ int last = dir;
+
+ // Update helpers.
+ g = p;
+ p = q;
+ q = q->node[dir];
+ dir = q->mem < node->mem;
+
+ // Save found node.
+ if (q == node)
+ f = q;
+
+ // Push the red node down.
+ if (!isRed(q) && !isRed(q->node[dir]))
+ {
+ if (isRed(q->node[!dir]))
+ p = p->node[last] = rbRotateSingle(q, dir);
+ else if (!isRed(q->node[!dir]))
+ {
+ MemNode *s = p->node[!last];
+
+ if (s)
+ {
+ if (!isRed(s->node[!last]) && !isRed(s->node[last]))
+ {
+ // Color flip.
+ p->red = 0;
+ s->red = 1;
+ q->red = 1;
+ }
+ else
+ {
+ int dir2 = g->node[1] == p;
+
+ if (isRed(s->node[last]))
+ g->node[dir2] = rbRotateDouble(p, last);
+ else if (isRed(s->node[!last]))
+ g->node[dir2] = rbRotateSingle(p, last);
+
+ // Ensure correct coloring.
+ q->red = g->node[dir2]->red = 1;
+ g->node[dir2]->node[0]->red = 0;
+ g->node[dir2]->node[1]->red = 0;
+ }
+ }
+ }
+ }
+ }
+
+ // Replace and remove.
+ ASMJIT_ASSERT(f);
+ ASMJIT_ASSERT(f != reinterpret_cast<MemNode *>(&head));
+ ASMJIT_ASSERT(q != reinterpret_cast<MemNode *>(&head));
+
+ if (f != q)
+ f->fillData(q);
+ p->node[p->node[1] == q] = q->node[!q->node[0]];
+
+ // Update root and make it black.
+ if ((this->_root = head.node[1]))
+ this->_root->red = 0;
+
+ // Unlink.
+ MemNode *next = q->next;
+ MemNode *prev = q->prev;
+
+ if (prev)
+ prev->next = next;
+ else
+ this->_first = next;
+ if (next)
+ next->prev = prev;
+ else
+ this->_last = prev;
+ if (this->_optimal == q)
+ this->_optimal = prev ? prev : next;
+
+ return q;
+}
+
+MemNode *MemoryManagerPrivate::findPtr(uint8_t *mem)
+{
+ MemNode *cur = this->_root;
+ while (cur)
+ {
+ uint8_t *curMem = cur->mem;
+ if (mem < curMem)
+ {
+ // Go left.
+ cur = cur->node[0];
+ continue;
+ }
+ else
+ {
+ uint8_t *curEnd = curMem + cur->size;
+ if (mem >= curEnd)
+ {
+ // Go right.
+ cur = cur->node[1];
+ continue;
+ }
+ else
+ // Match.
+ break;
+ }
+ }
+ return cur;
+}
+
+// ============================================================================
+// [AsmJit::MemoryManager]
+// ============================================================================
+
+MemoryManager::MemoryManager()
+{
+}
+
+MemoryManager::~MemoryManager()
+{
+}
+
+MemoryManager *MemoryManager::getGlobal()
+{
+ static VirtualMemoryManager memmgr;
+ return &memmgr;
+}
+
+// ============================================================================
+// [AsmJit::VirtualMemoryManager]
+// ============================================================================
+
+#ifndef ASMJIT_WINDOWS
+VirtualMemoryManager::VirtualMemoryManager()
+{
+ MemoryManagerPrivate *d = new(std::nothrow) MemoryManagerPrivate();
+ this->_d = static_cast<void *>(d);
+}
+#else
+VirtualMemoryManager::VirtualMemoryManager()
+{
+ MemoryManagerPrivate *d = new(std::nothrow) MemoryManagerPrivate(GetCurrentProcess());
+ this->_d = static_cast<void *>(d);
+}
+
+VirtualMemoryManager::VirtualMemoryManager(HANDLE hProcess)
+{
+ MemoryManagerPrivate *d = new(std::nothrow) MemoryManagerPrivate(hProcess);
+ this->_d = static_cast<void *>(d);
+}
+#endif // ASMJIT_WINDOWS
+
+VirtualMemoryManager::~VirtualMemoryManager()
+{
+ MemoryManagerPrivate *d = static_cast<MemoryManagerPrivate *>(this->_d);
+ delete d;
+}
+
+void *VirtualMemoryManager::alloc(size_t size, uint32_t type)
+{
+ MemoryManagerPrivate *d = static_cast<MemoryManagerPrivate *>(this->_d);
+
+ if (type == kMemAllocPermanent)
+ return d->allocPermanent(size);
+ else
+ return d->allocFreeable(size);
+}
+
+bool VirtualMemoryManager::free(void *address)
+{
+ MemoryManagerPrivate *d = static_cast<MemoryManagerPrivate *>(this->_d);
+ return d->free(address);
+}
+
+bool VirtualMemoryManager::shrink(void *address, size_t used)
+{
+ MemoryManagerPrivate *d = static_cast<MemoryManagerPrivate *>(this->_d);
+ return d->shrink(address, used);
+}
+
+void VirtualMemoryManager::freeAll()
+{
+ MemoryManagerPrivate *d = static_cast<MemoryManagerPrivate *>(this->_d);
+
+ // Calling MemoryManager::freeAll() will never keep allocated memory.
+ return d->freeAll(false);
+}
+
+size_t VirtualMemoryManager::getUsedBytes()
+{
+ MemoryManagerPrivate *d = static_cast<MemoryManagerPrivate *>(this->_d);
+ return d->_used;
+}
+
+size_t VirtualMemoryManager::getAllocatedBytes()
+{
+ MemoryManagerPrivate *d = static_cast<MemoryManagerPrivate *>(this->_d);
+ return d->_allocated;
+}
+
+bool VirtualMemoryManager::getKeepVirtualMemory() const
+{
+ MemoryManagerPrivate *d = static_cast<MemoryManagerPrivate *>(this->_d);
+ return d->_keepVirtualMemory;
+}
+
+void VirtualMemoryManager::setKeepVirtualMemory(bool keepVirtualMemory)
+{
+ MemoryManagerPrivate *d = static_cast<MemoryManagerPrivate *>(this->_d);
+ d->_keepVirtualMemory = keepVirtualMemory;
+}
+
+// ============================================================================
+// [AsmJit::VirtualMemoryManager - Debug]
+// ============================================================================
+
+#ifdef ASMJIT_MEMORY_MANAGER_DUMP
+
+struct GraphVizContext
+{
+ GraphVizContext();
+ ~GraphVizContext();
+
+ bool openFile(const char *fileName);
+ void closeFile();
+
+ void dumpNode(MemNode *node);
+ void connect(MemNode *node, MemNode *other, const char *dst);
+
+ FILE *file;
+};
+
+GraphVizContext::GraphVizContext() : file(nullptr)
+{
+}
+
+GraphVizContext::~GraphVizContext()
+{
+ this->closeFile();
+}
+
+bool GraphVizContext::openFile(const char *fileName)
+{
+ this->file = fopen(fileName, "w");
+ return !!this->file;
+}
+
+void GraphVizContext::closeFile()
+{
+ if (this->file)
+ {
+ fclose(this->file);
+ this->file = nullptr;
+ }
+}
+
+void GraphVizContext::dumpNode(MemNode* node)
+{
+ fprintf(file, " NODE_%p [shape=record, style=filled, color=%s, label=\"<L>|<C>Mem: %p, Used: %d/%d|<R>\"];\n", node, node->red ? "red" : "gray", node->mem, node->used, node->size);
+
+ if (node->node[0])
+ this->connect(node, node->node[0], "L");
+ if (node->node[1])
+ this->connect(node, node->node[1], "R");
+}
+
+void GraphVizContext::connect(MemNode *node, MemNode *other, const char *dst)
+{
+ this->dumpNode(other);
+
+ fprintf(file, " NODE_%p:%s -> NODE_%p:C", node, dst, other);
+ if (other->red)
+ fprintf(file, " [style=bold, color=red]");
+ fprintf(file, ";\n");
+}
+
+void VirtualMemoryManager::dump(const char *fileName)
+{
+ MemoryManagerPrivate *d = static_cast<MemoryManagerPrivate *>(this->_d);
+ GraphVizContext ctx;
+
+ if (!ctx.openFile(fileName))
+ return;
+
+ fprintf(ctx.file, "digraph {\n");
+ if (d->_root)
+ ctx.dumpNode(d->_root);
+ fprintf(ctx.file, "}\n");
+}
+#endif // ASMJIT_MEMORY_MANAGER_DUMP
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/memorymanager.h
@@ -1,1 +1,174 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+// [Guard]
+#ifndef _ASMJIT_CORE_MEMORYMANAGER_H
+#define _ASMJIT_CORE_MEMORYMANAGER_H
+
+// [Dependencies - AsmJit]
+#include "../core/build.h"
+#include "../core/defs.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+// [Debug]
+// #define ASMJIT_MEMORY_MANAGER_DUMP
+
+namespace AsmJit
+{
+
+//! @addtogroup AsmJit_MemoryManagement
+//! @{
+
+// ============================================================================
+// [AsmJit::MemoryManager]
+// ============================================================================
+
+//! @brief Virtual memory manager interface.
+//!
+//! This class is pure virtual. You can get default virtual memory manager using
+//! @c getGlobal() method. If you want to create more memory managers with same
+//! functionality as global memory manager use @c VirtualMemoryManager class.
+struct MemoryManager
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create memory manager instance.
+ ASMJIT_API MemoryManager();
+ //! @brief Destroy memory manager instance, this means also to free all memory
+ //! blocks.
+ ASMJIT_API virtual ~MemoryManager();
+
+ // --------------------------------------------------------------------------
+ // [Interface]
+ // --------------------------------------------------------------------------
+
+ //! @brief Allocate a @a size bytes of virtual memory.
+ //!
+ //! Note that if you are implementing your own virtual memory manager then you
+ //! can quitly ignore type of allocation. This is mainly for AsmJit to memory
+ //! manager that allocated memory will be never freed.
+ virtual void *alloc(size_t size, uint32_t type = kMemAllocFreeable) = 0;
+ //! @brief Free previously allocated memory at a given @a address.
+ virtual bool free(void *address) = 0;
+ //! @brief Free some tail memory.
+ virtual bool shrink(void *address, size_t used) = 0;
+ //! @brief Free all allocated memory.
+ virtual void freeAll() = 0;
+
+ //! @brief Get how many bytes are currently used.
+ virtual size_t getUsedBytes() = 0;
+ //! @brief Get how many bytes are currently allocated.
+ virtual size_t getAllocatedBytes() = 0;
+
+ // --------------------------------------------------------------------------
+ // [Statics]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get global memory manager instance.
+ //!
+ //! Global instance is instance of @c VirtualMemoryManager class. Global memory
+ //! manager is used by default by @ref Assembler::make() and @ref Compiler::make()
+ //! methods.
+ ASMJIT_API static MemoryManager *getGlobal();
+};
+
+// ============================================================================
+// [AsmJit::VirtualMemoryManager]
+// ============================================================================
+
+//! @brief Reference implementation of memory manager that uses
+//! @ref AsmJit::VirtualMemory class to allocate chunks of virtual memory
+//! and bit arrays to manage it.
+struct VirtualMemoryManager : public MemoryManager
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a @c VirtualMemoryManager instance.
+ ASMJIT_API VirtualMemoryManager();
+
+#ifdef ASMJIT_WINDOWS
+ //! @brief Create a @c VirtualMemoryManager instance for process @a hProcess.
+ //!
+ //! This is specialized version of constructor available only for windows and
+ //! usable to alloc/free memory of different process.
+ ASMJIT_API VirtualMemoryManager(HANDLE hProcess);
+#endif // ASMJIT_WINDOWS
+
+ //! @brief Destroy the @c VirtualMemoryManager instance, this means also to
+ //! free all blocks.
+ ASMJIT_API virtual ~VirtualMemoryManager();
+
+ // --------------------------------------------------------------------------
+ // [Interface]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual void *alloc(size_t size, uint32_t type = kMemAllocFreeable);
+ ASMJIT_API virtual bool free(void *address);
+ ASMJIT_API virtual bool shrink(void *address, size_t used);
+ ASMJIT_API virtual void freeAll();
+
+ ASMJIT_API virtual size_t getUsedBytes();
+ ASMJIT_API virtual size_t getAllocatedBytes();
+
+ // --------------------------------------------------------------------------
+ // [Virtual Memory Manager Specific]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get whether to keep allocated memory after memory manager is
+ //! destroyed.
+ //!
+ //! @sa @c setKeepVirtualMemory().
+ ASMJIT_API bool getKeepVirtualMemory() const;
+
+ //! @brief Set whether to keep allocated memory after memory manager is
+ //! destroyed.
+ //!
+ //! This method is usable when patching code of remote process. You need to
+ //! allocate process memory, store generated assembler into it and patch the
+ //! method you want to redirect (into your code). This method affects only
+ //! VirtualMemoryManager destructor. After destruction all internal
+ //! structures are freed, only the process virtual memory remains.
+ //!
+ //! @note Memory allocated with kMemAllocPermanent is always kept.
+ //!
+ //! @sa @c getKeepVirtualMemory().
+ ASMJIT_API void setKeepVirtualMemory(bool keepVirtualMemory);
+
+ // --------------------------------------------------------------------------
+ // [Debug]
+ // --------------------------------------------------------------------------
+
+#ifdef ASMJIT_MEMORY_MANAGER_DUMP
+ //! @brief Dump memory manager tree into file.
+ //!
+ //! Generated output is using DOT language (from graphviz package).
+ ASMJIT_API void dump(const char *fileName);
+#endif // ASMJIT_MEMORY_MANAGER_DUMP
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Pointer to private data hidden from the public API.
+ void *_d;
+};
+
+//! @}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_CORE_MEMORYMANAGER_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/memorymarker.h
@@ -1,1 +1,56 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+// [Guard]
+#ifndef _ASMJIT_CORE_MEMORYMARKER_H
+#define _ASMJIT_CORE_MEMORYMARKER_H
+
+// [Dependencies - AsmJit]
+#include "../core/build.h"
+#include "../core/defs.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+//! @addtogroup AsmJit_MemoryManagement
+//! @{
+
+// ============================================================================
+// [AsmJit::MemoryMarker]
+// ============================================================================
+
+//! @brief Virtual memory marker interface.
+struct MemoryMarker
+{
+ ASMJIT_NO_COPY(MemoryMarker)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API MemoryMarker() { }
+ ASMJIT_API virtual ~MemoryMarker() { }
+
+ // --------------------------------------------------------------------------
+ // [Interface]
+ // --------------------------------------------------------------------------
+
+ virtual void mark(const void *ptr, size_t size) = 0;
+};
+
+//! @}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_CORE_MEMORYMARKER_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/operand.cpp
@@ -1,1 +1,44 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/operand.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [AsmJit::Operand]
+// ============================================================================
+
+const Operand noOperand;
+
+// ============================================================================
+// [AsmJit::Imm]
+// ============================================================================
+
+//! @brief Create signed immediate value operand.
+Imm imm(sysint_t i)
+{
+ return Imm(i, false);
+}
+
+//! @brief Create unsigned immediate value operand.
+Imm uimm(sysuint_t i)
+{
+ return Imm((sysint_t)i, true);
+}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/operand.h
@@ -1,1 +1,527 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_CORE_OPERAND_H
+#define _ASMJIT_CORE_OPERAND_H
+
+// [Dependencies - AsmJit]
+#include "../core/defs.h"
+
+namespace AsmJit
+{
+
+//! @addtogroup AsmJit_Core
+//! @{
+
+// ============================================================================
+// [AsmJit::_OperandData]
+// ============================================================================
+
+//! @internal
+//!
+//! @brief Base operand data.
+struct _OpBase
+{
+ //! @brief Type of operand, see @c kOperandType.
+ uint8_t op;
+ //! @brief Size of operand (register, address, immediate, or variable).
+ uint8_t size;
+ //! @brief Not used.
+ uint8_t reserved[2];
+
+ //! @brief Operand ID (private variable for @c Assembler and @c Compiler classes).
+ //!
+ //! @note Uninitialized operand has always zero id.
+ uint32_t id;
+};
+
+//! @internal
+//!
+//! @brief Label operand data.
+struct _OpLabel
+{
+ //! @brief Type of operand, see @c kOperandType (in this case @c kOperandLabel).
+ uint8_t op;
+ //! @brief Size of label, currently not used.
+ uint8_t size;
+ //! @brief Not used.
+ uint8_t reserved[2];
+
+ //! @brief Operand ID.
+ uint32_t id;
+};
+
+//! @internal
+//!
+//! @brief Register operand data.
+struct _OpReg
+{
+ //! @brief Type of operand, see @c kOperandType (in this case @c kOperandReg).
+ uint8_t op;
+ //! @brief Size of register.
+ uint8_t size;
+ //! @brief Not used.
+ uint8_t reserved[2];
+
+ //! @brief Operand id.
+ uint32_t id;
+ //! @brief Register/Variable code, see @c REG.
+ uint32_t code;
+};
+
+//! @internal
+//!
+//! @brief Variable operand data.
+struct _OpVar
+{
+ //! @brief Type of operand, see @c kOperandType (in this case @c kOperandVar).
+ uint8_t op;
+ //! @brief Size of variable (0 if don't known).
+ uint8_t size;
+ //! @brief Not used.
+ uint8_t reserved[2];
+
+ //! @brief Operand ID.
+ uint32_t id;
+
+ //! @brief Type (and later also code) of register, see @c kX86RegType, @c kX86RegCode.
+ //!
+ //! @note Register code and variable code are two different things. In most
+ //! cases regCode is very related to varType, but general purpose registers
+ //! are divided to 64-bit, 32-bit, 16-bit and 8-bit entities so the regCode
+ //! can be used to access these, varType remains unchanged from the
+ //! initialization state. Variable type describes mainly variable type and
+ //! home memory size.
+ uint32_t regCode;
+
+ //! @brief Type of variable. See @c kX86VarType enum.
+ uint32_t varType;
+};
+
+//! @internal
+//!
+//! @brief Memory operand data.
+struct _OpMem
+{
+ //! @brief Type of operand, see @c kOperandType (in this case @c kOperandMem).
+ uint8_t op;
+ //! @brief Size of pointer.
+ uint8_t size;
+
+ //! @brief Memory operand type, see @c kOperandMemType.
+ uint8_t type;
+ //! @brief Segment override prefix, see @c kX86Seg.
+ uint8_t segment : 4;
+ //! @brief Emit MOV/LEA instruction using 16-bit/32-bit form of base/index
+ //! registers.
+ uint8_t sizePrefix : 1;
+ //! @brief Index register shift/scale (0 to 3 inclusive, see @c kScale).
+ uint8_t shift : 3;
+
+ //! @brief Operand ID.
+ uint32_t id;
+
+ //! @brief Base register index, variable or label id.
+ uint32_t base;
+ //! @brief Index register index or variable id.
+ uint32_t index;
+
+ //! @brief Target (for 32-bit, absolute address).
+ void *target;
+ //! @brief Displacement.
+ sysint_t displacement;
+};
+
+//! @internal
+//!
+//! @brief Immediate operand data.
+struct _OpImm
+{
+ //! @brief Type of operand, see @c kOperandType (in this case @c kOperandImm)..
+ uint8_t op;
+ //! @brief Size of immediate (or 0 to autodetect).
+ uint8_t size;
+ //! @brief @c true if immediate is unsigned.
+ uint8_t isUnsigned;
+ //! @brief Not used.
+ uint8_t reserved;
+
+ //! @brief Operand ID.
+ uint32_t id;
+ //! @brief Immediate value.
+ sysint_t value;
+};
+
+//! @internal
+//!
+//! @brief Binary operand data.
+struct _OpBin
+{
+ //! @brief First four 32-bit integers.
+ uint32_t u32[4];
+ //! @brief Second two 32-bit or 64-bit integers.
+ uintptr_t uptr[2];
+};
+
+// ============================================================================
+// [AsmJit::Operand]
+// ============================================================================
+
+//! @brief Operand can contain register, memory location, immediate, or label.
+struct Operand
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create an uninitialized operand.
+ Operand()
+ {
+ memset(this, 0, sizeof(Operand));
+ this->_base.id = kInvalidValue;
+ }
+
+ //! @brief Create a reference to @a other operand.
+ Operand(const Operand &other)
+ {
+ this->_init(other);
+ }
+
+#ifndef ASMJIT_NODOC
+ Operand(const _DontInitialize &) { }
+#endif // ASMJIT_NODOC
+
+ // --------------------------------------------------------------------------
+ // [Init & Copy]
+ // --------------------------------------------------------------------------
+
+ //! @internal
+ //!
+ //! @brief Initialize operand to @a other (used by constructors).
+ void _init(const Operand &other) { memcpy(this, &other, sizeof(Operand)); }
+
+ //! @internal
+ //!
+ //! @brief Initialize operand to @a other (used by assign operators).
+ void _copy(const Operand &other) { memcpy(this, &other, sizeof(Operand)); }
+
+ // --------------------------------------------------------------------------
+ // [Data]
+ // --------------------------------------------------------------------------
+
+ template<typename T> T &getData() { return reinterpret_cast<T &>(this->_base); }
+
+ template<typename T> const T &getData() const { return reinterpret_cast<const T &>(this->_base); }
+
+ // --------------------------------------------------------------------------
+ // [Type]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get type of the operand, see @c kOperandType.
+ uint32_t getType() const { return this->_base.op; }
+
+ //! @brief Get whether the operand is none (@c kOperandNone).
+ bool isNone() const { return this->_base.op == kOperandNone; }
+
+ //! @brief Get whether the operand is any (general purpose, mmx or sse) register (@c kOperandReg).
+ bool isReg() const { return this->_base.op == kOperandReg; }
+
+ //! @brief Get whether the operand is memory address (@c kOperandMem).
+ bool isMem() const { return this->_base.op == kOperandMem; }
+
+ //! @brief Get whether the operand is immediate (@c kOperandImm).
+ bool isImm() const { return this->_base.op == kOperandImm; }
+
+ //! @brief Get whether the operand is label (@c kOperandLabel).
+ bool isLabel() const { return this->_base.op == kOperandLabel; }
+
+ //! @brief Get whether the operand is variable (@c kOperandVar).
+ bool isVar() const { return this->_base.op == kOperandVar; }
+
+ //! @brief Get whether the operand is variable or memory.
+ bool isVarMem() const { return !!(this->_base.op & (kOperandVar | kOperandMem)); }
+
+ //! @brief Get whether the operand is register and type of register is @a regType.
+ bool isRegType(uint32_t regType) const { return this->_base.op == kOperandReg && (this->_reg.code & kRegTypeMask) == regType; }
+
+ //! @brief Get whether the operand is register and code of register is @a regCode.
+ bool isRegCode(uint32_t regCode) const { return this->_base.op == kOperandReg && this->_reg.code == regCode; }
+
+ //! @brief Get whether the operand is register and index of register is @a regIndex.
+ bool isRegIndex(uint32_t regIndex) const { return this->_base.op == kOperandReg && (this->_reg.code & kRegIndexMask) == (regIndex & kRegIndexMask); }
+
+ //! @brief Get whether the operand is any register or memory.
+ bool isRegMem() const { return !!(this->_base.op & (kOperandReg | kOperandMem)); }
+
+ //! @brief Get whether the operand is register of @a regType type or memory.
+ bool isRegTypeMem(uint32_t regType) const { return (this->_base.op == kOperandReg && (this->_reg.code & kRegTypeMask) == regType) || this->_base.op == kOperandMem; }
+
+ // --------------------------------------------------------------------------
+ // [Size]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get size of the operand in bytes.
+ uint32_t getSize() const { return this->_base.size; }
+
+ // --------------------------------------------------------------------------
+ // [Id]
+ // --------------------------------------------------------------------------
+
+ //! @brief Return operand Id (Operand Id's are used internally by
+ //! @c Assembler and @c Compiler classes).
+ //!
+ //! @note There is no way how to change or remove operand id. If you don't
+ //! need the operand just assign different operand to this one.
+ uint32_t getId() const { return this->_base.id; }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ union
+ {
+ //! @brief Base operand data.
+ _OpBase _base;
+ //! @brief Label operand data.
+ _OpLabel _lbl;
+ //! @brief Register operand data.
+ _OpReg _reg;
+ //! @brief Variable operand data.
+ _OpVar _var;
+ //! @brief Memory operand data.
+ _OpMem _mem;
+ //! @brief Immediate operand data.
+ _OpImm _imm;
+ //! @brief Binary data.
+ _OpBin _bin;
+ };
+};
+
+ASMJIT_VAR const Operand noOperand;
+
+// ============================================================================
+// [AsmJit::Reg]
+// ============================================================================
+
+//! @brief Base class for all register operands.
+struct Reg : public Operand
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new base register.
+ Reg(uint32_t code, uint32_t size) : Operand(_DontInitialize())
+ {
+ this->_reg.op = kOperandReg;
+ this->_reg.size = static_cast<uint8_t>(size);
+ this->_reg.id = kInvalidValue;
+ this->_reg.code = code;
+ }
+
+ //! @brief Create a new reference to @a other.
+ Reg(const Reg &other) : Operand(other) { }
+
+#ifndef ASMJIT_NODOC
+ Reg(const _DontInitialize &dontInitialize) : Operand(dontInitialize) { }
+#endif // ASMJIT_NODOC
+
+ // --------------------------------------------------------------------------
+ // [Reg Specific]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get register code, see @c REG.
+ uint32_t getRegCode() const { return this->_reg.code; }
+
+ //! @brief Get register type, see @c REG.
+ uint32_t getRegType() const { return this->_reg.code & kRegTypeMask; }
+
+ //! @brief Get register index (value from 0 to 7/15).
+ uint32_t getRegIndex() const { return this->_reg.code & kRegIndexMask; }
+
+ //! @brief Get whether register code is equal to @a code.
+ bool isRegCode(uint32_t code) const { return this->_reg.code == code; }
+
+ //! @brief Get whether register code is equal to @a type.
+ bool isRegType(uint32_t type) const { return (this->_reg.code & kRegTypeMask) == type; }
+
+ //! @brief Get whether register index is equal to @a index.
+ bool isRegIndex(uint32_t index) const { return (this->_reg.code & kRegIndexMask) == index; }
+
+ //! @brief Set register code to @a code.
+ Reg &setCode(uint32_t code)
+ {
+ this->_reg.code = code;
+ return *this;
+ }
+
+ //! @brief Set register size to @a size.
+ Reg &setSize(uint32_t size)
+ {
+ this->_reg.size = static_cast<uint8_t>(size);
+ return *this;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Operator Overload]
+ // --------------------------------------------------------------------------
+
+ Reg &operator=(const Reg &other) { this->_copy(other); return *this; }
+
+ bool operator==(const Reg &other) const { return this->getRegCode() == other.getRegCode(); }
+
+ bool operator!=(const Reg &other) const { return this->getRegCode() != other.getRegCode(); }
+};
+
+// ============================================================================
+// [AsmJit::Imm]
+// ============================================================================
+
+//! @brief Immediate operand.
+//!
+//! Immediate operand is part of instruction (it's inlined after it).
+//!
+//! To create immediate operand, use @c imm() and @c uimm() constructors
+//! or constructors provided by @c Immediate class itself.
+struct Imm : public Operand
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new signed or unsigned immediate value, assigning the value to @a i.
+ Imm(sysint_t i = 0, bool isUnsigned = false) : Operand(_DontInitialize())
+ {
+ this->_imm.op = kOperandImm;
+ this->_imm.size = 0;
+ this->_imm.isUnsigned = isUnsigned;
+ this->_imm.reserved = 0;
+
+ this->_imm.id = kInvalidValue;
+ this->_imm.value = i;
+ }
+
+ //! @brief Create a new immediate value from @a other.
+ Imm(const Imm &other) : Operand(other) { }
+
+ // --------------------------------------------------------------------------
+ // [Immediate Specific]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get whether an immediate is unsigned value.
+ bool isUnsigned() const { return !!this->_imm.isUnsigned; }
+
+ //! @brief Get signed immediate value.
+ sysint_t getValue() const { return this->_imm.value; }
+
+ //! @brief Get unsigned immediate value.
+ sysuint_t getUValue() const { return static_cast<sysuint_t>(this->_imm.value); }
+
+ //! @brief Set immediate value as signed type to @a val.
+ Imm &setValue(sysint_t val, bool isUnsigned = false)
+ {
+ this->_imm.value = val;
+ this->_imm.isUnsigned = isUnsigned;
+ return *this;
+ }
+
+ //! @brief Set immediate value as unsigned type to @a val.
+ Imm &setUValue(sysuint_t val)
+ {
+ this->_imm.value = static_cast<sysint_t>(val);
+ this->_imm.isUnsigned = true;
+ return *this;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Operator Overload]
+ // --------------------------------------------------------------------------
+
+ //! @brief Assign a signed value @a val to the immediate operand.
+ Imm &operator=(sysint_t val) { this->setValue(val); return *this; }
+
+ //! @brief Assign @a other to the immediate operand.
+ Imm &operator=(const Imm &other) { this->_copy(other); return *this; }
+};
+
+//! @brief Create signed immediate value operand.
+ASMJIT_API Imm imm(sysint_t i);
+
+//! @brief Create unsigned immediate value operand.
+ASMJIT_API Imm uimm(sysuint_t i);
+
+// ============================================================================
+// [AsmJit::Label]
+// ============================================================================
+
+//! @brief Label (jump target or data location).
+//!
+//! Label represents locations typically used as jump targets, but may be also
+//! used as position where are stored constants or static variables. If you
+//! want to use @c Label you need first to associate it with @c Assembler or
+//! @c Compiler instance. To create new label use @c Assembler::newLabel() or
+//! @c Compiler::newLabel().
+//!
+//! Example of using labels:
+//!
+//! @code
+//! // Create Assembler or Compiler instance.
+//! X86Assembler a;
+//!
+//! // Create Label instance.
+//! Label L_1(a);
+//!
+//! // ... your code ...
+//!
+//! // Using label, see @c AsmJit::Assembler or @c AsmJit::Compiler.
+//! a.jump(L_1);
+//!
+//! // ... your code ...
+//!
+//! // Bind label to current position, see @c AsmJit::Assembler::bind() or
+//! // @c AsmJit::Compiler::bind().
+//! a.bind(L_1);
+//! @endcode
+struct Label : public Operand
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create new, unassociated label.
+ Label() : Operand(_DontInitialize())
+ {
+ this->_lbl.op = kOperandLabel;
+ this->_lbl.size = 0;
+ this->_lbl.id = kInvalidValue;
+ }
+
+ //! @brief Create reference to another label.
+ Label(const Label &other) : Operand(other) { }
+
+ //! @brief Destroy the label.
+ ~Label() { }
+
+ // --------------------------------------------------------------------------
+ // [Operator Overload]
+ // --------------------------------------------------------------------------
+
+#ifndef ASMJIT_NODOC
+ Label &operator=(const Label &other) { this->_copy(other); return *this; }
+
+ bool operator==(const Label &other) const { return this->_base.id == other._base.id; }
+ bool operator!=(const Label &other) const { return this->_base.id != other._base.id; }
+#endif // ASMJIT_NODOC
+};
+
+//! @}
+
+} // AsmJit namespace
+
+// [Guard]
+#endif // _ASMJIT_CORE_OPERAND_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/podvector.h
@@ -1,1 +1,225 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_CORE_PODVECTOR_H
+#define _ASMJIT_CORE_PODVECTOR_H
+
+// [Dependencies - AsmJit]
+#include "../core/assert.h"
+#include "../core/defs.h"
+
+namespace AsmJit
+{
+
+//! @addtogroup AsmJit_Core
+//! @{
+
+// ============================================================================
+// [AsmJit::PodVector<T>]
+// ============================================================================
+
+//! @brief Template used to store and manage array of POD data.
+//!
+//! This template has these adventages over other vector<> templates:
+//! - Non-copyable (designed to be non-copyable, we want it)
+//! - No copy-on-write (some implementations of stl can use it)
+//! - Optimized for working only with POD types
+//! - Uses ASMJIT_... memory management macros
+template <typename T> struct PodVector
+{
+ ASMJIT_NO_COPY(PodVector<T>)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create new instance of PodVector template. Data will not
+ //! be allocated (will be NULL).
+ PodVector() : _data(nullptr), _length(0), _capacity(0) { }
+
+ //! @brief Destroy PodVector and free all data.
+ ~PodVector()
+ {
+ if (this->_data)
+ ASMJIT_FREE(this->_data);
+ }
+
+ // --------------------------------------------------------------------------
+ // [Data]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get data.
+ T *getData() { return this->_data; }
+ //! @overload
+ const T *getData() const { return this->_data; }
+
+ //! @brief Get length.
+ size_t getLength() const { return this->_length; }
+ //! @brief Get capacity.
+ size_t getCapacity() const { return this->_capacity; }
+
+ // --------------------------------------------------------------------------
+ // [Manipulation]
+ // --------------------------------------------------------------------------
+
+ //! @brief Clear vector data, but not free internal buffer.
+ void clear()
+ {
+ this->_length = 0;
+ }
+
+ //! @brief Clear vector data and free internal buffer.
+ void reset()
+ {
+ if (this->_data)
+ {
+ ASMJIT_FREE(this->_data);
+ this->_data = nullptr;
+ this->_length = 0;
+ this->_capacity = 0;
+ }
+ }
+
+ //! @brief Prepend @a item to vector.
+ bool prepend(const T &item)
+ {
+ if (this->_length == this->_capacity && !this->_grow())
+ return false;
+
+ memmove(this->_data + 1, this->_data, sizeof(T) * this->_length);
+ memcpy(this->_data, &item, sizeof(T));
+
+ ++this->_length;
+ return true;
+ }
+
+ //! @brief Insert an @a item at the @a index.
+ bool insert(size_t index, const T &item)
+ {
+ ASMJIT_ASSERT(index <= this->_length);
+ if (this->_length == this->_capacity && !this->_grow())
+ return false;
+
+ T *dst = this->_data + index;
+ memmove(dst + 1, dst, this->_length - index);
+ memcpy(dst, &item, sizeof(T));
+
+ ++this->_length;
+ return true;
+ }
+
+ //! @brief Append @a item to vector.
+ bool append(const T &item)
+ {
+ if (this->_length == this->_capacity && !this->_grow())
+ return false;
+
+ memcpy(this->_data + this->_length, &item, sizeof(T));
+
+ ++this->_length;
+ return true;
+ }
+
+ //! @brief Get index of @a val or kInvalidSize if not found.
+ size_t indexOf(const T &val) const
+ {
+ for (size_t i = 0, len = this->_length; i < len; ++i)
+ if (this->_data[i] == val)
+ return i;
+ return kInvalidSize;
+ }
+
+ //! @brief Remove element at index @a i.
+ void removeAt(size_t i)
+ {
+ ASMJIT_ASSERT(i < this->_length);
+
+ T *dst = this->_data + i;
+ --this->_length;
+ memmove(dst, dst + 1, this->_length - i);
+ }
+
+ //! @brief Swap this pod-vector with @a other.
+ void swap(PodVector<T> &other)
+ {
+ T *_tmp_data = this->_data;
+ size_t _tmp_length = this->_length;
+ size_t _tmp_capacity = this->_capacity;
+
+ this->_data = other._data;
+ this->_length = other._length;
+ this->_capacity = other._capacity;
+
+ other._data = _tmp_data;
+ other._length = _tmp_length;
+ other._capacity = _tmp_capacity;
+ }
+
+ //! @brief Get item at position @a i.
+ T &operator[](size_t i)
+ {
+ ASMJIT_ASSERT(i < this->_length);
+ return this->_data[i];
+ }
+ //! @brief Get item at position @a i.
+ const T &operator[](size_t i) const
+ {
+ ASMJIT_ASSERT(i < this->_length);
+ return this->_data[i];
+ }
+
+ //! @brief Append the item and return address so it can be initialized.
+ T *newItem()
+ {
+ if (this->_length == this->_capacity && !this->_grow())
+ return nullptr;
+ return this->_data + this->_length++;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Private]
+ // --------------------------------------------------------------------------
+
+ //! @brief Called to grow internal array.
+ bool _grow()
+ {
+ return this->_realloc(this->_capacity < 16 ? 16 : this->_capacity * 2);
+ }
+
+ //! @brief Realloc internal array to fit @a to items.
+ bool _realloc(size_t to)
+ {
+ ASMJIT_ASSERT(to >= this->_length);
+
+ T *p = reinterpret_cast<T *>(this->_data ? ASMJIT_REALLOC(this->_data, to * sizeof(T)) : ASMJIT_MALLOC(to * sizeof(T)));
+
+ if (!p)
+ return false;
+
+ this->_data = p;
+ this->_capacity = to;
+ return true;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Items data.
+ T *_data;
+ //! @brief Length of buffer (count of items in array).
+ size_t _length;
+ //! @brief Capacity of buffer (maximum items that can fit to current array).
+ size_t _capacity;
+};
+
+//! @}
+
+} // AsmJit namespace
+
+#endif // _ASMJIT_CORE_PODVECTOR_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/stringbuilder.cpp
@@ -1,1 +1,385 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/defs.h"
+#include "../core/intutil.h"
+#include "../core/stringbuilder.h"
+
+// [Dependencies - C]
+#include <cstdarg>
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+// Should be placed in read-only memory.
+static const char StringBuilder_empty[4] = { 0 };
+
+// ============================================================================
+// [AsmJit::StringBuilder - Construction / Destruction]
+// ============================================================================
+
+StringBuilder::StringBuilder() : _data(const_cast<char *>(StringBuilder_empty)), _length(0), _capacity(0), _canFree(false)
+{
+}
+
+StringBuilder::~StringBuilder()
+{
+ if (this->_canFree)
+ ASMJIT_FREE(this->_data);
+}
+
+// ============================================================================
+// [AsmJit::StringBuilder - Prepare / Reserve]
+// ============================================================================
+
+char *StringBuilder::prepare(uint32_t op, size_t len)
+{
+ // --------------------------------------------------------------------------
+ // [Set]
+ // --------------------------------------------------------------------------
+
+ if (op == kStringBuilderOpSet)
+ {
+ // We don't care here, but we can't return a NULL pointer since it indicates
+ // failure in memory allocation.
+ if (!len)
+ {
+ if (this->_data != StringBuilder_empty)
+ this->_data[0] = 0;
+
+ this->_length = 0;
+ return this->_data;
+ }
+
+ if (this->_capacity < len)
+ {
+ if (len >= IntUtil::maxValue<size_t>() - sizeof(uintptr_t) * 2)
+ return nullptr;
+
+ size_t to = IntUtil::align(len, sizeof(uintptr_t));
+ if (to < 256 - sizeof(uintptr_t))
+ to = 256 - sizeof(uintptr_t);
+
+ char *newData = static_cast<char *>(ASMJIT_MALLOC(to + sizeof(uintptr_t)));
+ if (!newData)
+ {
+ this->clear();
+ return nullptr;
+ }
+
+ if (this->_canFree)
+ ASMJIT_FREE(this->_data);
+
+ this->_data = newData;
+ this->_capacity = to + sizeof(uintptr_t) - 1;
+ this->_canFree = true;
+ }
+
+ this->_data[len] = 0;
+ this->_length = len;
+
+ ASMJIT_ASSERT(this->_length <= this->_capacity);
+ return this->_data;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Append]
+ // --------------------------------------------------------------------------
+
+ else
+ {
+ // We don't care here, but we can't return a NULL pointer since it indicates
+ // failure in memory allocation.
+ if (!len)
+ return this->_data + this->_length;
+
+ // Overflow.
+ if (IntUtil::maxValue<size_t>() - sizeof(uintptr_t) * 2 - this->_length < len)
+ return nullptr;
+
+ size_t after = this->_length + len;
+ if (this->_capacity < after)
+ {
+ size_t to = this->_capacity;
+
+ if (to < 256)
+ to = 256;
+
+ while (to < 1024 * 1024 && to < after)
+ to *= 2;
+
+ if (to < after)
+ {
+ to = after;
+ if (to < IntUtil::maxValue<size_t>() - 1024 * 32)
+ to = IntUtil::align<size_t>(to, 1024 * 32);
+ }
+
+ to = IntUtil::align(to, sizeof(uintptr_t));
+ char *newData = static_cast<char *>(ASMJIT_MALLOC(to + sizeof(uintptr_t)));
+
+ if (!newData)
+ return nullptr;
+
+ ::memcpy(newData, this->_data, this->_length);
+
+ if (this->_canFree)
+ ASMJIT_FREE(this->_data);
+
+ this->_data = newData;
+ this->_capacity = to + sizeof(uintptr_t) - 1;
+ this->_canFree = true;
+ }
+
+ char *ret = this->_data + this->_length;
+ this->_data[after] = 0;
+ this->_length = after;
+
+ ASMJIT_ASSERT(this->_length <= this->_capacity);
+ return ret;
+ }
+}
+
+bool StringBuilder::reserve(size_t to)
+{
+ if (this->_capacity >= to)
+ return true;
+
+ if (to >= IntUtil::maxValue<size_t>() - sizeof(uintptr_t) * 2)
+ return false;
+
+ to = IntUtil::align(to, sizeof(uintptr_t));
+
+ char *newData = static_cast<char *>(ASMJIT_MALLOC(to + sizeof(uintptr_t)));
+ if (!newData)
+ return false;
+
+ ::memcpy(newData, this->_data, this->_length + 1);
+ if (this->_canFree)
+ ASMJIT_FREE(this->_data);
+
+ this->_data = newData;
+ this->_capacity = to + sizeof(uintptr_t) - 1;
+ this->_canFree = true;
+ return true;
+}
+
+// ============================================================================
+// [AsmJit::StringBuilder - Clear]
+// ============================================================================
+
+void StringBuilder::clear()
+{
+ if (this->_data != StringBuilder_empty)
+ this->_data[0] = 0;
+ this->_length = 0;
+}
+
+// ============================================================================
+// [AsmJit::StringBuilder - Methods]
+// ============================================================================
+
+bool StringBuilder::_opString(uint32_t op, const char *str, size_t len)
+{
+ if (len == kInvalidSize)
+ len = ::strlen(str);
+
+ char *p = this->prepare(op, len);
+ if (!p)
+ return false;
+
+ ::memcpy(p, str, len);
+ return true;
+}
+
+bool StringBuilder::_opChars(uint32_t op, char c, size_t len)
+{
+ char *p = this->prepare(op, len);
+ if (!p)
+ return false;
+
+ ::memset(p, c, len);
+ return true;
+}
+
+static const char StringBuilder_numbers[] = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ";
+
+bool StringBuilder::_opNumber(uint32_t op, uint64_t i, uint32_t base, size_t width, uint32_t flags)
+{
+ if (base < 2 || base > 36)
+ base = 10;
+
+ char buf[128];
+ char *p = buf + ASMJIT_ARRAY_SIZE(buf);
+
+ uint64_t orig = i;
+ char sign = 0;
+
+ // --------------------------------------------------------------------------
+ // [Sign]
+ // --------------------------------------------------------------------------
+
+ if ((flags & kStringBuilderNumSigned) && static_cast<int64_t>(i) < 0)
+ {
+ i = static_cast<uint64_t>(-static_cast<int64_t>(i));
+ sign = '-';
+ }
+ else if (flags & kStringBuilderNumShowSign)
+ sign = '+';
+ else if (flags & kStringBuilderNumShowSpace)
+ sign = ' ';
+
+ // --------------------------------------------------------------------------
+ // [Number]
+ // --------------------------------------------------------------------------
+
+ do
+ {
+ uint64_t d = i / base;
+ uint64_t r = i % base;
+
+ *--p = StringBuilder_numbers[r];
+ i = d;
+ } while (i);
+
+ size_t numberLength = static_cast<size_t>(buf + ASMJIT_ARRAY_SIZE(buf) - p);
+
+ // --------------------------------------------------------------------------
+ // [Alternate Form]
+ // --------------------------------------------------------------------------
+
+ if (flags & kStringBuilderNumAlternate)
+ {
+ if (base == 8 && orig)
+ *--p = '0';
+ if (base == 16)
+ {
+ *--p = 'x';
+ *--p = '0';
+ }
+ }
+
+ // --------------------------------------------------------------------------
+ // [Width]
+ // --------------------------------------------------------------------------
+
+ if (sign)
+ *--p = sign;
+
+ if (width > 256)
+ width = 256;
+
+ if (width <= numberLength)
+ width = 0;
+ else
+ width -= numberLength;
+
+ // --------------------------------------------------------------------------
+ // [Write]
+ // --------------------------------------------------------------------------
+
+ size_t prefixLength = static_cast<size_t>(buf + ASMJIT_ARRAY_SIZE(buf) - p) - numberLength;
+ char *data = this->prepare(op, prefixLength + width + numberLength);
+
+ if (!data)
+ return false;
+
+ ::memcpy(data, p, prefixLength);
+ data += prefixLength;
+
+ ::memset(data, '0', width);
+ data += width;
+
+ ::memcpy(data, p + prefixLength, numberLength);
+ return true;
+}
+
+bool StringBuilder::_opHex(uint32_t op, const void *data, size_t len)
+{
+ if (len >= IntUtil::maxValue<size_t>() / 2)
+ return false;
+
+ char *dst = this->prepare(op, len);
+ if (!dst)
+ return false;
+
+ const char *src = static_cast<const char *>(data);
+ for (size_t i = 0; i < len; ++i, dst += 2, ++src)
+ {
+ dst[0] = StringBuilder_numbers[(src[0] >> 4) & 0xF];
+ dst[1] = StringBuilder_numbers[src[0] & 0xF];
+ }
+
+ return true;
+}
+
+bool StringBuilder::_opVFormat(uint32_t op, const char *fmt, va_list ap)
+{
+ char buf[1024];
+
+ vsnprintf(buf, ASMJIT_ARRAY_SIZE(buf), fmt, ap);
+ buf[ASMJIT_ARRAY_SIZE(buf) - 1] = 0;
+
+ return this->_opString(op, buf);
+}
+
+bool StringBuilder::setFormat(const char *fmt, ...)
+{
+ va_list ap;
+ va_start(ap, fmt);
+ bool result = this->_opVFormat(kStringBuilderOpSet, fmt, ap);
+ va_end(ap);
+
+ return result;
+}
+
+bool StringBuilder::appendFormat(const char *fmt, ...)
+{
+ va_list ap;
+ va_start(ap, fmt);
+ bool result = _opVFormat(kStringBuilderOpAppend, fmt, ap);
+ va_end(ap);
+
+ return result;
+}
+
+bool StringBuilder::eq(const char *str, size_t len) const
+{
+ const char *aData = this->_data;
+ const char *bData = str;
+
+ size_t aLength = this->_length;
+ size_t bLength = len;
+
+ if (bLength == kInvalidSize)
+ {
+ size_t i;
+ for (i = 0; i < aLength; ++i)
+ if (aData[i] != bData[i] || !bData[i])
+ return false;
+
+ return !bData[i];
+ }
+ else
+ {
+ if (aLength != bLength)
+ return false;
+
+ return !::memcmp(aData, bData, aLength);
+ }
+}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/stringbuilder.h
@@ -1,1 +1,184 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+// [Guard]
+#ifndef _ASMJIT_CORE_STRINGBUILDER_H
+#define _ASMJIT_CORE_STRINGBUILDER_H
+
+// [Dependencies - AsmJit]
+#include "../core/assert.h"
+#include "../core/defs.h"
+
+namespace AsmJit
+{
+
+//! @addtogroup AsmJit_Core
+//! @{
+
+// ============================================================================
+// [AsmJit::StringBuilder]
+// ============================================================================
+
+//! @brief String builder.
+//!
+//! String builder was designed to be able to build a string using append like
+//! operation to append numbers, other strings, or signle characters. It can
+//! allocate it's own buffer or use a buffer created on the stack.
+//!
+//! String builder contains method specific to AsmJit functionality, used for
+//! logging or HTML output.
+struct StringBuilder
+{
+ ASMJIT_NO_COPY(StringBuilder)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API StringBuilder();
+ ASMJIT_API ~StringBuilder();
+
+ StringBuilder(const _DontInitialize &) { }
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get string builder capacity.
+ size_t getCapacity() const { return this->_capacity; }
+
+ //! @brief Get length.
+ size_t getLength() const { return this->_length; }
+
+ //! @brief Get null-terminated string data.
+ char *getData() { return this->_data; }
+
+ //! @brief Get null-terminated string data (const).
+ const char *getData() const { return this->_data; }
+
+ // --------------------------------------------------------------------------
+ // [Prepare / Reserve]
+ // --------------------------------------------------------------------------
+
+ //! @brief Prepare to set/append.
+ ASMJIT_API char *prepare(uint32_t op, size_t len);
+
+ //! @brief Reserve @a to bytes in string builder.
+ ASMJIT_API bool reserve(size_t to);
+
+ // --------------------------------------------------------------------------
+ // [Clear]
+ // --------------------------------------------------------------------------
+
+ //! @brief Clear the content in String builder.
+ ASMJIT_API void clear();
+
+ // --------------------------------------------------------------------------
+ // [Methods]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API bool _opString(uint32_t op, const char *str, size_t len = kInvalidSize);
+ ASMJIT_API bool _opVFormat(uint32_t op, const char *fmt, va_list ap);
+ ASMJIT_API bool _opChars(uint32_t op, char c, size_t len);
+ ASMJIT_API bool _opNumber(uint32_t op, uint64_t i, uint32_t base = 0, size_t width = 0, uint32_t flags = 0);
+ ASMJIT_API bool _opHex(uint32_t op, const void *data, size_t length);
+
+ //! @brief Replace the current content by @a str of @a len.
+ bool setString(const char *str, size_t len = kInvalidSize) { return this->_opString(kStringBuilderOpSet, str, len); }
+
+ //! @brief Replace the current content by formatted string @a fmt.
+ bool setVFormat(const char *fmt, va_list ap) { return this->_opVFormat(kStringBuilderOpSet, fmt, ap); }
+
+ //! @brief Replace the current content by formatted string @a fmt.
+ ASMJIT_API bool setFormat(const char *fmt, ...);
+
+ //! @brief Replace the current content by @a c of @a len.
+ bool setChars(char c, size_t len) { return this->_opChars(kStringBuilderOpSet, c, len); }
+
+ //! @brief Replace the current content by @a i..
+ bool setNumber(uint64_t i, uint32_t base = 0, size_t width = 0, uint32_t flags = 0) { return this->_opNumber(kStringBuilderOpSet, i, base, width, flags); }
+
+ //! @brief Append @a str of @a len.
+ bool appendString(const char *str, size_t len = kInvalidSize) { return this->_opString(kStringBuilderOpAppend, str, len); }
+
+ //! @brief Append a formatted string @a fmt to the current content.
+ bool appendVFormat(const char *fmt, va_list ap) { return this->_opVFormat(kStringBuilderOpAppend, fmt, ap); }
+
+ //! @brief Append a formatted string @a fmt to the current content.
+ ASMJIT_API bool appendFormat(const char *fmt, ...);
+
+ //! @brief Append @a c of @a len.
+ bool appendChars(char c, size_t len) { return this->_opChars(kStringBuilderOpAppend, c, len); }
+
+ //! @brief Append @a i.
+ bool appendNumber(uint64_t i, uint32_t base = 0, size_t width = 0, uint32_t flags = 0) { return this->_opNumber(kStringBuilderOpAppend, i, base, width, flags); }
+
+ //! @brief Check for equality with other @a str.
+ ASMJIT_API bool eq(const char *str, size_t len = kInvalidSize) const;
+
+ //! @brief Check for equality with StringBuilder @a other.
+ bool eq(const StringBuilder &other) const { return this->eq(other._data); }
+
+ // --------------------------------------------------------------------------
+ // [Operator Overload]
+ // --------------------------------------------------------------------------
+
+ bool operator==(const StringBuilder &other) const { return this->eq(other); }
+ bool operator!=(const StringBuilder &other) const { return !this->eq(other); }
+
+ bool operator==(const char *str) const { return this->eq(str); }
+ bool operator!=(const char *str) const { return !this->eq(str); }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief String data.
+ char *_data;
+ //! @brief Length.
+ size_t _length;
+ //! @brief Capacity.
+ size_t _capacity;
+ //! @brief Whether the string can be freed.
+ size_t _canFree;
+};
+
+// ============================================================================
+// [AsmJit::StringBuilderT]
+// ============================================================================
+
+template<size_t N> struct StringBuilderT : public StringBuilder
+{
+ ASMJIT_NO_COPY(StringBuilderT<N>)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ StringBuilderT() : StringBuilder(_DontInitialize())
+ {
+ this->_data = this->_embeddedData;
+ this->_data[0] = 0;
+
+ this->_length = 0;
+ this->_capacity = 0;
+ this->_canFree = false;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Embedded data.
+ char _embeddedData[(N + sizeof(uintptr_t)) & ~(sizeof(uintptr_t) - 1)];
+};
+
+//! @}
+
+} // AsmJit namespace
+
+#endif // _ASMJIT_CORE_STRINGBUILDER_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/stringutil.cpp
@@ -1,1 +1,94 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/assert.h"
+#include "../core/stringutil.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [AsmJit::StringUtil]
+// ============================================================================
+
+static const char letters[] = "0123456789ABCDEF";
+
+char *StringUtil::copy(char *dst, const char *src, size_t len)
+{
+ if (!src)
+ return dst;
+
+ if (len == kInvalidSize)
+ {
+ while (*src)
+ *dst++ = *src++;
+ }
+ else
+ {
+ memcpy(dst, src, len);
+ dst += len;
+ }
+
+ return dst;
+}
+
+char *StringUtil::fill(char *dst, int c, size_t len)
+{
+ memset(dst, c, len);
+ return dst + len;
+}
+
+char *StringUtil::hex(char *dst, const uint8_t *src, size_t len)
+{
+ for (size_t i = len; i; --i, dst += 2, ++src)
+ {
+ dst[0] = letters[(src[0] >> 4) & 0xF];
+ dst[1] = letters[src[0] & 0xF];
+ }
+
+ return dst;
+}
+
+// Not too efficient, but this is mainly for debugging:)
+char *StringUtil::utoa(char *dst, uintptr_t i, size_t base)
+{
+ ASMJIT_ASSERT(base <= 16);
+
+ char buf[128];
+ char *p = buf + 128;
+
+ do
+ {
+ uintptr_t b = i % base;
+ *--p = letters[b];
+ i /= base;
+ } while (i);
+
+ return StringUtil::copy(dst, p, static_cast<size_t>(buf + 128 - p));
+}
+
+char *StringUtil::itoa(char *dst, intptr_t i, size_t base)
+{
+ if (i < 0)
+ {
+ *dst++ = '-';
+ i = -i;
+ }
+
+ return StringUtil::utoa(dst, static_cast<uintptr_t>(i), base);
+}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/stringutil.h
@@ -1,1 +1,46 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+// [Guard]
+#ifndef _ASMJIT_CORE_STRINGUTIL_H
+#define _ASMJIT_CORE_STRINGUTIL_H
+
+// [Dependencies - AsmJit]
+#include "../core/defs.h"
+
+namespace AsmJit
+{
+
+//! @addtogroup AsmJit_Core
+//! @{
+
+// ============================================================================
+// [AsmJit::StringUtil]
+// ============================================================================
+
+//! @brief String utilities.
+struct StringUtil
+{
+ ASMJIT_API static char *copy(char *dst, const char *src, size_t len = kInvalidSize);
+ ASMJIT_API static char *fill(char *dst, int c, size_t len);
+ ASMJIT_API static char *hex(char *dst, const uint8_t *src, size_t len);
+
+ ASMJIT_API static char *utoa(char *dst, uintptr_t i, size_t base = 10);
+ ASMJIT_API static char *itoa(char *dst, intptr_t i, size_t base = 10);
+
+ static void memset32(uint32_t *p, uint32_t c, size_t len)
+ {
+ for (size_t i = 0; i < len; ++i)
+ p[i] = c;
+ }
+};
+
+//! @}
+
+} // AsmJit namespace
+
+#endif // _ASMJIT_CORE_STRINGUTIL_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/virtualmemory.cpp
@@ -1,1 +1,163 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/intutil.h"
+#include "../core/virtualmemory.h"
+
+// [Dependencies - Windows]
+#ifdef ASMJIT_WINDOWS
+# include "windowsh_wrapper.h"
+#endif // ASMJIT_WINDOWS
+
+// [Dependencies - Posix]
+#ifdef ASMJIT_POSIX
+# include <sys/types.h>
+# include <sys/mman.h>
+# include <unistd.h>
+#endif // ASMJIT_POSIX
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [AsmJit::VirtualMemory - Windows]
+// ============================================================================
+
+#ifdef ASMJIT_WINDOWS
+struct VirtualMemoryLocal
+{
+ VirtualMemoryLocal()
+ {
+ SYSTEM_INFO info;
+ GetSystemInfo(&info);
+
+ this->alignment = info.dwAllocationGranularity;
+ this->pageSize = IntUtil::roundUpToPowerOf2<uint32_t>(info.dwPageSize);
+ }
+
+ size_t alignment;
+ size_t pageSize;
+};
+
+static VirtualMemoryLocal &vm()
+{
+ static VirtualMemoryLocal vm;
+ return vm;
+};
+
+void *VirtualMemory::alloc(size_t length, size_t *allocated, bool canExecute)
+{
+ return allocProcessMemory(GetCurrentProcess(), length, allocated, canExecute);
+}
+
+void VirtualMemory::free(void *addr, size_t length)
+{
+ return freeProcessMemory(GetCurrentProcess(), addr, length);
+}
+
+void *VirtualMemory::allocProcessMemory(HANDLE hProcess, size_t length, size_t *allocated, bool canExecute)
+{
+ // VirtualAlloc rounds allocated size to page size automatically.
+ size_t msize = IntUtil::roundUp(length, vm().pageSize);
+
+ // Windows XP SP2 / Vista allow Data Excution Prevention (DEP).
+ WORD protect = canExecute ? PAGE_EXECUTE_READWRITE : PAGE_READWRITE;
+ LPVOID mbase = VirtualAllocEx(hProcess, nullptr, msize, MEM_COMMIT | MEM_RESERVE, protect);
+ if (!mbase)
+ return nullptr;
+
+ ASMJIT_ASSERT(IntUtil::isAligned<size_t>(reinterpret_cast<size_t>(mbase), vm().alignment));
+
+ if (allocated)
+ *allocated = msize;
+ return mbase;
+}
+
+void VirtualMemory::freeProcessMemory(HANDLE hProcess, void *addr, size_t /* length */)
+{
+ VirtualFreeEx(hProcess, addr, 0, MEM_RELEASE);
+}
+
+size_t VirtualMemory::getAlignment()
+{
+ return vm().alignment;
+}
+
+size_t VirtualMemory::getPageSize()
+{
+ return vm().pageSize;
+}
+#endif // ASMJIT_WINDOWS
+
+// ============================================================================
+// [AsmJit::VirtualMemory - Posix]
+// ============================================================================
+
+#ifdef ASMJIT_POSIX
+
+// MacOS uses MAP_ANON instead of MAP_ANONYMOUS.
+#ifndef MAP_ANONYMOUS
+# define MAP_ANONYMOUS MAP_ANON
+#endif // MAP_ANONYMOUS
+
+struct VirtualMemoryLocal
+{
+ VirtualMemoryLocal()
+ {
+ this->alignment = this->pageSize = ::getpagesize();
+ }
+
+ size_t alignment;
+ size_t pageSize;
+};
+
+static VirtualMemoryLocal &vm()
+{
+ static VirtualMemoryLocal vm;
+ return vm;
+}
+
+void *VirtualMemory::alloc(size_t length, size_t *allocated, bool canExecute)
+{
+ size_t msize = IntUtil::roundUp<size_t>(length, vm().pageSize);
+ int protection = PROT_READ | PROT_WRITE | (canExecute ? PROT_EXEC : 0);
+
+ void *mbase = ::mmap(nullptr, msize, protection, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+ if (mbase == MAP_FAILED)
+ return nullptr;
+
+ if (allocated)
+ *allocated = msize;
+ return mbase;
+}
+
+void VirtualMemory::free(void *addr, size_t length)
+{
+ munmap(addr, length);
+}
+
+size_t VirtualMemory::getAlignment()
+{
+ return vm().alignment;
+}
+
+size_t VirtualMemory::getPageSize()
+{
+ return vm().pageSize;
+}
+#endif // ASMJIT_POSIX
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/virtualmemory.h
@@ -1,1 +1,82 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+// [Guard]
+#ifndef _ASMJIT_CORE_VIRTUALMEMORY_H
+#define _ASMJIT_CORE_VIRTUALMEMORY_H
+
+// [Dependencies - AsmJit]
+#include "../core/build.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+//! @addtogroup AsmJit_Core
+//! @{
+
+// ============================================================================
+// [AsmJit::VirtualMemory]
+// ============================================================================
+
+//! @brief Class that helps with allocating memory for executing code
+//! generated by JIT compiler.
+//!
+//! There are defined functions that provides facility to allocate and free
+//! memory where can be executed code. If processor and operating system
+//! supports execution protection then you can't run code from normally
+//! malloc()'ed memory.
+//!
+//! Functions are internally implemented by operating system dependent way.
+//! VirtualAlloc() function is used for Windows operating system and mmap()
+//! for posix ones. If you want to study or create your own functions, look
+//! at VirtualAlloc() or mmap() documentation (depends on you target OS).
+//!
+//! Under posix operating systems is also useable mprotect() function, that
+//! can enable execution protection to malloc()'ed memory block.
+struct VirtualMemory
+{
+ //! @brief Allocate virtual memory.
+ //!
+ //! Pages are readable/writeable, but they are not guaranteed to be
+ //! executable unless 'canExecute' is true. Returns the address of
+ //! allocated memory, or NULL if failed.
+ ASMJIT_API static void *alloc(size_t length, size_t *allocated, bool canExecute);
+
+ //! @brief Free memory allocated by @c alloc()
+ ASMJIT_API static void free(void *addr, size_t length);
+
+#ifdef ASMJIT_WINDOWS
+ //! @brief Allocate virtual memory of @a hProcess.
+ //!
+ //! @note This function is Windows specific.
+ ASMJIT_API static void *allocProcessMemory(HANDLE hProcess, size_t length, size_t *allocated, bool canExecute);
+
+ //! @brief Free virtual memory of @a hProcess.
+ //!
+ //! @note This function is Windows specific.
+ ASMJIT_API static void freeProcessMemory(HANDLE hProcess, void *addr, size_t length);
+#endif // ASMJIT_WINDOWS
+
+ //! @brief Get the alignment guaranteed by alloc().
+ ASMJIT_API static size_t getAlignment();
+
+ //! @brief Get size of single page.
+ ASMJIT_API static size_t getPageSize();
+};
+
+//! @}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_CORE_VIRTUALMEMORY_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/zonememory.cpp
@@ -1,1 +1,130 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/defs.h"
+#include "../core/intutil.h"
+#include "../core/zonememory.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [AsmJit::ZoneMemory]
+// ============================================================================
+
+ZoneMemory::ZoneMemory(size_t chunkSize)
+{
+ this->_chunks = nullptr;
+ this->_total = 0;
+ this->_chunkSize = chunkSize;
+}
+
+ZoneMemory::~ZoneMemory()
+{
+ this->reset();
+}
+
+void *ZoneMemory::alloc(size_t size)
+{
+ ZoneChunk *cur = this->_chunks;
+
+ // Align to 4 or 8 bytes.
+ size = IntUtil::align(size, sizeof(size_t));
+
+ if (!cur || cur->getRemainingBytes() < size)
+ {
+ size_t chSize = this->_chunkSize;
+
+ if (chSize < size)
+ chSize = size;
+
+ cur = static_cast<ZoneChunk *>(ASMJIT_MALLOC(sizeof(ZoneChunk) - sizeof(void *) + chSize));
+ if (!cur)
+ return nullptr;
+
+ cur->prev = this->_chunks;
+ cur->pos = 0;
+ cur->size = chSize;
+
+ this->_chunks = cur;
+ }
+
+ uint8_t *p = cur->data + cur->pos;
+ cur->pos += size;
+ this->_total += size;
+
+ ASMJIT_ASSERT(cur->pos <= cur->size);
+ return static_cast<void *>(p);
+}
+
+char *ZoneMemory::sdup(const char *str)
+{
+ if (!str)
+ return nullptr;
+
+ size_t len = strlen(str);
+ if (!len)
+ return nullptr;
+
+ // Include NULL terminator and limit string length.
+ if (++len > 256)
+ len = 256;
+
+ char *m = static_cast<char *>(alloc(IntUtil::align<size_t>(len, 16)));
+ if (!m)
+ return nullptr;
+
+ memcpy(m, str, len);
+ m[len - 1] = 0;
+ return m;
+}
+
+void ZoneMemory::clear()
+{
+ ZoneChunk *cur = this->_chunks;
+
+ if (!cur)
+ return;
+
+ cur = cur->prev;
+ while (cur)
+ {
+ ZoneChunk *prev = cur->prev;
+ ASMJIT_FREE(cur);
+ cur = prev;
+ }
+
+ this->_chunks->pos = 0;
+ this->_chunks->prev = nullptr;
+ this->_total = 0;
+}
+
+void ZoneMemory::reset()
+{
+ ZoneChunk *cur = this->_chunks;
+
+ this->_chunks = nullptr;
+ this->_total = 0;
+
+ while (cur)
+ {
+ ZoneChunk *prev = cur->prev;
+ ASMJIT_FREE(cur);
+ cur = prev;
+ }
+}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/core/zonememory.h
@@ -1,1 +1,153 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+// [Guard]
+#ifndef _ASMJIT_CORE_ZONEMEMORY_H
+#define _ASMJIT_CORE_ZONEMEMORY_H
+
+// [Dependencies - AsmJit]
+#include "../core/build.h"
+
+namespace AsmJit
+{
+
+//! @addtogroup AsmJit_Core
+//! @{
+
+// ============================================================================
+// [AsmJit::ZoneChunk]
+// ============================================================================
+
+//! @internal
+//!
+//! @brief One allocated chunk of memory.
+struct ZoneChunk
+{
+ // --------------------------------------------------------------------------
+ // [Methods]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get count of remaining (unused) bytes in chunk.
+ size_t getRemainingBytes() const { return this->size - this->pos; }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Link to previous chunk.
+ ZoneChunk *prev;
+ //! @brief Position in this chunk.
+ size_t pos;
+ //! @brief Size of this chunk (in bytes).
+ size_t size;
+
+ //! @brief Data.
+ uint8_t data[sizeof(void *)];
+};
+
+// ============================================================================
+// [AsmJit::ZoneMemory]
+// ============================================================================
+
+//! @brief Memory allocator designed to fast alloc memory that will be freed
+//! in one step.
+//!
+//! @note This is hackery for performance. Concept is that objects created
+//! by @c ZoneMemory are freed all at once. This means that lifetime of
+//! these objects are the same as the zone object itself.
+struct ZoneMemory
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create new instance of @c ZoneMemory.
+ //! @param chunkSize Default size for one zone chunk.
+ ASMJIT_API ZoneMemory(size_t chunkSize);
+
+ //! @brief Destroy @ref ZoneMemory instance.
+ ASMJIT_API ~ZoneMemory();
+
+ // --------------------------------------------------------------------------
+ // [Methods]
+ // --------------------------------------------------------------------------
+
+ //! @brief Allocate @c size bytes of memory and return pointer to it.
+ //!
+ //! Pointer allocated by this way will be valid until @c ZoneMemory object
+ //! is destroyed. To create class by this way use placement @c new and
+ //! @c delete operators:
+ //!
+ //! @code
+ //! // Example of allocating simple class
+ //!
+ //! // Your class
+ //! class Object
+ //! {
+ //! // members...
+ //! };
+ //!
+ //! // Your function
+ //! void f()
+ //! {
+ //! // We are using AsmJit namespace
+ //! using namespace AsmJit
+ //!
+ //! // Create zone object with chunk size of 65536 bytes.
+ //! ZoneMemory zone(65536);
+ //!
+ //! // Create your objects using zone object allocating, for example:
+ //! Object* obj = new(zone.alloc(sizeof(YourClass))) Object();
+ //!
+ //! // ... lifetime of your objects ...
+ //!
+ //! // Destroy your objects:
+ //! obj->~Object();
+ //!
+ //! // ZoneMemory destructor will free all memory allocated through it,
+ //! // alternative is to call @c zone.reset().
+ //! }
+ //! @endcode
+ ASMJIT_API void *alloc(size_t size);
+
+ //! @brief Helper to duplicate string.
+ ASMJIT_API char *sdup(const char *str);
+
+ //! @brief Free all allocated memory except first block that remains for reuse.
+ //!
+ //! Note that this method will invalidate all instances using this memory
+ //! allocated by this zone instance.
+ ASMJIT_API void clear();
+
+ //! @brief Free all allocated memory at once.
+ //!
+ //! Note that this method will invalidate all instances using this memory
+ //! allocated by this zone instance.
+ ASMJIT_API void reset();
+
+ //! @brief Get total size of allocated objects - by @c alloc().
+ size_t getTotal() const { return this->_total; }
+ //! @brief Get (default) chunk size.
+ size_t getChunkSize() const { return this->_chunkSize; }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Last allocated chunk of memory.
+ ZoneChunk *_chunks;
+ //! @brief Total size of allocated objects - by @c alloc() method.
+ size_t _total;
+ //! @brief One chunk size.
+ size_t _chunkSize;
+};
+
+//! @}
+
+} // AsmJit namespace
+
+#endif // _ASMJIT_CORE_ZONEMEMORY_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86.h
@@ -1,1 +1,27 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+// [Guard]
+#ifndef _ASMJIT_X86_H
+#define _ASMJIT_X86_H
+
+// [Dependencies - AsmJit]
+#include "core.h"
+
+#include "x86/x86assembler.h"
+#include "x86/x86compiler.h"
+#include "x86/x86compilercontext.h"
+#include "x86/x86compilerfunc.h"
+#include "x86/x86compileritem.h"
+#include "x86/x86cpuinfo.h"
+#include "x86/x86defs.h"
+#include "x86/x86func.h"
+#include "x86/x86operand.h"
+#include "x86/x86util.h"
+
+// [Guard]
+#endif // _ASMJIT_X86_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86/x86assembler.cpp
@@ -1,1 +1,3043 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/assembler.h"
+#include "../core/context.h"
+#include "../core/cpuinfo.h"
+#include "../core/defs.h"
+#include "../core/intutil.h"
+#include "../core/logger.h"
+#include "../core/memorymanager.h"
+#include "../core/memorymarker.h"
+#include "../core/stringutil.h"
+
+#include "../x86/x86assembler.h"
+#include "../x86/x86cpuinfo.h"
+#include "../x86/x86defs.h"
+#include "../x86/x86operand.h"
+#include "../x86/x86util.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit {
+
+// ============================================================================
+// [Constants]
+// ============================================================================
+
+enum { kMaxCommentLength = 80 };
+
+// ============================================================================
+// [AsmJit::X64TrampolineWriter]
+// ============================================================================
+
+#if defined(ASMJIT_X64)
+//! @brief Class used to determine size of trampoline and as trampoline writer.
+struct X64TrampolineWriter
+{
+ // Size of trampoline
+ enum
+ {
+ kSizeJmp = 6,
+ kSizeAddr = 8,
+ kSizeTotal = kSizeJmp + kSizeAddr
+ };
+
+ // Write trampoline into code at address @a code that will jump to @a target.
+ static void writeTrampoline(uint8_t* code, uint64_t target)
+ {
+ code[0] = 0xFF; // Jmp OpCode.
+ code[1] = 0x25; // ModM (RIP addressing).
+ ((uint32_t*)(code + 2))[0] = 0; // Offset (zero).
+ ((uint64_t*)(code + kSizeJmp))[0] = (uint64_t)target; // Absolute address.
+ }
+};
+#endif // ASMJIT_X64
+
+// ============================================================================
+// [AsmJit::X86Assembler - Construction / Destruction]
+// ============================================================================
+
+X86Assembler::X86Assembler(Context* context) :
+ Assembler(context)
+{
+ _properties = IntUtil::maskFromIndex(kX86PropertyOptimizedAlign);
+}
+
+X86Assembler::~X86Assembler()
+{
+}
+
+// ============================================================================
+// [AsmJit::X86Assembler - Buffer - Setters (X86-Extensions)]
+// ============================================================================
+
+void X86Assembler::setVarAt(size_t pos, sysint_t i, uint8_t isUnsigned, uint32_t size)
+{
+ if (size == 1 && !isUnsigned) setByteAt (pos, (int8_t )i);
+ else if (size == 1 && isUnsigned) setByteAt (pos, (uint8_t )i);
+ else if (size == 2 && !isUnsigned) setWordAt (pos, (int16_t )i);
+ else if (size == 2 && isUnsigned) setWordAt (pos, (uint16_t)i);
+ else if (size == 4 && !isUnsigned) setDWordAt(pos, (int32_t )i);
+ else if (size == 4 && isUnsigned) setDWordAt(pos, (uint32_t)i);
+
+#if defined(ASMJIT_X64)
+ else if (size == 8 && !isUnsigned) setQWordAt(pos, (int64_t )i);
+ else if (size == 8 && isUnsigned) setQWordAt(pos, (uint64_t)i);
+#endif // ASMJIT_X64
+
+ else
+ ASMJIT_ASSERT(0);
+}
+
+// ============================================================================
+// [AsmJit::X86Assembler - Emit]
+// ============================================================================
+
+void X86Assembler::_emitModM(
+ uint8_t opReg, const Mem& mem, sysint_t immSize)
+{
+ ASMJIT_ASSERT(mem.getType() == kOperandMem);
+
+ uint8_t baseReg = mem.getBase() & 0x7;
+ uint8_t indexReg = mem.getIndex() & 0x7;
+ sysint_t disp = mem.getDisplacement();
+ uint32_t shift = mem.getShift();
+
+ if (mem.getMemType() == kOperandMemNative)
+ {
+ // [base + displacemnt]
+ if (!mem.hasIndex())
+ {
+ // ESP/RSP/R12 == 4
+ if (baseReg == 4)
+ {
+ uint8_t mod = 0;
+
+ if (disp)
+ mod = IntUtil::isInt8(disp) ? 1 : 2;
+
+ _emitMod(mod, opReg, 4);
+ _emitSib(0, 4, 4);
+
+ if (disp)
+ {
+ if (IntUtil::isInt8(disp))
+ _emitByte((int8_t)disp);
+ else
+ _emitInt32((int32_t)disp);
+ }
+ }
+ // EBP/RBP/R13 == 5
+ else if (baseReg != 5 && !disp)
+ {
+ _emitMod(0, opReg, baseReg);
+ }
+ else if (IntUtil::isInt8(disp))
+ {
+ _emitMod(1, opReg, baseReg);
+ _emitByte((int8_t)disp);
+ }
+ else
+ {
+ _emitMod(2, opReg, baseReg);
+ _emitInt32((int32_t)disp);
+ }
+ }
+
+ // [base + index * scale + displacemnt]
+ else
+ {
+ // ASMJIT_ASSERT(indexReg != RID_ESP);
+
+ // EBP/RBP/R13 == 5
+ if (baseReg != 5 && !disp)
+ {
+ _emitMod(0, opReg, 4);
+ _emitSib(shift, indexReg, baseReg);
+ }
+ else if (IntUtil::isInt8(disp))
+ {
+ _emitMod(1, opReg, 4);
+ _emitSib(shift, indexReg, baseReg);
+ _emitByte((int8_t)disp);
+ }
+ else
+ {
+ _emitMod(2, opReg, 4);
+ _emitSib(shift, indexReg, baseReg);
+ _emitInt32((int32_t)disp);
+ }
+ }
+ }
+
+ // Address | 32-bit mode | 64-bit mode
+ // ------------------------------+-------------+---------------
+ // [displacement] | ABSOLUTE | RELATIVE (RIP)
+ // [index * scale + displacemnt] | ABSOLUTE | ABSOLUTE (ZERO EXTENDED)
+ else
+ {
+ // - In 32-bit mode the absolute addressing model is used.
+ // - In 64-bit mode the relative addressing model is used together with
+ // the absolute addressing. Main problem is that if instruction
+ // contains SIB then relative addressing (RIP) is not possible.
+
+#if defined(ASMJIT_X86)
+
+ if (mem.hasIndex())
+ {
+ // ASMJIT_ASSERT(mem.getMemIndex() != 4); // ESP/RSP == 4
+ _emitMod(0, opReg, 4);
+ _emitSib(shift, indexReg, 5);
+ }
+ else
+ {
+ _emitMod(0, opReg, 5);
+ }
+
+ // X86 uses absolute addressing model, all relative addresses will be
+ // relocated to absolute ones.
+ if (mem.getMemType() == kOperandMemLabel)
+ {
+ LabelData& l_data = _labels[mem._mem.base & kOperandIdValueMask];
+ RelocData r_data;
+ uint32_t relocId = _relocData.getLength();
+
+ // Relative addressing will be relocated to absolute address.
+ r_data.type = kRelocRelToAbs;
+ r_data.size = 4;
+ r_data.offset = getOffset();
+ r_data.destination = disp;
+
+ if (l_data.offset != -1)
+ {
+ // Bound label.
+ r_data.destination += l_data.offset;
+
+ // Add a dummy DWORD.
+ _emitInt32(0);
+ }
+ else
+ {
+ // Non-bound label.
+ _emitDisplacement(l_data, -4 - immSize, 4)->relocId = relocId;
+ }
+
+ _relocData.append(r_data);
+ }
+ else
+ {
+ // Absolute address
+ _emitInt32( (int32_t)((uint8_t*)mem._mem.target + disp) );
+ }
+
+#else
+
+ // X64 uses relative addressing model
+ if (mem.getMemType() == kOperandMemLabel)
+ {
+ LabelData& l_data = _labels[mem._mem.base & kOperandIdValueMask];
+
+ if (mem.hasIndex())
+ {
+ // Indexing is not possible.
+ setError(kErrorIllegalAddressing);
+ return;
+ }
+
+ // Relative address (RIP +/- displacement).
+ _emitMod(0, opReg, 5);
+
+ disp -= (4 + immSize);
+
+ if (l_data.offset != -1)
+ {
+ // Bound label.
+ disp += getOffset() - l_data.offset;
+
+ // Displacement is known.
+ _emitInt32((int32_t)disp);
+ }
+ else
+ {
+ // Non-bound label.
+ _emitDisplacement(l_data, disp, 4);
+ }
+ }
+ else
+ {
+ // Absolute address (truncated to 32-bits), this kind of address requires
+ // SIB byte (4).
+ _emitMod(0, opReg, 4);
+
+ if (mem.hasIndex())
+ {
+ // ASMJIT_ASSERT(mem.getMemIndex() != 4); // ESP/RSP == 4
+ _emitSib(shift, indexReg, 5);
+ }
+ else
+ {
+ _emitSib(0, 4, 5);
+ }
+
+ // Truncate to 32-bits.
+ sysuint_t target = (sysuint_t)((uint8_t*)mem._mem.target + disp);
+
+ if (target > (sysuint_t)0xFFFFFFFF)
+ {
+ if (_logger)
+ {
+ _logger->logString("*** ASSEMBER WARNING - Absolute address truncated to 32-bits.\n");
+ }
+ target &= 0xFFFFFFFF;
+ }
+
+ _emitInt32( (int32_t)((uint32_t)target) );
+ }
+
+#endif // ASMJIT_X64
+
+ }
+}
+
+void X86Assembler::_emitModRM(
+ uint8_t opReg, const Operand& op, sysint_t immSize)
+{
+ ASMJIT_ASSERT(op.getType() == kOperandReg || op.getType() == kOperandMem);
+
+ if (op.getType() == kOperandReg)
+ _emitModR(opReg, reinterpret_cast<const Reg&>(op).getRegCode());
+ else
+ _emitModM(opReg, reinterpret_cast<const Mem&>(op), immSize);
+}
+
+void X86Assembler::_emitSegmentPrefix(const Operand& rm)
+{
+ static const uint8_t segmentCode[6] =
+ {
+ 0x26, // ES
+ 0x2E, // SS
+ 0x36, // SS
+ 0x3E, // DS
+ 0x64, // FS
+ 0x65 // GS
+ };
+
+ if (!rm.isMem())
+ return;
+
+ uint32_t seg = reinterpret_cast<const Mem&>(rm).getSegment();
+ if (seg >= kX86RegNumSeg)
+ return;
+
+ _emitByte(segmentCode[seg]);
+}
+
+void X86Assembler::_emitX86Inl(
+ uint32_t opCode, uint8_t i16bit, uint8_t rexw, uint8_t reg, bool forceRexPrefix)
+{
+ // 16-bit prefix.
+ if (i16bit) _emitByte(0x66);
+
+ // Instruction prefix.
+ if (opCode & 0xFF000000) _emitByte((uint8_t)((opCode & 0xFF000000) >> 24));
+
+ // REX prefix.
+#if defined(ASMJIT_X64)
+ _emitRexR(rexw, 0, reg, forceRexPrefix);
+#endif // ASMJIT_X64
+
+ // Instruction opcodes.
+ if (opCode & 0x00FF0000) _emitByte((uint8_t)((opCode & 0x00FF0000) >> 16));
+ if (opCode & 0x0000FF00) _emitByte((uint8_t)((opCode & 0x0000FF00) >> 8));
+
+ _emitByte((uint8_t)(opCode & 0x000000FF) + (reg & 0x7));
+}
+
+void X86Assembler::_emitX86RM(
+ uint32_t opCode, uint8_t i16bit, uint8_t rexw, uint8_t o,
+ const Operand& op, sysint_t immSize, bool forceRexPrefix)
+{
+ // 16-bit prefix.
+ if (i16bit) _emitByte(0x66);
+
+ // Segment prefix.
+ _emitSegmentPrefix(op);
+
+ // Instruction prefix.
+ if (opCode & 0xFF000000) _emitByte((uint8_t)((opCode & 0xFF000000) >> 24));
+
+ // REX prefix.
+#if defined(ASMJIT_X64)
+ _emitRexRM(rexw, o, op, forceRexPrefix);
+#endif // ASMJIT_X64
+
+ // Instruction opcodes.
+ if (opCode & 0x00FF0000) _emitByte((uint8_t)((opCode & 0x00FF0000) >> 16));
+ if (opCode & 0x0000FF00) _emitByte((uint8_t)((opCode & 0x0000FF00) >> 8));
+ _emitByte((uint8_t)(opCode & 0x000000FF));
+
+ // Mod R/M.
+ _emitModRM(o, op, immSize);
+}
+
+void X86Assembler::_emitFpu(uint32_t opCode)
+{
+ _emitOpCode(opCode);
+}
+
+void X86Assembler::_emitFpuSTI(uint32_t opCode, uint32_t sti)
+{
+ // Illegal stack offset.
+ ASMJIT_ASSERT(0 <= sti && sti < 8);
+ _emitOpCode(opCode + sti);
+}
+
+void X86Assembler::_emitFpuMEM(uint32_t opCode, uint8_t opReg, const Mem& mem)
+{
+ // Segment prefix.
+ _emitSegmentPrefix(mem);
+
+ // Instruction prefix.
+ if (opCode & 0xFF000000) _emitByte((uint8_t)((opCode & 0xFF000000) >> 24));
+
+ // REX prefix.
+#if defined(ASMJIT_X64)
+ _emitRexRM(0, opReg, mem, false);
+#endif // ASMJIT_X64
+
+ // Instruction opcodes.
+ if (opCode & 0x00FF0000) _emitByte((uint8_t)((opCode & 0x00FF0000) >> 16));
+ if (opCode & 0x0000FF00) _emitByte((uint8_t)((opCode & 0x0000FF00) >> 8));
+
+ _emitByte((uint8_t)((opCode & 0x000000FF)));
+ _emitModM(opReg, mem, 0);
+}
+
+void X86Assembler::_emitMmu(uint32_t opCode, uint8_t rexw, uint8_t opReg,
+ const Operand& src, sysint_t immSize)
+{
+ // Segment prefix.
+ _emitSegmentPrefix(src);
+
+ // Instruction prefix.
+ if (opCode & 0xFF000000) _emitByte((uint8_t)((opCode & 0xFF000000) >> 24));
+
+ // REX prefix.
+#if defined(ASMJIT_X64)
+ _emitRexRM(rexw, opReg, src, false);
+#endif // ASMJIT_X64
+
+ // Instruction opcodes.
+ if (opCode & 0x00FF0000) _emitByte((uint8_t)((opCode & 0x00FF0000) >> 16));
+
+ // No checking, MMX/SSE instructions have always two opcodes or more.
+ _emitByte((uint8_t)((opCode & 0x0000FF00) >> 8));
+ _emitByte((uint8_t)((opCode & 0x000000FF)));
+
+ if (src.isReg())
+ _emitModR(opReg, reinterpret_cast<const Reg&>(src).getRegCode());
+ else
+ _emitModM(opReg, reinterpret_cast<const Mem&>(src), immSize);
+}
+
+X86Assembler::LabelLink* X86Assembler::_emitDisplacement(
+ LabelData& l_data, sysint_t inlinedDisplacement, int size)
+{
+ ASMJIT_ASSERT(l_data.offset == -1);
+ ASMJIT_ASSERT(size == 1 || size == 4);
+
+ // Chain with label.
+ LabelLink* link = _newLabelLink();
+ link->prev = l_data.links;
+ link->offset = getOffset();
+ link->displacement = inlinedDisplacement;
+
+ l_data.links = link;
+
+ // Emit label size as dummy data.
+ if (size == 1)
+ _emitByte(0x01);
+ else // if (size == 4)
+ _emitDWord(0x04040404);
+
+ return link;
+}
+
+void X86Assembler::_emitJmpOrCallReloc(uint32_t instruction, void* target)
+{
+ RelocData rd;
+
+ rd.type = kRelocTrampoline;
+
+#if defined(ASMJIT_X64)
+ // If we are compiling in 64-bit mode, we can use trampoline if relative jump
+ // is not possible.
+ _trampolineSize += X64TrampolineWriter::kSizeTotal;
+#endif // ARCHITECTURE_SPECIFIC
+
+ rd.size = 4;
+ rd.offset = getOffset();
+ rd.address = target;
+
+ _relocData.append(rd);
+
+ // Emit dummy 32-bit integer (will be overwritten by relocCode()).
+ _emitInt32(0);
+}
+
+//! @internal
+//!
+//! @brief Get whether the extended register (additional eight registers
+//! introduced by 64-bit mode) is used.
+static inline bool X86Assembler_isExtRegisterUsed(const Operand& op)
+{
+ // Hacky, but correct.
+ // - If operand type is register then extended register is register with
+ // index 8 and greater (8 to 15 inclusive).
+ // - If operand type is memory operand then we need to take care about
+ // label (in _mem.base) and kInvalidValue, we just decrement the value
+ // by 8 and check if it's at interval 0 to 7 inclusive (if it's there
+ // then it's extended register.
+ return (op.isReg() && (op._reg.code & kRegIndexMask) >= 8U) ||
+ (op.isMem() && ((((uint32_t)op._mem.base - 8U) < 8U) ||
+ (((uint32_t)op._mem.index - 8U) < 8U) ));
+}
+
+// Logging helpers.
+static const char* AssemblerX86_operandSize[] =
+{
+ nullptr,
+ "byte ptr ",
+ "word ptr ",
+ nullptr,
+ "dword ptr ",
+ nullptr,
+ nullptr,
+ nullptr,
+ "qword ptr ",
+ nullptr,
+ "tword ptr ",
+ nullptr,
+ nullptr,
+ nullptr,
+ nullptr,
+ nullptr,
+ "dqword ptr "
+};
+
+static const char X86Assembler_segmentName[] =
+ "es:\0"
+ "cs:\0"
+ "ss:\0"
+ "ds:\0"
+ "fs:\0"
+ "gs:\0"
+ "\0\0\0\0";
+
+static char* X86Assembler_dumpInstructionName(char* buf, uint32_t code)
+{
+ ASMJIT_ASSERT(code < _kX86InstCount);
+ return StringUtil::copy(buf, x86InstInfo[code].getName());
+}
+
+char* X86Assembler_dumpRegister(char* buf, uint32_t type, uint32_t index)
+{
+ // NE == Not-Encodable.
+ const char reg8l[] = "al\0\0" "cl\0\0" "dl\0\0" "bl\0\0" "spl\0" "bpl\0" "sil\0" "dil\0" ;
+ const char reg8h[] = "ah\0\0" "ch\0\0" "dh\0\0" "bh\0\0" "NE\0\0" "NE\0\0" "NE\0\0" "NE\0\0";
+ const char reg16[] = "ax\0\0" "cx\0\0" "dx\0\0" "bx\0\0" "sp\0\0" "bp\0\0" "si\0\0" "di\0\0";
+
+ switch (type)
+ {
+ case kX86RegTypeGpbLo:
+ if (index < 8)
+ return StringUtil::copy(buf, ®8l[index*4]);
+
+ *buf++ = 'r';
+ goto _EmitID;
+
+ case kX86RegTypeGpbHi:
+ if (index < 4)
+ return StringUtil::copy(buf, ®8h[index*4]);
+
+_EmitNE:
+ return StringUtil::copy(buf, "NE");
+
+ case kX86RegTypeGpw:
+ if (index < 8)
+ return StringUtil::copy(buf, ®16[index*4]);
+
+ *buf++ = 'r';
+ buf = StringUtil::utoa(buf, index);
+ *buf++ = 'w';
+ return buf;
+
+ case kX86RegTypeGpd:
+ if (index < 8)
+ {
+ *buf++ = 'e';
+ return StringUtil::copy(buf, ®16[index*4]);
+ }
+
+ *buf++ = 'r';
+ buf = StringUtil::utoa(buf, index);
+ *buf++ = 'd';
+ return buf;
+
+ case kX86RegTypeGpq:
+ *buf++ = 'r';
+
+ if (index < 8)
+ return StringUtil::copy(buf, ®16[index*4]);
+
+_EmitID:
+ return StringUtil::utoa(buf, index);
+
+ case kX86RegTypeX87:
+ *buf++ = 's';
+ *buf++ = 't';
+ goto _EmitID;
+
+ case kX86RegTypeMm:
+ *buf++ = 'm';
+ *buf++ = 'm';
+ goto _EmitID;
+
+ case kX86RegTypeXmm:
+ *buf++ = 'x';
+ *buf++ = 'm';
+ *buf++ = 'm';
+ goto _EmitID;
+
+ case kX86RegTypeYmm:
+ *buf++ = 'y';
+ *buf++ = 'm';
+ *buf++ = 'm';
+ goto _EmitID;
+
+ case kX86RegTypeSeg:
+ if (index < kX86RegNumSeg)
+ return StringUtil::copy(buf, &X86Assembler_segmentName[index*4], 2);
+
+ goto _EmitNE;
+
+ default:
+ return buf;
+ }
+}
+
+char* X86Assembler_dumpOperand(char* buf, const Operand* op, uint32_t memRegType, uint32_t loggerFlags)
+{
+ if (op->isReg())
+ {
+ const Reg& reg = reinterpret_cast<const Reg&>(*op);
+ return X86Assembler_dumpRegister(buf, reg.getRegType(), reg.getRegIndex());
+ }
+ else if (op->isMem())
+ {
+ const Mem& mem = reinterpret_cast<const Mem&>(*op);
+ uint32_t seg = mem.getSegment();
+
+ bool isAbsolute = false;
+
+ if (op->getSize() <= 16)
+ buf = StringUtil::copy(buf, AssemblerX86_operandSize[op->getSize()]);
+
+ if (seg < kX86RegNumSeg)
+ buf = StringUtil::copy(buf, &X86Assembler_segmentName[seg * 4]);
+
+ *buf++ = '[';
+
+ switch (mem.getMemType())
+ {
+ case kOperandMemNative:
+ {
+ // [base + index << shift + displacement]
+ buf = X86Assembler_dumpRegister(buf, memRegType, mem.getBase());
+ break;
+ }
+ case kOperandMemLabel:
+ {
+ // [label + index << shift + displacement]
+ buf += sprintf(buf, "L.%u", mem.getBase() & kOperandIdValueMask);
+ break;
+ }
+ case kOperandMemAbsolute:
+ {
+ // [absolute]
+ isAbsolute = true;
+ buf = StringUtil::utoa(buf, (sysuint_t)mem.getTarget() + mem.getDisplacement(), 16);
+ break;
+ }
+ }
+
+ if (mem.hasIndex())
+ {
+ buf = StringUtil::copy(buf, " + ");
+ buf = X86Assembler_dumpRegister(buf, memRegType, mem.getIndex());
+
+ if (mem.getShift())
+ {
+ buf = StringUtil::copy(buf, " * ");
+ *buf++ = "1248"[mem.getShift() & 3];
+ }
+ }
+
+ if (mem.getDisplacement() && !isAbsolute)
+ {
+ sysint_t d = mem.getDisplacement();
+ uint32_t base = 10;
+ char sign = '+';
+
+ if (d < 0)
+ {
+ d = -d;
+ sign = '-';
+ }
+
+ buf[0] = ' ';
+ buf[1] = sign;
+ buf[2] = ' ';
+ buf += 3;
+
+ if ((loggerFlags & kLoggerOutputHexDisplacement) && d > 9)
+ {
+ buf[0] = '0';
+ buf[1] = 'x';
+ buf += 2;
+ base = 16;
+ }
+
+ buf = StringUtil::utoa(buf, static_cast<uintptr_t>(d), base);
+ }
+
+ *buf++ = ']';
+ return buf;
+ }
+ else if (op->isImm())
+ {
+ const Imm& i = reinterpret_cast<const Imm&>(*op);
+
+ sysuint_t value = i.getUValue();
+ uint32_t base = 10;
+
+ if ((loggerFlags & kLoggerOutputHexImmediate) && value > 9)
+ base = 16;
+
+ if (i.isUnsigned() || base == 16)
+ {
+ return StringUtil::utoa(buf, value, base);
+ }
+ else
+ {
+ return StringUtil::itoa(buf, static_cast<sysint_t>(value), base);
+ }
+ }
+ else if (op->isLabel())
+ {
+ return buf + sprintf(buf, "L.%u", op->getId() & kOperandIdValueMask);
+ }
+ else
+ {
+ return StringUtil::copy(buf, "None");
+ }
+}
+
+static char* X86Assembler_dumpInstruction(char* buf,
+ uint32_t code, uint32_t emitOptions,
+ const Operand* o0,
+ const Operand* o1,
+ const Operand* o2,
+ uint32_t memRegType,
+ uint32_t loggerFlags)
+{
+ // Rex, lock, and short prefix.
+ if (emitOptions & kX86EmitOptionRex)
+ buf = StringUtil::copy(buf, "rex ", 4);
+
+ if (emitOptions & kX86EmitOptionLock)
+ buf = StringUtil::copy(buf, "lock ", 5);
+
+ if (emitOptions & kX86EmitOptionShortJump)
+ buf = StringUtil::copy(buf, "short ", 6);
+
+ // Dump instruction name.
+ buf = X86Assembler_dumpInstructionName(buf, code);
+
+ // Dump operands.
+ if (!o0->isNone()) { *buf++ = ' '; buf = X86Assembler_dumpOperand(buf, o0, memRegType, loggerFlags); }
+ if (!o1->isNone()) { *buf++ = ','; *buf++ = ' '; buf = X86Assembler_dumpOperand(buf, o1, memRegType, loggerFlags); }
+ if (!o2->isNone()) { *buf++ = ','; *buf++ = ' '; buf = X86Assembler_dumpOperand(buf, o2, memRegType, loggerFlags); }
+
+ return buf;
+}
+
+static char* X86Assembler_dumpComment(char* buf, size_t len, const uint8_t* binaryData, size_t binaryLen, const char* comment)
+{
+ size_t currentLength = len;
+ size_t commentLength = comment ? strnlen(comment, kMaxCommentLength) : 0;
+
+ if (binaryLen || commentLength)
+ {
+ size_t align = 32;
+ char sep = ';';
+
+ for (size_t i = !binaryLen; i < 2; i++)
+ {
+ char* bufBegin = buf;
+
+ // Append align.
+ if (currentLength < align)
+ {
+ buf = StringUtil::fill(buf, ' ', align - currentLength);
+ }
+
+ // Append separator.
+ if (sep)
+ {
+ *buf++ = sep;
+ *buf++ = ' ';
+ }
+
+ // Append binary data or comment.
+ if (!i)
+ {
+ buf = StringUtil::hex(buf, binaryData, binaryLen);
+ if (!commentLength)
+ break;
+ }
+ else
+ {
+ buf = StringUtil::copy(buf, comment, commentLength);
+ }
+
+ currentLength += (size_t)(buf - bufBegin);
+ align += 18;
+ sep = '|';
+ }
+ }
+
+ *buf++ = '\n';
+ return buf;
+}
+
+static const _OpReg _patchedHiRegs[4] =
+{
+ // Operand |Size|Reserved0|Reserved1| OperandId | RegisterCode |
+ // ----------+----+---------+---------+--------------+-----------------------+
+ { kOperandReg, 1, {0 ,0 }, kInvalidValue, kX86RegTypeGpbLo | 4 },
+ { kOperandReg, 1, {0 ,0 }, kInvalidValue, kX86RegTypeGpbLo | 5 },
+ { kOperandReg, 1, {0 ,0 }, kInvalidValue, kX86RegTypeGpbLo | 6 },
+ { kOperandReg, 1, {0 ,0 }, kInvalidValue, kX86RegTypeGpbLo | 7 }
+};
+
+void X86Assembler::_emitInstruction(uint32_t code)
+{
+ _emitInstruction(code, &noOperand, &noOperand, &noOperand);
+}
+
+void X86Assembler::_emitInstruction(uint32_t code, const Operand* o0)
+{
+ _emitInstruction(code, o0, &noOperand, &noOperand);
+}
+
+void X86Assembler::_emitInstruction(uint32_t code, const Operand* o0, const Operand* o1)
+{
+ _emitInstruction(code, o0, o1, &noOperand);
+}
+
+void X86Assembler::_emitInstruction(uint32_t code, const Operand* o0, const Operand* o1, const Operand* o2)
+{
+ ASMJIT_ASSERT(!!o0);
+ ASMJIT_ASSERT(!!o1);
+ ASMJIT_ASSERT(!!o2);
+
+ const Operand* _loggerOperands[3];
+
+ uint32_t bLoHiUsed = 0;
+#if defined(ASMJIT_X86)
+ uint32_t forceRexPrefix = false;
+#else
+ uint32_t forceRexPrefix = _emitOptions & kX86EmitOptionRex;
+#endif
+ uint32_t memRegType = kX86RegTypeGpz;
+
+#if defined(ASMJIT_DEBUG)
+ bool assertIllegal = false;
+#endif // ASMJIT_DEBUG
+
+ const Imm* immOperand = nullptr;
+ uint32_t immSize = 0;
+
+#define _FINISHED() \
+ goto _End
+
+#define _FINISHED_IMMEDIATE(_Operand_, _Size_) \
+ do { \
+ immOperand = reinterpret_cast<const Imm*>(_Operand_); \
+ immSize = (_Size_); \
+ goto _EmitImmediate; \
+ } while (0)
+
+ // Convert operands to kOperandNone if needed.
+ if (o0->isReg()) bLoHiUsed |= o0->_reg.code & (kX86RegTypeGpbLo | kX86RegTypeGpbHi);
+ if (o1->isReg()) bLoHiUsed |= o1->_reg.code & (kX86RegTypeGpbLo | kX86RegTypeGpbHi);
+ if (o2->isReg()) bLoHiUsed |= o2->_reg.code & (kX86RegTypeGpbLo | kX86RegTypeGpbHi);
+
+ size_t beginOffset = getOffset();
+ const X86InstInfo* id = &x86InstInfo[code];
+
+ if (code >= _kX86InstCount)
+ {
+ setError(kErrorUnknownInstruction);
+ goto _Cleanup;
+ }
+
+ // Check if register operand is BPL, SPL, SIL, DIL and do action that depends
+ // to current mode:
+ // - 64-bit: - Force REX prefix.
+ //
+ // Check if register operand is AH, BH, CH or DH and do action that depends
+ // to current mode:
+ // - 32-bit: - Patch operand index (index += 4), because we are using
+ // different index what is used in opcode.
+ // - 64-bit: - Check whether there is REX prefix and raise error if it is.
+ // - Do the same as in 32-bit mode - patch register index.
+ //
+ // NOTE: This is a hit hacky, but I added this to older code-base and I have
+ // no energy to rewrite it. Maybe in future all of this can be cleaned up!
+ if (bLoHiUsed | forceRexPrefix)
+ {
+ _loggerOperands[0] = o0;
+ _loggerOperands[1] = o1;
+ _loggerOperands[2] = o2;
+
+#if defined(ASMJIT_X64)
+ // Check if there is register that makes this instruction un-encodable.
+
+ forceRexPrefix |= (uint32_t)X86Assembler_isExtRegisterUsed(*o0);
+ forceRexPrefix |= (uint32_t)X86Assembler_isExtRegisterUsed(*o1);
+ forceRexPrefix |= (uint32_t)X86Assembler_isExtRegisterUsed(*o2);
+
+ if (o0->isRegType(kX86RegTypeGpbLo) && (o0->_reg.code & kRegIndexMask) >= 4) forceRexPrefix = true;
+ else if (o1->isRegType(kX86RegTypeGpbLo) && (o1->_reg.code & kRegIndexMask) >= 4) forceRexPrefix = true;
+ else if (o2->isRegType(kX86RegTypeGpbLo) && (o2->_reg.code & kRegIndexMask) >= 4) forceRexPrefix = true;
+
+ if ((bLoHiUsed & kX86RegTypeGpbHi) && forceRexPrefix)
+ {
+ goto _IllegalInstruction;
+ }
+#endif // ASMJIT_X64
+
+ // Patch GPB.HI operand index.
+ if (bLoHiUsed & kX86RegTypeGpbHi)
+ {
+ if (o0->isRegType(kX86RegTypeGpbHi)) o0 = reinterpret_cast<const Operand*>(&_patchedHiRegs[o0->_reg.code & kRegIndexMask]);
+ if (o1->isRegType(kX86RegTypeGpbHi)) o1 = reinterpret_cast<const Operand*>(&_patchedHiRegs[o1->_reg.code & kRegIndexMask]);
+ if (o2->isRegType(kX86RegTypeGpbHi)) o2 = reinterpret_cast<const Operand*>(&_patchedHiRegs[o2->_reg.code & kRegIndexMask]);
+ }
+ }
+
+ // Check for buffer space (and grow if needed).
+ if (!canEmit()) goto _Cleanup;
+
+ if (_emitOptions & kX86EmitOptionLock)
+ {
+ if (!id->isLockable())
+ goto _IllegalInstruction;
+ _emitByte(0xF0);
+ }
+
+ switch (id->getGroup())
+ {
+ case kX86InstGroupNone:
+ {
+ _FINISHED();
+ }
+
+ case kX86InstGroupEmit:
+ {
+ _emitOpCode(id->_opCode[0]);
+ _FINISHED();
+ }
+
+ case kX86InstGroupArith:
+ {
+ uint32_t opCode = id->_opCode[0];
+ uint8_t opReg = (uint8_t)id->_opCodeR;
+
+ // Mem <- Reg
+ if (o0->isMem() && o1->isReg())
+ {
+ _emitX86RM(opCode + (o1->getSize() != 1),
+ o1->getSize() == 2,
+ o1->getSize() == 8,
+ reinterpret_cast<const GpReg&>(*o1).getRegCode(),
+ reinterpret_cast<const Operand&>(*o0),
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ // Reg <- Reg|Mem
+ if (o0->isReg() && o1->isRegMem())
+ {
+ _emitX86RM(opCode + 2 + (o0->getSize() != 1),
+ o0->getSize() == 2,
+ o0->getSize() == 8,
+ reinterpret_cast<const GpReg&>(*o0).getRegCode(),
+ reinterpret_cast<const Operand&>(*o1),
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ // Alternate Form - AL, AX, EAX, RAX.
+ if (o0->isRegIndex(0) && o1->isImm())
+ {
+ if (o0->getSize() == 1 || !IntUtil::isInt8(static_cast<const Imm*>(o1)->getValue()))
+ {
+ if (o0->getSize() == 2)
+ _emitByte(0x66); // 16-bit.
+ else if (o0->getSize() == 8)
+ _emitByte(0x48); // REX.W.
+
+ _emitByte((opReg << 3) | (0x04 + (o0->getSize() != 1)));
+ _FINISHED_IMMEDIATE(o1, IntUtil::_min<uint32_t>(o0->getSize(), 4));
+ }
+ }
+
+ if (o0->isRegMem() && o1->isImm())
+ {
+ const Imm& imm = reinterpret_cast<const Imm&>(*o1);
+ immSize = IntUtil::isInt8(imm.getValue()) ? 1 : IntUtil::_min<uint32_t>(o0->getSize(), 4);
+
+ _emitX86RM(id->_opCode[1] + (o0->getSize() != 1 ? (immSize != 1 ? 1 : 3) : 0),
+ o0->getSize() == 2,
+ o0->getSize() == 8,
+ opReg, reinterpret_cast<const Operand&>(*o0),
+ immSize, forceRexPrefix);
+ _FINISHED_IMMEDIATE(&imm, immSize);
+ }
+
+ break;
+ }
+
+ case kX86InstGroupBSwap:
+ {
+ if (o0->isReg())
+ {
+ const GpReg& dst = reinterpret_cast<const GpReg&>(*o0);
+
+#if defined(ASMJIT_X64)
+ _emitRexR(dst.getRegType() == kX86RegTypeGpq, 1, dst.getRegCode(), forceRexPrefix);
+#endif // ASMJIT_X64
+ _emitByte(0x0F);
+ _emitModR(1, dst.getRegCode());
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupBTest:
+ {
+ if (o0->isRegMem() && o1->isReg())
+ {
+ const Operand& dst = reinterpret_cast<const Operand&>(*o0);
+ const GpReg& src = reinterpret_cast<const GpReg&>(*o1);
+
+ _emitX86RM(id->_opCode[0],
+ src.isRegType(kX86RegTypeGpw),
+ src.isRegType(kX86RegTypeGpq),
+ src.getRegCode(),
+ dst,
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ if (o0->isRegMem() && o1->isImm())
+ {
+ const Operand& dst = reinterpret_cast<const Operand&>(*o0);
+
+ _emitX86RM(id->_opCode[1],
+ dst.getSize() == 2,
+ dst.getSize() == 8,
+ (uint8_t)id->_opCodeR,
+ dst,
+ 1, forceRexPrefix);
+ _FINISHED_IMMEDIATE(o1, 1);
+ }
+
+ break;
+ }
+
+ case kX86InstGroupCall:
+ {
+ if (o0->isRegTypeMem(kX86RegTypeGpz))
+ {
+ const Operand& dst = reinterpret_cast<const Operand&>(*o0);
+ _emitX86RM(0xFF,
+ 0,
+ 0, 2, dst,
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ if (o0->isImm())
+ {
+ const Imm& imm = reinterpret_cast<const Imm&>(*o0);
+ _emitByte(0xE8);
+ _emitJmpOrCallReloc(kX86InstGroupCall, (void*)imm.getValue());
+ _FINISHED();
+ }
+
+ if (o0->isLabel())
+ {
+ LabelData& l_data = _labels[reinterpret_cast<const Label*>(o0)->getId() & kOperandIdValueMask];
+
+ if (l_data.offset != -1)
+ {
+ // Bound label.
+ static const sysint_t rel32_size = 5;
+ sysint_t offs = l_data.offset - getOffset();
+
+ ASMJIT_ASSERT(offs <= 0);
+
+ _emitByte(0xE8);
+ _emitInt32((int32_t)(offs - rel32_size));
+ }
+ else
+ {
+ // Non-bound label.
+ _emitByte(0xE8);
+ _emitDisplacement(l_data, -4, 4);
+ }
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupCrc32:
+ {
+ if (o0->isReg() && o1->isRegMem())
+ {
+ const GpReg& dst = reinterpret_cast<const GpReg&>(*o0);
+ const Operand& src = reinterpret_cast<const Operand&>(*o1);
+ ASMJIT_ASSERT(dst.getRegType() == kX86RegTypeGpd || dst.getRegType() == kX86RegTypeGpq);
+
+ _emitX86RM(id->_opCode[0] + (src.getSize() != 1),
+ src.getSize() == 2,
+ dst.getRegType() == 8, dst.getRegCode(), src,
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupEnter:
+ {
+ if (o0->isImm() && o1->isImm())
+ {
+ _emitByte(0xC8);
+ _emitWord((uint16_t)(uintptr_t)reinterpret_cast<const Imm&>(*o2).getValue());
+ _emitByte((uint8_t )(uintptr_t)reinterpret_cast<const Imm&>(*o1).getValue());
+ _FINISHED();
+ }
+ break;
+ }
+
+ case kX86InstGroupIMul:
+ {
+ // 1 operand
+ if (o0->isRegMem() && o1->isNone() && o2->isNone())
+ {
+ const Operand& src = reinterpret_cast<const Operand&>(*o0);
+ _emitX86RM(0xF6 + (src.getSize() != 1),
+ src.getSize() == 2,
+ src.getSize() == 8, 5, src,
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+ // 2 operands
+ else if (o0->isReg() && !o1->isNone() && o2->isNone())
+ {
+ const GpReg& dst = reinterpret_cast<const GpReg&>(*o0);
+ ASMJIT_ASSERT(!dst.isRegType(kX86RegTypeGpw));
+
+ if (o1->isRegMem())
+ {
+ const Operand& src = reinterpret_cast<const Operand&>(*o1);
+
+ _emitX86RM(0x0FAF,
+ dst.isRegType(kX86RegTypeGpw),
+ dst.isRegType(kX86RegTypeGpq), dst.getRegCode(), src,
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+ else if (o1->isImm())
+ {
+ const Imm& imm = reinterpret_cast<const Imm&>(*o1);
+
+ if (IntUtil::isInt8(imm.getValue()))
+ {
+ _emitX86RM(0x6B,
+ dst.isRegType(kX86RegTypeGpw),
+ dst.isRegType(kX86RegTypeGpq), dst.getRegCode(), dst,
+ 1, forceRexPrefix);
+ _FINISHED_IMMEDIATE(&imm, 1);
+ }
+ else
+ {
+ immSize = dst.isRegType(kX86RegTypeGpw) ? 2 : 4;
+ _emitX86RM(0x69,
+ dst.isRegType(kX86RegTypeGpw),
+ dst.isRegType(kX86RegTypeGpq), dst.getRegCode(), dst,
+ immSize, forceRexPrefix);
+ _FINISHED_IMMEDIATE(&imm, immSize);
+ }
+ }
+ }
+ // 3 operands
+ else if (o0->isReg() && o1->isRegMem() && o2->isImm())
+ {
+ const GpReg& dst = reinterpret_cast<const GpReg&>(*o0);
+ const Operand& src = reinterpret_cast<const Operand&>(*o1);
+ const Imm& imm = reinterpret_cast<const Imm&>(*o2);
+
+ if (IntUtil::isInt8(imm.getValue()))
+ {
+ _emitX86RM(0x6B,
+ dst.isRegType(kX86RegTypeGpw),
+ dst.isRegType(kX86RegTypeGpq), dst.getRegCode(), src,
+ 1, forceRexPrefix);
+ _FINISHED_IMMEDIATE(&imm, 1);
+ }
+ else
+ {
+ immSize = dst.isRegType(kX86RegTypeGpw) ? 2 : 4;
+ _emitX86RM(0x69,
+ dst.isRegType(kX86RegTypeGpw),
+ dst.isRegType(kX86RegTypeGpq), dst.getRegCode(), src,
+ immSize, forceRexPrefix);
+ _FINISHED_IMMEDIATE(&imm, immSize);
+ }
+ }
+
+ break;
+ }
+
+ case kX86InstGroupIncDec:
+ {
+ if (o0->isRegMem())
+ {
+ const Operand& dst = reinterpret_cast<const Operand&>(*o0);
+
+ // INC [r16|r32] in 64-bit mode is not encodable.
+#if defined(ASMJIT_X86)
+ if ((dst.isReg()) && (dst.isRegType(kX86RegTypeGpw) || dst.isRegType(kX86RegTypeGpd)))
+ {
+ _emitX86Inl(id->_opCode[0],
+ dst.isRegType(kX86RegTypeGpw),
+ 0, reinterpret_cast<const Reg&>(dst).getRegCode(),
+ false);
+ _FINISHED();
+ }
+#endif // ASMJIT_X86
+
+ _emitX86RM(id->_opCode[1] + (dst.getSize() != 1),
+ dst.getSize() == 2,
+ dst.getSize() == 8, (uint8_t)id->_opCodeR, dst,
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupJcc:
+ {
+ if (o0->isLabel())
+ {
+ LabelData& l_data = _labels[reinterpret_cast<const Label*>(o0)->getId() & kOperandIdValueMask];
+
+ uint32_t hint = (uint32_t)(o1->isImm() ? reinterpret_cast<const Imm&>(*o1).getValue() : 0);
+ bool isShortJump = !!(_emitOptions & kX86EmitOptionShortJump);
+
+ // Emit jump hint if configured for that.
+ if ((hint & (kCondHintLikely | kCondHintUnlikely)) && (_properties & (1 << kX86PropertyJumpHints)))
+ {
+ if (hint & kCondHintLikely)
+ _emitByte(kX86CondPrefixLikely);
+ else if (hint & kCondHintUnlikely)
+ _emitByte(kX86CondPrefixUnlikely);
+ }
+
+ if (l_data.offset != -1)
+ {
+ // Bound label.
+ static const sysint_t rel8_size = 2;
+ static const sysint_t rel32_size = 6;
+ sysint_t offs = l_data.offset - getOffset();
+
+ ASMJIT_ASSERT(offs <= 0);
+
+ if (IntUtil::isInt8(offs - rel8_size))
+ {
+ _emitByte(0x70 | (uint8_t)id->_opCode[0]);
+ _emitByte((uint8_t)(int8_t)(offs - rel8_size));
+
+ // Change the emit options so logger can log instruction correctly.
+ _emitOptions |= kX86EmitOptionShortJump;
+ }
+ else
+ {
+ if (isShortJump && _logger)
+ {
+ _logger->logString("*** ASSEMBLER WARNING: Emitting long conditional jump, but short jump instruction forced!\n");
+ _emitOptions &= ~kX86EmitOptionShortJump;
+ }
+
+ _emitByte(0x0F);
+ _emitByte(0x80 | (uint8_t)id->_opCode[0]);
+ _emitInt32((int32_t)(offs - rel32_size));
+ }
+ }
+ else
+ {
+ // Non-bound label.
+ if (isShortJump)
+ {
+ _emitByte(0x70 | (uint8_t)id->_opCode[0]);
+ _emitDisplacement(l_data, -1, 1);
+ }
+ else
+ {
+ _emitByte(0x0F);
+ _emitByte(0x80 | (uint8_t)id->_opCode[0]);
+ _emitDisplacement(l_data, -4, 4);
+ }
+ }
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupJmp:
+ {
+ if (o0->isRegMem())
+ {
+ const Operand& dst = reinterpret_cast<const Operand&>(*o0);
+
+ _emitX86RM(0xFF,
+ 0,
+ 0, 4, dst,
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ if (o0->isImm())
+ {
+ const Imm& imm = reinterpret_cast<const Imm&>(*o0);
+ _emitByte(0xE9);
+ _emitJmpOrCallReloc(kX86InstGroupJmp, (void*)imm.getValue());
+ _FINISHED();
+ }
+
+ if (o0->isLabel())
+ {
+ LabelData& l_data = _labels[reinterpret_cast<const Label*>(o0)->getId() & kOperandIdValueMask];
+ bool isShortJump = !!(_emitOptions & kX86EmitOptionShortJump);
+
+ if (l_data.offset != -1)
+ {
+ // Bound label.
+ const sysint_t rel8_size = 2;
+ const sysint_t rel32_size = 5;
+ sysint_t offs = l_data.offset - getOffset();
+
+ if (IntUtil::isInt8(offs - rel8_size))
+ {
+ _emitByte(0xEB);
+ _emitByte((uint8_t)(int8_t)(offs - rel8_size));
+
+ // Change the emit options so logger can log instruction correctly.
+ _emitOptions |= kX86EmitOptionShortJump;
+ }
+ else
+ {
+ if (isShortJump)
+ {
+ if (_logger)
+ {
+ _logger->logString("*** ASSEMBLER WARNING: Emitting long jump, but short jump instruction forced!\n");
+ _emitOptions &= ~kX86EmitOptionShortJump;
+ }
+ }
+
+ _emitByte(0xE9);
+ _emitInt32((int32_t)(offs - rel32_size));
+ }
+ }
+ else
+ {
+ // Non-bound label.
+ if (isShortJump)
+ {
+ _emitByte(0xEB);
+ _emitDisplacement(l_data, -1, 1);
+ }
+ else
+ {
+ _emitByte(0xE9);
+ _emitDisplacement(l_data, -4, 4);
+ }
+ }
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupLea:
+ {
+ if (o0->isReg() && o1->isMem())
+ {
+ const GpReg& dst = reinterpret_cast<const GpReg&>(*o0);
+ const Mem& src = reinterpret_cast<const Mem&>(*o1);
+
+ // Size override prefix support.
+ if (src.getSizePrefix())
+ {
+ _emitByte(0x67);
+#if defined(ASMJIT_X86)
+ memRegType = kX86RegTypeGpw;
+#else
+ memRegType = kX86RegTypeGpd;
+#endif
+ }
+
+ _emitX86RM(0x8D,
+ dst.isRegType(kX86RegTypeGpw),
+ dst.isRegType(kX86RegTypeGpq), dst.getRegCode(), src,
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupMem:
+ {
+ if (o0->isMem())
+ {
+ _emitX86RM(id->_opCode[0], 0, (uint8_t)id->_opCode[1], (uint8_t)id->_opCodeR, reinterpret_cast<const Mem&>(*o0), 0, forceRexPrefix);
+ _FINISHED();
+ }
+ break;
+ }
+
+ case kX86InstGroupMov:
+ {
+ const Operand& dst = *o0;
+ const Operand& src = *o1;
+
+ switch (dst.getType() << 4 | src.getType())
+ {
+ // Reg <- Reg/Mem
+ case (kOperandReg << 4) | kOperandReg:
+ {
+ // Reg <- Sreg
+ if (src.isRegType(kX86RegTypeSeg))
+ {
+ ASMJIT_ASSERT(dst.isRegType(kX86RegTypeGpw) ||
+ dst.isRegType(kX86RegTypeGpd) ||
+ dst.isRegType(kX86RegTypeGpq) );
+
+ _emitX86RM(0x8C,
+ dst.getSize() == 2,
+ dst.getSize() == 8,
+ reinterpret_cast<const SegmentReg&>(src).getRegCode(),
+ reinterpret_cast<const Operand&>(dst),
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ // Sreg <- Reg/Mem
+ if (dst.isRegType(kX86RegTypeSeg))
+ {
+ ASMJIT_ASSERT(src.isRegType(kX86RegTypeGpw ) ||
+ src.isRegType(kX86RegTypeGpd ) ||
+ src.isRegType(kX86RegTypeGpq ) );
+
+_Emit_Mov_Sreg_RM:
+ _emitX86RM(0x8E,
+ src.getSize() == 2,
+ src.getSize() == 8,
+ reinterpret_cast<const SegmentReg&>(dst).getRegCode(),
+ reinterpret_cast<const Operand&>(src),
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ ASMJIT_ASSERT(src.isRegType(kX86RegTypeGpbLo) ||
+ src.isRegType(kX86RegTypeGpbHi) ||
+ src.isRegType(kX86RegTypeGpw ) ||
+ src.isRegType(kX86RegTypeGpd ) ||
+ src.isRegType(kX86RegTypeGpq ) );
+ // ... fall through ...
+ }
+ case (kOperandReg << 4) | kOperandMem:
+ {
+ // Sreg <- Mem
+ if (dst.isRegType(kX86RegTypeSeg))
+ {
+ goto _Emit_Mov_Sreg_RM;
+ }
+
+ ASMJIT_ASSERT(dst.isRegType(kX86RegTypeGpbLo) ||
+ dst.isRegType(kX86RegTypeGpbHi) ||
+ dst.isRegType(kX86RegTypeGpw ) ||
+ dst.isRegType(kX86RegTypeGpd ) ||
+ dst.isRegType(kX86RegTypeGpq ) );
+
+ _emitX86RM(0x0000008A + (dst.getSize() != 1),
+ dst.isRegType(kX86RegTypeGpw),
+ dst.isRegType(kX86RegTypeGpq),
+ reinterpret_cast<const GpReg&>(dst).getRegCode(),
+ reinterpret_cast<const Operand&>(src),
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ // Reg <- Imm
+ case (kOperandReg << 4) | kOperandImm:
+ {
+ const GpReg& dst = reinterpret_cast<const GpReg&>(*o0);
+ const Imm& src = reinterpret_cast<const Imm&>(*o1);
+
+ // In 64-bit mode the immediate can be 64-bits long if the
+ // destination operand type is register (otherwise 32-bits).
+ immSize = dst.getSize();
+
+#if defined(ASMJIT_X64)
+ // Optimize instruction size by using 32-bit immediate if value can
+ // fit into it.
+ if (immSize == 8 && IntUtil::isInt32(src.getValue()))
+ {
+ _emitX86RM(0xC7,
+ 0, // 16BIT
+ 1, // REX.W
+ 0, // O
+ dst,
+ 0, forceRexPrefix);
+ immSize = 4;
+ }
+ else
+ {
+#endif // ASMJIT_X64
+ _emitX86Inl((dst.getSize() == 1 ? 0xB0 : 0xB8),
+ dst.isRegType(kX86RegTypeGpw),
+ dst.isRegType(kX86RegTypeGpq),
+ dst.getRegCode(), forceRexPrefix);
+#if defined(ASMJIT_X64)
+ }
+#endif // ASMJIT_X64
+
+ _FINISHED_IMMEDIATE(&src, immSize);
+ }
+
+ // Mem <- Reg/Sreg
+ case (kOperandMem << 4) | kOperandReg:
+ {
+ if (src.isRegType(kX86RegTypeSeg))
+ {
+ // Mem <- Sreg
+ _emitX86RM(0x8C,
+ dst.getSize() == 2,
+ dst.getSize() == 8,
+ reinterpret_cast<const SegmentReg&>(src).getRegCode(),
+ reinterpret_cast<const Operand&>(dst),
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+ else
+ {
+ // Mem <- Reg
+ ASMJIT_ASSERT(src.isRegType(kX86RegTypeGpbLo) ||
+ src.isRegType(kX86RegTypeGpbHi) ||
+ src.isRegType(kX86RegTypeGpw ) ||
+ src.isRegType(kX86RegTypeGpd ) ||
+ src.isRegType(kX86RegTypeGpq ) );
+
+ _emitX86RM(0x88 + (src.getSize() != 1),
+ src.isRegType(kX86RegTypeGpw),
+ src.isRegType(kX86RegTypeGpq),
+ reinterpret_cast<const GpReg&>(src).getRegCode(),
+ reinterpret_cast<const Operand&>(dst),
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+ }
+
+ // Mem <- Imm
+ case (kOperandMem << 4) | kOperandImm:
+ {
+ immSize = IntUtil::_min<uint32_t>(dst.getSize(), 4);
+
+ _emitX86RM(0xC6 + (dst.getSize() != 1),
+ dst.getSize() == 2,
+ dst.getSize() == 8,
+ 0,
+ reinterpret_cast<const Operand&>(dst),
+ immSize, forceRexPrefix);
+ _FINISHED_IMMEDIATE(&src, immSize);
+ }
+ }
+
+ break;
+ }
+
+ case kX86InstGroupMovPtr:
+ {
+ if ((o0->isReg() && o1->isImm()) || (o0->isImm() && o1->isReg()))
+ {
+ bool reverse = o1->getType() == kOperandReg;
+ uint8_t opCode = !reverse ? 0xA0 : 0xA2;
+ const GpReg& reg = reinterpret_cast<const GpReg&>(!reverse ? *o0 : *o1);
+ const Imm& imm = reinterpret_cast<const Imm&>(!reverse ? *o1 : *o0);
+
+ if (reg.getRegIndex())
+ goto _IllegalInstruction;
+
+ if (reg.isRegType(kX86RegTypeGpw)) _emitByte(0x66);
+#if defined(ASMJIT_X64)
+ _emitRexR(reg.getSize() == 8, 0, 0, forceRexPrefix);
+#endif // ASMJIT_X64
+ _emitByte(opCode + (reg.getSize() != 1));
+ _FINISHED_IMMEDIATE(&imm, sizeof(sysint_t));
+ }
+
+ break;
+ }
+
+ case kX86InstGroupMovSxMovZx:
+ {
+ if (o0->isReg() && o1->isRegMem())
+ {
+ const GpReg& dst = reinterpret_cast<const GpReg&>(*o0);
+ const Operand& src = reinterpret_cast<const Operand&>(*o1);
+
+ if (dst.getSize() == 1)
+ goto _IllegalInstruction;
+
+ if (src.getSize() != 1 && src.getSize() != 2)
+ goto _IllegalInstruction;
+
+ if (src.getSize() == 2 && dst.getSize() == 2)
+ goto _IllegalInstruction;
+
+ _emitX86RM(id->_opCode[0] + (src.getSize() != 1),
+ dst.isRegType(kX86RegTypeGpw),
+ dst.isRegType(kX86RegTypeGpq),
+ dst.getRegCode(),
+ src,
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ break;
+ }
+
+#if defined(ASMJIT_X64)
+ case kX86InstGroupMovSxD:
+ {
+ if (o0->isReg() && o1->isRegMem())
+ {
+ const GpReg& dst = reinterpret_cast<const GpReg&>(*o0);
+ const Operand& src = reinterpret_cast<const Operand&>(*o1);
+ _emitX86RM(0x00000063,
+ 0,
+ 1, dst.getRegCode(), src,
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ break;
+ }
+#endif // ASMJIT_X64
+
+ case kX86InstGroupPush:
+ {
+ if (o0->isRegType(kX86RegTypeSeg))
+ {
+ static const uint32_t opcodeList[] =
+ {
+ 0x06, // ES.
+ 0x0E, // CS.
+ 0x16, // SS.
+ 0x1E, // DS.
+ 0x0FA0, // FS.
+ 0x0FA8 // GS.
+ };
+
+ unsigned int segment = reinterpret_cast<const SegmentReg*>(o0)->getRegIndex();
+ ASMJIT_ASSERT(segment < kX86SegCount);
+
+ unsigned int opcode = opcodeList[segment];
+
+ if (opcode > 0xFF)
+ _emitByte(opcode >> 8);
+ _emitByte(opcode & 0xFF);
+
+ _FINISHED();
+ }
+
+ // This section is only for immediates, memory/register operands are handled in kX86InstGroupPop.
+ if (o0->isImm())
+ {
+ const Imm& imm = reinterpret_cast<const Imm&>(*o0);
+
+ if (IntUtil::isInt8(imm.getValue()))
+ {
+ _emitByte(0x6A);
+ _FINISHED_IMMEDIATE(&imm, 1);
+ }
+ else
+ {
+ _emitByte(0x68);
+ _FINISHED_IMMEDIATE(&imm, 4);
+ }
+ }
+
+ // ... goto kX86InstGroupPop ...
+ }
+
+ case kX86InstGroupPop:
+ {
+ if (o0->isRegType(kX86RegTypeSeg))
+ {
+ static const uint32_t opcodeList[] =
+ {
+ 0x07, // ES.
+ 0, // CS.
+ 0x17, // SS.
+ 0x1F, // DS.
+ 0x0FA1, // FS.
+ 0x0FA9 // GS.
+ };
+
+ unsigned int segment = reinterpret_cast<const SegmentReg*>(o0)->getRegIndex();
+ ASMJIT_ASSERT(segment < kX86SegCount);
+
+ unsigned int opcode = opcodeList[segment];
+ ASMJIT_ASSERT(!!opcode);
+
+ if (opcode > 0xFF)
+ _emitByte(opcode >> 8);
+ _emitByte(opcode & 0xFF);
+
+ _FINISHED();
+ }
+
+ if (o0->isReg())
+ {
+ ASMJIT_ASSERT(o0->isRegType(kX86RegTypeGpw) || o0->isRegType(kX86RegTypeGpz));
+ _emitX86Inl(id->_opCode[0], o0->isRegType(kX86RegTypeGpw), 0, reinterpret_cast<const GpReg&>(*o0).getRegCode(), forceRexPrefix);
+ _FINISHED();
+ }
+
+ if (o0->isMem())
+ {
+ _emitX86RM(id->_opCode[1], o0->getSize() == 2, 0, (uint8_t)id->_opCodeR, reinterpret_cast<const Operand&>(*o0), 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupRegRm:
+ {
+ if (o0->isReg() && o1->isRegMem())
+ {
+ const GpReg& dst = reinterpret_cast<const GpReg&>(*o0);
+ const Operand& src = reinterpret_cast<const Operand&>(*o1);
+ ASMJIT_ASSERT(dst.getSize() != 1);
+
+ _emitX86RM(id->_opCode[0],
+ dst.getRegType() == kX86RegTypeGpw,
+ dst.getRegType() == kX86RegTypeGpq, dst.getRegCode(), src,
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupRm:
+ {
+ if (o0->isRegMem())
+ {
+ const Operand& op = reinterpret_cast<const Operand&>(*o0);
+ _emitX86RM(id->_opCode[0] + (op.getSize() != 1),
+ op.getSize() == 2,
+ op.getSize() == 8, (uint8_t)id->_opCodeR, op,
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupRmByte:
+ {
+ if (o0->isRegMem())
+ {
+ const Operand& op = reinterpret_cast<const Operand&>(*o0);
+
+ // Only BYTE register or BYTE/TYPELESS memory location can be used.
+ ASMJIT_ASSERT(op.getSize() <= 1);
+
+ _emitX86RM(id->_opCode[0], false, false, 0, op, 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupRmReg:
+ {
+ if (o0->isRegMem() && o1->isReg())
+ {
+ const Operand& dst = reinterpret_cast<const Operand&>(*o0);
+ const GpReg& src = reinterpret_cast<const GpReg&>(*o1);
+ _emitX86RM(id->_opCode[0] + (src.getSize() != 1),
+ src.getRegType() == kX86RegTypeGpw,
+ src.getRegType() == kX86RegTypeGpq, src.getRegCode(), dst,
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupRep:
+ {
+ uint32_t opCode = id->_opCode[0];
+ uint32_t opSize = id->_opCode[1];
+
+ // Emit REP prefix (1 BYTE).
+ _emitByte(opCode >> 24);
+
+ if (opSize != 1) opCode++; // D, Q and W form.
+ if (opSize == 2) _emitByte(0x66); // 16-bit prefix.
+#if defined(ASMJIT_X64)
+ else if (opSize == 8) _emitByte(0x48); // REX.W prefix.
+#endif // ASMJIT_X64
+
+ // Emit opcode (1 BYTE).
+ _emitByte(opCode & 0xFF);
+ _FINISHED();
+ }
+
+ case kX86InstGroupRet:
+ {
+ if (o0->isNone())
+ {
+ _emitByte(0xC3);
+ _FINISHED();
+ }
+ else if (o0->isImm())
+ {
+ const Imm& imm = reinterpret_cast<const Imm&>(*o0);
+ ASMJIT_ASSERT(IntUtil::isUInt16(imm.getValue()));
+
+ if (!imm.getValue())
+ {
+ _emitByte(0xC3);
+ _FINISHED();
+ }
+ else
+ {
+ _emitByte(0xC2);
+ _FINISHED_IMMEDIATE(&imm, 2);
+ }
+ }
+
+ break;
+ }
+
+ case kX86InstGroupRot:
+ {
+ if (o0->isRegMem() && (o1->isRegCode(kX86RegCl) || o1->isImm()))
+ {
+ // generate opcode. For these operations is base 0xC0 or 0xD0.
+ bool useImm8 = o1->isImm() && reinterpret_cast<const Imm&>(*o1).getValue() != 1;
+ uint32_t opCode = useImm8 ? 0xC0 : 0xD0;
+
+ // size and operand type modifies the opcode
+ if (o0->getSize() != 1) opCode |= 0x01;
+ if (o1->getType() == kOperandReg) opCode |= 0x02;
+
+ _emitX86RM(opCode,
+ o0->getSize() == 2,
+ o0->getSize() == 8,
+ (uint8_t)id->_opCodeR, reinterpret_cast<const Operand&>(*o0),
+ useImm8 ? 1 : 0, forceRexPrefix);
+
+ if (useImm8)
+ _FINISHED_IMMEDIATE(o1, 1);
+ else
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupShldShrd:
+ {
+ if (o0->isRegMem() && o1->isReg() && (o2->isImm() || (o2->isReg() && o2->isRegCode(kX86RegCl))))
+ {
+ const Operand& dst = reinterpret_cast<const Operand&>(*o0);
+ const GpReg& src1 = reinterpret_cast<const GpReg&>(*o1);
+ const Operand& src2 = reinterpret_cast<const Operand&>(*o2);
+
+ ASMJIT_ASSERT(dst.getSize() == src1.getSize());
+
+ _emitX86RM(id->_opCode[0] + src2.isReg(),
+ src1.isRegType(kX86RegTypeGpw),
+ src1.isRegType(kX86RegTypeGpq),
+ src1.getRegCode(), dst,
+ src2.isImm() ? 1 : 0, forceRexPrefix);
+ if (src2.isImm())
+ _FINISHED_IMMEDIATE(&src2, 1);
+ else
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupTest:
+ {
+ if (o0->isRegMem() && o1->isReg())
+ {
+ ASMJIT_ASSERT(o0->getSize() == o1->getSize());
+ _emitX86RM(0x84 + (o1->getSize() != 1),
+ o1->getSize() == 2, o1->getSize() == 8,
+ reinterpret_cast<const Reg&>(*o1).getRegCode(),
+ reinterpret_cast<const Operand&>(*o0),
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ // Alternate Form - AL, AX, EAX, RAX.
+ if (o0->isRegIndex(0) && o1->isImm())
+ {
+ immSize = IntUtil::_min<uint32_t>(o0->getSize(), 4);
+
+ if (o0->getSize() == 2) _emitByte(0x66); // 16-bit.
+#if defined(ASMJIT_X64)
+ _emitRexRM(o0->getSize() == 8, 0, reinterpret_cast<const Operand&>(*o0), forceRexPrefix);
+#endif // ASMJIT_X64
+ _emitByte(0xA8 + (o0->getSize() != 1));
+ _FINISHED_IMMEDIATE(o1, immSize);
+ }
+
+ if (o0->isRegMem() && o1->isImm())
+ {
+ immSize = IntUtil::_min<uint32_t>(o0->getSize(), 4);
+
+ if (o0->getSize() == 2) _emitByte(0x66); // 16-bit.
+ _emitSegmentPrefix(reinterpret_cast<const Operand&>(*o0)); // Segment prefix.
+#if defined(ASMJIT_X64)
+ _emitRexRM(o0->getSize() == 8, 0, reinterpret_cast<const Operand&>(*o0), forceRexPrefix);
+#endif // ASMJIT_X64
+ _emitByte(0xF6 + (o0->getSize() != 1));
+ _emitModRM(0, reinterpret_cast<const Operand&>(*o0), immSize);
+ _FINISHED_IMMEDIATE(o1, immSize);
+ }
+
+ break;
+ }
+
+ case kX86InstGroupXchg:
+ {
+ if (o0->isRegMem() && o1->isReg())
+ {
+ const Operand& dst = reinterpret_cast<const Operand&>(*o0);
+ const GpReg& src = reinterpret_cast<const GpReg&>(*o1);
+
+ if (src.isRegType(kX86RegTypeGpw)) _emitByte(0x66); // 16-bit.
+ _emitSegmentPrefix(dst); // segment prefix
+#if defined(ASMJIT_X64)
+ _emitRexRM(src.isRegType(kX86RegTypeGpq), src.getRegCode(), dst, forceRexPrefix);
+#endif // ASMJIT_X64
+
+ // Special opcode for index 0 registers (AX, EAX, RAX vs register).
+ if ((dst.getType() == kOperandReg && dst.getSize() > 1) &&
+ (!reinterpret_cast<const GpReg&>(dst).getRegCode() ||
+ !reinterpret_cast<const GpReg&>(src).getRegCode() ))
+ {
+ uint8_t index = reinterpret_cast<const GpReg&>(dst).getRegCode() | src.getRegCode();
+ _emitByte(0x90 + index);
+ _FINISHED();
+ }
+
+ _emitByte(0x86 + (src.getSize() != 1));
+ _emitModRM(src.getRegCode(), dst, 0);
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupMovBE:
+ {
+ if (o0->isReg() && o1->isMem())
+ {
+ _emitX86RM(0x000F38F0,
+ o0->isRegType(kX86RegTypeGpw),
+ o0->isRegType(kX86RegTypeGpq),
+ reinterpret_cast<const GpReg&>(*o0).getRegCode(),
+ reinterpret_cast<const Mem&>(*o1),
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ if (o0->isMem() && o1->isReg())
+ {
+ _emitX86RM(0x000F38F1,
+ o1->isRegType(kX86RegTypeGpw),
+ o1->isRegType(kX86RegTypeGpq),
+ reinterpret_cast<const GpReg&>(*o1).getRegCode(),
+ reinterpret_cast<const Mem&>(*o0),
+ 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupX87StM:
+ {
+ if (o0->isRegType(kX86RegTypeX87))
+ {
+ uint8_t i1 = reinterpret_cast<const X87Reg&>(*o0).getRegIndex();
+ uint8_t i2 = 0;
+
+ if (code != kX86InstFCom && code != kX86InstFComP)
+ {
+ if (!o1->isRegType(kX86RegTypeX87))
+ goto _IllegalInstruction;
+ i2 = reinterpret_cast<const X87Reg&>(*o1).getRegIndex();
+ }
+ else if (i1 && i2)
+ {
+ goto _IllegalInstruction;
+ }
+
+ _emitByte(!i1
+ ? ((id->_opCode[0] & 0xFF000000) >> 24)
+ : ((id->_opCode[0] & 0x00FF0000) >> 16));
+ _emitByte(!i1
+ ? ((id->_opCode[0] & 0x0000FF00) >> 8) + i2
+ : ((id->_opCode[0] & 0x000000FF) ) + i1);
+ _FINISHED();
+ }
+
+ if (o0->isMem() && (o0->getSize() == 4 || o0->getSize() == 8) && o1->isNone())
+ {
+ const Mem& m = reinterpret_cast<const Mem&>(*o0);
+
+ // Segment prefix.
+ _emitSegmentPrefix(m);
+
+ _emitByte(o0->getSize() == 4
+ ? ((id->_opCode[0] & 0xFF000000) >> 24)
+ : ((id->_opCode[0] & 0x00FF0000) >> 16));
+ _emitModM((uint8_t)id->_opCodeR, m, 0);
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupX87StI:
+ {
+ if (o0->isRegType(kX86RegTypeX87))
+ {
+ uint8_t i = reinterpret_cast<const X87Reg&>(*o0).getRegIndex();
+ _emitByte((uint8_t)((id->_opCode[0] & 0x0000FF00) >> 8));
+ _emitByte((uint8_t)((id->_opCode[0] & 0x000000FF) + i));
+ _FINISHED();
+ }
+ break;
+ }
+
+ case kX86InstGroupX87Status:
+ {
+ if (o0->isReg() &&
+ reinterpret_cast<const Reg&>(*o0).getRegType() <= kX86RegTypeGpq &&
+ !reinterpret_cast<const Reg&>(*o0).getRegIndex())
+ {
+ _emitOpCode(id->_opCode[1]);
+ _FINISHED();
+ }
+
+ if (o0->isMem())
+ {
+ _emitX86RM(id->_opCode[0], 0, 0, (uint8_t)id->_opCodeR, reinterpret_cast<const Mem&>(*o0), 0, forceRexPrefix);
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupX87FldFst:
+ {
+ if (o0->isRegType(kX86RegTypeX87))
+ {
+ _emitByte((uint8_t)((id->_opCode[1] & 0xFF000000) >> 24));
+ _emitByte((uint8_t)((id->_opCode[1] & 0x00FF0000) >> 16) +
+ reinterpret_cast<const X87Reg&>(*o0).getRegIndex());
+ _FINISHED();
+ }
+
+ // ... fall through to kX86InstGroupX87Mem ...
+ }
+
+ case kX86InstGroupX87Mem:
+ {
+ if (!o0->isMem())
+ goto _IllegalInstruction;
+ const Mem& m = reinterpret_cast<const Mem&>(*o0);
+
+ uint8_t opCode = 0x00, mod = 0;
+
+ if (o0->getSize() == 2 && (id->_opFlags[0] & kX86InstOpStM2))
+ {
+ opCode = (uint8_t)((id->_opCode[0] & 0xFF000000) >> 24);
+ mod = (uint8_t)id->_opCodeR;
+ }
+ if (o0->getSize() == 4 && (id->_opFlags[0] & kX86InstOpStM4))
+ {
+ opCode = (uint8_t)((id->_opCode[0] & 0x00FF0000) >> 16);
+ mod = (uint8_t)id->_opCodeR;
+ }
+ if (o0->getSize() == 8 && (id->_opFlags[0] & kX86InstOpStM8))
+ {
+ opCode = (uint8_t)((id->_opCode[0] & 0x0000FF00) >> 8);
+ mod = (uint8_t)((id->_opCode[0] & 0x000000FF) );
+ }
+
+ if (opCode)
+ {
+ _emitSegmentPrefix(m);
+ _emitByte(opCode);
+ _emitModM(mod, m, 0);
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupMmuMov:
+ {
+ ASMJIT_ASSERT(!!id->_opFlags[0]);
+ ASMJIT_ASSERT(!!id->_opFlags[1]);
+
+ // Check parameters (X)MM|GP32_64 <- (X)MM|GP32_64|Mem|Imm
+ if ((o0->isMem() && !(id->_opFlags[0] & kX86InstOpMem)) ||
+ (o0->isRegType(kX86RegTypeMm ) && !(id->_opFlags[0] & kX86InstOpMm )) ||
+ (o0->isRegType(kX86RegTypeXmm) && !(id->_opFlags[0] & kX86InstOpXmm)) ||
+ (o0->isRegType(kX86RegTypeGpd) && !(id->_opFlags[0] & kX86InstOpGd )) ||
+ (o0->isRegType(kX86RegTypeGpq) && !(id->_opFlags[0] & kX86InstOpGq )) ||
+ (o1->isRegType(kX86RegTypeMm ) && !(id->_opFlags[1] & kX86InstOpMm )) ||
+ (o1->isRegType(kX86RegTypeXmm) && !(id->_opFlags[1] & kX86InstOpXmm)) ||
+ (o1->isRegType(kX86RegTypeGpd) && !(id->_opFlags[1] & kX86InstOpGd )) ||
+ (o1->isRegType(kX86RegTypeGpq) && !(id->_opFlags[1] & kX86InstOpGq )) ||
+ (o1->isMem() && !(id->_opFlags[1] & kX86InstOpMem)) )
+ {
+ goto _IllegalInstruction;
+ }
+
+ // Illegal.
+ if (o0->isMem() && o1->isMem())
+ goto _IllegalInstruction;
+
+ uint8_t rexw = ((id->_opFlags[0] | id->_opFlags[1]) & kX86InstOpNoRex)
+ ? 0
+ : o0->isRegType(kX86RegTypeGpq) | o1->isRegType(kX86RegTypeGpq);
+
+ // (X)MM|Reg <- (X)MM|Reg
+ if (o0->isReg() && o1->isReg())
+ {
+ _emitMmu(id->_opCode[0], rexw,
+ reinterpret_cast<const Reg&>(*o0).getRegCode(),
+ reinterpret_cast<const Reg&>(*o1),
+ 0);
+ _FINISHED();
+ }
+
+ // (X)MM|Reg <- Mem
+ if (o0->isReg() && o1->isMem())
+ {
+ _emitMmu(id->_opCode[0], rexw,
+ reinterpret_cast<const Reg&>(*o0).getRegCode(),
+ reinterpret_cast<const Mem&>(*o1),
+ 0);
+ _FINISHED();
+ }
+
+ // Mem <- (X)MM|Reg
+ if (o0->isMem() && o1->isReg())
+ {
+ _emitMmu(id->_opCode[1], rexw,
+ reinterpret_cast<const Reg&>(*o1).getRegCode(),
+ reinterpret_cast<const Mem&>(*o0),
+ 0);
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupMmuMovD:
+ {
+ if ((o0->isRegType(kX86RegTypeMm) || o0->isRegType(kX86RegTypeXmm)) && (o1->isRegType(kX86RegTypeGpd) || o1->isMem()))
+ {
+ _emitMmu(o0->isRegType(kX86RegTypeXmm) ? 0x66000F6E : 0x00000F6E, 0,
+ reinterpret_cast<const Reg&>(*o0).getRegCode(),
+ reinterpret_cast<const Operand&>(*o1),
+ 0);
+ _FINISHED();
+ }
+
+ if ((o0->isRegType(kX86RegTypeGpd) || o0->isMem()) && (o1->isRegType(kX86RegTypeMm) || o1->isRegType(kX86RegTypeXmm)))
+ {
+ _emitMmu(o1->isRegType(kX86RegTypeXmm) ? 0x66000F7E : 0x00000F7E, 0,
+ reinterpret_cast<const Reg&>(*o1).getRegCode(),
+ reinterpret_cast<const Operand&>(*o0),
+ 0);
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupMmuMovQ:
+ {
+ if (o0->isRegType(kX86RegTypeMm) && o1->isRegType(kX86RegTypeMm))
+ {
+ _emitMmu(0x00000F6F, 0,
+ reinterpret_cast<const MmReg&>(*o0).getRegCode(),
+ reinterpret_cast<const MmReg&>(*o1),
+ 0);
+ _FINISHED();
+ }
+
+ if (o0->isRegType(kX86RegTypeXmm) && o1->isRegType(kX86RegTypeXmm))
+ {
+ _emitMmu(0xF3000F7E, 0,
+ reinterpret_cast<const XmmReg&>(*o0).getRegCode(),
+ reinterpret_cast<const XmmReg&>(*o1),
+ 0);
+ _FINISHED();
+ }
+
+ // Convenience - movdq2q
+ if (o0->isRegType(kX86RegTypeMm) && o1->isRegType(kX86RegTypeXmm))
+ {
+ _emitMmu(0xF2000FD6, 0,
+ reinterpret_cast<const MmReg&>(*o0).getRegCode(),
+ reinterpret_cast<const XmmReg&>(*o1),
+ 0);
+ _FINISHED();
+ }
+
+ // Convenience - movq2dq
+ if (o0->isRegType(kX86RegTypeXmm) && o1->isRegType(kX86RegTypeMm))
+ {
+ _emitMmu(0xF3000FD6, 0,
+ reinterpret_cast<const XmmReg&>(*o0).getRegCode(),
+ reinterpret_cast<const MmReg&>(*o1),
+ 0);
+ _FINISHED();
+ }
+
+ if (o0->isRegType(kX86RegTypeMm) && o1->isMem())
+ {
+ _emitMmu(0x00000F6F, 0,
+ reinterpret_cast<const MmReg&>(*o0).getRegCode(),
+ reinterpret_cast<const Mem&>(*o1),
+ 0);
+ _FINISHED();
+ }
+
+ if (o0->isRegType(kX86RegTypeXmm) && o1->isMem())
+ {
+ _emitMmu(0xF3000F7E, 0,
+ reinterpret_cast<const XmmReg&>(*o0).getRegCode(),
+ reinterpret_cast<const Mem&>(*o1),
+ 0);
+ _FINISHED();
+ }
+
+ if (o0->isMem() && o1->isRegType(kX86RegTypeMm))
+ {
+ _emitMmu(0x00000F7F, 0,
+ reinterpret_cast<const MmReg&>(*o1).getRegCode(),
+ reinterpret_cast<const Mem&>(*o0),
+ 0);
+ _FINISHED();
+ }
+
+ if (o0->isMem() && o1->isRegType(kX86RegTypeXmm))
+ {
+ _emitMmu(0x66000FD6, 0,
+ reinterpret_cast<const XmmReg&>(*o1).getRegCode(),
+ reinterpret_cast<const Mem&>(*o0),
+ 0);
+ _FINISHED();
+ }
+
+#if defined(ASMJIT_X64)
+ if ((o0->isRegType(kX86RegTypeMm) || o0->isRegType(kX86RegTypeXmm)) && (o1->isRegType(kX86RegTypeGpq) || o1->isMem()))
+ {
+ _emitMmu(o0->isRegType(kX86RegTypeXmm) ? 0x66000F6E : 0x00000F6E, 1,
+ reinterpret_cast<const Reg&>(*o0).getRegCode(),
+ reinterpret_cast<const Operand&>(*o1),
+ 0);
+ _FINISHED();
+ }
+
+ if ((o0->isRegType(kX86RegTypeGpq) || o0->isMem()) && (o1->isRegType(kX86RegTypeMm) || o1->isRegType(kX86RegTypeXmm)))
+ {
+ _emitMmu(o1->isRegType(kX86RegTypeXmm) ? 0x66000F7E : 0x00000F7E, 1,
+ reinterpret_cast<const Reg&>(*o1).getRegCode(),
+ reinterpret_cast<const Operand&>(*o0),
+ 0);
+ _FINISHED();
+ }
+#endif // ASMJIT_X64
+
+ break;
+ }
+
+ case kX86InstGroupMmuExtract:
+ {
+ if (!(o0->isRegMem() &&
+ (o1->isRegType(kX86RegTypeXmm) || (code == kX86InstPExtrW && o1->isRegType(kX86RegTypeMm))) &&
+ o2->isImm()))
+ {
+ goto _IllegalInstruction;
+ }
+
+ uint32_t opCode = id->_opCode[0];
+ uint8_t isGpdGpq = o0->isRegType(kX86RegTypeGpd) | o0->isRegType(kX86RegTypeGpq);
+
+ if (code == kX86InstPExtrB && (o0->getSize() && o0->getSize() != 1) && !isGpdGpq)
+ goto _IllegalInstruction;
+ if (code == kX86InstPExtrW && (o0->getSize() && o0->getSize() != 2) && !isGpdGpq)
+ goto _IllegalInstruction;
+ if (code == kX86InstPExtrD && (o0->getSize() && o0->getSize() != 4) && !isGpdGpq)
+ goto _IllegalInstruction;
+ if (code == kX86InstPExtrQ && (o0->getSize() && o0->getSize() != 8) && !isGpdGpq)
+ goto _IllegalInstruction;
+
+ if (o1->isRegType(kX86RegTypeXmm)) opCode |= 0x66000000;
+
+ if (o0->isReg())
+ {
+ _emitMmu(opCode, id->_opCodeR | (uint8_t)o0->isRegType(kX86RegTypeGpq),
+ reinterpret_cast<const Reg&>(*o1).getRegCode(),
+ reinterpret_cast<const Reg&>(*o0), 1);
+ _FINISHED_IMMEDIATE(o2, 1);
+ }
+
+ if (o0->isMem())
+ {
+ _emitMmu(opCode, (uint8_t)id->_opCodeR,
+ reinterpret_cast<const Reg&>(*o1).getRegCode(),
+ reinterpret_cast<const Mem&>(*o0), 1);
+ _FINISHED_IMMEDIATE(o2, 1);
+ }
+
+ break;
+ }
+
+ case kX86InstGroupMmuPrefetch:
+ {
+ if (o0->isMem() && o1->isImm())
+ {
+ const Mem& mem = reinterpret_cast<const Mem&>(*o0);
+ const Imm& hint = reinterpret_cast<const Imm&>(*o1);
+
+ _emitMmu(0x00000F18, 0, (uint8_t)hint.getValue(), mem, 0);
+ _FINISHED();
+ }
+
+ break;
+ }
+
+ case kX86InstGroupMmuRmI:
+ {
+ ASMJIT_ASSERT(!!id->_opFlags[0]);
+ ASMJIT_ASSERT(!!id->_opFlags[1]);
+
+ // Check parameters (X)MM|GP32_64 <- (X)MM|GP32_64|Mem|Imm
+ if (!o0->isReg() ||
+ (o0->isRegType(kX86RegTypeMm ) && !(id->_opFlags[0] & kX86InstOpMm )) ||
+ (o0->isRegType(kX86RegTypeXmm) && !(id->_opFlags[0] & kX86InstOpXmm)) ||
+ (o0->isRegType(kX86RegTypeGpd) && !(id->_opFlags[0] & kX86InstOpGd )) ||
+ (o0->isRegType(kX86RegTypeGpq) && !(id->_opFlags[0] & kX86InstOpGq )) ||
+ (o1->isRegType(kX86RegTypeMm ) && !(id->_opFlags[1] & kX86InstOpMm )) ||
+ (o1->isRegType(kX86RegTypeXmm) && !(id->_opFlags[1] & kX86InstOpXmm)) ||
+ (o1->isRegType(kX86RegTypeGpd) && !(id->_opFlags[1] & kX86InstOpGd )) ||
+ (o1->isRegType(kX86RegTypeGpq) && !(id->_opFlags[1] & kX86InstOpGq )) ||
+ (o1->isMem() && !(id->_opFlags[1] & kX86InstOpMem)) ||
+ (o1->isImm() && !(id->_opFlags[1] & kX86InstOpImm)))
+ {
+ goto _IllegalInstruction;
+ }
+
+ uint32_t prefix =
+ ((id->_opFlags[0] & kX86InstOpMmXmm) == kX86InstOpMmXmm && o0->isRegType(kX86RegTypeXmm)) ||
+ ((id->_opFlags[1] & kX86InstOpMmXmm) == kX86InstOpMmXmm && o1->isRegType(kX86RegTypeXmm))
+ ? 0x66000000
+ : 0x00000000;
+
+ uint8_t rexw = ((id->_opFlags[0] | id->_opFlags[1]) & kX86InstOpNoRex)
+ ? 0
+ : o0->isRegType(kX86RegTypeGpq) | o1->isRegType(kX86RegTypeGpq);
+
+ // (X)MM <- (X)MM (opcode0)
+ if (o1->isReg())
+ {
+ if (!(id->_opFlags[1] & (kX86InstOpMmXmm | kX86InstOpGqd)))
+ goto _IllegalInstruction;
+ _emitMmu(id->_opCode[0] | prefix, rexw,
+ reinterpret_cast<const Reg&>(*o0).getRegCode(),
+ reinterpret_cast<const Reg&>(*o1), 0);
+ _FINISHED();
+ }
+ // (X)MM <- Mem (opcode0)
+ if (o1->isMem())
+ {
+ if (!(id->_opFlags[1] & kX86InstOpMem))
+ goto _IllegalInstruction;
+ _emitMmu(id->_opCode[0] | prefix, rexw,
+ reinterpret_cast<const Reg&>(*o0).getRegCode(),
+ reinterpret_cast<const Mem&>(*o1), 0);
+ _FINISHED();
+ }
+ // (X)MM <- Imm (opcode1+opcodeR)
+ if (o1->isImm())
+ {
+ if (!(id->_opFlags[1] & kX86InstOpImm))
+ goto _IllegalInstruction;
+ _emitMmu(id->_opCode[1] | prefix, rexw,
+ (uint8_t)id->_opCodeR,
+ reinterpret_cast<const Reg&>(*o0), 1);
+ _FINISHED_IMMEDIATE(o1, 1);
+ }
+
+ break;
+ }
+
+ case kX86InstGroupMmuRmImm8:
+ {
+ ASMJIT_ASSERT(!!id->_opFlags[0]);
+ ASMJIT_ASSERT(!!id->_opFlags[1]);
+
+ // Check parameters (X)MM|GP32_64 <- (X)MM|GP32_64|Mem|Imm
+ if (!o0->isReg() ||
+ (o0->isRegType(kX86RegTypeMm ) && !(id->_opFlags[0] & kX86InstOpMm )) ||
+ (o0->isRegType(kX86RegTypeXmm) && !(id->_opFlags[0] & kX86InstOpXmm)) ||
+ (o0->isRegType(kX86RegTypeGpd) && !(id->_opFlags[0] & kX86InstOpGd )) ||
+ (o0->isRegType(kX86RegTypeGpq) && !(id->_opFlags[0] & kX86InstOpGq )) ||
+ (o1->isRegType(kX86RegTypeMm ) && !(id->_opFlags[1] & kX86InstOpMm )) ||
+ (o1->isRegType(kX86RegTypeXmm) && !(id->_opFlags[1] & kX86InstOpXmm)) ||
+ (o1->isRegType(kX86RegTypeGpd) && !(id->_opFlags[1] & kX86InstOpGd )) ||
+ (o1->isRegType(kX86RegTypeGpq) && !(id->_opFlags[1] & kX86InstOpGq )) ||
+ (o1->isMem() && !(id->_opFlags[1] & kX86InstOpMem)) ||
+ !o2->isImm())
+ {
+ goto _IllegalInstruction;
+ }
+
+ uint32_t prefix =
+ ((id->_opFlags[0] & kX86InstOpMmXmm) == kX86InstOpMmXmm && o0->isRegType(kX86RegTypeXmm)) ||
+ ((id->_opFlags[1] & kX86InstOpMmXmm) == kX86InstOpMmXmm && o1->isRegType(kX86RegTypeXmm))
+ ? 0x66000000
+ : 0x00000000;
+
+ uint8_t rexw = ((id->_opFlags[0]|id->_opFlags[1]) & kX86InstOpNoRex)
+ ? 0
+ : o0->isRegType(kX86RegTypeGpq) | o1->isRegType(kX86RegTypeGpq);
+
+ // (X)MM <- (X)MM (opcode0)
+ if (o1->isReg())
+ {
+ if (!(id->_opFlags[1] & (kX86InstOpMmXmm | kX86InstOpGqd)))
+goto _IllegalInstruction;
+ _emitMmu(id->_opCode[0] | prefix, rexw,
+ reinterpret_cast<const Reg&>(*o0).getRegCode(),
+ reinterpret_cast<const Reg&>(*o1), 1);
+ _FINISHED_IMMEDIATE(o2, 1);
+ }
+ // (X)MM <- Mem (opcode0)
+ if (o1->isMem())
+ {
+ if (!(id->_opFlags[1] & kX86InstOpMem))
+ goto _IllegalInstruction;
+ _emitMmu(id->_opCode[0] | prefix, rexw,
+ reinterpret_cast<const Reg&>(*o0).getRegCode(),
+ reinterpret_cast<const Mem&>(*o1), 1);
+ _FINISHED_IMMEDIATE(o2, 1);
+ }
+
+ break;
+ }
+
+ case kX86InstGroupMmuRm3dNow:
+ {
+ if (o0->isRegType(kX86RegTypeMm) && (o1->isRegType(kX86RegTypeMm) || o1->isMem()))
+ {
+ _emitMmu(id->_opCode[0], 0,
+ reinterpret_cast<const Reg&>(*o0).getRegCode(),
+ reinterpret_cast<const Mem&>(*o1), 1);
+ _emitByte((uint8_t)id->_opCode[1]);
+ _FINISHED();
+ }
+
+ break;
+ }
+ }
+
+_IllegalInstruction:
+ // Set an error. If we run in release mode assertion will be not used, so we
+ // must inform about invalid state.
+ setError(kErrorIllegalInstruction);
+
+#if defined(ASMJIT_DEBUG)
+ assertIllegal = true;
+#endif // ASMJIT_DEBUG
+ goto _End;
+
+_EmitImmediate:
+ {
+ sysint_t value = immOperand->getValue();
+ switch (immSize)
+ {
+ case 1: _emitByte ((uint8_t )(sysuint_t)value); break;
+ case 2: _emitWord ((uint16_t)(sysuint_t)value); break;
+ case 4: _emitDWord((uint32_t)(sysuint_t)value); break;
+#if defined(ASMJIT_X64)
+ case 8: _emitQWord((uint64_t)(sysuint_t)value); break;
+#endif // ASMJIT_X64
+ default: ASMJIT_ASSERT(0);
+ }
+ }
+
+_End:
+ if (_logger
+#if defined(ASMJIT_DEBUG)
+ || assertIllegal
+#endif // ASMJIT_DEBUG
+ )
+ {
+ char bufStorage[512];
+ char* buf = bufStorage;
+
+ // Detect truncated operand.
+ Imm immTemporary(0);
+ uint32_t loggerFlags = 0;
+
+ // Use the original operands, because BYTE some of them were replaced.
+ if (bLoHiUsed)
+ {
+ o0 = _loggerOperands[0];
+ o1 = _loggerOperands[1];
+ o2 = _loggerOperands[2];
+ }
+
+ if (immOperand)
+ {
+ sysint_t value = immOperand->getValue();
+ bool isUnsigned = immOperand->isUnsigned();
+
+ switch (immSize)
+ {
+ case 1: if ( isUnsigned && !IntUtil::isUInt8 (value)) { immTemporary.setValue((uint8_t)(sysuint_t)value, true ); break; }
+ if (!isUnsigned && !IntUtil::isInt8 (value)) { immTemporary.setValue((uint8_t)(sysuint_t)value, false); break; }
+ break;
+ case 2: if ( isUnsigned && !IntUtil::isUInt16(value)) { immTemporary.setValue((uint16_t)(sysuint_t)value, true ); break; }
+ if (!isUnsigned && !IntUtil::isInt16 (value)) { immTemporary.setValue((uint16_t)(sysuint_t)value, false); break; }
+ break;
+ case 4: if ( isUnsigned && !IntUtil::isUInt32(value)) { immTemporary.setValue((uint32_t)(sysuint_t)value, true ); break; }
+ if (!isUnsigned && !IntUtil::isInt32 (value)) { immTemporary.setValue((uint32_t)(sysuint_t)value, false); break; }
+ break;
+ }
+
+ if (immTemporary.getValue())
+ {
+ if (o0 == immOperand) o0 = &immTemporary;
+ if (o1 == immOperand) o1 = &immTemporary;
+ if (o2 == immOperand) o2 = &immTemporary;
+ }
+ }
+
+ if (_logger)
+ {
+ buf = StringUtil::copy(buf, _logger->getInstructionPrefix());
+ loggerFlags = _logger->getFlags();
+ }
+
+ buf = X86Assembler_dumpInstruction(buf, code, _emitOptions, o0, o1, o2, memRegType, loggerFlags);
+
+ if (loggerFlags & kLoggerOutputBinary)
+ buf = X86Assembler_dumpComment(buf, (size_t)(buf - bufStorage), getCode() + beginOffset, getOffset() - beginOffset, _inlineComment);
+ else
+ buf = X86Assembler_dumpComment(buf, (size_t)(buf - bufStorage), nullptr, 0, _inlineComment);
+
+ // We don't need to NULL terminate the resulting string.
+#if defined(ASMJIT_DEBUG)
+ if (_logger)
+#endif // ASMJIT_DEBUG
+ _logger->logString(bufStorage, (size_t)(buf - bufStorage));
+
+#if defined(ASMJIT_DEBUG)
+ if (assertIllegal)
+ {
+ // Here we need to NULL terminate.
+ buf[0] = '\0';
+
+ // Raise an assertion failure, because this situation shouldn't happen.
+ assertionFailure(__FILE__, __LINE__, bufStorage);
+ }
+#endif // ASMJIT_DEBUG
+ }
+
+_Cleanup:
+ _inlineComment = nullptr;
+ _emitOptions = 0;
+}
+
+void X86Assembler::_emitJcc(uint32_t code, const Label* label, uint32_t hint)
+{
+ if (hint == kCondHintNone)
+ {
+ _emitInstruction(code, label);
+ }
+ else
+ {
+ Imm imm(hint);
+ _emitInstruction(code, label, &imm);
+ }
+}
+
+// ============================================================================
+// [AsmJit::Assembler - Relocation helpers]
+// ============================================================================
+
+size_t X86Assembler::relocCode(void* _dst, sysuint_t addressBase) const
+{
+ // Copy code to virtual memory (this is a given _dst pointer).
+ uint8_t* dst = reinterpret_cast<uint8_t*>(_dst);
+
+ size_t coff = _buffer.getOffset();
+
+ // We are copying the exact size of the generated code. Extra code for trampolines
+ // is generated on-the-fly by relocator (this code doesn't exist at the moment).
+ memcpy(dst, _buffer.getData(), coff);
+
+#if defined(ASMJIT_X64)
+ // Trampoline pointer.
+ uint8_t* tramp = dst + coff;
+#endif // ASMJIT_X64
+
+ // Relocate all recorded locations.
+ size_t i;
+ size_t len = _relocData.getLength();
+
+ for (i = 0; i < len; i++)
+ {
+ const RelocData& r = _relocData[i];
+ sysint_t val = 0;
+
+#if defined(ASMJIT_X64)
+ // Whether to use trampoline, can be only used if relocation type is
+ // kRelocAbsToRel.
+ bool useTrampoline = false;
+#endif // ASMJIT_X64
+
+ // Be sure that reloc data structure is correct.
+ //ASMJIT_ASSERT((size_t)(r.offset + r.size) <= csize);
+
+ switch (r.type)
+ {
+ case kRelocAbsToAbs:
+ val = (sysint_t)(r.address);
+ break;
+
+ case kRelocRelToAbs:
+ val = (sysint_t)(addressBase + r.destination);
+ break;
+
+ case kRelocAbsToRel:
+ case kRelocTrampoline:
+ val = (sysint_t)( (sysuint_t)r.address - (addressBase + (sysuint_t)r.offset + 4) );
+
+#if defined(ASMJIT_X64)
+ if (r.type == kRelocTrampoline && !IntUtil::isInt32(val))
+ {
+ val = (sysint_t)( (sysuint_t)tramp - ((sysuint_t)_dst + (sysuint_t)r.offset + 4) );
+ useTrampoline = true;
+ }
+#endif // ASMJIT_X64
+ break;
+
+ default:
+ ASMJIT_ASSERT(0);
+ }
+
+ switch (r.size)
+ {
+ case 4:
+ *reinterpret_cast<int32_t*>(dst + r.offset) = static_cast<int32_t>(val);
+ break;
+
+ case 8:
+ *reinterpret_cast<int64_t*>(dst + r.offset) = static_cast<int64_t>(val);
+ break;
+
+ default:
+ ASMJIT_ASSERT(0);
+ }
+
+#if defined(ASMJIT_X64)
+ if (useTrampoline)
+ {
+ if (getLogger())
+ {
+ getLogger()->logFormat("; Trampoline from %p -> %p\n", (int8_t*)addressBase + r.offset, r.address);
+ }
+
+ X64TrampolineWriter::writeTrampoline(tramp, (uint64_t)r.address);
+ tramp += X64TrampolineWriter::kSizeTotal;
+ }
+#endif // ASMJIT_X64
+ }
+
+#if defined(ASMJIT_X64)
+ return (size_t)(tramp - dst);
+#else
+ return (size_t)(coff);
+#endif // ASMJIT_X64
+}
+
+// ============================================================================
+// [AsmJit::Assembler - EmbedLabel]
+// ============================================================================
+
+void X86Assembler::embedLabel(const Label& label)
+{
+ ASMJIT_ASSERT(label.getId() != kInvalidValue);
+ if (!canEmit()) return;
+
+ LabelData& l_data = _labels[label.getId() & kOperandIdValueMask];
+ RelocData r_data;
+
+ if (_logger)
+ {
+ _logger->logFormat(sizeof(sysint_t) == 4 ? ".dd L.%u\n" : ".dq L.%u\n", (uint32_t)label.getId() & kOperandIdValueMask);
+ }
+
+ r_data.type = kRelocRelToAbs;
+ r_data.size = sizeof(sysint_t);
+ r_data.offset = getOffset();
+ r_data.destination = 0;
+
+ if (l_data.offset != -1)
+ {
+ // Bound label.
+ r_data.destination = l_data.offset;
+ }
+ else
+ {
+ // Non-bound label. Need to chain.
+ LabelLink* link = _newLabelLink();
+
+ link->prev = (LabelLink*)l_data.links;
+ link->offset = getOffset();
+ link->displacement = 0;
+ link->relocId = _relocData.getLength();
+
+ l_data.links = link;
+ }
+
+ _relocData.append(r_data);
+
+ // Emit dummy intptr_t (4 or 8 bytes that depends on address size).
+ _emitIntPtrT(0);
+}
+
+// ============================================================================
+// [AsmJit::Assembler - Align]
+// ============================================================================
+
+void X86Assembler::align(uint32_t m)
+{
+ if (!canEmit())
+ return;
+
+ if (_logger)
+ _logger->logFormat("%s.align %u\n", _logger->getInstructionPrefix(), (unsigned)m);
+
+ if (!m) return;
+
+ if (m > 64)
+ {
+ ASMJIT_ASSERT(0);
+ return;
+ }
+
+ sysint_t i = m - (getOffset() % m);
+ if (static_cast<uint32_t>(i) == m) return;
+
+ if (_properties & (1 << kX86PropertyOptimizedAlign))
+ {
+ const X86CpuInfo* ci = X86CpuInfo::getGlobal();
+
+ // NOPs optimized for Intel:
+ // Intel 64 and IA-32 Architectures Software Developer's Manual
+ // - Volume 2B
+ // - Instruction Set Reference N-Z
+ // - NOP
+
+ // NOPs optimized for AMD:
+ // Software Optimization Guide for AMD Family 10h Processors (Quad-Core)
+ // - 4.13 - Code Padding with Operand-Size Override and Multibyte NOP
+
+ // Intel and AMD.
+ static const uint8_t nop1[] = { 0x90 };
+ static const uint8_t nop2[] = { 0x66, 0x90 };
+ static const uint8_t nop3[] = { 0x0F, 0x1F, 0x00 };
+ static const uint8_t nop4[] = { 0x0F, 0x1F, 0x40, 0x00 };
+ static const uint8_t nop5[] = { 0x0F, 0x1F, 0x44, 0x00, 0x00 };
+ static const uint8_t nop6[] = { 0x66, 0x0F, 0x1F, 0x44, 0x00, 0x00 };
+ static const uint8_t nop7[] = { 0x0F, 0x1F, 0x80, 0x00, 0x00, 0x00, 0x00 };
+ static const uint8_t nop8[] = { 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 };
+ static const uint8_t nop9[] = { 0x66, 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+ // AMD.
+ static const uint8_t nop10[] = { 0x66, 0x66, 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 };
+ static const uint8_t nop11[] = { 0x66, 0x66, 0x66, 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+ const uint8_t* p;
+ sysint_t n;
+
+ if (ci->getVendorId() == kCpuIntel && ((ci->getFamily() & 0x0F) == 6 || (ci->getFamily() & 0x0F) == 15))
+ {
+ do {
+ switch (i)
+ {
+ case 1: p = nop1; n = 1; break;
+ case 2: p = nop2; n = 2; break;
+ case 3: p = nop3; n = 3; break;
+ case 4: p = nop4; n = 4; break;
+ case 5: p = nop5; n = 5; break;
+ case 6: p = nop6; n = 6; break;
+ case 7: p = nop7; n = 7; break;
+ case 8: p = nop8; n = 8; break;
+ default: p = nop9; n = 9; break;
+ }
+
+ i -= n;
+ do { _emitByte(*p++); } while(--n);
+ } while (i);
+
+ return;
+ }
+
+ if (ci->getVendorId() == kCpuAmd && ci->getFamily() >= 0x0F)
+ {
+ do {
+ switch (i)
+ {
+ case 1: p = nop1 ; n = 1; break;
+ case 2: p = nop2 ; n = 2; break;
+ case 3: p = nop3 ; n = 3; break;
+ case 4: p = nop4 ; n = 4; break;
+ case 5: p = nop5 ; n = 5; break;
+ case 6: p = nop6 ; n = 6; break;
+ case 7: p = nop7 ; n = 7; break;
+ case 8: p = nop8 ; n = 8; break;
+ case 9: p = nop9 ; n = 9; break;
+ case 10: p = nop10; n = 10; break;
+ default: p = nop11; n = 11; break;
+ }
+
+ i -= n;
+ do { _emitByte(*p++); } while(--n);
+ } while (i);
+
+ return;
+ }
+#if defined(ASMJIT_X86)
+ // Legacy NOPs, 0x90 with 0x66 prefix.
+ do {
+ switch (i)
+ {
+ default: _emitByte(0x66); i--;
+ case 3: _emitByte(0x66); i--;
+ case 2: _emitByte(0x66); i--;
+ case 1: _emitByte(0x90); i--;
+ }
+ } while(i);
+#endif
+ }
+
+ // Legacy NOPs, only 0x90. In 64-bit mode, we can't use 0x66 prefix.
+ do {
+ _emitByte(0x90);
+ } while(--i);
+}
+
+// ============================================================================
+// [AsmJit::Assembler - Label]
+// ============================================================================
+
+Label X86Assembler::newLabel()
+{
+ Label label;
+ label._base.id = (uint32_t)_labels.getLength() | kOperandIdTypeLabel;
+
+ LabelData l_data;
+ l_data.offset = -1;
+ l_data.links = nullptr;
+ _labels.append(l_data);
+
+ return label;
+}
+
+void X86Assembler::registerLabels(size_t count)
+{
+ // Duplicated newLabel() code, but we are not creating Label instances.
+ LabelData l_data;
+ l_data.offset = -1;
+ l_data.links = nullptr;
+
+ for (size_t i = 0; i < count; i++)
+ _labels.append(l_data);
+}
+
+void X86Assembler::bind(const Label& label)
+{
+ // Only labels created by newLabel() can be used by Assembler.
+ ASMJIT_ASSERT(label.getId() != kInvalidValue);
+ // Never go out of bounds.
+ ASMJIT_ASSERT((label.getId() & kOperandIdValueMask) < _labels.getLength());
+
+ // Get label data based on label id.
+ LabelData& l_data = _labels[label.getId() & kOperandIdValueMask];
+
+ // Label can be bound only once.
+ ASMJIT_ASSERT(l_data.offset == -1);
+
+ // Log.
+ if (_logger) _logger->logFormat("L.%u:\n", (uint32_t)label.getId() & kOperandIdValueMask);
+
+ sysint_t pos = getOffset();
+
+ LabelLink* link = l_data.links;
+ LabelLink* prev = nullptr;
+
+ while (link)
+ {
+ sysint_t offset = link->offset;
+
+ if (link->relocId != -1)
+ {
+ // If linked label points to RelocData then instead of writing relative
+ // displacement to assembler stream, we will write it to RelocData.
+ _relocData[link->relocId].destination += pos;
+ }
+ else
+ {
+ // Not using relocId, this means that we overwriting real displacement
+ // in assembler stream.
+ int32_t patchedValue = (int32_t)(pos - offset + link->displacement);
+ uint32_t size = getByteAt(offset);
+
+ // Only these size specifiers are allowed.
+ ASMJIT_ASSERT(size == 1 || size == 4);
+
+ if (size == 4)
+ {
+ setInt32At(offset, patchedValue);
+ }
+ else // if (size == 1)
+ {
+ if (IntUtil::isInt8(patchedValue))
+ {
+ setByteAt(offset, (uint8_t)(int8_t)patchedValue);
+ }
+ else
+ {
+ // Fatal error.
+ setError(kErrorIllegalShortJump);
+ }
+ }
+ }
+
+ prev = link->prev;
+ link = prev;
+ }
+
+ // Chain unused links.
+ link = l_data.links;
+ if (link)
+ {
+ if (!prev) prev = link;
+
+ prev->prev = _unusedLinks;
+ _unusedLinks = link;
+ }
+
+ // Unlink label if it was linked.
+ l_data.offset = pos;
+ l_data.links = nullptr;
+}
+
+// ============================================================================
+// [AsmJit::Assembler - Make]
+// ============================================================================
+
+void* X86Assembler::make()
+{
+ // Do nothing on error state or when no instruction was emitted.
+ if (_error || !getCodeSize())
+ return nullptr;
+
+ void* p;
+ _error = _context->generate(&p, this);
+ return p;
+}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86/x86assembler.h
@@ -1,1 +1,5444 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_X86_X86ASSEMBLER_H
+#define _ASMJIT_X86_X86ASSEMBLER_H
+
+// [Dependencies - AsmJit]
+#include "../core/assembler.h"
+
+#include "../x86/x86defs.h"
+#include "../x86/x86operand.h"
+#include "../x86/x86util.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+//! @addtogroup AsmJit_X86
+//! @{
+
+// ============================================================================
+// [AsmJit::X86Assembler]
+// ============================================================================
+
+//! @brief X86Assembler - low level x86/x64 code generation.
+//!
+//! @ref X86Assembler is the main class in AsmJit for generating low level
+//! x86/x64 binary stream. It creates internal buffer where opcodes are stored
+//! and contains methods that mimics x86/x64 assembler instructions. Code
+//! generation should be safe, because basic type-checks are done by the C++
+//! compiler. It's nearly impossible to create invalid instruction (for example
+//! <code>mov [eax], [eax]</code> that will not be detected at compile time by
+//! C++ compiler.
+//!
+//! Each call to assembler intrinsics directly emits instruction to internal
+//! binary stream. Instruction emitting also contains runtime checks so it
+//! should be impossible to create an instruction that is not valid (except
+//! there is bug in AsmJit).
+//!
+//! @ref X86Assembler contains internal buffer where all emitted instructions
+//! are stored. Look at @ref Buffer for an implementation. To generate and
+//! allocate memory for function use @ref X86Assembler::make() method that will
+//! allocate memory using the provided memory manager (see @ref MemoryManager)
+//! and relocates the output code to the provided address. If you want to create
+//! your function manually, you should look at @ref VirtualMemory interface and
+//! use @ref X86Assembler::relocCode() method to relocate emitted code into
+//! provided memory location. You can also take the emitted buffer by @ref
+//! X86Assembler::take() to do something else with it. If you take buffer, you
+//! must free it manually by using @ref ASMJIT_FREE() macro.
+//!
+//! @section AsmJit_Assembler_CodeGeneration Code Generation
+//!
+//! To generate code is only needed to create instance of @c AsmJit::Assembler
+//! and to use intrinsics. See example how to do that:
+//!
+//! @code
+//! // Use AsmJit namespace.
+//! using namespace AsmJit;
+//!
+//! // Create Assembler instance.
+//! Assembler a;
+//!
+//! // Prolog.
+//! a.push(ebp);
+//! a.mov(ebp, esp);
+//!
+//! // Mov 1024 to EAX, EAX is also return value.
+//! a.mov(eax, imm(1024));
+//!
+//! // Epilog.
+//! a.mov(esp, ebp);
+//! a.pop(ebp);
+//!
+//! // Return.
+//! a.ret();
+//! @endcode
+//!
+//! You can see that syntax is very close to Intel one. Only difference is that
+//! you are calling functions that emits the binary code for you. All registers
+//! are in @c AsmJit namespace, so it's very comfortable to use it (look at
+//! first line). There is also used method @c AsmJit::imm() to create an
+//! immediate value. Use @c AsmJit::uimm() to create unsigned immediate value.
+//!
+//! There is also possibility to use memory addresses and immediates. To build
+//! memory address use @c ptr(), @c byte_ptr(), @c word_ptr(), @c dword_ptr()
+//! or other friend methods. In most cases you needs only @c ptr() method, but
+//! there are instructions where you must specify address size,
+//!
+//! for example (a is @c AsmJit::Assembler instance):
+//!
+//! @code
+//! a.mov(ptr(eax), imm(0)); // mov ptr [eax], 0
+//! a.mov(ptr(eax), edx); // mov ptr [eax], edx
+//! @endcode
+//!
+//! But it's also possible to create complex addresses:
+//!
+//! @code
+//! // eax + ecx*x addresses
+//! a.mov(ptr(eax, ecx, kScaleNone), imm(0)); // mov ptr [eax + ecx], 0
+//! a.mov(ptr(eax, ecx, kScale2Times), imm(0)); // mov ptr [eax + ecx * 2], 0
+//! a.mov(ptr(eax, ecx, kScale4Times), imm(0)); // mov ptr [eax + ecx * 4], 0
+//! a.mov(ptr(eax, ecx, kScale8Times), imm(0)); // mov ptr [eax + ecx * 8], 0
+//! // eax + ecx*x + disp addresses
+//! a.mov(ptr(eax, ecx, kScaleNone, 4), imm(0)); // mov ptr [eax + ecx + 4], 0
+//! a.mov(ptr(eax, ecx, kScale2Times, 8), imm(0)); // mov ptr [eax + ecx * 2 + 8], 0
+//! a.mov(ptr(eax, ecx, kScale4Times, 12), imm(0)); // mov ptr [eax + ecx * 4 + 12], 0
+//! a.mov(ptr(eax, ecx, kScale8Times, 16), imm(0)); // mov ptr [eax + ecx * 8 + 16], 0
+//! @endcode
+//!
+//! All addresses shown are using @c AsmJit::ptr() to make memory operand.
+//! Some assembler instructions (single operand ones) needs to specify memory
+//! operand size. For example calling <code>a.inc(ptr(eax))</code> can't be
+//! used. @c AsmJit::Assembler::inc(), @c AsmJit::Assembler::dec() and similar
+//! instructions can't be serialized without specifying how bytes they are
+//! operating on. See next code how assembler works:
+//!
+//! @code
+//! // [byte] address
+//! a.inc(byte_ptr(eax)); // inc byte ptr [eax]
+//! a.dec(byte_ptr(eax)); // dec byte ptr [eax]
+//! // [word] address
+//! a.inc(word_ptr(eax)); // inc word ptr [eax]
+//! a.dec(word_ptr(eax)); // dec word ptr [eax]
+//! // [dword] address
+//! a.inc(dword_ptr(eax)); // inc dword ptr [eax]
+//! a.dec(dword_ptr(eax)); // dec dword ptr [eax]
+//! @endcode
+//!
+//! @section AsmJit_Assembler_CallingJitCode Calling JIT Code
+//!
+//! While you are over from emitting instructions, you can make your function
+//! using @c AsmJit::Assembler::make() method. This method will use memory
+//! manager to allocate virtual memory and relocates generated code to it. For
+//! memory allocation is used global memory manager by default and memory is
+//! freeable, but of course this default behavior can be overridden specifying
+//! your memory manager and allocation type. If you want to do with code
+//! something else you can always override make() method and do what you want.
+//!
+//! You can get size of generated code by @c getCodeSize() or @c getOffset()
+//! methods. These methods returns you code size (or more precisely current code
+//! offset) in bytes. Use takeCode() to take internal buffer (all pointers in
+//! @c AsmJit::Assembler instance will be zeroed and current buffer returned)
+//! to use it. If you don't take it, @c AsmJit::Assembler destructor will
+//! free it automatically. To alloc and run code manually don't use
+//! @c malloc()'ed memory, but instead use @c AsmJit::VirtualMemory::alloc()
+//! to get memory for executing (specify @c canExecute to @c true) or
+//! @c AsmJit::MemoryManager that provides more effective and comfortable way
+//! to allocate virtual memory.
+//!
+//! See next example how to allocate memory where you can execute code created
+//! by @c AsmJit::Assembler:
+//!
+//! @code
+//! using namespace AsmJit;
+//!
+//! Assembler a;
+//!
+//! // ... your code generation
+//!
+//! // your function prototype
+//! typedef void (*MyFn)();
+//!
+//! // make your function
+//! MyFn fn = asmjit_cast<MyFn>(a.make());
+//!
+//! // call your function
+//! fn();
+//!
+//! // If you don't need your function again, free it.
+//! MemoryManager::getGlobal()->free(fn);
+//! @endcode
+//!
+//! There is also low level alternative how to allocate virtual memory and
+//! relocate code to it:
+//!
+//! @code
+//! using namespace AsmJit;
+//!
+//! Assembler a;
+//! // Your code generation ...
+//!
+//! // Your function prototype.
+//! typedef void (*MyFn)();
+//!
+//! // Alloc memory for your function.
+//! MyFn fn = asmjit_cast<MyFn>(
+//! MemoryManager::getGlobal()->alloc(a.getCodeSize());
+//!
+//! // Relocate the code (will make the function).
+//! a.relocCode(fn);
+//!
+//! // Call the generated function.
+//! fn();
+//!
+//! // If you don't need your function anymore, it should be freed.
+//! MemoryManager::getGlobal()->free(fn);
+//! @endcode
+//!
+//! @c note This was very primitive example how to call generated code.
+//! In real production code you will never alloc and free code for one run,
+//! you will usually use generated code many times.
+//!
+//! @section AsmJit_Assembler_Labels Labels
+//!
+//! While generating assembler code, you will usually need to create complex
+//! code with labels. Labels are fully supported and you can call @c jmp or
+//! @c je (and similar) instructions to initialized or yet uninitialized label.
+//! Each label expects to be bound into offset. To bind label to specific
+//! offset, use @c bind() method.
+//!
+//! See next example that contains complete code that creates simple memory
+//! copy function (in DWORD entities).
+//!
+//! @code
+//! // Example: Usage of Label (32-bit code).
+//! //
+//! // Create simple DWORD memory copy function:
+//! // ASMJIT_STDCALL void copy32(uint32_t* dst, const uint32_t* src, size_t count);
+//! using namespace AsmJit;
+//!
+//! // Assembler instance.
+//! Assembler a;
+//!
+//! // Constants.
+//! const int arg_offset = 8; // Arguments offset (STDCALL EBP).
+//! const int arg_size = 12; // Arguments size.
+//!
+//! // Labels.
+//! Label L_Loop = a.newLabel();
+//!
+//! // Prolog.
+//! a.push(ebp);
+//! a.mov(ebp, esp);
+//! a.push(esi);
+//! a.push(edi);
+//!
+//! // Fetch arguments
+//! a.mov(esi, dword_ptr(ebp, arg_offset + 0)); // Get dst.
+//! a.mov(edi, dword_ptr(ebp, arg_offset + 4)); // Get src.
+//! a.mov(ecx, dword_ptr(ebp, arg_offset + 8)); // Get count.
+//!
+//! // Bind L_Loop label to here.
+//! a.bind(L_Loop);
+//!
+//! Copy 4 bytes.
+//! a.mov(eax, dword_ptr(esi));
+//! a.mov(dword_ptr(edi), eax);
+//!
+//! // Increment pointers.
+//! a.add(esi, 4);
+//! a.add(edi, 4);
+//!
+//! // Repeat loop until (--ecx != 0).
+//! a.dec(ecx);
+//! a.jz(L_Loop);
+//!
+//! // Epilog.
+//! a.pop(edi);
+//! a.pop(esi);
+//! a.mov(esp, ebp);
+//! a.pop(ebp);
+//!
+//! // Return: STDCALL convention is to pop stack in called function.
+//! a.ret(arg_size);
+//! @endcode
+//!
+//! If you need more abstraction for generating assembler code and you want
+//! to hide calling conventions between 32-bit and 64-bit operating systems,
+//! look at @c Compiler class that is designed for higher level code
+//! generation.
+//!
+//! @section AsmJit_Assembler_AdvancedCodeGeneration Advanced Code Generation
+//!
+//! This section describes some advanced generation features of @c Assembler
+//! class which can be simply overlooked. The first thing that is very likely
+//! needed is generic register support. In previous example the named registers
+//! were used. AsmJit contains functions which can convert register index into
+//! operand and back.
+//!
+//! Let's define function which can be used to generate some abstract code:
+//!
+//! @code
+//! // Simple function that generates dword copy.
+//! void genCopyDWord(
+//! Assembler& a,
+//! const GpReg& dst, const GpReg& src, const GpReg& tmp)
+//! {
+//! a.mov(tmp, dword_ptr(src));
+//! a.mov(dword_ptr(dst), tmp);
+//! }
+//! @endcode
+//!
+//! This function can be called like <code>genCopyDWord(a, edi, esi, ebx)</code>
+//! or by using existing @ref GpReg instances. This abstraction allows to join
+//! more code sections together without rewriting each to use specific registers.
+//! You need to take care only about implicit registers which may be used by
+//! several instructions (like mul, imul, div, idiv, shifting, etc...).
+//!
+//! Next, more advanced, but often needed technique is that you can build your
+//! own registers allocator. X86 architecture contains 8 general purpose registers,
+//! 8 MMX (MM) registers and 8 SSE (XMM) registers. The X64 (AMD64) architecture
+//! extends count of general purpose registers and SSE2 registers to 16. Use the
+//! @c kX86RegNumBase constant to get count of GP or XMM registers or @c kX86RegNumGp,
+//! @c kX86RegNumMm and @c kX86RegNumXmm constants individually.
+//!
+//! To build register from index (value from 0 inclusive to kRegNumXXX
+//! exclusive) use @ref gpd(), @ref gpq() or @ref gpz() functions. To create
+//! a 8 or 16-bit register use @ref gpw(), @ref gpb_lo() or @ref gpb_hi().
+//! To create other registers there are similar methods like @ref mm(), @ref xmm()
+//! and @ref st().
+//!
+//! So our function call to genCopyDWord can be also used like this:
+//!
+//! @code
+//! genCopyDWord(a, gpd(kX86RegIndexEdi), gpd(kX86RegIndexEsi), gpd(kX86RegIndexEbx));
+//! @endcode
+//!
+//! kX86RegIndexXXX are constants defined by @ref kX86RegIndex enum. You can use your
+//! own register allocator (or register slot manager) to alloc / free registers
+//! so kX86RegIndexXXX values can be replaced by your variables (0 to kRegNumXXX-1).
+//!
+//! @sa @ref X86Compiler.
+struct X86Assembler : public Assembler
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API X86Assembler(Context *context = JitContext::getGlobal());
+ ASMJIT_API virtual ~X86Assembler();
+
+ // --------------------------------------------------------------------------
+ // [Buffer - Setters (X86-Extensions)]
+ // --------------------------------------------------------------------------
+
+ //! @brief Set custom variable @a i at position @a pos.
+ //!
+ //! @note This function is used to patch existing code.
+ ASMJIT_API void setVarAt(size_t pos, sysint_t i, uint8_t isUnsigned, uint32_t size);
+
+ // --------------------------------------------------------------------------
+ // [Emit]
+ //
+ // These functions are not protected against buffer overrun. Each place of
+ // code which calls these functions ensures that there is some space using
+ // canEmit() method. Emitters are internally protected in AsmJit::Buffer,
+ // but only in debug builds.
+ // --------------------------------------------------------------------------
+
+ //! @brief Emit single @a opCode without operands.
+ void _emitOpCode(uint32_t opCode)
+ {
+ // Instruction prefix.
+ if (opCode & 0xFF000000)
+ _emitByte(static_cast<uint8_t>((opCode >> 24) & 0xFF));
+
+ // Instruction opcodes.
+ if (opCode & 0x00FF0000)
+ _emitByte(static_cast<uint8_t>((opCode >> 16) & 0xFF));
+ if (opCode & 0x0000FF00)
+ _emitByte(static_cast<uint8_t>((opCode >> 8) & 0xFF));
+
+ // Last opcode is always emitted (can be also 0x00).
+ _emitByte(static_cast<uint8_t>(opCode & 0xFF));
+ }
+
+ //! @brief Emit MODR/M byte.
+ void _emitMod(uint8_t m, uint8_t o, uint8_t r) { this->_emitByte(((m & 0x03) << 6) | ((o & 0x07) << 3) | (r & 0x07)); }
+
+ //! @brief Emit SIB byte.
+ void _emitSib(uint8_t s, uint8_t i, uint8_t b) { this->_emitByte(((s & 0x03) << 6) | ((i & 0x07) << 3) | (b & 0x07)); }
+
+ //! @brief Emit REX prefix (64-bit mode only).
+ void _emitRexR(uint8_t w, uint8_t opReg, uint8_t regCode, bool forceRexPrefix)
+ {
+#ifdef ASMJIT_X64
+ // w - Default operand size(0=Default, 1=64-bit).
+ // r - Register field (1=high bit extension of the ModR/M REG field).
+ // x - Index field not used in RexR
+ // b - Base field (1=high bit extension of the ModR/M or SIB Base field).
+ uint32_t rex = static_cast<uint32_t>(!!forceRexPrefix) << 6; // Rex prefix code.
+ rex += static_cast<uint32_t>(w) << 3; // Rex.W (w << 3).
+ rex += (static_cast<uint32_t>(opReg) & 0x08) >> 1; // Rex.R (r << 2).
+ rex += (static_cast<uint32_t>(regCode) & 0x08) >> 3; // Rex.B (b << 0).
+
+ if (rex)
+ this->_emitByte(static_cast<uint8_t>(rex | 0x40));
+#else
+ ASMJIT_UNUSED(w);
+ ASMJIT_UNUSED(opReg);
+ ASMJIT_UNUSED(regCode);
+ ASMJIT_UNUSED(forceRexPrefix);
+#endif // ASMJIT_X64
+ }
+
+ //! @brief Emit REX prefix (64-bit mode only).
+ void _emitRexRM(uint8_t w, uint8_t opReg, const Operand &rm, bool forceRexPrefix)
+ {
+#ifdef ASMJIT_X64
+ // w - Default operand size(0=Default, 1=64-bit).
+ // r - Register field (1=high bit extension of the ModR/M REG field).
+ // x - Index field (1=high bit extension of the SIB Index field).
+ // b - Base field (1=high bit extension of the ModR/M or SIB Base field).
+ uint32_t rex = static_cast<uint32_t>(!!forceRexPrefix) << 6; // Rex prefix code.
+ rex += static_cast<uint32_t>(w) << 3; // Rex.W (w << 3).
+ rex += (static_cast<uint32_t>(opReg) & 0x08) >> 1; // Rex.R (r << 2).
+
+ uint32_t b = 0;
+ uint32_t x = 0;
+
+ if (rm.isReg())
+ b = !!(static_cast<const Reg &>(rm).getRegCode() & 0x08);
+ else if (rm.isMem())
+ {
+ b = !!(static_cast<const Mem &>(rm).getBase() & 0x8) && static_cast<const Mem &>(rm).getBase() != kInvalidValue;
+ x = !!(static_cast<const Mem &>(rm).getIndex() & 0x8) && static_cast<const Mem &>(rm).getIndex() != kInvalidValue;
+ }
+
+ rex += x << 1; // Rex.R (x << 1).
+ rex += b; // Rex.B (b << 0).
+
+ if (rex)
+ this->_emitByte(static_cast<uint8_t>(rex | 0x40));
+#else
+ ASMJIT_UNUSED(w);
+ ASMJIT_UNUSED(opReg);
+ ASMJIT_UNUSED(rm);
+#endif // ASMJIT_X64
+ }
+
+ //! @brief Emit Register / Register - calls _emitMod(3, opReg, r)
+ void _emitModR(uint8_t opReg, uint8_t r) { this->_emitMod(3, opReg, r); }
+
+ //! @brief Emit Register / Register - calls _emitMod(3, opReg, r.code())
+ void _emitModR(uint8_t opReg, const Reg &r) { this->_emitMod(3, opReg, r.getRegCode()); }
+
+ //! @brief Emit register / memory address combination to buffer.
+ //!
+ //! This method can hangle addresses from simple to complex ones with
+ //! index and displacement.
+ ASMJIT_API void _emitModM(uint8_t opReg, const Mem &mem, sysint_t immSize);
+
+ //! @brief Emit Reg<-Reg or Reg<-Reg|Mem ModRM (can be followed by SIB
+ //! and displacement) to buffer.
+ //!
+ //! This function internally calls @c _emitModM() or _emitModR() that depends
+ //! to @a op type.
+ //!
+ //! @note @a opReg is usually real register ID (see @c R) but some instructions
+ //! have specific format and in that cases @a opReg is part of opcode.
+ ASMJIT_API void _emitModRM(uint8_t opReg, const Operand &op, sysint_t immSize);
+
+ //! @brief Emit CS (code segmend) prefix.
+ //!
+ //! Behavior of this function is to emit code prefix only if memory operand
+ //! address uses code segment. Code segment is used through memory operand
+ //! with attached @c AsmJit::Label.
+ ASMJIT_API void _emitSegmentPrefix(const Operand &rm);
+
+ //! @brief Emit instruction where register is inlined to opcode.
+ ASMJIT_API void _emitX86Inl(uint32_t opCode, uint8_t i16bit, uint8_t rexw, uint8_t reg, bool forceRexPrefix);
+
+ //! @brief Emit instruction with reg/memory operand.
+ ASMJIT_API void _emitX86RM(uint32_t opCode, uint8_t i16bit, uint8_t rexw, uint8_t o, const Operand &op, sysint_t immSize, bool forceRexPrefix);
+
+ //! @brief Emit FPU instruction with no operands.
+ ASMJIT_API void _emitFpu(uint32_t opCode);
+
+ //! @brief Emit FPU instruction with one operand @a sti (index of FPU register).
+ ASMJIT_API void _emitFpuSTI(uint32_t opCode, uint32_t sti);
+
+ //! @brief Emit FPU instruction with one operand @a opReg and memory operand @a mem.
+ ASMJIT_API void _emitFpuMEM(uint32_t opCode, uint8_t opReg, const Mem &mem);
+
+ //! @brief Emit MMX/SSE instruction.
+ ASMJIT_API void _emitMmu(uint32_t opCode, uint8_t rexw, uint8_t opReg, const Operand& src, sysint_t immSize);
+
+ //! @brief Emit displacement.
+ ASMJIT_API LabelLink *_emitDisplacement(LabelData &l_data, sysint_t inlinedDisplacement, int size);
+
+ //! @brief Emit relative relocation to absolute pointer @a target. It's needed
+ //! to add what instruction is emitting this, because in x64 mode the relative
+ //! displacement can be impossible to calculate and in this case the trampoline
+ //! is used.
+ ASMJIT_API void _emitJmpOrCallReloc(uint32_t instruction, void *target);
+
+ // Helpers to decrease binary code size. These four emit methods are just
+ // helpers thats used by assembler. They call emitX86() adding NULLs
+ // to first, second and third operand, if needed.
+
+ //! @brief Emit X86/FPU or MM/XMM instruction.
+ ASMJIT_API void _emitInstruction(uint32_t code);
+
+ //! @brief Emit X86/FPU or MM/XMM instruction.
+ ASMJIT_API void _emitInstruction(uint32_t code, const Operand *o0);
+
+ //! @brief Emit X86/FPU or MM/XMM instruction.
+ ASMJIT_API void _emitInstruction(uint32_t code, const Operand *o0, const Operand *o1);
+
+ //! @brief Emit X86/FPU or MM/XMM instruction.
+ //!
+ //! Operands @a o1, @a o2 or @a o3 can be @c NULL if they are not used.
+ //!
+ //! Hint: Use @c emitX86() helpers to emit instructions.
+ ASMJIT_API void _emitInstruction(uint32_t code, const Operand *o0, const Operand *o1, const Operand *o2);
+
+ //! @brief Private method for emitting jcc.
+ ASMJIT_API void _emitJcc(uint32_t code, const Label *label, uint32_t hint);
+
+ //! @brief Private method for emitting short jcc.
+ void _emitShortJcc(uint32_t code, const Label *label, uint32_t hint)
+ {
+ this->_emitOptions |= kX86EmitOptionShortJump;
+ this->_emitJcc(code, label, hint);
+ }
+
+ // --------------------------------------------------------------------------
+ // [EmbedLabel]
+ // --------------------------------------------------------------------------
+
+ //! @brief Embed absolute label pointer (4 or 8 bytes).
+ ASMJIT_API void embedLabel(const Label &label);
+
+ // --------------------------------------------------------------------------
+ // [Align]
+ // --------------------------------------------------------------------------
+
+ //! @brief Align target buffer to @a m bytes.
+ //!
+ //! Typical usage of this is to align labels at start of the inner loops.
+ //!
+ //! Inserts @c nop() instructions or CPU optimized NOPs.
+ ASMJIT_API void align(uint32_t m);
+
+ // --------------------------------------------------------------------------
+ // [Label]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create and return new label.
+ ASMJIT_API Label newLabel();
+
+ //! @brief Register labels (used by @c Compiler).
+ ASMJIT_API void registerLabels(size_t count);
+
+ //! @brief Bind label to the current offset.
+ //!
+ //! @note Label can be bound only once!
+ ASMJIT_API void bind(const Label &label);
+
+ // --------------------------------------------------------------------------
+ // [Reloc]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual size_t relocCode(void *dst, sysuint_t addressBase) const;
+
+ // --------------------------------------------------------------------------
+ // [Make]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual void *make();
+
+ // --------------------------------------------------------------------------
+ // [Embed]
+ // --------------------------------------------------------------------------
+
+ //! @brief Add 8-bit integer data to the instuction stream.
+ void db(uint8_t x) { embed(&x, 1); }
+ //! @brief Add 16-bit integer data to the instuction stream.
+ void dw(uint16_t x) { embed(&x, 2); }
+ //! @brief Add 32-bit integer data to the instuction stream.
+ void dd(uint32_t x) { embed(&x, 4); }
+ //! @brief Add 64-bit integer data to the instuction stream.
+ void dq(uint64_t x) { embed(&x, 8); }
+
+ //! @brief Add 8-bit integer data to the instuction stream.
+ void dint8(int8_t x) { embed(&x, sizeof(int8_t)); }
+ //! @brief Add 8-bit integer data to the instuction stream.
+ void duint8(uint8_t x) { embed(&x, sizeof(uint8_t)); }
+
+ //! @brief Add 16-bit integer data to the instuction stream.
+ void dint16(int16_t x) { embed(&x, sizeof(int16_t)); }
+ //! @brief Add 16-bit integer data to the instuction stream.
+ void duint16(uint16_t x) { embed(&x, sizeof(uint16_t)); }
+
+ //! @brief Add 32-bit integer data to the instuction stream.
+ void dint32(int32_t x) { embed(&x, sizeof(int32_t)); }
+ //! @brief Add 32-bit integer data to the instuction stream.
+ void duint32(uint32_t x) { embed(&x, sizeof(uint32_t)); }
+
+ //! @brief Add 64-bit integer data to the instuction stream.
+ void dint64(int64_t x) { embed(&x, sizeof(int64_t)); }
+ //! @brief Add 64-bit integer data to the instuction stream.
+ void duint64(uint64_t x) { embed(&x, sizeof(uint64_t)); }
+
+ //! @brief Add system-integer data to the instuction stream.
+ void dintptr(intptr_t x) { embed(&x, sizeof(intptr_t)); }
+ //! @brief Add system-integer data to the instuction stream.
+ void duintptr(uintptr_t x) { embed(&x, sizeof(uintptr_t)); }
+
+ //! @brief Add float data to the instuction stream.
+ void dfloat(float x) { embed(&x, sizeof(float)); }
+ //! @brief Add double data to the instuction stream.
+ void ddouble(double x) { embed(&x, sizeof(double)); }
+
+ //! @brief Add pointer data to the instuction stream.
+ void dptr(void* x) { embed(&x, sizeof(void*)); }
+
+ //! @brief Add MM data to the instuction stream.
+ void dmm(const MmData& x) { embed(&x, sizeof(MmData)); }
+ //! @brief Add XMM data to the instuction stream.
+ void dxmm(const XmmData& x) { embed(&x, sizeof(XmmData)); }
+
+ //! @brief Add data to the instuction stream.
+ void data(const void* data, size_t size) { embed(data, size); }
+
+ //! @brief Add data in a given structure instance to the instuction stream.
+ template<typename T>
+ void dstruct(const T& x) { embed(&x, sizeof(T)); }
+
+ // --------------------------------------------------------------------------
+ // [X86 Instructions]
+ // --------------------------------------------------------------------------
+
+ //! @brief Add with Carry.
+ void adc(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstAdc, &dst, &src); }
+ //! @brief Add with Carry.
+ void adc(const GpReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstAdc, &dst, &src); }
+ //! @brief Add with Carry.
+ void adc(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstAdc, &dst, &src); }
+ //! @brief Add with Carry.
+ void adc(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstAdc, &dst, &src); }
+ //! @brief Add with Carry.
+ void adc(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstAdc, &dst, &src); }
+
+ //! @brief Add.
+ void add(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstAdd, &dst, &src); }
+ //! @brief Add.
+ void add(const GpReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstAdd, &dst, &src); }
+ //! @brief Add.
+ void add(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstAdd, &dst, &src); }
+ //! @brief Add.
+ void add(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstAdd, &dst, &src); }
+ //! @brief Add.
+ void add(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstAdd, &dst, &src); }
+
+ //! @brief Logical And.
+ void and_(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstAnd, &dst, &src); }
+ //! @brief Logical And.
+ void and_(const GpReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstAnd, &dst, &src); }
+ //! @brief Logical And.
+ void and_(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstAnd, &dst, &src); }
+ //! @brief Logical And.
+ void and_(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstAnd, &dst, &src); }
+ //! @brief Logical And.
+ void and_(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstAnd, &dst, &src); }
+
+ //! @brief Bit Scan Forward.
+ void bsf(const GpReg& dst, const GpReg& src)
+ {
+ ASMJIT_ASSERT(!dst.isGpb());
+ _emitInstruction(kX86InstBsf, &dst, &src);
+ }
+ //! @brief Bit Scan Forward.
+ void bsf(const GpReg& dst, const Mem& src)
+ {
+ ASMJIT_ASSERT(!dst.isGpb());
+ _emitInstruction(kX86InstBsf, &dst, &src);
+ }
+
+ //! @brief Bit Scan Reverse.
+ void bsr(const GpReg& dst, const GpReg& src)
+ {
+ ASMJIT_ASSERT(!dst.isGpb());
+ _emitInstruction(kX86InstBsr, &dst, &src);
+ }
+ //! @brief Bit Scan Reverse.
+ void bsr(const GpReg& dst, const Mem& src)
+ {
+ ASMJIT_ASSERT(!dst.isGpb());
+ _emitInstruction(kX86InstBsr, &dst, &src);
+ }
+
+ //! @brief Byte swap (32-bit or 64-bit registers only) (i486).
+ void bswap(const GpReg& dst)
+ {
+ ASMJIT_ASSERT(dst.getRegType() == kX86RegTypeGpd || dst.getRegType() == kX86RegTypeGpq);
+ _emitInstruction(kX86InstBSwap, &dst);
+ }
+
+ //! @brief Bit test.
+ void bt(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstBt, &dst, &src); }
+ //! @brief Bit test.
+ void bt(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstBt, &dst, &src); }
+ //! @brief Bit test.
+ void bt(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstBt, &dst, &src); }
+ //! @brief Bit test.
+ void bt(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstBt, &dst, &src); }
+
+ //! @brief Bit test and complement.
+ void btc(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstBtc, &dst, &src); }
+ //! @brief Bit test and complement.
+ void btc(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstBtc, &dst, &src); }
+ //! @brief Bit test and complement.
+ void btc(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstBtc, &dst, &src); }
+ //! @brief Bit test and complement.
+ void btc(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstBtc, &dst, &src); }
+
+ //! @brief Bit test and reset.
+ void btr(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstBtr, &dst, &src); }
+ //! @brief Bit test and reset.
+ void btr(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstBtr, &dst, &src); }
+ //! @brief Bit test and reset.
+ void btr(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstBtr, &dst, &src); }
+ //! @brief Bit test and reset.
+ void btr(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstBtr, &dst, &src); }
+
+ //! @brief Bit test and set.
+ void bts(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstBts, &dst, &src); }
+ //! @brief Bit test and set.
+ void bts(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstBts, &dst, &src); }
+ //! @brief Bit test and set.
+ void bts(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstBts, &dst, &src); }
+ //! @brief Bit test and set.
+ void bts(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstBts, &dst, &src); }
+
+ //! @brief Call Procedure.
+ void call(const GpReg& dst)
+ {
+ ASMJIT_ASSERT(dst.isRegType(kX86RegTypeGpz));
+ _emitInstruction(kX86InstCall, &dst);
+ }
+ //! @brief Call Procedure.
+ void call(const Mem& dst)
+ { _emitInstruction(kX86InstCall, &dst); }
+ //! @brief Call Procedure.
+ void call(const Imm& dst)
+ { _emitInstruction(kX86InstCall, &dst); }
+ //! @brief Call Procedure.
+ //! @overload
+ void call(void* dst)
+ {
+ Imm imm((sysint_t)dst);
+ _emitInstruction(kX86InstCall, &imm);
+ }
+
+ //! @brief Call Procedure.
+ void call(const Label& label)
+ { _emitInstruction(kX86InstCall, &label); }
+
+ //! @brief Convert Byte to Word (Sign Extend).
+ //!
+ //! AX <- Sign Extend AL
+ void cbw()
+ { _emitInstruction(kX86InstCbw); }
+
+ //! @brief Convert Word to DWord (Sign Extend).
+ //!
+ //! DX:AX <- Sign Extend AX
+ void cwd()
+ { _emitInstruction(kX86InstCwd); }
+
+ //! @brief Convert Word to DWord (Sign Extend).
+ //!
+ //! EAX <- Sign Extend AX
+ void cwde()
+ { _emitInstruction(kX86InstCwde); }
+
+ //! @brief Convert DWord to QWord (Sign Extend).
+ //!
+ //! EDX:EAX <- Sign Extend EAX
+ void cdq()
+ { _emitInstruction(kX86InstCdq); }
+
+#if defined(ASMJIT_X64)
+ //! @brief Convert DWord to QWord (Sign Extend).
+ //!
+ //! RAX <- Sign Extend EAX
+ void cdqe()
+ { _emitInstruction(kX86InstCdqe); }
+#endif // ASMJIT_X64
+
+ //! @brief Clear Carry flag
+ //!
+ //! This instruction clears the CF flag in the EFLAGS register.
+ void clc()
+ { _emitInstruction(kX86InstClc); }
+
+ //! @brief Clear Direction flag
+ //!
+ //! This instruction clears the DF flag in the EFLAGS register.
+ void cld()
+ { _emitInstruction(kX86InstCld); }
+
+ //! @brief Complement Carry Flag.
+ //!
+ //! This instruction complements the CF flag in the EFLAGS register.
+ //! (CF = NOT CF)
+ void cmc()
+ { _emitInstruction(kX86InstCmc); }
+
+ //! @brief Conditional Move.
+ void cmov(kX86Cond cc, const GpReg& dst, const GpReg& src)
+ { _emitInstruction(X86Util::getCMovccInstFromCond(cc), &dst, &src); }
+
+ //! @brief Conditional Move.
+ void cmov(kX86Cond cc, const GpReg& dst, const Mem& src)
+ { _emitInstruction(X86Util::getCMovccInstFromCond(cc), &dst, &src); }
+
+ //! @brief Conditional Move.
+ void cmova (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovA , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmova (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovA , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovae (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovAE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovae (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovAE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovb (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovB , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovb (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovB , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovbe (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovBE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovbe (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovBE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovc (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovC , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovc (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovC , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmove (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmove (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovg (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovG , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovg (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovG , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovge (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovGE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovge (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovGE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovl (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovL , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovl (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovL , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovle (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovLE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovle (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovLE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovna (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovNA , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovna (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovNA , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnae(const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovNAE, &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnae(const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovNAE, &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnb (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovNB , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnb (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovNB , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnbe(const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovNBE, &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnbe(const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovNBE, &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnc (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovNC , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnc (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovNC , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovne (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovNE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovne (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovNE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovng (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovNG , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovng (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovNG , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnge(const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovNGE, &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnge(const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovNGE, &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnl (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovNL , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnl (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovNL , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnle(const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovNLE, &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnle(const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovNLE, &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovno (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovNO , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovno (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovNO , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnp (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovNP , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnp (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovNP , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovns (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovNS , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovns (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovNS , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnz (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovNZ , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnz (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovNZ , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovo (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovO , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovo (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovO , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovp (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovP , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovp (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovP , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovpe (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovPE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovpe (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovPE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovpo (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovPO , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovpo (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovPO , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovs (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovS , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovs (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovS , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovz (const GpReg& dst, const GpReg& src) { _emitInstruction(kX86InstCMovZ , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovz (const GpReg& dst, const Mem& src) { _emitInstruction(kX86InstCMovZ , &dst, &src); }
+
+ //! @brief Compare Two Operands.
+ void cmp(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstCmp, &dst, &src); }
+ //! @brief Compare Two Operands.
+ void cmp(const GpReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCmp, &dst, &src); }
+ //! @brief Compare Two Operands.
+ void cmp(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstCmp, &dst, &src); }
+ //! @brief Compare Two Operands.
+ void cmp(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstCmp, &dst, &src); }
+ //! @brief Compare Two Operands.
+ void cmp(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstCmp, &dst, &src); }
+
+ //! @brief Compare and Exchange (i486).
+ void cmpxchg(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstCmpXCHG, &dst, &src); }
+ //! @brief Compare and Exchange (i486).
+ void cmpxchg(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstCmpXCHG, &dst, &src); }
+
+ //! @brief Compares the 64-bit value in EDX:EAX with the memory operand (Pentium).
+ //!
+ //! If the values are equal, then this instruction stores the 64-bit value
+ //! in ECX:EBX into the memory operand and sets the zero flag. Otherwise,
+ //! this instruction copies the 64-bit memory operand into the EDX:EAX
+ //! registers and clears the zero flag.
+ void cmpxchg8b(const Mem& dst)
+ { _emitInstruction(kX86InstCmpXCHG8B, &dst); }
+
+#if defined(ASMJIT_X64)
+ //! @brief Compares the 128-bit value in RDX:RAX with the memory operand (X64).
+ //!
+ //! If the values are equal, then this instruction stores the 128-bit value
+ //! in RCX:RBX into the memory operand and sets the zero flag. Otherwise,
+ //! this instruction copies the 128-bit memory operand into the RDX:RAX
+ //! registers and clears the zero flag.
+ void cmpxchg16b(const Mem& dst)
+ { _emitInstruction(kX86InstCmpXCHG16B, &dst); }
+#endif // ASMJIT_X64
+
+ //! @brief CPU Identification (i486).
+ void cpuid()
+ { _emitInstruction(kX86InstCpuId); }
+
+#if defined(ASMJIT_X64)
+ //! @brief Convert QWord to DQWord (Sign Extend).
+ //!
+ //! RDX:RAX <- Sign Extend RAX
+ void cqo()
+ { _emitInstruction(kX86InstCqo); }
+#endif // ASMJIT_X64
+
+#if defined(ASMJIT_X86)
+ //! @brief Decimal adjust AL after addition
+ //!
+ //! This instruction adjusts the sum of two packed BCD values to create
+ //! a packed BCD result.
+ //!
+ //! @note This instruction is only available in 32-bit mode.
+ void daa()
+ { _emitInstruction(kX86InstDaa); }
+#endif // ASMJIT_X86
+
+#if defined(ASMJIT_X86)
+ //! @brief Decimal adjust AL after subtraction
+ //!
+ //! This instruction adjusts the result of the subtraction of two packed
+ //! BCD values to create a packed BCD result.
+ //!
+ //! @note This instruction is only available in 32-bit mode.
+ void das()
+ { _emitInstruction(kX86InstDas); }
+#endif // ASMJIT_X86
+
+ //! @brief Decrement by 1.
+ //! @note This instruction can be slower than sub(dst, 1)
+ void dec(const GpReg& dst)
+ { _emitInstruction(kX86InstDec, &dst); }
+ //! @brief Decrement by 1.
+ //! @note This instruction can be slower than sub(dst, 1)
+ void dec(const Mem& dst)
+ { _emitInstruction(kX86InstDec, &dst); }
+
+ //! @brief Unsigned divide.
+ //!
+ //! This instruction divides (unsigned) the value in the AL, AX, or EAX
+ //! register by the source operand and stores the result in the AX,
+ //! DX:AX, or EDX:EAX registers.
+ void div(const GpReg& src)
+ { _emitInstruction(kX86InstDiv, &src); }
+ //! @brief Unsigned divide.
+ //! @overload
+ void div(const Mem& src)
+ { _emitInstruction(kX86InstDiv, &src); }
+
+ //! @brief Make Stack Frame for Procedure Parameters.
+ void enter(const Imm& imm16, const Imm& imm8)
+ { _emitInstruction(kX86InstEnter, &imm16, &imm8); }
+
+ //! @brief Signed divide.
+ //!
+ //! This instruction divides (signed) the value in the AL, AX, or EAX
+ //! register by the source operand and stores the result in the AX,
+ //! DX:AX, or EDX:EAX registers.
+ void idiv(const GpReg& src)
+ { _emitInstruction(kX86InstIDiv, &src); }
+ //! @brief Signed divide.
+ //! @overload
+ void idiv(const Mem& src)
+ { _emitInstruction(kX86InstIDiv, &src); }
+
+ //! @brief Signed multiply.
+ //!
+ //! Source operand (in a general-purpose register or memory location)
+ //! is multiplied by the value in the AL, AX, or EAX register (depending
+ //! on the operand size) and the product is stored in the AX, DX:AX, or
+ //! EDX:EAX registers, respectively.
+ void imul(const GpReg& src)
+ { _emitInstruction(kX86InstIMul, &src); }
+ //! @overload
+ void imul(const Mem& src)
+ { _emitInstruction(kX86InstIMul, &src); }
+
+ //! @brief Signed multiply.
+ //!
+ //! Destination operand (the first operand) is multiplied by the source
+ //! operand (second operand). The destination operand is a general-purpose
+ //! register and the source operand is an immediate value, a general-purpose
+ //! register, or a memory location. The product is then stored in the
+ //! destination operand location.
+ void imul(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstIMul, &dst, &src); }
+ //! @brief Signed multiply.
+ //! @overload
+ void imul(const GpReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstIMul, &dst, &src); }
+ //! @brief Signed multiply.
+ //! @overload
+ void imul(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstIMul, &dst, &src); }
+
+ //! @brief Signed multiply.
+ //!
+ //! source operand (which can be a general-purpose register or a memory
+ //! location) is multiplied by the second source operand (an immediate
+ //! value). The product is then stored in the destination operand
+ //! (a general-purpose register).
+ void imul(const GpReg& dst, const GpReg& src, const Imm& imm)
+ { _emitInstruction(kX86InstIMul, &dst, &src, &imm); }
+ //! @overload
+ void imul(const GpReg& dst, const Mem& src, const Imm& imm)
+ { _emitInstruction(kX86InstIMul, &dst, &src, &imm); }
+
+ //! @brief Increment by 1.
+ //! @note This instruction can be slower than add(dst, 1)
+ void inc(const GpReg& dst)
+ { _emitInstruction(kX86InstInc, &dst); }
+ //! @brief Increment by 1.
+ //! @note This instruction can be slower than add(dst, 1)
+ void inc(const Mem& dst)
+ { _emitInstruction(kX86InstInc, &dst); }
+
+ //! @brief Interrupt 3 - trap to debugger.
+ void int3()
+ { _emitInstruction(kX86InstInt3); }
+
+ //! @brief Jump to label @a label if condition @a cc is met.
+ //!
+ //! This instruction checks the state of one or more of the status flags in
+ //! the EFLAGS register (CF, OF, PF, SF, and ZF) and, if the flags are in the
+ //! specified state (condition), performs a jump to the target instruction
+ //! specified by the destination operand. A condition code (cc) is associated
+ //! with each instruction to indicate the condition being tested for. If the
+ //! condition is not satisfied, the jump is not performed and execution
+ //! continues with the instruction following the Jcc instruction.
+ void j(kX86Cond cc, const Label& label, uint32_t hint = kCondHintNone)
+ {
+ _emitJcc(X86Util::getJccInstFromCond(cc), &label, hint);
+ }
+
+ //! @brief Jump to label @a label if condition is met.
+ void ja (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJA , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jae (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJAE , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jb (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJB , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jbe (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJBE , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jc (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJC , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void je (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJE , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jg (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJG , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jge (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJGE , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jl (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJL , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jle (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJLE , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jna (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNA , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jnae(const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNAE, &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jnb (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNB , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jnbe(const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNBE, &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jnc (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNC , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jne (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNE , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jng (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNG , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jnge(const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNGE, &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jnl (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNL , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jnle(const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNLE, &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jno (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNO , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jnp (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNP , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jns (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNS , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jnz (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNZ , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jo (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJO , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jp (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJP , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jpe (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJPE , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jpo (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJPO , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void js (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJS , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jz (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJZ , &label, hint); }
+
+ //! @brief Short jump to label @a label if condition @a cc is met.
+ //! @sa j()
+ void short_j(kX86Cond cc, const Label& label, uint32_t hint = kCondHintNone)
+ {
+ _emitOptions |= kX86EmitOptionShortJump;
+ j(cc, label, hint);
+ }
+
+ //! @brief Short jump to label @a label if condition is met.
+ void short_ja (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJA , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jae (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJAE , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jb (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJB , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jbe (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJBE , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jc (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJC , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_je (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJE , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jg (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJG , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jge (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJGE , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jl (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJL , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jle (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJLE , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jna (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJNA , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jnae(const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJNAE, &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jnb (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJNB , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jnbe(const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJNBE, &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jnc (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJNC , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jne (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJNE , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jng (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJNG , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jnge(const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJNGE, &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jnl (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJNL , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jnle(const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJNLE, &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jno (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJNO , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jnp (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJNP , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jns (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJNS , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jnz (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJNZ , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jo (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJO , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jp (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJP , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jpe (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJPE , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jpo (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJPO , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_js (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJS , &label, hint); }
+ //! @brief Short jump to label @a label if condition is met.
+ void short_jz (const Label& label, uint32_t hint = kCondHintNone) { _emitShortJcc(kX86InstJZ , &label, hint); }
+
+ //! @brief Jump.
+ //! @overload
+ void jmp(const GpReg& dst)
+ { _emitInstruction(kX86InstJmp, &dst); }
+ //! @brief Jump.
+ //! @overload
+ void jmp(const Mem& dst)
+ { _emitInstruction(kX86InstJmp, &dst); }
+ //! @brief Jump.
+ //! @overload
+ void jmp(const Imm& dst)
+ { _emitInstruction(kX86InstJmp, &dst); }
+
+ //! @brief Jump.
+ //! @overload
+ void jmp(void* dst)
+ {
+ Imm imm((sysint_t)dst);
+ _emitInstruction(kX86InstJmp, &imm);
+ }
+
+ //! @brief Jump.
+ //!
+ //! This instruction transfers program control to a different point
+ //! in the instruction stream without recording return information.
+ //! The destination (target) operand specifies the label of the
+ //! instruction being jumped to.
+ void jmp(const Label& label)
+ { _emitInstruction(kX86InstJmp, &label); }
+
+ //! @brief Short jump.
+ //! @sa jmp()
+ void short_jmp(const Label& label)
+ {
+ _emitOptions |= kX86EmitOptionShortJump;
+ _emitInstruction(kX86InstJmp, &label);
+ }
+
+ //! @brief Load Effective Address
+ //!
+ //! This instruction computes the effective address of the second
+ //! operand (the source operand) and stores it in the first operand
+ //! (destination operand). The source operand is a memory address
+ //! (offset part) specified with one of the processors addressing modes.
+ //! The destination operand is a general-purpose register.
+ void lea(const GpReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstLea, &dst, &src); }
+
+ //! @brief High Level Procedure Exit.
+ void leave()
+ { _emitInstruction(kX86InstLeave); }
+
+ //! @brief Move.
+ //!
+ //! This instruction copies the second operand (source operand) to the first
+ //! operand (destination operand). The source operand can be an immediate
+ //! value, general-purpose register, segment register, or memory location.
+ //! The destination register can be a general-purpose register, segment
+ //! register, or memory location. Both operands must be the same size, which
+ //! can be a byte, a word, or a DWORD.
+ //!
+ //! @note To move MMX or SSE registers to/from GP registers or memory, use
+ //! corresponding functions: @c movd(), @c movq(), etc. Passing MMX or SSE
+ //! registers to @c mov() is illegal.
+ void mov(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstMov, &dst, &src); }
+ //! @brief Move.
+ //! @overload
+ void mov(const GpReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMov, &dst, &src); }
+ //! @brief Move.
+ //! @overload
+ void mov(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstMov, &dst, &src); }
+ //! @brief Move.
+ //! @overload
+ void mov(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstMov, &dst, &src); }
+ //! @brief Move.
+ //! @overload
+ void mov(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstMov, &dst, &src); }
+
+ //! @brief Move from segment register.
+ //! @overload.
+ void mov(const GpReg& dst, const SegmentReg& src)
+ { _emitInstruction(kX86InstMov, &dst, &src); }
+
+ //! @brief Move from segment register.
+ //! @overload.
+ void mov(const Mem& dst, const SegmentReg& src)
+ { _emitInstruction(kX86InstMov, &dst, &src); }
+
+ //! @brief Move to segment register.
+ //! @overload.
+ void mov(const SegmentReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstMov, &dst, &src); }
+
+ //! @brief Move to segment register.
+ //! @overload.
+ void mov(const SegmentReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMov, &dst, &src); }
+
+ //! @brief Move byte, word, dword or qword from absolute address @a src to
+ //! AL, AX, EAX or RAX register.
+ void mov_ptr(const GpReg& dst, void* src)
+ {
+ ASMJIT_ASSERT(!dst.getRegIndex());
+ Imm imm((sysint_t)src);
+ _emitInstruction(kX86InstMovPtr, &dst, &imm);
+ }
+
+ //! @brief Move byte, word, dword or qword from AL, AX, EAX or RAX register
+ //! to absolute address @a dst.
+ void mov_ptr(void* dst, const GpReg& src)
+ {
+ ASMJIT_ASSERT(!src.getRegIndex());
+ Imm imm((sysint_t)dst);
+ _emitInstruction(kX86InstMovPtr, &imm, &src);
+ }
+
+ //! @brief Move with Sign-Extension.
+ //!
+ //! This instruction copies the contents of the source operand (register
+ //! or memory location) to the destination operand (register) and sign
+ //! extends the value to 16, 32 or 64-bits.
+ //!
+ //! @sa movsxd().
+ void movsx(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstMovSX, &dst, &src); }
+ //! @brief Move with Sign-Extension.
+ //! @overload
+ void movsx(const GpReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovSX, &dst, &src); }
+
+#if defined(ASMJIT_X64)
+ //! @brief Move DWord to QWord with sign-extension.
+ void movsxd(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstMovSXD, &dst, &src); }
+ //! @brief Move DWord to QWord with sign-extension.
+ //! @overload
+ void movsxd(const GpReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovSXD, &dst, &src); }
+#endif // ASMJIT_X64
+
+ //! @brief Move with Zero-Extend.
+ //!
+ //! This instruction copies the contents of the source operand (register
+ //! or memory location) to the destination operand (register) and zero
+ //! extends the value to 16 or 32-bits. The size of the converted value
+ //! depends on the operand-size attribute.
+ void movzx(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstMovZX, &dst, &src); }
+ //! @brief Move with Zero-Extend.
+ //! @brief Overload
+ void movzx(const GpReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovZX, &dst, &src); }
+
+ //! @brief Unsigned multiply.
+ //!
+ //! Source operand (in a general-purpose register or memory location)
+ //! is multiplied by the value in the AL, AX, or EAX register (depending
+ //! on the operand size) and the product is stored in the AX, DX:AX, or
+ //! EDX:EAX registers, respectively.
+ void mul(const GpReg& src)
+ { _emitInstruction(kX86InstMul, &src); }
+ //! @brief Unsigned multiply.
+ //! @overload
+ void mul(const Mem& src)
+ { _emitInstruction(kX86InstMul, &src); }
+
+ //! @brief Two's Complement Negation.
+ void neg(const GpReg& dst)
+ { _emitInstruction(kX86InstNeg, &dst); }
+ //! @brief Two's Complement Negation.
+ void neg(const Mem& dst)
+ { _emitInstruction(kX86InstNeg, &dst); }
+
+ //! @brief No Operation.
+ //!
+ //! This instruction performs no operation. This instruction is a one-byte
+ //! instruction that takes up space in the instruction stream but does not
+ //! affect the machine context, except the EIP register. The NOP instruction
+ //! is an alias mnemonic for the XCHG (E)AX, (E)AX instruction.
+ void nop()
+ { _emitInstruction(kX86InstNop); }
+
+ //! @brief One's Complement Negation.
+ void not_(const GpReg& dst)
+ { _emitInstruction(kX86InstNot, &dst); }
+ //! @brief One's Complement Negation.
+ void not_(const Mem& dst)
+ { _emitInstruction(kX86InstNot, &dst); }
+
+ //! @brief Logical Inclusive OR.
+ void or_(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstOr, &dst, &src); }
+ //! @brief Logical Inclusive OR.
+ void or_(const GpReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstOr, &dst, &src); }
+ //! @brief Logical Inclusive OR.
+ void or_(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstOr, &dst, &src); }
+ //! @brief Logical Inclusive OR.
+ void or_(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstOr, &dst, &src); }
+ //! @brief Logical Inclusive OR.
+ void or_(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstOr, &dst, &src); }
+
+ //! @brief Pop a Value from the Stack.
+ //!
+ //! This instruction loads the value from the top of the stack to the location
+ //! specified with the destination operand and then increments the stack pointer.
+ //! The destination operand can be a general purpose register, memory location,
+ //! or segment register.
+ void pop(const GpReg& dst)
+ {
+ ASMJIT_ASSERT(dst.isRegType(kX86RegTypeGpw) || dst.isRegType(kX86RegTypeGpz));
+ _emitInstruction(kX86InstPop, &dst);
+ }
+ //! @brief Pop a Segment Register from the Stack.
+ //!
+ //! @note There is no instruction to pop a cs segment register.
+ void pop(const SegmentReg& dst)
+ {
+ ASMJIT_ASSERT(dst.getRegIndex() != kX86SegCs);
+ _emitInstruction(kX86InstPop, &dst);
+ }
+
+ void pop(const Mem& dst)
+ {
+ ASMJIT_ASSERT(dst.getSize() == 2 || dst.getSize() == sizeof(sysint_t));
+ _emitInstruction(kX86InstPop, &dst);
+ }
+
+#if defined(ASMJIT_X86)
+ //! @brief Pop All General-Purpose Registers.
+ //!
+ //! Pop EDI, ESI, EBP, EBX, EDX, ECX, and EAX.
+ void popad()
+ { _emitInstruction(kX86InstPopAD); }
+#endif // ASMJIT_X86
+
+ //! @brief Pop Stack into EFLAGS Register (32-bit or 64-bit).
+ void popf()
+ {
+#if defined(ASMJIT_X86)
+ popfd();
+#else
+ popfq();
+#endif
+ }
+
+#if defined(ASMJIT_X86)
+ //! @brief Pop Stack into EFLAGS Register (32-bit).
+ void popfd() { _emitInstruction(kX86InstPopFD); }
+#else
+ //! @brief Pop Stack into EFLAGS Register (64-bit).
+ void popfq() { _emitInstruction(kX86InstPopFQ); }
+#endif
+
+ //! @brief Push WORD/DWORD/QWORD Onto the Stack.
+ //!
+ //! @note 32-bit architecture pushed DWORD while 64-bit
+ //! pushes QWORD. 64-bit mode not provides instruction to
+ //! push 32-bit register/memory.
+ void push(const GpReg& src)
+ {
+ ASMJIT_ASSERT(src.isRegType(kX86RegTypeGpw) || src.isRegType(kX86RegTypeGpz));
+ _emitInstruction(kX86InstPush, &src);
+ }
+ //! @brief Push Segment Register Onto the Stack.
+ void push(const SegmentReg& src)
+ { _emitInstruction(kX86InstPush, &src); }
+ //! @brief Push WORD/DWORD/QWORD Onto the Stack.
+ void push(const Mem& src)
+ {
+ ASMJIT_ASSERT(src.getSize() == 2 || src.getSize() == sizeof(sysint_t));
+ _emitInstruction(kX86InstPush, &src);
+ }
+ //! @brief Push WORD/DWORD/QWORD Onto the Stack.
+ void push(const Imm& src)
+ { _emitInstruction(kX86InstPush, &src); }
+
+#if defined(ASMJIT_X86)
+ //! @brief Push All General-Purpose Registers.
+ //!
+ //! Push EAX, ECX, EDX, EBX, original ESP, EBP, ESI, and EDI.
+ void pushad()
+ { _emitInstruction(kX86InstPushAD); }
+#endif // ASMJIT_X86
+
+ //! @brief Push EFLAGS Register (32-bit or 64-bit) onto the Stack.
+ void pushf()
+ {
+#if defined(ASMJIT_X86)
+ pushfd();
+#else
+ pushfq();
+#endif
+ }
+
+#if defined(ASMJIT_X86)
+ //! @brief Push EFLAGS Register (32-bit) onto the Stack.
+ void pushfd() { _emitInstruction(kX86InstPushFD); }
+#else
+ //! @brief Push EFLAGS Register (64-bit) onto the Stack.
+ void pushfq() { _emitInstruction(kX86InstPushFQ); }
+#endif // ASMJIT_X86
+
+ //! @brief Rotate Bits Left.
+ //! @note @a src register can be only @c cl.
+ void rcl(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstRcl, &dst, &src); }
+ //! @brief Rotate Bits Left.
+ void rcl(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstRcl, &dst, &src); }
+ //! @brief Rotate Bits Left.
+ //! @note @a src register can be only @c cl.
+ void rcl(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstRcl, &dst, &src); }
+ //! @brief Rotate Bits Left.
+ void rcl(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstRcl, &dst, &src); }
+
+ //! @brief Rotate Bits Right.
+ //! @note @a src register can be only @c cl.
+ void rcr(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstRcr, &dst, &src); }
+ //! @brief Rotate Bits Right.
+ void rcr(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstRcr, &dst, &src); }
+ //! @brief Rotate Bits Right.
+ //! @note @a src register can be only @c cl.
+ void rcr(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstRcr, &dst, &src); }
+ //! @brief Rotate Bits Right.
+ void rcr(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstRcr, &dst, &src); }
+
+ //! @brief Read Time-Stamp Counter (Pentium).
+ void rdtsc()
+ { _emitInstruction(kX86InstRdtsc); }
+
+ //! @brief Read Time-Stamp Counter and Processor ID (New).
+ void rdtscp()
+ { _emitInstruction(kX86InstRdtscP); }
+
+ //! @brief Load ECX/RCX BYTEs from DS:[ESI/RSI] to AL.
+ void rep_lodsb()
+ { _emitInstruction(kX86InstRepLodSB); }
+
+ //! @brief Load ECX/RCX DWORDs from DS:[ESI/RSI] to EAX.
+ void rep_lodsd()
+ { _emitInstruction(kX86InstRepLodSD); }
+
+#if defined(ASMJIT_X64)
+ //! @brief Load ECX/RCX QWORDs from DS:[ESI/RSI] to RAX.
+ void rep_lodsq()
+ { _emitInstruction(kX86InstRepLodSQ); }
+#endif // ASMJIT_X64
+
+ //! @brief Load ECX/RCX WORDs from DS:[ESI/RSI] to AX.
+ void rep_lodsw()
+ { _emitInstruction(kX86InstRepLodSW); }
+
+ //! @brief Move ECX/RCX BYTEs from DS:[ESI/RSI] to ES:[EDI/RDI].
+ void rep_movsb()
+ { _emitInstruction(kX86InstRepMovSB); }
+
+ //! @brief Move ECX/RCX DWORDs from DS:[ESI/RSI] to ES:[EDI/RDI].
+ void rep_movsd()
+ { _emitInstruction(kX86InstRepMovSD); }
+
+#if defined(ASMJIT_X64)
+ //! @brief Move ECX/RCX QWORDs from DS:[ESI/RSI] to ES:[EDI/RDI].
+ void rep_movsq()
+ { _emitInstruction(kX86InstRepMovSQ); }
+#endif // ASMJIT_X64
+
+ //! @brief Move ECX/RCX WORDs from DS:[ESI/RSI] to ES:[EDI/RDI].
+ void rep_movsw()
+ { _emitInstruction(kX86InstRepMovSW); }
+
+ //! @brief Fill ECX/RCX BYTEs at ES:[EDI/RDI] with AL.
+ void rep_stosb()
+ { _emitInstruction(kX86InstRepStoSB); }
+
+ //! @brief Fill ECX/RCX DWORDs at ES:[EDI/RDI] with EAX.
+ void rep_stosd()
+ { _emitInstruction(kX86InstRepStoSD); }
+
+#if defined(ASMJIT_X64)
+ //! @brief Fill ECX/RCX QWORDs at ES:[EDI/RDI] with RAX.
+ void rep_stosq()
+ { _emitInstruction(kX86InstRepStoSQ); }
+#endif // ASMJIT_X64
+
+ //! @brief Fill ECX/RCX WORDs at ES:[EDI/RDI] with AX.
+ void rep_stosw()
+ { _emitInstruction(kX86InstRepStoSW); }
+
+ //! @brief Repeated find nonmatching BYTEs in ES:[EDI/RDI] and DS:[ESI/RDI].
+ void repe_cmpsb()
+ { _emitInstruction(kX86InstRepECmpSB); }
+
+ //! @brief Repeated find nonmatching DWORDs in ES:[EDI/RDI] and DS:[ESI/RDI].
+ void repe_cmpsd()
+ { _emitInstruction(kX86InstRepECmpSD); }
+
+#if defined(ASMJIT_X64)
+ //! @brief Repeated find nonmatching QWORDs in ES:[EDI/RDI] and DS:[ESI/RDI].
+ void repe_cmpsq()
+ { _emitInstruction(kX86InstRepECmpSQ); }
+#endif // ASMJIT_X64
+
+ //! @brief Repeated find nonmatching WORDs in ES:[EDI/RDI] and DS:[ESI/RDI].
+ void repe_cmpsw()
+ { _emitInstruction(kX86InstRepECmpSW); }
+
+ //! @brief Find non-AL BYTE starting at ES:[EDI/RDI].
+ void repe_scasb()
+ { _emitInstruction(kX86InstRepEScaSB); }
+
+ //! @brief Find non-EAX DWORD starting at ES:[EDI/RDI].
+ void repe_scasd()
+ { _emitInstruction(kX86InstRepEScaSD); }
+
+#if defined(ASMJIT_X64)
+ //! @brief Find non-RAX QWORD starting at ES:[EDI/RDI].
+ void repe_scasq()
+ { _emitInstruction(kX86InstRepEScaSQ); }
+#endif // ASMJIT_X64
+
+ //! @brief Find non-AX WORD starting at ES:[EDI/RDI].
+ void repe_scasw()
+ { _emitInstruction(kX86InstRepEScaSW); }
+
+ //! @brief Repeated find nonmatching BYTEs in ES:[EDI/RDI] and DS:[ESI/RDI].
+ void repne_cmpsb()
+ { _emitInstruction(kX86InstRepNECmpSB); }
+
+ //! @brief Repeated find nonmatching DWORDs in ES:[EDI/RDI] and DS:[ESI/RDI].
+ void repne_cmpsd()
+ { _emitInstruction(kX86InstRepNECmpSD); }
+
+#if defined(ASMJIT_X64)
+ //! @brief Repeated find nonmatching QWORDs in ES:[EDI/RDI] and DS:[ESI/RDI].
+ void repne_cmpsq()
+ { _emitInstruction(kX86InstRepNECmpSQ); }
+#endif // ASMJIT_X64
+
+ //! @brief Repeated find nonmatching WORDs in ES:[EDI/RDI] and DS:[ESI/RDI].
+ void repne_cmpsw()
+ { _emitInstruction(kX86InstRepNECmpSW); }
+
+ //! @brief Find AL, starting at ES:[EDI/RDI].
+ void repne_scasb()
+ { _emitInstruction(kX86InstRepNEScaSB); }
+
+ //! @brief Find EAX, starting at ES:[EDI/RDI].
+ void repne_scasd()
+ { _emitInstruction(kX86InstRepNEScaSD); }
+
+#if defined(ASMJIT_X64)
+ //! @brief Find RAX, starting at ES:[EDI/RDI].
+ void repne_scasq()
+ { _emitInstruction(kX86InstRepNEScaSQ); }
+#endif // ASMJIT_X64
+
+ //! @brief Find AX, starting at ES:[EDI/RDI].
+ void repne_scasw()
+ { _emitInstruction(kX86InstRepNEScaSW); }
+
+ //! @brief Return from Procedure.
+ void ret()
+ { _emitInstruction(kX86InstRet); }
+
+ //! @brief Return from Procedure.
+ void ret(const Imm& imm16)
+ { _emitInstruction(kX86InstRet, &imm16); }
+
+ //! @brief Rotate Bits Left.
+ //! @note @a src register can be only @c cl.
+ void rol(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstRol, &dst, &src); }
+ //! @brief Rotate Bits Left.
+ void rol(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstRol, &dst, &src); }
+ //! @brief Rotate Bits Left.
+ //! @note @a src register can be only @c cl.
+ void rol(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstRol, &dst, &src); }
+ //! @brief Rotate Bits Left.
+ void rol(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstRol, &dst, &src); }
+
+ //! @brief Rotate Bits Right.
+ //! @note @a src register can be only @c cl.
+ void ror(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstRor, &dst, &src); }
+ //! @brief Rotate Bits Right.
+ void ror(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstRor, &dst, &src); }
+ //! @brief Rotate Bits Right.
+ //! @note @a src register can be only @c cl.
+ void ror(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstRor, &dst, &src); }
+ //! @brief Rotate Bits Right.
+ void ror(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstRor, &dst, &src); }
+
+#if defined(ASMJIT_X86)
+ //! @brief Store AH into Flags.
+ void sahf()
+ { _emitInstruction(kX86InstSahf); }
+#endif // ASMJIT_X86
+
+ //! @brief Integer subtraction with borrow.
+ void sbb(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstSbb, &dst, &src); }
+ //! @brief Integer subtraction with borrow.
+ void sbb(const GpReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstSbb, &dst, &src); }
+ //! @brief Integer subtraction with borrow.
+ void sbb(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstSbb, &dst, &src); }
+ //! @brief Integer subtraction with borrow.
+ void sbb(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstSbb, &dst, &src); }
+ //! @brief Integer subtraction with borrow.
+ void sbb(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstSbb, &dst, &src); }
+
+ //! @brief Shift Bits Left.
+ //! @note @a src register can be only @c cl.
+ void sal(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstSal, &dst, &src); }
+ //! @brief Shift Bits Left.
+ void sal(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstSal, &dst, &src); }
+ //! @brief Shift Bits Left.
+ //! @note @a src register can be only @c cl.
+ void sal(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstSal, &dst, &src); }
+ //! @brief Shift Bits Left.
+ void sal(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstSal, &dst, &src); }
+
+ //! @brief Shift Bits Right.
+ //! @note @a src register can be only @c cl.
+ void sar(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstSar, &dst, &src); }
+ //! @brief Shift Bits Right.
+ void sar(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstSar, &dst, &src); }
+ //! @brief Shift Bits Right.
+ //! @note @a src register can be only @c cl.
+ void sar(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstSar, &dst, &src); }
+ //! @brief Shift Bits Right.
+ void sar(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstSar, &dst, &src); }
+
+ //! @brief Set Byte on Condition.
+ void set(kX86Cond cc, const GpReg& dst)
+ {
+ ASMJIT_ASSERT(dst.getSize() == 1);
+ _emitInstruction(X86Util::getSetccInstFromCond(cc), &dst);
+ }
+
+ //! @brief Set Byte on Condition.
+ void set(kX86Cond cc, const Mem& dst)
+ {
+ ASMJIT_ASSERT(dst.getSize() <= 1);
+ _emitInstruction(X86Util::getSetccInstFromCond(cc), &dst);
+ }
+
+ //! @brief Set Byte on Condition.
+ void seta (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetA , &dst); }
+ //! @brief Set Byte on Condition.
+ void seta (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetA , &dst); }
+ //! @brief Set Byte on Condition.
+ void setae (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetAE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setae (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetAE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setb (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetB , &dst); }
+ //! @brief Set Byte on Condition.
+ void setb (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetB , &dst); }
+ //! @brief Set Byte on Condition.
+ void setbe (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetBE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setbe (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetBE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setc (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetC , &dst); }
+ //! @brief Set Byte on Condition.
+ void setc (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetC , &dst); }
+ //! @brief Set Byte on Condition.
+ void sete (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetE , &dst); }
+ //! @brief Set Byte on Condition.
+ void sete (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setg (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetG , &dst); }
+ //! @brief Set Byte on Condition.
+ void setg (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetG , &dst); }
+ //! @brief Set Byte on Condition.
+ void setge (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetGE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setge (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetGE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setl (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetL , &dst); }
+ //! @brief Set Byte on Condition.
+ void setl (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetL , &dst); }
+ //! @brief Set Byte on Condition.
+ void setle (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetLE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setle (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetLE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setna (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNA , &dst); }
+ //! @brief Set Byte on Condition.
+ void setna (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNA , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnae(const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNAE, &dst); }
+ //! @brief Set Byte on Condition.
+ void setnae(const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNAE, &dst); }
+ //! @brief Set Byte on Condition.
+ void setnb (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNB , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnb (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNB , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnbe(const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNBE, &dst); }
+ //! @brief Set Byte on Condition.
+ void setnbe(const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNBE, &dst); }
+ //! @brief Set Byte on Condition.
+ void setnc (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNC , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnc (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNC , &dst); }
+ //! @brief Set Byte on Condition.
+ void setne (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setne (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setng (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNG , &dst); }
+ //! @brief Set Byte on Condition.
+ void setng (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNG , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnge(const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNGE, &dst); }
+ //! @brief Set Byte on Condition.
+ void setnge(const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNGE, &dst); }
+ //! @brief Set Byte on Condition.
+ void setnl (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNL , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnl (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNL , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnle(const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNLE, &dst); }
+ //! @brief Set Byte on Condition.
+ void setnle(const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNLE, &dst); }
+ //! @brief Set Byte on Condition.
+ void setno (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNO , &dst); }
+ //! @brief Set Byte on Condition.
+ void setno (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNO , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnp (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNP , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnp (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNP , &dst); }
+ //! @brief Set Byte on Condition.
+ void setns (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNS , &dst); }
+ //! @brief Set Byte on Condition.
+ void setns (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNS , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnz (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNZ , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnz (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNZ , &dst); }
+ //! @brief Set Byte on Condition.
+ void seto (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetO , &dst); }
+ //! @brief Set Byte on Condition.
+ void seto (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetO , &dst); }
+ //! @brief Set Byte on Condition.
+ void setp (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetP , &dst); }
+ //! @brief Set Byte on Condition.
+ void setp (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetP , &dst); }
+ //! @brief Set Byte on Condition.
+ void setpe (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetPE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setpe (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetPE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setpo (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetPO , &dst); }
+ //! @brief Set Byte on Condition.
+ void setpo (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetPO , &dst); }
+ //! @brief Set Byte on Condition.
+ void sets (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetS , &dst); }
+ //! @brief Set Byte on Condition.
+ void sets (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetS , &dst); }
+ //! @brief Set Byte on Condition.
+ void setz (const GpReg& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetZ , &dst); }
+ //! @brief Set Byte on Condition.
+ void setz (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetZ , &dst); }
+
+ //! @brief Shift Bits Left.
+ //! @note @a src register can be only @c cl.
+ void shl(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstShl, &dst, &src); }
+ //! @brief Shift Bits Left.
+ void shl(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstShl, &dst, &src); }
+ //! @brief Shift Bits Left.
+ //! @note @a src register can be only @c cl.
+ void shl(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstShl, &dst, &src); }
+ //! @brief Shift Bits Left.
+ void shl(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstShl, &dst, &src); }
+
+ //! @brief Shift Bits Right.
+ //! @note @a src register can be only @c cl.
+ void shr(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstShr, &dst, &src); }
+ //! @brief Shift Bits Right.
+ void shr(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstShr, &dst, &src); }
+ //! @brief Shift Bits Right.
+ //! @note @a src register can be only @c cl.
+ void shr(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstShr, &dst, &src); }
+ //! @brief Shift Bits Right.
+ void shr(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstShr, &dst, &src); }
+
+ //! @brief Double Precision Shift Left.
+ //! @note src2 register can be only @c cl register.
+ void shld(const GpReg& dst, const GpReg& src1, const GpReg& src2)
+ { _emitInstruction(kX86InstShld, &dst, &src1, &src2); }
+ //! @brief Double Precision Shift Left.
+ void shld(const GpReg& dst, const GpReg& src1, const Imm& src2)
+ { _emitInstruction(kX86InstShld, &dst, &src1, &src2); }
+ //! @brief Double Precision Shift Left.
+ //! @note src2 register can be only @c cl register.
+ void shld(const Mem& dst, const GpReg& src1, const GpReg& src2)
+ { _emitInstruction(kX86InstShld, &dst, &src1, &src2); }
+ //! @brief Double Precision Shift Left.
+ void shld(const Mem& dst, const GpReg& src1, const Imm& src2)
+ { _emitInstruction(kX86InstShld, &dst, &src1, &src2); }
+
+ //! @brief Double Precision Shift Right.
+ //! @note src2 register can be only @c cl register.
+ void shrd(const GpReg& dst, const GpReg& src1, const GpReg& src2)
+ { _emitInstruction(kX86InstShrd, &dst, &src1, &src2); }
+ //! @brief Double Precision Shift Right.
+ void shrd(const GpReg& dst, const GpReg& src1, const Imm& src2)
+ { _emitInstruction(kX86InstShrd, &dst, &src1, &src2); }
+ //! @brief Double Precision Shift Right.
+ //! @note src2 register can be only @c cl register.
+ void shrd(const Mem& dst, const GpReg& src1, const GpReg& src2)
+ { _emitInstruction(kX86InstShrd, &dst, &src1, &src2); }
+ //! @brief Double Precision Shift Right.
+ void shrd(const Mem& dst, const GpReg& src1, const Imm& src2)
+ { _emitInstruction(kX86InstShrd, &dst, &src1, &src2); }
+
+ //! @brief Set Carry Flag to 1.
+ void stc()
+ { _emitInstruction(kX86InstStc); }
+
+ //! @brief Set Direction Flag to 1.
+ void std()
+ { _emitInstruction(kX86InstStd); }
+
+ //! @brief Subtract.
+ void sub(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstSub, &dst, &src); }
+ //! @brief Subtract.
+ void sub(const GpReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstSub, &dst, &src); }
+ //! @brief Subtract.
+ void sub(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstSub, &dst, &src); }
+ //! @brief Subtract.
+ void sub(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstSub, &dst, &src); }
+ //! @brief Subtract.
+ void sub(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstSub, &dst, &src); }
+
+ //! @brief Logical Compare.
+ void test(const GpReg& op1, const GpReg& op2)
+ { _emitInstruction(kX86InstTest, &op1, &op2); }
+ //! @brief Logical Compare.
+ void test(const GpReg& op1, const Imm& op2)
+ { _emitInstruction(kX86InstTest, &op1, &op2); }
+ //! @brief Logical Compare.
+ void test(const Mem& op1, const GpReg& op2)
+ { _emitInstruction(kX86InstTest, &op1, &op2); }
+ //! @brief Logical Compare.
+ void test(const Mem& op1, const Imm& op2)
+ { _emitInstruction(kX86InstTest, &op1, &op2); }
+
+ //! @brief Undefined instruction - Raise invalid opcode exception.
+ void ud2()
+ { _emitInstruction(kX86InstUd2); }
+
+ //! @brief Exchange and Add.
+ void xadd(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstXadd, &dst, &src); }
+ //! @brief Exchange and Add.
+ void xadd(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstXadd, &dst, &src); }
+
+ //! @brief Exchange Register/Memory with Register.
+ void xchg(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstXchg, &dst, &src); }
+ //! @brief Exchange Register/Memory with Register.
+ void xchg(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstXchg, &dst, &src); }
+ //! @brief Exchange Register/Memory with Register.
+ void xchg(const GpReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstXchg, &src, &dst); }
+
+ //! @brief Exchange Register/Memory with Register.
+ void xor_(const GpReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstXor, &dst, &src); }
+ //! @brief Exchange Register/Memory with Register.
+ void xor_(const GpReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstXor, &dst, &src); }
+ //! @brief Exchange Register/Memory with Register.
+ void xor_(const GpReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstXor, &dst, &src); }
+ //! @brief Exchange Register/Memory with Register.
+ void xor_(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstXor, &dst, &src); }
+ //! @brief Exchange Register/Memory with Register.
+ void xor_(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstXor, &dst, &src); }
+
+ // --------------------------------------------------------------------------
+ // [X87 Instructions (FPU)]
+ // --------------------------------------------------------------------------
+
+ //! @brief Compute 2^x - 1 (FPU).
+ void f2xm1()
+ { _emitInstruction(kX86InstF2XM1); }
+
+ //! @brief Absolute Value of st(0) (FPU).
+ void fabs()
+ { _emitInstruction(kX86InstFAbs); }
+
+ //! @brief Add @a src to @a dst and store result in @a dst (FPU).
+ //!
+ //! @note One of dst or src must be st(0).
+ void fadd(const X87Reg& dst, const X87Reg& src)
+ {
+ ASMJIT_ASSERT(!dst.getRegIndex() || !src.getRegIndex());
+ _emitInstruction(kX86InstFAdd, &dst, &src);
+ }
+
+ //! @brief Add @a src to st(0) and store result in st(0) (FPU).
+ //!
+ //! @note SP-FP or DP-FP determined by @a adr size.
+ void fadd(const Mem& src)
+ { _emitInstruction(kX86InstFAdd, &src); }
+
+ //! @brief Add st(0) to @a dst and POP register stack (FPU).
+ void faddp(const X87Reg& dst = st(1))
+ { _emitInstruction(kX86InstFAddP, &dst); }
+
+ //! @brief Load Binary Coded Decimal (FPU).
+ void fbld(const Mem& src)
+ { _emitInstruction(kX86InstFBLd, &src); }
+
+ //! @brief Store BCD Integer and Pop (FPU).
+ void fbstp(const Mem& dst)
+ { _emitInstruction(kX86InstFBStP, &dst); }
+
+ //! @brief Change st(0) Sign (FPU).
+ void fchs()
+ { _emitInstruction(kX86InstFCHS); }
+
+ //! @brief Clear Exceptions (FPU).
+ //!
+ //! Clear floating-point exception flags after checking for pending unmasked
+ //! floating-point exceptions.
+ //!
+ //! Clears the floating-point exception flags (PE, UE, OE, ZE, DE, and IE),
+ //! the exception summary status flag (ES), the stack fault flag (SF), and
+ //! the busy flag (B) in the FPU status word. The FCLEX instruction checks
+ //! for and handles any pending unmasked floating-point exceptions before
+ //! clearing the exception flags.
+ void fclex()
+ { _emitInstruction(kX86InstFClex); }
+
+ //! @brief FP Conditional Move (FPU).
+ void fcmovb(const X87Reg& src)
+ { _emitInstruction(kX86InstFCMovB, &src); }
+ //! @brief FP Conditional Move (FPU).
+ void fcmovbe(const X87Reg& src)
+ { _emitInstruction(kX86InstFCMovBE, &src); }
+ //! @brief FP Conditional Move (FPU).
+ void fcmove(const X87Reg& src)
+ { _emitInstruction(kX86InstFCMovE, &src); }
+ //! @brief FP Conditional Move (FPU).
+ void fcmovnb(const X87Reg& src)
+ { _emitInstruction(kX86InstFCMovNB, &src); }
+ //! @brief FP Conditional Move (FPU).
+ void fcmovnbe(const X87Reg& src)
+ { _emitInstruction(kX86InstFCMovNBE, &src); }
+ //! @brief FP Conditional Move (FPU).
+ void fcmovne(const X87Reg& src)
+ { _emitInstruction(kX86InstFCMovNE, &src); }
+ //! @brief FP Conditional Move (FPU).
+ void fcmovnu(const X87Reg& src)
+ { _emitInstruction(kX86InstFCMovNU, &src); }
+ //! @brief FP Conditional Move (FPU).
+ void fcmovu(const X87Reg& src)
+ { _emitInstruction(kX86InstFCMovU, &src); }
+
+ //! @brief Compare st(0) with @a reg (FPU).
+ void fcom(const X87Reg& reg = st(1))
+ { _emitInstruction(kX86InstFCom, ®); }
+ //! @brief Compare st(0) with 4-byte or 8-byte FP at @a src (FPU).
+ void fcom(const Mem& src)
+ { _emitInstruction(kX86InstFCom, &src); }
+
+ //! @brief Compare st(0) with @a reg and pop the stack (FPU).
+ void fcomp(const X87Reg& reg = st(1))
+ { _emitInstruction(kX86InstFComP, ®); }
+ //! @brief Compare st(0) with 4-byte or 8-byte FP at @a adr and pop the
+ //! stack (FPU).
+ void fcomp(const Mem& mem)
+ { _emitInstruction(kX86InstFComP, &mem); }
+
+ //! @brief Compare st(0) with st(1) and pop register stack twice (FPU).
+ void fcompp()
+ { _emitInstruction(kX86InstFComPP); }
+
+ //! @brief Compare st(0) and @a reg and Set EFLAGS (FPU).
+ void fcomi(const X87Reg& reg)
+ { _emitInstruction(kX86InstFComI, ®); }
+
+ //! @brief Compare st(0) and @a reg and Set EFLAGS and pop the stack (FPU).
+ void fcomip(const X87Reg& reg)
+ { _emitInstruction(kX86InstFComIP, ®); }
+
+ //! @brief Cosine (FPU).
+ //!
+ //! This instruction calculates the cosine of the source operand in
+ //! register st(0) and stores the result in st(0).
+ void fcos()
+ { _emitInstruction(kX86InstFCos); }
+
+ //! @brief Decrement Stack-Top Pointer (FPU).
+ //!
+ //! Subtracts one from the TOP field of the FPU status word (decrements
+ //! the top-ofstack pointer). If the TOP field contains a 0, it is set
+ //! to 7. The effect of this instruction is to rotate the stack by one
+ //! position. The contents of the FPU data registers and tag register
+ //! are not affected.
+ void fdecstp()
+ { _emitInstruction(kX86InstFDecStP); }
+
+ //! @brief Divide @a dst by @a src (FPU).
+ //!
+ //! @note One of @a dst or @a src register must be st(0).
+ void fdiv(const X87Reg& dst, const X87Reg& src)
+ {
+ ASMJIT_ASSERT(!dst.getRegIndex() || !src.getRegIndex());
+ _emitInstruction(kX86InstFDiv, &dst, &src);
+ }
+ //! @brief Divide st(0) by 32-bit or 64-bit FP value (FPU).
+ void fdiv(const Mem& src)
+ { _emitInstruction(kX86InstFDiv, &src); }
+
+ //! @brief Divide @a reg by st(0) (FPU).
+ void fdivp(const X87Reg& reg = st(1))
+ { _emitInstruction(kX86InstFDivP, ®); }
+
+ //! @brief Reverse Divide @a dst by @a src (FPU).
+ //!
+ //! @note One of @a dst or @a src register must be st(0).
+ void fdivr(const X87Reg& dst, const X87Reg& src)
+ {
+ ASMJIT_ASSERT(!dst.getRegIndex() || !src.getRegIndex());
+ _emitInstruction(kX86InstFDivR, &dst, &src);
+ }
+ //! @brief Reverse Divide st(0) by 32-bit or 64-bit FP value (FPU).
+ void fdivr(const Mem& src)
+ { _emitInstruction(kX86InstFDivR, &src); }
+
+ //! @brief Reverse Divide @a reg by st(0) (FPU).
+ void fdivrp(const X87Reg& reg = st(1))
+ { _emitInstruction(kX86InstFDivRP, ®); }
+
+ //! @brief Free Floating-Point Register (FPU).
+ //!
+ //! Sets the tag in the FPU tag register associated with register @a reg
+ //! to empty (11B). The contents of @a reg and the FPU stack-top pointer
+ //! (TOP) are not affected.
+ void ffree(const X87Reg& reg)
+ { _emitInstruction(kX86InstFFree, ®); }
+
+ //! @brief Add 16-bit or 32-bit integer to st(0) (FPU).
+ void fiadd(const Mem& src)
+ {
+ ASMJIT_ASSERT(src.getSize() == 2 || src.getSize() == 4);
+ _emitInstruction(kX86InstFIAdd, &src);
+ }
+
+ //! @brief Compare st(0) with 16-bit or 32-bit Integer (FPU).
+ void ficom(const Mem& src)
+ {
+ ASMJIT_ASSERT(src.getSize() == 2 || src.getSize() == 4);
+ _emitInstruction(kX86InstFICom, &src);
+ }
+
+ //! @brief Compare st(0) with 16-bit or 32-bit Integer and pop the stack (FPU).
+ void ficomp(const Mem& src)
+ {
+ ASMJIT_ASSERT(src.getSize() == 2 || src.getSize() == 4);
+ _emitInstruction(kX86InstFIComP, &src);
+ }
+
+ //! @brief Divide st(0) by 32-bit or 16-bit integer (@a src) (FPU).
+ void fidiv(const Mem& src)
+ {
+ ASMJIT_ASSERT(src.getSize() == 2 || src.getSize() == 4);
+ _emitInstruction(kX86InstFIDiv, &src);
+ }
+
+ //! @brief Reverse Divide st(0) by 32-bit or 16-bit integer (@a src) (FPU).
+ void fidivr(const Mem& src)
+ {
+ ASMJIT_ASSERT(src.getSize() == 2 || src.getSize() == 4);
+ _emitInstruction(kX86InstFIDivR, &src);
+ }
+
+ //! @brief Load 16-bit, 32-bit or 64-bit Integer and push it to the stack (FPU).
+ //!
+ //! Converts the signed-integer source operand into double extended-precision
+ //! floating point format and pushes the value onto the FPU register stack.
+ //! The source operand can be a word, doubleword, or quadword integer. It is
+ //! loaded without rounding errors. The sign of the source operand is
+ //! preserved.
+ void fild(const Mem& src)
+ {
+ ASMJIT_ASSERT(src.getSize() == 2 || src.getSize() == 4 || src.getSize() == 8);
+ _emitInstruction(kX86InstFILd, &src);
+ }
+
+ //! @brief Multiply st(0) by 16-bit or 32-bit integer and store it
+ //! to st(0) (FPU).
+ void fimul(const Mem& src)
+ {
+ ASMJIT_ASSERT(src.getSize() == 2 || src.getSize() == 4);
+ _emitInstruction(kX86InstFIMul, &src);
+ }
+
+ //! @brief Increment Stack-Top Pointer (FPU).
+ //!
+ //! Adds one to the TOP field of the FPU status word (increments the
+ //! top-of-stack pointer). If the TOP field contains a 7, it is set to 0.
+ //! The effect of this instruction is to rotate the stack by one position.
+ //! The contents of the FPU data registers and tag register are not affected.
+ //! This operation is not equivalent to popping the stack, because the tag
+ //! for the previous top-of-stack register is not marked empty.
+ void fincstp()
+ { _emitInstruction(kX86InstFIncStP); }
+
+ //! @brief Initialize Floating-Point Unit (FPU).
+ //!
+ //! Initialize FPU after checking for pending unmasked floating-point
+ //! exceptions.
+ void finit()
+ { _emitInstruction(kX86InstFInit); }
+
+ //! @brief Subtract 16-bit or 32-bit integer from st(0) and store result to
+ //! st(0) (FPU).
+ void fisub(const Mem& src)
+ {
+ ASMJIT_ASSERT(src.getSize() == 2 || src.getSize() == 4);
+ _emitInstruction(kX86InstFISub, &src);
+ }
+
+ //! @brief Reverse Subtract 16-bit or 32-bit integer from st(0) and
+ //! store result to st(0) (FPU).
+ void fisubr(const Mem& src)
+ {
+ ASMJIT_ASSERT(src.getSize() == 2 || src.getSize() == 4);
+ _emitInstruction(kX86InstFISubR, &src);
+ }
+
+ //! @brief Initialize Floating-Point Unit (FPU).
+ //!
+ //! Initialize FPU without checking for pending unmasked floating-point
+ //! exceptions.
+ void fninit()
+ { _emitInstruction(kX86InstFNInit); }
+
+ //! @brief Store st(0) as 16-bit or 32-bit Integer to @a dst (FPU).
+ void fist(const Mem& dst)
+ {
+ ASMJIT_ASSERT(dst.getSize() == 2 || dst.getSize() == 4);
+ _emitInstruction(kX86InstFISt, &dst);
+ }
+
+ //! @brief Store st(0) as 16-bit, 32-bit or 64-bit Integer to @a dst and pop
+ //! stack (FPU).
+ void fistp(const Mem& dst)
+ {
+ ASMJIT_ASSERT(dst.getSize() == 2 || dst.getSize() == 4 || dst.getSize() == 8);
+ _emitInstruction(kX86InstFIStP, &dst);
+ }
+
+ //! @brief Push 32-bit, 64-bit or 80-bit Floating Point Value onto the FPU
+ //! register stack (FPU).
+ void fld(const Mem& src)
+ {
+ ASMJIT_ASSERT(src.getSize() == 4 || src.getSize() == 8 || src.getSize() == 10);
+ _emitInstruction(kX86InstFLd, &src);
+ }
+
+ //! @brief Push @a reg onto the FPU register stack (FPU).
+ void fld(const X87Reg& reg)
+ { _emitInstruction(kX86InstFLd, ®); }
+
+ //! @brief Push +1.0 onto the FPU register stack (FPU).
+ void fld1()
+ { _emitInstruction(kX86InstFLd1); }
+
+ //! @brief Push log2(10) onto the FPU register stack (FPU).
+ void fldl2t()
+ { _emitInstruction(kX86InstFLdL2T); }
+
+ //! @brief Push log2(e) onto the FPU register stack (FPU).
+ void fldl2e()
+ { _emitInstruction(kX86InstFLdL2E); }
+
+ //! @brief Push pi onto the FPU register stack (FPU).
+ void fldpi()
+ { _emitInstruction(kX86InstFLdPi); }
+
+ //! @brief Push log10(2) onto the FPU register stack (FPU).
+ void fldlg2()
+ { _emitInstruction(kX86InstFLdLg2); }
+
+ //! @brief Push ln(2) onto the FPU register stack (FPU).
+ void fldln2()
+ { _emitInstruction(kX86InstFLdLn2); }
+
+ //! @brief Push +0.0 onto the FPU register stack (FPU).
+ void fldz()
+ { _emitInstruction(kX86InstFLdZ); }
+
+ //! @brief Load x87 FPU Control Word (2 bytes) (FPU).
+ void fldcw(const Mem& src)
+ { _emitInstruction(kX86InstFLdCw, &src); }
+
+ //! @brief Load x87 FPU Environment (14 or 28 bytes) (FPU).
+ void fldenv(const Mem& src)
+ { _emitInstruction(kX86InstFLdEnv, &src); }
+
+ //! @brief Multiply @a dst by @a src and store result in @a dst (FPU).
+ //!
+ //! @note One of dst or src must be st(0).
+ void fmul(const X87Reg& dst, const X87Reg& src)
+ {
+ ASMJIT_ASSERT(!dst.getRegIndex() || !src.getRegIndex());
+ _emitInstruction(kX86InstFMul, &dst, &src);
+ }
+ //! @brief Multiply st(0) by @a src and store result in st(0) (FPU).
+ //!
+ //! @note SP-FP or DP-FP determined by @a adr size.
+ void fmul(const Mem& src)
+ { _emitInstruction(kX86InstFMul, &src); }
+
+ //! @brief Multiply st(0) by @a dst and POP register stack (FPU).
+ void fmulp(const X87Reg& dst = st(1))
+ { _emitInstruction(kX86InstFMulP, &dst); }
+
+ //! @brief Clear Exceptions (FPU).
+ //!
+ //! Clear floating-point exception flags without checking for pending
+ //! unmasked floating-point exceptions.
+ //!
+ //! Clears the floating-point exception flags (PE, UE, OE, ZE, DE, and IE),
+ //! the exception summary status flag (ES), the stack fault flag (SF), and
+ //! the busy flag (B) in the FPU status word. The FCLEX instruction does
+ //! not checks for and handles any pending unmasked floating-point exceptions
+ //! before clearing the exception flags.
+ void fnclex()
+ { _emitInstruction(kX86InstFNClex); }
+
+ //! @brief No Operation (FPU).
+ void fnop()
+ { _emitInstruction(kX86InstFNop); }
+
+ //! @brief Save FPU State (FPU).
+ //!
+ //! Store FPU environment to m94byte or m108byte without
+ //! checking for pending unmasked FP exceptions.
+ //! Then re-initialize the FPU.
+ void fnsave(const Mem& dst)
+ { _emitInstruction(kX86InstFNSave, &dst); }
+
+ //! @brief Store x87 FPU Environment (FPU).
+ //!
+ //! Store FPU environment to @a dst (14 or 28 Bytes) without checking for
+ //! pending unmasked floating-point exceptions. Then mask all floating
+ //! point exceptions.
+ void fnstenv(const Mem& dst)
+ { _emitInstruction(kX86InstFNStEnv, &dst); }
+
+ //! @brief Store x87 FPU Control Word (FPU).
+ //!
+ //! Store FPU control word to @a dst (2 Bytes) without checking for pending
+ //! unmasked floating-point exceptions.
+ void fnstcw(const Mem& dst)
+ { _emitInstruction(kX86InstFNStCw, &dst); }
+
+ //! @brief Store x87 FPU Status Word (2 Bytes) (FPU).
+ void fnstsw(const GpReg& dst)
+ {
+ ASMJIT_ASSERT(dst.isRegCode(kX86RegAx));
+ _emitInstruction(kX86InstFNStSw, &dst);
+ }
+ //! @brief Store x87 FPU Status Word (2 Bytes) (FPU).
+ void fnstsw(const Mem& dst)
+ { _emitInstruction(kX86InstFNStSw, &dst); }
+
+ //! @brief Partial Arctangent (FPU).
+ //!
+ //! Replace st(1) with arctan(st(1)/st(0)) and pop the register stack.
+ void fpatan()
+ { _emitInstruction(kX86InstFPAtan); }
+
+ //! @brief Partial Remainder (FPU).
+ //!
+ //! Replace st(0) with the remainder obtained from dividing st(0) by st(1).
+ void fprem()
+ { _emitInstruction(kX86InstFPRem); }
+
+ //! @brief Partial Remainder (FPU).
+ //!
+ //! Replace st(0) with the IEEE remainder obtained from dividing st(0) by
+ //! st(1).
+ void fprem1()
+ { _emitInstruction(kX86InstFPRem1); }
+
+ //! @brief Partial Tangent (FPU).
+ //!
+ //! Replace st(0) with its tangent and push 1 onto the FPU stack.
+ void fptan()
+ { _emitInstruction(kX86InstFPTan); }
+
+ //! @brief Round to Integer (FPU).
+ //!
+ //! Rount st(0) to an Integer.
+ void frndint()
+ { _emitInstruction(kX86InstFRndInt); }
+
+ //! @brief Restore FPU State (FPU).
+ //!
+ //! Load FPU state from src (94 or 108 bytes).
+ void frstor(const Mem& src)
+ { _emitInstruction(kX86InstFRstor, &src); }
+
+ //! @brief Save FPU State (FPU).
+ //!
+ //! Store FPU state to 94 or 108-bytes after checking for
+ //! pending unmasked FP exceptions. Then reinitialize
+ //! the FPU.
+ void fsave(const Mem& dst)
+ { _emitInstruction(kX86InstFSave, &dst); }
+
+ //! @brief Scale (FPU).
+ //!
+ //! Scale st(0) by st(1).
+ void fscale()
+ { _emitInstruction(kX86InstFScale); }
+
+ //! @brief Sine (FPU).
+ //!
+ //! This instruction calculates the sine of the source operand in
+ //! register st(0) and stores the result in st(0).
+ void fsin()
+ { _emitInstruction(kX86InstFSin); }
+
+ //! @brief Sine and Cosine (FPU).
+ //!
+ //! Compute the sine and cosine of st(0); replace st(0) with
+ //! the sine, and push the cosine onto the register stack.
+ void fsincos()
+ { _emitInstruction(kX86InstFSinCos); }
+
+ //! @brief Square Root (FPU).
+ //!
+ //! Calculates square root of st(0) and stores the result in st(0).
+ void fsqrt()
+ { _emitInstruction(kX86InstFSqrt); }
+
+ //! @brief Store Floating Point Value (FPU).
+ //!
+ //! Store st(0) as 32-bit or 64-bit floating point value to @a dst.
+ void fst(const Mem& dst)
+ {
+ ASMJIT_ASSERT(dst.getSize() == 4 || dst.getSize() == 8);
+ _emitInstruction(kX86InstFSt, &dst);
+ }
+
+ //! @brief Store Floating Point Value (FPU).
+ //!
+ //! Store st(0) to @a reg.
+ void fst(const X87Reg& reg)
+ { _emitInstruction(kX86InstFSt, ®); }
+
+ //! @brief Store Floating Point Value and Pop Register Stack (FPU).
+ //!
+ //! Store st(0) as 32-bit or 64-bit floating point value to @a dst
+ //! and pop register stack.
+ void fstp(const Mem& dst)
+ {
+ ASMJIT_ASSERT(dst.getSize() == 4 || dst.getSize() == 8 || dst.getSize() == 10);
+ _emitInstruction(kX86InstFStP, &dst);
+ }
+
+ //! @brief Store Floating Point Value and Pop Register Stack (FPU).
+ //!
+ //! Store st(0) to @a reg and pop register stack.
+ void fstp(const X87Reg& reg)
+ { _emitInstruction(kX86InstFStP, ®); }
+
+ //! @brief Store x87 FPU Control Word (FPU).
+ //!
+ //! Store FPU control word to @a dst (2 Bytes) after checking for pending
+ //! unmasked floating-point exceptions.
+ void fstcw(const Mem& dst)
+ { _emitInstruction(kX86InstFStCw, &dst); }
+
+ //! @brief Store x87 FPU Environment (FPU).
+ //!
+ //! Store FPU environment to @a dst (14 or 28 Bytes) after checking for
+ //! pending unmasked floating-point exceptions. Then mask all floating
+ //! point exceptions.
+ void fstenv(const Mem& dst)
+ { _emitInstruction(kX86InstFStEnv, &dst); }
+
+ //! @brief Store x87 FPU Status Word (2 Bytes) (FPU).
+ void fstsw(const GpReg& dst)
+ {
+ ASMJIT_ASSERT(dst.isRegCode(kX86RegAx));
+ _emitInstruction(kX86InstFStSw, &dst);
+ }
+ //! @brief Store x87 FPU Status Word (2 Bytes) (FPU).
+ void fstsw(const Mem& dst)
+ { _emitInstruction(kX86InstFStSw, &dst); }
+
+ //! @brief Subtract @a src from @a dst and store result in @a dst (FPU).
+ //!
+ //! @note One of dst or src must be st(0).
+ void fsub(const X87Reg& dst, const X87Reg& src)
+ {
+ ASMJIT_ASSERT(!dst.getRegIndex() || !src.getRegIndex());
+ _emitInstruction(kX86InstFSub, &dst, &src);
+ }
+ //! @brief Subtract @a src from st(0) and store result in st(0) (FPU).
+ //!
+ //! @note SP-FP or DP-FP determined by @a adr size.
+ void fsub(const Mem& src)
+ {
+ ASMJIT_ASSERT(src.getSize() == 4 || src.getSize() == 8);
+ _emitInstruction(kX86InstFSub, &src);
+ }
+
+ //! @brief Subtract st(0) from @a dst and POP register stack (FPU).
+ void fsubp(const X87Reg& dst = st(1))
+ { _emitInstruction(kX86InstFSubP, &dst); }
+
+ //! @brief Reverse Subtract @a src from @a dst and store result in @a dst (FPU).
+ //!
+ //! @note One of dst or src must be st(0).
+ void fsubr(const X87Reg& dst, const X87Reg& src)
+ {
+ ASMJIT_ASSERT(!dst.getRegIndex() || !src.getRegIndex());
+ _emitInstruction(kX86InstFSubR, &dst, &src);
+ }
+
+ //! @brief Reverse Subtract @a src from st(0) and store result in st(0) (FPU).
+ //!
+ //! @note SP-FP or DP-FP determined by @a adr size.
+ void fsubr(const Mem& src)
+ {
+ ASMJIT_ASSERT(src.getSize() == 4 || src.getSize() == 8);
+ _emitInstruction(kX86InstFSubR, &src);
+ }
+
+ //! @brief Reverse Subtract st(0) from @a dst and POP register stack (FPU).
+ void fsubrp(const X87Reg& dst = st(1))
+ { _emitInstruction(kX86InstFSubRP, &dst); }
+
+ //! @brief Floating point test - Compare st(0) with 0.0. (FPU).
+ void ftst()
+ { _emitInstruction(kX86InstFTst); }
+
+ //! @brief Unordered Compare st(0) with @a reg (FPU).
+ void fucom(const X87Reg& reg = st(1))
+ { _emitInstruction(kX86InstFUCom, ®); }
+
+ //! @brief Unordered Compare st(0) and @a reg, check for ordered values
+ //! and Set EFLAGS (FPU).
+ void fucomi(const X87Reg& reg)
+ { _emitInstruction(kX86InstFUComI, ®); }
+
+ //! @brief UnorderedCompare st(0) and @a reg, Check for ordered values
+ //! and Set EFLAGS and pop the stack (FPU).
+ void fucomip(const X87Reg& reg = st(1))
+ { _emitInstruction(kX86InstFUComIP, ®); }
+
+ //! @brief Unordered Compare st(0) with @a reg and pop register stack (FPU).
+ void fucomp(const X87Reg& reg = st(1))
+ { _emitInstruction(kX86InstFUComP, ®); }
+
+ //! @brief Unordered compare st(0) with st(1) and pop register stack twice
+ //! (FPU).
+ void fucompp()
+ { _emitInstruction(kX86InstFUComPP); }
+
+ void fwait()
+ { _emitInstruction(kX86InstFWait); }
+
+ //! @brief Examine st(0) (FPU).
+ //!
+ //! Examines the contents of the ST(0) register and sets the condition code
+ //! flags C0, C2, and C3 in the FPU status word to indicate the class of
+ //! value or number in the register.
+ void fxam()
+ { _emitInstruction(kX86InstFXam); }
+
+ //! @brief Exchange Register Contents (FPU).
+ //!
+ //! Exchange content of st(0) with @a reg.
+ void fxch(const X87Reg& reg = st(1))
+ { _emitInstruction(kX86InstFXch, ®); }
+
+ //! @brief Restore FP And MMX(tm) State And Streaming SIMD Extension State
+ //! (FPU, MMX, SSE).
+ //!
+ //! Load FP and MMX(tm) technology and Streaming SIMD Extension state from
+ //! src (512 bytes).
+ void fxrstor(const Mem& src)
+ { _emitInstruction(kX86InstFXRstor, &src); }
+
+ //! @brief Store FP and MMX(tm) State and Streaming SIMD Extension State
+ //! (FPU, MMX, SSE).
+ //!
+ //! Store FP and MMX(tm) technology state and Streaming SIMD Extension state
+ //! to dst (512 bytes).
+ void fxsave(const Mem& dst)
+ { _emitInstruction(kX86InstFXSave, &dst); }
+
+ //! @brief Extract Exponent and Significand (FPU).
+ //!
+ //! Separate value in st(0) into exponent and significand, store exponent
+ //! in st(0), and push the significand onto the register stack.
+ void fxtract()
+ { _emitInstruction(kX86InstFXtract); }
+
+ //! @brief Compute y * log2(x).
+ //!
+ //! Replace st(1) with (st(1) * log2st(0)) and pop the register stack.
+ void fyl2x()
+ { _emitInstruction(kX86InstFYL2X); }
+
+ //! @brief Compute y * log_2(x+1).
+ //!
+ //! Replace st(1) with (st(1) * (log2st(0) + 1.0)) and pop the register stack.
+ void fyl2xp1()
+ { _emitInstruction(kX86InstFYL2XP1); }
+
+ // --------------------------------------------------------------------------
+ // [MMX]
+ // --------------------------------------------------------------------------
+
+ //! @brief Empty MMX state.
+ void emms()
+ { _emitInstruction(kX86InstEmms); }
+
+ //! @brief Move DWord (MMX).
+ void movd(const Mem& dst, const MmReg& src)
+ { _emitInstruction(kX86InstMovD, &dst, &src); }
+ //! @brief Move DWord (MMX).
+ void movd(const GpReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstMovD, &dst, &src); }
+ //! @brief Move DWord (MMX).
+ void movd(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovD, &dst, &src); }
+ //! @brief Move DWord (MMX).
+ void movd(const MmReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstMovD, &dst, &src); }
+
+ //! @brief Move QWord (MMX).
+ void movq(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstMovQ, &dst, &src); }
+ //! @brief Move QWord (MMX).
+ void movq(const Mem& dst, const MmReg& src)
+ { _emitInstruction(kX86InstMovQ, &dst, &src); }
+#if defined(ASMJIT_X64)
+ //! @brief Move QWord (MMX).
+ void movq(const GpReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstMovQ, &dst, &src); }
+#endif
+ //! @brief Move QWord (MMX).
+ void movq(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovQ, &dst, &src); }
+#if defined(ASMJIT_X64)
+ //! @brief Move QWord (MMX).
+ void movq(const MmReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstMovQ, &dst, &src); }
+#endif
+
+ //! @brief Pack with Signed Saturation (MMX).
+ void packsswb(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPackSSWB, &dst, &src); }
+ //! @brief Pack with Signed Saturation (MMX).
+ void packsswb(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPackSSWB, &dst, &src); }
+
+ //! @brief Pack with Signed Saturation (MMX).
+ void packssdw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPackSSDW, &dst, &src); }
+ //! @brief Pack with Signed Saturation (MMX).
+ void packssdw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPackSSDW, &dst, &src); }
+
+ //! @brief Pack with Unsigned Saturation (MMX).
+ void packuswb(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPackUSWB, &dst, &src); }
+ //! @brief Pack with Unsigned Saturation (MMX).
+ void packuswb(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPackUSWB, &dst, &src); }
+
+ //! @brief Packed BYTE Add (MMX).
+ void paddb(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPAddB, &dst, &src); }
+ //! @brief Packed BYTE Add (MMX).
+ void paddb(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddB, &dst, &src); }
+
+ //! @brief Packed WORD Add (MMX).
+ void paddw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPAddW, &dst, &src); }
+ //! @brief Packed WORD Add (MMX).
+ void paddw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddW, &dst, &src); }
+
+ //! @brief Packed DWORD Add (MMX).
+ void paddd(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPAddD, &dst, &src); }
+ //! @brief Packed DWORD Add (MMX).
+ void paddd(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddD, &dst, &src); }
+
+ //! @brief Packed Add with Saturation (MMX).
+ void paddsb(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPAddSB, &dst, &src); }
+ //! @brief Packed Add with Saturation (MMX).
+ void paddsb(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddSB, &dst, &src); }
+
+ //! @brief Packed Add with Saturation (MMX).
+ void paddsw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPAddSW, &dst, &src); }
+ //! @brief Packed Add with Saturation (MMX).
+ void paddsw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddSW, &dst, &src); }
+
+ //! @brief Packed Add Unsigned with Saturation (MMX).
+ void paddusb(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPAddUSB, &dst, &src); }
+ //! @brief Packed Add Unsigned with Saturation (MMX).
+ void paddusb(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddUSB, &dst, &src); }
+
+ //! @brief Packed Add Unsigned with Saturation (MMX).
+ void paddusw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPAddUSW, &dst, &src); }
+ //! @brief Packed Add Unsigned with Saturation (MMX).
+ void paddusw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddUSW, &dst, &src); }
+
+ //! @brief Logical AND (MMX).
+ void pand(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPAnd, &dst, &src); }
+ //! @brief Logical AND (MMX).
+ void pand(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAnd, &dst, &src); }
+
+ //! @brief Logical AND Not (MMX).
+ void pandn(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPAndN, &dst, &src); }
+ //! @brief Logical AND Not (MMX).
+ void pandn(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAndN, &dst, &src); }
+
+ //! @brief Packed Compare for Equal (BYTES) (MMX).
+ void pcmpeqb(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPCmpEqB, &dst, &src); }
+ //! @brief Packed Compare for Equal (BYTES) (MMX).
+ void pcmpeqb(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpEqB, &dst, &src); }
+
+ //! @brief Packed Compare for Equal (WORDS) (MMX).
+ void pcmpeqw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPCmpEqW, &dst, &src); }
+ //! @brief Packed Compare for Equal (WORDS) (MMX).
+ void pcmpeqw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpEqW, &dst, &src); }
+
+ //! @brief Packed Compare for Equal (DWORDS) (MMX).
+ void pcmpeqd(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPCmpEqD, &dst, &src); }
+ //! @brief Packed Compare for Equal (DWORDS) (MMX).
+ void pcmpeqd(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpEqD, &dst, &src); }
+
+ //! @brief Packed Compare for Greater Than (BYTES) (MMX).
+ void pcmpgtb(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPCmpGtB, &dst, &src); }
+ //! @brief Packed Compare for Greater Than (BYTES) (MMX).
+ void pcmpgtb(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpGtB, &dst, &src); }
+
+ //! @brief Packed Compare for Greater Than (WORDS) (MMX).
+ void pcmpgtw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPCmpGtW, &dst, &src); }
+ //! @brief Packed Compare for Greater Than (WORDS) (MMX).
+ void pcmpgtw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpGtW, &dst, &src); }
+
+ //! @brief Packed Compare for Greater Than (DWORDS) (MMX).
+ void pcmpgtd(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPCmpGtD, &dst, &src); }
+ //! @brief Packed Compare for Greater Than (DWORDS) (MMX).
+ void pcmpgtd(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpGtD, &dst, &src); }
+
+ //! @brief Packed Multiply High (MMX).
+ void pmulhw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPMulHW, &dst, &src); }
+ //! @brief Packed Multiply High (MMX).
+ void pmulhw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulHW, &dst, &src); }
+
+ //! @brief Packed Multiply Low (MMX).
+ void pmullw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPMulLW, &dst, &src); }
+ //! @brief Packed Multiply Low (MMX).
+ void pmullw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulLW, &dst, &src); }
+
+ //! @brief Bitwise Logical OR (MMX).
+ void por(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPOr, &dst, &src); }
+ //! @brief Bitwise Logical OR (MMX).
+ void por(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPOr, &dst, &src); }
+
+ //! @brief Packed Multiply and Add (MMX).
+ void pmaddwd(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPMAddWD, &dst, &src); }
+ //! @brief Packed Multiply and Add (MMX).
+ void pmaddwd(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMAddWD, &dst, &src); }
+
+ //! @brief Packed Shift Left Logical (MMX).
+ void pslld(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSllD, &dst, &src); }
+ //! @brief Packed Shift Left Logical (MMX).
+ void pslld(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSllD, &dst, &src); }
+ //! @brief Packed Shift Left Logical (MMX).
+ void pslld(const MmReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSllD, &dst, &src); }
+
+ //! @brief Packed Shift Left Logical (MMX).
+ void psllq(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSllQ, &dst, &src); }
+ //! @brief Packed Shift Left Logical (MMX).
+ void psllq(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSllQ, &dst, &src); }
+ //! @brief Packed Shift Left Logical (MMX).
+ void psllq(const MmReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSllQ, &dst, &src); }
+
+ //! @brief Packed Shift Left Logical (MMX).
+ void psllw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSllW, &dst, &src); }
+ //! @brief Packed Shift Left Logical (MMX).
+ void psllw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSllW, &dst, &src); }
+ //! @brief Packed Shift Left Logical (MMX).
+ void psllw(const MmReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSllW, &dst, &src); }
+
+ //! @brief Packed Shift Right Arithmetic (MMX).
+ void psrad(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSraD, &dst, &src); }
+ //! @brief Packed Shift Right Arithmetic (MMX).
+ void psrad(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSraD, &dst, &src); }
+ //! @brief Packed Shift Right Arithmetic (MMX).
+ void psrad(const MmReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSraD, &dst, &src); }
+
+ //! @brief Packed Shift Right Arithmetic (MMX).
+ void psraw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSraW, &dst, &src); }
+ //! @brief Packed Shift Right Arithmetic (MMX).
+ void psraw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSraW, &dst, &src); }
+ //! @brief Packed Shift Right Arithmetic (MMX).
+ void psraw(const MmReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSraW, &dst, &src); }
+
+ //! @brief Packed Shift Right Logical (MMX).
+ void psrld(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSrlD, &dst, &src); }
+ //! @brief Packed Shift Right Logical (MMX).
+ void psrld(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSrlD, &dst, &src); }
+ //! @brief Packed Shift Right Logical (MMX).
+ void psrld(const MmReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSrlD, &dst, &src); }
+
+ //! @brief Packed Shift Right Logical (MMX).
+ void psrlq(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSrlQ, &dst, &src); }
+ //! @brief Packed Shift Right Logical (MMX).
+ void psrlq(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSrlQ, &dst, &src); }
+ //! @brief Packed Shift Right Logical (MMX).
+ void psrlq(const MmReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSrlQ, &dst, &src); }
+
+ //! @brief Packed Shift Right Logical (MMX).
+ void psrlw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSrlW, &dst, &src); }
+ //! @brief Packed Shift Right Logical (MMX).
+ void psrlw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSrlW, &dst, &src); }
+ //! @brief Packed Shift Right Logical (MMX).
+ void psrlw(const MmReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSrlW, &dst, &src); }
+
+ //! @brief Packed Subtract (MMX).
+ void psubb(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSubB, &dst, &src); }
+ //! @brief Packed Subtract (MMX).
+ void psubb(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubB, &dst, &src); }
+
+ //! @brief Packed Subtract (MMX).
+ void psubw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSubW, &dst, &src); }
+ //! @brief Packed Subtract (MMX).
+ void psubw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubW, &dst, &src); }
+
+ //! @brief Packed Subtract (MMX).
+ void psubd(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSubD, &dst, &src); }
+ //! @brief Packed Subtract (MMX).
+ void psubd(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubD, &dst, &src); }
+
+ //! @brief Packed Subtract with Saturation (MMX).
+ void psubsb(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSubSB, &dst, &src); }
+ //! @brief Packed Subtract with Saturation (MMX).
+ void psubsb(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubSB, &dst, &src); }
+
+ //! @brief Packed Subtract with Saturation (MMX).
+ void psubsw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSubSW, &dst, &src); }
+ //! @brief Packed Subtract with Saturation (MMX).
+ void psubsw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubSW, &dst, &src); }
+
+ //! @brief Packed Subtract with Unsigned Saturation (MMX).
+ void psubusb(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSubUSB, &dst, &src); }
+ //! @brief Packed Subtract with Unsigned Saturation (MMX).
+ void psubusb(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubUSB, &dst, &src); }
+
+ //! @brief Packed Subtract with Unsigned Saturation (MMX).
+ void psubusw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSubUSW, &dst, &src); }
+ //! @brief Packed Subtract with Unsigned Saturation (MMX).
+ void psubusw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubUSW, &dst, &src); }
+
+ //! @brief Unpack High Packed Data (MMX).
+ void punpckhbw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPunpckHBW, &dst, &src); }
+ //! @brief Unpack High Packed Data (MMX).
+ void punpckhbw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckHBW, &dst, &src); }
+
+ //! @brief Unpack High Packed Data (MMX).
+ void punpckhwd(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPunpckHWD, &dst, &src); }
+ //! @brief Unpack High Packed Data (MMX).
+ void punpckhwd(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckHWD, &dst, &src); }
+
+ //! @brief Unpack High Packed Data (MMX).
+ void punpckhdq(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPunpckHDQ, &dst, &src); }
+ //! @brief Unpack High Packed Data (MMX).
+ void punpckhdq(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckHDQ, &dst, &src); }
+
+ //! @brief Unpack High Packed Data (MMX).
+ void punpcklbw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPunpckLBW, &dst, &src); }
+ //! @brief Unpack High Packed Data (MMX).
+ void punpcklbw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckLBW, &dst, &src); }
+
+ //! @brief Unpack High Packed Data (MMX).
+ void punpcklwd(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPunpckLWD, &dst, &src); }
+ //! @brief Unpack High Packed Data (MMX).
+ void punpcklwd(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckLWD, &dst, &src); }
+
+ //! @brief Unpack High Packed Data (MMX).
+ void punpckldq(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPunpckLDQ, &dst, &src); }
+ //! @brief Unpack High Packed Data (MMX).
+ void punpckldq(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckLDQ, &dst, &src); }
+
+ //! @brief Bitwise Exclusive OR (MMX).
+ void pxor(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPXor, &dst, &src); }
+ //! @brief Bitwise Exclusive OR (MMX).
+ void pxor(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPXor, &dst, &src); }
+
+ // -------------------------------------------------------------------------
+ // [3dNow]
+ // -------------------------------------------------------------------------
+
+ //! @brief Faster EMMS (3dNow!).
+ //!
+ //! @note Use only for early AMD processors where is only 3dNow! or SSE. If
+ //! CPU contains SSE2, it's better to use @c emms() ( @c femms() is mapped
+ //! to @c emms() ).
+ void femms()
+ { _emitInstruction(kX86InstFEmms); }
+
+ //! @brief Packed SP-FP to Integer Convert (3dNow!).
+ void pf2id(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPF2ID, &dst, &src); }
+ //! @brief Packed SP-FP to Integer Convert (3dNow!).
+ void pf2id(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPF2ID, &dst, &src); }
+
+ //! @brief Packed SP-FP to Integer Word Convert (3dNow!).
+ void pf2iw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPF2IW, &dst, &src); }
+ //! @brief Packed SP-FP to Integer Word Convert (3dNow!).
+ void pf2iw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPF2IW, &dst, &src); }
+
+ //! @brief Packed SP-FP Accumulate (3dNow!).
+ void pfacc(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPFAcc, &dst, &src); }
+ //! @brief Packed SP-FP Accumulate (3dNow!).
+ void pfacc(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFAcc, &dst, &src); }
+
+ //! @brief Packed SP-FP Addition (3dNow!).
+ void pfadd(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPFAdd, &dst, &src); }
+ //! @brief Packed SP-FP Addition (3dNow!).
+ void pfadd(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFAdd, &dst, &src); }
+
+ //! @brief Packed SP-FP Compare - dst == src (3dNow!).
+ void pfcmpeq(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPFCmpEQ, &dst, &src); }
+ //! @brief Packed SP-FP Compare - dst == src (3dNow!).
+ void pfcmpeq(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFCmpEQ, &dst, &src); }
+
+ //! @brief Packed SP-FP Compare - dst >= src (3dNow!).
+ void pfcmpge(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPFCmpGE, &dst, &src); }
+ //! @brief Packed SP-FP Compare - dst >= src (3dNow!).
+ void pfcmpge(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFCmpGE, &dst, &src); }
+
+ //! @brief Packed SP-FP Compare - dst > src (3dNow!).
+ void pfcmpgt(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPFCmpGT, &dst, &src); }
+ //! @brief Packed SP-FP Compare - dst > src (3dNow!).
+ void pfcmpgt(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFCmpGT, &dst, &src); }
+
+ //! @brief Packed SP-FP Maximum (3dNow!).
+ void pfmax(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPFMax, &dst, &src); }
+ //! @brief Packed SP-FP Maximum (3dNow!).
+ void pfmax(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFMax, &dst, &src); }
+
+ //! @brief Packed SP-FP Minimum (3dNow!).
+ void pfmin(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPFMin, &dst, &src); }
+ //! @brief Packed SP-FP Minimum (3dNow!).
+ void pfmin(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFMin, &dst, &src); }
+
+ //! @brief Packed SP-FP Multiply (3dNow!).
+ void pfmul(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPFMul, &dst, &src); }
+ //! @brief Packed SP-FP Multiply (3dNow!).
+ void pfmul(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFMul, &dst, &src); }
+
+ //! @brief Packed SP-FP Negative Accumulate (3dNow!).
+ void pfnacc(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPFNAcc, &dst, &src); }
+ //! @brief Packed SP-FP Negative Accumulate (3dNow!).
+ void pfnacc(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFNAcc, &dst, &src); }
+
+ //! @brief Packed SP-FP Mixed Accumulate (3dNow!).
+ void pfpnacc(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPFPNAcc, &dst, &src); }
+ //! @brief Packed SP-FP Mixed Accumulate (3dNow!).
+ void pfpnacc(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFPNAcc, &dst, &src); }
+
+ //! @brief Packed SP-FP Reciprocal Approximation (3dNow!).
+ void pfrcp(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPFRcp, &dst, &src); }
+ //! @brief Packed SP-FP Reciprocal Approximation (3dNow!).
+ void pfrcp(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFRcp, &dst, &src); }
+
+ //! @brief Packed SP-FP Reciprocal, First Iteration Step (3dNow!).
+ void pfrcpit1(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPFRcpIt1, &dst, &src); }
+ //! @brief Packed SP-FP Reciprocal, First Iteration Step (3dNow!).
+ void pfrcpit1(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFRcpIt1, &dst, &src); }
+
+ //! @brief Packed SP-FP Reciprocal, Second Iteration Step (3dNow!).
+ void pfrcpit2(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPFRcpIt2, &dst, &src); }
+ //! @brief Packed SP-FP Reciprocal, Second Iteration Step (3dNow!).
+ void pfrcpit2(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFRcpIt2, &dst, &src); }
+
+ //! @brief Packed SP-FP Reciprocal Square Root, First Iteration Step (3dNow!).
+ void pfrsqit1(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPFRSqIt1, &dst, &src); }
+ //! @brief Packed SP-FP Reciprocal Square Root, First Iteration Step (3dNow!).
+ void pfrsqit1(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFRSqIt1, &dst, &src); }
+
+ //! @brief Packed SP-FP Reciprocal Square Root Approximation (3dNow!).
+ void pfrsqrt(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPFRSqrt, &dst, &src); }
+ //! @brief Packed SP-FP Reciprocal Square Root Approximation (3dNow!).
+ void pfrsqrt(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFRSqrt, &dst, &src); }
+
+ //! @brief Packed SP-FP Subtract (3dNow!).
+ void pfsub(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPFSub, &dst, &src); }
+ //! @brief Packed SP-FP Subtract (3dNow!).
+ void pfsub(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFSub, &dst, &src); }
+
+ //! @brief Packed SP-FP Reverse Subtract (3dNow!).
+ void pfsubr(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPFSubR, &dst, &src); }
+ //! @brief Packed SP-FP Reverse Subtract (3dNow!).
+ void pfsubr(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFSubR, &dst, &src); }
+
+ //! @brief Packed DWords to SP-FP (3dNow!).
+ void pi2fd(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPI2FD, &dst, &src); }
+ //! @brief Packed DWords to SP-FP (3dNow!).
+ void pi2fd(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPI2FD, &dst, &src); }
+
+ //! @brief Packed Words to SP-FP (3dNow!).
+ void pi2fw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPI2FW, &dst, &src); }
+ //! @brief Packed Words to SP-FP (3dNow!).
+ void pi2fw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPI2FW, &dst, &src); }
+
+ //! @brief Packed swap DWord (3dNow!)
+ void pswapd(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSwapD, &dst, &src); }
+ //! @brief Packed swap DWord (3dNow!)
+ void pswapd(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSwapD, &dst, &src); }
+
+ // --------------------------------------------------------------------------
+ // [SSE]
+ // --------------------------------------------------------------------------
+
+ //! @brief Packed SP-FP Add (SSE).
+ void addps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstAddPS, &dst, &src); }
+ //! @brief Packed SP-FP Add (SSE).
+ void addps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstAddPS, &dst, &src); }
+
+ //! @brief Scalar SP-FP Add (SSE).
+ void addss(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstAddSS, &dst, &src); }
+ //! @brief Scalar SP-FP Add (SSE).
+ void addss(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstAddSS, &dst, &src); }
+
+ //! @brief Bit-wise Logical And Not For SP-FP (SSE).
+ void andnps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstAndnPS, &dst, &src); }
+ //! @brief Bit-wise Logical And Not For SP-FP (SSE).
+ void andnps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstAndnPS, &dst, &src); }
+
+ //! @brief Bit-wise Logical And For SP-FP (SSE).
+ void andps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstAndPS, &dst, &src); }
+ //! @brief Bit-wise Logical And For SP-FP (SSE).
+ void andps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstAndPS, &dst, &src); }
+
+ //! @brief Packed SP-FP Compare (SSE).
+ void cmpps(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstCmpPS, &dst, &src, &imm8); }
+ //! @brief Packed SP-FP Compare (SSE).
+ void cmpps(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstCmpPS, &dst, &src, &imm8); }
+
+ //! @brief Compare Scalar SP-FP Values (SSE).
+ void cmpss(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstCmpSS, &dst, &src, &imm8); }
+ //! @brief Compare Scalar SP-FP Values (SSE).
+ void cmpss(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstCmpSS, &dst, &src, &imm8); }
+
+ //! @brief Scalar Ordered SP-FP Compare and Set EFLAGS (SSE).
+ void comiss(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstComISS, &dst, &src); }
+ //! @brief Scalar Ordered SP-FP Compare and Set EFLAGS (SSE).
+ void comiss(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstComISS, &dst, &src); }
+
+ //! @brief Packed Signed INT32 to Packed SP-FP Conversion (SSE).
+ void cvtpi2ps(const XmmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstCvtPI2PS, &dst, &src); }
+ //! @brief Packed Signed INT32 to Packed SP-FP Conversion (SSE).
+ void cvtpi2ps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtPI2PS, &dst, &src); }
+
+ //! @brief Packed SP-FP to Packed INT32 Conversion (SSE).
+ void cvtps2pi(const MmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstCvtPS2PI, &dst, &src); }
+ //! @brief Packed SP-FP to Packed INT32 Conversion (SSE).
+ void cvtps2pi(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtPS2PI, &dst, &src); }
+
+ //! @brief Scalar Signed INT32 to SP-FP Conversion (SSE).
+ void cvtsi2ss(const XmmReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstCvtSI2SS, &dst, &src); }
+ //! @brief Scalar Signed INT32 to SP-FP Conversion (SSE).
+ void cvtsi2ss(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtSI2SS, &dst, &src); }
+
+ //! @brief Scalar SP-FP to Signed INT32 Conversion (SSE).
+ void cvtss2si(const GpReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstCvtSS2SI, &dst, &src); }
+ //! @brief Scalar SP-FP to Signed INT32 Conversion (SSE).
+ void cvtss2si(const GpReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtSS2SI, &dst, &src); }
+
+ //! @brief Packed SP-FP to Packed INT32 Conversion (truncate) (SSE).
+ void cvttps2pi(const MmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstCvttPS2PI, &dst, &src); }
+ //! @brief Packed SP-FP to Packed INT32 Conversion (truncate) (SSE).
+ void cvttps2pi(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvttPS2PI, &dst, &src); }
+
+ //! @brief Scalar SP-FP to Signed INT32 Conversion (truncate) (SSE).
+ void cvttss2si(const GpReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstCvttSS2SI, &dst, &src); }
+ //! @brief Scalar SP-FP to Signed INT32 Conversion (truncate) (SSE).
+ void cvttss2si(const GpReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvttSS2SI, &dst, &src); }
+
+ //! @brief Packed SP-FP Divide (SSE).
+ void divps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstDivPS, &dst, &src); }
+ //! @brief Packed SP-FP Divide (SSE).
+ void divps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstDivPS, &dst, &src); }
+
+ //! @brief Scalar SP-FP Divide (SSE).
+ void divss(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstDivSS, &dst, &src); }
+ //! @brief Scalar SP-FP Divide (SSE).
+ void divss(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstDivSS, &dst, &src); }
+
+ //! @brief Load Streaming SIMD Extension Control/Status (SSE).
+ void ldmxcsr(const Mem& src)
+ { _emitInstruction(kX86InstLdMXCSR, &src); }
+
+ //! @brief Byte Mask Write (SSE).
+ //!
+ //! @note The default memory location is specified by DS:EDI.
+ void maskmovq(const MmReg& data, const MmReg& mask)
+ { _emitInstruction(kX86InstMaskMovQ, &data, &mask); }
+
+ //! @brief Packed SP-FP Maximum (SSE).
+ void maxps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMaxPS, &dst, &src); }
+ //! @brief Packed SP-FP Maximum (SSE).
+ void maxps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMaxPS, &dst, &src); }
+
+ //! @brief Scalar SP-FP Maximum (SSE).
+ void maxss(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMaxSS, &dst, &src); }
+ //! @brief Scalar SP-FP Maximum (SSE).
+ void maxss(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMaxSS, &dst, &src); }
+
+ //! @brief Packed SP-FP Minimum (SSE).
+ void minps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMinPS, &dst, &src); }
+ //! @brief Packed SP-FP Minimum (SSE).
+ void minps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMinPS, &dst, &src); }
+
+ //! @brief Scalar SP-FP Minimum (SSE).
+ void minss(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMinSS, &dst, &src); }
+ //! @brief Scalar SP-FP Minimum (SSE).
+ void minss(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMinSS, &dst, &src); }
+
+ //! @brief Move Aligned Packed SP-FP Values (SSE).
+ void movaps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovAPS, &dst, &src); }
+ //! @brief Move Aligned Packed SP-FP Values (SSE).
+ void movaps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovAPS, &dst, &src); }
+
+ //! @brief Move Aligned Packed SP-FP Values (SSE).
+ void movaps(const Mem& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovAPS, &dst, &src); }
+
+ //! @brief Move DWord.
+ void movd(const Mem& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovD, &dst, &src); }
+ //! @brief Move DWord.
+ void movd(const GpReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovD, &dst, &src); }
+ //! @brief Move DWord.
+ void movd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovD, &dst, &src); }
+ //! @brief Move DWord.
+ void movd(const XmmReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstMovD, &dst, &src); }
+
+ //! @brief Move QWord (SSE).
+ void movq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovQ, &dst, &src); }
+ //! @brief Move QWord (SSE).
+ void movq(const Mem& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovQ, &dst, &src); }
+#if defined(ASMJIT_X64)
+ //! @brief Move QWord (SSE).
+ void movq(const GpReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovQ, &dst, &src); }
+#endif // ASMJIT_X64
+ //! @brief Move QWord (SSE).
+ void movq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovQ, &dst, &src); }
+#if defined(ASMJIT_X64)
+ //! @brief Move QWord (SSE).
+ void movq(const XmmReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstMovQ, &dst, &src); }
+#endif // ASMJIT_X64
+
+ //! @brief Move 64 Bits Non Temporal (SSE).
+ void movntq(const Mem& dst, const MmReg& src)
+ { _emitInstruction(kX86InstMovNTQ, &dst, &src); }
+
+ //! @brief High to Low Packed SP-FP (SSE).
+ void movhlps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovHLPS, &dst, &src); }
+
+ //! @brief Move High Packed SP-FP (SSE).
+ void movhps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovHPS, &dst, &src); }
+
+ //! @brief Move High Packed SP-FP (SSE).
+ void movhps(const Mem& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovHPS, &dst, &src); }
+
+ //! @brief Move Low to High Packed SP-FP (SSE).
+ void movlhps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovLHPS, &dst, &src); }
+
+ //! @brief Move Low Packed SP-FP (SSE).
+ void movlps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovLPS, &dst, &src); }
+
+ //! @brief Move Low Packed SP-FP (SSE).
+ void movlps(const Mem& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovLPS, &dst, &src); }
+
+ //! @brief Move Aligned Four Packed SP-FP Non Temporal (SSE).
+ void movntps(const Mem& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovNTPS, &dst, &src); }
+
+ //! @brief Move Scalar SP-FP (SSE).
+ void movss(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovSS, &dst, &src); }
+
+ //! @brief Move Scalar SP-FP (SSE).
+ void movss(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovSS, &dst, &src); }
+
+ //! @brief Move Scalar SP-FP (SSE).
+ void movss(const Mem& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovSS, &dst, &src); }
+
+ //! @brief Move Unaligned Packed SP-FP Values (SSE).
+ void movups(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovUPS, &dst, &src); }
+ //! @brief Move Unaligned Packed SP-FP Values (SSE).
+ void movups(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovUPS, &dst, &src); }
+
+ //! @brief Move Unaligned Packed SP-FP Values (SSE).
+ void movups(const Mem& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovUPS, &dst, &src); }
+
+ //! @brief Packed SP-FP Multiply (SSE).
+ void mulps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMulPS, &dst, &src); }
+ //! @brief Packed SP-FP Multiply (SSE).
+ void mulps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMulPS, &dst, &src); }
+
+ //! @brief Scalar SP-FP Multiply (SSE).
+ void mulss(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMulSS, &dst, &src); }
+ //! @brief Scalar SP-FP Multiply (SSE).
+ void mulss(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMulSS, &dst, &src); }
+
+ //! @brief Bit-wise Logical OR for SP-FP Data (SSE).
+ void orps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstOrPS, &dst, &src); }
+ //! @brief Bit-wise Logical OR for SP-FP Data (SSE).
+ void orps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstOrPS, &dst, &src); }
+
+ //! @brief Packed Average (SSE).
+ void pavgb(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPAvgB, &dst, &src); }
+ //! @brief Packed Average (SSE).
+ void pavgb(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAvgB, &dst, &src); }
+
+ //! @brief Packed Average (SSE).
+ void pavgw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPAvgW, &dst, &src); }
+ //! @brief Packed Average (SSE).
+ void pavgw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAvgW, &dst, &src); }
+
+ //! @brief Extract Word (SSE).
+ void pextrw(const GpReg& dst, const MmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPExtrW, &dst, &src, &imm8); }
+
+ //! @brief Insert Word (SSE).
+ void pinsrw(const MmReg& dst, const GpReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPInsRW, &dst, &src, &imm8); }
+ //! @brief Insert Word (SSE).
+ void pinsrw(const MmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPInsRW, &dst, &src, &imm8); }
+
+ //! @brief Packed Signed Integer Word Maximum (SSE).
+ void pmaxsw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPMaxSW, &dst, &src); }
+ //! @brief Packed Signed Integer Word Maximum (SSE).
+ void pmaxsw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMaxSW, &dst, &src); }
+
+ //! @brief Packed Unsigned Integer Byte Maximum (SSE).
+ void pmaxub(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPMaxUB, &dst, &src); }
+ //! @brief Packed Unsigned Integer Byte Maximum (SSE).
+ void pmaxub(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMaxUB, &dst, &src); }
+
+ //! @brief Packed Signed Integer Word Minimum (SSE).
+ void pminsw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPMinSW, &dst, &src); }
+ //! @brief Packed Signed Integer Word Minimum (SSE).
+ void pminsw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMinSW, &dst, &src); }
+
+ //! @brief Packed Unsigned Integer Byte Minimum (SSE).
+ void pminub(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPMinUB, &dst, &src); }
+ //! @brief Packed Unsigned Integer Byte Minimum (SSE).
+ void pminub(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMinUB, &dst, &src); }
+
+ //! @brief Move Byte Mask To Integer (SSE).
+ void pmovmskb(const GpReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPMovMskB, &dst, &src); }
+
+ //! @brief Packed Multiply High Unsigned (SSE).
+ void pmulhuw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPMulHUW, &dst, &src); }
+ //! @brief Packed Multiply High Unsigned (SSE).
+ void pmulhuw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulHUW, &dst, &src); }
+
+ //! @brief Packed Sum of Absolute Differences (SSE).
+ void psadbw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSADBW, &dst, &src); }
+ //! @brief Packed Sum of Absolute Differences (SSE).
+ void psadbw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSADBW, &dst, &src); }
+
+ //! @brief Packed Shuffle word (SSE).
+ void pshufw(const MmReg& dst, const MmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPShufW, &dst, &src, &imm8); }
+ //! @brief Packed Shuffle word (SSE).
+ void pshufw(const MmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPShufW, &dst, &src, &imm8); }
+
+ //! @brief Packed SP-FP Reciprocal (SSE).
+ void rcpps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstRcpPS, &dst, &src); }
+ //! @brief Packed SP-FP Reciprocal (SSE).
+ void rcpps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstRcpPS, &dst, &src); }
+
+ //! @brief Scalar SP-FP Reciprocal (SSE).
+ void rcpss(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstRcpSS, &dst, &src); }
+ //! @brief Scalar SP-FP Reciprocal (SSE).
+ void rcpss(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstRcpSS, &dst, &src); }
+
+ //! @brief Prefetch (SSE).
+ void prefetch(const Mem& mem, const Imm& hint)
+ { _emitInstruction(kX86InstPrefetch, &mem, &hint); }
+
+ //! @brief Compute Sum of Absolute Differences (SSE).
+ void psadbw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPSADBW, &dst, &src); }
+ //! @brief Compute Sum of Absolute Differences (SSE).
+ void psadbw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSADBW, &dst, &src); }
+
+ //! @brief Packed SP-FP Square Root Reciprocal (SSE).
+ void rsqrtps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstSqrtPS, &dst, &src); }
+ //! @brief Packed SP-FP Square Root Reciprocal (SSE).
+ void rsqrtps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstSqrtPS, &dst, &src); }
+
+ //! @brief Scalar SP-FP Square Root Reciprocal (SSE).
+ void rsqrtss(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstSqrtSS, &dst, &src); }
+ //! @brief Scalar SP-FP Square Root Reciprocal (SSE).
+ void rsqrtss(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstSqrtSS, &dst, &src); }
+
+ //! @brief Store fence (SSE).
+ void sfence()
+ { _emitInstruction(kX86InstSFence); }
+
+ //! @brief Shuffle SP-FP (SSE).
+ void shufps(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstShufPS, &dst, &src, &imm8); }
+ //! @brief Shuffle SP-FP (SSE).
+ void shufps(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstShufPS, &dst, &src, &imm8); }
+
+ //! @brief Packed SP-FP Square Root (SSE).
+ void sqrtps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstSqrtPS, &dst, &src); }
+ //! @brief Packed SP-FP Square Root (SSE).
+ void sqrtps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstSqrtPS, &dst, &src); }
+
+ //! @brief Scalar SP-FP Square Root (SSE).
+ void sqrtss(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstSqrtSS, &dst, &src); }
+ //! @brief Scalar SP-FP Square Root (SSE).
+ void sqrtss(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstSqrtSS, &dst, &src); }
+
+ //! @brief Store Streaming SIMD Extension Control/Status (SSE).
+ void stmxcsr(const Mem& dst)
+ { _emitInstruction(kX86InstStMXCSR, &dst); }
+
+ //! @brief Packed SP-FP Subtract (SSE).
+ void subps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstSubPS, &dst, &src); }
+ //! @brief Packed SP-FP Subtract (SSE).
+ void subps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstSubPS, &dst, &src); }
+
+ //! @brief Scalar SP-FP Subtract (SSE).
+ void subss(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstSubSS, &dst, &src); }
+ //! @brief Scalar SP-FP Subtract (SSE).
+ void subss(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstSubSS, &dst, &src); }
+
+ //! @brief Unordered Scalar SP-FP compare and set EFLAGS (SSE).
+ void ucomiss(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstUComISS, &dst, &src); }
+ //! @brief Unordered Scalar SP-FP compare and set EFLAGS (SSE).
+ void ucomiss(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstUComISS, &dst, &src); }
+
+ //! @brief Unpack High Packed SP-FP Data (SSE).
+ void unpckhps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstUnpckHPS, &dst, &src); }
+ //! @brief Unpack High Packed SP-FP Data (SSE).
+ void unpckhps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstUnpckHPS, &dst, &src); }
+
+ //! @brief Unpack Low Packed SP-FP Data (SSE).
+ void unpcklps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstUnpckLPS, &dst, &src); }
+ //! @brief Unpack Low Packed SP-FP Data (SSE).
+ void unpcklps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstUnpckLPS, &dst, &src); }
+
+ //! @brief Bit-wise Logical Xor for SP-FP Data (SSE).
+ void xorps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstXorPS, &dst, &src); }
+ //! @brief Bit-wise Logical Xor for SP-FP Data (SSE).
+ void xorps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstXorPS, &dst, &src); }
+
+ // --------------------------------------------------------------------------
+ // [SSE2]
+ // --------------------------------------------------------------------------
+
+ //! @brief Packed DP-FP Add (SSE2).
+ void addpd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstAddPD, &dst, &src); }
+ //! @brief Packed DP-FP Add (SSE2).
+ void addpd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstAddPD, &dst, &src); }
+
+ //! @brief Scalar DP-FP Add (SSE2).
+ void addsd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstAddSD, &dst, &src); }
+ //! @brief Scalar DP-FP Add (SSE2).
+ void addsd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstAddSD, &dst, &src); }
+
+ //! @brief Bit-wise Logical And Not For DP-FP (SSE2).
+ void andnpd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstAndnPD, &dst, &src); }
+ //! @brief Bit-wise Logical And Not For DP-FP (SSE2).
+ void andnpd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstAndnPD, &dst, &src); }
+
+ //! @brief Bit-wise Logical And For DP-FP (SSE2).
+ void andpd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstAndPD, &dst, &src); }
+ //! @brief Bit-wise Logical And For DP-FP (SSE2).
+ void andpd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstAndPD, &dst, &src); }
+
+ //! @brief Flush Cache Line (SSE2).
+ void clflush(const Mem& mem)
+ { _emitInstruction(kX86InstClFlush, &mem); }
+
+ //! @brief Packed DP-FP Compare (SSE2).
+ void cmppd(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstCmpPD, &dst, &src, &imm8); }
+ //! @brief Packed DP-FP Compare (SSE2).
+ void cmppd(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstCmpPD, &dst, &src, &imm8); }
+
+ //! @brief Compare Scalar SP-FP Values (SSE2).
+ void cmpsd(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstCmpSD, &dst, &src, &imm8); }
+ //! @brief Compare Scalar SP-FP Values (SSE2).
+ void cmpsd(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstCmpSD, &dst, &src, &imm8); }
+
+ //! @brief Scalar Ordered DP-FP Compare and Set EFLAGS (SSE2).
+ void comisd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstComISD, &dst, &src); }
+ //! @brief Scalar Ordered DP-FP Compare and Set EFLAGS (SSE2).
+ void comisd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstComISD, &dst, &src); }
+
+ //! @brief Convert Packed Dword Integers to Packed DP-FP Values (SSE2).
+ void cvtdq2pd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstCvtDQ2PD, &dst, &src); }
+ //! @brief Convert Packed Dword Integers to Packed DP-FP Values (SSE2).
+ void cvtdq2pd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtDQ2PD, &dst, &src); }
+
+ //! @brief Convert Packed Dword Integers to Packed SP-FP Values (SSE2).
+ void cvtdq2ps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstCvtDQ2PS, &dst, &src); }
+ //! @brief Convert Packed Dword Integers to Packed SP-FP Values (SSE2).
+ void cvtdq2ps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtDQ2PS, &dst, &src); }
+
+ //! @brief Convert Packed DP-FP Values to Packed Dword Integers (SSE2).
+ void cvtpd2dq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstCvtPD2DQ, &dst, &src); }
+ //! @brief Convert Packed DP-FP Values to Packed Dword Integers (SSE2).
+ void cvtpd2dq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtPD2DQ, &dst, &src); }
+
+ //! @brief Convert Packed DP-FP Values to Packed Dword Integers (SSE2).
+ void cvtpd2pi(const MmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstCvtPD2PI, &dst, &src); }
+ //! @brief Convert Packed DP-FP Values to Packed Dword Integers (SSE2).
+ void cvtpd2pi(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtPD2PI, &dst, &src); }
+
+ //! @brief Convert Packed DP-FP Values to Packed SP-FP Values (SSE2).
+ void cvtpd2ps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstCvtPD2PS, &dst, &src); }
+ //! @brief Convert Packed DP-FP Values to Packed SP-FP Values (SSE2).
+ void cvtpd2ps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtPD2PS, &dst, &src); }
+
+ //! @brief Convert Packed Dword Integers to Packed DP-FP Values (SSE2).
+ void cvtpi2pd(const XmmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstCvtPI2PD, &dst, &src); }
+ //! @brief Convert Packed Dword Integers to Packed DP-FP Values (SSE2).
+ void cvtpi2pd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtPI2PD, &dst, &src); }
+
+ //! @brief Convert Packed SP-FP Values to Packed Dword Integers (SSE2).
+ void cvtps2dq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstCvtPS2DQ, &dst, &src); }
+ //! @brief Convert Packed SP-FP Values to Packed Dword Integers (SSE2).
+ void cvtps2dq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtPS2DQ, &dst, &src); }
+
+ //! @brief Convert Packed SP-FP Values to Packed DP-FP Values (SSE2).
+ void cvtps2pd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstCvtPS2PD, &dst, &src); }
+ //! @brief Convert Packed SP-FP Values to Packed DP-FP Values (SSE2).
+ void cvtps2pd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtPS2PD, &dst, &src); }
+
+ //! @brief Convert Scalar DP-FP Value to Dword Integer (SSE2).
+ void cvtsd2si(const GpReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstCvtSD2SI, &dst, &src); }
+ //! @brief Convert Scalar DP-FP Value to Dword Integer (SSE2).
+ void cvtsd2si(const GpReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtSD2SI, &dst, &src); }
+
+ //! @brief Convert Scalar DP-FP Value to Scalar SP-FP Value (SSE2).
+ void cvtsd2ss(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstCvtSD2SS, &dst, &src); }
+ //! @brief Convert Scalar DP-FP Value to Scalar SP-FP Value (SSE2).
+ void cvtsd2ss(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtSD2SS, &dst, &src); }
+
+ //! @brief Convert Dword Integer to Scalar DP-FP Value (SSE2).
+ void cvtsi2sd(const XmmReg& dst, const GpReg& src)
+ { _emitInstruction(kX86InstCvtSI2SD, &dst, &src); }
+ //! @brief Convert Dword Integer to Scalar DP-FP Value (SSE2).
+ void cvtsi2sd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtSI2SD, &dst, &src); }
+
+ //! @brief Convert Scalar SP-FP Value to Scalar DP-FP Value (SSE2).
+ void cvtss2sd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstCvtSS2SD, &dst, &src); }
+ //! @brief Convert Scalar SP-FP Value to Scalar DP-FP Value (SSE2).
+ void cvtss2sd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtSS2SD, &dst, &src); }
+
+ //! @brief Convert with Truncation Packed DP-FP Values to Packed Dword Integers (SSE2).
+ void cvttpd2pi(const MmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstCvttPD2PI, &dst, &src); }
+ //! @brief Convert with Truncation Packed DP-FP Values to Packed Dword Integers (SSE2).
+ void cvttpd2pi(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvttPD2PI, &dst, &src); }
+
+ //! @brief Convert with Truncation Packed DP-FP Values to Packed Dword Integers (SSE2).
+ void cvttpd2dq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstCvttPD2DQ, &dst, &src); }
+ //! @brief Convert with Truncation Packed DP-FP Values to Packed Dword Integers (SSE2).
+ void cvttpd2dq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvttPD2DQ, &dst, &src); }
+
+ //! @brief Convert with Truncation Packed SP-FP Values to Packed Dword Integers (SSE2).
+ void cvttps2dq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstCvttPS2DQ, &dst, &src); }
+ //! @brief Convert with Truncation Packed SP-FP Values to Packed Dword Integers (SSE2).
+ void cvttps2dq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvttPS2DQ, &dst, &src); }
+
+ //! @brief Convert with Truncation Scalar DP-FP Value to Signed Dword Integer (SSE2).
+ void cvttsd2si(const GpReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstCvttSD2SI, &dst, &src); }
+ //! @brief Convert with Truncation Scalar DP-FP Value to Signed Dword Integer (SSE2).
+ void cvttsd2si(const GpReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvttSD2SI, &dst, &src); }
+
+ //! @brief Packed DP-FP Divide (SSE2).
+ void divpd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstDivPD, &dst, &src); }
+ //! @brief Packed DP-FP Divide (SSE2).
+ void divpd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstDivPD, &dst, &src); }
+
+ //! @brief Scalar DP-FP Divide (SSE2).
+ void divsd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstDivSD, &dst, &src); }
+ //! @brief Scalar DP-FP Divide (SSE2).
+ void divsd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstDivSD, &dst, &src); }
+
+ //! @brief Load Fence (SSE2).
+ void lfence()
+ { _emitInstruction(kX86InstLFence); }
+
+ //! @brief Store Selected Bytes of Double Quadword (SSE2).
+ //!
+ //! @note Target is DS:EDI.
+ void maskmovdqu(const XmmReg& src, const XmmReg& mask)
+ { _emitInstruction(kX86InstMaskMovDQU, &src, &mask); }
+
+ //! @brief Return Maximum Packed Double-Precision FP Values (SSE2).
+ void maxpd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMaxPD, &dst, &src); }
+ //! @brief Return Maximum Packed Double-Precision FP Values (SSE2).
+ void maxpd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMaxPD, &dst, &src); }
+
+ //! @brief Return Maximum Scalar Double-Precision FP Value (SSE2).
+ void maxsd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMaxSD, &dst, &src); }
+ //! @brief Return Maximum Scalar Double-Precision FP Value (SSE2).
+ void maxsd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMaxSD, &dst, &src); }
+
+ //! @brief Memory Fence (SSE2).
+ void mfence()
+ { _emitInstruction(kX86InstMFence); }
+
+ //! @brief Return Minimum Packed DP-FP Values (SSE2).
+ void minpd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMinPD, &dst, &src); }
+ //! @brief Return Minimum Packed DP-FP Values (SSE2).
+ void minpd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMinPD, &dst, &src); }
+
+ //! @brief Return Minimum Scalar DP-FP Value (SSE2).
+ void minsd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMinSD, &dst, &src); }
+ //! @brief Return Minimum Scalar DP-FP Value (SSE2).
+ void minsd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMinSD, &dst, &src); }
+
+ //! @brief Move Aligned DQWord (SSE2).
+ void movdqa(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovDQA, &dst, &src); }
+ //! @brief Move Aligned DQWord (SSE2).
+ void movdqa(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovDQA, &dst, &src); }
+
+ //! @brief Move Aligned DQWord (SSE2).
+ void movdqa(const Mem& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovDQA, &dst, &src); }
+
+ //! @brief Move Unaligned Double Quadword (SSE2).
+ void movdqu(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovDQU, &dst, &src); }
+ //! @brief Move Unaligned Double Quadword (SSE2).
+ void movdqu(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovDQU, &dst, &src); }
+
+ //! @brief Move Unaligned Double Quadword (SSE2).
+ void movdqu(const Mem& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovDQU, &dst, &src); }
+
+ //! @brief Extract Packed SP-FP Sign Mask (SSE2).
+ void movmskps(const GpReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovMskPS, &dst, &src); }
+
+ //! @brief Extract Packed DP-FP Sign Mask (SSE2).
+ void movmskpd(const GpReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovMskPD, &dst, &src); }
+
+ //! @brief Move Scalar Double-Precision FP Value (SSE2).
+ void movsd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovSD, &dst, &src); }
+ //! @brief Move Scalar Double-Precision FP Value (SSE2).
+ void movsd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovSD, &dst, &src); }
+
+ //! @brief Move Scalar Double-Precision FP Value (SSE2).
+ void movsd(const Mem& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovSD, &dst, &src); }
+
+ //! @brief Move Aligned Packed Double-Precision FP Values (SSE2).
+ void movapd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovAPD, &dst, &src); }
+
+ //! @brief Move Aligned Packed Double-Precision FP Values (SSE2).
+ void movapd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovAPD, &dst, &src); }
+
+ //! @brief Move Aligned Packed Double-Precision FP Values (SSE2).
+ void movapd(const Mem& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovAPD, &dst, &src); }
+
+ //! @brief Move Quadword from XMM to MMX Technology Register (SSE2).
+ void movdq2q(const MmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovDQ2Q, &dst, &src); }
+
+ //! @brief Move Quadword from MMX Technology to XMM Register (SSE2).
+ void movq2dq(const XmmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstMovQ2DQ, &dst, &src); }
+
+ //! @brief Move High Packed Double-Precision FP Value (SSE2).
+ void movhpd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovHPD, &dst, &src); }
+
+ //! @brief Move High Packed Double-Precision FP Value (SSE2).
+ void movhpd(const Mem& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovHPD, &dst, &src); }
+
+ //! @brief Move Low Packed Double-Precision FP Value (SSE2).
+ void movlpd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovLPD, &dst, &src); }
+
+ //! @brief Move Low Packed Double-Precision FP Value (SSE2).
+ void movlpd(const Mem& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovLPD, &dst, &src); }
+
+ //! @brief Store Double Quadword Using Non-Temporal Hint (SSE2).
+ void movntdq(const Mem& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovNTDQ, &dst, &src); }
+
+ //! @brief Store Store DWORD Using Non-Temporal Hint (SSE2).
+ void movnti(const Mem& dst, const GpReg& src)
+ { _emitInstruction(kX86InstMovNTI, &dst, &src); }
+
+ //! @brief Store Packed Double-Precision FP Values Using Non-Temporal Hint (SSE2).
+ void movntpd(const Mem& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovNTPD, &dst, &src); }
+
+ //! @brief Move Unaligned Packed Double-Precision FP Values (SSE2).
+ void movupd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovUPD, &dst, &src); }
+
+ //! @brief Move Unaligned Packed Double-Precision FP Values (SSE2).
+ void movupd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovUPD, &dst, &src); }
+
+ //! @brief Move Unaligned Packed Double-Precision FP Values (SSE2).
+ void movupd(const Mem& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovUPD, &dst, &src); }
+
+ //! @brief Packed DP-FP Multiply (SSE2).
+ void mulpd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMulPD, &dst, &src); }
+ //! @brief Packed DP-FP Multiply (SSE2).
+ void mulpd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMulPD, &dst, &src); }
+
+ //! @brief Scalar DP-FP Multiply (SSE2).
+ void mulsd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMulSD, &dst, &src); }
+ //! @brief Scalar DP-FP Multiply (SSE2).
+ void mulsd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMulSD, &dst, &src); }
+
+ //! @brief Bit-wise Logical OR for DP-FP Data (SSE2).
+ void orpd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstOrPD, &dst, &src); }
+ //! @brief Bit-wise Logical OR for DP-FP Data (SSE2).
+ void orpd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstOrPD, &dst, &src); }
+
+ //! @brief Pack with Signed Saturation (SSE2).
+ void packsswb(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPackSSWB, &dst, &src); }
+ //! @brief Pack with Signed Saturation (SSE2).
+ void packsswb(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPackSSWB, &dst, &src); }
+
+ //! @brief Pack with Signed Saturation (SSE2).
+ void packssdw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPackSSDW, &dst, &src); }
+ //! @brief Pack with Signed Saturation (SSE2).
+ void packssdw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPackSSDW, &dst, &src); }
+
+ //! @brief Pack with Unsigned Saturation (SSE2).
+ void packuswb(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPackUSWB, &dst, &src); }
+ //! @brief Pack with Unsigned Saturation (SSE2).
+ void packuswb(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPackUSWB, &dst, &src); }
+
+ //! @brief Packed BYTE Add (SSE2).
+ void paddb(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPAddB, &dst, &src); }
+ //! @brief Packed BYTE Add (SSE2).
+ void paddb(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddB, &dst, &src); }
+
+ //! @brief Packed WORD Add (SSE2).
+ void paddw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPAddW, &dst, &src); }
+ //! @brief Packed WORD Add (SSE2).
+ void paddw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddW, &dst, &src); }
+
+ //! @brief Packed DWORD Add (SSE2).
+ void paddd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPAddD, &dst, &src); }
+ //! @brief Packed DWORD Add (SSE2).
+ void paddd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddD, &dst, &src); }
+
+ //! @brief Packed QWORD Add (SSE2).
+ void paddq(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPAddQ, &dst, &src); }
+ //! @brief Packed QWORD Add (SSE2).
+ void paddq(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddQ, &dst, &src); }
+
+ //! @brief Packed QWORD Add (SSE2).
+ void paddq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPAddQ, &dst, &src); }
+ //! @brief Packed QWORD Add (SSE2).
+ void paddq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddQ, &dst, &src); }
+
+ //! @brief Packed Add with Saturation (SSE2).
+ void paddsb(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPAddSB, &dst, &src); }
+ //! @brief Packed Add with Saturation (SSE2).
+ void paddsb(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddSB, &dst, &src); }
+
+ //! @brief Packed Add with Saturation (SSE2).
+ void paddsw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPAddSW, &dst, &src); }
+ //! @brief Packed Add with Saturation (SSE2).
+ void paddsw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddSW, &dst, &src); }
+
+ //! @brief Packed Add Unsigned with Saturation (SSE2).
+ void paddusb(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPAddUSB, &dst, &src); }
+ //! @brief Packed Add Unsigned with Saturation (SSE2).
+ void paddusb(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddUSB, &dst, &src); }
+
+ //! @brief Packed Add Unsigned with Saturation (SSE2).
+ void paddusw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPAddUSW, &dst, &src); }
+ //! @brief Packed Add Unsigned with Saturation (SSE2).
+ void paddusw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddUSW, &dst, &src); }
+
+ //! @brief Logical AND (SSE2).
+ void pand(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPAnd, &dst, &src); }
+ //! @brief Logical AND (SSE2).
+ void pand(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAnd, &dst, &src); }
+
+ //! @brief Logical AND Not (SSE2).
+ void pandn(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPAndN, &dst, &src); }
+ //! @brief Logical AND Not (SSE2).
+ void pandn(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAndN, &dst, &src); }
+
+ //! @brief Spin Loop Hint (SSE2).
+ void pause()
+ { _emitInstruction(kX86InstPause); }
+
+ //! @brief Packed Average (SSE2).
+ void pavgb(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPAvgB, &dst, &src); }
+ //! @brief Packed Average (SSE2).
+ void pavgb(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAvgB, &dst, &src); }
+
+ //! @brief Packed Average (SSE2).
+ void pavgw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPAvgW, &dst, &src); }
+ //! @brief Packed Average (SSE2).
+ void pavgw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAvgW, &dst, &src); }
+
+ //! @brief Packed Compare for Equal (BYTES) (SSE2).
+ void pcmpeqb(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPCmpEqB, &dst, &src); }
+ //! @brief Packed Compare for Equal (BYTES) (SSE2).
+ void pcmpeqb(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpEqB, &dst, &src); }
+
+ //! @brief Packed Compare for Equal (WORDS) (SSE2).
+ void pcmpeqw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPCmpEqW, &dst, &src); }
+ //! @brief Packed Compare for Equal (WORDS) (SSE2).
+ void pcmpeqw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpEqW, &dst, &src); }
+
+ //! @brief Packed Compare for Equal (DWORDS) (SSE2).
+ void pcmpeqd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPCmpEqD, &dst, &src); }
+ //! @brief Packed Compare for Equal (DWORDS) (SSE2).
+ void pcmpeqd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpEqD, &dst, &src); }
+
+ //! @brief Packed Compare for Greater Than (BYTES) (SSE2).
+ void pcmpgtb(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPCmpGtB, &dst, &src); }
+ //! @brief Packed Compare for Greater Than (BYTES) (SSE2).
+ void pcmpgtb(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpGtB, &dst, &src); }
+
+ //! @brief Packed Compare for Greater Than (WORDS) (SSE2).
+ void pcmpgtw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPCmpGtW, &dst, &src); }
+ //! @brief Packed Compare for Greater Than (WORDS) (SSE2).
+ void pcmpgtw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpGtW, &dst, &src); }
+
+ //! @brief Packed Compare for Greater Than (DWORDS) (SSE2).
+ void pcmpgtd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPCmpGtD, &dst, &src); }
+ //! @brief Packed Compare for Greater Than (DWORDS) (SSE2).
+ void pcmpgtd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpGtD, &dst, &src); }
+
+ //! @brief Packed Signed Integer Word Maximum (SSE2).
+ void pmaxsw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMaxSW, &dst, &src); }
+ //! @brief Packed Signed Integer Word Maximum (SSE2).
+ void pmaxsw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMaxSW, &dst, &src); }
+
+ //! @brief Packed Unsigned Integer Byte Maximum (SSE2).
+ void pmaxub(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMaxUB, &dst, &src); }
+ //! @brief Packed Unsigned Integer Byte Maximum (SSE2).
+ void pmaxub(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMaxUB, &dst, &src); }
+
+ //! @brief Packed Signed Integer Word Minimum (SSE2).
+ void pminsw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMinSW, &dst, &src); }
+ //! @brief Packed Signed Integer Word Minimum (SSE2).
+ void pminsw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMinSW, &dst, &src); }
+
+ //! @brief Packed Unsigned Integer Byte Minimum (SSE2).
+ void pminub(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMinUB, &dst, &src); }
+ //! @brief Packed Unsigned Integer Byte Minimum (SSE2).
+ void pminub(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMinUB, &dst, &src); }
+
+ //! @brief Move Byte Mask (SSE2).
+ void pmovmskb(const GpReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMovMskB, &dst, &src); }
+
+ //! @brief Packed Multiply High (SSE2).
+ void pmulhw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMulHW, &dst, &src); }
+ //! @brief Packed Multiply High (SSE2).
+ void pmulhw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulHW, &dst, &src); }
+
+ //! @brief Packed Multiply High Unsigned (SSE2).
+ void pmulhuw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMulHUW, &dst, &src); }
+ //! @brief Packed Multiply High Unsigned (SSE2).
+ void pmulhuw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulHUW, &dst, &src); }
+
+ //! @brief Packed Multiply Low (SSE2).
+ void pmullw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMulLW, &dst, &src); }
+ //! @brief Packed Multiply Low (SSE2).
+ void pmullw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulLW, &dst, &src); }
+
+ //! @brief Packed Multiply to QWORD (SSE2).
+ void pmuludq(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPMulUDQ, &dst, &src); }
+ //! @brief Packed Multiply to QWORD (SSE2).
+ void pmuludq(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulUDQ, &dst, &src); }
+
+ //! @brief Packed Multiply to QWORD (SSE2).
+ void pmuludq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMulUDQ, &dst, &src); }
+ //! @brief Packed Multiply to QWORD (SSE2).
+ void pmuludq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulUDQ, &dst, &src); }
+
+ //! @brief Bitwise Logical OR (SSE2).
+ void por(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPOr, &dst, &src); }
+ //! @brief Bitwise Logical OR (SSE2).
+ void por(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPOr, &dst, &src); }
+
+ //! @brief Packed Shift Left Logical (SSE2).
+ void pslld(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPSllD, &dst, &src); }
+ //! @brief Packed Shift Left Logical (SSE2).
+ void pslld(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSllD, &dst, &src); }
+ //! @brief Packed Shift Left Logical (SSE2).
+ void pslld(const XmmReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSllD, &dst, &src); }
+
+ //! @brief Packed Shift Left Logical (SSE2).
+ void psllq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPSllQ, &dst, &src); }
+ //! @brief Packed Shift Left Logical (SSE2).
+ void psllq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSllQ, &dst, &src); }
+ //! @brief Packed Shift Left Logical (SSE2).
+ void psllq(const XmmReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSllQ, &dst, &src); }
+
+ //! @brief Packed Shift Left Logical (SSE2).
+ void psllw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPSllW, &dst, &src); }
+ //! @brief Packed Shift Left Logical (SSE2).
+ void psllw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSllW, &dst, &src); }
+ //! @brief Packed Shift Left Logical (SSE2).
+ void psllw(const XmmReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSllW, &dst, &src); }
+
+ //! @brief Packed Shift Left Logical (SSE2).
+ void pslldq(const XmmReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSllDQ, &dst, &src); }
+
+ //! @brief Packed Shift Right Arithmetic (SSE2).
+ void psrad(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPSraD, &dst, &src); }
+ //! @brief Packed Shift Right Arithmetic (SSE2).
+ void psrad(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSraD, &dst, &src); }
+ //! @brief Packed Shift Right Arithmetic (SSE2).
+ void psrad(const XmmReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSraD, &dst, &src); }
+
+ //! @brief Packed Shift Right Arithmetic (SSE2).
+ void psraw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPSraW, &dst, &src); }
+ //! @brief Packed Shift Right Arithmetic (SSE2).
+ void psraw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSraW, &dst, &src); }
+ //! @brief Packed Shift Right Arithmetic (SSE2).
+ void psraw(const XmmReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSraW, &dst, &src); }
+
+ //! @brief Packed Subtract (SSE2).
+ void psubb(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPSubB, &dst, &src); }
+ //! @brief Packed Subtract (SSE2).
+ void psubb(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubB, &dst, &src); }
+
+ //! @brief Packed Subtract (SSE2).
+ void psubw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPSubW, &dst, &src); }
+ //! @brief Packed Subtract (SSE2).
+ void psubw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubW, &dst, &src); }
+
+ //! @brief Packed Subtract (SSE2).
+ void psubd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPSubD, &dst, &src); }
+ //! @brief Packed Subtract (SSE2).
+ void psubd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubD, &dst, &src); }
+
+ //! @brief Packed Subtract (SSE2).
+ void psubq(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSubQ, &dst, &src); }
+ //! @brief Packed Subtract (SSE2).
+ void psubq(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubQ, &dst, &src); }
+
+ //! @brief Packed Subtract (SSE2).
+ void psubq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPSubQ, &dst, &src); }
+ //! @brief Packed Subtract (SSE2).
+ void psubq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubQ, &dst, &src); }
+
+ //! @brief Packed Multiply and Add (SSE2).
+ void pmaddwd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMAddWD, &dst, &src); }
+ //! @brief Packed Multiply and Add (SSE2).
+ void pmaddwd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMAddWD, &dst, &src); }
+
+ //! @brief Shuffle Packed DWORDs (SSE2).
+ void pshufd(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPShufD, &dst, &src, &imm8); }
+ //! @brief Shuffle Packed DWORDs (SSE2).
+ void pshufd(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPShufD, &dst, &src, &imm8); }
+
+ //! @brief Shuffle Packed High Words (SSE2).
+ void pshufhw(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPShufHW, &dst, &src, &imm8); }
+ //! @brief Shuffle Packed High Words (SSE2).
+ void pshufhw(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPShufHW, &dst, &src, &imm8); }
+
+ //! @brief Shuffle Packed Low Words (SSE2).
+ void pshuflw(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPShufLW, &dst, &src, &imm8); }
+ //! @brief Shuffle Packed Low Words (SSE2).
+ void pshuflw(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPShufLW, &dst, &src, &imm8); }
+
+ //! @brief Packed Shift Right Logical (SSE2).
+ void psrld(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPSrlD, &dst, &src); }
+ //! @brief Packed Shift Right Logical (SSE2).
+ void psrld(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSrlD, &dst, &src); }
+ //! @brief Packed Shift Right Logical (SSE2).
+ void psrld(const XmmReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSrlD, &dst, &src); }
+
+ //! @brief Packed Shift Right Logical (SSE2).
+ void psrlq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPSrlQ, &dst, &src); }
+ //! @brief Packed Shift Right Logical (SSE2).
+ void psrlq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSrlQ, &dst, &src); }
+ //! @brief Packed Shift Right Logical (SSE2).
+ void psrlq(const XmmReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSrlQ, &dst, &src); }
+
+ //! @brief DQWord Shift Right Logical (MMX).
+ void psrldq(const XmmReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSrlDQ, &dst, &src); }
+
+ //! @brief Packed Shift Right Logical (SSE2).
+ void psrlw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPSrlW, &dst, &src); }
+ //! @brief Packed Shift Right Logical (SSE2).
+ void psrlw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSrlW, &dst, &src); }
+ //! @brief Packed Shift Right Logical (SSE2).
+ void psrlw(const XmmReg& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSrlW, &dst, &src); }
+
+ //! @brief Packed Subtract with Saturation (SSE2).
+ void psubsb(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPSubSB, &dst, &src); }
+ //! @brief Packed Subtract with Saturation (SSE2).
+ void psubsb(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubSB, &dst, &src); }
+
+ //! @brief Packed Subtract with Saturation (SSE2).
+ void psubsw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPSubSW, &dst, &src); }
+ //! @brief Packed Subtract with Saturation (SSE2).
+ void psubsw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubSW, &dst, &src); }
+
+ //! @brief Packed Subtract with Unsigned Saturation (SSE2).
+ void psubusb(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPSubUSB, &dst, &src); }
+ //! @brief Packed Subtract with Unsigned Saturation (SSE2).
+ void psubusb(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubUSB, &dst, &src); }
+
+ //! @brief Packed Subtract with Unsigned Saturation (SSE2).
+ void psubusw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPSubUSW, &dst, &src); }
+ //! @brief Packed Subtract with Unsigned Saturation (SSE2).
+ void psubusw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubUSW, &dst, &src); }
+
+ //! @brief Unpack High Data (SSE2).
+ void punpckhbw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPunpckHBW, &dst, &src); }
+ //! @brief Unpack High Data (SSE2).
+ void punpckhbw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckHBW, &dst, &src); }
+
+ //! @brief Unpack High Data (SSE2).
+ void punpckhwd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPunpckHWD, &dst, &src); }
+ //! @brief Unpack High Data (SSE2).
+ void punpckhwd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckHWD, &dst, &src); }
+
+ //! @brief Unpack High Data (SSE2).
+ void punpckhdq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPunpckHDQ, &dst, &src); }
+ //! @brief Unpack High Data (SSE2).
+ void punpckhdq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckHDQ, &dst, &src); }
+
+ //! @brief Unpack High Data (SSE2).
+ void punpckhqdq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPunpckHQDQ, &dst, &src); }
+ //! @brief Unpack High Data (SSE2).
+ void punpckhqdq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckHQDQ, &dst, &src); }
+
+ //! @brief Unpack Low Data (SSE2).
+ void punpcklbw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPunpckLBW, &dst, &src); }
+ //! @brief Unpack Low Data (SSE2).
+ void punpcklbw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckLBW, &dst, &src); }
+
+ //! @brief Unpack Low Data (SSE2).
+ void punpcklwd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPunpckLWD, &dst, &src); }
+ //! @brief Unpack Low Data (SSE2).
+ void punpcklwd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckLWD, &dst, &src); }
+
+ //! @brief Unpack Low Data (SSE2).
+ void punpckldq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPunpckLDQ, &dst, &src); }
+ //! @brief Unpack Low Data (SSE2).
+ void punpckldq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckLDQ, &dst, &src); }
+
+ //! @brief Unpack Low Data (SSE2).
+ void punpcklqdq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPunpckLQDQ, &dst, &src); }
+ //! @brief Unpack Low Data (SSE2).
+ void punpcklqdq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckLQDQ, &dst, &src); }
+
+ //! @brief Bitwise Exclusive OR (SSE2).
+ void pxor(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPXor, &dst, &src); }
+ //! @brief Bitwise Exclusive OR (SSE2).
+ void pxor(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPXor, &dst, &src); }
+
+ //! @brief Shuffle DP-FP (SSE2).
+ void shufpd(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstShufPD, &dst, &src, &imm8); }
+ //! @brief Shuffle DP-FP (SSE2).
+ void shufpd(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstShufPD, &dst, &src, &imm8); }
+
+ //! @brief Compute Square Roots of Packed DP-FP Values (SSE2).
+ void sqrtpd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstSqrtPD, &dst, &src); }
+ //! @brief Compute Square Roots of Packed DP-FP Values (SSE2).
+ void sqrtpd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstSqrtPD, &dst, &src); }
+
+ //! @brief Compute Square Root of Scalar DP-FP Value (SSE2).
+ void sqrtsd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstSqrtSD, &dst, &src); }
+ //! @brief Compute Square Root of Scalar DP-FP Value (SSE2).
+ void sqrtsd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstSqrtSD, &dst, &src); }
+
+ //! @brief Packed DP-FP Subtract (SSE2).
+ void subpd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstSubPD, &dst, &src); }
+ //! @brief Packed DP-FP Subtract (SSE2).
+ void subpd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstSubPD, &dst, &src); }
+
+ //! @brief Scalar DP-FP Subtract (SSE2).
+ void subsd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstSubSD, &dst, &src); }
+ //! @brief Scalar DP-FP Subtract (SSE2).
+ void subsd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstSubSD, &dst, &src); }
+
+ //! @brief Scalar Unordered DP-FP Compare and Set EFLAGS (SSE2).
+ void ucomisd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstUComISD, &dst, &src); }
+ //! @brief Scalar Unordered DP-FP Compare and Set EFLAGS (SSE2).
+ void ucomisd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstUComISD, &dst, &src); }
+
+ //! @brief Unpack and Interleave High Packed Double-Precision FP Values (SSE2).
+ void unpckhpd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstUnpckHPD, &dst, &src); }
+ //! @brief Unpack and Interleave High Packed Double-Precision FP Values (SSE2).
+ void unpckhpd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstUnpckHPD, &dst, &src); }
+
+ //! @brief Unpack and Interleave Low Packed Double-Precision FP Values (SSE2).
+ void unpcklpd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstUnpckLPD, &dst, &src); }
+ //! @brief Unpack and Interleave Low Packed Double-Precision FP Values (SSE2).
+ void unpcklpd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstUnpckLPD, &dst, &src); }
+
+ //! @brief Bit-wise Logical OR for DP-FP Data (SSE2).
+ void xorpd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstXorPD, &dst, &src); }
+ //! @brief Bit-wise Logical OR for DP-FP Data (SSE2).
+ void xorpd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstXorPD, &dst, &src); }
+
+ // --------------------------------------------------------------------------
+ // [SSE3]
+ // --------------------------------------------------------------------------
+
+ //! @brief Packed DP-FP Add/Subtract (SSE3).
+ void addsubpd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstAddSubPD, &dst, &src); }
+ //! @brief Packed DP-FP Add/Subtract (SSE3).
+ void addsubpd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstAddSubPD, &dst, &src); }
+
+ //! @brief Packed SP-FP Add/Subtract (SSE3).
+ void addsubps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstAddSubPS, &dst, &src); }
+ //! @brief Packed SP-FP Add/Subtract (SSE3).
+ void addsubps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstAddSubPS, &dst, &src); }
+
+ //! @brief Store Integer with Truncation (SSE3).
+ void fisttp(const Mem& dst)
+ { _emitInstruction(kX86InstFISttP, &dst); }
+
+ //! @brief Packed DP-FP Horizontal Add (SSE3).
+ void haddpd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstHAddPD, &dst, &src); }
+ //! @brief Packed DP-FP Horizontal Add (SSE3).
+ void haddpd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstHAddPD, &dst, &src); }
+
+ //! @brief Packed SP-FP Horizontal Add (SSE3).
+ void haddps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstHAddPS, &dst, &src); }
+ //! @brief Packed SP-FP Horizontal Add (SSE3).
+ void haddps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstHAddPS, &dst, &src); }
+
+ //! @brief Packed DP-FP Horizontal Subtract (SSE3).
+ void hsubpd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstHSubPD, &dst, &src); }
+ //! @brief Packed DP-FP Horizontal Subtract (SSE3).
+ void hsubpd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstHSubPD, &dst, &src); }
+
+ //! @brief Packed SP-FP Horizontal Subtract (SSE3).
+ void hsubps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstHSubPS, &dst, &src); }
+ //! @brief Packed SP-FP Horizontal Subtract (SSE3).
+ void hsubps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstHSubPS, &dst, &src); }
+
+ //! @brief Load Unaligned Integer 128 Bits (SSE3).
+ void lddqu(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstLdDQU, &dst, &src); }
+
+ //! @brief Set Up Monitor Address (SSE3).
+ void monitor()
+ { _emitInstruction(kX86InstMonitor); }
+
+ //! @brief Move One DP-FP and Duplicate (SSE3).
+ void movddup(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovDDup, &dst, &src); }
+ //! @brief Move One DP-FP and Duplicate (SSE3).
+ void movddup(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovDDup, &dst, &src); }
+
+ //! @brief Move Packed SP-FP High and Duplicate (SSE3).
+ void movshdup(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovSHDup, &dst, &src); }
+ //! @brief Move Packed SP-FP High and Duplicate (SSE3).
+ void movshdup(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovSHDup, &dst, &src); }
+
+ //! @brief Move Packed SP-FP Low and Duplicate (SSE3).
+ void movsldup(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstMovSLDup, &dst, &src); }
+ //! @brief Move Packed SP-FP Low and Duplicate (SSE3).
+ void movsldup(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovSLDup, &dst, &src); }
+
+ //! @brief Monitor Wait (SSE3).
+ void mwait()
+ { _emitInstruction(kX86InstMWait); }
+
+ // --------------------------------------------------------------------------
+ // [SSSE3]
+ // --------------------------------------------------------------------------
+
+ //! @brief Packed SIGN (SSSE3).
+ void psignb(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSignB, &dst, &src); }
+ //! @brief Packed SIGN (SSSE3).
+ void psignb(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSignB, &dst, &src); }
+
+ //! @brief Packed SIGN (SSSE3).
+ void psignb(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPSignB, &dst, &src); }
+ //! @brief Packed SIGN (SSSE3).
+ void psignb(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSignB, &dst, &src); }
+
+ //! @brief Packed SIGN (SSSE3).
+ void psignw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSignW, &dst, &src); }
+ //! @brief Packed SIGN (SSSE3).
+ void psignw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSignW, &dst, &src); }
+
+ //! @brief Packed SIGN (SSSE3).
+ void psignw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPSignW, &dst, &src); }
+ //! @brief Packed SIGN (SSSE3).
+ void psignw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSignW, &dst, &src); }
+
+ //! @brief Packed SIGN (SSSE3).
+ void psignd(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPSignD, &dst, &src); }
+ //! @brief Packed SIGN (SSSE3).
+ void psignd(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSignD, &dst, &src); }
+
+ //! @brief Packed SIGN (SSSE3).
+ void psignd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPSignD, &dst, &src); }
+ //! @brief Packed SIGN (SSSE3).
+ void psignd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSignD, &dst, &src); }
+
+ //! @brief Packed Horizontal Add (SSSE3).
+ void phaddw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPHAddW, &dst, &src); }
+ //! @brief Packed Horizontal Add (SSSE3).
+ void phaddw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHAddW, &dst, &src); }
+
+ //! @brief Packed Horizontal Add (SSSE3).
+ void phaddw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPHAddW, &dst, &src); }
+ //! @brief Packed Horizontal Add (SSSE3).
+ void phaddw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHAddW, &dst, &src); }
+
+ //! @brief Packed Horizontal Add (SSSE3).
+ void phaddd(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPHAddD, &dst, &src); }
+ //! @brief Packed Horizontal Add (SSSE3).
+ void phaddd(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHAddD, &dst, &src); }
+
+ //! @brief Packed Horizontal Add (SSSE3).
+ void phaddd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPHAddD, &dst, &src); }
+ //! @brief Packed Horizontal Add (SSSE3).
+ void phaddd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHAddD, &dst, &src); }
+
+ //! @brief Packed Horizontal Add and Saturate (SSSE3).
+ void phaddsw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPHAddSW, &dst, &src); }
+ //! @brief Packed Horizontal Add and Saturate (SSSE3).
+ void phaddsw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHAddSW, &dst, &src); }
+
+ //! @brief Packed Horizontal Add and Saturate (SSSE3).
+ void phaddsw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPHAddSW, &dst, &src); }
+ //! @brief Packed Horizontal Add and Saturate (SSSE3).
+ void phaddsw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHAddSW, &dst, &src); }
+
+ //! @brief Packed Horizontal Subtract (SSSE3).
+ void phsubw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPHSubW, &dst, &src); }
+ //! @brief Packed Horizontal Subtract (SSSE3).
+ void phsubw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHSubW, &dst, &src); }
+
+ //! @brief Packed Horizontal Subtract (SSSE3).
+ void phsubw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPHSubW, &dst, &src); }
+ //! @brief Packed Horizontal Subtract (SSSE3).
+ void phsubw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHSubW, &dst, &src); }
+
+ //! @brief Packed Horizontal Subtract (SSSE3).
+ void phsubd(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPHSubD, &dst, &src); }
+ //! @brief Packed Horizontal Subtract (SSSE3).
+ void phsubd(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHSubD, &dst, &src); }
+
+ //! @brief Packed Horizontal Subtract (SSSE3).
+ void phsubd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPHSubD, &dst, &src); }
+ //! @brief Packed Horizontal Subtract (SSSE3).
+ void phsubd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHSubD, &dst, &src); }
+
+ //! @brief Packed Horizontal Subtract and Saturate (SSSE3).
+ void phsubsw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPHSubSW, &dst, &src); }
+ //! @brief Packed Horizontal Subtract and Saturate (SSSE3).
+ void phsubsw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHSubSW, &dst, &src); }
+
+ //! @brief Packed Horizontal Subtract and Saturate (SSSE3).
+ void phsubsw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPHSubSW, &dst, &src); }
+ //! @brief Packed Horizontal Subtract and Saturate (SSSE3).
+ void phsubsw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHSubSW, &dst, &src); }
+
+ //! @brief Multiply and Add Packed Signed and Unsigned Bytes (SSSE3).
+ void pmaddubsw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPMAddUBSW, &dst, &src); }
+ //! @brief Multiply and Add Packed Signed and Unsigned Bytes (SSSE3).
+ void pmaddubsw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMAddUBSW, &dst, &src); }
+
+ //! @brief Multiply and Add Packed Signed and Unsigned Bytes (SSSE3).
+ void pmaddubsw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMAddUBSW, &dst, &src); }
+ //! @brief Multiply and Add Packed Signed and Unsigned Bytes (SSSE3).
+ void pmaddubsw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMAddUBSW, &dst, &src); }
+
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsb(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPAbsB, &dst, &src); }
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsb(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAbsB, &dst, &src); }
+
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsb(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPAbsB, &dst, &src); }
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsb(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAbsB, &dst, &src); }
+
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPAbsW, &dst, &src); }
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAbsW, &dst, &src); }
+
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPAbsW, &dst, &src); }
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAbsW, &dst, &src); }
+
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsd(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPAbsD, &dst, &src); }
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsd(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAbsD, &dst, &src); }
+
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPAbsD, &dst, &src); }
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAbsD, &dst, &src); }
+
+ //! @brief Packed Multiply High with Round and Scale (SSSE3).
+ void pmulhrsw(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPMulHRSW, &dst, &src); }
+ //! @brief Packed Multiply High with Round and Scale (SSSE3).
+ void pmulhrsw(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulHRSW, &dst, &src); }
+
+ //! @brief Packed Multiply High with Round and Scale (SSSE3).
+ void pmulhrsw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMulHRSW, &dst, &src); }
+ //! @brief Packed Multiply High with Round and Scale (SSSE3).
+ void pmulhrsw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulHRSW, &dst, &src); }
+
+ //! @brief Packed Shuffle Bytes (SSSE3).
+ void pshufb(const MmReg& dst, const MmReg& src)
+ { _emitInstruction(kX86InstPShufB, &dst, &src); }
+ //! @brief Packed Shuffle Bytes (SSSE3).
+ void pshufb(const MmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPShufB, &dst, &src); }
+
+ //! @brief Packed Shuffle Bytes (SSSE3).
+ void pshufb(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPShufB, &dst, &src); }
+ //! @brief Packed Shuffle Bytes (SSSE3).
+ void pshufb(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPShufB, &dst, &src); }
+
+ //! @brief Packed Shuffle Bytes (SSSE3).
+ void palignr(const MmReg& dst, const MmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPAlignR, &dst, &src, &imm8); }
+ //! @brief Packed Shuffle Bytes (SSSE3).
+ void palignr(const MmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPAlignR, &dst, &src, &imm8); }
+
+ //! @brief Packed Shuffle Bytes (SSSE3).
+ void palignr(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPAlignR, &dst, &src, &imm8); }
+ //! @brief Packed Shuffle Bytes (SSSE3).
+ void palignr(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPAlignR, &dst, &src, &imm8); }
+
+ // --------------------------------------------------------------------------
+ // [SSE4.1]
+ // --------------------------------------------------------------------------
+
+ //! @brief Blend Packed DP-FP Values (SSE4.1).
+ void blendpd(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstBlendPD, &dst, &src, &imm8); }
+ //! @brief Blend Packed DP-FP Values (SSE4.1).
+ void blendpd(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstBlendPD, &dst, &src, &imm8); }
+
+ //! @brief Blend Packed SP-FP Values (SSE4.1).
+ void blendps(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstBlendPS, &dst, &src, &imm8); }
+ //! @brief Blend Packed SP-FP Values (SSE4.1).
+ void blendps(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstBlendPS, &dst, &src, &imm8); }
+
+ //! @brief Variable Blend Packed DP-FP Values (SSE4.1).
+ void blendvpd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstBlendVPD, &dst, &src); }
+ //! @brief Variable Blend Packed DP-FP Values (SSE4.1).
+ void blendvpd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstBlendVPD, &dst, &src); }
+
+ //! @brief Variable Blend Packed SP-FP Values (SSE4.1).
+ void blendvps(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstBlendVPS, &dst, &src); }
+ //! @brief Variable Blend Packed SP-FP Values (SSE4.1).
+ void blendvps(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstBlendVPS, &dst, &src); }
+
+ //! @brief Dot Product of Packed DP-FP Values (SSE4.1).
+ void dppd(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstDpPD, &dst, &src, &imm8); }
+ //! @brief Dot Product of Packed DP-FP Values (SSE4.1).
+ void dppd(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstDpPD, &dst, &src, &imm8); }
+
+ //! @brief Dot Product of Packed SP-FP Values (SSE4.1).
+ void dpps(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstDpPS, &dst, &src, &imm8); }
+ //! @brief Dot Product of Packed SP-FP Values (SSE4.1).
+ void dpps(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstDpPS, &dst, &src, &imm8); }
+
+ //! @brief Extract Packed SP-FP Value (SSE4.1).
+ void extractps(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstExtractPS, &dst, &src, &imm8); }
+ //! @brief Extract Packed SP-FP Value (SSE4.1).
+ void extractps(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstExtractPS, &dst, &src, &imm8); }
+
+ //! @brief Load Double Quadword Non-Temporal Aligned Hint (SSE4.1).
+ void movntdqa(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovNTDQA, &dst, &src); }
+
+ //! @brief Compute Multiple Packed Sums of Absolute Difference (SSE4.1).
+ void mpsadbw(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstMPSADBW, &dst, &src, &imm8); }
+ //! @brief Compute Multiple Packed Sums of Absolute Difference (SSE4.1).
+ void mpsadbw(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstMPSADBW, &dst, &src, &imm8); }
+
+ //! @brief Pack with Unsigned Saturation (SSE4.1).
+ void packusdw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPackUSDW, &dst, &src); }
+ //! @brief Pack with Unsigned Saturation (SSE4.1).
+ void packusdw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPackUSDW, &dst, &src); }
+
+ //! @brief Variable Blend Packed Bytes (SSE4.1).
+ void pblendvb(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPBlendVB, &dst, &src); }
+ //! @brief Variable Blend Packed Bytes (SSE4.1).
+ void pblendvb(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPBlendVB, &dst, &src); }
+
+ //! @brief Blend Packed Words (SSE4.1).
+ void pblendw(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPBlendW, &dst, &src, &imm8); }
+ //! @brief Blend Packed Words (SSE4.1).
+ void pblendw(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPBlendW, &dst, &src, &imm8); }
+
+ //! @brief Compare Packed Qword Data for Equal (SSE4.1).
+ void pcmpeqq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPCmpEqQ, &dst, &src); }
+ //! @brief Compare Packed Qword Data for Equal (SSE4.1).
+ void pcmpeqq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpEqQ, &dst, &src); }
+
+ //! @brief Extract Byte (SSE4.1).
+ void pextrb(const GpReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPExtrB, &dst, &src, &imm8); }
+ //! @brief Extract Byte (SSE4.1).
+ void pextrb(const Mem& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPExtrB, &dst, &src, &imm8); }
+
+ //! @brief Extract Dword (SSE4.1).
+ void pextrd(const GpReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPExtrD, &dst, &src, &imm8); }
+ //! @brief Extract Dword (SSE4.1).
+ void pextrd(const Mem& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPExtrD, &dst, &src, &imm8); }
+
+ //! @brief Extract Dword (SSE4.1).
+ void pextrq(const GpReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPExtrQ, &dst, &src, &imm8); }
+ //! @brief Extract Dword (SSE4.1).
+ void pextrq(const Mem& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPExtrQ, &dst, &src, &imm8); }
+
+ //! @brief Extract Word (SSE4.1).
+ void pextrw(const GpReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPExtrW, &dst, &src, &imm8); }
+ //! @brief Extract Word (SSE4.1).
+ void pextrw(const Mem& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPExtrW, &dst, &src, &imm8); }
+
+ //! @brief Packed Horizontal Word Minimum (SSE4.1).
+ void phminposuw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPHMinPOSUW, &dst, &src); }
+ //! @brief Packed Horizontal Word Minimum (SSE4.1).
+ void phminposuw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHMinPOSUW, &dst, &src); }
+
+ //! @brief Insert Byte (SSE4.1).
+ void pinsrb(const XmmReg& dst, const GpReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPInsRB, &dst, &src, &imm8); }
+ //! @brief Insert Byte (SSE4.1).
+ void pinsrb(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPInsRB, &dst, &src, &imm8); }
+
+ //! @brief Insert Dword (SSE4.1).
+ void pinsrd(const XmmReg& dst, const GpReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPInsRD, &dst, &src, &imm8); }
+ //! @brief Insert Dword (SSE4.1).
+ void pinsrd(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPInsRD, &dst, &src, &imm8); }
+
+ //! @brief Insert Dword (SSE4.1).
+ void pinsrq(const XmmReg& dst, const GpReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPInsRQ, &dst, &src, &imm8); }
+ //! @brief Insert Dword (SSE4.1).
+ void pinsrq(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPInsRQ, &dst, &src, &imm8); }
+
+ //! @brief Insert Word (SSE2).
+ void pinsrw(const XmmReg& dst, const GpReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPInsRW, &dst, &src, &imm8); }
+ //! @brief Insert Word (SSE2).
+ void pinsrw(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPInsRW, &dst, &src, &imm8); }
+
+ //! @brief Maximum of Packed Word Integers (SSE4.1).
+ void pmaxuw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMaxUW, &dst, &src); }
+ //! @brief Maximum of Packed Word Integers (SSE4.1).
+ void pmaxuw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMaxUW, &dst, &src); }
+
+ //! @brief Maximum of Packed Signed Byte Integers (SSE4.1).
+ void pmaxsb(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMaxSB, &dst, &src); }
+ //! @brief Maximum of Packed Signed Byte Integers (SSE4.1).
+ void pmaxsb(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMaxSB, &dst, &src); }
+
+ //! @brief Maximum of Packed Signed Dword Integers (SSE4.1).
+ void pmaxsd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMaxSD, &dst, &src); }
+ //! @brief Maximum of Packed Signed Dword Integers (SSE4.1).
+ void pmaxsd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMaxSD, &dst, &src); }
+
+ //! @brief Maximum of Packed Unsigned Dword Integers (SSE4.1).
+ void pmaxud(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMaxUD, &dst, &src); }
+ //! @brief Maximum of Packed Unsigned Dword Integers (SSE4.1).
+ void pmaxud(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMaxUD, &dst, &src); }
+
+ //! @brief Minimum of Packed Signed Byte Integers (SSE4.1).
+ void pminsb(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMinSB, &dst, &src); }
+ //! @brief Minimum of Packed Signed Byte Integers (SSE4.1).
+ void pminsb(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMinSB, &dst, &src); }
+
+ //! @brief Minimum of Packed Word Integers (SSE4.1).
+ void pminuw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMinUW, &dst, &src); }
+ //! @brief Minimum of Packed Word Integers (SSE4.1).
+ void pminuw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMinUW, &dst, &src); }
+
+ //! @brief Minimum of Packed Dword Integers (SSE4.1).
+ void pminud(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMinUD, &dst, &src); }
+ //! @brief Minimum of Packed Dword Integers (SSE4.1).
+ void pminud(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMinUD, &dst, &src); }
+
+ //! @brief Minimum of Packed Dword Integers (SSE4.1).
+ void pminsd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMinSD, &dst, &src); }
+ //! @brief Minimum of Packed Dword Integers (SSE4.1).
+ void pminsd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMinSD, &dst, &src); }
+
+ //! @brief Packed Move with Sign Extend (SSE4.1).
+ void pmovsxbw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMovSXBW, &dst, &src); }
+ //! @brief Packed Move with Sign Extend (SSE4.1).
+ void pmovsxbw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovSXBW, &dst, &src); }
+
+ //! @brief Packed Move with Sign Extend (SSE4.1).
+ void pmovsxbd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMovSXBD, &dst, &src); }
+ //! @brief Packed Move with Sign Extend (SSE4.1).
+ void pmovsxbd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovSXBD, &dst, &src); }
+
+ //! @brief Packed Move with Sign Extend (SSE4.1).
+ void pmovsxbq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMovSXBQ, &dst, &src); }
+ //! @brief Packed Move with Sign Extend (SSE4.1).
+ void pmovsxbq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovSXBQ, &dst, &src); }
+
+ //! @brief Packed Move with Sign Extend (SSE4.1).
+ void pmovsxwd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMovSXWD, &dst, &src); }
+ //! @brief Packed Move with Sign Extend (SSE4.1).
+ void pmovsxwd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovSXWD, &dst, &src); }
+
+ //! @brief (SSE4.1).
+ void pmovsxwq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMovSXWQ, &dst, &src); }
+ //! @brief (SSE4.1).
+ void pmovsxwq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovSXWQ, &dst, &src); }
+
+ //! @brief (SSE4.1).
+ void pmovsxdq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMovSXDQ, &dst, &src); }
+ //! @brief (SSE4.1).
+ void pmovsxdq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovSXDQ, &dst, &src); }
+
+ //! @brief Packed Move with Zero Extend (SSE4.1).
+ void pmovzxbw(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMovZXBW, &dst, &src); }
+ //! @brief Packed Move with Zero Extend (SSE4.1).
+ void pmovzxbw(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovZXBW, &dst, &src); }
+
+ //! @brief Packed Move with Zero Extend (SSE4.1).
+ void pmovzxbd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMovZXBD, &dst, &src); }
+ //! @brief Packed Move with Zero Extend (SSE4.1).
+ void pmovzxbd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovZXBD, &dst, &src); }
+
+ //! @brief Packed Move with Zero Extend (SSE4.1).
+ void pmovzxbq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMovZXBQ, &dst, &src); }
+ //! @brief Packed Move with Zero Extend (SSE4.1).
+ void pmovzxbq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovZXBQ, &dst, &src); }
+
+ //! @brief Packed Move with Zero Extend (SSE4.1).
+ void pmovzxwd(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMovZXWD, &dst, &src); }
+ //! @brief Packed Move with Zero Extend (SSE4.1).
+ void pmovzxwd(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovZXWD, &dst, &src); }
+
+ //! @brief (SSE4.1).
+ void pmovzxwq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMovZXWQ, &dst, &src); }
+ //! @brief (SSE4.1).
+ void pmovzxwq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovZXWQ, &dst, &src); }
+
+ //! @brief (SSE4.1).
+ void pmovzxdq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMovZXDQ, &dst, &src); }
+ //! @brief (SSE4.1).
+ void pmovzxdq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovZXDQ, &dst, &src); }
+
+ //! @brief Multiply Packed Signed Dword Integers (SSE4.1).
+ void pmuldq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMulDQ, &dst, &src); }
+ //! @brief Multiply Packed Signed Dword Integers (SSE4.1).
+ void pmuldq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulDQ, &dst, &src); }
+
+ //! @brief Multiply Packed Signed Integers and Store Low Result (SSE4.1).
+ void pmulld(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPMulLD, &dst, &src); }
+ //! @brief Multiply Packed Signed Integers and Store Low Result (SSE4.1).
+ void pmulld(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulLD, &dst, &src); }
+
+ //! @brief Logical Compare (SSE4.1).
+ void ptest(const XmmReg& op1, const XmmReg& op2)
+ { _emitInstruction(kX86InstPTest, &op1, &op2); }
+ //! @brief Logical Compare (SSE4.1).
+ void ptest(const XmmReg& op1, const Mem& op2)
+ { _emitInstruction(kX86InstPTest, &op1, &op2); }
+
+ //! Round Packed SP-FP Values @brief (SSE4.1).
+ void roundps(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstRoundPS, &dst, &src, &imm8); }
+ //! Round Packed SP-FP Values @brief (SSE4.1).
+ void roundps(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstRoundPS, &dst, &src, &imm8); }
+
+ //! @brief Round Scalar SP-FP Values (SSE4.1).
+ void roundss(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstRoundSS, &dst, &src, &imm8); }
+ //! @brief Round Scalar SP-FP Values (SSE4.1).
+ void roundss(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstRoundSS, &dst, &src, &imm8); }
+
+ //! @brief Round Packed DP-FP Values (SSE4.1).
+ void roundpd(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstRoundPD, &dst, &src, &imm8); }
+ //! @brief Round Packed DP-FP Values (SSE4.1).
+ void roundpd(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstRoundPD, &dst, &src, &imm8); }
+
+ //! @brief Round Scalar DP-FP Values (SSE4.1).
+ void roundsd(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstRoundSD, &dst, &src, &imm8); }
+ //! @brief Round Scalar DP-FP Values (SSE4.1).
+ void roundsd(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstRoundSD, &dst, &src, &imm8); }
+
+ // --------------------------------------------------------------------------
+ // [SSE4.2]
+ // --------------------------------------------------------------------------
+
+ //! @brief Accumulate CRC32 Value (polynomial 0x11EDC6F41) (SSE4.2).
+ void crc32(const GpReg& dst, const GpReg& src)
+ {
+ ASMJIT_ASSERT(dst.isRegType(kX86RegTypeGpd) || dst.isRegType(kX86RegTypeGpq));
+ _emitInstruction(kX86InstCrc32, &dst, &src);
+ }
+ //! @brief Accumulate CRC32 Value (polynomial 0x11EDC6F41) (SSE4.2).
+ void crc32(const GpReg& dst, const Mem& src)
+ {
+ ASMJIT_ASSERT(dst.isRegType(kX86RegTypeGpd) || dst.isRegType(kX86RegTypeGpq));
+ _emitInstruction(kX86InstCrc32, &dst, &src);
+ }
+
+ //! @brief Packed Compare Explicit Length Strings, Return Index (SSE4.2).
+ void pcmpestri(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPCmpEStrI, &dst, &src, &imm8); }
+ //! @brief Packed Compare Explicit Length Strings, Return Index (SSE4.2).
+ void pcmpestri(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPCmpEStrI, &dst, &src, &imm8); }
+
+ //! @brief Packed Compare Explicit Length Strings, Return Mask (SSE4.2).
+ void pcmpestrm(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPCmpEStrM, &dst, &src, &imm8); }
+ //! @brief Packed Compare Explicit Length Strings, Return Mask (SSE4.2).
+ void pcmpestrm(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPCmpEStrM, &dst, &src, &imm8); }
+
+ //! @brief Packed Compare Implicit Length Strings, Return Index (SSE4.2).
+ void pcmpistri(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPCmpIStrI, &dst, &src, &imm8); }
+ //! @brief Packed Compare Implicit Length Strings, Return Index (SSE4.2).
+ void pcmpistri(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPCmpIStrI, &dst, &src, &imm8); }
+
+ //! @brief Packed Compare Implicit Length Strings, Return Mask (SSE4.2).
+ void pcmpistrm(const XmmReg& dst, const XmmReg& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPCmpIStrM, &dst, &src, &imm8); }
+ //! @brief Packed Compare Implicit Length Strings, Return Mask (SSE4.2).
+ void pcmpistrm(const XmmReg& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPCmpIStrM, &dst, &src, &imm8); }
+
+ //! @brief Compare Packed Data for Greater Than (SSE4.2).
+ void pcmpgtq(const XmmReg& dst, const XmmReg& src)
+ { _emitInstruction(kX86InstPCmpGtQ, &dst, &src); }
+ //! @brief Compare Packed Data for Greater Than (SSE4.2).
+ void pcmpgtq(const XmmReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpGtQ, &dst, &src); }
+
+ //! @brief Return the Count of Number of Bits Set to 1 (SSE4.2).
+ void popcnt(const GpReg& dst, const GpReg& src)
+ {
+ ASMJIT_ASSERT(!dst.isGpb());
+ ASMJIT_ASSERT(src.getRegType() == dst.getRegType());
+ _emitInstruction(kX86InstPopCnt, &dst, &src);
+ }
+ //! @brief Return the Count of Number of Bits Set to 1 (SSE4.2).
+ void popcnt(const GpReg& dst, const Mem& src)
+ {
+ ASMJIT_ASSERT(!dst.isGpb());
+ _emitInstruction(kX86InstPopCnt, &dst, &src);
+ }
+
+ // -------------------------------------------------------------------------
+ // [AMD only]
+ // -------------------------------------------------------------------------
+
+ //! @brief Prefetch (3dNow - Amd).
+ //!
+ //! Loads the entire 64-byte aligned memory sequence containing the
+ //! specified memory address into the L1 data cache. The position of
+ //! the specified memory address within the 64-byte cache line is
+ //! irrelevant. If a cache hit occurs, or if a memory fault is detected,
+ //! no bus cycle is initiated and the instruction is treated as a NOP.
+ void amd_prefetch(const Mem& mem)
+ { _emitInstruction(kX86InstAmdPrefetch, &mem); }
+
+ //! @brief Prefetch and set cache to modified (3dNow - Amd).
+ //!
+ //! The PREFETCHW instruction loads the prefetched line and sets the
+ //! cache-line state to Modified, in anticipation of subsequent data
+ //! writes to the line. The PREFETCH instruction, by contrast, typically
+ //! sets the cache-line state to Exclusive (depending on the hardware
+ //! implementation).
+ void amd_prefetchw(const Mem& mem)
+ { _emitInstruction(kX86InstAmdPrefetchW, &mem); }
+
+ // -------------------------------------------------------------------------
+ // [Intel only]
+ // -------------------------------------------------------------------------
+
+ //! @brief Move Data After Swapping Bytes (SSE3 - Intel Atom).
+ void movbe(const GpReg& dst, const Mem& src)
+ {
+ ASMJIT_ASSERT(!dst.isGpb());
+ _emitInstruction(kX86InstMovBE, &dst, &src);
+ }
+
+ //! @brief Move Data After Swapping Bytes (SSE3 - Intel Atom).
+ void movbe(const Mem& dst, const GpReg& src)
+ {
+ ASMJIT_ASSERT(!src.isGpb());
+ _emitInstruction(kX86InstMovBE, &dst, &src);
+ }
+
+ // -------------------------------------------------------------------------
+ // [Emit Options]
+ // -------------------------------------------------------------------------
+
+ //! @brief Assert LOCK# Signal Prefix.
+ //!
+ //! This instruction causes the processor's LOCK# signal to be asserted
+ //! during execution of the accompanying instruction (turns the
+ //! instruction into an atomic instruction). In a multiprocessor environment,
+ //! the LOCK# signal insures that the processor has exclusive use of any shared
+ //! memory while the signal is asserted.
+ //!
+ //! The LOCK prefix can be prepended only to the following instructions and
+ //! to those forms of the instructions that use a memory operand: ADD, ADC,
+ //! AND, BTC, BTR, BTS, CMPXCHG, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD,
+ //! and XCHG. An undefined opcode exception will be generated if the LOCK
+ //! prefix is used with any other instruction. The XCHG instruction always
+ //! asserts the LOCK# signal regardless of the presence or absence of the LOCK
+ //! prefix.
+ //!
+ //! @sa @c kX86EmitOptionLock.
+ void lock()
+ { _emitOptions |= kX86EmitOptionLock; }
+
+ //! @brief Force REX prefix to be emitted.
+ //!
+ //! This option should be used carefully, because there are unencodable
+ //! combinations. If you want to access ah, bh, ch or dh registers then you
+ //! can't emit REX prefix and it will cause an illegal instruction error.
+ //!
+ //! @note REX prefix is only valid for X64/AMD64 platform.
+ //!
+ //! @sa @c kX86EmitOptionRex.
+ void rex()
+ { _emitOptions |= kX86EmitOptionRex; }
+};
+
+//! @}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_X86_X86ASSEMBLER_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86/x86compiler.cpp
@@ -1,1 +1,878 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/intutil.h"
+#include "../core/stringutil.h"
+
+#include "../x86/x86assembler.h"
+#include "../x86/x86compiler.h"
+#include "../x86/x86compilercontext.h"
+#include "../x86/x86compilerfunc.h"
+#include "../x86/x86compileritem.h"
+#include "../x86/x86util.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit {
+
+// ============================================================================
+// [AsmJit::CompilerUtil]
+// ============================================================================
+
+bool CompilerUtil::isStack16ByteAligned()
+{
+ // Stack is always aligned to 16-bytes when using 64-bit OS.
+ bool result = (sizeof(uintptr_t) == 8);
+
+ // Modern Linux, APPLE and UNIX guarantees stack alignment to 16 bytes by
+ // default. I'm really not sure about all UNIX operating systems, because
+ // 16-byte alignment is an addition to an older specification.
+#if (defined(__linux__) || \
+ defined(__linux) || \
+ defined(linux) || \
+ defined(__unix__) || \
+ defined(__FreeBSD__) || \
+ defined(__NetBSD__) || \
+ defined(__OpenBSD__) || \
+ defined(__DARWIN__) || \
+ defined(__APPLE__) )
+ result = true;
+#endif // __linux__
+
+ return result;
+}
+
+// ============================================================================
+// [AsmJit::X86Compiler - Construction / Destruction]
+// ============================================================================
+
+X86Compiler::X86Compiler(Context* context) :
+ Compiler(context)
+{
+ _properties |= IntUtil::maskFromIndex(kX86PropertyOptimizedAlign);
+}
+
+X86Compiler::~X86Compiler()
+{
+}
+
+// ============================================================================
+// [AsmJit::Compiler - Function Builder]
+// ============================================================================
+
+X86CompilerFuncDecl* X86Compiler::newFunc_(uint32_t convention, uint32_t returnType, const uint32_t* arguments, uint32_t argumentsCount)
+{
+ ASMJIT_ASSERT(!_func);
+
+ X86CompilerFuncDecl* func = Compiler_newItem<X86CompilerFuncDecl>(this);
+
+ _func = func;
+ _varNameId = 0;
+
+ func->setPrototype(convention, returnType, arguments, argumentsCount);
+ addItem(func);
+
+ bind(func->_entryLabel);
+ func->_createVariables();
+
+ return func;
+}
+
+X86CompilerFuncDecl* X86Compiler::endFunc()
+{
+ X86CompilerFuncDecl* func = getFunc();
+ ASMJIT_ASSERT(!!func);
+
+ bind(func->_exitLabel);
+ addItem(func->_end);
+
+ func->setFuncFlag(kFuncFlagIsFinished);
+ _func = nullptr;
+
+ return func;
+}
+
+// ============================================================================
+// [AsmJit::Compiler - EmitInstruction]
+// ============================================================================
+
+static inline X86CompilerInst* X86Compiler_newInstruction(X86Compiler* self, uint32_t code, Operand* opData, uint32_t opCount)
+{
+ if (code >= _kX86InstJBegin && code <= _kX86InstJEnd)
+ {
+ void* p = self->_zoneMemory.alloc(sizeof(X86CompilerJmpInst));
+ return new(p) X86CompilerJmpInst(self, code, opData, opCount);
+ }
+ else
+ {
+ void* p = self->_zoneMemory.alloc(sizeof(X86CompilerInst) + opCount * sizeof(Operand));
+ return new(p) X86CompilerInst(self, code, opData, opCount);
+ }
+}
+
+void X86Compiler::_emitInstruction(uint32_t code)
+{
+ X86CompilerInst* inst = X86Compiler_newInstruction(this, code, nullptr, 0);
+
+ if (!inst)
+ {
+ setError(kErrorNoHeapMemory);
+ return;
+ }
+
+ addItem(inst);
+
+ if (_cc)
+ {
+ inst->_offset = _cc->_currentOffset;
+ inst->prepare(*_cc);
+ }
+}
+
+void X86Compiler::_emitInstruction(uint32_t code, const Operand* o0)
+{
+ Operand* operands = reinterpret_cast<Operand*>(_zoneMemory.alloc(1 * sizeof(Operand)));
+
+ if (!operands)
+ {
+ setError(kErrorNoHeapMemory);
+ return;
+ }
+
+ operands[0] = *o0;
+ X86CompilerInst* inst = X86Compiler_newInstruction(this, code, operands, 1);
+
+ if (!inst)
+ {
+ setError(kErrorNoHeapMemory);
+ return;
+ }
+
+ addItem(inst);
+
+ if (_cc)
+ {
+ inst->_offset = _cc->_currentOffset;
+ inst->prepare(*_cc);
+ }
+}
+
+void X86Compiler::_emitInstruction(uint32_t code, const Operand* o0, const Operand* o1)
+{
+ Operand* operands = reinterpret_cast<Operand*>(_zoneMemory.alloc(2 * sizeof(Operand)));
+
+ if (!operands)
+ {
+ setError(kErrorNoHeapMemory);
+ return;
+ }
+
+ operands[0] = *o0;
+ operands[1] = *o1;
+ X86CompilerInst* inst = X86Compiler_newInstruction(this, code, operands, 2);
+
+ if (!inst)
+ {
+ setError(kErrorNoHeapMemory);
+ return;
+ }
+
+ addItem(inst);
+
+ if (_cc)
+ {
+ inst->_offset = _cc->_currentOffset;
+ inst->prepare(*_cc);
+ }
+}
+
+void X86Compiler::_emitInstruction(uint32_t code, const Operand* o0, const Operand* o1, const Operand* o2)
+{
+ Operand* operands = reinterpret_cast<Operand*>(_zoneMemory.alloc(3 * sizeof(Operand)));
+
+ if (!operands)
+ {
+ setError(kErrorNoHeapMemory);
+ return;
+ }
+
+ operands[0] = *o0;
+ operands[1] = *o1;
+ operands[2] = *o2;
+ X86CompilerInst* inst = X86Compiler_newInstruction(this, code, operands, 3);
+
+ if (!inst)
+ {
+ setError(kErrorNoHeapMemory);
+ return;
+ }
+
+ addItem(inst);
+
+ if (_cc)
+ {
+ inst->_offset = _cc->_currentOffset;
+ inst->prepare(*_cc);
+ }
+}
+
+void X86Compiler::_emitInstruction(uint32_t code, const Operand* o0, const Operand* o1, const Operand* o2, const Operand* o3)
+{
+ Operand* operands = reinterpret_cast<Operand*>(_zoneMemory.alloc(4 * sizeof(Operand)));
+
+ if (!operands)
+ {
+ setError(kErrorNoHeapMemory);
+ return;
+ }
+
+ operands[0] = *o0;
+ operands[1] = *o1;
+ operands[2] = *o2;
+ operands[3] = *o3;
+ X86CompilerInst* inst = X86Compiler_newInstruction(this, code, operands, 4);
+
+ if (!inst)
+ {
+ setError(kErrorNoHeapMemory);
+ return;
+ }
+
+ addItem(inst);
+
+ if (_cc)
+ {
+ inst->_offset = _cc->_currentOffset;
+ inst->prepare(*_cc);
+ }
+}
+
+void X86Compiler::_emitInstruction(uint32_t code, const Operand* o0, const Operand* o1, const Operand* o2, const Operand* o3, const Operand* o4)
+{
+ Operand* operands = reinterpret_cast<Operand*>(_zoneMemory.alloc(5 * sizeof(Operand)));
+
+ if (!operands)
+ {
+ setError(kErrorNoHeapMemory);
+ return;
+ }
+
+ operands[0] = *o0;
+ operands[1] = *o1;
+ operands[2] = *o2;
+ operands[3] = *o3;
+ operands[4] = *o4;
+ X86CompilerInst* inst = X86Compiler_newInstruction(this, code, operands, 5);
+
+ if (!inst)
+ {
+ setError(kErrorNoHeapMemory);
+ return;
+ }
+
+ addItem(inst);
+
+ if (_cc)
+ {
+ inst->_offset = _cc->_currentOffset;
+ inst->prepare(*_cc);
+ }
+}
+
+void X86Compiler::_emitJcc(uint32_t code, const Label* label, uint32_t hint)
+{
+ if (hint == kCondHintNone)
+ {
+ _emitInstruction(code, label);
+ }
+ else
+ {
+ Imm imm(hint);
+ _emitInstruction(code, label, &imm);
+ }
+}
+
+X86CompilerFuncCall* X86Compiler::_emitCall(const Operand* o0)
+{
+ X86CompilerFuncDecl* func = getFunc();
+
+ if (!func)
+ {
+ setError(kErrorNoFunction);
+ return nullptr;
+ }
+
+ X86CompilerFuncCall* call = Compiler_newItem<X86CompilerFuncCall>(this, func, o0);
+ if (!call)
+ {
+ setError(kErrorNoHeapMemory);
+ return nullptr;
+ }
+
+ addItem(call);
+ return call;
+}
+
+void X86Compiler::_emitReturn(const Operand* first, const Operand* second)
+{
+ X86CompilerFuncDecl* func = getFunc();
+
+ if (!func)
+ {
+ setError(kErrorNoFunction);
+ return;
+ }
+
+ X86CompilerFuncRet* ret = Compiler_newItem<X86CompilerFuncRet>(this, func, first, second);
+
+ if (!ret)
+ {
+ setError(kErrorNoHeapMemory);
+ return;
+ }
+
+ addItem(ret);
+}
+
+// ============================================================================
+// [AsmJit::Compiler - Align]
+// ============================================================================
+
+void X86Compiler::align(uint32_t m)
+{
+ addItem(Compiler_newItem<X86CompilerAlign>(this, m));
+}
+
+// ============================================================================
+// [AsmJit::Compiler - Label]
+// ============================================================================
+
+Label X86Compiler::newLabel()
+{
+ Label label;
+ label._base.id = static_cast<uint32_t>(_targets.getLength()) | kOperandIdTypeLabel;
+
+ CompilerTarget* target = Compiler_newItem<X86CompilerTarget>(this, label);
+ _targets.append(target);
+
+ return label;
+}
+
+void X86Compiler::bind(const Label& label)
+{
+ uint32_t id = label.getId() & kOperandIdValueMask;
+
+ ASMJIT_ASSERT(id != kInvalidValue);
+ ASMJIT_ASSERT(id < _targets.getLength());
+
+ addItem(_targets[id]);
+}
+
+// ============================================================================
+// [AsmJit::Compiler - Variables]
+// ============================================================================
+
+X86CompilerVar* X86Compiler::_newVar(const char* name, uint32_t type, uint32_t size)
+{
+ X86CompilerVar* var = reinterpret_cast<X86CompilerVar*>(_zoneMemory.alloc(sizeof(X86CompilerVar)));
+ if (!var) return nullptr;
+
+ char nameBuffer[32];
+ if (!name)
+ {
+ sprintf(nameBuffer, "var_%d", _varNameId);
+ name = nameBuffer;
+ _varNameId++;
+ }
+
+ var->_name = _zoneMemory.sdup(name);
+ var->_id = static_cast<uint32_t>(_vars.getLength()) | kOperandIdTypeVar;
+
+ var->_type = static_cast<uint8_t>(type);
+ var->_class = x86VarInfo[type].getClass();
+ var->_priority = 10;
+
+ var->_isRegArgument = false;
+ var->_isMemArgument = false;
+ var->_isCalculated = false;
+ var->_unused = 0;
+
+ var->_size = size;
+
+ var->firstItem = nullptr;
+ var->lastItem = nullptr;
+ var->funcScope = getFunc();
+ var->funcCall = nullptr;
+
+ var->homeRegisterIndex = kRegIndexInvalid;
+ var->prefRegisterMask = 0;
+
+ var->homeMemoryOffset = 0;
+ var->homeMemoryData = nullptr;
+
+ var->regIndex = kRegIndexInvalid;
+ var->workOffset = kInvalidValue;
+
+ var->nextActive = nullptr;
+ var->prevActive = nullptr;
+
+ var->state = kVarStateUnused;
+ var->changed = false;
+ var->saveOnUnuse = false;
+
+ var->regReadCount = 0;
+ var->regWriteCount = 0;
+ var->regRwCount = 0;
+
+ var->regGpbLoCount = 0;
+ var->regGpbHiCount = 0;
+
+ var->memReadCount = 0;
+ var->memWriteCount = 0;
+ var->memRwCount = 0;
+
+ var->tPtr = nullptr;
+
+ _vars.append(var);
+ return var;
+}
+
+GpVar X86Compiler::newGpVar(uint32_t varType, const char* name)
+{
+ ASMJIT_ASSERT(varType < kX86VarTypeCount && (x86VarInfo[varType].getClass() & kX86VarClassGp));
+
+#if defined(ASMJIT_X86)
+ if (x86VarInfo[varType].getSize() > 4)
+ {
+ varType = kX86VarTypeGpd;
+ if (_logger)
+ _logger->logString("*** COMPILER WARNING: QWORD variable translated to DWORD, FIX YOUR CODE! ***\n");
+ }
+#endif // ASMJIT_X86
+
+ X86CompilerVar* var = _newVar(name, varType, x86VarInfo[varType].getSize());
+ return var->asGpVar();
+}
+
+GpVar X86Compiler::getGpArg(uint32_t argIndex)
+{
+ X86CompilerFuncDecl* func = getFunc();
+ GpVar var;
+
+ if (func)
+ {
+ X86FuncDecl* decl = func->getDecl();
+
+ if (argIndex < decl->getArgumentsCount())
+ {
+ X86CompilerVar* cv = func->getVar(argIndex);
+
+ var._var.id = cv->getId();
+ var._var.size = cv->getSize();
+ var._var.regCode = x86VarInfo[cv->getType()].getCode();
+ var._var.varType = cv->getType();
+ }
+ }
+
+ return var;
+}
+
+MmVar X86Compiler::newMmVar(uint32_t varType, const char* name)
+{
+ ASMJIT_ASSERT(varType < kX86VarTypeCount && (x86VarInfo[varType].getClass() & kX86VarClassMm));
+
+ X86CompilerVar* var = _newVar(name, varType, 8);
+ return var->asMmVar();
+}
+
+MmVar X86Compiler::getMmArg(uint32_t argIndex)
+{
+ X86CompilerFuncDecl* func = getFunc();
+ MmVar var;
+
+ if (func)
+ {
+ const X86FuncDecl* decl = func->getDecl();
+
+ if (argIndex < decl->getArgumentsCount())
+ {
+ X86CompilerVar* cv = func->getVar(argIndex);
+
+ var._var.id = cv->getId();
+ var._var.size = cv->getSize();
+ var._var.regCode = x86VarInfo[cv->getType()].getCode();
+ var._var.varType = cv->getType();
+ }
+ }
+
+ return var;
+}
+
+XmmVar X86Compiler::newXmmVar(uint32_t varType, const char* name)
+{
+ ASMJIT_ASSERT(varType < kX86VarTypeCount && (x86VarInfo[varType].getClass() & kX86VarClassXmm));
+
+ X86CompilerVar* var = _newVar(name, varType, 16);
+ return var->asXmmVar();
+}
+
+XmmVar X86Compiler::getXmmArg(uint32_t argIndex)
+{
+ X86CompilerFuncDecl* func = getFunc();
+ XmmVar var;
+
+ if (func)
+ {
+ const X86FuncDecl* decl = func->getDecl();
+
+ if (argIndex < decl->getArgumentsCount())
+ {
+ X86CompilerVar* cv = func->getVar(argIndex);
+
+ var._var.id = cv->getId();
+ var._var.size = cv->getSize();
+ var._var.regCode = x86VarInfo[cv->getType()].getCode();
+ var._var.varType = cv->getType();
+ }
+ }
+
+ return var;
+}
+
+void X86Compiler::_vhint(Var& var, uint32_t hintId, uint32_t hintValue)
+{
+ if (var.getId() == kInvalidValue)
+ return;
+
+ X86CompilerVar* cv = _getVar(var.getId());
+ ASMJIT_ASSERT(!!cv);
+
+ X86CompilerHint* item = Compiler_newItem<X86CompilerHint>(this, cv, hintId, hintValue);
+ addItem(item);
+}
+
+void X86Compiler::alloc(Var& var)
+{
+ _vhint(var, kVarHintAlloc, kInvalidValue);
+}
+
+void X86Compiler::alloc(Var& var, uint32_t regIndex)
+{
+ if (regIndex > 31)
+ return;
+
+ _vhint(var, kVarHintAlloc, IntUtil::maskFromIndex(regIndex));
+}
+
+void X86Compiler::alloc(Var& var, const Reg& reg)
+{
+ _vhint(var, kVarHintAlloc, IntUtil::maskFromIndex(reg.getRegIndex()));
+}
+
+void X86Compiler::save(Var& var)
+{
+ _vhint(var, kVarHintSave, kInvalidValue);
+}
+
+void X86Compiler::spill(Var& var)
+{
+ _vhint(var, kVarHintSpill, kInvalidValue);
+}
+
+void X86Compiler::unuse(Var& var)
+{
+ _vhint(var, kVarHintUnuse, kInvalidValue);
+}
+
+uint32_t X86Compiler::getPriority(Var& var) const
+{
+ if (var.getId() == kInvalidValue)
+ return kInvalidValue;
+
+ X86CompilerVar* vdata = _getVar(var.getId());
+ ASMJIT_ASSERT(!!vdata);
+
+ return vdata->getPriority();
+}
+
+void X86Compiler::setPriority(Var& var, uint32_t priority)
+{
+ if (var.getId() == kInvalidValue)
+ return;
+
+ X86CompilerVar* vdata = _getVar(var.getId());
+ ASMJIT_ASSERT(!!vdata);
+
+ if (priority > 100) priority = 100;
+ vdata->_priority = static_cast<uint8_t>(priority);
+}
+
+bool X86Compiler::getSaveOnUnuse(Var& var) const
+{
+ if (var.getId() == kInvalidValue)
+ return false;
+
+ X86CompilerVar* vdata = _getVar(var.getId());
+ ASMJIT_ASSERT(!!vdata);
+
+ return (bool)vdata->saveOnUnuse;
+}
+
+void X86Compiler::setSaveOnUnuse(Var& var, bool value)
+{
+ if (var.getId() == kInvalidValue)
+ return;
+
+ X86CompilerVar* vdata = _getVar(var.getId());
+ ASMJIT_ASSERT(!!vdata);
+
+ vdata->saveOnUnuse = value;
+}
+
+void X86Compiler::rename(Var& var, const char* name)
+{
+ if (var.getId() == kInvalidValue)
+ return;
+
+ X86CompilerVar* vdata = _getVar(var.getId());
+ ASMJIT_ASSERT(!!vdata);
+
+ vdata->_name = _zoneMemory.sdup(name);
+}
+
+// ============================================================================
+// [AsmJit::Compiler - State]
+// ============================================================================
+
+X86CompilerState* X86Compiler::_newState(uint32_t memVarsCount)
+{
+ X86CompilerState* state = reinterpret_cast<X86CompilerState*>(_zoneMemory.alloc(
+ sizeof(X86CompilerState) + memVarsCount * sizeof(void*)));
+ return state;
+}
+
+// ============================================================================
+// [AsmJit::Compiler - Make]
+// ============================================================================
+
+void* X86Compiler::make()
+{
+ X86Assembler x86Asm(_context);
+
+ x86Asm._properties = _properties;
+ x86Asm.setLogger(_logger);
+
+ serialize(x86Asm);
+
+ if (this->getError())
+ return nullptr;
+
+ if (x86Asm.getError())
+ {
+ setError(x86Asm.getError());
+ return nullptr;
+ }
+
+ void* result = x86Asm.make();
+
+ if (_logger)
+ {
+ _logger->logFormat("*** COMPILER SUCCESS - Wrote %u bytes, code: %u, trampolines: %u.\n\n",
+ (unsigned int)x86Asm.getCodeSize(),
+ (unsigned int)x86Asm.getOffset(),
+ (unsigned int)x86Asm.getTrampolineSize());
+ }
+
+ return result;
+}
+
+void X86Compiler::serialize(Assembler& a)
+{
+ X86CompilerContext x86Context(this);
+ X86Assembler& x86Asm = static_cast<X86Assembler&>(a);
+
+ CompilerItem* start = _first;
+ CompilerItem* stop = nullptr;
+
+ // Register all labels.
+ x86Asm.registerLabels(_targets.getLength());
+
+ // Make code.
+ for (;;)
+ {
+ _cc = nullptr;
+
+ // ------------------------------------------------------------------------
+ // [Find Function]
+ // ------------------------------------------------------------------------
+
+ for (;;)
+ {
+ if (!start)
+ return;
+
+ if (start->getType() == kCompilerItemFuncDecl)
+ break;
+
+ start->emit(x86Asm);
+ start = start->getNext();
+ }
+
+ // ------------------------------------------------------------------------
+ // [Setup CompilerContext]
+ // ------------------------------------------------------------------------
+
+ stop = static_cast<X86CompilerFuncDecl*>(start)->getEnd();
+
+ x86Context._func = static_cast<X86CompilerFuncDecl*>(start);
+ x86Context._start = start;
+ x86Context._stop = stop;
+ x86Context._extraBlock = stop->getPrev();
+
+ // Detect whether the function generation was finished.
+ if (!x86Context._func->isFinished() || !x86Context._func->getEnd()->getPrev())
+ {
+ setError(kErrorIncompleteFunction);
+ return;
+ }
+
+ // ------------------------------------------------------------------------
+ // Step 1:
+ // - Assign/increment offset of each item.
+ // - Extract variables from instructions.
+ // - Prepare variables for register allocator:
+ // - Update read(r) / write(w) / read/write(x) statistics.
+ // - Update register / memory usage statistics.
+ // - Find scope (first / last item) of variables.
+ // ------------------------------------------------------------------------
+
+ CompilerItem* cur;
+ for (cur = start; ; cur = cur->getNext())
+ {
+ cur->prepare(x86Context);
+ if (cur == stop)
+ break;
+ }
+
+ // We set compiler context also to Compiler so newly emitted instructions
+ // can call CompilerItem::prepare() on itself.
+ _cc = &x86Context;
+
+ // ------------------------------------------------------------------------
+ // Step 2:
+ // - Translate special instructions (imul, cmpxchg8b, ...).
+ // - Alloc registers.
+ // - Translate forward jumps.
+ // - Alloc memory operands (variables related).
+ // - Emit function prolog.
+ // - Emit function epilog.
+ // - Patch memory operands (variables related).
+ // - Dump function prototype and variable statistics (if enabled).
+ // ------------------------------------------------------------------------
+
+ // Translate special instructions and run alloc registers.
+ cur = start;
+
+ do {
+ do {
+ // Assign current offset of each item back to CompilerContext.
+ x86Context._currentOffset = cur->_offset;
+ // Assign previous item to compiler so each variable spill/alloc will
+ // be emitted before.
+ _current = cur->getPrev();
+
+ cur = cur->translate(x86Context);
+ } while (cur);
+
+ x86Context._isUnreachable = true;
+
+ size_t len = x86Context._backCode.getLength();
+ while (x86Context._backPos < len)
+ {
+ cur = x86Context._backCode[x86Context._backPos++]->getNext();
+ if (!cur->isTranslated()) break;
+
+ cur = nullptr;
+ }
+ } while (cur);
+
+ // Translate forward jumps.
+ {
+ ForwardJumpData* j = x86Context._forwardJumps;
+ while (j)
+ {
+ x86Context._assignState(j->state);
+ _current = j->inst->getPrev();
+ j->inst->doJump(x86Context);
+ j = j->next;
+ }
+ }
+
+ // Alloc memory operands (variables related).
+ x86Context._allocMemoryOperands();
+
+ // Emit function prolog / epilog.
+ x86Context.getFunc()->_preparePrologEpilog(x86Context);
+
+ _current = x86Context._func->getEntryTarget();
+ x86Context.getFunc()->_emitProlog(x86Context);
+
+ _current = x86Context._func->getExitTarget();
+ x86Context.getFunc()->_emitEpilog(x86Context);
+
+ // Patch memory operands (variables related).
+ _current = _last;
+ x86Context._patchMemoryOperands(start, stop);
+
+ // Dump function prototype and variable statistics (if enabled).
+ if (_logger)
+ x86Context.getFunc()->_dumpFunction(x86Context);
+
+ // ------------------------------------------------------------------------
+ // Hack: need to register labels that was created by the Step 2.
+ // ------------------------------------------------------------------------
+
+ if (x86Asm._labels.getLength() < _targets.getLength())
+ x86Asm.registerLabels(_targets.getLength() - x86Asm._labels.getLength());
+
+ CompilerItem* extraBlock = x86Context._extraBlock;
+
+ // ------------------------------------------------------------------------
+ // Step 3:
+ // - Emit instructions to Assembler stream.
+ // ------------------------------------------------------------------------
+
+ for (cur = start; ; cur = cur->getNext())
+ {
+ cur->emit(x86Asm);
+ if (cur == extraBlock) break;
+ }
+
+ // ------------------------------------------------------------------------
+ // Step 4:
+ // - Emit everything else (post action).
+ // ------------------------------------------------------------------------
+
+ for (cur = start; ; cur = cur->getNext())
+ {
+ cur->post(x86Asm);
+ if (cur == extraBlock) break;
+ }
+
+ start = extraBlock->getNext();
+ x86Context._clear();
+ }
+}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86/x86compiler.h
@@ -1,1 +1,5830 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_X86_X86COMPILER_H
+#define _ASMJIT_X86_X86COMPILER_H
+
+// [Dependencies - AsmJit]
+#include "../core/build.h"
+#include "../core/compiler.h"
+#include "../core/compilercontext.h"
+#include "../core/compilerfunc.h"
+#include "../core/compileritem.h"
+
+#include "../x86/x86assembler.h"
+#include "../x86/x86defs.h"
+#include "../x86/x86func.h"
+#include "../x86/x86util.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+//! @internal
+//!
+//! @brief Mark methods not supported by @ref Compiler. These methods are
+//! usually used only in function prologs/epilogs or to manage stack.
+#define ASMJIT_NOT_SUPPORTED_BY_COMPILER 0
+
+namespace AsmJit {
+
+//! @addtogroup AsmJit_X86
+//! @{
+
+// ============================================================================
+// [Forward Declarations]
+// ============================================================================
+
+struct X86Compiler;
+struct X86CompilerAlign;
+struct X86CompilerContext;
+struct X86CompilerFuncCall;
+struct X86CompilerFuncDecl;
+struct X86CompilerFuncEnd;
+struct X86CompilerInst;
+struct X86CompilerJmpInst;
+struct X86CompilerState;
+struct X86CompilerTarget;
+struct X86CompilerVar;
+
+// ============================================================================
+// [AsmJit::X86CompilerVar]
+// ============================================================================
+
+//! @brief @ref X86Compiler variable.
+struct X86CompilerVar : public CompilerVar
+{
+ // --------------------------------------------------------------------------
+ // [AsVar]
+ // --------------------------------------------------------------------------
+
+ GpVar asGpVar() const
+ {
+ GpVar var;
+ var._var.id = _id;
+ var._var.size = _size;
+ var._var.regCode = x86VarInfo[_type].getCode();
+ var._var.varType = _type;
+ return var;
+ }
+
+ MmVar asMmVar() const
+ {
+ MmVar var;
+ var._var.id = _id;
+ var._var.size = _size;
+ var._var.regCode = x86VarInfo[_type].getCode();
+ var._var.varType = _type;
+ return var;
+ }
+
+ XmmVar asXmmVar() const
+ {
+ XmmVar var;
+ var._var.id = _id;
+ var._var.size = _size;
+ var._var.regCode = x86VarInfo[_type].getCode();
+ var._var.varType = _type;
+ return var;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Members - Scope]
+ // --------------------------------------------------------------------------
+
+ //! @brief The first item where the variable is accessed.
+ //! @note If this member is @c NULL then variable isn't used.
+ CompilerItem* firstItem;
+ //! @brief The last item where the variable is accessed.
+ CompilerItem* lastItem;
+
+ //! @brief Scope (NULL if variable is global).
+ X86CompilerFuncDecl* funcScope;
+ //! @brief The first call which is after the @c firstItem.
+ X86CompilerFuncCall* funcCall;
+
+ // --------------------------------------------------------------------------
+ // [Members - Home]
+ // --------------------------------------------------------------------------
+
+ //! @brief Home register index or @c kRegIndexInvalid (used by register allocator).
+ uint32_t homeRegisterIndex;
+ //! @brief Preferred registers mask.
+ uint32_t prefRegisterMask;
+
+ //! @brief Home memory address offset.
+ int32_t homeMemoryOffset;
+ //! @brief Used by @c CompilerContext, do not touch (initially NULL).
+ void* homeMemoryData;
+
+ // --------------------------------------------------------------------------
+ // [Members - Actual]
+ // --------------------------------------------------------------------------
+
+ //! @brief Actual register index (connected with actual @c X86CompilerState).
+ uint32_t regIndex;
+ //! @brief Actual working offset. This member is set before register allocator
+ //! is called. If workOffset is same as CompilerContext::_currentOffset then
+ //! this variable is probably used in next instruction and can't be spilled.
+ uint32_t workOffset;
+
+ //! @brief Next active variable in circular double-linked list.
+ X86CompilerVar* nextActive;
+ //! @brief Previous active variable in circular double-linked list.
+ X86CompilerVar* prevActive;
+
+ // --------------------------------------------------------------------------
+ // [Members - Flags]
+ // --------------------------------------------------------------------------
+
+ //! @brief Variable state (connected with actual @c X86CompilerState).
+ uint8_t state;
+ //! @brief Whether variable was changed (connected with actual @c X86CompilerState).
+ uint8_t changed;
+ //! @brief Save on unuse (at end of the variable scope).
+ uint8_t saveOnUnuse;
+
+ // --------------------------------------------------------------------------
+ // [Members - Statistics]
+ // --------------------------------------------------------------------------
+
+ //! @brief Register read access statistics.
+ uint32_t regReadCount;
+ //! @brief Register write access statistics.
+ uint32_t regWriteCount;
+ //! @brief Register read/write access statistics (related to a single instruction).
+ uint32_t regRwCount;
+
+ //! @brief Register GpbLo access statistics.
+ uint32_t regGpbLoCount;
+ //! @brief Register GpbHi access statistics.
+ uint32_t regGpbHiCount;
+
+ //! @brief Memory read statistics.
+ uint32_t memReadCount;
+ //! @brief Memory write statistics.
+ uint32_t memWriteCount;
+ //! @brief Memory read+write statistics.
+ uint32_t memRwCount;
+
+ // --------------------------------------------------------------------------
+ // [Members - Temporary]
+ // --------------------------------------------------------------------------
+
+ //! @brief Temporary data that can be used in prepare/translate stage.
+ //!
+ //! Initial value is NULL and it's expected that after use it's set back to
+ //! NULL.
+ //!
+ //! The temporary data is designed to be used by algorithms that need to
+ //! set some state into variables, do something and then clean-up. See
+ //! state switch and function call for details.
+ union
+ {
+ void* tPtr;
+ intptr_t tInt;
+ };
+};
+
+// ============================================================================
+// [AsmJit::X86CompilerState]
+// ============================================================================
+
+//! @brief @ref X86Compiler state.
+struct X86CompilerState : CompilerState
+{
+ enum
+ {
+ //! @brief Base for Gp registers.
+ kStateRegGpBase = 0,
+ //! @brief Base for Mm registers.
+ kStateRegMmBase = 16,
+ //! @brief Base for Xmm registers.
+ kStateRegXmmBase = 24,
+
+ //! @brief Count of all registers in @ref X86CompilerState.
+ kStateRegCount = 16 + 8 + 16
+ };
+
+ // --------------------------------------------------------------------------
+ // [Clear]
+ // --------------------------------------------------------------------------
+
+ void clear()
+ { memset(this, 0, sizeof(*this)); }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ union
+ {
+ //! @brief All allocated variables in one array.
+ X86CompilerVar* regs[kStateRegCount];
+
+ struct
+ {
+ //! @brief Allocated GP registers.
+ X86CompilerVar* gp[16];
+ //! @brief Allocated MM registers.
+ X86CompilerVar* mm[8];
+ //! @brief Allocated XMM registers.
+ X86CompilerVar* xmm[16];
+ };
+ };
+
+ //! @brief Used GP registers bit-mask.
+ uint32_t usedGP;
+ //! @brief Used MM registers bit-mask.
+ uint32_t usedMM;
+ //! @brief Used XMM registers bit-mask.
+ uint32_t usedXMM;
+
+ //! @brief Changed GP registers bit-mask.
+ uint32_t changedGP;
+ //! @brief Changed MM registers bit-mask.
+ uint32_t changedMM;
+ //! @brief Changed XMM registers bit-mask.
+ uint32_t changedXMM;
+
+ //! @brief Count of variables in @c memVarsData.
+ uint32_t memVarsCount;
+ //! @brief Variables stored in memory (@c kVarStateMem).
+ //!
+ //! When saving / restoring state it's important to keep registers which are
+ //! still in memory. Register is always unused when it is going out-of-scope.
+ //! All variables which are not here are unused (@c kVarStateUnused).
+ X86CompilerVar* memVarsData[1];
+};
+
+// ============================================================================
+// [AsmJit::VarMemBlock]
+// ============================================================================
+
+struct VarMemBlock
+{
+ int32_t offset;
+ uint32_t size;
+
+ VarMemBlock* nextUsed;
+ VarMemBlock* nextFree;
+};
+
+// ============================================================================
+// [AsmJit::VarAllocRecord]
+// ============================================================================
+
+//! @brief Variable alloc record (for each instruction that uses variables).
+//!
+//! Variable record contains pointer to variable data and register allocation
+//! flags. These flags are important to determine the best alloc instruction.
+struct VarAllocRecord
+{
+ //! @brief Variable data (the structure owned by @c Compiler).
+ X86CompilerVar* vdata;
+ //! @brief Variable alloc flags, see @c kVarAllocFlags.
+ uint32_t vflags;
+ //! @brief Register mask (default is 0).
+ uint32_t regMask;
+};
+
+// ============================================================================
+// [AsmJit::VarCallRecord]
+// ============================================================================
+
+//! @brief Variable call-fn record (for each callable that uses variables).
+//!
+//! This record contains variables that are used to call a function (using
+//! @c X86CompilerFuncCall item). Each variable contains the registers where
+//! it must be and registers where the value will be returned.
+struct VarCallRecord
+{
+ //! @brief Variable data (the structure owned by @c Compiler).
+ X86CompilerVar* vdata;
+ uint32_t flags;
+
+ uint8_t inCount;
+ uint8_t inDone;
+
+ uint8_t outCount;
+ uint8_t outDone;
+
+ enum FLAGS
+ {
+ kFlagInGp = 0x0001,
+ kFlagInMm = 0x0002,
+ kFlagInXmm = 0x0004,
+ kFlagInStack = 0x0008,
+
+ kFlagOutEax = 0x0010,
+ kFlagOutEdx = 0x0020,
+ kFlagOutSt0 = 0x0040,
+ kFlagOutSt1 = 0x0080,
+ kFlagOutMm0 = 0x0100,
+ kFlagOutXmm0 = 0x0400,
+ kFlagOutXmm1 = 0x0800,
+
+ kFlagInMemPtr = 0x1000,
+ kFlagCallReg = 0x2000,
+ kFlagCallMem = 0x4000,
+ kFlagUnuseAfterUse = 0x8000
+ };
+};
+
+// ============================================================================
+// [AsmJit::VarHintRecord]
+// ============================================================================
+
+struct VarHintRecord
+{
+ X86CompilerVar* vdata;
+ uint32_t hint;
+};
+
+// ============================================================================
+// [AsmJit::ForwardJumpData]
+// ============================================================================
+
+struct ForwardJumpData
+{
+ X86CompilerJmpInst* inst;
+ X86CompilerState* state;
+ ForwardJumpData* next;
+};
+
+// ============================================================================
+// [AsmJit::CompilerUtil]
+// ============================================================================
+
+//! @brief Static class that contains utility methods.
+struct CompilerUtil
+{
+ ASMJIT_API static bool isStack16ByteAligned();
+};
+
+// ============================================================================
+// [AsmJit::X86Compiler]
+// ============================================================================
+
+//! @brief Compiler - high level code generation.
+//!
+//! This class is used to store instruction stream and allows to modify
+//! it on the fly. It uses different concept than @c AsmJit::Assembler class
+//! and in fact @c AsmJit::Assembler is only used as a backend. Compiler never
+//! emits machine code and each instruction you use is stored to instruction
+//! array instead. This allows to modify instruction stream later and for
+//! example to reorder instructions to make better performance.
+//!
+//! Using @c AsmJit::Compiler moves code generation to higher level. Higher
+//! level constructs allows to write more abstract and extensible code that
+//! is not possible with pure @c AsmJit::Assembler class. Because
+//! @c AsmJit::Compiler needs to create many objects and lifetime of these
+//! objects is small (same as @c AsmJit::Compiler lifetime itself) it uses
+//! very fast memory management model. This model allows to create object
+//! instances in nearly zero time (compared to @c malloc() or @c new()
+//! operators) so overhead by creating machine code by @c AsmJit::Compiler
+//! is minimized.
+//!
+//! @section AsmJit_Compiler_TheStory The Story
+//!
+//! Before telling you how Compiler works I'd like to write a story. I'd like
+//! to cover reasons why this class was created and why I'm recommending to use
+//! it. When I released the first version of AsmJit (0.1) it was a toy. The
+//! first function I wrote was function which is still available as testjit and
+//! which simply returns 1024. The reason why function works for both 32-bit/
+//! 64-bit mode and for Windows/Unix specific calling conventions is luck, no
+//! arguments usage and no registers usage except returning value in EAX/RAX.
+//!
+//! Then I started a project called BlitJit which was targetted to generating
+//! JIT code for computer graphics. After writing some lines I decided that I
+//! can't join pieces of code together without abstraction, should be
+//! pixels source pointer in ESI/RSI or EDI/RDI or it's completelly
+//! irrellevant? What about destination pointer and SSE2 register for reading
+//! input pixels? The simple answer might be "just pick some one and use it".
+//!
+//! Another reason for abstraction is function calling-conventions. It's really
+//! not easy to write assembler code for 32-bit and 64-bit platform supporting
+//! three calling conventions (32-bit is similar between Windows and Unix, but
+//! 64-bit calling conventions are different).
+//!
+//! At this time I realized that I can't write code which uses named registers,
+//! I need to abstract it. In most cases you don't need specific register, you
+//! need to emit instruction that does something with 'virtual' register(s),
+//! memory, immediate or label.
+//!
+//! The first version of AsmJit with Compiler was 0.5 (or 0.6?, can't remember).
+//! There was support for 32-bit and 64-bit mode, function calling conventions,
+//! but when emitting instructions the developer needed to decide which
+//! registers are changed, which are only read or completely overwritten. This
+//! model helped a lot when generating code, especially when joining more
+//! code-sections together, but there was also small possibility for mistakes.
+//! Simply the first version of Compiler was great improvement over low-level
+//! Assembler class, but the API design wasn't perfect.
+//!
+//! The second version of Compiler, completelly rewritten and based on
+//! different goals, is part of AsmJit starting at version 1.0. This version
+//! was designed after the first one and it contains serious improvements over
+//! the old one. The first improvement is that you just use instructions with
+//! virtual registers - called variables. When using compiler there is no way
+//! to use native registers, there are variables instead. AsmJit is smarter
+//! than before and it knows which register is needed only for read (r),
+//! read/write (w) or overwrite (x). Supported are also instructions which
+//! are using some registers in implicit way (these registers are not part of
+//! instruction definition in string form). For example to use CPUID instruction
+//! you must give it four variables which will be automatically allocated to
+//! input/output registers (EAX, EBX, ECX, EDX).
+//!
+//! Another improvement is algorithm used by a register allocator. In first
+//! version the registers were allocated when creating instruction stream. In
+//! new version registers are allocated after calling @c Compiler::make(). This
+//! means that register allocator has information about scope of all variables
+//! and their usage statistics. The algorithm to allocate registers is very
+//! simple and it's always called as a 'linear scan register allocator'. When
+//! you get out of registers the all possible variables are scored and the worst
+//! is spilled. Of course algorithm ignores the variables used for current
+//! instruction.
+//!
+//! In addition, because registers are allocated after the code stream is
+//! generated, the state switches between jumps are handled by Compiler too.
+//! You don't need to worry about jumps, compiler always do this dirty work
+//! for you.
+//!
+//! The nearly last thing I'd like to present is calling other functions from
+//! the generated code. AsmJit uses a @c FunctionPrototype class to hold
+//! the function parameters, their position in stack (or register index) and
+//! function return value. This class is used internally, but it can be
+//! used to create your own function calling-convention. All standard function
+//! calling conventions are implemented.
+//!
+//! Please enjoy the new version of Compiler, it was created for writing a
+//! low-level code using high-level API, leaving developer to concentrate to
+//! real problems and not to solving a register puzzle.
+//!
+//! @section AsmJit_Compiler_CodeGeneration Code Generation
+//!
+//! First that is needed to know about compiler is that compiler never emits
+//! machine code. It's used as a middleware between @c AsmJit::Assembler and
+//! your code. There is also convenience method @c make() that allows to
+//! generate machine code directly without creating @c AsmJit::Assembler
+//! instance.
+//!
+//! Comparison of generating machine code through @c Assembler and directly
+//! by @c Compiler:
+//!
+//! @code
+//! // Assembler instance is low level code generation class that emits
+//! // machine code.
+//! X86Assembler a;
+//!
+//! // Compiler instance is high level code generation class that stores all
+//! // instructions in internal representation.
+//! X86Compiler c;
+//!
+//! // ... put your code here ...
+//!
+//! // Final step - generate code. AsmJit::Compiler::serialize() will serialize
+//! // all instructions into Assembler and this ensures generating real machine
+//! // code.
+//! c.serialize(a);
+//!
+//! // Your function
+//! void* fn = a.make();
+//! @endcode
+//!
+//! Example how to generate machine code using only @c Compiler (preferred):
+//!
+//! @code
+//! // Compiler instance is enough.
+//! X86Compiler c;
+//!
+//! // ... put your code here ...
+//!
+//! // Your function
+//! void* fn = c.make();
+//! @endcode
+//!
+//! You can see that there is @c AsmJit::Compiler::serialize() function that
+//! emits instructions into @c AsmJit::Assembler(). This layered architecture
+//! means that each class is used for something different and there is no code
+//! duplication. For convenience there is also @c AsmJit::Compiler::make()
+//! method that can create your function using @c AsmJit::Assembler, but
+//! internally (this is preffered bahavior when using @c AsmJit::Compiler).
+//!
+//! The @c make() method allocates memory using @c Context instance passed
+//! into the @c X86Compiler constructor. If code generator is used to create JIT
+//! function then virtual memory allocated by @c MemoryManager is used. To get
+//! global memory manager use @c MemoryManager::getGlobal().
+//!
+//! @code
+//! // Compiler instance is enough.
+//! X86Compiler c;
+//!
+//! // ... put your code using Compiler instance ...
+//!
+//! // Your function
+//! void* fn = c.make();
+//!
+//! // Free it if you don't want it anymore
+//! // (using global memory manager instance)
+//! MemoryManager::getGlobal()->free(fn);
+//! @endcode
+//!
+//! @section AsmJit_Compiler_Functions Functions
+//!
+//! To build functions with @c Compiler, see @c AsmJit::Compiler::newFunc()
+//! method.
+//!
+//! @section AsmJit_Compiler_Variables Variables
+//!
+//! Compiler is able to manage variables and function arguments. Internally
+//! there is no difference between function argument and variable declared
+//! inside. To get function argument you use @c getGpArg() method and to declare
+//! variable use @c newGpVar(), @c newMmVar() and @c newXmmVar() methods. The @c newXXX()
+//! methods accept also parameter describing the variable type. For example
+//! the @c newGpVar() method always creates variable which size matches the target
+//! architecture size (for 32-bit target the 32-bit variable is created, for
+//! 64-bit target the variable size is 64-bit). To override this behavior the
+//! variable type must be specified.
+//!
+//! @code
+//! // Compiler and function declaration - void f(int*);
+//! X86Compiler c;
+//! c.newFunc(kX86FuncConvDefault, BuildFunction1<int*>());
+//!
+//! // Get argument variable (it's pointer).
+//! GpVar a1(c.getGpArg(0));
+//!
+//! // Create your variables.
+//! GpVar x1(c.newGpVar(kX86VarTypeGpd));
+//! GpVar x2(c.newGpVar(kX86VarTypeGpd));
+//!
+//! // Init your variables.
+//! c.mov(x1, 1);
+//! c.mov(x2, 2);
+//!
+//! // ... your code ...
+//! c.add(x1, x2);
+//! // ... your code ...
+//!
+//! // Store result to a given pointer in first argument
+//! c.mov(dword_ptr(a1), x1);
+//!
+//! // End of function body.
+//! c.endFunc();
+//!
+//! // Make the function.
+//! typedef void (*MyFn)(int*);
+//! MyFn fn = asmjit_cast<MyFn>(c.make());
+//! @endcode
+//!
+//! This code snipped needs to be explained. You can see that there are more
+//! variable types that can be used by @c Compiler. Most useful variables can
+//! be allocated using general purpose registers (@c GpVar), MMX registers
+//! (@c MmVar) or SSE registers (@c XmmVar).
+//!
+//! X86/X64 variable types:
+//!
+//! - @c kX86VarTypeGpd - 32-bit general purpose register (EAX, EBX, ...).
+//! - @c kX86VarTypeGpq - 64-bit general purpose register (RAX, RBX, ...).
+//! - @c kX86VarTypeGpz - 32-bit or 64-bit general purpose register, depends
+//! to target architecture. Mapped to @c kX86VarTypeGpd or @c kX86VarTypeGpq.
+//!
+//! - @c kX86VarTypeX87 - 80-bit floating point stack register st(0 to 7).
+//! - @c kX86VarTypeX87SS - 32-bit floating point stack register st(0 to 7).
+//! - @c kX86VarTypeX87SD - 64-bit floating point stack register st(0 to 7).
+//!
+//! - @c VARIALBE_TYPE_MM - 64-bit MMX register.
+//!
+//! - @c kX86VarTypeXmm - 128-bit SSE register.
+//! - @c kX86VarTypeXmmSS - 128-bit SSE register which contains
+//! scalar 32-bit single precision floating point.
+//! - @c kX86VarTypeXmmSD - 128-bit SSE register which contains
+//! scalar 64-bit double precision floating point.
+//! - @c kX86VarTypeXmmPS - 128-bit SSE register which contains
+//! 4 packed 32-bit single precision floating points.
+//! - @c kX86VarTypeXmmPD - 128-bit SSE register which contains
+//! 2 packed 64-bit double precision floating points.
+//!
+//! Unified variable types:
+//!
+//! - @c kX86VarTypeInt32 - 32-bit general purpose register.
+//! - @c kX86VarTypeInt64 - 64-bit general purpose register.
+//! - @c kX86VarTypeIntPtr - 32-bit or 64-bit general purpose register / pointer.
+//!
+//! - @c kX86VarTypeFloat - 32-bit single precision floating point.
+//! - @c kX86VarTypeDouble - 64-bit double precision floating point.
+//!
+//! Variable states:
+//!
+//! - @c kVarStateUnused - State that is assigned to newly created
+//! variables or to not used variables (dereferenced to zero).
+//! - @c kVarStateReg - State that means that variable is currently
+//! allocated in register.
+//! - @c kVarStateMem - State that means that variable is currently
+//! only in memory location.
+//!
+//! When you create new variable, initial state is always @c kVarStateUnused,
+//! allocating it to register or spilling to memory changes this state to
+//! @c kVarStateReg or @c kVarStateMem, respectively.
+//! During variable lifetime it's usual that its state is changed multiple
+//! times. To generate better code, you can control allocating and spilling
+//! by using up to four types of methods that allows it (see next list).
+//!
+//! Explicit variable allocating / spilling methods:
+//!
+//! - @c Compiler::alloc() - Explicit method to alloc variable into
+//! register. You can use this before loops or code blocks.
+//!
+//! - @c Compiler::spill() - Explicit method to spill variable. If variable
+//! is in register and you call this method, it's moved to its home memory
+//! location. If variable is not in register no operation is performed.
+//!
+//! - @c Compiler::unuse() - Unuse variable (you can use this to end the
+//! variable scope or sub-scope).
+//!
+//! Please see AsmJit tutorials (testcompiler.cpp and testvariables.cpp) for
+//! more complete examples.
+//!
+//! @section AsmJit_Compiler_MemoryManagement Memory Management
+//!
+//! @c Compiler Memory management follows these rules:
+//! - Everything created by @c Compiler is always freed by @c Compiler.
+//! - To get decent performance, compiler always uses larger memory buffer
+//! for objects to allocate and when compiler instance is destroyed, this
+//! buffer is freed. Destructors of active objects are called when
+//! destroying compiler instance. Destructors of abadonded compiler
+//! objects are called immediately after abadonding them.
+//! - This type of memory management is called 'zone memory management'.
+//!
+//! This means that you can't use any @c Compiler object after destructing it,
+//! it also means that each object like @c Label, @c Var and others are created
+//! and managed by @c Compiler itself. These objects contain ID which is used
+//! internally by Compiler to store additional information about these objects.
+//!
+//! @section AsmJit_Compiler_StateManagement Control-Flow and State Management.
+//!
+//! The @c Compiler automatically manages state of the variables when using
+//! control flow instructions like jumps, conditional jumps and calls. There
+//! is minimal heuristics for choosing the method how state is saved or restored.
+//!
+//! Generally the state can be changed only when using jump or conditional jump
+//! instruction. When using non-conditional jump then state change is embedded
+//! into the instruction stream before the jump. When using conditional jump
+//! the @c Compiler decides whether to restore state before the jump or whether
+//! to use another block where state is restored. The last case is that no-code
+//! have to be emitted and there is no state change (this is of course ideal).
+//!
+//! Choosing whether to embed 'restore-state' section before conditional jump
+//! is quite simple. If jump is likely to be 'taken' then code is embedded, if
+//! jump is unlikely to be taken then the small code section for state-switch
+//! will be generated instead.
+//!
+//! Next example is the situation where the extended code block is used to
+//! do state-change:
+//!
+//! @code
+//! X86Compiler c;
+//!
+//! c.newFunc(kX86FuncConvDefault, FuncBuilder0<Void>());
+//! c.getFunc()->setHint(kFuncHintNaked, true);
+//!
+//! // Labels.
+//! Label L0 = c.newLabel();
+//!
+//! // Variables.
+//! GpVar var0 = c.newGpVar();
+//! GpVar var1 = c.newGpVar();
+//!
+//! // Cleanup. After these two lines, the var0 and var1 will be always stored
+//! // in registers. Our example is very small, but in larger code the var0 can
+//! // be spilled by xor(var1, var1).
+//! c.xor_(var0, var0);
+//! c.xor_(var1, var1);
+//! c.cmp(var0, var1);
+//! // State:
+//! // var0 - register.
+//! // var1 - register.
+//!
+//! // We manually spill these variables.
+//! c.spill(var0);
+//! c.spill(var1);
+//! // State:
+//! // var0 - memory.
+//! // var1 - memory.
+//!
+//! // Conditional jump to L0. It will be always taken, but compiler thinks that
+//! // it is unlikely taken so it will embed state change code somewhere.
+//! c.je(L0);
+//!
+//! // Do something. The variables var0 and var1 will be allocated again.
+//! c.add(var0, 1);
+//! c.add(var1, 2);
+//! // State:
+//! // var0 - register.
+//! // var1 - register.
+//!
+//! // Bind label here, the state is not changed.
+//! c.bind(L0);
+//! // State:
+//! // var0 - register.
+//! // var1 - register.
+//!
+//! // We need to use var0 and var1, because if compiler detects that variables
+//! // are out of scope then it optimizes the state-change.
+//! c.sub(var0, var1);
+//! // State:
+//! // var0 - register.
+//! // var1 - register.
+//!
+//! c.endFunc();
+//! @endcode
+//!
+//! The output:
+//!
+//! @verbatim
+//! xor eax, eax ; xor var_0, var_0
+//! xor ecx, ecx ; xor var_1, var_1
+//! cmp eax, ecx ; cmp var_0, var_1
+//! mov [esp - 24], eax ; spill var_0
+//! mov [esp - 28], ecx ; spill var_1
+//! je L0_Switch
+//! mov eax, [esp - 24] ; alloc var_0
+//! add eax, 1 ; add var_0, 1
+//! mov ecx, [esp - 28] ; alloc var_1
+//! add ecx, 2 ; add var_1, 2
+//! L0:
+//! sub eax, ecx ; sub var_0, var_1
+//! ret
+//!
+//! ; state-switch begin
+//! L0_Switch0:
+//! mov eax, [esp - 24] ; alloc var_0
+//! mov ecx, [esp - 28] ; alloc var_1
+//! jmp short L0
+//! ; state-switch end
+//! @endverbatim
+//!
+//! You can see that the state-switch section was generated (see L0_Switch0).
+//! The compiler is unable to restore state immediately when emitting the
+//! forward jump (the code is generated from first to last instruction and
+//! the target state is simply not known at this time).
+//!
+//! To tell @c Compiler that you want to embed state-switch code before jump
+//! it's needed to create backward jump (where also processor expects that it
+//! will be taken). To demonstrate the possibility to embed state-switch before
+//! jump we use slightly modified code:
+//!
+//! @code
+//! X86Compiler c;
+//!
+//! c.newFunc(kX86FuncConvDefault, FuncBuilder0<Void>());
+//! c.getFunc()->setHint(kFuncHintNaked, true);
+//!
+//! // Labels.
+//! Label L0 = c.newLabel();
+//!
+//! // Variables.
+//! GpVar var0 = c.newGpVar();
+//! GpVar var1 = c.newGpVar();
+//!
+//! // Cleanup. After these two lines, the var0 and var1 will be always stored
+//! // in registers. Our example is very small, but in larger code the var0 can
+//! // be spilled by xor(var1, var1).
+//! c.xor_(var0, var0);
+//! c.xor_(var1, var1);
+//! // State:
+//! // var0 - register.
+//! // var1 - register.
+//!
+//! // We manually spill these variables.
+//! c.spill(var0);
+//! c.spill(var1);
+//! // State:
+//! // var0 - memory.
+//! // var1 - memory.
+//!
+//! // Bind our label here.
+//! c.bind(L0);
+//!
+//! // Do something, the variables will be allocated again.
+//! c.add(var0, 1);
+//! c.add(var1, 2);
+//! // State:
+//! // var0 - register.
+//! // var1 - register.
+//!
+//! // Backward conditional jump to L0. The default behavior is that it is taken
+//! // so state-change code will be embedded here.
+//! c.je(L0);
+//!
+//! c.endFunc();
+//! @endcode
+//!
+//! The output:
+//!
+//! @verbatim
+//! xor ecx, ecx ; xor var_0, var_0
+//! xor edx, edx ; xor var_1, var_1
+//! mov [esp - 24], ecx ; spill var_0
+//! mov [esp - 28], edx ; spill var_1
+//! L.2:
+//! mov ecx, [esp - 24] ; alloc var_0
+//! add ecx, 1 ; add var_0, 1
+//! mov edx, [esp - 28] ; alloc var_1
+//! add edx, 2 ; add var_1, 2
+//!
+//! ; state-switch begin
+//! mov [esp - 24], ecx ; spill var_0
+//! mov [esp - 28], edx ; spill var_1
+//! ; state-switch end
+//!
+//! je short L.2
+//! ret
+//! @endverbatim
+//!
+//! Please notice where the state-switch section is located. The @c Compiler
+//! decided that jump is likely to be taken so the state change is embedded
+//! before the conditional jump. To change this behavior into the previous
+//! case it's needed to add a hint (@c kCondHintLikely or @c kCondHintUnlikely).
+//!
+//! Replacing the <code>c.je(L0)</code> by <code>c.je(L0, kCondHintUnlikely)
+//! will generate code like this:
+//!
+//! @verbatim
+//! xor ecx, ecx ; xor var_0, var_0
+//! xor edx, edx ; xor var_1, var_1
+//! mov [esp - 24], ecx ; spill var_0
+//! mov [esp - 28], edx ; spill var_1
+//! L0:
+//! mov ecx, [esp - 24] ; alloc var_0
+//! add ecx, 1 ; add var_0, a
+//! mov edx, [esp - 28] ; alloc var_1
+//! add edx, 2 ; add var_1, 2
+//! je L0_Switch, 2
+//! ret
+//!
+//! ; state-switch begin
+//! L0_Switch:
+//! mov [esp - 24], ecx ; spill var_0
+//! mov [esp - 28], edx ; spill var_1
+//! jmp short L0
+//! ; state-switch end
+//! @endverbatim
+//!
+//! This section provided information about how state-change works. The
+//! behavior is deterministic and it can be overridden.
+//!
+//! @section AsmJit_Compiler_AdvancedCodeGeneration Advanced Code Generation
+//!
+//! This section describes advanced method of code generation available to
+//! @c Compiler (but also to @c Assembler). When emitting code to instruction
+//! stream the methods like @c mov(), @c add(), @c sub() can be called directly
+//! (advantage is static-type control performed also by C++ compiler) or
+//! indirectly using @c emit() method. The @c emit() method needs only
+//! instruction code and operands.
+//!
+//! Example of code generating by standard type-safe API:
+//!
+//! @code
+//! X86Compiler c;
+//! GpVar var0 = c.newGpVar();
+//! GpVar var1 = c.newGpVar();
+//!
+//! ...
+//!
+//! c.mov(var0, imm(0));
+//! c.add(var0, var1);
+//! c.sub(var0, var1);
+//! @endcode
+//!
+//! The code above can be rewritten as:
+//!
+//! @code
+//! X86Compiler c;
+//! GpVar var0 = c.newGpVar();
+//! GpVar var1 = c.newGpVar();
+//!
+//! ...
+//!
+//! c.emit(kX86InstMov, var0, imm(0));
+//! c.emit(kX86InstAdd, var0, var1);
+//! c.emit(kX86InstSub, var0, var1);
+//! @endcode
+//!
+//! The advantage of first snippet is very friendly API and type-safe control
+//! that is controlled by the C++ compiler. The advantage of second snippet is
+//! availability to replace or generate instruction code in different places.
+//! See the next example how the @c emit() method can be used to generate
+//! abstract code.
+//!
+//! Use case:
+//!
+//! @code
+//! bool emitArithmetic(Compiler& c, XmmVar& var0, XmmVar& var1, const char* op)
+//! {
+//! uint code = kInstNone;
+//!
+//! if (strcmp(op, "ADD") == 0)
+//! code = kX86InstAddSS;
+//! else if (strcmp(op, "SUBTRACT") == 0)
+//! code = kX86InstSubSS;
+//! else if (strcmp(op, "MULTIPLY") == 0)
+//! code = kX86InstMulSS;
+//! else if (strcmp(op, "DIVIDE") == 0)
+//! code = kX86InstDivSS;
+//! else
+//! // Invalid parameter?
+//! return false;
+//!
+//! c.emit(code, var0, var1);
+//! }
+//! @endcode
+//!
+//! Other use cases are waiting for you! Be sure that instruction you are
+//! emitting is correct and encodable, because if not, Assembler will set
+//! error code to @c kErrorUnknownInstruction.
+//!
+//! @section AsmJit_Compiler_CompilerDetails Compiler Details
+//!
+//! This section is here for people interested in the compiling process. There
+//! are few steps that must be done for each compiled function (or your code).
+//!
+//! When your @c Compiler instance is ready, you can create function and add
+//! compiler-items using intrinsics or higher level methods implemented by the
+//! @c AsmJit::Compiler. When you are done (all instructions serialized) you
+//! should call @c AsmJit::Compiler::make() method which will analyze your code,
+//! allocate registers and memory for local variables and serialize all items
+//! to @c AsmJit::Assembler instance. Next steps shows what's done internally
+//! before code is serialized into @c AsmJit::Assembler
+//! (implemented in @c AsmJit::Compiler::serialize() method).
+//!
+//! 1. Compiler try to match function and end-function items (these items
+//! define function body and blocks).
+//!
+//! 2. For all items inside the function-body the virtual functions
+//! are called in this order:
+//! - CompilerItem::prepare()
+//! - CompilerItem::translate()
+//! - CompilerItem::emit()
+//! - CompilerItem::post()
+//!
+//! There is some extra work when emitting function prolog / epilog and
+//! register allocator.
+//!
+//! 3. Emit jump tables data.
+//!
+//! When everything here ends, @c AsmJit::Assembler contains binary stream
+//! that needs only relocation to be callable by C/C++ code.
+//!
+//! @section AsmJit_Compiler_Differences Summary of Differences between @c Assembler and @c Compiler
+//!
+//! - Instructions are not translated to machine code immediately, they are
+//! stored as emmitables, see @c AsmJit::CompilerItem.
+//! - Contains function builder and ability to call other functions.
+//! - Contains register allocator and variable management.
+//! - Contains a lot of helper methods to simplify the code generation not
+//! available/possible in @c AsmJit::Assembler.
+//! - Ability to pre-process or post-process the code which is being generated.
+struct X86Compiler : public Compiler
+{
+ // Special X86 instructions:
+ // - cpuid,
+ // - cbw, cwd, cwde, cdq, cdqe, cqo
+ // - cmpxchg
+ // - cmpxchg8b, cmpxchg16b,
+ // - daa, das,
+ // - imul, mul, idiv, div,
+ // - mov_ptr
+ // - lahf, sahf
+ // - maskmovq, maskmovdqu
+ // - enter, leave
+ // - ret
+ // - monitor, mwait
+ // - pop, popad, popfd, popfq,
+ // - push, pushad, pushfd, pushfq
+ // - rcl, rcr, rol, ror, sal, sar, shl, shr
+ // - shld, shrd
+ // - rdtsc. rdtscp
+ // - lodsb, lodsd, lodsq, lodsw
+ // - movsb, movsd, movsq, movsw
+ // - stosb, stosd, stosq, stosw
+ // - cmpsb, cmpsd, cmpsq, cmpsw
+ // - scasb, scasd, scasq, scasw
+ //
+ // Special X87 instructions:
+ // - fisttp
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a @ref X86Compiler instance.
+ ASMJIT_API X86Compiler(Context* context = JitContext::getGlobal());
+ //! @brief Destroy the @ref X86Compiler instance.
+ ASMJIT_API ~X86Compiler();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get current function as @ref X86CompilerFuncDecl.
+ //!
+ //! This method can be called within @c newFunc() and @c endFunc()
+ //! block to get current function you are working with. It's recommended
+ //! to store @c AsmJit::Function pointer returned by @c newFunc<> method,
+ //! because this allows you in future implement function sections outside of
+ //! function itself (yeah, this is possible!).
+ X86CompilerFuncDecl* getFunc() const
+ { return reinterpret_cast<X86CompilerFuncDecl*>(_func); }
+
+ // --------------------------------------------------------------------------
+ // [Function Builder]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new function.
+ //!
+ //! @param cconv Calling convention to use (see @c kX86FuncConv enum)
+ //! @param params Function arguments prototype.
+ //!
+ //! This method is usually used as a first step when generating functions
+ //! by @c Compiler. First parameter @a cconv specifies function calling
+ //! convention to use. Second parameter @a params specifies function
+ //! arguments. To create function arguments are used templates
+ //! @c BuildFunction0<>, @c BuildFunction1<...>, @c BuildFunction2<...>,
+ //! etc...
+ //!
+ //! Templates with BuildFunction prefix are used to generate argument IDs
+ //! based on real C++ types. See next example how to generate function with
+ //! two 32-bit integer arguments.
+ //!
+ //! @code
+ //! // Building function using AsmJit::Compiler example.
+ //!
+ //! // Compiler instance
+ //! X86Compiler c;
+ //!
+ //! // Begin of function (also emits function @c Prolog)
+ //! c.newFunc(
+ //! // Default calling convention (32-bit cdecl or 64-bit for host OS)
+ //! kX86FuncConvDefault,
+ //! // Using function builder to generate arguments list
+ //! BuildFunction2<int, int>());
+ //!
+ //! // End of function (also emits function @c Epilog)
+ //! c.endFunc();
+ //! @endcode
+ //!
+ //! You can see that building functions is really easy. Previous code snipped
+ //! will generate code for function with two 32-bit integer arguments. You
+ //! can access arguments by @c AsmJit::Function::argument() method. Arguments
+ //! are indexed from 0 (like everything in C).
+ //!
+ //! @code
+ //! // Accessing function arguments through AsmJit::Function example.
+ //!
+ //! // Compiler instance
+ //! X86Compiler c;
+ //!
+ //! // Begin of function (also emits function @c Prolog)
+ //! c.newFunc(
+ //! // Default calling convention (32-bit cdecl or 64-bit for host OS)
+ //! kX86FuncConvDefault,
+ //! // Using function builder to generate arguments list
+ //! BuildFunction2<int, int>());
+ //!
+ //! // Arguments are like other variables, you need to reference them by
+ //! // variable operands:
+ //! GpVar a0 = c.getGpArg(0);
+ //! GpVar a1 = c.getGpArg(1);
+ //!
+ //! // Use them.
+ //! c.add(a0, a1);
+ //!
+ //! // End of function (emits function epilog and return)
+ //! c.endFunc();
+ //! @endcode
+ //!
+ //! Arguments are like variables. How to manipulate with variables is
+ //! documented in @c AsmJit::Compiler, variables section.
+ //!
+ //! @note To get current function use @c currentFunction() method or save
+ //! pointer to @c AsmJit::Function returned by @c AsmJit::Compiler::newFunc<>
+ //! method. Recommended is to save the pointer.
+ //!
+ //! @sa @c BuildFunction0, @c BuildFunction1, @c BuildFunction2, ...
+ X86CompilerFuncDecl* newFunc(uint32_t convention, const FuncPrototype& func)
+ { return newFunc_(convention, func.getReturnType(), func.getArguments(), func.getArgumentsCount()); }
+
+ //! @brief Create a new function (low level version).
+ //!
+ //! @param cconv Function calling convention (see @c AsmJit::kX86FuncConv).
+ //! @param args Function arguments (see @c AsmJit::kX86VarType).
+ //! @param count Arguments count.
+ //!
+ //! This method is internally called from @c newFunc() method and
+ //! contains arguments thats used internally by @c AsmJit::Compiler.
+ //!
+ //! @note To get current function use @c currentFunction() method.
+ ASMJIT_API X86CompilerFuncDecl* newFunc_(uint32_t convenion, uint32_t returnType, const uint32_t* arguments, uint32_t argumentsCount);
+
+ //! @brief End of current function scope and all variables.
+ ASMJIT_API X86CompilerFuncDecl* endFunc();
+
+ // --------------------------------------------------------------------------
+ // [Emit]
+ // --------------------------------------------------------------------------
+
+ //! @brief Emit instruction with no operand.
+ ASMJIT_API void _emitInstruction(uint32_t code);
+
+ //! @brief Emit instruction with one operand.
+ ASMJIT_API void _emitInstruction(uint32_t code, const Operand* o0);
+
+ //! @brief Emit instruction with two operands.
+ ASMJIT_API void _emitInstruction(uint32_t code, const Operand* o0, const Operand* o1);
+
+ //! @brief Emit instruction with three operands.
+ ASMJIT_API void _emitInstruction(uint32_t code, const Operand* o0, const Operand* o1, const Operand* o2);
+
+ //! @brief Emit instruction with four operands (Special instructions).
+ ASMJIT_API void _emitInstruction(uint32_t code, const Operand* o0, const Operand* o1, const Operand* o2, const Operand* o3);
+
+ //! @brief Emit instruction with five operands (Special instructions).
+ ASMJIT_API void _emitInstruction(uint32_t code, const Operand* o0, const Operand* o1, const Operand* o2, const Operand* o3, const Operand* o4);
+
+ //! @brief Private method for emitting jcc.
+ ASMJIT_API void _emitJcc(uint32_t code, const Label* label, uint32_t hint);
+
+ //! @brief Private method for emitting function call.
+ ASMJIT_API X86CompilerFuncCall* _emitCall(const Operand* o0);
+
+ //! @brief Private method for returning a value from the function.
+ ASMJIT_API void _emitReturn(const Operand* first, const Operand* second);
+
+ // --------------------------------------------------------------------------
+ // [Align]
+ // --------------------------------------------------------------------------
+
+ //! @brief Align target buffer to @a m bytes.
+ //!
+ //! Typical usage of this is to align labels at start of the inner loops.
+ //!
+ //! Inserts @c nop() instructions or CPU optimized NOPs.
+ ASMJIT_API void align(uint32_t m);
+
+ // --------------------------------------------------------------------------
+ // [Label]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create and return new label.
+ ASMJIT_API Label newLabel();
+
+ //! @brief Bind label to the current offset.
+ //!
+ //! @note Label can be bound only once!
+ ASMJIT_API void bind(const Label& label);
+
+ // --------------------------------------------------------------------------
+ // [Variables]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get compiler variable at @a id.
+ X86CompilerVar* _getVar(uint32_t id) const
+ {
+ ASMJIT_ASSERT(id != kInvalidValue);
+ return reinterpret_cast<X86CompilerVar*>(_vars[id & kOperandIdValueMask]);
+ }
+
+ //! @internal
+ //!
+ //! @brief Create a new variable data.
+ ASMJIT_API X86CompilerVar* _newVar(const char* name, uint32_t type, uint32_t size);
+
+ //! @brief Create a new general-purpose variable.
+ ASMJIT_API GpVar newGpVar(uint32_t varType = kX86VarTypeGpz, const char* name = nullptr);
+ //! @brief Get argument as general-purpose variable.
+ ASMJIT_API GpVar getGpArg(uint32_t argIndex);
+
+ //! @brief Create a new MM variable.
+ ASMJIT_API MmVar newMmVar(uint32_t varType = kX86VarTypeMm, const char* name = nullptr);
+ //! @brief Get argument as MM variable.
+ ASMJIT_API MmVar getMmArg(uint32_t argIndex);
+
+ //! @brief Create a new XMM variable.
+ ASMJIT_API XmmVar newXmmVar(uint32_t varType = kX86VarTypeXmm, const char* name = nullptr);
+ //! @brief Get argument as XMM variable.
+ ASMJIT_API XmmVar getXmmArg(uint32_t argIndex);
+
+ //! @internal
+ //!
+ //! @brief Serialize variable hint.
+ ASMJIT_API void _vhint(Var& var, uint32_t hintId, uint32_t hintValue);
+
+ //! @brief Alloc variable @a var.
+ ASMJIT_API void alloc(Var& var);
+ //! @brief Alloc variable @a var using @a regIndex as a register index.
+ ASMJIT_API void alloc(Var& var, uint32_t regIndex);
+ //! @brief Alloc variable @a var using @a reg as a demanded register.
+ ASMJIT_API void alloc(Var& var, const Reg& reg);
+ //! @brief Spill variable @a var.
+ ASMJIT_API void spill(Var& var);
+ //! @brief Save variable @a var if modified.
+ ASMJIT_API void save(Var& var);
+ //! @brief Unuse variable @a var.
+ ASMJIT_API void unuse(Var& var);
+
+ //! @brief Get memory home of variable @a var.
+ ASMJIT_API void getMemoryHome(Var& var, GpVar* home, int* displacement = nullptr);
+
+ //! @brief Set memory home of variable @a var.
+ //!
+ //! Default memory home location is on stack (ESP/RSP), but when needed the
+ //! bebahior can be changed by this method.
+ //!
+ //! It is an error to chaining memory home locations. For example the given
+ //! code is invalid:
+ //!
+ //! @code
+ //! X86Compiler c;
+ //!
+ //! ...
+ //! GpVar v0 = c.newGpVar();
+ //! GpVar v1 = c.newGpVar();
+ //! GpVar v2 = c.newGpVar();
+ //! GpVar v3 = c.newGpVar();
+ //!
+ //! c.setMemoryHome(v1, v0, 0); // Allowed, [v0] is memory home for v1.
+ //! c.setMemoryHome(v2, v0, 4); // Allowed, [v0+4] is memory home for v2.
+ //! c.setMemoryHome(v3, v2); // CHAINING, NOT ALLOWED!
+ //! @endcode
+ ASMJIT_API void setMemoryHome(Var& var, const GpVar& home, int displacement = 0);
+
+ //! @brief Get priority of variable @a var.
+ ASMJIT_API uint32_t getPriority(Var& var) const;
+ //! @brief Set priority of variable @a var to @a priority.
+ ASMJIT_API void setPriority(Var& var, uint32_t priority);
+
+ //! @brief Get save-on-unuse @a var property.
+ ASMJIT_API bool getSaveOnUnuse(Var& var) const;
+ //! @brief Set save-on-unuse @a var property to @a value.
+ ASMJIT_API void setSaveOnUnuse(Var& var, bool value);
+
+ //! @brief Rename variable @a var to @a name.
+ //!
+ //! @note Only new name will appear in the logger.
+ ASMJIT_API void rename(Var& var, const char* name);
+
+ // --------------------------------------------------------------------------
+ // [State]
+ // --------------------------------------------------------------------------
+
+ //! @internal
+ //!
+ //! @brief Create a new @ref X86CompilerState.
+ ASMJIT_API X86CompilerState* _newState(uint32_t memVarsCount);
+
+ // --------------------------------------------------------------------------
+ // [Make]
+ // --------------------------------------------------------------------------
+
+ //! @brief Make is convenience method to make currently serialized code and
+ //! return pointer to generated function.
+ //!
+ //! What you need is only to cast this pointer to your function type and call
+ //! it. Note that if there was an error and calling @c getError() method doesn't
+ //! return @c kErrorOk (zero) then this function always returns @c NULL and
+ //! error value remains the same.
+ ASMJIT_API virtual void* make();
+
+ //! @brief Method that will emit everything to @c Assembler instance @a a.
+ ASMJIT_API virtual void serialize(Assembler& a);
+
+ // --------------------------------------------------------------------------
+ // [Data]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get target from label @a id.
+ X86CompilerTarget* _getTarget(uint32_t id)
+ {
+ ASMJIT_ASSERT((id & kOperandIdTypeMask) == kOperandIdTypeLabel);
+ return reinterpret_cast<X86CompilerTarget*>(_targets[id & kOperandIdValueMask]);
+ }
+
+ // --------------------------------------------------------------------------
+ // [Embed]
+ // --------------------------------------------------------------------------
+
+ //! @brief Add 8-bit integer data to the instuction stream.
+ void db(uint8_t x) { embed(&x, 1); }
+ //! @brief Add 16-bit integer data to the instuction stream.
+ void dw(uint16_t x) { embed(&x, 2); }
+ //! @brief Add 32-bit integer data to the instuction stream.
+ void dd(uint32_t x) { embed(&x, 4); }
+ //! @brief Add 64-bit integer data to the instuction stream.
+ void dq(uint64_t x) { embed(&x, 8); }
+
+ //! @brief Add 8-bit integer data to the instuction stream.
+ void dint8(int8_t x) { embed(&x, sizeof(int8_t)); }
+ //! @brief Add 8-bit integer data to the instuction stream.
+ void duint8(uint8_t x) { embed(&x, sizeof(uint8_t)); }
+
+ //! @brief Add 16-bit integer data to the instuction stream.
+ void dint16(int16_t x) { embed(&x, sizeof(int16_t)); }
+ //! @brief Add 16-bit integer data to the instuction stream.
+ void duint16(uint16_t x) { embed(&x, sizeof(uint16_t)); }
+
+ //! @brief Add 32-bit integer data to the instuction stream.
+ void dint32(int32_t x) { embed(&x, sizeof(int32_t)); }
+ //! @brief Add 32-bit integer data to the instuction stream.
+ void duint32(uint32_t x) { embed(&x, sizeof(uint32_t)); }
+
+ //! @brief Add 64-bit integer data to the instuction stream.
+ void dint64(int64_t x) { embed(&x, sizeof(int64_t)); }
+ //! @brief Add 64-bit integer data to the instuction stream.
+ void duint64(uint64_t x) { embed(&x, sizeof(uint64_t)); }
+
+ //! @brief Add system-integer data to the instuction stream.
+ void dintptr(intptr_t x) { embed(&x, sizeof(intptr_t)); }
+ //! @brief Add system-integer data to the instuction stream.
+ void duintptr(uintptr_t x) { embed(&x, sizeof(uintptr_t)); }
+
+ //! @brief Add float data to the instuction stream.
+ void dfloat(float x) { embed(&x, sizeof(float)); }
+ //! @brief Add double data to the instuction stream.
+ void ddouble(double x) { embed(&x, sizeof(double)); }
+
+ //! @brief Add pointer data to the instuction stream.
+ void dptr(void* x) { embed(&x, sizeof(void*)); }
+
+ //! @brief Add MM data to the instuction stream.
+ void dmm(const MmData& x) { embed(&x, sizeof(MmData)); }
+ //! @brief Add XMM data to the instuction stream.
+ void dxmm(const XmmData& x) { embed(&x, sizeof(XmmData)); }
+
+ //! @brief Add data to the instuction stream.
+ void data(const void* data, size_t size) { embed(data, size); }
+
+ //! @brief Add data in a given structure instance to the instuction stream.
+ template<typename T>
+ void dstruct(const T& x) { embed(&x, sizeof(T)); }
+
+ // --------------------------------------------------------------------------
+ // [Custom Instructions]
+ // --------------------------------------------------------------------------
+
+ // These emitters are used by custom compiler code (register alloc / spill,
+ // prolog / epilog generator, ...).
+
+ void emit(uint32_t code)
+ { _emitInstruction(code); }
+
+ void emit(uint32_t code, const Operand& o0)
+ { _emitInstruction(code, &o0); }
+
+ void emit(uint32_t code, const Operand& o0, const Operand& o1)
+ { _emitInstruction(code, &o0, &o1); }
+
+ void emit(uint32_t code, const Operand& o0, const Operand& o1, const Operand& o2)
+ { _emitInstruction(code, &o0, &o1, &o2); }
+
+ // --------------------------------------------------------------------------
+ // [X86 Instructions]
+ // --------------------------------------------------------------------------
+
+ //! @brief Add with Carry.
+ void adc(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstAdc, &dst, &src); }
+
+ //! @brief Add with Carry.
+ void adc(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstAdc, &dst, &src); }
+
+ //! @brief Add with Carry.
+ void adc(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstAdc, &dst, &src); }
+
+ //! @brief Add with Carry.
+ void adc(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstAdc, &dst, &src); }
+
+ //! @brief Add with Carry.
+ void adc(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstAdc, &dst, &src); }
+
+ //! @brief Add.
+ void add(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstAdd, &dst, &src); }
+
+ //! @brief Add.
+ void add(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstAdd, &dst, &src); }
+
+ //! @brief Add.
+ void add(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstAdd, &dst, &src); }
+
+ //! @brief Add.
+ void add(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstAdd, &dst, &src); }
+
+ //! @brief Add.
+ void add(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstAdd, &dst, &src); }
+
+ //! @brief Logical And.
+ void and_(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstAnd, &dst, &src); }
+
+ //! @brief Logical And.
+ void and_(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstAnd, &dst, &src); }
+
+ //! @brief Logical And.
+ void and_(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstAnd, &dst, &src); }
+
+ //! @brief Logical And.
+ void and_(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstAnd, &dst, &src); }
+
+ //! @brief Logical And.
+ void and_(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstAnd, &dst, &src); }
+
+ //! @brief Bit Scan Forward.
+ void bsf(const GpVar& dst, const GpVar& src)
+ {
+ ASMJIT_ASSERT(!dst.isGpb());
+ _emitInstruction(kX86InstBsf, &dst, &src);
+ }
+
+ //! @brief Bit Scan Forward.
+ void bsf(const GpVar& dst, const Mem& src)
+ {
+ ASMJIT_ASSERT(!dst.isGpb());
+ _emitInstruction(kX86InstBsf, &dst, &src);
+ }
+
+ //! @brief Bit Scan Reverse.
+ void bsr(const GpVar& dst, const GpVar& src)
+ {
+ ASMJIT_ASSERT(!dst.isGpb());
+ _emitInstruction(kX86InstBsr, &dst, &src);
+ }
+
+ //! @brief Bit Scan Reverse.
+ void bsr(const GpVar& dst, const Mem& src)
+ {
+ ASMJIT_ASSERT(!dst.isGpb());
+ _emitInstruction(kX86InstBsr, &dst, &src);
+ }
+
+ //! @brief Byte swap (32-bit or 64-bit registers only) (i486).
+ void bswap(const GpVar& dst)
+ {
+ // ASMJIT_ASSERT(dst.getRegType() == kX86RegGPD || dst.getRegType() == kX86RegGPQ);
+ _emitInstruction(kX86InstBSwap, &dst);
+ }
+
+ //! @brief Bit test.
+ void bt(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstBt, &dst, &src); }
+
+ //! @brief Bit test.
+ void bt(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstBt, &dst, &src); }
+
+ //! @brief Bit test.
+ void bt(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstBt, &dst, &src); }
+
+ //! @brief Bit test.
+ void bt(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstBt, &dst, &src); }
+
+ //! @brief Bit test and complement.
+ void btc(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstBtc, &dst, &src); }
+
+ //! @brief Bit test and complement.
+ void btc(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstBtc, &dst, &src); }
+
+ //! @brief Bit test and complement.
+ void btc(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstBtc, &dst, &src); }
+
+ //! @brief Bit test and complement.
+ void btc(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstBtc, &dst, &src); }
+
+ //! @brief Bit test and reset.
+ void btr(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstBtr, &dst, &src); }
+
+ //! @brief Bit test and reset.
+ void btr(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstBtr, &dst, &src); }
+
+ //! @brief Bit test and reset.
+ void btr(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstBtr, &dst, &src); }
+
+ //! @brief Bit test and reset.
+ void btr(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstBtr, &dst, &src); }
+
+ //! @brief Bit test and set.
+ void bts(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstBts, &dst, &src); }
+
+ //! @brief Bit test and set.
+ void bts(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstBts, &dst, &src); }
+
+ //! @brief Bit test and set.
+ void bts(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstBts, &dst, &src); }
+
+ //! @brief Bit test and set.
+ void bts(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstBts, &dst, &src); }
+
+ //! @brief Call Procedure.
+ X86CompilerFuncCall* call(const GpVar& dst)
+ { return _emitCall(&dst); }
+
+ //! @brief Call Procedure.
+ X86CompilerFuncCall* call(const Mem& dst)
+ { return _emitCall(&dst); }
+
+ //! @brief Call Procedure.
+ X86CompilerFuncCall* call(const Imm& dst)
+ { return _emitCall(&dst); }
+
+ //! @brief Call Procedure.
+ //! @overload
+ X86CompilerFuncCall* call(void* dst)
+ {
+ Imm imm((sysint_t)dst);
+ return _emitCall(&imm);
+ }
+
+ //! @brief Call Procedure.
+ X86CompilerFuncCall* call(const Label& label)
+ { return _emitCall(&label); }
+
+ //! @brief Convert Byte to Word (Sign Extend).
+ void cbw(const GpVar& dst)
+ { _emitInstruction(kX86InstCbw, &dst); }
+
+ //! @brief Convert Word to DWord (Sign Extend).
+ void cwd(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstCwd, &dst, &src); }
+
+ //! @brief Convert Word to DWord (Sign Extend).
+ void cwde(const GpVar& dst)
+ { _emitInstruction(kX86InstCwde, &dst); }
+
+ //! @brief Convert Word to DWord (Sign Extend).
+ void cdq(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstCdq, &dst, &src); }
+
+#if defined(ASMJIT_X64)
+ //! @brief Convert DWord to QWord (Sign Extend).
+ void cdqe(const GpVar& dst)
+ { _emitInstruction(kX86InstCdqe, &dst); }
+#endif // ASMJIT_X64
+
+#if defined(ASMJIT_X64)
+ //! @brief Convert QWord to DQWord (Sign Extend).
+ void cqo(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstCqo, &dst, &src); }
+#endif // ASMJIT_X64
+
+ //! @brief Clear Carry flag
+ //!
+ //! This instruction clears the CF flag in the EFLAGS register.
+ void clc()
+ { _emitInstruction(kX86InstClc); }
+
+ //! @brief Clear Direction flag
+ //!
+ //! This instruction clears the DF flag in the EFLAGS register.
+ void cld()
+ { _emitInstruction(kX86InstCld); }
+
+ //! @brief Complement Carry Flag.
+ //!
+ //! This instruction complements the CF flag in the EFLAGS register.
+ //! (CF = NOT CF)
+ void cmc()
+ { _emitInstruction(kX86InstCmc); }
+
+ //! @brief Conditional Move.
+ void cmov(kX86Cond cc, const GpVar& dst, const GpVar& src)
+ { _emitInstruction(X86Util::getCMovccInstFromCond(cc), &dst, &src); }
+
+ //! @brief Conditional Move.
+ void cmov(kX86Cond cc, const GpVar& dst, const Mem& src)
+ { _emitInstruction(X86Util::getCMovccInstFromCond(cc), &dst, &src); }
+
+ //! @brief Conditional Move.
+ void cmova (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovA , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmova (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovA , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovae (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovAE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovae (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovAE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovb (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovB , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovb (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovB , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovbe (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovBE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovbe (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovBE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovc (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovC , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovc (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovC , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmove (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmove (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovg (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovG , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovg (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovG , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovge (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovGE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovge (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovGE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovl (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovL , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovl (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovL , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovle (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovLE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovle (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovLE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovna (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovNA , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovna (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovNA , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnae(const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovNAE, &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnae(const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovNAE, &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnb (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovNB , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnb (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovNB , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnbe(const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovNBE, &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnbe(const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovNBE, &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnc (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovNC , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnc (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovNC , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovne (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovNE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovne (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovNE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovng (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovNG , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovng (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovNG , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnge(const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovNGE, &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnge(const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovNGE, &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnl (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovNL , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnl (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovNL , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnle(const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovNLE, &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnle(const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovNLE, &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovno (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovNO , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovno (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovNO , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnp (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovNP , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnp (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovNP , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovns (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovNS , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovns (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovNS , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnz (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovNZ , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovnz (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovNZ , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovo (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovO , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovo (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovO , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovp (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovP , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovp (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovP , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovpe (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovPE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovpe (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovPE , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovpo (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovPO , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovpo (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovPO , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovs (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovS , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovs (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovS , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovz (const GpVar& dst, const GpVar& src) { _emitInstruction(kX86InstCMovZ , &dst, &src); }
+ //! @brief Conditional Move.
+ void cmovz (const GpVar& dst, const Mem& src) { _emitInstruction(kX86InstCMovZ , &dst, &src); }
+
+ //! @brief Compare Two Operands.
+ void cmp(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstCmp, &dst, &src); }
+
+ //! @brief Compare Two Operands.
+ void cmp(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCmp, &dst, &src); }
+
+ //! @brief Compare Two Operands.
+ void cmp(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstCmp, &dst, &src); }
+
+ //! @brief Compare Two Operands.
+ void cmp(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstCmp, &dst, &src); }
+
+ //! @brief Compare Two Operands.
+ void cmp(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstCmp, &dst, &src); }
+
+ //! @brief Compare and Exchange (i486).
+ void cmpxchg(const GpVar cmp_1_eax, const GpVar& cmp_2, const GpVar& src)
+ {
+ ASMJIT_ASSERT(cmp_1_eax.getId() != src.getId());
+ _emitInstruction(kX86InstCmpXCHG, &cmp_1_eax, &cmp_2, &src);
+ }
+
+ //! @brief Compare and Exchange (i486).
+ void cmpxchg(const GpVar cmp_1_eax, const Mem& cmp_2, const GpVar& src)
+ {
+ ASMJIT_ASSERT(cmp_1_eax.getId() != src.getId());
+ _emitInstruction(kX86InstCmpXCHG, &cmp_1_eax, &cmp_2, &src);
+ }
+
+ //! @brief Compares the 64-bit value in EDX:EAX with the memory operand (Pentium).
+ //!
+ //! If the values are equal, then this instruction stores the 64-bit value
+ //! in ECX:EBX into the memory operand and sets the zero flag. Otherwise,
+ //! this instruction copies the 64-bit memory operand into the EDX:EAX
+ //! registers and clears the zero flag.
+ void cmpxchg8b(
+ const GpVar& cmp_edx, const GpVar& cmp_eax,
+ const GpVar& cmp_ecx, const GpVar& cmp_ebx,
+ const Mem& dst)
+ {
+ ASMJIT_ASSERT(cmp_edx.getId() != cmp_eax.getId() &&
+ cmp_eax.getId() != cmp_ecx.getId() &&
+ cmp_ecx.getId() != cmp_ebx.getId());
+
+ _emitInstruction(kX86InstCmpXCHG8B, &cmp_edx, &cmp_eax, &cmp_ecx, &cmp_ebx, &dst);
+ }
+
+#if defined(ASMJIT_X64)
+ //! @brief Compares the 128-bit value in RDX:RAX with the memory operand (X64).
+ //!
+ //! If the values are equal, then this instruction stores the 128-bit value
+ //! in RCX:RBX into the memory operand and sets the zero flag. Otherwise,
+ //! this instruction copies the 128-bit memory operand into the RDX:RAX
+ //! registers and clears the zero flag.
+ void cmpxchg16b(
+ const GpVar& cmp_edx, const GpVar& cmp_eax,
+ const GpVar& cmp_ecx, const GpVar& cmp_ebx,
+ const Mem& dst)
+ {
+ ASMJIT_ASSERT(cmp_edx.getId() != cmp_eax.getId() &&
+ cmp_eax.getId() != cmp_ecx.getId() &&
+ cmp_ecx.getId() != cmp_ebx.getId());
+
+ _emitInstruction(kX86InstCmpXCHG16B, &cmp_edx, &cmp_eax, &cmp_ecx, &cmp_ebx, &dst);
+ }
+#endif // ASMJIT_X64
+
+ //! @brief CPU Identification (i486).
+ void cpuid(
+ const GpVar& inout_eax,
+ const GpVar& out_ebx,
+ const GpVar& out_ecx,
+ const GpVar& out_edx)
+ {
+ // Destination variables must be different.
+ ASMJIT_ASSERT(inout_eax.getId() != out_ebx.getId() &&
+ out_ebx.getId() != out_ecx.getId() &&
+ out_ecx.getId() != out_edx.getId());
+
+ _emitInstruction(kX86InstCpuId, &inout_eax, &out_ebx, &out_ecx, &out_edx);
+ }
+
+#if defined(ASMJIT_X86)
+ void daa(const GpVar& dst)
+ { _emitInstruction(kX86InstDaa, &dst); }
+#endif // ASMJIT_X86
+
+#if defined(ASMJIT_X86)
+ void das(const GpVar& dst)
+ { _emitInstruction(kX86InstDas, &dst); }
+#endif // ASMJIT_X86
+
+ //! @brief Decrement by 1.
+ //! @note This instruction can be slower than sub(dst, 1)
+ void dec(const GpVar& dst)
+ { _emitInstruction(kX86InstDec, &dst); }
+
+ //! @brief Decrement by 1.
+ //! @note This instruction can be slower than sub(dst, 1)
+ void dec(const Mem& dst)
+ { _emitInstruction(kX86InstDec, &dst); }
+
+ //! @brief Unsigned divide.
+ //!
+ //! This instruction divides (unsigned) the value in the AL, AX, or EAX
+ //! register by the source operand and stores the result in the AX,
+ //! DX:AX, or EDX:EAX registers.
+ void div(const GpVar& dst_rem, const GpVar& dst_quot, const GpVar& src)
+ {
+ // Destination variables must be different.
+ ASMJIT_ASSERT(dst_rem.getId() != dst_quot.getId());
+ _emitInstruction(kX86InstDiv, &dst_rem, &dst_quot, &src);
+ }
+
+ //! @brief Unsigned divide.
+ //! @overload
+ void div(const GpVar& dst_rem, const GpVar& dst_quot, const Mem& src)
+ {
+ // Destination variables must be different.
+ ASMJIT_ASSERT(dst_rem.getId() != dst_quot.getId());
+ _emitInstruction(kX86InstDiv, &dst_rem, &dst_quot, &src);
+ }
+
+#if ASMJIT_NOT_SUPPORTED_BY_COMPILER
+ //! @brief Make Stack Frame for Procedure Parameters.
+ void enter(const Imm& imm16, const Imm& imm8)
+ { _emitInstruction(kX86InstEnter, &imm16, &imm8); }
+#endif // ASMJIT_NOT_SUPPORTED_BY_COMPILER
+
+ //! @brief Signed divide.
+ //!
+ //! This instruction divides (signed) the value in the AL, AX, or EAX
+ //! register by the source operand and stores the result in the AX,
+ //! DX:AX, or EDX:EAX registers.
+ void idiv(const GpVar& dst_rem, const GpVar& dst_quot, const GpVar& src)
+ {
+ // Destination variables must be different.
+ ASMJIT_ASSERT(dst_rem.getId() != dst_quot.getId());
+ _emitInstruction(kX86InstIDiv, &dst_rem, &dst_quot, &src);
+ }
+
+ //! @brief Signed divide.
+ //! @overload
+ void idiv(const GpVar& dst_rem, const GpVar& dst_quot, const Mem& src)
+ {
+ // Destination variables must be different.
+ ASMJIT_ASSERT(dst_rem.getId() != dst_quot.getId());
+ _emitInstruction(kX86InstIDiv, &dst_rem, &dst_quot, &src);
+ }
+
+ //! @brief Signed multiply.
+ //!
+ //! [dst_lo:dst_hi] = dst_hi * src.
+ void imul(const GpVar& dst_hi, const GpVar& dst_lo, const GpVar& src)
+ {
+ // Destination variables must be different.
+ ASMJIT_ASSERT(dst_hi.getId() != dst_lo.getId());
+ _emitInstruction(kX86InstIMul, &dst_hi, &dst_lo, &src);
+ }
+
+ //! @overload
+ void imul(const GpVar& dst_hi, const GpVar& dst_lo, const Mem& src)
+ {
+ // Destination variables must be different.
+ ASMJIT_ASSERT(dst_hi.getId() != dst_lo.getId());
+ _emitInstruction(kX86InstIMul, &dst_hi, &dst_lo, &src);
+ }
+
+ //! @brief Signed multiply.
+ //!
+ //! Destination operand (the first operand) is multiplied by the source
+ //! operand (second operand). The destination operand is a general-purpose
+ //! register and the source operand is an immediate value, a general-purpose
+ //! register, or a memory location. The product is then stored in the
+ //! destination operand location.
+ void imul(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstIMul, &dst, &src); }
+
+ //! @brief Signed multiply.
+ //! @overload
+ void imul(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstIMul, &dst, &src); }
+
+ //! @brief Signed multiply.
+ //! @overload
+ void imul(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstIMul, &dst, &src); }
+
+ //! @brief Signed multiply.
+ //!
+ //! source operand (which can be a general-purpose register or a memory
+ //! location) is multiplied by the second source operand (an immediate
+ //! value). The product is then stored in the destination operand
+ //! (a general-purpose register).
+ void imul(const GpVar& dst, const GpVar& src, const Imm& imm)
+ { _emitInstruction(kX86InstIMul, &dst, &src, &imm); }
+
+ //! @overload
+ void imul(const GpVar& dst, const Mem& src, const Imm& imm)
+ { _emitInstruction(kX86InstIMul, &dst, &src, &imm); }
+
+ //! @brief Increment by 1.
+ //! @note This instruction can be slower than add(dst, 1)
+ void inc(const GpVar& dst)
+ { _emitInstruction(kX86InstInc, &dst); }
+
+ //! @brief Increment by 1.
+ //! @note This instruction can be slower than add(dst, 1)
+ void inc(const Mem& dst)
+ { _emitInstruction(kX86InstInc, &dst); }
+
+ //! @brief Interrupt 3 - trap to debugger.
+ void int3()
+ { _emitInstruction(kX86InstInt3); }
+
+ //! @brief Jump to label @a label if condition @a cc is met.
+ //!
+ //! This instruction checks the state of one or more of the status flags in
+ //! the EFLAGS register (CF, OF, PF, SF, and ZF) and, if the flags are in the
+ //! specified state (condition), performs a jump to the target instruction
+ //! specified by the destination operand. A condition code (cc) is associated
+ //! with each instruction to indicate the condition being tested for. If the
+ //! condition is not satisfied, the jump is not performed and execution
+ //! continues with the instruction following the Jcc instruction.
+ void j(kX86Cond cc, const Label& label, uint32_t hint = kCondHintNone)
+ { _emitJcc(X86Util::getJccInstFromCond(cc), &label, hint); }
+
+ //! @brief Jump to label @a label if condition is met.
+ void ja (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJA , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jae (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJAE , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jb (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJB , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jbe (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJBE , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jc (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJC , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void je (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJE , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jg (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJG , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jge (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJGE , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jl (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJL , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jle (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJLE , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jna (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNA , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jnae(const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNAE, &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jnb (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNB , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jnbe(const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNBE, &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jnc (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNC , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jne (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNE , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jng (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNG , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jnge(const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNGE, &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jnl (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNL , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jnle(const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNLE, &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jno (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNO , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jnp (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNP , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jns (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNS , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jnz (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJNZ , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jo (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJO , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jp (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJP , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jpe (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJPE , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jpo (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJPO , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void js (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJS , &label, hint); }
+ //! @brief Jump to label @a label if condition is met.
+ void jz (const Label& label, uint32_t hint = kCondHintNone) { _emitJcc(kX86InstJZ , &label, hint); }
+
+ //! @brief Jump.
+ //! @overload
+ void jmp(const GpVar& dst)
+ { _emitInstruction(kX86InstJmp, &dst); }
+
+ //! @brief Jump.
+ //! @overload
+ void jmp(const Mem& dst)
+ { _emitInstruction(kX86InstJmp, &dst); }
+
+ //! @brief Jump.
+ //! @overload
+ void jmp(const Imm& dst)
+ { _emitInstruction(kX86InstJmp, &dst); }
+
+ //! @brief Jump.
+ //! @overload
+ void jmp(void* dst)
+ {
+ Imm imm((sysint_t)dst);
+ _emitInstruction(kX86InstJmp, &imm);
+ }
+
+ //! @brief Jump.
+ //!
+ //! This instruction transfers program control to a different point
+ //! in the instruction stream without recording return information.
+ //! The destination (target) operand specifies the label of the
+ //! instruction being jumped to.
+ void jmp(const Label& label)
+ { _emitInstruction(kX86InstJmp, &label); }
+
+ //! @brief Load Effective Address
+ //!
+ //! This instruction computes the effective address of the second
+ //! operand (the source operand) and stores it in the first operand
+ //! (destination operand). The source operand is a memory address
+ //! (offset part) specified with one of the processors addressing modes.
+ //! The destination operand is a general-purpose register.
+ void lea(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstLea, &dst, &src); }
+
+#if ASMJIT_NOT_SUPPORTED_BY_COMPILER
+ //! @brief High Level Procedure Exit.
+ void leave()
+ { _emitInstruction(kX86InstLeave); }
+#endif // ASMJIT_NOT_SUPPORTED_BY_COMPILER
+
+ //! @brief Move.
+ //!
+ //! This instruction copies the second operand (source operand) to the first
+ //! operand (destination operand). The source operand can be an immediate
+ //! value, general-purpose register, segment register, or memory location.
+ //! The destination register can be a general-purpose register, segment
+ //! register, or memory location. Both operands must be the same size, which
+ //! can be a byte, a word, or a DWORD.
+ //!
+ //! @note To move MMX or SSE registers to/from GP registers or memory, use
+ //! corresponding functions: @c movd(), @c movq(), etc. Passing MMX or SSE
+ //! registers to @c mov() is illegal.
+ void mov(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstMov, &dst, &src); }
+
+ //! @brief Move.
+ //! @overload
+ void mov(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMov, &dst, &src); }
+
+ //! @brief Move.
+ //! @overload
+ void mov(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstMov, &dst, &src); }
+
+ //! @brief Move.
+ //! @overload
+ void mov(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstMov, &dst, &src); }
+
+ //! @brief Move.
+ //! @overload
+ void mov(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstMov, &dst, &src); }
+
+ //! @brief Move from segment register.
+ //! @overload.
+ void mov(const GpVar& dst, const SegmentReg& src)
+ { _emitInstruction(kX86InstMov, &dst, &src); }
+
+ //! @brief Move from segment register.
+ //! @overload.
+ void mov(const Mem& dst, const SegmentReg& src)
+ { _emitInstruction(kX86InstMov, &dst, &src); }
+
+ //! @brief Move to segment register.
+ //! @overload.
+ void mov(const SegmentReg& dst, const GpVar& src)
+ { _emitInstruction(kX86InstMov, &dst, &src); }
+
+ //! @brief Move to segment register.
+ //! @overload.
+ void mov(const SegmentReg& dst, const Mem& src)
+ { _emitInstruction(kX86InstMov, &dst, &src); }
+
+ //! @brief Move byte, word, dword or qword from absolute address @a src to
+ //! AL, AX, EAX or RAX register.
+ void mov_ptr(const GpVar& dst, void* src)
+ {
+ Imm imm((sysint_t)src);
+ _emitInstruction(kX86InstMovPtr, &dst, &imm);
+ }
+
+ //! @brief Move byte, word, dword or qword from AL, AX, EAX or RAX register
+ //! to absolute address @a dst.
+ void mov_ptr(void* dst, const GpVar& src)
+ {
+ Imm imm((sysint_t)dst);
+ _emitInstruction(kX86InstMovPtr, &imm, &src);
+ }
+
+ //! @brief Move with Sign-Extension.
+ //!
+ //! This instruction copies the contents of the source operand (register
+ //! or memory location) to the destination operand (register) and sign
+ //! extends the value to 16, 32 or 64-bits.
+ //!
+ //! @sa movsxd().
+ void movsx(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstMovSX, &dst, &src); }
+
+ //! @brief Move with Sign-Extension.
+ //! @overload
+ void movsx(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovSX, &dst, &src); }
+
+#if defined(ASMJIT_X64)
+ //! @brief Move DWord to QWord with sign-extension.
+ void movsxd(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstMovSXD, &dst, &src); }
+
+ //! @brief Move DWord to QWord with sign-extension.
+ //! @overload
+ void movsxd(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovSXD, &dst, &src); }
+#endif // ASMJIT_X64
+
+ //! @brief Move with Zero-Extend.
+ //!
+ //! This instruction copies the contents of the source operand (register
+ //! or memory location) to the destination operand (register) and zero
+ //! extends the value to 16 or 32-bits. The size of the converted value
+ //! depends on the operand-size attribute.
+ void movzx(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstMovZX, &dst, &src); }
+
+ //! @brief Move with Zero-Extend.
+ //! @brief Overload
+ void movzx(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovZX, &dst, &src); }
+
+ //! @brief Unsigned multiply.
+ //!
+ //! Source operand (in a general-purpose register or memory location)
+ //! is multiplied by the value in the AL, AX, or EAX register (depending
+ //! on the operand size) and the product is stored in the AX, DX:AX, or
+ //! EDX:EAX registers, respectively.
+ void mul(const GpVar& dst_hi, const GpVar& dst_lo, const GpVar& src)
+ {
+ // Destination variables must be different.
+ ASMJIT_ASSERT(dst_hi.getId() != dst_lo.getId());
+ _emitInstruction(kX86InstMul, &dst_hi, &dst_lo, &src);
+ }
+
+ //! @brief Unsigned multiply.
+ //! @overload
+ void mul(const GpVar& dst_hi, const GpVar& dst_lo, const Mem& src)
+ {
+ // Destination variables must be different.
+ ASMJIT_ASSERT(dst_hi.getId() != dst_lo.getId());
+ _emitInstruction(kX86InstMul, &dst_hi, &dst_lo, &src);
+ }
+
+ //! @brief Two's Complement Negation.
+ void neg(const GpVar& dst)
+ { _emitInstruction(kX86InstNeg, &dst); }
+
+ //! @brief Two's Complement Negation.
+ void neg(const Mem& dst)
+ { _emitInstruction(kX86InstNeg, &dst); }
+
+ //! @brief No Operation.
+ //!
+ //! This instruction performs no operation. This instruction is a one-byte
+ //! instruction that takes up space in the instruction stream but does not
+ //! affect the machine context, except the EIP register. The NOP instruction
+ //! is an alias mnemonic for the XCHG (E)AX, (E)AX instruction.
+ void nop()
+ { _emitInstruction(kX86InstNop); }
+
+ //! @brief One's Complement Negation.
+ void not_(const GpVar& dst)
+ { _emitInstruction(kX86InstNot, &dst); }
+
+ //! @brief One's Complement Negation.
+ void not_(const Mem& dst)
+ { _emitInstruction(kX86InstNot, &dst); }
+
+ //! @brief Logical Inclusive OR.
+ void or_(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstOr, &dst, &src); }
+
+ //! @brief Logical Inclusive OR.
+ void or_(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstOr, &dst, &src); }
+
+ //! @brief Logical Inclusive OR.
+ void or_(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstOr, &dst, &src); }
+
+ //! @brief Logical Inclusive OR.
+ void or_(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstOr, &dst, &src); }
+
+ //! @brief Logical Inclusive OR.
+ void or_(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstOr, &dst, &src); }
+
+ //! @brief Pop a Value from the Stack.
+ //!
+ //! This instruction loads the value from the top of the stack to the location
+ //! specified with the destination operand and then increments the stack pointer.
+ //! The destination operand can be a general purpose register, memory location,
+ //! or segment register.
+ void pop(const GpVar& dst)
+ { _emitInstruction(kX86InstPop, &dst); }
+
+ void pop(const Mem& dst)
+ {
+ ASMJIT_ASSERT(dst.getSize() == 2 || dst.getSize() == sizeof(sysint_t));
+ _emitInstruction(kX86InstPop, &dst);
+ }
+
+#if defined(ASMJIT_X86)
+ //! @brief Pop All General-Purpose Registers.
+ //!
+ //! Pop EDI, ESI, EBP, EBX, EDX, ECX, and EAX.
+ void popad()
+ { _emitInstruction(kX86InstPopAD); }
+#endif // ASMJIT_X86
+
+ //! @brief Pop Stack into EFLAGS Register (32-bit or 64-bit).
+ void popf()
+ {
+#if defined(ASMJIT_X86)
+ popfd();
+#else
+ popfq();
+#endif
+ }
+
+#if defined(ASMJIT_X86)
+ //! @brief Pop Stack into EFLAGS Register (32-bit).
+ void popfd()
+ { _emitInstruction(kX86InstPopFD); }
+#else
+ //! @brief Pop Stack into EFLAGS Register (64-bit).
+ void popfq()
+ { _emitInstruction(kX86InstPopFQ); }
+#endif
+
+ //! @brief Push WORD/DWORD/QWORD Onto the Stack.
+ //!
+ //! @note 32-bit architecture pushed DWORD while 64-bit
+ //! pushes QWORD. 64-bit mode not provides instruction to
+ //! push 32-bit register/memory.
+ void push(const GpVar& src)
+ { _emitInstruction(kX86InstPush, &src); }
+
+ //! @brief Push WORD/DWORD/QWORD Onto the Stack.
+ void push(const Mem& src)
+ {
+ ASMJIT_ASSERT(src.getSize() == 2 || src.getSize() == sizeof(sysint_t));
+ _emitInstruction(kX86InstPush, &src);
+ }
+
+ //! @brief Push WORD/DWORD/QWORD Onto the Stack.
+ void push(const Imm& src)
+ { _emitInstruction(kX86InstPush, &src); }
+
+#if defined(ASMJIT_X86)
+ //! @brief Push All General-Purpose Registers.
+ //!
+ //! Push EAX, ECX, EDX, EBX, original ESP, EBP, ESI, and EDI.
+ void pushad()
+ { _emitInstruction(kX86InstPushAD); }
+#endif // ASMJIT_X86
+
+ //! @brief Push EFLAGS Register (32-bit or 64-bit) onto the Stack.
+ void pushf()
+ {
+#if defined(ASMJIT_X86)
+ pushfd();
+#else
+ pushfq();
+#endif
+ }
+
+#if defined(ASMJIT_X86)
+ //! @brief Push EFLAGS Register (32-bit) onto the Stack.
+ void pushfd()
+ { _emitInstruction(kX86InstPushFD); }
+#else
+ //! @brief Push EFLAGS Register (64-bit) onto the Stack.
+ void pushfq()
+ { _emitInstruction(kX86InstPushFQ); }
+#endif // ASMJIT_X86
+
+ //! @brief Rotate Bits Left.
+ //! @note @a src register can be only @c cl.
+ void rcl(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstRcl, &dst, &src); }
+
+ //! @brief Rotate Bits Left.
+ void rcl(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstRcl, &dst, &src); }
+
+ //! @brief Rotate Bits Left.
+ //! @note @a src register can be only @c cl.
+ void rcl(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstRcl, &dst, &src); }
+
+ //! @brief Rotate Bits Left.
+ void rcl(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstRcl, &dst, &src); }
+
+ //! @brief Rotate Bits Right.
+ //! @note @a src register can be only @c cl.
+ void rcr(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstRcr, &dst, &src); }
+
+ //! @brief Rotate Bits Right.
+ void rcr(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstRcr, &dst, &src); }
+
+ //! @brief Rotate Bits Right.
+ //! @note @a src register can be only @c cl.
+ void rcr(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstRcr, &dst, &src); }
+
+ //! @brief Rotate Bits Right.
+ void rcr(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstRcr, &dst, &src); }
+
+ //! @brief Read Time-Stamp Counter (Pentium).
+ void rdtsc(const GpVar& dst_edx, const GpVar& dst_eax)
+ {
+ // Destination registers must be different.
+ ASMJIT_ASSERT(dst_edx.getId() != dst_eax.getId());
+ _emitInstruction(kX86InstRdtsc, &dst_edx, &dst_eax);
+ }
+
+ //! @brief Read Time-Stamp Counter and Processor ID (New).
+ void rdtscp(const GpVar& dst_edx, const GpVar& dst_eax, const GpVar& dst_ecx)
+ {
+ // Destination registers must be different.
+ ASMJIT_ASSERT(dst_edx.getId() != dst_eax.getId() && dst_eax.getId() != dst_ecx.getId());
+ _emitInstruction(kX86InstRdtscP, &dst_edx, &dst_eax, &dst_ecx);
+ }
+
+ //! @brief Load ECX/RCX BYTEs from DS:[ESI/RSI] to AL.
+ void rep_lodsb(const GpVar& dst_val, const GpVar& src_addr, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to dst=EAX,RAX, src=DS:ESI/RSI, cnt=ECX/RCX.
+ ASMJIT_ASSERT(dst_val.getId() != src_addr.getId() && src_addr.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepLodSB, &dst_val, &src_addr, &cnt_ecx);
+ }
+
+ //! @brief Load ECX/RCX DWORDs from DS:[ESI/RSI] to EAX.
+ void rep_lodsd(const GpVar& dst_val, const GpVar& src_addr, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to dst=EAX,RAX, src=DS:ESI/RSI, cnt=ECX/RCX.
+ ASMJIT_ASSERT(dst_val.getId() != src_addr.getId() && src_addr.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepLodSD, &dst_val, &src_addr, &cnt_ecx);
+ }
+
+#if defined(ASMJIT_X64)
+ //! @brief Load ECX/RCX QWORDs from DS:[ESI/RSI] to RAX.
+ void rep_lodsq(const GpVar& dst_val, const GpVar& src_addr, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to dst=EAX,RAX, src=DS:ESI/RSI, cnt=ECX/RCX.
+ ASMJIT_ASSERT(dst_val.getId() != src_addr.getId() && src_addr.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepLodSQ, &dst_val, &src_addr, &cnt_ecx);
+ }
+#endif // ASMJIT_X64
+
+ //! @brief Load ECX/RCX WORDs from DS:[ESI/RSI] to AX.
+ void rep_lodsw(const GpVar& dst_val, const GpVar& src_addr, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to dst=EAX,RAX, src=DS:ESI/RSI, cnt=ECX/RCX.
+ ASMJIT_ASSERT(dst_val.getId() != src_addr.getId() && src_addr.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepLodSW, &dst_val, &src_addr, &cnt_ecx);
+ }
+
+ //! @brief Move ECX/RCX BYTEs from DS:[ESI/RSI] to ES:[EDI/RDI].
+ void rep_movsb(const GpVar& dst_addr, const GpVar& src_addr, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to dst=ES:EDI,RDI, src=DS:ESI/RSI, cnt=ECX/RCX.
+ ASMJIT_ASSERT(dst_addr.getId() != src_addr.getId() && src_addr.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepMovSB, &dst_addr, &src_addr, &cnt_ecx);
+ }
+
+ //! @brief Move ECX/RCX DWORDs from DS:[ESI/RSI] to ES:[EDI/RDI].
+ void rep_movsd(const GpVar& dst_addr, const GpVar& src_addr, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to dst=ES:EDI,RDI, src=DS:ESI/RSI, cnt=ECX/RCX.
+ ASMJIT_ASSERT(dst_addr.getId() != src_addr.getId() && src_addr.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepMovSD, &dst_addr, &src_addr, &cnt_ecx);
+ }
+
+#if defined(ASMJIT_X64)
+ //! @brief Move ECX/RCX QWORDs from DS:[ESI/RSI] to ES:[EDI/RDI].
+ void rep_movsq(const GpVar& dst_addr, const GpVar& src_addr, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to dst=ES:EDI,RDI, src=DS:ESI/RSI, cnt=ECX/RCX.
+ ASMJIT_ASSERT(dst_addr.getId() != src_addr.getId() && src_addr.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepMovSQ, &dst_addr, &src_addr, &cnt_ecx);
+ }
+#endif // ASMJIT_X64
+
+ //! @brief Move ECX/RCX WORDs from DS:[ESI/RSI] to ES:[EDI/RDI].
+ void rep_movsw(const GpVar& dst_addr, const GpVar& src_addr, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to dst=ES:EDI,RDI, src=DS:ESI/RSI, cnt=ECX/RCX.
+ ASMJIT_ASSERT(dst_addr.getId() != src_addr.getId() && src_addr.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepMovSW, &dst_addr, &src_addr, &cnt_ecx);
+ }
+
+ //! @brief Fill ECX/RCX BYTEs at ES:[EDI/RDI] with AL.
+ void rep_stosb(const GpVar& dst_addr, const GpVar& src_val, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to dst=ES:EDI,RDI, src=EAX/RAX, cnt=ECX/RCX.
+ ASMJIT_ASSERT(dst_addr.getId() != src_val.getId() && src_val.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepStoSB, &dst_addr, &src_val, &cnt_ecx);
+ }
+
+ //! @brief Fill ECX/RCX DWORDs at ES:[EDI/RDI] with EAX.
+ void rep_stosd(const GpVar& dst_addr, const GpVar& src_val, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to dst=ES:EDI,RDI, src=EAX/RAX, cnt=ECX/RCX.
+ ASMJIT_ASSERT(dst_addr.getId() != src_val.getId() && src_val.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepStoSD, &dst_addr, &src_val, &cnt_ecx);
+ }
+
+#if defined(ASMJIT_X64)
+ //! @brief Fill ECX/RCX QWORDs at ES:[EDI/RDI] with RAX.
+ void rep_stosq(const GpVar& dst_addr, const GpVar& src_val, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to dst=ES:EDI,RDI, src=EAX/RAX, cnt=ECX/RCX.
+ ASMJIT_ASSERT(dst_addr.getId() != src_val.getId() && src_val.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepStoSQ, &dst_addr, &src_val, &cnt_ecx);
+ }
+#endif // ASMJIT_X64
+
+ //! @brief Fill ECX/RCX WORDs at ES:[EDI/RDI] with AX.
+ void rep_stosw(const GpVar& dst_addr, const GpVar& src_val, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to dst=ES:EDI,RDI, src=EAX/RAX, cnt=ECX/RCX.
+ ASMJIT_ASSERT(dst_addr.getId() != src_val.getId() && src_val.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepStoSW, &dst_addr, &src_val, &cnt_ecx);
+ }
+
+ //! @brief Repeated find nonmatching BYTEs in ES:[EDI/RDI] and DS:[ESI/RDI].
+ void repe_cmpsb(const GpVar& cmp1_addr, const GpVar& cmp2_addr, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to cmp1=ES:EDI,RDI, cmp2=ES:[EDI/RDI], cnt=ECX/RCX.
+ ASMJIT_ASSERT(cmp1_addr.getId() != cmp2_addr.getId() && cmp2_addr.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepECmpSB, &cmp1_addr, &cmp2_addr, &cnt_ecx);
+ }
+
+ //! @brief Repeated find nonmatching DWORDs in ES:[EDI/RDI] and DS:[ESI/RDI].
+ void repe_cmpsd(const GpVar& cmp1_addr, const GpVar& cmp2_addr, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to cmp1=ES:EDI,RDI, cmp2=ES:[EDI/RDI], cnt=ECX/RCX.
+ ASMJIT_ASSERT(cmp1_addr.getId() != cmp2_addr.getId() && cmp2_addr.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepECmpSD, &cmp1_addr, &cmp2_addr, &cnt_ecx);
+ }
+
+#if defined(ASMJIT_X64)
+ //! @brief Repeated find nonmatching QWORDs in ES:[EDI/RDI] and DS:[ESI/RDI].
+ void repe_cmpsq(const GpVar& cmp1_addr, const GpVar& cmp2_addr, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to cmp1=ES:EDI,RDI, cmp2=ES:[EDI/RDI], cnt=ECX/RCX.
+ ASMJIT_ASSERT(cmp1_addr.getId() != cmp2_addr.getId() && cmp2_addr.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepECmpSQ, &cmp1_addr, &cmp2_addr, &cnt_ecx);
+ }
+#endif // ASMJIT_X64
+
+ //! @brief Repeated find nonmatching WORDs in ES:[EDI/RDI] and DS:[ESI/RDI].
+ void repe_cmpsw(const GpVar& cmp1_addr, const GpVar& cmp2_addr, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to cmp1=ES:EDI,RDI, cmp2=ES:[EDI/RDI], cnt=ECX/RCX.
+ ASMJIT_ASSERT(cmp1_addr.getId() != cmp2_addr.getId() && cmp2_addr.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepECmpSW, &cmp1_addr, &cmp2_addr, &cnt_ecx);
+ }
+
+ //! @brief Find non-AL BYTE starting at ES:[EDI/RDI].
+ void repe_scasb(const GpVar& cmp1_addr, const GpVar& cmp2_val, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to cmp1=ES:EDI,RDI, src=AL, cnt=ECX/RCX.
+ ASMJIT_ASSERT(cmp1_addr.getId() != cmp2_val.getId() && cmp2_val.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepEScaSB, &cmp1_addr, &cmp2_val, &cnt_ecx);
+ }
+
+ //! @brief Find non-EAX DWORD starting at ES:[EDI/RDI].
+ void repe_scasd(const GpVar& cmp1_addr, const GpVar& cmp2_val, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to cmp1=ES:EDI,RDI, src=EAX, cnt=ECX/RCX.
+ ASMJIT_ASSERT(cmp1_addr.getId() != cmp2_val.getId() && cmp2_val.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepEScaSD, &cmp1_addr, &cmp2_val, &cnt_ecx);
+ }
+
+#if defined(ASMJIT_X64)
+ //! @brief Find non-RAX QWORD starting at ES:[EDI/RDI].
+ void repe_scasq(const GpVar& cmp1_addr, const GpVar& cmp2_val, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to cmp1=ES:EDI,RDI, src=RAX, cnt=ECX/RCX.
+ ASMJIT_ASSERT(cmp1_addr.getId() != cmp2_val.getId() && cmp2_val.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepEScaSQ, &cmp1_addr, &cmp2_val, &cnt_ecx);
+ }
+#endif // ASMJIT_X64
+
+ //! @brief Find non-AX WORD starting at ES:[EDI/RDI].
+ void repe_scasw(const GpVar& cmp1_addr, const GpVar& cmp2_val, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to cmp1=ES:EDI,RDI, src=AX, cnt=ECX/RCX.
+ ASMJIT_ASSERT(cmp1_addr.getId() != cmp2_val.getId() && cmp2_val.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepEScaSW, &cmp1_addr, &cmp2_val, &cnt_ecx);
+ }
+
+ //! @brief Find matching BYTEs in [RDI] and [RSI].
+ void repne_cmpsb(const GpVar& cmp1_addr, const GpVar& cmp2_addr, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to cmp1=ES:EDI,RDI, cmp2=ES:[EDI/RDI], cnt=ECX/RCX.
+ ASMJIT_ASSERT(cmp1_addr.getId() != cmp2_addr.getId() && cmp2_addr.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepNECmpSB, &cmp1_addr, &cmp2_addr, &cnt_ecx);
+ }
+
+ //! @brief Find matching DWORDs in [RDI] and [RSI].
+ void repne_cmpsd(const GpVar& cmp1_addr, const GpVar& cmp2_addr, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to cmp1=ES:EDI,RDI, cmp2=ES:[EDI/RDI], cnt=ECX/RCX.
+ ASMJIT_ASSERT(cmp1_addr.getId() != cmp2_addr.getId() && cmp2_addr.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepNECmpSD, &cmp1_addr, &cmp2_addr, &cnt_ecx);
+ }
+
+#if defined(ASMJIT_X64)
+ //! @brief Find matching QWORDs in [RDI] and [RSI].
+ void repne_cmpsq(const GpVar& cmp1_addr, const GpVar& cmp2_addr, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to cmp1=ES:EDI,RDI, cmp2=ES:[EDI/RDI], cnt=ECX/RCX.
+ ASMJIT_ASSERT(cmp1_addr.getId() != cmp2_addr.getId() && cmp2_addr.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepNECmpSQ, &cmp1_addr, &cmp2_addr, &cnt_ecx);
+ }
+#endif // ASMJIT_X64
+
+ //! @brief Find matching WORDs in [RDI] and [RSI].
+ void repne_cmpsw(const GpVar& cmp1_addr, const GpVar& cmp2_addr, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to cmp1=ES:EDI,RDI, cmp2=ES:[EDI/RDI], cnt=ECX/RCX.
+ ASMJIT_ASSERT(cmp1_addr.getId() != cmp2_addr.getId() && cmp2_addr.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepNECmpSW, &cmp1_addr, &cmp2_addr, &cnt_ecx);
+ }
+
+ //! @brief Find AL, starting at ES:[EDI/RDI].
+ void repne_scasb(const GpVar& cmp1_addr, const GpVar& cmp2_val, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to cmp1=ES:EDI,RDI, src=AL, cnt=ECX/RCX.
+ ASMJIT_ASSERT(cmp1_addr.getId() != cmp2_val.getId() && cmp2_val.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepNEScaSB, &cmp1_addr, &cmp2_val, &cnt_ecx);
+ }
+
+ //! @brief Find EAX, starting at ES:[EDI/RDI].
+ void repne_scasd(const GpVar& cmp1_addr, const GpVar& cmp2_val, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to cmp1=ES:EDI,RDI, src=EAX, cnt=ECX/RCX.
+ ASMJIT_ASSERT(cmp1_addr.getId() != cmp2_val.getId() && cmp2_val.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepNEScaSD, &cmp1_addr, &cmp2_val, &cnt_ecx);
+ }
+
+#if defined(ASMJIT_X64)
+ //! @brief Find RAX, starting at ES:[EDI/RDI].
+ void repne_scasq(const GpVar& cmp1_addr, const GpVar& cmp2_val, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to cmp1=ES:EDI,RDI, src=RAX, cnt=ECX/RCX.
+ ASMJIT_ASSERT(cmp1_addr.getId() != cmp2_val.getId() && cmp2_val.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepNEScaSQ, &cmp1_addr, &cmp2_val, &cnt_ecx);
+ }
+#endif // ASMJIT_X64
+
+ //! @brief Find AX, starting at ES:[EDI/RDI].
+ void repne_scasw(const GpVar& cmp1_addr, const GpVar& cmp2_val, const GpVar& cnt_ecx)
+ {
+ // All registers must be unique, they will be reallocated to cmp1=ES:EDI,RDI, src=AX, cnt=ECX/RCX.
+ ASMJIT_ASSERT(cmp1_addr.getId() != cmp2_val.getId() && cmp2_val.getId() != cnt_ecx.getId());
+ _emitInstruction(kX86InstRepNEScaSW, &cmp1_addr, &cmp2_val, &cnt_ecx);
+ }
+
+ //! @brief Return from Procedure.
+ void ret()
+ { _emitReturn(nullptr, nullptr); }
+
+ //! @brief Return from Procedure.
+ void ret(const GpVar& first)
+ { _emitReturn(&first, nullptr); }
+
+ //! @brief Return from Procedure.
+ void ret(const GpVar& first, const GpVar& second)
+ { _emitReturn(&first, &second); }
+
+ //! @brief Return from Procedure.
+ void ret(const XmmVar& first)
+ { _emitReturn(&first, nullptr); }
+
+ //! @brief Return from Procedure.
+ void ret(const XmmVar& first, const XmmVar& second)
+ { _emitReturn(&first, &second); }
+
+ //! @brief Rotate Bits Left.
+ //! @note @a src register can be only @c cl.
+ void rol(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstRol, &dst, &src); }
+
+ //! @brief Rotate Bits Left.
+ void rol(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstRol, &dst, &src); }
+
+ //! @brief Rotate Bits Left.
+ //! @note @a src register can be only @c cl.
+ void rol(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstRol, &dst, &src); }
+
+ //! @brief Rotate Bits Left.
+ void rol(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstRol, &dst, &src); }
+
+ //! @brief Rotate Bits Right.
+ //! @note @a src register can be only @c cl.
+ void ror(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstRor, &dst, &src); }
+
+ //! @brief Rotate Bits Right.
+ void ror(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstRor, &dst, &src); }
+
+ //! @brief Rotate Bits Right.
+ //! @note @a src register can be only @c cl.
+ void ror(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstRor, &dst, &src); }
+
+ //! @brief Rotate Bits Right.
+ void ror(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstRor, &dst, &src); }
+
+#if defined(ASMJIT_X86)
+ //! @brief Store @a var (allocated to AH/AX/EAX/RAX) into Flags.
+ void sahf(const GpVar& var)
+ { _emitInstruction(kX86InstSahf, &var); }
+#endif // ASMJIT_X86
+
+ //! @brief Integer subtraction with borrow.
+ void sbb(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstSbb, &dst, &src); }
+
+ //! @brief Integer subtraction with borrow.
+ void sbb(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstSbb, &dst, &src); }
+
+ //! @brief Integer subtraction with borrow.
+ void sbb(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstSbb, &dst, &src); }
+
+ //! @brief Integer subtraction with borrow.
+ void sbb(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstSbb, &dst, &src); }
+
+ //! @brief Integer subtraction with borrow.
+ void sbb(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstSbb, &dst, &src); }
+
+ //! @brief Shift Bits Left.
+ //! @note @a src register can be only @c cl.
+ void sal(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstSal, &dst, &src); }
+
+ //! @brief Shift Bits Left.
+ void sal(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstSal, &dst, &src); }
+
+ //! @brief Shift Bits Left.
+ //! @note @a src register can be only @c cl.
+ void sal(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstSal, &dst, &src); }
+
+ //! @brief Shift Bits Left.
+ void sal(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstSal, &dst, &src); }
+
+ //! @brief Shift Bits Right.
+ //! @note @a src register can be only @c cl.
+ void sar(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstSar, &dst, &src); }
+
+ //! @brief Shift Bits Right.
+ void sar(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstSar, &dst, &src); }
+
+ //! @brief Shift Bits Right.
+ //! @note @a src register can be only @c cl.
+ void sar(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstSar, &dst, &src); }
+
+ //! @brief Shift Bits Right.
+ void sar(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstSar, &dst, &src); }
+
+ //! @brief Set Byte on Condition.
+ void set(kX86Cond cc, const GpVar& dst)
+ {
+ ASMJIT_ASSERT(dst.getSize() == 1);
+ _emitInstruction(X86Util::getSetccInstFromCond(cc), &dst);
+ }
+
+ //! @brief Set Byte on Condition.
+ void set(kX86Cond cc, const Mem& dst)
+ {
+ ASMJIT_ASSERT(dst.getSize() <= 1);
+ _emitInstruction(X86Util::getSetccInstFromCond(cc), &dst);
+ }
+
+ //! @brief Set Byte on Condition.
+ void seta (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetA , &dst); }
+ //! @brief Set Byte on Condition.
+ void seta (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetA , &dst); }
+ //! @brief Set Byte on Condition.
+ void setae (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetAE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setae (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetAE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setb (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetB , &dst); }
+ //! @brief Set Byte on Condition.
+ void setb (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetB , &dst); }
+ //! @brief Set Byte on Condition.
+ void setbe (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetBE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setbe (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetBE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setc (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetC , &dst); }
+ //! @brief Set Byte on Condition.
+ void setc (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetC , &dst); }
+ //! @brief Set Byte on Condition.
+ void sete (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetE , &dst); }
+ //! @brief Set Byte on Condition.
+ void sete (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setg (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetG , &dst); }
+ //! @brief Set Byte on Condition.
+ void setg (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetG , &dst); }
+ //! @brief Set Byte on Condition.
+ void setge (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetGE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setge (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetGE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setl (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetL , &dst); }
+ //! @brief Set Byte on Condition.
+ void setl (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetL , &dst); }
+ //! @brief Set Byte on Condition.
+ void setle (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetLE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setle (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetLE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setna (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNA , &dst); }
+ //! @brief Set Byte on Condition.
+ void setna (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNA , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnae(const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNAE, &dst); }
+ //! @brief Set Byte on Condition.
+ void setnae(const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNAE, &dst); }
+ //! @brief Set Byte on Condition.
+ void setnb (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNB , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnb (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNB , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnbe(const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNBE, &dst); }
+ //! @brief Set Byte on Condition.
+ void setnbe(const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNBE, &dst); }
+ //! @brief Set Byte on Condition.
+ void setnc (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNC , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnc (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNC , &dst); }
+ //! @brief Set Byte on Condition.
+ void setne (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setne (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setng (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNG , &dst); }
+ //! @brief Set Byte on Condition.
+ void setng (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNG , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnge(const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNGE, &dst); }
+ //! @brief Set Byte on Condition.
+ void setnge(const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNGE, &dst); }
+ //! @brief Set Byte on Condition.
+ void setnl (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNL , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnl (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNL , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnle(const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNLE, &dst); }
+ //! @brief Set Byte on Condition.
+ void setnle(const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNLE, &dst); }
+ //! @brief Set Byte on Condition.
+ void setno (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNO , &dst); }
+ //! @brief Set Byte on Condition.
+ void setno (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNO , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnp (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNP , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnp (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNP , &dst); }
+ //! @brief Set Byte on Condition.
+ void setns (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNS , &dst); }
+ //! @brief Set Byte on Condition.
+ void setns (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNS , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnz (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetNZ , &dst); }
+ //! @brief Set Byte on Condition.
+ void setnz (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetNZ , &dst); }
+ //! @brief Set Byte on Condition.
+ void seto (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetO , &dst); }
+ //! @brief Set Byte on Condition.
+ void seto (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetO , &dst); }
+ //! @brief Set Byte on Condition.
+ void setp (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetP , &dst); }
+ //! @brief Set Byte on Condition.
+ void setp (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetP , &dst); }
+ //! @brief Set Byte on Condition.
+ void setpe (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetPE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setpe (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetPE , &dst); }
+ //! @brief Set Byte on Condition.
+ void setpo (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetPO , &dst); }
+ //! @brief Set Byte on Condition.
+ void setpo (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetPO , &dst); }
+ //! @brief Set Byte on Condition.
+ void sets (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetS , &dst); }
+ //! @brief Set Byte on Condition.
+ void sets (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetS , &dst); }
+ //! @brief Set Byte on Condition.
+ void setz (const GpVar& dst) { ASMJIT_ASSERT(dst.getSize() == 1); _emitInstruction(kX86InstSetZ , &dst); }
+ //! @brief Set Byte on Condition.
+ void setz (const Mem& dst) { ASMJIT_ASSERT(dst.getSize() <= 1); _emitInstruction(kX86InstSetZ , &dst); }
+
+ //! @brief Shift Bits Left.
+ //! @note @a src register can be only @c cl.
+ void shl(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstShl, &dst, &src); }
+
+ //! @brief Shift Bits Left.
+ void shl(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstShl, &dst, &src); }
+
+ //! @brief Shift Bits Left.
+ //! @note @a src register can be only @c cl.
+ void shl(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstShl, &dst, &src); }
+
+ //! @brief Shift Bits Left.
+ void shl(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstShl, &dst, &src); }
+
+ //! @brief Shift Bits Right.
+ //! @note @a src register can be only @c cl.
+ void shr(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstShr, &dst, &src); }
+
+ //! @brief Shift Bits Right.
+ void shr(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstShr, &dst, &src); }
+
+ //! @brief Shift Bits Right.
+ //! @note @a src register can be only @c cl.
+ void shr(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstShr, &dst, &src); }
+
+ //! @brief Shift Bits Right.
+ void shr(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstShr, &dst, &src); }
+
+ //! @brief Double Precision Shift Left.
+ //! @note src2 register can be only @c cl register.
+ void shld(const GpVar& dst, const GpVar& src1, const GpVar& src2)
+ { _emitInstruction(kX86InstShld, &dst, &src1, &src2); }
+
+ //! @brief Double Precision Shift Left.
+ void shld(const GpVar& dst, const GpVar& src1, const Imm& src2)
+ { _emitInstruction(kX86InstShld, &dst, &src1, &src2); }
+
+ //! @brief Double Precision Shift Left.
+ //! @note src2 register can be only @c cl register.
+ void shld(const Mem& dst, const GpVar& src1, const GpVar& src2)
+ { _emitInstruction(kX86InstShld, &dst, &src1, &src2); }
+
+ //! @brief Double Precision Shift Left.
+ void shld(const Mem& dst, const GpVar& src1, const Imm& src2)
+ { _emitInstruction(kX86InstShld, &dst, &src1, &src2); }
+
+ //! @brief Double Precision Shift Right.
+ //! @note src2 register can be only @c cl register.
+ void shrd(const GpVar& dst, const GpVar& src1, const GpVar& src2)
+ { _emitInstruction(kX86InstShrd, &dst, &src1, &src2); }
+
+ //! @brief Double Precision Shift Right.
+ void shrd(const GpVar& dst, const GpVar& src1, const Imm& src2)
+ { _emitInstruction(kX86InstShrd, &dst, &src1, &src2); }
+
+ //! @brief Double Precision Shift Right.
+ //! @note src2 register can be only @c cl register.
+ void shrd(const Mem& dst, const GpVar& src1, const GpVar& src2)
+ { _emitInstruction(kX86InstShrd, &dst, &src1, &src2); }
+
+ //! @brief Double Precision Shift Right.
+ void shrd(const Mem& dst, const GpVar& src1, const Imm& src2)
+ { _emitInstruction(kX86InstShrd, &dst, &src1, &src2); }
+
+ //! @brief Set Carry Flag to 1.
+ void stc()
+ { _emitInstruction(kX86InstStc); }
+
+ //! @brief Set Direction Flag to 1.
+ void std()
+ { _emitInstruction(kX86InstStd); }
+
+ //! @brief Subtract.
+ void sub(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstSub, &dst, &src); }
+
+ //! @brief Subtract.
+ void sub(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstSub, &dst, &src); }
+
+ //! @brief Subtract.
+ void sub(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstSub, &dst, &src); }
+
+ //! @brief Subtract.
+ void sub(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstSub, &dst, &src); }
+
+ //! @brief Subtract.
+ void sub(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstSub, &dst, &src); }
+
+ //! @brief Logical Compare.
+ void test(const GpVar& op1, const GpVar& op2)
+ { _emitInstruction(kX86InstTest, &op1, &op2); }
+
+ //! @brief Logical Compare.
+ void test(const GpVar& op1, const Imm& op2)
+ { _emitInstruction(kX86InstTest, &op1, &op2); }
+
+ //! @brief Logical Compare.
+ void test(const Mem& op1, const GpVar& op2)
+ { _emitInstruction(kX86InstTest, &op1, &op2); }
+
+ //! @brief Logical Compare.
+ void test(const Mem& op1, const Imm& op2)
+ { _emitInstruction(kX86InstTest, &op1, &op2); }
+
+ //! @brief Undefined instruction - Raise invalid opcode exception.
+ void ud2()
+ { _emitInstruction(kX86InstUd2); }
+
+ //! @brief Exchange and Add.
+ void xadd(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstXadd, &dst, &src); }
+
+ //! @brief Exchange and Add.
+ void xadd(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstXadd, &dst, &src); }
+
+ //! @brief Exchange Register/Memory with Register.
+ void xchg(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstXchg, &dst, &src); }
+
+ //! @brief Exchange Register/Memory with Register.
+ void xchg(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstXchg, &dst, &src); }
+
+ //! @brief Exchange Register/Memory with Register.
+ void xchg(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstXchg, &src, &dst); }
+
+ //! @brief Exchange Register/Memory with Register.
+ void xor_(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstXor, &dst, &src); }
+
+ //! @brief Exchange Register/Memory with Register.
+ void xor_(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstXor, &dst, &src); }
+
+ //! @brief Exchange Register/Memory with Register.
+ void xor_(const GpVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstXor, &dst, &src); }
+
+ //! @brief Exchange Register/Memory with Register.
+ void xor_(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstXor, &dst, &src); }
+
+ //! @brief Exchange Register/Memory with Register.
+ void xor_(const Mem& dst, const Imm& src)
+ { _emitInstruction(kX86InstXor, &dst, &src); }
+
+ // --------------------------------------------------------------------------
+ // [MMX]
+ // --------------------------------------------------------------------------
+
+ //! @brief Empty MMX state.
+ void emms()
+ { _emitInstruction(kX86InstEmms); }
+
+ //! @brief Move DWord (MMX).
+ void movd(const Mem& dst, const MmVar& src)
+ { _emitInstruction(kX86InstMovD, &dst, &src); }
+
+ //! @brief Move DWord (MMX).
+ void movd(const GpVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstMovD, &dst, &src); }
+
+ //! @brief Move DWord (MMX).
+ void movd(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovD, &dst, &src); }
+
+ //! @brief Move DWord (MMX).
+ void movd(const MmVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstMovD, &dst, &src); }
+
+ //! @brief Move QWord (MMX).
+ void movq(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstMovQ, &dst, &src); }
+
+ //! @brief Move QWord (MMX).
+ void movq(const Mem& dst, const MmVar& src)
+ { _emitInstruction(kX86InstMovQ, &dst, &src); }
+
+#if defined(ASMJIT_X64)
+ //! @brief Move QWord (MMX).
+ void movq(const GpVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstMovQ, &dst, &src); }
+#endif
+
+ //! @brief Move QWord (MMX).
+ void movq(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovQ, &dst, &src); }
+
+#if defined(ASMJIT_X64)
+ //! @brief Move QWord (MMX).
+ void movq(const MmVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstMovQ, &dst, &src); }
+#endif
+
+ //! @brief Pack with Signed Saturation (MMX).
+ void packsswb(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPackSSWB, &dst, &src); }
+
+ //! @brief Pack with Signed Saturation (MMX).
+ void packsswb(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPackSSWB, &dst, &src); }
+
+ //! @brief Pack with Signed Saturation (MMX).
+ void packssdw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPackSSDW, &dst, &src); }
+
+ //! @brief Pack with Signed Saturation (MMX).
+ void packssdw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPackSSDW, &dst, &src); }
+
+ //! @brief Pack with Unsigned Saturation (MMX).
+ void packuswb(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPackUSWB, &dst, &src); }
+
+ //! @brief Pack with Unsigned Saturation (MMX).
+ void packuswb(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPackUSWB, &dst, &src); }
+
+ //! @brief Packed BYTE Add (MMX).
+ void paddb(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPAddB, &dst, &src); }
+
+ //! @brief Packed BYTE Add (MMX).
+ void paddb(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddB, &dst, &src); }
+
+ //! @brief Packed WORD Add (MMX).
+ void paddw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPAddW, &dst, &src); }
+
+ //! @brief Packed WORD Add (MMX).
+ void paddw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddW, &dst, &src); }
+
+ //! @brief Packed DWORD Add (MMX).
+ void paddd(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPAddD, &dst, &src); }
+
+ //! @brief Packed DWORD Add (MMX).
+ void paddd(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddD, &dst, &src); }
+
+ //! @brief Packed Add with Saturation (MMX).
+ void paddsb(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPAddSB, &dst, &src); }
+
+ //! @brief Packed Add with Saturation (MMX).
+ void paddsb(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddSB, &dst, &src); }
+
+ //! @brief Packed Add with Saturation (MMX).
+ void paddsw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPAddSW, &dst, &src); }
+
+ //! @brief Packed Add with Saturation (MMX).
+ void paddsw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddSW, &dst, &src); }
+
+ //! @brief Packed Add Unsigned with Saturation (MMX).
+ void paddusb(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPAddUSB, &dst, &src); }
+
+ //! @brief Packed Add Unsigned with Saturation (MMX).
+ void paddusb(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddUSB, &dst, &src); }
+
+ //! @brief Packed Add Unsigned with Saturation (MMX).
+ void paddusw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPAddUSW, &dst, &src); }
+
+ //! @brief Packed Add Unsigned with Saturation (MMX).
+ void paddusw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddUSW, &dst, &src); }
+
+ //! @brief Logical AND (MMX).
+ void pand(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPAnd, &dst, &src); }
+
+ //! @brief Logical AND (MMX).
+ void pand(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAnd, &dst, &src); }
+
+ //! @brief Logical AND Not (MMX).
+ void pandn(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPAndN, &dst, &src); }
+
+ //! @brief Logical AND Not (MMX).
+ void pandn(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAndN, &dst, &src); }
+
+ //! @brief Packed Compare for Equal (BYTES) (MMX).
+ void pcmpeqb(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPCmpEqB, &dst, &src); }
+
+ //! @brief Packed Compare for Equal (BYTES) (MMX).
+ void pcmpeqb(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpEqB, &dst, &src); }
+
+ //! @brief Packed Compare for Equal (WORDS) (MMX).
+ void pcmpeqw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPCmpEqW, &dst, &src); }
+
+ //! @brief Packed Compare for Equal (WORDS) (MMX).
+ void pcmpeqw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpEqW, &dst, &src); }
+
+ //! @brief Packed Compare for Equal (DWORDS) (MMX).
+ void pcmpeqd(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPCmpEqD, &dst, &src); }
+
+ //! @brief Packed Compare for Equal (DWORDS) (MMX).
+ void pcmpeqd(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpEqD, &dst, &src); }
+
+ //! @brief Packed Compare for Greater Than (BYTES) (MMX).
+ void pcmpgtb(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPCmpGtB, &dst, &src); }
+
+ //! @brief Packed Compare for Greater Than (BYTES) (MMX).
+ void pcmpgtb(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpGtB, &dst, &src); }
+
+ //! @brief Packed Compare for Greater Than (WORDS) (MMX).
+ void pcmpgtw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPCmpGtW, &dst, &src); }
+
+ //! @brief Packed Compare for Greater Than (WORDS) (MMX).
+ void pcmpgtw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpGtW, &dst, &src); }
+
+ //! @brief Packed Compare for Greater Than (DWORDS) (MMX).
+ void pcmpgtd(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPCmpGtD, &dst, &src); }
+
+ //! @brief Packed Compare for Greater Than (DWORDS) (MMX).
+ void pcmpgtd(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpGtD, &dst, &src); }
+
+ //! @brief Packed Multiply High (MMX).
+ void pmulhw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPMulHW, &dst, &src); }
+
+ //! @brief Packed Multiply High (MMX).
+ void pmulhw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulHW, &dst, &src); }
+
+ //! @brief Packed Multiply Low (MMX).
+ void pmullw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPMulLW, &dst, &src); }
+
+ //! @brief Packed Multiply Low (MMX).
+ void pmullw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulLW, &dst, &src); }
+
+ //! @brief Bitwise Logical OR (MMX).
+ void por(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPOr, &dst, &src); }
+
+ //! @brief Bitwise Logical OR (MMX).
+ void por(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPOr, &dst, &src); }
+
+ //! @brief Packed Multiply and Add (MMX).
+ void pmaddwd(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPMAddWD, &dst, &src); }
+
+ //! @brief Packed Multiply and Add (MMX).
+ void pmaddwd(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMAddWD, &dst, &src); }
+
+ //! @brief Packed Shift Left Logical (MMX).
+ void pslld(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSllD, &dst, &src); }
+
+ //! @brief Packed Shift Left Logical (MMX).
+ void pslld(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSllD, &dst, &src); }
+
+ //! @brief Packed Shift Left Logical (MMX).
+ void pslld(const MmVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSllD, &dst, &src); }
+
+ //! @brief Packed Shift Left Logical (MMX).
+ void psllq(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSllQ, &dst, &src); }
+
+ //! @brief Packed Shift Left Logical (MMX).
+ void psllq(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSllQ, &dst, &src); }
+
+ //! @brief Packed Shift Left Logical (MMX).
+ void psllq(const MmVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSllQ, &dst, &src); }
+
+ //! @brief Packed Shift Left Logical (MMX).
+ void psllw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSllW, &dst, &src); }
+
+ //! @brief Packed Shift Left Logical (MMX).
+ void psllw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSllW, &dst, &src); }
+
+ //! @brief Packed Shift Left Logical (MMX).
+ void psllw(const MmVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSllW, &dst, &src); }
+
+ //! @brief Packed Shift Right Arithmetic (MMX).
+ void psrad(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSraD, &dst, &src); }
+
+ //! @brief Packed Shift Right Arithmetic (MMX).
+ void psrad(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSraD, &dst, &src);}
+
+ //! @brief Packed Shift Right Arithmetic (MMX).
+ void psrad(const MmVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSraD, &dst, &src); }
+
+ //! @brief Packed Shift Right Arithmetic (MMX).
+ void psraw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSraW, &dst, &src); }
+
+ //! @brief Packed Shift Right Arithmetic (MMX).
+ void psraw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSraW, &dst, &src); }
+
+ //! @brief Packed Shift Right Arithmetic (MMX).
+ void psraw(const MmVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSraW, &dst, &src); }
+
+ //! @brief Packed Shift Right Logical (MMX).
+ void psrld(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSrlD, &dst, &src); }
+
+ //! @brief Packed Shift Right Logical (MMX).
+ void psrld(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSrlD, &dst, &src); }
+
+ //! @brief Packed Shift Right Logical (MMX).
+ void psrld(const MmVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSrlD, &dst, &src); }
+
+ //! @brief Packed Shift Right Logical (MMX).
+ void psrlq(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSrlQ, &dst, &src); }
+
+ //! @brief Packed Shift Right Logical (MMX).
+ void psrlq(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSrlQ, &dst, &src); }
+
+ //! @brief Packed Shift Right Logical (MMX).
+ void psrlq(const MmVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSrlQ, &dst, &src); }
+
+ //! @brief Packed Shift Right Logical (MMX).
+ void psrlw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSrlW, &dst, &src); }
+
+ //! @brief Packed Shift Right Logical (MMX).
+ void psrlw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSrlW, &dst, &src); }
+
+ //! @brief Packed Shift Right Logical (MMX).
+ void psrlw(const MmVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSrlW, &dst, &src); }
+
+ //! @brief Packed Subtract (MMX).
+ void psubb(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSubB, &dst, &src); }
+
+ //! @brief Packed Subtract (MMX).
+ void psubb(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubB, &dst, &src); }
+
+ //! @brief Packed Subtract (MMX).
+ void psubw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSubW, &dst, &src); }
+
+ //! @brief Packed Subtract (MMX).
+ void psubw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubW, &dst, &src); }
+
+ //! @brief Packed Subtract (MMX).
+ void psubd(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSubD, &dst, &src); }
+
+ //! @brief Packed Subtract (MMX).
+ void psubd(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubD, &dst, &src); }
+
+ //! @brief Packed Subtract with Saturation (MMX).
+ void psubsb(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSubSB, &dst, &src); }
+
+ //! @brief Packed Subtract with Saturation (MMX).
+ void psubsb(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubSB, &dst, &src); }
+
+ //! @brief Packed Subtract with Saturation (MMX).
+ void psubsw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSubSW, &dst, &src); }
+
+ //! @brief Packed Subtract with Saturation (MMX).
+ void psubsw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubSW, &dst, &src); }
+
+ //! @brief Packed Subtract with Unsigned Saturation (MMX).
+ void psubusb(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSubUSB, &dst, &src); }
+
+ //! @brief Packed Subtract with Unsigned Saturation (MMX).
+ void psubusb(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubUSB, &dst, &src); }
+
+ //! @brief Packed Subtract with Unsigned Saturation (MMX).
+ void psubusw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSubUSW, &dst, &src); }
+
+ //! @brief Packed Subtract with Unsigned Saturation (MMX).
+ void psubusw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubUSW, &dst, &src); }
+
+ //! @brief Unpack High Packed Data (MMX).
+ void punpckhbw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPunpckHBW, &dst, &src); }
+
+ //! @brief Unpack High Packed Data (MMX).
+ void punpckhbw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckHBW, &dst, &src); }
+
+ //! @brief Unpack High Packed Data (MMX).
+ void punpckhwd(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPunpckHWD, &dst, &src); }
+
+ //! @brief Unpack High Packed Data (MMX).
+ void punpckhwd(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckHWD, &dst, &src); }
+
+ //! @brief Unpack High Packed Data (MMX).
+ void punpckhdq(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPunpckHDQ, &dst, &src); }
+
+ //! @brief Unpack High Packed Data (MMX).
+ void punpckhdq(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckHDQ, &dst, &src); }
+
+ //! @brief Unpack High Packed Data (MMX).
+ void punpcklbw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPunpckLBW, &dst, &src); }
+
+ //! @brief Unpack High Packed Data (MMX).
+ void punpcklbw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckLBW, &dst, &src); }
+
+ //! @brief Unpack High Packed Data (MMX).
+ void punpcklwd(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPunpckLWD, &dst, &src); }
+
+ //! @brief Unpack High Packed Data (MMX).
+ void punpcklwd(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckLWD, &dst, &src); }
+
+ //! @brief Unpack High Packed Data (MMX).
+ void punpckldq(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPunpckLDQ, &dst, &src); }
+
+ //! @brief Unpack High Packed Data (MMX).
+ void punpckldq(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckLDQ, &dst, &src); }
+
+ //! @brief Bitwise Exclusive OR (MMX).
+ void pxor(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPXor, &dst, &src); }
+
+ //! @brief Bitwise Exclusive OR (MMX).
+ void pxor(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPXor, &dst, &src); }
+
+ // --------------------------------------------------------------------------
+ // [3dNow]
+ // --------------------------------------------------------------------------
+
+ //! @brief Faster EMMS (3dNow!).
+ //!
+ //! @note Use only for early AMD processors where is only 3dNow! or SSE. If
+ //! CPU contains SSE2, it's better to use @c emms() ( @c femms() is mapped
+ //! to @c emms() ).
+ void femms()
+ { _emitInstruction(kX86InstFEmms); }
+
+ //! @brief Packed SP-FP to Integer Convert (3dNow!).
+ void pf2id(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPF2ID, &dst, &src); }
+
+ //! @brief Packed SP-FP to Integer Convert (3dNow!).
+ void pf2id(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPF2ID, &dst, &src); }
+
+ //! @brief Packed SP-FP to Integer Word Convert (3dNow!).
+ void pf2iw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPF2IW, &dst, &src); }
+
+ //! @brief Packed SP-FP to Integer Word Convert (3dNow!).
+ void pf2iw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPF2IW, &dst, &src); }
+
+ //! @brief Packed SP-FP Accumulate (3dNow!).
+ void pfacc(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPFAcc, &dst, &src); }
+
+ //! @brief Packed SP-FP Accumulate (3dNow!).
+ void pfacc(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFAcc, &dst, &src); }
+
+ //! @brief Packed SP-FP Addition (3dNow!).
+ void pfadd(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPFAdd, &dst, &src); }
+
+ //! @brief Packed SP-FP Addition (3dNow!).
+ void pfadd(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFAdd, &dst, &src); }
+
+ //! @brief Packed SP-FP Compare - dst == src (3dNow!).
+ void pfcmpeq(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPFCmpEQ, &dst, &src); }
+
+ //! @brief Packed SP-FP Compare - dst == src (3dNow!).
+ void pfcmpeq(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFCmpEQ, &dst, &src); }
+
+ //! @brief Packed SP-FP Compare - dst >= src (3dNow!).
+ void pfcmpge(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPFCmpGE, &dst, &src); }
+
+ //! @brief Packed SP-FP Compare - dst >= src (3dNow!).
+ void pfcmpge(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFCmpGE, &dst, &src); }
+
+ //! @brief Packed SP-FP Compare - dst > src (3dNow!).
+ void pfcmpgt(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPFCmpGT, &dst, &src); }
+
+ //! @brief Packed SP-FP Compare - dst > src (3dNow!).
+ void pfcmpgt(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFCmpGT, &dst, &src); }
+
+ //! @brief Packed SP-FP Maximum (3dNow!).
+ void pfmax(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPFMax, &dst, &src); }
+
+ //! @brief Packed SP-FP Maximum (3dNow!).
+ void pfmax(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFMax, &dst, &src); }
+
+ //! @brief Packed SP-FP Minimum (3dNow!).
+ void pfmin(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPFMin, &dst, &src); }
+
+ //! @brief Packed SP-FP Minimum (3dNow!).
+ void pfmin(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFMin, &dst, &src); }
+
+ //! @brief Packed SP-FP Multiply (3dNow!).
+ void pfmul(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPFMul, &dst, &src); }
+
+ //! @brief Packed SP-FP Multiply (3dNow!).
+ void pfmul(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFMul, &dst, &src); }
+
+ //! @brief Packed SP-FP Negative Accumulate (3dNow!).
+ void pfnacc(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPFNAcc, &dst, &src); }
+
+ //! @brief Packed SP-FP Negative Accumulate (3dNow!).
+ void pfnacc(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFNAcc, &dst, &src); }
+
+ //! @brief Packed SP-FP Mixed Accumulate (3dNow!).
+ void pfpnacc(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPFPNAcc, &dst, &src); }
+
+ //! @brief Packed SP-FP Mixed Accumulate (3dNow!).
+ void pfpnacc(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFPNAcc, &dst, &src); }
+
+ //! @brief Packed SP-FP Reciprocal Approximation (3dNow!).
+ void pfrcp(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPFRcp, &dst, &src); }
+
+ //! @brief Packed SP-FP Reciprocal Approximation (3dNow!).
+ void pfrcp(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFRcp, &dst, &src); }
+
+ //! @brief Packed SP-FP Reciprocal, First Iteration Step (3dNow!).
+ void pfrcpit1(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPFRcpIt1, &dst, &src); }
+
+ //! @brief Packed SP-FP Reciprocal, First Iteration Step (3dNow!).
+ void pfrcpit1(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFRcpIt1, &dst, &src); }
+
+ //! @brief Packed SP-FP Reciprocal, Second Iteration Step (3dNow!).
+ void pfrcpit2(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPFRcpIt2, &dst, &src); }
+
+ //! @brief Packed SP-FP Reciprocal, Second Iteration Step (3dNow!).
+ void pfrcpit2(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFRcpIt2, &dst, &src); }
+
+ //! @brief Packed SP-FP Reciprocal Square Root, First Iteration Step (3dNow!).
+ void pfrsqit1(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPFRSqIt1, &dst, &src); }
+
+ //! @brief Packed SP-FP Reciprocal Square Root, First Iteration Step (3dNow!).
+ void pfrsqit1(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFRSqIt1, &dst, &src); }
+
+ //! @brief Packed SP-FP Reciprocal Square Root Approximation (3dNow!).
+ void pfrsqrt(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPFRSqrt, &dst, &src); }
+
+ //! @brief Packed SP-FP Reciprocal Square Root Approximation (3dNow!).
+ void pfrsqrt(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFRSqrt, &dst, &src); }
+
+ //! @brief Packed SP-FP Subtract (3dNow!).
+ void pfsub(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPFSub, &dst, &src); }
+
+ //! @brief Packed SP-FP Subtract (3dNow!).
+ void pfsub(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFSub, &dst, &src); }
+
+ //! @brief Packed SP-FP Reverse Subtract (3dNow!).
+ void pfsubr(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPFSubR, &dst, &src); }
+
+ //! @brief Packed SP-FP Reverse Subtract (3dNow!).
+ void pfsubr(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPFSubR, &dst, &src); }
+
+ //! @brief Packed DWords to SP-FP (3dNow!).
+ void pi2fd(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPI2FD, &dst, &src); }
+
+ //! @brief Packed DWords to SP-FP (3dNow!).
+ void pi2fd(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPI2FD, &dst, &src); }
+
+ //! @brief Packed Words to SP-FP (3dNow!).
+ void pi2fw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPI2FW, &dst, &src); }
+
+ //! @brief Packed Words to SP-FP (3dNow!).
+ void pi2fw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPI2FW, &dst, &src); }
+
+ //! @brief Packed swap DWord (3dNow!)
+ void pswapd(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSwapD, &dst, &src); }
+
+ //! @brief Packed swap DWord (3dNow!)
+ void pswapd(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSwapD, &dst, &src); }
+
+ // --------------------------------------------------------------------------
+ // [SSE]
+ // --------------------------------------------------------------------------
+
+ //! @brief Packed SP-FP Add (SSE).
+ void addps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstAddPS, &dst, &src); }
+ //! @brief Packed SP-FP Add (SSE).
+ void addps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstAddPS, &dst, &src); }
+
+ //! @brief Scalar SP-FP Add (SSE).
+ void addss(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstAddSS, &dst, &src); }
+ //! @brief Scalar SP-FP Add (SSE).
+ void addss(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstAddSS, &dst, &src); }
+
+ //! @brief Bit-wise Logical And Not For SP-FP (SSE).
+ void andnps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstAndnPS, &dst, &src); }
+ //! @brief Bit-wise Logical And Not For SP-FP (SSE).
+ void andnps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstAndnPS, &dst, &src); }
+
+ //! @brief Bit-wise Logical And For SP-FP (SSE).
+ void andps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstAndPS, &dst, &src); }
+ //! @brief Bit-wise Logical And For SP-FP (SSE).
+ void andps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstAndPS, &dst, &src); }
+
+ //! @brief Packed SP-FP Compare (SSE).
+ void cmpps(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstCmpPS, &dst, &src, &imm8); }
+ //! @brief Packed SP-FP Compare (SSE).
+ void cmpps(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstCmpPS, &dst, &src, &imm8); }
+
+ //! @brief Compare Scalar SP-FP Values (SSE).
+ void cmpss(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstCmpSS, &dst, &src, &imm8); }
+ //! @brief Compare Scalar SP-FP Values (SSE).
+ void cmpss(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstCmpSS, &dst, &src, &imm8); }
+
+ //! @brief Scalar Ordered SP-FP Compare and Set EFLAGS (SSE).
+ void comiss(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstComISS, &dst, &src); }
+ //! @brief Scalar Ordered SP-FP Compare and Set EFLAGS (SSE).
+ void comiss(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstComISS, &dst, &src); }
+
+ //! @brief Packed Signed INT32 to Packed SP-FP Conversion (SSE).
+ void cvtpi2ps(const XmmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstCvtPI2PS, &dst, &src); }
+ //! @brief Packed Signed INT32 to Packed SP-FP Conversion (SSE).
+ void cvtpi2ps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtPI2PS, &dst, &src); }
+
+ //! @brief Packed SP-FP to Packed INT32 Conversion (SSE).
+ void cvtps2pi(const MmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstCvtPS2PI, &dst, &src); }
+ //! @brief Packed SP-FP to Packed INT32 Conversion (SSE).
+ void cvtps2pi(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtPS2PI, &dst, &src); }
+
+ //! @brief Scalar Signed INT32 to SP-FP Conversion (SSE).
+ void cvtsi2ss(const XmmVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstCvtSI2SS, &dst, &src); }
+ //! @brief Scalar Signed INT32 to SP-FP Conversion (SSE).
+ void cvtsi2ss(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtSI2SS, &dst, &src); }
+
+ //! @brief Scalar SP-FP to Signed INT32 Conversion (SSE).
+ void cvtss2si(const GpVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstCvtSS2SI, &dst, &src); }
+ //! @brief Scalar SP-FP to Signed INT32 Conversion (SSE).
+ void cvtss2si(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtSS2SI, &dst, &src); }
+
+ //! @brief Packed SP-FP to Packed INT32 Conversion (truncate) (SSE).
+ void cvttps2pi(const MmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstCvttPS2PI, &dst, &src); }
+ //! @brief Packed SP-FP to Packed INT32 Conversion (truncate) (SSE).
+ void cvttps2pi(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvttPS2PI, &dst, &src); }
+
+ //! @brief Scalar SP-FP to Signed INT32 Conversion (truncate) (SSE).
+ void cvttss2si(const GpVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstCvttSS2SI, &dst, &src); }
+ //! @brief Scalar SP-FP to Signed INT32 Conversion (truncate) (SSE).
+ void cvttss2si(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvttSS2SI, &dst, &src); }
+
+ //! @brief Packed SP-FP Divide (SSE).
+ void divps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstDivPS, &dst, &src); }
+ //! @brief Packed SP-FP Divide (SSE).
+ void divps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstDivPS, &dst, &src); }
+
+ //! @brief Scalar SP-FP Divide (SSE).
+ void divss(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstDivSS, &dst, &src); }
+ //! @brief Scalar SP-FP Divide (SSE).
+ void divss(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstDivSS, &dst, &src); }
+
+ //! @brief Load Streaming SIMD Extension Control/Status (SSE).
+ void ldmxcsr(const Mem& src)
+ { _emitInstruction(kX86InstLdMXCSR, &src); }
+
+ //! @brief Byte Mask Write (SSE).
+ //!
+ //! @note The default memory location is specified by DS:EDI.
+ void maskmovq(const GpVar& dst_ptr, const MmVar& data, const MmVar& mask)
+ { _emitInstruction(kX86InstMaskMovQ, &dst_ptr, &data, &mask); }
+
+ //! @brief Packed SP-FP Maximum (SSE).
+ void maxps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMaxPS, &dst, &src); }
+ //! @brief Packed SP-FP Maximum (SSE).
+ void maxps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMaxPS, &dst, &src); }
+
+ //! @brief Scalar SP-FP Maximum (SSE).
+ void maxss(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMaxSS, &dst, &src); }
+ //! @brief Scalar SP-FP Maximum (SSE).
+ void maxss(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMaxSS, &dst, &src); }
+
+ //! @brief Packed SP-FP Minimum (SSE).
+ void minps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMinPS, &dst, &src); }
+ //! @brief Packed SP-FP Minimum (SSE).
+ void minps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMinPS, &dst, &src); }
+
+ //! @brief Scalar SP-FP Minimum (SSE).
+ void minss(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMinSS, &dst, &src); }
+ //! @brief Scalar SP-FP Minimum (SSE).
+ void minss(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMinSS, &dst, &src); }
+
+ //! @brief Move Aligned Packed SP-FP Values (SSE).
+ void movaps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovAPS, &dst, &src); }
+ //! @brief Move Aligned Packed SP-FP Values (SSE).
+ void movaps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovAPS, &dst, &src); }
+
+ //! @brief Move Aligned Packed SP-FP Values (SSE).
+ void movaps(const Mem& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovAPS, &dst, &src); }
+
+ //! @brief Move DWord.
+ void movd(const Mem& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovD, &dst, &src); }
+ //! @brief Move DWord.
+ void movd(const GpVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovD, &dst, &src); }
+ //! @brief Move DWord.
+ void movd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovD, &dst, &src); }
+ //! @brief Move DWord.
+ void movd(const XmmVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstMovD, &dst, &src); }
+
+ //! @brief Move QWord (SSE).
+ void movq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovQ, &dst, &src); }
+ //! @brief Move QWord (SSE).
+ void movq(const Mem& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovQ, &dst, &src); }
+#if defined(ASMJIT_X64)
+ //! @brief Move QWord (SSE).
+ void movq(const GpVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovQ, &dst, &src); }
+#endif // ASMJIT_X64
+ //! @brief Move QWord (SSE).
+ void movq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovQ, &dst, &src); }
+#if defined(ASMJIT_X64)
+ //! @brief Move QWord (SSE).
+ void movq(const XmmVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstMovQ, &dst, &src); }
+#endif // ASMJIT_X64
+
+ //! @brief Move 64 Bits Non Temporal (SSE).
+ void movntq(const Mem& dst, const MmVar& src)
+ { _emitInstruction(kX86InstMovNTQ, &dst, &src); }
+
+ //! @brief High to Low Packed SP-FP (SSE).
+ void movhlps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovHLPS, &dst, &src); }
+
+ //! @brief Move High Packed SP-FP (SSE).
+ void movhps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovHPS, &dst, &src); }
+
+ //! @brief Move High Packed SP-FP (SSE).
+ void movhps(const Mem& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovHPS, &dst, &src); }
+
+ //! @brief Move Low to High Packed SP-FP (SSE).
+ void movlhps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovLHPS, &dst, &src); }
+
+ //! @brief Move Low Packed SP-FP (SSE).
+ void movlps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovLPS, &dst, &src); }
+
+ //! @brief Move Low Packed SP-FP (SSE).
+ void movlps(const Mem& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovLPS, &dst, &src); }
+
+ //! @brief Move Aligned Four Packed SP-FP Non Temporal (SSE).
+ void movntps(const Mem& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovNTPS, &dst, &src); }
+
+ //! @brief Move Scalar SP-FP (SSE).
+ void movss(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovSS, &dst, &src); }
+
+ //! @brief Move Scalar SP-FP (SSE).
+ void movss(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovSS, &dst, &src); }
+
+ //! @brief Move Scalar SP-FP (SSE).
+ void movss(const Mem& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovSS, &dst, &src); }
+
+ //! @brief Move Unaligned Packed SP-FP Values (SSE).
+ void movups(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovUPS, &dst, &src); }
+ //! @brief Move Unaligned Packed SP-FP Values (SSE).
+ void movups(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovUPS, &dst, &src); }
+
+ //! @brief Move Unaligned Packed SP-FP Values (SSE).
+ void movups(const Mem& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovUPS, &dst, &src); }
+
+ //! @brief Packed SP-FP Multiply (SSE).
+ void mulps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMulPS, &dst, &src); }
+ //! @brief Packed SP-FP Multiply (SSE).
+ void mulps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMulPS, &dst, &src); }
+
+ //! @brief Scalar SP-FP Multiply (SSE).
+ void mulss(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMulSS, &dst, &src); }
+ //! @brief Scalar SP-FP Multiply (SSE).
+ void mulss(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMulSS, &dst, &src); }
+
+ //! @brief Bit-wise Logical OR for SP-FP Data (SSE).
+ void orps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstOrPS, &dst, &src); }
+ //! @brief Bit-wise Logical OR for SP-FP Data (SSE).
+ void orps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstOrPS, &dst, &src); }
+
+ //! @brief Packed Average (SSE).
+ void pavgb(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPAvgB, &dst, &src); }
+ //! @brief Packed Average (SSE).
+ void pavgb(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAvgB, &dst, &src); }
+
+ //! @brief Packed Average (SSE).
+ void pavgw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPAvgW, &dst, &src); }
+ //! @brief Packed Average (SSE).
+ void pavgw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAvgW, &dst, &src); }
+
+ //! @brief Extract Word (SSE).
+ void pextrw(const GpVar& dst, const MmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPExtrW, &dst, &src, &imm8); }
+
+ //! @brief Insert Word (SSE).
+ void pinsrw(const MmVar& dst, const GpVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPInsRW, &dst, &src, &imm8); }
+ //! @brief Insert Word (SSE).
+ void pinsrw(const MmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPInsRW, &dst, &src, &imm8); }
+
+ //! @brief Packed Signed Integer Word Maximum (SSE).
+ void pmaxsw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPMaxSW, &dst, &src); }
+ //! @brief Packed Signed Integer Word Maximum (SSE).
+ void pmaxsw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMaxSW, &dst, &src); }
+
+ //! @brief Packed Unsigned Integer Byte Maximum (SSE).
+ void pmaxub(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPMaxUB, &dst, &src); }
+ //! @brief Packed Unsigned Integer Byte Maximum (SSE).
+ void pmaxub(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMaxUB, &dst, &src); }
+
+ //! @brief Packed Signed Integer Word Minimum (SSE).
+ void pminsw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPMinSW, &dst, &src); }
+ //! @brief Packed Signed Integer Word Minimum (SSE).
+ void pminsw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMinSW, &dst, &src); }
+
+ //! @brief Packed Unsigned Integer Byte Minimum (SSE).
+ void pminub(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPMinUB, &dst, &src); }
+ //! @brief Packed Unsigned Integer Byte Minimum (SSE).
+ void pminub(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMinUB, &dst, &src); }
+
+ //! @brief Move Byte Mask To Integer (SSE).
+ void pmovmskb(const GpVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPMovMskB, &dst, &src); }
+
+ //! @brief Packed Multiply High Unsigned (SSE).
+ void pmulhuw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPMulHUW, &dst, &src); }
+ //! @brief Packed Multiply High Unsigned (SSE).
+ void pmulhuw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulHUW, &dst, &src); }
+
+ //! @brief Packed Sum of Absolute Differences (SSE).
+ void psadbw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSADBW, &dst, &src); }
+ //! @brief Packed Sum of Absolute Differences (SSE).
+ void psadbw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSADBW, &dst, &src); }
+
+ //! @brief Packed Shuffle word (SSE).
+ void pshufw(const MmVar& dst, const MmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPShufW, &dst, &src, &imm8); }
+ //! @brief Packed Shuffle word (SSE).
+ void pshufw(const MmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPShufW, &dst, &src, &imm8); }
+
+ //! @brief Packed SP-FP Reciprocal (SSE).
+ void rcpps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstRcpPS, &dst, &src); }
+ //! @brief Packed SP-FP Reciprocal (SSE).
+ void rcpps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstRcpPS, &dst, &src); }
+
+ //! @brief Scalar SP-FP Reciprocal (SSE).
+ void rcpss(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstRcpSS, &dst, &src); }
+ //! @brief Scalar SP-FP Reciprocal (SSE).
+ void rcpss(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstRcpSS, &dst, &src); }
+
+ //! @brief Prefetch (SSE).
+ void prefetch(const Mem& mem, const Imm& hint)
+ { _emitInstruction(kX86InstPrefetch, &mem, &hint); }
+
+ //! @brief Compute Sum of Absolute Differences (SSE).
+ void psadbw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPSADBW, &dst, &src); }
+ //! @brief Compute Sum of Absolute Differences (SSE).
+ void psadbw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSADBW, &dst, &src); }
+
+ //! @brief Packed SP-FP Square Root Reciprocal (SSE).
+ void rsqrtps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstSqrtPS, &dst, &src); }
+ //! @brief Packed SP-FP Square Root Reciprocal (SSE).
+ void rsqrtps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstSqrtPS, &dst, &src); }
+
+ //! @brief Scalar SP-FP Square Root Reciprocal (SSE).
+ void rsqrtss(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstSqrtSS, &dst, &src); }
+ //! @brief Scalar SP-FP Square Root Reciprocal (SSE).
+ void rsqrtss(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstSqrtSS, &dst, &src); }
+
+ //! @brief Store fence (SSE).
+ void sfence()
+ { _emitInstruction(kX86InstSFence); }
+
+ //! @brief Shuffle SP-FP (SSE).
+ void shufps(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstShufPS, &dst, &src, &imm8); }
+ //! @brief Shuffle SP-FP (SSE).
+ void shufps(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstShufPS, &dst, &src, &imm8); }
+
+ //! @brief Packed SP-FP Square Root (SSE).
+ void sqrtps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstSqrtPS, &dst, &src); }
+ //! @brief Packed SP-FP Square Root (SSE).
+ void sqrtps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstSqrtPS, &dst, &src); }
+
+ //! @brief Scalar SP-FP Square Root (SSE).
+ void sqrtss(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstSqrtSS, &dst, &src); }
+ //! @brief Scalar SP-FP Square Root (SSE).
+ void sqrtss(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstSqrtSS, &dst, &src); }
+
+ //! @brief Store Streaming SIMD Extension Control/Status (SSE).
+ void stmxcsr(const Mem& dst)
+ { _emitInstruction(kX86InstStMXCSR, &dst); }
+
+ //! @brief Packed SP-FP Subtract (SSE).
+ void subps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstSubPS, &dst, &src); }
+ //! @brief Packed SP-FP Subtract (SSE).
+ void subps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstSubPS, &dst, &src); }
+
+ //! @brief Scalar SP-FP Subtract (SSE).
+ void subss(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstSubSS, &dst, &src); }
+ //! @brief Scalar SP-FP Subtract (SSE).
+ void subss(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstSubSS, &dst, &src); }
+
+ //! @brief Unordered Scalar SP-FP compare and set EFLAGS (SSE).
+ void ucomiss(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstUComISS, &dst, &src); }
+ //! @brief Unordered Scalar SP-FP compare and set EFLAGS (SSE).
+ void ucomiss(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstUComISS, &dst, &src); }
+
+ //! @brief Unpack High Packed SP-FP Data (SSE).
+ void unpckhps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstUnpckHPS, &dst, &src); }
+ //! @brief Unpack High Packed SP-FP Data (SSE).
+ void unpckhps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstUnpckHPS, &dst, &src); }
+
+ //! @brief Unpack Low Packed SP-FP Data (SSE).
+ void unpcklps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstUnpckLPS, &dst, &src); }
+ //! @brief Unpack Low Packed SP-FP Data (SSE).
+ void unpcklps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstUnpckLPS, &dst, &src); }
+
+ //! @brief Bit-wise Logical Xor for SP-FP Data (SSE).
+ void xorps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstXorPS, &dst, &src); }
+ //! @brief Bit-wise Logical Xor for SP-FP Data (SSE).
+ void xorps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstXorPS, &dst, &src); }
+
+ // --------------------------------------------------------------------------
+ // [SSE2]
+ // --------------------------------------------------------------------------
+
+ //! @brief Packed DP-FP Add (SSE2).
+ void addpd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstAddPD, &dst, &src); }
+ //! @brief Packed DP-FP Add (SSE2).
+ void addpd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstAddPD, &dst, &src); }
+
+ //! @brief Scalar DP-FP Add (SSE2).
+ void addsd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstAddSD, &dst, &src); }
+ //! @brief Scalar DP-FP Add (SSE2).
+ void addsd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstAddSD, &dst, &src); }
+
+ //! @brief Bit-wise Logical And Not For DP-FP (SSE2).
+ void andnpd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstAndnPD, &dst, &src); }
+ //! @brief Bit-wise Logical And Not For DP-FP (SSE2).
+ void andnpd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstAndnPD, &dst, &src); }
+
+ //! @brief Bit-wise Logical And For DP-FP (SSE2).
+ void andpd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstAndPD, &dst, &src); }
+ //! @brief Bit-wise Logical And For DP-FP (SSE2).
+ void andpd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstAndPD, &dst, &src); }
+
+ //! @brief Flush Cache Line (SSE2).
+ void clflush(const Mem& mem)
+ { _emitInstruction(kX86InstClFlush, &mem); }
+
+ //! @brief Packed DP-FP Compare (SSE2).
+ void cmppd(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstCmpPD, &dst, &src, &imm8); }
+ //! @brief Packed DP-FP Compare (SSE2).
+ void cmppd(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstCmpPD, &dst, &src, &imm8); }
+
+ //! @brief Compare Scalar SP-FP Values (SSE2).
+ void cmpsd(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstCmpSD, &dst, &src, &imm8); }
+ //! @brief Compare Scalar SP-FP Values (SSE2).
+ void cmpsd(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstCmpSD, &dst, &src, &imm8); }
+
+ //! @brief Scalar Ordered DP-FP Compare and Set EFLAGS (SSE2).
+ void comisd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstComISD, &dst, &src); }
+ //! @brief Scalar Ordered DP-FP Compare and Set EFLAGS (SSE2).
+ void comisd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstComISD, &dst, &src); }
+
+ //! @brief Convert Packed Dword Integers to Packed DP-FP Values (SSE2).
+ void cvtdq2pd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstCvtDQ2PD, &dst, &src); }
+ //! @brief Convert Packed Dword Integers to Packed DP-FP Values (SSE2).
+ void cvtdq2pd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtDQ2PD, &dst, &src); }
+
+ //! @brief Convert Packed Dword Integers to Packed SP-FP Values (SSE2).
+ void cvtdq2ps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstCvtDQ2PS, &dst, &src); }
+ //! @brief Convert Packed Dword Integers to Packed SP-FP Values (SSE2).
+ void cvtdq2ps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtDQ2PS, &dst, &src); }
+
+ //! @brief Convert Packed DP-FP Values to Packed Dword Integers (SSE2).
+ void cvtpd2dq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstCvtPD2DQ, &dst, &src); }
+ //! @brief Convert Packed DP-FP Values to Packed Dword Integers (SSE2).
+ void cvtpd2dq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtPD2DQ, &dst, &src); }
+
+ //! @brief Convert Packed DP-FP Values to Packed Dword Integers (SSE2).
+ void cvtpd2pi(const MmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstCvtPD2PI, &dst, &src); }
+ //! @brief Convert Packed DP-FP Values to Packed Dword Integers (SSE2).
+ void cvtpd2pi(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtPD2PI, &dst, &src); }
+
+ //! @brief Convert Packed DP-FP Values to Packed SP-FP Values (SSE2).
+ void cvtpd2ps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstCvtPD2PS, &dst, &src); }
+ //! @brief Convert Packed DP-FP Values to Packed SP-FP Values (SSE2).
+ void cvtpd2ps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtPD2PS, &dst, &src); }
+
+ //! @brief Convert Packed Dword Integers to Packed DP-FP Values (SSE2).
+ void cvtpi2pd(const XmmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstCvtPI2PD, &dst, &src); }
+ //! @brief Convert Packed Dword Integers to Packed DP-FP Values (SSE2).
+ void cvtpi2pd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtPI2PD, &dst, &src); }
+
+ //! @brief Convert Packed SP-FP Values to Packed Dword Integers (SSE2).
+ void cvtps2dq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstCvtPS2DQ, &dst, &src); }
+ //! @brief Convert Packed SP-FP Values to Packed Dword Integers (SSE2).
+ void cvtps2dq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtPS2DQ, &dst, &src); }
+
+ //! @brief Convert Packed SP-FP Values to Packed DP-FP Values (SSE2).
+ void cvtps2pd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstCvtPS2PD, &dst, &src); }
+ //! @brief Convert Packed SP-FP Values to Packed DP-FP Values (SSE2).
+ void cvtps2pd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtPS2PD, &dst, &src); }
+
+ //! @brief Convert Scalar DP-FP Value to Dword Integer (SSE2).
+ void cvtsd2si(const GpVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstCvtSD2SI, &dst, &src); }
+ //! @brief Convert Scalar DP-FP Value to Dword Integer (SSE2).
+ void cvtsd2si(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtSD2SI, &dst, &src); }
+
+ //! @brief Convert Scalar DP-FP Value to Scalar SP-FP Value (SSE2).
+ void cvtsd2ss(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstCvtSD2SS, &dst, &src); }
+ //! @brief Convert Scalar DP-FP Value to Scalar SP-FP Value (SSE2).
+ void cvtsd2ss(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtSD2SS, &dst, &src); }
+
+ //! @brief Convert Dword Integer to Scalar DP-FP Value (SSE2).
+ void cvtsi2sd(const XmmVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstCvtSI2SD, &dst, &src); }
+ //! @brief Convert Dword Integer to Scalar DP-FP Value (SSE2).
+ void cvtsi2sd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtSI2SD, &dst, &src); }
+
+ //! @brief Convert Scalar SP-FP Value to Scalar DP-FP Value (SSE2).
+ void cvtss2sd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstCvtSS2SD, &dst, &src); }
+ //! @brief Convert Scalar SP-FP Value to Scalar DP-FP Value (SSE2).
+ void cvtss2sd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvtSS2SD, &dst, &src); }
+
+ //! @brief Convert with Truncation Packed DP-FP Values to Packed Dword Integers (SSE2).
+ void cvttpd2pi(const MmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstCvttPD2PI, &dst, &src); }
+ //! @brief Convert with Truncation Packed DP-FP Values to Packed Dword Integers (SSE2).
+ void cvttpd2pi(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvttPD2PI, &dst, &src); }
+
+ //! @brief Convert with Truncation Packed DP-FP Values to Packed Dword Integers (SSE2).
+ void cvttpd2dq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstCvttPD2DQ, &dst, &src); }
+ //! @brief Convert with Truncation Packed DP-FP Values to Packed Dword Integers (SSE2).
+ void cvttpd2dq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvttPD2DQ, &dst, &src); }
+
+ //! @brief Convert with Truncation Packed SP-FP Values to Packed Dword Integers (SSE2).
+ void cvttps2dq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstCvttPS2DQ, &dst, &src); }
+ //! @brief Convert with Truncation Packed SP-FP Values to Packed Dword Integers (SSE2).
+ void cvttps2dq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvttPS2DQ, &dst, &src); }
+
+ //! @brief Convert with Truncation Scalar DP-FP Value to Signed Dword Integer (SSE2).
+ void cvttsd2si(const GpVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstCvttSD2SI, &dst, &src); }
+ //! @brief Convert with Truncation Scalar DP-FP Value to Signed Dword Integer (SSE2).
+ void cvttsd2si(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCvttSD2SI, &dst, &src); }
+
+ //! @brief Packed DP-FP Divide (SSE2).
+ void divpd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstDivPD, &dst, &src); }
+ //! @brief Packed DP-FP Divide (SSE2).
+ void divpd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstDivPD, &dst, &src); }
+
+ //! @brief Scalar DP-FP Divide (SSE2).
+ void divsd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstDivSD, &dst, &src); }
+ //! @brief Scalar DP-FP Divide (SSE2).
+ void divsd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstDivSD, &dst, &src); }
+
+ //! @brief Load Fence (SSE2).
+ void lfence()
+ { _emitInstruction(kX86InstLFence); }
+
+ //! @brief Store Selected Bytes of Double Quadword (SSE2).
+ //!
+ //! @note Target is DS:EDI.
+ void maskmovdqu(const GpVar& dst_ptr, const XmmVar& src, const XmmVar& mask)
+ { _emitInstruction(kX86InstMaskMovDQU, &dst_ptr, &src, &mask); }
+
+ //! @brief Return Maximum Packed Double-Precision FP Values (SSE2).
+ void maxpd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMaxPD, &dst, &src); }
+ //! @brief Return Maximum Packed Double-Precision FP Values (SSE2).
+ void maxpd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMaxPD, &dst, &src); }
+
+ //! @brief Return Maximum Scalar Double-Precision FP Value (SSE2).
+ void maxsd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMaxSD, &dst, &src); }
+ //! @brief Return Maximum Scalar Double-Precision FP Value (SSE2).
+ void maxsd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMaxSD, &dst, &src); }
+
+ //! @brief Memory Fence (SSE2).
+ void mfence()
+ { _emitInstruction(kX86InstMFence); }
+
+ //! @brief Return Minimum Packed DP-FP Values (SSE2).
+ void minpd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMinPD, &dst, &src); }
+ //! @brief Return Minimum Packed DP-FP Values (SSE2).
+ void minpd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMinPD, &dst, &src); }
+
+ //! @brief Return Minimum Scalar DP-FP Value (SSE2).
+ void minsd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMinSD, &dst, &src); }
+ //! @brief Return Minimum Scalar DP-FP Value (SSE2).
+ void minsd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMinSD, &dst, &src); }
+
+ //! @brief Move Aligned DQWord (SSE2).
+ void movdqa(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovDQA, &dst, &src); }
+ //! @brief Move Aligned DQWord (SSE2).
+ void movdqa(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovDQA, &dst, &src); }
+
+ //! @brief Move Aligned DQWord (SSE2).
+ void movdqa(const Mem& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovDQA, &dst, &src); }
+
+ //! @brief Move Unaligned Double Quadword (SSE2).
+ void movdqu(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovDQU, &dst, &src); }
+ //! @brief Move Unaligned Double Quadword (SSE2).
+ void movdqu(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovDQU, &dst, &src); }
+
+ //! @brief Move Unaligned Double Quadword (SSE2).
+ void movdqu(const Mem& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovDQU, &dst, &src); }
+
+ //! @brief Extract Packed SP-FP Sign Mask (SSE2).
+ void movmskps(const GpVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovMskPS, &dst, &src); }
+
+ //! @brief Extract Packed DP-FP Sign Mask (SSE2).
+ void movmskpd(const GpVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovMskPD, &dst, &src); }
+
+ //! @brief Move Scalar Double-Precision FP Value (SSE2).
+ void movsd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovSD, &dst, &src); }
+ //! @brief Move Scalar Double-Precision FP Value (SSE2).
+ void movsd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovSD, &dst, &src); }
+
+ //! @brief Move Scalar Double-Precision FP Value (SSE2).
+ void movsd(const Mem& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovSD, &dst, &src); }
+
+ //! @brief Move Aligned Packed Double-Precision FP Values (SSE2).
+ void movapd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovAPD, &dst, &src); }
+
+ //! @brief Move Aligned Packed Double-Precision FP Values (SSE2).
+ void movapd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovAPD, &dst, &src); }
+
+ //! @brief Move Aligned Packed Double-Precision FP Values (SSE2).
+ void movapd(const Mem& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovAPD, &dst, &src); }
+
+ //! @brief Move Quadword from XMM to MMX Technology Register (SSE2).
+ void movdq2q(const MmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovDQ2Q, &dst, &src); }
+
+ //! @brief Move Quadword from MMX Technology to XMM Register (SSE2).
+ void movq2dq(const XmmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstMovQ2DQ, &dst, &src); }
+
+ //! @brief Move High Packed Double-Precision FP Value (SSE2).
+ void movhpd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovHPD, &dst, &src); }
+
+ //! @brief Move High Packed Double-Precision FP Value (SSE2).
+ void movhpd(const Mem& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovHPD, &dst, &src); }
+
+ //! @brief Move Low Packed Double-Precision FP Value (SSE2).
+ void movlpd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovLPD, &dst, &src); }
+
+ //! @brief Move Low Packed Double-Precision FP Value (SSE2).
+ void movlpd(const Mem& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovLPD, &dst, &src); }
+
+ //! @brief Store Double Quadword Using Non-Temporal Hint (SSE2).
+ void movntdq(const Mem& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovNTDQ, &dst, &src); }
+
+ //! @brief Store Store DWORD Using Non-Temporal Hint (SSE2).
+ void movnti(const Mem& dst, const GpVar& src)
+ { _emitInstruction(kX86InstMovNTI, &dst, &src); }
+
+ //! @brief Store Packed Double-Precision FP Values Using Non-Temporal Hint (SSE2).
+ void movntpd(const Mem& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovNTPD, &dst, &src); }
+
+ //! @brief Move Unaligned Packed Double-Precision FP Values (SSE2).
+ void movupd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovUPD, &dst, &src); }
+
+ //! @brief Move Unaligned Packed Double-Precision FP Values (SSE2).
+ void movupd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovUPD, &dst, &src); }
+
+ //! @brief Move Unaligned Packed Double-Precision FP Values (SSE2).
+ void movupd(const Mem& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovUPD, &dst, &src); }
+
+ //! @brief Packed DP-FP Multiply (SSE2).
+ void mulpd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMulPD, &dst, &src); }
+ //! @brief Packed DP-FP Multiply (SSE2).
+ void mulpd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMulPD, &dst, &src); }
+
+ //! @brief Scalar DP-FP Multiply (SSE2).
+ void mulsd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMulSD, &dst, &src); }
+ //! @brief Scalar DP-FP Multiply (SSE2).
+ void mulsd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMulSD, &dst, &src); }
+
+ //! @brief Bit-wise Logical OR for DP-FP Data (SSE2).
+ void orpd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstOrPD, &dst, &src); }
+ //! @brief Bit-wise Logical OR for DP-FP Data (SSE2).
+ void orpd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstOrPD, &dst, &src); }
+
+ //! @brief Pack with Signed Saturation (SSE2).
+ void packsswb(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPackSSWB, &dst, &src); }
+ //! @brief Pack with Signed Saturation (SSE2).
+ void packsswb(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPackSSWB, &dst, &src); }
+
+ //! @brief Pack with Signed Saturation (SSE2).
+ void packssdw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPackSSDW, &dst, &src); }
+ //! @brief Pack with Signed Saturation (SSE2).
+ void packssdw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPackSSDW, &dst, &src); }
+
+ //! @brief Pack with Unsigned Saturation (SSE2).
+ void packuswb(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPackUSWB, &dst, &src); }
+ //! @brief Pack with Unsigned Saturation (SSE2).
+ void packuswb(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPackUSWB, &dst, &src); }
+
+ //! @brief Packed BYTE Add (SSE2).
+ void paddb(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPAddB, &dst, &src); }
+ //! @brief Packed BYTE Add (SSE2).
+ void paddb(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddB, &dst, &src); }
+
+ //! @brief Packed WORD Add (SSE2).
+ void paddw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPAddW, &dst, &src); }
+ //! @brief Packed WORD Add (SSE2).
+ void paddw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddW, &dst, &src); }
+
+ //! @brief Packed DWORD Add (SSE2).
+ void paddd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPAddD, &dst, &src); }
+ //! @brief Packed DWORD Add (SSE2).
+ void paddd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddD, &dst, &src); }
+
+ //! @brief Packed QWORD Add (SSE2).
+ void paddq(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPAddQ, &dst, &src); }
+ //! @brief Packed QWORD Add (SSE2).
+ void paddq(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddQ, &dst, &src); }
+
+ //! @brief Packed QWORD Add (SSE2).
+ void paddq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPAddQ, &dst, &src); }
+ //! @brief Packed QWORD Add (SSE2).
+ void paddq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddQ, &dst, &src); }
+
+ //! @brief Packed Add with Saturation (SSE2).
+ void paddsb(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPAddSB, &dst, &src); }
+ //! @brief Packed Add with Saturation (SSE2).
+ void paddsb(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddSB, &dst, &src); }
+
+ //! @brief Packed Add with Saturation (SSE2).
+ void paddsw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPAddSW, &dst, &src); }
+ //! @brief Packed Add with Saturation (SSE2).
+ void paddsw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddSW, &dst, &src); }
+
+ //! @brief Packed Add Unsigned with Saturation (SSE2).
+ void paddusb(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPAddUSB, &dst, &src); }
+ //! @brief Packed Add Unsigned with Saturation (SSE2).
+ void paddusb(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddUSB, &dst, &src); }
+
+ //! @brief Packed Add Unsigned with Saturation (SSE2).
+ void paddusw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPAddUSW, &dst, &src); }
+ //! @brief Packed Add Unsigned with Saturation (SSE2).
+ void paddusw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAddUSW, &dst, &src); }
+
+ //! @brief Logical AND (SSE2).
+ void pand(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPAnd, &dst, &src); }
+ //! @brief Logical AND (SSE2).
+ void pand(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAnd, &dst, &src); }
+
+ //! @brief Logical AND Not (SSE2).
+ void pandn(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPAndN, &dst, &src); }
+ //! @brief Logical AND Not (SSE2).
+ void pandn(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAndN, &dst, &src); }
+
+ //! @brief Spin Loop Hint (SSE2).
+ void pause()
+ { _emitInstruction(kX86InstPause); }
+
+ //! @brief Packed Average (SSE2).
+ void pavgb(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPAvgB, &dst, &src); }
+ //! @brief Packed Average (SSE2).
+ void pavgb(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAvgB, &dst, &src); }
+
+ //! @brief Packed Average (SSE2).
+ void pavgw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPAvgW, &dst, &src); }
+ //! @brief Packed Average (SSE2).
+ void pavgw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAvgW, &dst, &src); }
+
+ //! @brief Packed Compare for Equal (BYTES) (SSE2).
+ void pcmpeqb(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPCmpEqB, &dst, &src); }
+ //! @brief Packed Compare for Equal (BYTES) (SSE2).
+ void pcmpeqb(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpEqB, &dst, &src); }
+
+ //! @brief Packed Compare for Equal (WORDS) (SSE2).
+ void pcmpeqw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPCmpEqW, &dst, &src); }
+ //! @brief Packed Compare for Equal (WORDS) (SSE2).
+ void pcmpeqw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpEqW, &dst, &src); }
+
+ //! @brief Packed Compare for Equal (DWORDS) (SSE2).
+ void pcmpeqd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPCmpEqD, &dst, &src); }
+ //! @brief Packed Compare for Equal (DWORDS) (SSE2).
+ void pcmpeqd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpEqD, &dst, &src); }
+
+ //! @brief Packed Compare for Greater Than (BYTES) (SSE2).
+ void pcmpgtb(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPCmpGtB, &dst, &src); }
+ //! @brief Packed Compare for Greater Than (BYTES) (SSE2).
+ void pcmpgtb(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpGtB, &dst, &src); }
+
+ //! @brief Packed Compare for Greater Than (WORDS) (SSE2).
+ void pcmpgtw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPCmpGtW, &dst, &src); }
+ //! @brief Packed Compare for Greater Than (WORDS) (SSE2).
+ void pcmpgtw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpGtW, &dst, &src); }
+
+ //! @brief Packed Compare for Greater Than (DWORDS) (SSE2).
+ void pcmpgtd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPCmpGtD, &dst, &src); }
+ //! @brief Packed Compare for Greater Than (DWORDS) (SSE2).
+ void pcmpgtd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpGtD, &dst, &src); }
+
+ //! @brief Extract Word (SSE2).
+ void pextrw(const GpVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPExtrW, &dst, &src, &imm8); }
+ //! @brief Extract Word (SSE2).
+ void pextrw(const Mem& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPExtrW, &dst, &src, &imm8); }
+
+ //! @brief Packed Signed Integer Word Maximum (SSE2).
+ void pmaxsw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMaxSW, &dst, &src); }
+ //! @brief Packed Signed Integer Word Maximum (SSE2).
+ void pmaxsw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMaxSW, &dst, &src); }
+
+ //! @brief Packed Unsigned Integer Byte Maximum (SSE2).
+ void pmaxub(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMaxUB, &dst, &src); }
+ //! @brief Packed Unsigned Integer Byte Maximum (SSE2).
+ void pmaxub(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMaxUB, &dst, &src); }
+
+ //! @brief Packed Signed Integer Word Minimum (SSE2).
+ void pminsw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMinSW, &dst, &src); }
+ //! @brief Packed Signed Integer Word Minimum (SSE2).
+ void pminsw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMinSW, &dst, &src); }
+
+ //! @brief Packed Unsigned Integer Byte Minimum (SSE2).
+ void pminub(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMinUB, &dst, &src); }
+ //! @brief Packed Unsigned Integer Byte Minimum (SSE2).
+ void pminub(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMinUB, &dst, &src); }
+
+ //! @brief Move Byte Mask (SSE2).
+ void pmovmskb(const GpVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMovMskB, &dst, &src); }
+
+ //! @brief Packed Multiply High (SSE2).
+ void pmulhw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMulHW, &dst, &src); }
+ //! @brief Packed Multiply High (SSE2).
+ void pmulhw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulHW, &dst, &src); }
+
+ //! @brief Packed Multiply High Unsigned (SSE2).
+ void pmulhuw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMulHUW, &dst, &src); }
+ //! @brief Packed Multiply High Unsigned (SSE2).
+ void pmulhuw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulHUW, &dst, &src); }
+
+ //! @brief Packed Multiply Low (SSE2).
+ void pmullw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMulLW, &dst, &src); }
+ //! @brief Packed Multiply Low (SSE2).
+ void pmullw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulLW, &dst, &src); }
+
+ //! @brief Packed Multiply to QWORD (SSE2).
+ void pmuludq(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPMulUDQ, &dst, &src); }
+ //! @brief Packed Multiply to QWORD (SSE2).
+ void pmuludq(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulUDQ, &dst, &src); }
+
+ //! @brief Packed Multiply to QWORD (SSE2).
+ void pmuludq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMulUDQ, &dst, &src); }
+ //! @brief Packed Multiply to QWORD (SSE2).
+ void pmuludq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulUDQ, &dst, &src); }
+
+ //! @brief Bitwise Logical OR (SSE2).
+ void por(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPOr, &dst, &src); }
+ //! @brief Bitwise Logical OR (SSE2).
+ void por(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPOr, &dst, &src); }
+
+ //! @brief Packed Shift Left Logical (SSE2).
+ void pslld(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPSllD, &dst, &src); }
+ //! @brief Packed Shift Left Logical (SSE2).
+ void pslld(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSllD, &dst, &src); }
+ //! @brief Packed Shift Left Logical (SSE2).
+ void pslld(const XmmVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSllD, &dst, &src); }
+
+ //! @brief Packed Shift Left Logical (SSE2).
+ void psllq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPSllQ, &dst, &src); }
+ //! @brief Packed Shift Left Logical (SSE2).
+ void psllq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSllQ, &dst, &src); }
+ //! @brief Packed Shift Left Logical (SSE2).
+ void psllq(const XmmVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSllQ, &dst, &src); }
+
+ //! @brief Packed Shift Left Logical (SSE2).
+ void psllw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPSllW, &dst, &src); }
+ //! @brief Packed Shift Left Logical (SSE2).
+ void psllw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSllW, &dst, &src); }
+ //! @brief Packed Shift Left Logical (SSE2).
+ void psllw(const XmmVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSllW, &dst, &src); }
+
+ //! @brief Packed Shift Left Logical (SSE2).
+ void pslldq(const XmmVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSllDQ, &dst, &src); }
+
+ //! @brief Packed Shift Right Arithmetic (SSE2).
+ void psrad(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPSraD, &dst, &src); }
+ //! @brief Packed Shift Right Arithmetic (SSE2).
+ void psrad(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSraD, &dst, &src); }
+ //! @brief Packed Shift Right Arithmetic (SSE2).
+ void psrad(const XmmVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSraD, &dst, &src); }
+
+ //! @brief Packed Shift Right Arithmetic (SSE2).
+ void psraw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPSraW, &dst, &src); }
+ //! @brief Packed Shift Right Arithmetic (SSE2).
+ void psraw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSraW, &dst, &src); }
+ //! @brief Packed Shift Right Arithmetic (SSE2).
+ void psraw(const XmmVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSraW, &dst, &src); }
+
+ //! @brief Packed Subtract (SSE2).
+ void psubb(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPSubB, &dst, &src); }
+ //! @brief Packed Subtract (SSE2).
+ void psubb(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubB, &dst, &src); }
+
+ //! @brief Packed Subtract (SSE2).
+ void psubw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPSubW, &dst, &src); }
+ //! @brief Packed Subtract (SSE2).
+ void psubw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubW, &dst, &src); }
+
+ //! @brief Packed Subtract (SSE2).
+ void psubd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPSubD, &dst, &src); }
+ //! @brief Packed Subtract (SSE2).
+ void psubd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubD, &dst, &src); }
+
+ //! @brief Packed Subtract (SSE2).
+ void psubq(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSubQ, &dst, &src); }
+ //! @brief Packed Subtract (SSE2).
+ void psubq(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubQ, &dst, &src); }
+
+ //! @brief Packed Subtract (SSE2).
+ void psubq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPSubQ, &dst, &src); }
+ //! @brief Packed Subtract (SSE2).
+ void psubq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubQ, &dst, &src); }
+
+ //! @brief Packed Multiply and Add (SSE2).
+ void pmaddwd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMAddWD, &dst, &src); }
+ //! @brief Packed Multiply and Add (SSE2).
+ void pmaddwd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMAddWD, &dst, &src); }
+
+ //! @brief Shuffle Packed DWORDs (SSE2).
+ void pshufd(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPShufD, &dst, &src, &imm8); }
+ //! @brief Shuffle Packed DWORDs (SSE2).
+ void pshufd(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPShufD, &dst, &src, &imm8); }
+
+ //! @brief Shuffle Packed High Words (SSE2).
+ void pshufhw(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPShufHW, &dst, &src, &imm8); }
+ //! @brief Shuffle Packed High Words (SSE2).
+ void pshufhw(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPShufHW, &dst, &src, &imm8); }
+
+ //! @brief Shuffle Packed Low Words (SSE2).
+ void pshuflw(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPShufLW, &dst, &src, &imm8); }
+ //! @brief Shuffle Packed Low Words (SSE2).
+ void pshuflw(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPShufLW, &dst, &src, &imm8); }
+
+ //! @brief Packed Shift Right Logical (SSE2).
+ void psrld(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPSrlD, &dst, &src); }
+ //! @brief Packed Shift Right Logical (SSE2).
+ void psrld(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSrlD, &dst, &src); }
+ //! @brief Packed Shift Right Logical (SSE2).
+ void psrld(const XmmVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSrlD, &dst, &src); }
+
+ //! @brief Packed Shift Right Logical (SSE2).
+ void psrlq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPSrlQ, &dst, &src); }
+ //! @brief Packed Shift Right Logical (SSE2).
+ void psrlq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSrlQ, &dst, &src); }
+ //! @brief Packed Shift Right Logical (SSE2).
+ void psrlq(const XmmVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSrlQ, &dst, &src); }
+
+ //! @brief DQWord Shift Right Logical (MMX).
+ void psrldq(const XmmVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSrlDQ, &dst, &src); }
+
+ //! @brief Packed Shift Right Logical (SSE2).
+ void psrlw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPSrlW, &dst, &src); }
+ //! @brief Packed Shift Right Logical (SSE2).
+ void psrlw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSrlW, &dst, &src); }
+ //! @brief Packed Shift Right Logical (SSE2).
+ void psrlw(const XmmVar& dst, const Imm& src)
+ { _emitInstruction(kX86InstPSrlW, &dst, &src); }
+
+ //! @brief Packed Subtract with Saturation (SSE2).
+ void psubsb(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPSubSB, &dst, &src); }
+ //! @brief Packed Subtract with Saturation (SSE2).
+ void psubsb(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubSB, &dst, &src); }
+
+ //! @brief Packed Subtract with Saturation (SSE2).
+ void psubsw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPSubSW, &dst, &src); }
+ //! @brief Packed Subtract with Saturation (SSE2).
+ void psubsw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubSW, &dst, &src); }
+
+ //! @brief Packed Subtract with Unsigned Saturation (SSE2).
+ void psubusb(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPSubUSB, &dst, &src); }
+ //! @brief Packed Subtract with Unsigned Saturation (SSE2).
+ void psubusb(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubUSB, &dst, &src); }
+
+ //! @brief Packed Subtract with Unsigned Saturation (SSE2).
+ void psubusw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPSubUSW, &dst, &src); }
+ //! @brief Packed Subtract with Unsigned Saturation (SSE2).
+ void psubusw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSubUSW, &dst, &src); }
+
+ //! @brief Unpack High Data (SSE2).
+ void punpckhbw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPunpckHBW, &dst, &src); }
+ //! @brief Unpack High Data (SSE2).
+ void punpckhbw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckHBW, &dst, &src); }
+
+ //! @brief Unpack High Data (SSE2).
+ void punpckhwd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPunpckHWD, &dst, &src); }
+ //! @brief Unpack High Data (SSE2).
+ void punpckhwd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckHWD, &dst, &src); }
+
+ //! @brief Unpack High Data (SSE2).
+ void punpckhdq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPunpckHDQ, &dst, &src); }
+ //! @brief Unpack High Data (SSE2).
+ void punpckhdq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckHDQ, &dst, &src); }
+
+ //! @brief Unpack High Data (SSE2).
+ void punpckhqdq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPunpckHQDQ, &dst, &src); }
+ //! @brief Unpack High Data (SSE2).
+ void punpckhqdq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckHQDQ, &dst, &src); }
+
+ //! @brief Unpack Low Data (SSE2).
+ void punpcklbw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPunpckLBW, &dst, &src); }
+ //! @brief Unpack Low Data (SSE2).
+ void punpcklbw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckLBW, &dst, &src); }
+
+ //! @brief Unpack Low Data (SSE2).
+ void punpcklwd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPunpckLWD, &dst, &src); }
+ //! @brief Unpack Low Data (SSE2).
+ void punpcklwd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckLWD, &dst, &src); }
+
+ //! @brief Unpack Low Data (SSE2).
+ void punpckldq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPunpckLDQ, &dst, &src); }
+ //! @brief Unpack Low Data (SSE2).
+ void punpckldq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckLDQ, &dst, &src); }
+
+ //! @brief Unpack Low Data (SSE2).
+ void punpcklqdq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPunpckLQDQ, &dst, &src); }
+ //! @brief Unpack Low Data (SSE2).
+ void punpcklqdq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPunpckLQDQ, &dst, &src); }
+
+ //! @brief Bitwise Exclusive OR (SSE2).
+ void pxor(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPXor, &dst, &src); }
+ //! @brief Bitwise Exclusive OR (SSE2).
+ void pxor(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPXor, &dst, &src); }
+
+ //! @brief Shuffle DP-FP (SSE2).
+ void shufpd(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstShufPD, &dst, &src, &imm8); }
+ //! @brief Shuffle DP-FP (SSE2).
+ void shufpd(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstShufPD, &dst, &src, &imm8); }
+
+ //! @brief Compute Square Roots of Packed DP-FP Values (SSE2).
+ void sqrtpd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstSqrtPD, &dst, &src); }
+ //! @brief Compute Square Roots of Packed DP-FP Values (SSE2).
+ void sqrtpd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstSqrtPD, &dst, &src); }
+
+ //! @brief Compute Square Root of Scalar DP-FP Value (SSE2).
+ void sqrtsd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstSqrtSD, &dst, &src); }
+ //! @brief Compute Square Root of Scalar DP-FP Value (SSE2).
+ void sqrtsd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstSqrtSD, &dst, &src); }
+
+ //! @brief Packed DP-FP Subtract (SSE2).
+ void subpd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstSubPD, &dst, &src); }
+ //! @brief Packed DP-FP Subtract (SSE2).
+ void subpd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstSubPD, &dst, &src); }
+
+ //! @brief Scalar DP-FP Subtract (SSE2).
+ void subsd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstSubSD, &dst, &src); }
+ //! @brief Scalar DP-FP Subtract (SSE2).
+ void subsd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstSubSD, &dst, &src); }
+
+ //! @brief Scalar Unordered DP-FP Compare and Set EFLAGS (SSE2).
+ void ucomisd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstUComISD, &dst, &src); }
+ //! @brief Scalar Unordered DP-FP Compare and Set EFLAGS (SSE2).
+ void ucomisd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstUComISD, &dst, &src); }
+
+ //! @brief Unpack and Interleave High Packed Double-Precision FP Values (SSE2).
+ void unpckhpd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstUnpckHPD, &dst, &src); }
+ //! @brief Unpack and Interleave High Packed Double-Precision FP Values (SSE2).
+ void unpckhpd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstUnpckHPD, &dst, &src); }
+
+ //! @brief Unpack and Interleave Low Packed Double-Precision FP Values (SSE2).
+ void unpcklpd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstUnpckLPD, &dst, &src); }
+ //! @brief Unpack and Interleave Low Packed Double-Precision FP Values (SSE2).
+ void unpcklpd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstUnpckLPD, &dst, &src); }
+
+ //! @brief Bit-wise Logical OR for DP-FP Data (SSE2).
+ void xorpd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstXorPD, &dst, &src); }
+ //! @brief Bit-wise Logical OR for DP-FP Data (SSE2).
+ void xorpd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstXorPD, &dst, &src); }
+
+ // --------------------------------------------------------------------------
+ // [SSE3]
+ // --------------------------------------------------------------------------
+
+ //! @brief Packed DP-FP Add/Subtract (SSE3).
+ void addsubpd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstAddSubPD, &dst, &src); }
+ //! @brief Packed DP-FP Add/Subtract (SSE3).
+ void addsubpd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstAddSubPD, &dst, &src); }
+
+ //! @brief Packed SP-FP Add/Subtract (SSE3).
+ void addsubps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstAddSubPS, &dst, &src); }
+ //! @brief Packed SP-FP Add/Subtract (SSE3).
+ void addsubps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstAddSubPS, &dst, &src); }
+
+#if ASMJIT_NOT_SUPPORTED_BY_COMPILER
+ // TODO: NOT IMPLEMENTED BY THE COMPILER.
+ //! @brief Store Integer with Truncation (SSE3).
+ void fisttp(const Mem& dst)
+ { _emitInstruction(kX86InstFISttP, &dst); }
+#endif // ASMJIT_NOT_SUPPORTED_BY_COMPILER
+
+ //! @brief Packed DP-FP Horizontal Add (SSE3).
+ void haddpd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstHAddPD, &dst, &src); }
+ //! @brief Packed DP-FP Horizontal Add (SSE3).
+ void haddpd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstHAddPD, &dst, &src); }
+
+ //! @brief Packed SP-FP Horizontal Add (SSE3).
+ void haddps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstHAddPS, &dst, &src); }
+ //! @brief Packed SP-FP Horizontal Add (SSE3).
+ void haddps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstHAddPS, &dst, &src); }
+
+ //! @brief Packed DP-FP Horizontal Subtract (SSE3).
+ void hsubpd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstHSubPD, &dst, &src); }
+ //! @brief Packed DP-FP Horizontal Subtract (SSE3).
+ void hsubpd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstHSubPD, &dst, &src); }
+
+ //! @brief Packed SP-FP Horizontal Subtract (SSE3).
+ void hsubps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstHSubPS, &dst, &src); }
+ //! @brief Packed SP-FP Horizontal Subtract (SSE3).
+ void hsubps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstHSubPS, &dst, &src); }
+
+ //! @brief Load Unaligned Integer 128 Bits (SSE3).
+ void lddqu(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstLdDQU, &dst, &src); }
+
+#if ASMJIT_NOT_SUPPORTED_BY_COMPILER
+ //! @brief Set Up Monitor Address (SSE3).
+ void monitor()
+ { _emitInstruction(kX86InstMonitor); }
+#endif // ASMJIT_NOT_SUPPORTED_BY_COMPILER
+
+ //! @brief Move One DP-FP and Duplicate (SSE3).
+ void movddup(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovDDup, &dst, &src); }
+ //! @brief Move One DP-FP and Duplicate (SSE3).
+ void movddup(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovDDup, &dst, &src); }
+
+ //! @brief Move Packed SP-FP High and Duplicate (SSE3).
+ void movshdup(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovSHDup, &dst, &src); }
+ //! @brief Move Packed SP-FP High and Duplicate (SSE3).
+ void movshdup(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovSHDup, &dst, &src); }
+
+ //! @brief Move Packed SP-FP Low and Duplicate (SSE3).
+ void movsldup(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstMovSLDup, &dst, &src); }
+ //! @brief Move Packed SP-FP Low and Duplicate (SSE3).
+ void movsldup(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovSLDup, &dst, &src); }
+
+#if ASMJIT_NOT_SUPPORTED_BY_COMPILER
+ //! @brief Monitor Wait (SSE3).
+ void mwait()
+ { _emitInstruction(kX86InstMWait); }
+#endif // ASMJIT_NOT_SUPPORTED_BY_COMPILER
+
+ // --------------------------------------------------------------------------
+ // [SSSE3]
+ // --------------------------------------------------------------------------
+
+ //! @brief Packed SIGN (SSSE3).
+ void psignb(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSignB, &dst, &src); }
+ //! @brief Packed SIGN (SSSE3).
+ void psignb(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSignB, &dst, &src); }
+
+ //! @brief Packed SIGN (SSSE3).
+ void psignb(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPSignB, &dst, &src); }
+ //! @brief Packed SIGN (SSSE3).
+ void psignb(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSignB, &dst, &src); }
+
+ //! @brief Packed SIGN (SSSE3).
+ void psignw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSignW, &dst, &src); }
+ //! @brief Packed SIGN (SSSE3).
+ void psignw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSignW, &dst, &src); }
+
+ //! @brief Packed SIGN (SSSE3).
+ void psignw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPSignW, &dst, &src); }
+ //! @brief Packed SIGN (SSSE3).
+ void psignw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSignW, &dst, &src); }
+
+ //! @brief Packed SIGN (SSSE3).
+ void psignd(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPSignD, &dst, &src); }
+ //! @brief Packed SIGN (SSSE3).
+ void psignd(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSignD, &dst, &src); }
+
+ //! @brief Packed SIGN (SSSE3).
+ void psignd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPSignD, &dst, &src); }
+ //! @brief Packed SIGN (SSSE3).
+ void psignd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPSignD, &dst, &src); }
+
+ //! @brief Packed Horizontal Add (SSSE3).
+ void phaddw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPHAddW, &dst, &src); }
+ //! @brief Packed Horizontal Add (SSSE3).
+ void phaddw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHAddW, &dst, &src); }
+
+ //! @brief Packed Horizontal Add (SSSE3).
+ void phaddw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPHAddW, &dst, &src); }
+ //! @brief Packed Horizontal Add (SSSE3).
+ void phaddw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHAddW, &dst, &src); }
+
+ //! @brief Packed Horizontal Add (SSSE3).
+ void phaddd(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPHAddD, &dst, &src); }
+ //! @brief Packed Horizontal Add (SSSE3).
+ void phaddd(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHAddD, &dst, &src); }
+
+ //! @brief Packed Horizontal Add (SSSE3).
+ void phaddd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPHAddD, &dst, &src); }
+ //! @brief Packed Horizontal Add (SSSE3).
+ void phaddd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHAddD, &dst, &src); }
+
+ //! @brief Packed Horizontal Add and Saturate (SSSE3).
+ void phaddsw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPHAddSW, &dst, &src); }
+ //! @brief Packed Horizontal Add and Saturate (SSSE3).
+ void phaddsw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHAddSW, &dst, &src); }
+
+ //! @brief Packed Horizontal Add and Saturate (SSSE3).
+ void phaddsw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPHAddSW, &dst, &src); }
+ //! @brief Packed Horizontal Add and Saturate (SSSE3).
+ void phaddsw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHAddSW, &dst, &src); }
+
+ //! @brief Packed Horizontal Subtract (SSSE3).
+ void phsubw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPHSubW, &dst, &src); }
+ //! @brief Packed Horizontal Subtract (SSSE3).
+ void phsubw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHSubW, &dst, &src); }
+
+ //! @brief Packed Horizontal Subtract (SSSE3).
+ void phsubw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPHSubW, &dst, &src); }
+ //! @brief Packed Horizontal Subtract (SSSE3).
+ void phsubw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHSubW, &dst, &src); }
+
+ //! @brief Packed Horizontal Subtract (SSSE3).
+ void phsubd(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPHSubD, &dst, &src); }
+ //! @brief Packed Horizontal Subtract (SSSE3).
+ void phsubd(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHSubD, &dst, &src); }
+
+ //! @brief Packed Horizontal Subtract (SSSE3).
+ void phsubd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPHSubD, &dst, &src); }
+ //! @brief Packed Horizontal Subtract (SSSE3).
+ void phsubd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHSubD, &dst, &src); }
+
+ //! @brief Packed Horizontal Subtract and Saturate (SSSE3).
+ void phsubsw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPHSubSW, &dst, &src); }
+ //! @brief Packed Horizontal Subtract and Saturate (SSSE3).
+ void phsubsw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHSubSW, &dst, &src); }
+
+ //! @brief Packed Horizontal Subtract and Saturate (SSSE3).
+ void phsubsw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPHSubSW, &dst, &src); }
+ //! @brief Packed Horizontal Subtract and Saturate (SSSE3).
+ void phsubsw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHSubSW, &dst, &src); }
+
+ //! @brief Multiply and Add Packed Signed and Unsigned Bytes (SSSE3).
+ void pmaddubsw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPMAddUBSW, &dst, &src); }
+ //! @brief Multiply and Add Packed Signed and Unsigned Bytes (SSSE3).
+ void pmaddubsw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMAddUBSW, &dst, &src); }
+
+ //! @brief Multiply and Add Packed Signed and Unsigned Bytes (SSSE3).
+ void pmaddubsw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMAddUBSW, &dst, &src); }
+ //! @brief Multiply and Add Packed Signed and Unsigned Bytes (SSSE3).
+ void pmaddubsw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMAddUBSW, &dst, &src); }
+
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsb(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPAbsB, &dst, &src); }
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsb(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAbsB, &dst, &src); }
+
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsb(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPAbsB, &dst, &src); }
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsb(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAbsB, &dst, &src); }
+
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPAbsW, &dst, &src); }
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAbsW, &dst, &src); }
+
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPAbsW, &dst, &src); }
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAbsW, &dst, &src); }
+
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsd(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPAbsD, &dst, &src); }
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsd(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAbsD, &dst, &src); }
+
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPAbsD, &dst, &src); }
+ //! @brief Packed Absolute Value (SSSE3).
+ void pabsd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPAbsD, &dst, &src); }
+
+ //! @brief Packed Multiply High with Round and Scale (SSSE3).
+ void pmulhrsw(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPMulHRSW, &dst, &src); }
+ //! @brief Packed Multiply High with Round and Scale (SSSE3).
+ void pmulhrsw(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulHRSW, &dst, &src); }
+
+ //! @brief Packed Multiply High with Round and Scale (SSSE3).
+ void pmulhrsw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMulHRSW, &dst, &src); }
+ //! @brief Packed Multiply High with Round and Scale (SSSE3).
+ void pmulhrsw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulHRSW, &dst, &src); }
+
+ //! @brief Packed Shuffle Bytes (SSSE3).
+ void pshufb(const MmVar& dst, const MmVar& src)
+ { _emitInstruction(kX86InstPShufB, &dst, &src); }
+ //! @brief Packed Shuffle Bytes (SSSE3).
+ void pshufb(const MmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPShufB, &dst, &src); }
+
+ //! @brief Packed Shuffle Bytes (SSSE3).
+ void pshufb(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPShufB, &dst, &src); }
+ //! @brief Packed Shuffle Bytes (SSSE3).
+ void pshufb(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPShufB, &dst, &src); }
+
+ //! @brief Packed Shuffle Bytes (SSSE3).
+ void palignr(const MmVar& dst, const MmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPAlignR, &dst, &src, &imm8); }
+ //! @brief Packed Shuffle Bytes (SSSE3).
+ void palignr(const MmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPAlignR, &dst, &src, &imm8); }
+
+ //! @brief Packed Shuffle Bytes (SSSE3).
+ void palignr(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPAlignR, &dst, &src, &imm8); }
+ //! @brief Packed Shuffle Bytes (SSSE3).
+ void palignr(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPAlignR, &dst, &src, &imm8); }
+
+ // --------------------------------------------------------------------------
+ // [SSE4.1]
+ // --------------------------------------------------------------------------
+
+ //! @brief Blend Packed DP-FP Values (SSE4.1).
+ void blendpd(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstBlendPD, &dst, &src, &imm8); }
+ //! @brief Blend Packed DP-FP Values (SSE4.1).
+ void blendpd(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstBlendPD, &dst, &src, &imm8); }
+
+ //! @brief Blend Packed SP-FP Values (SSE4.1).
+ void blendps(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstBlendPS, &dst, &src, &imm8); }
+ //! @brief Blend Packed SP-FP Values (SSE4.1).
+ void blendps(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstBlendPS, &dst, &src, &imm8); }
+
+ //! @brief Variable Blend Packed DP-FP Values (SSE4.1).
+ void blendvpd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstBlendVPD, &dst, &src); }
+ //! @brief Variable Blend Packed DP-FP Values (SSE4.1).
+ void blendvpd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstBlendVPD, &dst, &src); }
+
+ //! @brief Variable Blend Packed SP-FP Values (SSE4.1).
+ void blendvps(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstBlendVPS, &dst, &src); }
+ //! @brief Variable Blend Packed SP-FP Values (SSE4.1).
+ void blendvps(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstBlendVPS, &dst, &src); }
+
+ //! @brief Dot Product of Packed DP-FP Values (SSE4.1).
+ void dppd(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstDpPD, &dst, &src, &imm8); }
+ //! @brief Dot Product of Packed DP-FP Values (SSE4.1).
+ void dppd(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstDpPD, &dst, &src, &imm8); }
+
+ //! @brief Dot Product of Packed SP-FP Values (SSE4.1).
+ void dpps(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstDpPS, &dst, &src, &imm8); }
+ //! @brief Dot Product of Packed SP-FP Values (SSE4.1).
+ void dpps(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstDpPS, &dst, &src, &imm8); }
+
+ //! @brief Extract Packed SP-FP Value (SSE4.1).
+ void extractps(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstExtractPS, &dst, &src, &imm8); }
+ //! @brief Extract Packed SP-FP Value (SSE4.1).
+ void extractps(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstExtractPS, &dst, &src, &imm8); }
+
+ //! @brief Load Double Quadword Non-Temporal Aligned Hint (SSE4.1).
+ void movntdqa(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstMovNTDQA, &dst, &src); }
+
+ //! @brief Compute Multiple Packed Sums of Absolute Difference (SSE4.1).
+ void mpsadbw(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstMPSADBW, &dst, &src, &imm8); }
+ //! @brief Compute Multiple Packed Sums of Absolute Difference (SSE4.1).
+ void mpsadbw(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstMPSADBW, &dst, &src, &imm8); }
+
+ //! @brief Pack with Unsigned Saturation (SSE4.1).
+ void packusdw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPackUSDW, &dst, &src); }
+ //! @brief Pack with Unsigned Saturation (SSE4.1).
+ void packusdw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPackUSDW, &dst, &src); }
+
+ //! @brief Variable Blend Packed Bytes (SSE4.1).
+ void pblendvb(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPBlendVB, &dst, &src); }
+ //! @brief Variable Blend Packed Bytes (SSE4.1).
+ void pblendvb(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPBlendVB, &dst, &src); }
+
+ //! @brief Blend Packed Words (SSE4.1).
+ void pblendw(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPBlendW, &dst, &src, &imm8); }
+ //! @brief Blend Packed Words (SSE4.1).
+ void pblendw(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPBlendW, &dst, &src, &imm8); }
+
+ //! @brief Compare Packed Qword Data for Equal (SSE4.1).
+ void pcmpeqq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPCmpEqQ, &dst, &src); }
+ //! @brief Compare Packed Qword Data for Equal (SSE4.1).
+ void pcmpeqq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpEqQ, &dst, &src); }
+
+ //! @brief Extract Byte (SSE4.1).
+ void pextrb(const GpVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPExtrB, &dst, &src, &imm8); }
+ //! @brief Extract Byte (SSE4.1).
+ void pextrb(const Mem& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPExtrB, &dst, &src, &imm8); }
+
+ //! @brief Extract Dword (SSE4.1).
+ void pextrd(const GpVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPExtrD, &dst, &src, &imm8); }
+ //! @brief Extract Dword (SSE4.1).
+ void pextrd(const Mem& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPExtrD, &dst, &src, &imm8); }
+
+ //! @brief Extract Dword (SSE4.1).
+ void pextrq(const GpVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPExtrQ, &dst, &src, &imm8); }
+ //! @brief Extract Dword (SSE4.1).
+ void pextrq(const Mem& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPExtrQ, &dst, &src, &imm8); }
+
+ //! @brief Packed Horizontal Word Minimum (SSE4.1).
+ void phminposuw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPHMinPOSUW, &dst, &src); }
+ //! @brief Packed Horizontal Word Minimum (SSE4.1).
+ void phminposuw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPHMinPOSUW, &dst, &src); }
+
+ //! @brief Insert Byte (SSE4.1).
+ void pinsrb(const XmmVar& dst, const GpVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPInsRB, &dst, &src, &imm8); }
+ //! @brief Insert Byte (SSE4.1).
+ void pinsrb(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPInsRB, &dst, &src, &imm8); }
+
+ //! @brief Insert Dword (SSE4.1).
+ void pinsrd(const XmmVar& dst, const GpVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPInsRD, &dst, &src, &imm8); }
+ //! @brief Insert Dword (SSE4.1).
+ void pinsrd(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPInsRD, &dst, &src, &imm8); }
+
+ //! @brief Insert Dword (SSE4.1).
+ void pinsrq(const XmmVar& dst, const GpVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPInsRQ, &dst, &src, &imm8); }
+ //! @brief Insert Dword (SSE4.1).
+ void pinsrq(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPInsRQ, &dst, &src, &imm8); }
+
+ //! @brief Insert Word (SSE2).
+ void pinsrw(const XmmVar& dst, const GpVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPInsRW, &dst, &src, &imm8); }
+ //! @brief Insert Word (SSE2).
+ void pinsrw(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPInsRW, &dst, &src, &imm8); }
+
+ //! @brief Maximum of Packed Word Integers (SSE4.1).
+ void pmaxuw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMaxUW, &dst, &src); }
+ //! @brief Maximum of Packed Word Integers (SSE4.1).
+ void pmaxuw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMaxUW, &dst, &src); }
+
+ //! @brief Maximum of Packed Signed Byte Integers (SSE4.1).
+ void pmaxsb(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMaxSB, &dst, &src); }
+ //! @brief Maximum of Packed Signed Byte Integers (SSE4.1).
+ void pmaxsb(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMaxSB, &dst, &src); }
+
+ //! @brief Maximum of Packed Signed Dword Integers (SSE4.1).
+ void pmaxsd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMaxSD, &dst, &src); }
+ //! @brief Maximum of Packed Signed Dword Integers (SSE4.1).
+ void pmaxsd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMaxSD, &dst, &src); }
+
+ //! @brief Maximum of Packed Unsigned Dword Integers (SSE4.1).
+ void pmaxud(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMaxUD, &dst, &src); }
+ //! @brief Maximum of Packed Unsigned Dword Integers (SSE4.1).
+ void pmaxud(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMaxUD, &dst, &src); }
+
+ //! @brief Minimum of Packed Signed Byte Integers (SSE4.1).
+ void pminsb(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMinSB, &dst, &src); }
+ //! @brief Minimum of Packed Signed Byte Integers (SSE4.1).
+ void pminsb(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMinSB, &dst, &src); }
+
+ //! @brief Minimum of Packed Word Integers (SSE4.1).
+ void pminuw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMinUW, &dst, &src); }
+ //! @brief Minimum of Packed Word Integers (SSE4.1).
+ void pminuw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMinUW, &dst, &src); }
+
+ //! @brief Minimum of Packed Dword Integers (SSE4.1).
+ void pminud(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMinUD, &dst, &src); }
+ //! @brief Minimum of Packed Dword Integers (SSE4.1).
+ void pminud(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMinUD, &dst, &src); }
+
+ //! @brief Minimum of Packed Dword Integers (SSE4.1).
+ void pminsd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMinSD, &dst, &src); }
+ //! @brief Minimum of Packed Dword Integers (SSE4.1).
+ void pminsd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMinSD, &dst, &src); }
+
+ //! @brief Packed Move with Sign Extend (SSE4.1).
+ void pmovsxbw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMovSXBW, &dst, &src); }
+ //! @brief Packed Move with Sign Extend (SSE4.1).
+ void pmovsxbw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovSXBW, &dst, &src); }
+
+ //! @brief Packed Move with Sign Extend (SSE4.1).
+ void pmovsxbd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMovSXBD, &dst, &src); }
+ //! @brief Packed Move with Sign Extend (SSE4.1).
+ void pmovsxbd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovSXBD, &dst, &src); }
+
+ //! @brief Packed Move with Sign Extend (SSE4.1).
+ void pmovsxbq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMovSXBQ, &dst, &src); }
+ //! @brief Packed Move with Sign Extend (SSE4.1).
+ void pmovsxbq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovSXBQ, &dst, &src); }
+
+ //! @brief Packed Move with Sign Extend (SSE4.1).
+ void pmovsxwd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMovSXWD, &dst, &src); }
+ //! @brief Packed Move with Sign Extend (SSE4.1).
+ void pmovsxwd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovSXWD, &dst, &src); }
+
+ //! @brief (SSE4.1).
+ void pmovsxwq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMovSXWQ, &dst, &src); }
+ //! @brief (SSE4.1).
+ void pmovsxwq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovSXWQ, &dst, &src); }
+
+ //! @brief (SSE4.1).
+ void pmovsxdq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMovSXDQ, &dst, &src); }
+ //! @brief (SSE4.1).
+ void pmovsxdq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovSXDQ, &dst, &src); }
+
+ //! @brief Packed Move with Zero Extend (SSE4.1).
+ void pmovzxbw(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMovZXBW, &dst, &src); }
+ //! @brief Packed Move with Zero Extend (SSE4.1).
+ void pmovzxbw(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovZXBW, &dst, &src); }
+
+ //! @brief Packed Move with Zero Extend (SSE4.1).
+ void pmovzxbd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMovZXBD, &dst, &src); }
+ //! @brief Packed Move with Zero Extend (SSE4.1).
+ void pmovzxbd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovZXBD, &dst, &src); }
+
+ //! @brief Packed Move with Zero Extend (SSE4.1).
+ void pmovzxbq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMovZXBQ, &dst, &src); }
+ //! @brief Packed Move with Zero Extend (SSE4.1).
+ void pmovzxbq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovZXBQ, &dst, &src); }
+
+ //! @brief Packed Move with Zero Extend (SSE4.1).
+ void pmovzxwd(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMovZXWD, &dst, &src); }
+ //! @brief Packed Move with Zero Extend (SSE4.1).
+ void pmovzxwd(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovZXWD, &dst, &src); }
+
+ //! @brief (SSE4.1).
+ void pmovzxwq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMovZXWQ, &dst, &src); }
+ //! @brief (SSE4.1).
+ void pmovzxwq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovZXWQ, &dst, &src); }
+
+ //! @brief (SSE4.1).
+ void pmovzxdq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMovZXDQ, &dst, &src); }
+ //! @brief (SSE4.1).
+ void pmovzxdq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMovZXDQ, &dst, &src); }
+
+ //! @brief Multiply Packed Signed Dword Integers (SSE4.1).
+ void pmuldq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMulDQ, &dst, &src); }
+ //! @brief Multiply Packed Signed Dword Integers (SSE4.1).
+ void pmuldq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulDQ, &dst, &src); }
+
+ //! @brief Multiply Packed Signed Integers and Store Low Result (SSE4.1).
+ void pmulld(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPMulLD, &dst, &src); }
+ //! @brief Multiply Packed Signed Integers and Store Low Result (SSE4.1).
+ void pmulld(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPMulLD, &dst, &src); }
+
+ //! @brief Logical Compare (SSE4.1).
+ void ptest(const XmmVar& op1, const XmmVar& op2)
+ { _emitInstruction(kX86InstPTest, &op1, &op2); }
+ //! @brief Logical Compare (SSE4.1).
+ void ptest(const XmmVar& op1, const Mem& op2)
+ { _emitInstruction(kX86InstPTest, &op1, &op2); }
+
+ //! Round Packed SP-FP Values @brief (SSE4.1).
+ void roundps(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstRoundPS, &dst, &src, &imm8); }
+ //! Round Packed SP-FP Values @brief (SSE4.1).
+ void roundps(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstRoundPS, &dst, &src, &imm8); }
+
+ //! @brief Round Scalar SP-FP Values (SSE4.1).
+ void roundss(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstRoundSS, &dst, &src, &imm8); }
+ //! @brief Round Scalar SP-FP Values (SSE4.1).
+ void roundss(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstRoundSS, &dst, &src, &imm8); }
+
+ //! @brief Round Packed DP-FP Values (SSE4.1).
+ void roundpd(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstRoundPD, &dst, &src, &imm8); }
+ //! @brief Round Packed DP-FP Values (SSE4.1).
+ void roundpd(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstRoundPD, &dst, &src, &imm8); }
+
+ //! @brief Round Scalar DP-FP Values (SSE4.1).
+ void roundsd(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstRoundSD, &dst, &src, &imm8); }
+ //! @brief Round Scalar DP-FP Values (SSE4.1).
+ void roundsd(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstRoundSD, &dst, &src, &imm8); }
+
+ // --------------------------------------------------------------------------
+ // [SSE4.2]
+ // --------------------------------------------------------------------------
+
+ //! @brief Accumulate CRC32 Value (polynomial 0x11EDC6F41) (SSE4.2).
+ void crc32(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstCrc32, &dst, &src); }
+ //! @brief Accumulate CRC32 Value (polynomial 0x11EDC6F41) (SSE4.2).
+ void crc32(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstCrc32, &dst, &src); }
+
+ //! @brief Packed Compare Explicit Length Strings, Return Index (SSE4.2).
+ void pcmpestri(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPCmpEStrI, &dst, &src, &imm8); }
+ //! @brief Packed Compare Explicit Length Strings, Return Index (SSE4.2).
+ void pcmpestri(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPCmpEStrI, &dst, &src, &imm8); }
+
+ //! @brief Packed Compare Explicit Length Strings, Return Mask (SSE4.2).
+ void pcmpestrm(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPCmpEStrM, &dst, &src, &imm8); }
+ //! @brief Packed Compare Explicit Length Strings, Return Mask (SSE4.2).
+ void pcmpestrm(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPCmpEStrM, &dst, &src, &imm8); }
+
+ //! @brief Packed Compare Implicit Length Strings, Return Index (SSE4.2).
+ void pcmpistri(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPCmpIStrI, &dst, &src, &imm8); }
+ //! @brief Packed Compare Implicit Length Strings, Return Index (SSE4.2).
+ void pcmpistri(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPCmpIStrI, &dst, &src, &imm8); }
+
+ //! @brief Packed Compare Implicit Length Strings, Return Mask (SSE4.2).
+ void pcmpistrm(const XmmVar& dst, const XmmVar& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPCmpIStrM, &dst, &src, &imm8); }
+ //! @brief Packed Compare Implicit Length Strings, Return Mask (SSE4.2).
+ void pcmpistrm(const XmmVar& dst, const Mem& src, const Imm& imm8)
+ { _emitInstruction(kX86InstPCmpIStrM, &dst, &src, &imm8); }
+
+ //! @brief Compare Packed Data for Greater Than (SSE4.2).
+ void pcmpgtq(const XmmVar& dst, const XmmVar& src)
+ { _emitInstruction(kX86InstPCmpGtQ, &dst, &src); }
+ //! @brief Compare Packed Data for Greater Than (SSE4.2).
+ void pcmpgtq(const XmmVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPCmpGtQ, &dst, &src); }
+
+ //! @brief Return the Count of Number of Bits Set to 1 (SSE4.2).
+ void popcnt(const GpVar& dst, const GpVar& src)
+ { _emitInstruction(kX86InstPopCnt, &dst, &src); }
+ //! @brief Return the Count of Number of Bits Set to 1 (SSE4.2).
+ void popcnt(const GpVar& dst, const Mem& src)
+ { _emitInstruction(kX86InstPopCnt, &dst, &src); }
+
+ // --------------------------------------------------------------------------
+ // [AMD only]
+ // --------------------------------------------------------------------------
+
+ //! @brief Prefetch (3dNow - Amd).
+ //!
+ //! Loads the entire 64-byte aligned memory sequence containing the
+ //! specified memory address into the L1 data cache. The position of
+ //! the specified memory address within the 64-byte cache line is
+ //! irrelevant. If a cache hit occurs, or if a memory fault is detected,
+ //! no bus cycle is initiated and the instruction is treated as a NOP.
+ void amd_prefetch(const Mem& mem)
+ { _emitInstruction(kX86InstAmdPrefetch, &mem); }
+
+ //! @brief Prefetch and set cache to modified (3dNow - Amd).
+ //!
+ //! The PREFETCHW instruction loads the prefetched line and sets the
+ //! cache-line state to Modified, in anticipation of subsequent data
+ //! writes to the line. The PREFETCH instruction, by contrast, typically
+ //! sets the cache-line state to Exclusive (depending on the hardware
+ //! implementation).
+ void amd_prefetchw(const Mem& mem)
+ { _emitInstruction(kX86InstAmdPrefetchW, &mem); }
+
+ // --------------------------------------------------------------------------
+ // [Intel only]
+ // --------------------------------------------------------------------------
+
+ //! @brief Move Data After Swapping Bytes (SSE3 - Intel Atom).
+ void movbe(const GpVar& dst, const Mem& src)
+ {
+ ASMJIT_ASSERT(!dst.isGpb());
+ _emitInstruction(kX86InstMovBE, &dst, &src);
+ }
+
+ //! @brief Move Data After Swapping Bytes (SSE3 - Intel Atom).
+ void movbe(const Mem& dst, const GpVar& src)
+ {
+ ASMJIT_ASSERT(!src.isGpb());
+ _emitInstruction(kX86InstMovBE, &dst, &src);
+ }
+
+ // -------------------------------------------------------------------------
+ // [Emit Options]
+ // -------------------------------------------------------------------------
+
+ //! @brief Assert LOCK# Signal Prefix.
+ //!
+ //! This instruction causes the processor's LOCK# signal to be asserted
+ //! during execution of the accompanying instruction (turns the
+ //! instruction into an atomic instruction). In a multiprocessor environment,
+ //! the LOCK# signal insures that the processor has exclusive use of any shared
+ //! memory while the signal is asserted.
+ //!
+ //! The LOCK prefix can be prepended only to the following instructions and
+ //! to those forms of the instructions that use a memory operand: ADD, ADC,
+ //! AND, BTC, BTR, BTS, CMPXCHG, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD,
+ //! and XCHG. An undefined opcode exception will be generated if the LOCK
+ //! prefix is used with any other instruction. The XCHG instruction always
+ //! asserts the LOCK# signal regardless of the presence or absence of the LOCK
+ //! prefix.
+ void lock()
+ { _emitOptions |= kX86EmitOptionLock; }
+
+ //! @brief Force REX prefix to be emitted.
+ //!
+ //! This option should be used carefully, because there are unencodable
+ //! combinations. If you want to access ah, bh, ch or dh registers then you
+ //! can't emit REX prefix and it will cause an illegal instruction error.
+ //!
+ //! @note REX prefix is only valid for X64/AMD64 platform.
+ //!
+ //! @sa @c kX86EmitOptionRex.
+ void rex()
+ { _emitOptions |= kX86EmitOptionRex; }
+};
+
+//! @}
+
+} // AsmJit namespace
+
+#undef ASMJIT_NOT_SUPPORTED_BY_COMPILER
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_X86_X86COMPILER_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86/x86compilercontext.cpp
@@ -1,1 +1,1875 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/intutil.h"
+#include "../core/stringutil.h"
+
+#include "../x86/x86assembler.h"
+#include "../x86/x86compiler.h"
+#include "../x86/x86compilercontext.h"
+#include "../x86/x86compilerfunc.h"
+#include "../x86/x86compileritem.h"
+#include "../x86/x86util.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit {
+
+// ============================================================================
+// [AsmJit::CompilerContext - Construction / Destruction]
+// ============================================================================
+
+X86CompilerContext::X86CompilerContext(X86Compiler* x86Compiler) :
+ CompilerContext(x86Compiler)
+{
+ _state = &_x86State;
+
+ _clear();
+ _emitComments = !!x86Compiler->getLogger();
+}
+
+X86CompilerContext::~X86CompilerContext()
+{
+}
+
+// ============================================================================
+// [AsmJit::CompilerContext - Clear]
+// ============================================================================
+
+void X86CompilerContext::_clear()
+{
+ _zoneMemory.clear();
+ _func = nullptr;
+
+ _start = nullptr;
+ _stop = nullptr;
+
+ _x86State.clear();
+ _active = nullptr;
+
+ _forwardJumps = nullptr;
+
+ _currentOffset = 0;
+ _isUnreachable = 0;
+
+ _modifiedGpRegisters = 0;
+ _modifiedMmRegisters = 0;
+ _modifiedXmmRegisters = 0;
+
+ _allocableEBP = false;
+
+ _adjustESP = 0;
+
+ _argumentsBaseReg = kRegIndexInvalid; // Used by patcher.
+ _argumentsBaseOffset = 0; // Used by patcher.
+ _argumentsActualDisp = 0; // Used by translate().
+
+ _variablesBaseReg = kRegIndexInvalid; // Used by patcher.
+ _variablesBaseOffset = 0; // Used by patcher.
+ _variablesActualDisp = 0; // Used by translate()
+
+ _memUsed = nullptr;
+ _memFree = nullptr;
+
+ _mem4BlocksCount = 0;
+ _mem8BlocksCount = 0;
+ _mem16BlocksCount = 0;
+
+ _memBytesTotal = 0;
+
+ _backCode.clear();
+ _backPos = 0;
+}
+
+// ============================================================================
+// [AsmJit::CompilerContext - Construction / Destruction]
+// ============================================================================
+
+void X86CompilerContext::allocVar(X86CompilerVar* var, uint32_t regMask, uint32_t vflags)
+{
+ switch (var->getType())
+ {
+ case kX86VarTypeGpd:
+#if defined(ASMJIT_X64)
+ case kX86VarTypeGpq:
+#endif // ASMJIT_X64
+ allocGpVar(var, regMask, vflags);
+ break;
+
+ case kX86VarTypeX87:
+ case kX86VarTypeX87SS:
+ case kX86VarTypeX87SD:
+ // TODO: X87 Support.
+ break;
+
+ case kX86VarTypeMm:
+ allocMmVar(var, regMask, vflags);
+ break;
+
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ allocXmmVar(var, regMask, vflags);
+ break;
+ }
+
+ _postAlloc(var, vflags);
+}
+
+void X86CompilerContext::saveVar(X86CompilerVar* var)
+{
+ switch (var->getType())
+ {
+ case kX86VarTypeGpd:
+#if defined(ASMJIT_X64)
+ case kX86VarTypeGpq:
+#endif // ASMJIT_X64
+ saveGpVar(var);
+ break;
+
+ case kX86VarTypeX87:
+ case kX86VarTypeX87SS:
+ case kX86VarTypeX87SD:
+ // TODO: X87 Support.
+ break;
+
+ case kX86VarTypeMm:
+ saveMmVar(var);
+ break;
+
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ saveXmmVar(var);
+ break;
+ }
+}
+
+void X86CompilerContext::spillVar(X86CompilerVar* var)
+{
+ switch (var->getType())
+ {
+ case kX86VarTypeGpd:
+#if defined(ASMJIT_X64)
+ case kX86VarTypeGpq:
+#endif // ASMJIT_X64
+ spillGpVar(var);
+ break;
+
+ case kX86VarTypeX87:
+ case kX86VarTypeX87SS:
+ case kX86VarTypeX87SD:
+ // TODO: X87 Support.
+ break;
+
+ case kX86VarTypeMm:
+ spillMmVar(var);
+ break;
+
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ spillXmmVar(var);
+ break;
+ }
+}
+
+void X86CompilerContext::unuseVar(X86CompilerVar* var, uint32_t toState)
+{
+ ASMJIT_ASSERT(toState != kVarStateReg);
+
+ if (var->state == kVarStateReg)
+ {
+ uint32_t regIndex = var->regIndex;
+ switch (var->getType())
+ {
+ case kX86VarTypeGpd:
+#if defined(ASMJIT_X64)
+ case kX86VarTypeGpq:
+#endif // ASMJIT_X64
+ _x86State.gp[regIndex] = nullptr;
+ _freedGpRegister(regIndex);
+ break;
+
+ case kX86VarTypeX87:
+ case kX86VarTypeX87SS:
+ case kX86VarTypeX87SD:
+ // TODO: X87 Support.
+ break;
+
+ case kX86VarTypeMm:
+ _x86State.mm[regIndex] = nullptr;
+ _freedMmRegister(regIndex);
+ break;
+
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ _x86State.xmm[regIndex] = nullptr;
+ _freedXmmRegister(regIndex);
+ break;
+ }
+ }
+
+ var->state = toState;
+ var->changed = false;
+ var->regIndex = kRegIndexInvalid;
+}
+
+void X86CompilerContext::allocGpVar(X86CompilerVar* var, uint32_t regMask, uint32_t vflags)
+{
+ uint32_t fullMask = IntUtil::maskUpToIndex(kX86RegNumGp) & ~IntUtil::maskFromIndex(kX86RegIndexEsp);
+ if (!_allocableEBP)
+ fullMask &= ~IntUtil::maskFromIndex(kX86RegIndexEbp);
+
+ // Fix the regMask (0 or full bit-array means that any register may be used).
+ if (!regMask)
+ regMask = 0xFFFFFFFF;
+ regMask &= fullMask;
+
+ // Working variables.
+ uint32_t i;
+ uint32_t mask;
+
+ // Last register code (aka home).
+ uint32_t home = var->homeRegisterIndex;
+ // New register code.
+ uint32_t idx = kRegIndexInvalid;
+
+ // Preserved GP variables.
+ uint32_t preservedGP = var->funcScope->getDecl()->getGpPreservedMask();
+
+ // Spill candidate.
+ X86CompilerVar* spillCandidate = nullptr;
+
+ // Whether to alloc the non-preserved variables first.
+ bool nonPreservedFirst = true;
+
+ if (getFunc()->isCaller())
+ nonPreservedFirst = !var->funcCall || (var->funcCall->getOffset() >= var->lastItem->getOffset());
+
+ // --------------------------------------------------------------------------
+ // [Already Allocated]
+ // --------------------------------------------------------------------------
+
+ // Go away if variable is already allocated.
+ if (var->state == kVarStateReg)
+ {
+ uint32_t oldIndex = var->regIndex;
+
+ // Already allocated in the right register.
+ if (IntUtil::maskFromIndex(oldIndex) & regMask)
+ return;
+
+ // Try to find unallocated register first.
+ mask = regMask & ~_x86State.usedGP;
+ if (mask)
+ {
+ idx = IntUtil::findFirstBit(nonPreservedFirst && (mask & ~preservedGP) ? mask & ~preservedGP : mask);
+ }
+ // Then find the allocated and exchange later.
+ else
+ {
+ idx = IntUtil::findFirstBit(regMask & _x86State.usedGP);
+ }
+ ASMJIT_ASSERT(idx != kRegIndexInvalid);
+
+ X86CompilerVar* other = _x86State.gp[idx];
+ emitExchangeVar(var, idx, vflags, other);
+
+ _x86State.gp[oldIndex] = other;
+ _x86State.gp[idx ] = var;
+
+ if (other)
+ other->regIndex = oldIndex;
+ else
+ _freedGpRegister(oldIndex);
+
+ // Update X86CompilerVar.
+ var->state = kVarStateReg;
+ var->regIndex = idx;
+ var->homeRegisterIndex = idx;
+
+ _allocatedGpRegister(idx);
+ return;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Find Unused GP]
+ // --------------------------------------------------------------------------
+
+ // Home register code.
+ if ((idx == kRegIndexInvalid) &&
+ (home != kRegIndexInvalid) &&
+ (regMask & IntUtil::maskFromIndex(home)) &&
+ !(_x86State.usedGP & IntUtil::maskFromIndex(home)))
+ {
+ idx = home;
+ goto _Alloc;
+ }
+
+ // We start from 1, because EAX/RAX register is sometimes explicitly
+ // needed. So we trying to prevent reallocation in near future.
+ if (idx == kRegIndexInvalid)
+ {
+ for (i = 1, mask = (1 << i); i < kX86RegNumGp; i++, mask <<= 1)
+ {
+ if ((regMask & mask) && !(_x86State.usedGP & mask))
+ {
+ // Convenience to alloc non-preserved first or non-preserved last.
+ if (nonPreservedFirst)
+ {
+ if (idx != kRegIndexInvalid && (preservedGP & mask))
+ continue;
+
+ idx = i;
+ // If current register is preserved, we should try to find different
+ // one that is not. This can save one push / pop in prolog / epilog.
+ if (!(preservedGP & mask))
+ break;
+ }
+ else
+ {
+ if (idx != kRegIndexInvalid && !(preservedGP & mask))
+ continue;
+
+ idx = i;
+ // The opposite.
+ if (preservedGP & mask)
+ break;
+ }
+ }
+ }
+ }
+
+ // If not found, try EAX/RAX.
+ if ((idx == kRegIndexInvalid) &&
+ (regMask & IntUtil::maskFromIndex(kX86RegIndexEax)) &&
+ !(_x86State.usedGP & IntUtil::maskFromIndex(kX86RegIndexEax)))
+ {
+ idx = kX86RegIndexEax;
+ goto _Alloc;
+ }
+
+ // If regMask contains restricted registers which may be used then everything
+ // is handled inside this block.
+ if ((idx == kRegIndexInvalid) && (regMask != fullMask))
+ {
+ // Try to find unallocated register first.
+ mask = regMask & ~_x86State.usedGP;
+ if (mask)
+ {
+ idx = IntUtil::findFirstBit(nonPreservedFirst && (mask & ~preservedGP) ? (mask & ~preservedGP) : mask);
+ ASMJIT_ASSERT(idx != kRegIndexInvalid);
+ }
+ // Then find the allocated and spill later.
+ else
+ {
+ idx = IntUtil::findFirstBit(regMask & _x86State.usedGP);
+ ASMJIT_ASSERT(idx != kRegIndexInvalid);
+
+ // Spill register we need.
+ spillCandidate = _x86State.gp[idx];
+
+ // Jump to spill part of allocation.
+ goto L_Spill;
+ }
+ }
+
+ // --------------------------------------------------------------------------
+ // [Spill]
+ // --------------------------------------------------------------------------
+
+ // If register is still not found, spill other variable.
+ if (idx == kRegIndexInvalid)
+ {
+ if (!spillCandidate)
+ {
+ spillCandidate = _getSpillCandidateGP();
+ }
+
+ // Spill candidate not found?
+ if (!spillCandidate)
+ {
+ _compiler->setError(kErrorNoRegisters);
+ return;
+ }
+
+L_Spill:
+ // Prevented variables can't be spilled. _getSpillCandidate() never returns
+ // prevented variables, but when jumping to L_Spill it could happen.
+ if (spillCandidate->workOffset == _currentOffset)
+ {
+ _compiler->setError(kErrorOverlappedRegisters);
+ return;
+ }
+
+ idx = spillCandidate->regIndex;
+ spillGpVar(spillCandidate);
+ }
+
+ // --------------------------------------------------------------------------
+ // [Alloc]
+ // --------------------------------------------------------------------------
+
+_Alloc:
+ if (var->state == kVarStateMem && (vflags & kVarAllocRead))
+ {
+ emitLoadVar(var, idx);
+ }
+
+ // Update X86CompilerVar.
+ var->state = kVarStateReg;
+ var->regIndex = idx;
+ var->homeRegisterIndex = idx;
+
+ // Update CompilerState.
+ _allocatedVariable(var);
+}
+
+void X86CompilerContext::saveGpVar(X86CompilerVar* var)
+{
+ // Can't save variable that isn't allocated.
+ ASMJIT_ASSERT(var->state == kVarStateReg);
+ ASMJIT_ASSERT(var->regIndex != kRegIndexInvalid);
+
+ uint32_t idx = var->regIndex;
+ emitSaveVar(var, idx);
+
+ // Update X86CompilerVar.
+ var->changed = false;
+}
+
+void X86CompilerContext::spillGpVar(X86CompilerVar* var)
+{
+ // Can't spill variable that isn't allocated.
+ ASMJIT_ASSERT(var->state == kVarStateReg);
+ ASMJIT_ASSERT(var->regIndex != kRegIndexInvalid);
+
+ uint32_t idx = var->regIndex;
+
+ if (var->changed) emitSaveVar(var, idx);
+
+ // Update X86CompilerVar.
+ var->regIndex = kRegIndexInvalid;
+ var->state = kVarStateMem;
+ var->changed = false;
+
+ // Update CompilerState.
+ _x86State.gp[idx] = nullptr;
+ _freedGpRegister(idx);
+}
+
+void X86CompilerContext::allocMmVar(X86CompilerVar* var, uint32_t regMask, uint32_t vflags)
+{
+ // Fix the regMask (0 or full bit-array means that any register may be used).
+ if (!regMask) regMask = IntUtil::maskUpToIndex(kX86RegNumMm);
+ regMask &= IntUtil::maskUpToIndex(kX86RegNumMm);
+
+ // Working variables.
+ uint32_t i;
+ uint32_t mask;
+
+ // Last register code (aka home).
+ uint32_t home = var->homeRegisterIndex;
+ // New register code.
+ uint32_t idx = kRegIndexInvalid;
+
+ // Preserved MM variables.
+ //
+ // NOTE: Currently MM variables are not preserved and there is no calling
+ // convention known to me that does that. But on the other side it's possible
+ // to write such calling convention.
+ uint32_t preservedMM = var->funcScope->getDecl()->getMmPreservedMask();
+
+ // Spill candidate.
+ X86CompilerVar* spillCandidate = nullptr;
+
+ // Whether to alloc non-preserved first or last.
+ bool nonPreservedFirst = true;
+ if (this->getFunc()->isCaller())
+ {
+ nonPreservedFirst = !var->funcCall || var->funcCall->getOffset() >= var->lastItem->getOffset();
+ }
+
+ // --------------------------------------------------------------------------
+ // [Already Allocated]
+ // --------------------------------------------------------------------------
+
+ // Go away if variable is already allocated.
+ if (var->state == kVarStateReg)
+ {
+ uint32_t oldIndex = var->regIndex;
+
+ // Already allocated in the right register.
+ if (IntUtil::maskFromIndex(oldIndex) & regMask) return;
+
+ // Try to find unallocated register first.
+ mask = regMask & ~_x86State.usedMM;
+ if (mask)
+ {
+ idx = IntUtil::findFirstBit(
+ nonPreservedFirst && (mask & ~preservedMM) ? mask & ~preservedMM : mask);
+ }
+ // Then find the allocated and exchange later.
+ else
+ {
+ idx = IntUtil::findFirstBit(regMask & _x86State.usedMM);
+ }
+ ASMJIT_ASSERT(idx != kRegIndexInvalid);
+
+ X86CompilerVar* other = _x86State.mm[idx];
+ if (other) spillMmVar(other);
+
+ emitMoveVar(var, idx, vflags);
+ _freedMmRegister(oldIndex);
+ _x86State.mm[idx] = var;
+
+ // Update X86CompilerVar.
+ var->state = kVarStateReg;
+ var->regIndex = idx;
+ var->homeRegisterIndex = idx;
+
+ _allocatedMmRegister(idx);
+ return;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Find Unused MM]
+ // --------------------------------------------------------------------------
+
+ // If regMask contains restricted registers which may be used then everything
+ // is handled in this block.
+ if (regMask != IntUtil::maskUpToIndex(kX86RegNumMm))
+ {
+ // Try to find unallocated register first.
+ mask = regMask & ~_x86State.usedMM;
+ if (mask)
+ {
+ idx = IntUtil::findFirstBit(
+ nonPreservedFirst && (mask & ~preservedMM) ? mask & ~preservedMM : mask);
+ ASMJIT_ASSERT(idx != kRegIndexInvalid);
+ }
+ // Then find the allocated and spill later.
+ else
+ {
+ idx = IntUtil::findFirstBit(regMask & _x86State.usedMM);
+ ASMJIT_ASSERT(idx != kRegIndexInvalid);
+
+ // Spill register we need.
+ spillCandidate = _x86State.mm[idx];
+
+ // Jump to spill part of allocation.
+ goto L_Spill;
+ }
+ }
+
+ // Home register code.
+ if (idx == kRegIndexInvalid && home != kRegIndexInvalid)
+ {
+ if (!(_x86State.usedMM & (1U << home))) idx = home;
+ }
+
+ if (idx == kRegIndexInvalid)
+ {
+ for (i = 0, mask = (1 << i); i < kX86RegNumMm; i++, mask <<= 1)
+ {
+ if (!(_x86State.usedMM & mask))
+ {
+ // Convenience to alloc non-preserved first or non-preserved last.
+ if (nonPreservedFirst)
+ {
+ if (idx != kRegIndexInvalid && (preservedMM & mask)) continue;
+ idx = i;
+ // If current register is preserved, we should try to find different
+ // one that is not. This can save one push / pop in prolog / epilog.
+ if (!(preservedMM & mask)) break;
+ }
+ else
+ {
+ if (idx != kRegIndexInvalid && !(preservedMM & mask)) continue;
+ idx = i;
+ // The opposite.
+ if (preservedMM & mask) break;
+ }
+ }
+ }
+ }
+
+ // --------------------------------------------------------------------------
+ // [Spill]
+ // --------------------------------------------------------------------------
+
+ // If register is still not found, spill other variable.
+ if (idx == kRegIndexInvalid)
+ {
+ if (!spillCandidate) spillCandidate = _getSpillCandidateMM();
+
+ // Spill candidate not found?
+ if (!spillCandidate)
+ {
+ _compiler->setError(kErrorNoRegisters);
+ return;
+ }
+
+L_Spill:
+
+ // Prevented variables can't be spilled. _getSpillCandidate() never returns
+ // prevented variables, but when jumping to L_spill it can happen.
+ if (spillCandidate->workOffset == _currentOffset)
+ {
+ _compiler->setError(kErrorOverlappedRegisters);
+ return;
+ }
+
+ idx = spillCandidate->regIndex;
+ spillMmVar(spillCandidate);
+ }
+
+ // --------------------------------------------------------------------------
+ // [Alloc]
+ // --------------------------------------------------------------------------
+
+ if (var->state == kVarStateMem && (vflags & kVarAllocRead))
+ {
+ emitLoadVar(var, idx);
+ }
+
+ // Update X86CompilerVar.
+ var->state = kVarStateReg;
+ var->regIndex = idx;
+ var->homeRegisterIndex = idx;
+
+ // Update CompilerState.
+ _allocatedVariable(var);
+}
+
+void X86CompilerContext::saveMmVar(X86CompilerVar* var)
+{
+ // Can't save variable that isn't allocated.
+ ASMJIT_ASSERT(var->state == kVarStateReg);
+ ASMJIT_ASSERT(var->regIndex != kRegIndexInvalid);
+
+ uint32_t idx = var->regIndex;
+ emitSaveVar(var, idx);
+
+ // Update X86CompilerVar.
+ var->changed = false;
+}
+
+void X86CompilerContext::spillMmVar(X86CompilerVar* var)
+{
+ // Can't spill variable that isn't allocated.
+ ASMJIT_ASSERT(var->state == kVarStateReg);
+ ASMJIT_ASSERT(var->regIndex != kRegIndexInvalid);
+
+ uint32_t idx = var->regIndex;
+
+ if (var->changed) emitSaveVar(var, idx);
+
+ // Update X86CompilerVar.
+ var->regIndex = kRegIndexInvalid;
+ var->state = kVarStateMem;
+ var->changed = false;
+
+ // Update CompilerState.
+ _x86State.mm[idx] = nullptr;
+ _freedMmRegister(idx);
+}
+
+void X86CompilerContext::allocXmmVar(X86CompilerVar* var, uint32_t regMask, uint32_t vflags)
+{
+ // Fix the regMask (0 or full bit-array means that any register may be used).
+ if (!regMask) regMask = IntUtil::maskUpToIndex(kX86RegNumXmm);
+ regMask &= IntUtil::maskUpToIndex(kX86RegNumXmm);
+
+ // Working variables.
+ uint32_t i;
+ uint32_t mask;
+
+ // Last register code (aka home).
+ uint32_t home = var->homeRegisterIndex;
+ // New register code.
+ uint32_t idx = kRegIndexInvalid;
+
+ // Preserved XMM variables.
+ uint32_t preservedXMM = var->funcScope->getDecl()->getXmmPreservedMask();
+
+ // Spill candidate.
+ X86CompilerVar* spillCandidate = nullptr;
+
+ // Whether to alloc non-preserved first or last.
+ bool nonPreservedFirst = true;
+
+ if (this->getFunc()->isCaller())
+ nonPreservedFirst = !var->funcCall || (var->funcCall->getOffset() >= var->lastItem->getOffset());
+
+ // --------------------------------------------------------------------------
+ // [Already Allocated]
+ // --------------------------------------------------------------------------
+
+ // Go away if variable is already allocated.
+ if (var->state == kVarStateReg)
+ {
+ uint32_t oldIndex = var->regIndex;
+
+ // Already allocated in the right register.
+ if (IntUtil::maskFromIndex(oldIndex) & regMask) return;
+
+ // Try to find unallocated register first.
+ mask = regMask & ~_x86State.usedXMM;
+ if (mask)
+ {
+ idx = IntUtil::findFirstBit(
+ nonPreservedFirst && (mask & ~preservedXMM) ? mask & ~preservedXMM : mask);
+ }
+ // Then find the allocated and exchange later.
+ else
+ {
+ idx = IntUtil::findFirstBit(regMask & _x86State.usedXMM);
+ }
+ ASMJIT_ASSERT(idx != kRegIndexInvalid);
+
+ X86CompilerVar* other = _x86State.xmm[idx];
+ if (other) spillXmmVar(other);
+
+ emitMoveVar(var, idx, vflags);
+ _freedXmmRegister(oldIndex);
+ _x86State.xmm[idx] = var;
+
+ // Update X86CompilerVar.
+ var->state = kVarStateReg;
+ var->regIndex = idx;
+ var->homeRegisterIndex = idx;
+
+ _allocatedXmmRegister(idx);
+ return;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Find Unused XMM]
+ // --------------------------------------------------------------------------
+
+ // If regMask contains restricted registers which may be used then everything
+ // is handled in this block.
+ if (regMask != IntUtil::maskUpToIndex(kX86RegNumXmm))
+ {
+ // Try to find unallocated register first.
+ mask = regMask & ~_x86State.usedXMM;
+ if (mask)
+ {
+ idx = IntUtil::findFirstBit(
+ nonPreservedFirst && (mask & ~preservedXMM) ? mask & ~preservedXMM : mask);
+ ASMJIT_ASSERT(idx != kRegIndexInvalid);
+ }
+ // Then find the allocated and spill later.
+ else
+ {
+ idx = IntUtil::findFirstBit(regMask & _x86State.usedXMM);
+ ASMJIT_ASSERT(idx != kRegIndexInvalid);
+
+ // Spill register we need.
+ spillCandidate = _x86State.xmm[idx];
+
+ // Jump to spill part of allocation.
+ goto L_Spill;
+ }
+ }
+
+ // Home register code.
+ if (idx == kRegIndexInvalid && home != kRegIndexInvalid)
+ {
+ if (!(_x86State.usedXMM & (1U << home))) idx = home;
+ }
+
+ if (idx == kRegIndexInvalid)
+ {
+ for (i = 0, mask = (1 << i); i < kX86RegNumXmm; i++, mask <<= 1)
+ {
+ if (!(_x86State.usedXMM & mask))
+ {
+ // Convenience to alloc non-preserved first or non-preserved last.
+ if (nonPreservedFirst)
+ {
+ if (idx != kRegIndexInvalid && (preservedXMM & mask)) continue;
+ idx = i;
+ // If current register is preserved, we should try to find different
+ // one that is not. This can save one push / pop in prolog / epilog.
+ if (!(preservedXMM & mask)) break;
+ }
+ else
+ {
+ if (idx != kRegIndexInvalid && !(preservedXMM & mask)) continue;
+ idx = i;
+ // The opposite.
+ if (preservedXMM & mask) break;
+ }
+ }
+ }
+ }
+
+ // --------------------------------------------------------------------------
+ // [Spill]
+ // --------------------------------------------------------------------------
+
+ // If register is still not found, spill other variable.
+ if (idx == kRegIndexInvalid)
+ {
+ if (!spillCandidate)
+ spillCandidate = _getSpillCandidateXMM();
+
+ // Spill candidate not found?
+ if (!spillCandidate)
+ {
+ _compiler->setError(kErrorNoRegisters);
+ return;
+ }
+
+L_Spill:
+
+ // Prevented variables can't be spilled. _getSpillCandidate() never returns
+ // prevented variables, but when jumping to L_spill it can happen.
+ if (spillCandidate->workOffset == _currentOffset)
+ {
+ _compiler->setError(kErrorOverlappedRegisters);
+ return;
+ }
+
+ idx = spillCandidate->regIndex;
+ spillXmmVar(spillCandidate);
+ }
+
+ // --------------------------------------------------------------------------
+ // [Alloc]
+ // --------------------------------------------------------------------------
+
+ if (var->state == kVarStateMem && (vflags & kVarAllocRead))
+ {
+ emitLoadVar(var, idx);
+ }
+
+ // Update X86CompilerVar.
+ var->state = kVarStateReg;
+ var->regIndex = idx;
+ var->homeRegisterIndex = idx;
+
+ // Update CompilerState.
+ _allocatedVariable(var);
+}
+
+void X86CompilerContext::saveXmmVar(X86CompilerVar* var)
+{
+ // Can't save variable that isn't allocated.
+ ASMJIT_ASSERT(var->state == kVarStateReg);
+ ASMJIT_ASSERT(var->regIndex != kRegIndexInvalid);
+
+ uint32_t idx = var->regIndex;
+ emitSaveVar(var, idx);
+
+ // Update X86CompilerVar.
+ var->changed = false;
+}
+
+void X86CompilerContext::spillXmmVar(X86CompilerVar* var)
+{
+ // Can't spill variable that isn't allocated.
+ ASMJIT_ASSERT(var->state == kVarStateReg);
+ ASMJIT_ASSERT(var->regIndex != kRegIndexInvalid);
+
+ uint32_t idx = var->regIndex;
+
+ if (var->changed) emitSaveVar(var, idx);
+
+ // Update CompilerVar.
+ var->regIndex = kRegIndexInvalid;
+ var->state = kVarStateMem;
+ var->changed = false;
+
+ // Update CompilerState.
+ _x86State.xmm[idx] = nullptr;
+ _freedXmmRegister(idx);
+}
+
+void X86CompilerContext::emitLoadVar(X86CompilerVar* var, uint32_t regIndex)
+{
+ X86Compiler* x86Compiler = getCompiler();
+ Mem m = _getVarMem(var);
+
+ switch (var->getType())
+ {
+ case kX86VarTypeGpd:
+ x86Compiler->emit(kX86InstMov, gpd(regIndex), m);
+ if (_emitComments) goto _AddComment;
+ break;
+#if defined(ASMJIT_X64)
+ case kX86VarTypeGpq:
+ x86Compiler->emit(kX86InstMov, gpq(regIndex), m);
+ if (_emitComments) goto _AddComment;
+ break;
+#endif // ASMJIT_X64
+
+ case kX86VarTypeX87:
+ case kX86VarTypeX87SS:
+ case kX86VarTypeX87SD:
+ // TODO: X87 Support.
+ break;
+
+ case kX86VarTypeMm:
+ x86Compiler->emit(kX86InstMovQ, mm(regIndex), m);
+ if (_emitComments) goto _AddComment;
+ break;
+
+ case kX86VarTypeXmm:
+ x86Compiler->emit(kX86InstMovDQA, xmm(regIndex), m);
+ if (_emitComments) goto _AddComment;
+ break;
+ case kX86VarTypeXmmSS:
+ x86Compiler->emit(kX86InstMovSS, xmm(regIndex), m);
+ if (_emitComments) goto _AddComment;
+ break;
+ case kX86VarTypeXmmSD:
+ x86Compiler->emit(kX86InstMovSD, xmm(regIndex), m);
+ if (_emitComments) goto _AddComment;
+ break;
+ case kX86VarTypeXmmPS:
+ x86Compiler->emit(kX86InstMovAPS, xmm(regIndex), m);
+ if (_emitComments) goto _AddComment;
+ break;
+ case kX86VarTypeXmmPD:
+ x86Compiler->emit(kX86InstMovAPD, xmm(regIndex), m);
+ if (_emitComments) goto _AddComment;
+ break;
+ }
+ return;
+
+_AddComment:
+ x86Compiler->getCurrentItem()->formatComment("Alloc %s", var->getName());
+}
+
+void X86CompilerContext::emitSaveVar(X86CompilerVar* var, uint32_t regIndex)
+{
+ // Caller must ensure that variable is allocated.
+ ASMJIT_ASSERT(regIndex != kRegIndexInvalid);
+
+ X86Compiler* x86Compiler = getCompiler();
+ Mem m = _getVarMem(var);
+
+ switch (var->getType())
+ {
+ case kX86VarTypeGpd:
+ x86Compiler->emit(kX86InstMov, m, gpd(regIndex));
+ if (_emitComments) goto _AddComment;
+ break;
+#if defined(ASMJIT_X64)
+ case kX86VarTypeGpq:
+ x86Compiler->emit(kX86InstMov, m, gpq(regIndex));
+ if (_emitComments) goto _AddComment;
+ break;
+#endif // ASMJIT_X64
+
+ case kX86VarTypeX87:
+ case kX86VarTypeX87SS:
+ case kX86VarTypeX87SD:
+ // TODO: X87 Support.
+ break;
+
+ case kX86VarTypeMm:
+ x86Compiler->emit(kX86InstMovQ, m, mm(regIndex));
+ if (_emitComments) goto _AddComment;
+ break;
+
+ case kX86VarTypeXmm:
+ x86Compiler->emit(kX86InstMovDQA, m, xmm(regIndex));
+ if (_emitComments) goto _AddComment;
+ break;
+ case kX86VarTypeXmmSS:
+ x86Compiler->emit(kX86InstMovSS, m, xmm(regIndex));
+ if (_emitComments) goto _AddComment;
+ break;
+ case kX86VarTypeXmmSD:
+ x86Compiler->emit(kX86InstMovSD, m, xmm(regIndex));
+ if (_emitComments) goto _AddComment;
+ break;
+ case kX86VarTypeXmmPS:
+ x86Compiler->emit(kX86InstMovAPS, m, xmm(regIndex));
+ if (_emitComments) goto _AddComment;
+ break;
+ case kX86VarTypeXmmPD:
+ x86Compiler->emit(kX86InstMovAPD, m, xmm(regIndex));
+ if (_emitComments) goto _AddComment;
+ break;
+ }
+ return;
+
+_AddComment:
+ x86Compiler->getCurrentItem()->formatComment("Spill %s", var->getName());
+}
+
+void X86CompilerContext::emitMoveVar(X86CompilerVar* var, uint32_t regIndex, uint32_t vflags)
+{
+ // Caller must ensure that the given variable is allocated.
+ ASMJIT_ASSERT(var->regIndex != kRegIndexInvalid);
+
+ X86Compiler* x86Compiler = getCompiler();
+ if (!(vflags & kVarAllocRead)) return;
+
+ switch (var->getType())
+ {
+ case kX86VarTypeGpd:
+ x86Compiler->emit(kX86InstMov, gpd(regIndex), gpd(var->regIndex));
+ break;
+#if defined(ASMJIT_X64)
+ case kX86VarTypeGpq:
+ x86Compiler->emit(kX86InstMov, gpq(regIndex), gpq(var->regIndex));
+ break;
+#endif // ASMJIT_X64
+
+ case kX86VarTypeX87:
+ case kX86VarTypeX87SS:
+ case kX86VarTypeX87SD:
+ // TODO: X87 Support.
+ break;
+
+ case kX86VarTypeMm:
+ x86Compiler->emit(kX86InstMovQ, mm(regIndex), mm(var->regIndex));
+ break;
+
+ case kX86VarTypeXmm:
+ x86Compiler->emit(kX86InstMovDQA, xmm(regIndex), xmm(var->regIndex));
+ break;
+ case kX86VarTypeXmmSS:
+ x86Compiler->emit(kX86InstMovSS, xmm(regIndex), xmm(var->regIndex));
+ break;
+ case kX86VarTypeXmmSD:
+ x86Compiler->emit(kX86InstMovSD, xmm(regIndex), xmm(var->regIndex));
+ break;
+ case kX86VarTypeXmmPS:
+ x86Compiler->emit(kX86InstMovAPS, xmm(regIndex), xmm(var->regIndex));
+ break;
+ case kX86VarTypeXmmPD:
+ x86Compiler->emit(kX86InstMovAPD, xmm(regIndex), xmm(var->regIndex));
+ break;
+ }
+}
+
+void X86CompilerContext::emitExchangeVar(X86CompilerVar* var, uint32_t regIndex, uint32_t vflags, X86CompilerVar* other)
+{
+ // Caller must ensure that the given variable is allocated.
+ ASMJIT_ASSERT(var->regIndex != kRegIndexInvalid);
+
+ X86Compiler* x86Compiler = getCompiler();
+
+ // If other is not valid then we can just emit MOV (or other similar instruction).
+ if (!other)
+ {
+ emitMoveVar(var, regIndex, vflags);
+ return;
+ }
+
+ // If we need to alloc for write-only operation then we can move other
+ // variable away instead of exchanging them.
+ if (!(vflags & kVarAllocRead))
+ {
+ emitMoveVar(other, var->regIndex, kVarAllocRead);
+ return;
+ }
+
+ switch (var->getType())
+ {
+ case kX86VarTypeGpd:
+ x86Compiler->emit(kX86InstXchg, gpd(regIndex), gpd(var->regIndex));
+ break;
+#if defined(ASMJIT_X64)
+ case kX86VarTypeGpq:
+ x86Compiler->emit(kX86InstXchg, gpq(regIndex), gpq(var->regIndex));
+ break;
+#endif // ASMJIT_X64
+
+ case kX86VarTypeX87:
+ case kX86VarTypeX87SS:
+ case kX86VarTypeX87SD:
+ // TODO: X87 Support.
+ break;
+
+ // NOTE: MM and XMM registers shoudln't be exchanged using this way, it's
+ // correct, but instead of using one instruction we need three.
+
+ case kX86VarTypeMm:
+ {
+ MmReg a = mm(regIndex);
+ MmReg b = mm(var->regIndex);
+
+ x86Compiler->emit(kX86InstPXor, a, b);
+ x86Compiler->emit(kX86InstPXor, b, a);
+ x86Compiler->emit(kX86InstPXor, a, b);
+ break;
+ }
+
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ {
+ XmmReg a = xmm(regIndex);
+ XmmReg b = xmm(var->regIndex);
+
+ x86Compiler->emit(kX86InstXorPS, a, b);
+ x86Compiler->emit(kX86InstXorPS, b, a);
+ x86Compiler->emit(kX86InstXorPS, a, b);
+ break;
+ }
+
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ {
+ XmmReg a = xmm(regIndex);
+ XmmReg b = xmm(var->regIndex);
+
+ x86Compiler->emit(kX86InstXorPD, a, b);
+ x86Compiler->emit(kX86InstXorPD, b, a);
+ x86Compiler->emit(kX86InstXorPD, a, b);
+ break;
+ }
+
+ case kX86VarTypeXmm:
+ {
+ XmmReg a = xmm(regIndex);
+ XmmReg b = xmm(var->regIndex);
+
+ x86Compiler->emit(kX86InstPXor, a, b);
+ x86Compiler->emit(kX86InstPXor, b, a);
+ x86Compiler->emit(kX86InstPXor, a, b);
+ break;
+ }
+ }
+}
+
+void X86CompilerContext::_postAlloc(X86CompilerVar* var, uint32_t vflags)
+{
+ if (vflags & kVarAllocWrite)
+ var->changed = true;
+}
+
+void X86CompilerContext::_markMemoryUsed(X86CompilerVar* var)
+{
+ if (var->homeMemoryData) return;
+
+ VarMemBlock* mem = _allocMemBlock(var->getSize());
+ if (!mem) return;
+
+ var->homeMemoryData = mem;
+}
+
+Mem X86CompilerContext::_getVarMem(X86CompilerVar* var)
+{
+ Mem m;
+ m._mem.id = var->getId();
+
+ if (!var->isMemArgument())
+ m._mem.displacement = _adjustESP;
+
+ _markMemoryUsed(var);
+ return m;
+}
+
+static int32_t getSpillScore(X86CompilerVar* var, uint32_t currentOffset)
+{
+ int32_t score = 0;
+
+ ASMJIT_ASSERT(!!var->lastItem);
+ uint32_t lastOffset = var->lastItem->getOffset();
+
+ if (lastOffset >= currentOffset)
+ score += (int32_t)(lastOffset - currentOffset);
+
+ // Each write access decreases probability of spill.
+ score -= static_cast<int32_t>(var->regWriteCount) + static_cast<int32_t>(var->regRwCount);
+ // Each read-only access increases probability of spill.
+ score += static_cast<int32_t>(var->regReadCount);
+
+ // Each memory access increases probability of spill.
+ score += static_cast<int32_t>(var->memWriteCount) + static_cast<int32_t>(var->memRwCount);
+ score += static_cast<int32_t>(var->memReadCount);
+
+ return score;
+}
+
+X86CompilerVar* X86CompilerContext::_getSpillCandidateGP()
+{
+ return _getSpillCandidateGeneric(_x86State.gp, kX86RegNumGp);
+}
+
+X86CompilerVar* X86CompilerContext::_getSpillCandidateMM()
+{
+ return _getSpillCandidateGeneric(_x86State.mm, kX86RegNumMm);
+}
+
+X86CompilerVar* X86CompilerContext::_getSpillCandidateXMM()
+{
+ return _getSpillCandidateGeneric(_x86State.xmm, kX86RegNumXmm);
+}
+
+X86CompilerVar* X86CompilerContext::_getSpillCandidateGeneric(X86CompilerVar** varArray, uint32_t count)
+{
+ uint32_t i;
+
+ X86CompilerVar* candidate = nullptr;
+ uint32_t candidatePriority = 0;
+ int32_t candidateScore = 0;
+
+ uint32_t currentOffset = _compiler->getCurrentItem()->getOffset();
+
+ for (i = 0; i < count; i++)
+ {
+ // Get variable.
+ X86CompilerVar* cv = varArray[i];
+
+ // Never spill variables needed for next instruction.
+ if (!cv || cv->workOffset == _currentOffset) continue;
+
+ uint32_t variablePriority = cv->getPriority();
+ int32_t variableScore = getSpillScore(cv, currentOffset);
+
+ if (!candidate ||
+ (variablePriority > candidatePriority) ||
+ (variablePriority == candidatePriority && variableScore > candidateScore))
+ {
+ candidate = cv;
+ candidatePriority = variablePriority;
+ candidateScore = variableScore;
+ }
+ }
+
+ return candidate;
+}
+
+void X86CompilerContext::_addActive(X86CompilerVar* var)
+{
+ // Never call with variable that is already in active list.
+ ASMJIT_ASSERT(!var->nextActive);
+ ASMJIT_ASSERT(!var->prevActive);
+
+ if (!_active)
+ {
+ var->nextActive = var;
+ var->prevActive = var;
+
+ _active = var;
+ }
+ else
+ {
+ X86CompilerVar* vlast = static_cast<X86CompilerVar*>(_active)->prevActive;
+
+ vlast->nextActive = var;
+ static_cast<X86CompilerVar*>(_active)->prevActive = var;
+
+ var->nextActive = static_cast<X86CompilerVar*>(_active);
+ var->prevActive = vlast;
+ }
+}
+
+void X86CompilerContext::_freeActive(X86CompilerVar* var)
+{
+ X86CompilerVar* next = var->nextActive;
+ X86CompilerVar* prev = var->prevActive;
+
+ if (prev == next)
+ {
+ _active = nullptr;
+ }
+ else
+ {
+ if (_active == var)
+ _active = next;
+
+ prev->nextActive = next;
+ next->prevActive = prev;
+ }
+
+ var->nextActive = nullptr;
+ var->prevActive = nullptr;
+}
+
+void X86CompilerContext::_freeAllActive()
+{
+ if (!_active)
+ return;
+
+ X86CompilerVar* cur = static_cast<X86CompilerVar*>(_active);
+ for (;;)
+ {
+ X86CompilerVar* next = cur->nextActive;
+
+ cur->nextActive = nullptr;
+ cur->prevActive = nullptr;
+
+ if (next == _active)
+ break;
+ }
+
+ _active = nullptr;
+}
+
+void X86CompilerContext::_allocatedVariable(X86CompilerVar* var)
+{
+ uint32_t idx = var->regIndex;
+
+ switch (var->getType())
+ {
+ case kX86VarTypeGpd:
+ case kX86VarTypeGpq:
+ _x86State.gp[idx] = var;
+ _allocatedGpRegister(idx);
+ break;
+
+ case kX86VarTypeMm:
+ _x86State.mm[idx] = var;
+ _allocatedMmRegister(idx);
+ break;
+
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ _x86State.xmm[idx] = var;
+ _allocatedXmmRegister(idx);
+ break;
+
+ default:
+ ASMJIT_ASSERT(0);
+ break;
+ }
+}
+
+void X86CompilerContext::translateOperands(Operand* operands, uint32_t count)
+{
+ X86Compiler* x86Compiler = getCompiler();
+ uint32_t i;
+
+ // Translate variables to registers.
+ for (i = 0; i < count; i++)
+ {
+ Operand& o = operands[i];
+
+ if (o.isVar())
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(o.getId());
+ ASMJIT_ASSERT(!!cv);
+
+ o._reg.op = kOperandReg;
+ o._reg.code |= cv->regIndex;
+ }
+ else if (o.isMem())
+ {
+ if ((o.getId() & kOperandIdTypeMask) == kOperandIdTypeVar)
+ {
+ // Memory access. We just increment here actual displacement.
+ X86CompilerVar* cv = x86Compiler->_getVar(o.getId());
+ ASMJIT_ASSERT(!!cv);
+
+ o._mem.displacement += cv->isMemArgument()
+ ? _argumentsActualDisp
+ : _variablesActualDisp;
+ // NOTE: This is not enough, variable position will be patched later
+ // by X86CompilerContext::_patchMemoryOperands().
+ }
+ else if ((o._mem.base & kOperandIdTypeMask) == kOperandIdTypeVar)
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(o._mem.base);
+ ASMJIT_ASSERT(!!cv);
+
+ o._mem.base = cv->regIndex;
+ }
+
+ if ((o._mem.index & kOperandIdTypeMask) == kOperandIdTypeVar)
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(o._mem.index);
+ ASMJIT_ASSERT(!!cv);
+
+ o._mem.index = cv->regIndex;
+ }
+ }
+ }
+}
+
+void X86CompilerContext::addBackwardCode(X86CompilerJmpInst* from)
+{
+ _backCode.append(from);
+}
+
+void X86CompilerContext::addForwardJump(X86CompilerJmpInst* inst)
+{
+ ForwardJumpData* j =
+ reinterpret_cast<ForwardJumpData*>(_zoneMemory.alloc(sizeof(ForwardJumpData)));
+ if (!j) { _compiler->setError(kErrorNoHeapMemory); return; }
+
+ j->inst = inst;
+ j->state = _saveState();
+ j->next = _forwardJumps;
+ _forwardJumps = j;
+}
+
+X86CompilerState* X86CompilerContext::_saveState()
+{
+ X86Compiler* x86Compiler = getCompiler();
+
+ // Get count of variables stored in memory.
+ uint32_t memVarsCount = 0;
+ X86CompilerVar* cur = static_cast<X86CompilerVar*>(_active);
+
+ if (cur)
+ {
+ do {
+ if (cur->state == kVarStateMem) memVarsCount++;
+ cur = cur->nextActive;
+ } while (cur != _active);
+ }
+
+ // Alloc X86CompilerState structure (using zone allocator) and copy current
+ // state into it.
+ X86CompilerState* state = x86Compiler->_newState(memVarsCount);
+ memcpy(state, &_x86State, sizeof(X86CompilerState));
+
+ // Clear changed flags.
+ state->changedGP = 0;
+ state->changedMM = 0;
+ state->changedXMM = 0;
+
+ unsigned i;
+ unsigned mask;
+
+ // Save variables stored in REGISTERs and CHANGE flag.
+ for (i = 0, mask = 1; i < kX86RegNumGp; i++, mask <<= 1)
+ {
+ if (state->gp[i] && state->gp[i]->changed)
+ state->changedGP |= mask;
+ }
+
+ for (i = 0, mask = 1; i < kX86RegNumMm; i++, mask <<= 1)
+ {
+ if (state->mm[i] && state->mm[i]->changed)
+ state->changedMM |= mask;
+ }
+
+ for (i = 0, mask = 1; i < kX86RegNumXmm; i++, mask <<= 1)
+ {
+ if (state->xmm[i] && state->xmm[i]->changed)
+ state->changedXMM |= mask;
+ }
+
+ // Save variables stored in MEMORY.
+ state->memVarsCount = memVarsCount;
+ memVarsCount = 0;
+
+ cur = static_cast<X86CompilerVar*>(_active);
+ if (cur)
+ {
+ do {
+ if (cur->state == kVarStateMem) state->memVarsData[memVarsCount++] = cur;
+ cur = cur->nextActive;
+ } while (cur != _active);
+ }
+
+ // Finished.
+ return state;
+}
+
+void X86CompilerContext::_assignState(X86CompilerState* state)
+{
+ memcpy(&_x86State, state, sizeof(X86CompilerState));
+ _x86State.memVarsCount = 0;
+
+ unsigned i, mask;
+ X86CompilerVar* cv;
+
+ // Unuse all variables first.
+ cv = static_cast<X86CompilerVar*>(_active);
+ if (cv)
+ {
+ do {
+ cv->state = kVarStateUnused;
+ cv = cv->nextActive;
+ } while (cv != _active);
+ }
+
+ // Assign variables stored in memory which are not unused.
+ for (i = 0; i < state->memVarsCount; i++)
+ {
+ state->memVarsData[i]->state = kVarStateMem;
+ }
+
+ // Assign allocated variables.
+ for (i = 0, mask = 1; i < kX86RegNumGp; i++, mask <<= 1)
+ {
+ if ((cv = _x86State.gp[i]))
+ {
+ cv->state = kVarStateReg;
+ cv->regIndex = i;
+ cv->changed = !!(_x86State.changedGP & mask);
+ }
+ }
+
+ for (i = 0, mask = 1; i < kX86RegNumMm; i++, mask <<= 1)
+ {
+ if ((cv = _x86State.mm[i]))
+ {
+ cv->state = kVarStateReg;
+ cv->regIndex = i;
+ cv->changed = !!(_x86State.changedMM & mask);
+ }
+ }
+
+ for (i = 0, mask = 1; i < kX86RegNumXmm; i++, mask <<= 1)
+ {
+ if ((cv = _x86State.xmm[i]))
+ {
+ cv->state = kVarStateReg;
+ cv->regIndex = i;
+ cv->changed = !!(_x86State.changedXMM & mask);
+ }
+ }
+}
+
+void X86CompilerContext::_restoreState(X86CompilerState* state, uint32_t targetOffset)
+{
+ X86CompilerState* fromState = &_x86State;
+ X86CompilerState* toState = state;
+
+ // No change, rare...
+ if (fromState == toState)
+ return;
+
+ unsigned base;
+ unsigned i;
+
+ // --------------------------------------------------------------------------
+ // Set target state to all variables. cv->tInt is target state in this func.
+ // --------------------------------------------------------------------------
+
+ {
+ // UNUSED.
+ X86CompilerVar* cv = static_cast<X86CompilerVar*>(_active);
+ if (cv)
+ {
+ do {
+ cv->tInt = kVarStateUnused;
+ cv = cv->nextActive;
+ } while (cv != _active);
+ }
+
+ // MEMORY.
+ for (i = 0; i < toState->memVarsCount; i++)
+ {
+ toState->memVarsData[i]->tInt = kVarStateMem;
+ }
+
+ // REGISTER.
+ for (i = 0; i < X86CompilerState::kStateRegCount; i++)
+ {
+ if ((cv = toState->regs[i])) cv->tInt = kVarStateReg;
+ }
+ }
+
+ // --------------------------------------------------------------------------
+ // [GP-Registers Switch]
+ // --------------------------------------------------------------------------
+
+ // TODO.
+#if 0
+ for (i = 0; i < kX86RegNumGp; i++)
+ {
+ X86CompilerVar* fromVar = fromState->gp[i];
+ X86CompilerVar* toVar = toState->gp[i];
+
+ if (fromVar != toVar)
+ {
+ if (fromVar)
+ {
+ if (toVar)
+ {
+ if (fromState->gp[to
+ }
+ else
+ {
+ // It is possible that variable that was saved in state currently not
+ // exists (tInt is target scope!).
+ if (fromVar->tInt == kVarStateUnused)
+ {
+ unuseVar(fromVar, kVarStateUnused);
+ }
+ else
+ {
+ spillVar(fromVar);
+ }
+ }
+ }
+ }
+ else if (fromVar)
+ {
+ uint32_t mask = IntUtil::maskFromIndex(i);
+ // Variables are the same, we just need to compare changed flags.
+ if ((fromState->changedGP & mask) && !(toState->changedGP & mask)) saveVar(fromVar);
+ }
+ }
+#endif
+
+ // Spill.
+ for (base = 0, i = 0; i < X86CompilerState::kStateRegCount; i++)
+ {
+ // Change the base offset (from base offset so the register index can be calculated).
+ if (i == X86CompilerState::kStateRegMmBase || i == X86CompilerState::kStateRegXmmBase)
+ base = i;
+
+ uint32_t regIndex = i - base;
+ X86CompilerVar* fromVar = fromState->regs[i];
+ X86CompilerVar* toVar = toState->regs[i];
+
+ if (fromVar != toVar)
+ {
+ // Spill the register.
+ if (fromVar)
+ {
+ // It is possible that variable that was saved in state currently not
+ // exists (tInt is target scope!).
+ if (fromVar->tInt == kVarStateUnused)
+ unuseVar(fromVar, kVarStateUnused);
+ else
+ spillVar(fromVar);
+ }
+ }
+ else if (fromVar)
+ {
+ // Variables are the same, we just need to compare changed flags.
+ uint32_t mask = IntUtil::maskFromIndex(regIndex);
+
+ if ((fromState->changedGP & mask) && !(toState->changedGP & mask))
+ saveVar(fromVar);
+ }
+ }
+
+ // Alloc.
+ for (base = 0, i = 0; i < X86CompilerState::kStateRegCount; i++)
+ {
+ // Change the base offset (from base offset so the register index can be calculated).
+ if (i == X86CompilerState::kStateRegMmBase || i == X86CompilerState::kStateRegXmmBase)
+ base = i;
+
+ X86CompilerVar* fromVar = fromState->regs[i];
+ X86CompilerVar* toVar = toState->regs[i];
+
+ if (fromVar != toVar)
+ {
+ // Alloc register.
+ uint32_t regIndex = i - base;
+
+ if (toVar)
+ allocVar(toVar, IntUtil::maskFromIndex(regIndex), kVarAllocRead);
+ }
+
+ // TODO:
+ //if (toVar)
+ //{
+ // toVar->changed = to->changed;
+ //}
+ }
+
+ // --------------------------------------------------------------------------
+ // Update used masks.
+ // --------------------------------------------------------------------------
+
+ _x86State.usedGP = state->usedGP;
+ _x86State.usedMM = state->usedMM;
+ _x86State.usedXMM = state->usedXMM;
+
+ // --------------------------------------------------------------------------
+ // Update changed masks and cleanup.
+ // --------------------------------------------------------------------------
+
+ {
+ X86CompilerVar* cv = static_cast<X86CompilerVar*>(_active);
+ if (cv)
+ {
+ do {
+ if (cv->tInt != kVarStateReg)
+ {
+ cv->state = (int)cv->tInt;
+ cv->changed = false;
+ }
+
+ cv->tInt = 0;
+ cv = cv->nextActive;
+ } while (cv != _active);
+ }
+ }
+}
+
+VarMemBlock* X86CompilerContext::_allocMemBlock(uint32_t size)
+{
+ ASMJIT_ASSERT(size != 0);
+
+ // First try to find mem blocks.
+ VarMemBlock* mem = _memFree;
+ VarMemBlock* prev = nullptr;
+
+ while (mem)
+ {
+ VarMemBlock* next = mem->nextFree;
+
+ if (mem->size == size)
+ {
+ if (prev)
+ prev->nextFree = next;
+ else
+ _memFree = next;
+
+ mem->nextFree = nullptr;
+ return mem;
+ }
+
+ prev = mem;
+ mem = next;
+ }
+
+ // Never mind, create new.
+ mem = reinterpret_cast<VarMemBlock*>(_zoneMemory.alloc(sizeof(VarMemBlock)));
+ if (!mem)
+ {
+ _compiler->setError(kErrorNoHeapMemory);
+ return nullptr;
+ }
+
+ mem->offset = 0;
+ mem->size = size;
+
+ mem->nextUsed = _memUsed;
+ mem->nextFree = nullptr;
+
+ _memUsed = mem;
+
+ switch (size)
+ {
+ case 16: _mem16BlocksCount++; break;
+ case 8: _mem8BlocksCount++; break;
+ case 4: _mem4BlocksCount++; break;
+ }
+
+ return mem;
+}
+
+void X86CompilerContext::_freeMemBlock(VarMemBlock* mem)
+{
+ // Add mem to free blocks.
+ mem->nextFree = _memFree;
+ _memFree = mem;
+}
+
+void X86CompilerContext::_allocMemoryOperands()
+{
+ VarMemBlock* mem;
+
+ // Variables are allocated in this order:
+ // 1. 16-byte variables.
+ // 2. 8-byte variables.
+ // 3. 4-byte variables.
+ // 4. All others.
+
+ uint32_t start16 = 0;
+ uint32_t start8 = start16 + _mem16BlocksCount * 16;
+ uint32_t start4 = start8 + _mem8BlocksCount * 8;
+ uint32_t startX = IntUtil::align<uint32_t>(start4 + _mem4BlocksCount * 4, 16);
+
+ for (mem = _memUsed; mem; mem = mem->nextUsed)
+ {
+ uint32_t size = mem->size;
+ uint32_t offset;
+
+ switch (size)
+ {
+ case 16:
+ offset = start16;
+ start16 += 16;
+ break;
+
+ case 8:
+ offset = start8;
+ start8 += 8;
+ break;
+
+ case 4:
+ offset = start4;
+ start4 += 4;
+ break;
+
+ default:
+ // Align to 16 bytes if size is 16 or more.
+ if (size >= 16)
+ {
+ size = IntUtil::align<uint32_t>(size, 16);
+ startX = IntUtil::align<uint32_t>(startX, 16);
+ }
+
+ offset = startX;
+ startX += size;
+ break;
+ }
+
+ mem->offset = (int32_t)offset;
+ _memBytesTotal += size;
+ }
+}
+
+void X86CompilerContext::_patchMemoryOperands(CompilerItem* start, CompilerItem* stop)
+{
+ CompilerItem* cur;
+
+ for (cur = start;; cur = cur->getNext())
+ {
+ if (cur->getType() == kCompilerItemInst)
+ {
+ Mem* mem = reinterpret_cast<X86CompilerInst*>(cur)->_memOp;
+
+ if (mem && (mem->_mem.id & kOperandIdTypeMask) == kOperandIdTypeVar)
+ {
+ X86CompilerVar* cv = getCompiler()->_getVar(mem->_mem.id);
+ ASMJIT_ASSERT(!!cv);
+
+ if (cv->isMemArgument())
+ {
+ mem->_mem.base = _argumentsBaseReg;
+ mem->_mem.displacement += cv->homeMemoryOffset;
+ mem->_mem.displacement += _argumentsBaseOffset;
+ }
+ else
+ {
+ VarMemBlock* mb = reinterpret_cast<VarMemBlock*>(cv->homeMemoryData);
+ ASMJIT_ASSERT(!!mb);
+
+ mem->_mem.base = _variablesBaseReg;
+ mem->_mem.displacement += mb->offset;
+ mem->_mem.displacement += _variablesBaseOffset;
+ }
+ }
+ }
+ if (cur == stop) break;
+ }
+}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86/x86compilercontext.h
@@ -1,1 +1,322 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_X86_X86COMPILERCONTEXT_H
+#define _ASMJIT_X86_X86COMPILERCONTEXT_H
+
+// [Dependencies - AsmJit]
+#include "../core/intutil.h"
+#include "../core/podvector.h"
+
+#include "../x86/x86assembler.h"
+#include "../x86/x86compiler.h"
+#include "../x86/x86compilerfunc.h"
+#include "../x86/x86compileritem.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit {
+
+//! @addtogroup AsmJit_X86
+//! @{
+
+// ============================================================================
+// [AsmJit::X86CompilerContext]
+// ============================================================================
+
+//! @internal
+//!
+//! @brief Compiler context is used by @ref X86Compiler.
+//!
+//! X86Compiler context is used during compilation and normally developer doesn't
+//! need access to it. The context is user per function (it's reset after each
+//! function is generated).
+struct X86CompilerContext : public CompilerContext
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref X86CompilerContext instance.
+ ASMJIT_API X86CompilerContext(X86Compiler* x86Compiler);
+ //! @brief Destroy the @ref X86CompilerContext instance.
+ ASMJIT_API ~X86CompilerContext();
+
+ // --------------------------------------------------------------------------
+ // [Accessor]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get compiler as @ref X86Compiler.
+ X86Compiler* getCompiler() const
+ { return reinterpret_cast<X86Compiler*>(_compiler); }
+
+ //! @brief Get function as @ref X86CompilerFuncDecl.
+ X86CompilerFuncDecl* getFunc() const
+ { return reinterpret_cast<X86CompilerFuncDecl*>(_func); }
+
+ // --------------------------------------------------------------------------
+ // [Clear]
+ // --------------------------------------------------------------------------
+
+ //! @brief Clear context, preparing it for next function generation.
+ ASMJIT_API void _clear();
+
+ // --------------------------------------------------------------------------
+ // [Register Allocator]
+ // --------------------------------------------------------------------------
+
+ //! @brief Allocate variable
+ //!
+ //! Calls @c allocGpVar, @c allocMmVar or @c allocXmmVar methods.
+ ASMJIT_API void allocVar(X86CompilerVar* cv, uint32_t regMask, uint32_t vflags);
+
+ //! @brief Save variable.
+ //!
+ //! Calls @c saveGpVar, @c saveMmVar or @c saveXmmVar methods.
+ ASMJIT_API void saveVar(X86CompilerVar* cv);
+
+ //! @brief Spill variable.
+ //!
+ //! Calls @c spillGpVar, @c spillMmVar or @c spillXmmVar methods.
+ ASMJIT_API void spillVar(X86CompilerVar* cv);
+
+ //! @brief Unuse variable (didn't spill, just forget about it).
+ ASMJIT_API void unuseVar(X86CompilerVar* cv, uint32_t toState);
+
+ //! @brief Helper method that is called for each variable per item.
+ void _unuseVarOnEndOfScope(CompilerItem* item, X86CompilerVar* cv)
+ {
+ if (cv->lastItem == item)
+ unuseVar(cv, kVarStateUnused);
+ }
+ //! @overload
+ void _unuseVarOnEndOfScope(CompilerItem* item, VarAllocRecord* rec)
+ {
+ X86CompilerVar* cv = rec->vdata;
+ if (cv->lastItem == item || (rec->vflags & kVarAllocUnuseAfterUse))
+ unuseVar(cv, kVarStateUnused);
+ }
+ //! @overload
+ void _unuseVarOnEndOfScope(CompilerItem* item, VarCallRecord* rec)
+ {
+ X86CompilerVar* v = rec->vdata;
+ if (v->lastItem == item || (rec->flags & VarCallRecord::kFlagUnuseAfterUse))
+ unuseVar(v, kVarStateUnused);
+ }
+
+ //! @brief Allocate variable (GP).
+ ASMJIT_API void allocGpVar(X86CompilerVar* cv, uint32_t regMask, uint32_t vflags);
+ //! @brief Save variable (GP).
+ ASMJIT_API void saveGpVar(X86CompilerVar* cv);
+ //! @brief Spill variable (GP).
+ ASMJIT_API void spillGpVar(X86CompilerVar* cv);
+
+ //! @brief Allocate variable (MM).
+ ASMJIT_API void allocMmVar(X86CompilerVar* cv, uint32_t regMask, uint32_t vflags);
+ //! @brief Save variable (MM).
+ ASMJIT_API void saveMmVar(X86CompilerVar* cv);
+ //! @brief Spill variable (MM).
+ ASMJIT_API void spillMmVar(X86CompilerVar* cv);
+
+ //! @brief Allocate variable (XMM).
+ ASMJIT_API void allocXmmVar(X86CompilerVar* cv, uint32_t regMask, uint32_t vflags);
+ //! @brief Save variable (XMM).
+ ASMJIT_API void saveXmmVar(X86CompilerVar* cv);
+ //! @brief Spill variable (XMM).
+ ASMJIT_API void spillXmmVar(X86CompilerVar* cv);
+
+ //! @brief Emit load variable instruction(s).
+ ASMJIT_API void emitLoadVar(X86CompilerVar* cv, uint32_t regIndex);
+ //! @brief Emit save variable instruction(s).
+ ASMJIT_API void emitSaveVar(X86CompilerVar* cv, uint32_t regIndex);
+
+ //! @brief Emit move variable instruction(s).
+ ASMJIT_API void emitMoveVar(X86CompilerVar* cv, uint32_t regIndex, uint32_t vflags);
+ //! @brief Emit exchange variable instruction(s).
+ ASMJIT_API void emitExchangeVar(X86CompilerVar* cv, uint32_t regIndex, uint32_t vflags, X86CompilerVar* other);
+
+ //! @brief Called each time a variable is alloceted.
+ ASMJIT_API void _postAlloc(X86CompilerVar* cv, uint32_t vflags);
+ //! @brief Marks variable home memory as used (must be called at least once
+ //! for each variable that uses function local memory - stack).
+ ASMJIT_API void _markMemoryUsed(X86CompilerVar* cv);
+
+ ASMJIT_API Mem _getVarMem(X86CompilerVar* cv);
+
+ ASMJIT_API X86CompilerVar* _getSpillCandidateGP();
+ ASMJIT_API X86CompilerVar* _getSpillCandidateMM();
+ ASMJIT_API X86CompilerVar* _getSpillCandidateXMM();
+ ASMJIT_API X86CompilerVar* _getSpillCandidateGeneric(X86CompilerVar** varArray, uint32_t count);
+
+ bool _isActive(X86CompilerVar* cv)
+ { return !!cv->nextActive; }
+
+ ASMJIT_API void _addActive(X86CompilerVar* cv);
+ ASMJIT_API void _freeActive(X86CompilerVar* cv);
+ ASMJIT_API void _freeAllActive();
+
+ ASMJIT_API void _allocatedVariable(X86CompilerVar* cv);
+
+ void _allocatedGpRegister(uint32_t index)
+ {
+ _x86State.usedGP |= IntUtil::maskFromIndex(index);
+ _modifiedGpRegisters |= IntUtil::maskFromIndex(index);
+ }
+
+ void _allocatedMmRegister(uint32_t index)
+ {
+ _x86State.usedMM |= IntUtil::maskFromIndex(index);
+ _modifiedMmRegisters |= IntUtil::maskFromIndex(index);
+ }
+
+ void _allocatedXmmRegister(uint32_t index)
+ {
+ _x86State.usedXMM |= IntUtil::maskFromIndex(index);
+ _modifiedXmmRegisters |= IntUtil::maskFromIndex(index);
+ }
+
+ void _freedGpRegister(uint32_t index)
+ { _x86State.usedGP &= ~IntUtil::maskFromIndex(index); }
+
+ void _freedMmRegister(uint32_t index)
+ { _x86State.usedMM &= ~IntUtil::maskFromIndex(index); }
+
+ void _freedXmmRegister(uint32_t index)
+ { _x86State.usedXMM &= ~IntUtil::maskFromIndex(index); }
+
+ void _markGpRegisterModified(uint32_t index)
+ { _modifiedGpRegisters |= IntUtil::maskFromIndex(index); }
+
+ void _markMmRegisterModified(uint32_t index)
+ { _modifiedMmRegisters |= IntUtil::maskFromIndex(index); }
+
+ void _markXmmRegisterModified(uint32_t index)
+ { _modifiedXmmRegisters |= IntUtil::maskFromIndex(index); }
+
+ // TODO: Find code which uses this and improve.
+ void _newRegisterHomeIndex(X86CompilerVar* cv, uint32_t idx)
+ {
+ if (cv->homeRegisterIndex == kRegIndexInvalid)
+ cv->homeRegisterIndex = idx;
+ cv->prefRegisterMask |= (1U << idx);
+ }
+
+ // TODO: Find code which uses this and improve.
+ void _newRegisterHomeMask(X86CompilerVar* cv, uint32_t mask)
+ {
+ cv->prefRegisterMask |= mask;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Operand Patcher]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API void translateOperands(Operand* operands, uint32_t count);
+
+ // --------------------------------------------------------------------------
+ // [Backward Code]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API void addBackwardCode(X86CompilerJmpInst* from);
+
+ // --------------------------------------------------------------------------
+ // [Forward Jump]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API void addForwardJump(X86CompilerJmpInst* inst);
+
+ // --------------------------------------------------------------------------
+ // [State]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API X86CompilerState* _saveState();
+ ASMJIT_API void _assignState(X86CompilerState* state);
+ ASMJIT_API void _restoreState(X86CompilerState* state, uint32_t targetOffset = kInvalidValue);
+
+ // --------------------------------------------------------------------------
+ // [Memory Allocator]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API VarMemBlock* _allocMemBlock(uint32_t size);
+ ASMJIT_API void _freeMemBlock(VarMemBlock* mem);
+
+ ASMJIT_API void _allocMemoryOperands();
+ ASMJIT_API void _patchMemoryOperands(CompilerItem* start, CompilerItem* stop);
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief X86 specific compiler state (linked with @ref _state).
+ X86CompilerState _x86State;
+
+ //! @brief Forward jumps (single linked list).
+ ForwardJumpData* _forwardJumps;
+
+ //! @brief Global modified GP registers mask (per function).
+ uint32_t _modifiedGpRegisters;
+ //! @brief Global modified MM registers mask (per function).
+ uint32_t _modifiedMmRegisters;
+ //! @brief Global modified XMM registers mask (per function).
+ uint32_t _modifiedXmmRegisters;
+
+ //! @brief Whether the EBP/RBP register can be used by register allocator.
+ uint32_t _allocableEBP;
+
+ //! @brief ESP adjust constant (changed during PUSH/POP or when using
+ //! stack.
+ int _adjustESP;
+
+ //! @brief Function arguments base pointer (register).
+ uint32_t _argumentsBaseReg;
+ //! @brief Function arguments base offset.
+ int32_t _argumentsBaseOffset;
+ //! @brief Function arguments displacement.
+ int32_t _argumentsActualDisp;
+
+ //! @brief Function variables base pointer (register).
+ uint32_t _variablesBaseReg;
+ //! @brief Function variables base offset.
+ int32_t _variablesBaseOffset;
+ //! @brief Function variables displacement.
+ int32_t _variablesActualDisp;
+
+ //! @brief Used memory blocks (for variables, here is each created mem block
+ //! that can be also in _memFree list).
+ VarMemBlock* _memUsed;
+ //! @brief Free memory blocks (freed, prepared for another allocation).
+ VarMemBlock* _memFree;
+ //! @brief Count of 4-byte memory blocks used by the function.
+ uint32_t _mem4BlocksCount;
+ //! @brief Count of 8-byte memory blocks used by the function.
+ uint32_t _mem8BlocksCount;
+ //! @brief Count of 16-byte memory blocks used by the function.
+ uint32_t _mem16BlocksCount;
+ //! @brief Count of total bytes of stack memory used by the function.
+ uint32_t _memBytesTotal;
+
+ //! @brief List of items which need to be translated. These items are filled
+ //! by @c addBackwardCode().
+ PodVector<X86CompilerJmpInst*> _backCode;
+
+ //! @brief Backward code position (starts at 0).
+ sysuint_t _backPos;
+ //! @brief Whether to emit comments.
+ bool _emitComments;
+};
+
+//! @}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_X86_X86COMPILERCONTEXT_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86/x86compilerfunc.cpp
@@ -1,1 +1,2899 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/intutil.h"
+#include "../core/stringutil.h"
+
+#include "../x86/x86compiler.h"
+#include "../x86/x86compilercontext.h"
+#include "../x86/x86compilerfunc.h"
+#include "../x86/x86compileritem.h"
+#include "../x86/x86cpuinfo.h"
+#include "../x86/x86util.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit {
+
+// ============================================================================
+// [AsmJit::X86Assembler - Logging]
+// ============================================================================
+
+// Defined in AsmJit/X86/X86Assembler.cpp.
+char* X86Assembler_dumpRegister(char* buf, uint32_t type, uint32_t index);
+char* X86Assembler_dumpOperand(char* buf, const Operand* op, uint32_t memRegType, uint32_t loggerFlags);
+
+// ============================================================================
+// [AsmJit::X86CompilerFuncDecl - Construction / Destructioin]
+// ============================================================================
+
+X86CompilerFuncDecl::X86CompilerFuncDecl(X86Compiler* x86Compiler) :
+ CompilerFuncDecl(x86Compiler),
+ _gpModifiedAndPreserved(0),
+ _mmModifiedAndPreserved(0),
+ _xmmModifiedAndPreserved(0),
+ _movDqInstCode(kInstNone),
+ _pePushPopStackSize(0),
+ _peMovStackSize(0),
+ _peAdjustStackSize(0),
+ _memStackSize(0),
+ _memStackSize16(0)
+{
+ _decl = &_x86Decl;
+
+ // Just clear to safe defaults.
+ _funcHints |= IntUtil::maskFromIndex(kX86FuncHintPushPop);
+
+ // Stack is always aligned to 16-bytes when using 64-bit OS.
+ if (CompilerUtil::isStack16ByteAligned())
+ _funcHints |= IntUtil::maskFromIndex(kX86FuncHintAssume16ByteAlignment);
+
+ _entryLabel = x86Compiler->newLabel();
+ _exitLabel = x86Compiler->newLabel();
+
+ _entryTarget = x86Compiler->_getTarget(_entryLabel.getId());
+ _exitTarget = x86Compiler->_getTarget(_exitLabel.getId());
+
+ _end = Compiler_newItem<X86CompilerFuncEnd>(x86Compiler, this);
+}
+
+X86CompilerFuncDecl::~X86CompilerFuncDecl()
+{
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerFuncDecl - Interface]
+// ============================================================================
+
+void X86CompilerFuncDecl::prepare(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+ _offset = x86Context._currentOffset++;
+
+ _prepareVariables(this);
+}
+
+CompilerItem* X86CompilerFuncDecl::translate(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+
+ _allocVariables(x86Context);
+ return translated();
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerFuncDecl - Misc]
+// ============================================================================
+
+int X86CompilerFuncDecl::getMaxSize() const
+{
+ // NOP.
+ return 0;
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerFuncDecl - Prototype]
+// ============================================================================
+
+void X86CompilerFuncDecl::setPrototype(uint32_t convention, uint32_t returnType, const uint32_t* arguments, uint32_t argumentsCount)
+{
+ _x86Decl.setPrototype(convention, returnType, arguments, argumentsCount);
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerFuncDecl - Helpers]
+// ============================================================================
+
+void X86CompilerFuncDecl::_createVariables()
+{
+ X86Compiler* x86Compiler = getCompiler();
+
+ uint32_t i, count = _x86Decl.getArgumentsCount();
+ if (!count) return;
+
+ _vars = reinterpret_cast<CompilerVar**>(x86Compiler->getZoneMemory().alloc(count * sizeof(void*)));
+ if (!_vars)
+ {
+ x86Compiler->setError(kErrorNoHeapMemory);
+ return;
+ }
+
+ char argNameStorage[64];
+ char* argName = nullptr;
+
+ bool debug = !!x86Compiler->getLogger();
+ if (debug) argName = argNameStorage;
+
+ for (i = 0; i < count; i++)
+ {
+ FuncArg& arg = _x86Decl.getArgument(i);
+
+ if (debug)
+ snprintf(argName, ASMJIT_ARRAY_SIZE(argNameStorage), "arg_%u", i);
+
+ uint32_t size = X86Util::getVarSizeFromVarType(arg.getVarType());
+ X86CompilerVar* cv = x86Compiler->_newVar(argName, arg.getVarType(), size);
+
+ if (arg.getRegIndex() != kRegIndexInvalid)
+ {
+ cv->_isRegArgument = true;
+ cv->regIndex = arg.getRegIndex();
+ }
+
+ if (arg.getStackOffset() != kFuncStackInvalid)
+ {
+ cv->_isMemArgument = true;
+ cv->homeMemoryOffset = arg.getStackOffset();
+ }
+
+ _vars[i] = cv;
+ }
+}
+
+void X86CompilerFuncDecl::_prepareVariables(CompilerItem* first)
+{
+ uint32_t count = _x86Decl.getArgumentsCount();
+ if (!count) return;
+
+ for (uint32_t i = 0; i < count; i++)
+ {
+ X86CompilerVar* cv = getVar(i);
+
+ // This is where variable scope starts.
+ cv->firstItem = first;
+ // If this will not be changed then it will be deallocated immediately.
+ cv->lastItem = first;
+ }
+}
+
+void X86CompilerFuncDecl::_allocVariables(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+ uint32_t count = getDecl()->getArgumentsCount();
+
+ if (!count)
+ return;
+
+ for (uint32_t i = 0; i < count; i++)
+ {
+ X86CompilerVar* cv = getVar(i);
+
+ if (cv->firstItem || cv->isArgument())
+ {
+ // Variable is used.
+ if (cv->regIndex != kRegIndexInvalid)
+ {
+ cv->state = kVarStateReg;
+ // If variable is in register -> mark it as changed so it will not be
+ // lost by first spill.
+ cv->changed = true;
+ x86Context._allocatedVariable(cv);
+ }
+ else if (cv->isMemArgument())
+ {
+ cv->state = kVarStateMem;
+ }
+ }
+ else
+ {
+ // Variable is not used.
+ cv->regIndex = kRegIndexInvalid;
+ }
+ }
+}
+
+void X86CompilerFuncDecl::_preparePrologEpilog(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+
+ clearFuncFlag(
+ kX86FuncFlagPushPop |
+ kX86FuncFlagEmitEmms |
+ kX86FuncFlagEmitSFence |
+ kX86FuncFlagEmitLFence |
+ kX86FuncFlagAssume16ByteAlignment |
+ kX86FuncFlagPerform16ByteAlignment);
+
+ uint32_t accessibleMemoryBelowStack = 0;
+ if (getDecl()->getConvention() == kX86FuncConvX64U)
+ accessibleMemoryBelowStack = 128;
+
+ if (getHint(kX86FuncHintAssume16ByteAlignment ))
+ setFuncFlag(kX86FuncFlagAssume16ByteAlignment);
+
+ if (getHint(kX86FuncHintPerform16ByteAlignment))
+ setFuncFlag(kX86FuncFlagPerform16ByteAlignment);
+
+ if (getHint(kFuncHintNaked))
+ setFuncFlag(kFuncFlagIsNaked);
+
+ if (isCaller() && (x86Context._memBytesTotal > 0 || isAssumed16ByteAlignment()))
+ setFuncFlag(kX86FuncFlagIsEspAdjusted);
+
+ if (x86Context._memBytesTotal > accessibleMemoryBelowStack)
+ setFuncFlag(kX86FuncFlagIsEspAdjusted);
+
+ if (getHint(kX86FuncHintPushPop))
+ setFuncFlag(kX86FuncFlagPushPop);
+
+ if (getHint(kX86FuncHintEmms))
+ setFuncFlag(kX86FuncFlagEmitEmms);
+
+ if (getHint(kX86FuncHintSFence))
+ setFuncFlag(kX86FuncFlagEmitSFence);
+
+ if (getHint(kX86FuncHintLFence))
+ setFuncFlag(kX86FuncFlagEmitLFence);
+
+ // Updated to respect comment from issue #47, align also when using MMX code.
+ if (!isAssumed16ByteAlignment() && !isNaked() && (x86Context._mem16BlocksCount + (x86Context._mem8BlocksCount > 0)))
+ {
+ // Have to align stack to 16-bytes.
+ setFuncFlag(kX86FuncFlagIsEspAdjusted | kX86FuncFlagPerform16ByteAlignment);
+ }
+
+ _gpModifiedAndPreserved = x86Context._modifiedGpRegisters & _x86Decl.getGpPreservedMask() & (~IntUtil::maskFromIndex(kX86RegIndexEsp));
+ _mmModifiedAndPreserved = x86Context._modifiedMmRegisters & _x86Decl.getMmPreservedMask();
+ _xmmModifiedAndPreserved = x86Context._modifiedXmmRegisters & _x86Decl.getXmmPreservedMask();
+ _movDqInstCode = (isAssumed16ByteAlignment() | isPerformed16ByteAlignment()) ? kX86InstMovDQA : kX86InstMovDQU;
+
+ // Prolog & Epilog stack size.
+ {
+ int32_t memGpSize = IntUtil::bitCount(_gpModifiedAndPreserved) * sizeof(intptr_t);
+ int32_t memMmSize = IntUtil::bitCount(_mmModifiedAndPreserved) * 8;
+ int32_t memXmmSize = IntUtil::bitCount(_xmmModifiedAndPreserved) * 16;
+
+ if (hasFuncFlag(kX86FuncFlagPushPop))
+ {
+ _pePushPopStackSize = memGpSize;
+ _peMovStackSize = memXmmSize + IntUtil::align<int32_t>(memMmSize, 16);
+ }
+ else
+ {
+ _pePushPopStackSize = 0;
+ _peMovStackSize = memXmmSize + IntUtil::align<int32_t>(memMmSize + memGpSize, 16);
+ }
+ }
+
+ if (isPerformed16ByteAlignment())
+ {
+ _peAdjustStackSize += IntUtil::delta<int32_t>(_pePushPopStackSize, 16);
+ }
+ else
+ {
+ int32_t v = 16 - sizeof(uintptr_t);
+
+ if (!isNaked())
+ v -= sizeof(uintptr_t);
+
+ v -= _pePushPopStackSize & 15;
+
+ if (v < 0)
+ v += 16;
+
+ _peAdjustStackSize = v;
+
+ //_peAdjustStackSize += IntUtil::delta<int32_t>(_pePushPopStackSize + v, 16);
+ }
+
+ // Memory stack size.
+ _memStackSize = x86Context._memBytesTotal;
+ _memStackSize16 = IntUtil::align(_memStackSize, 16);
+
+ if (isNaked())
+ {
+ x86Context._argumentsBaseReg = kX86RegIndexEsp;
+ x86Context._argumentsBaseOffset = hasFuncFlag(kX86FuncFlagIsEspAdjusted)
+ ? (_funcCallStackSize + _memStackSize16 + _peMovStackSize + _pePushPopStackSize + _peAdjustStackSize)
+ : (_pePushPopStackSize);
+ }
+ else
+ {
+ x86Context._argumentsBaseReg = kX86RegIndexEbp;
+ x86Context._argumentsBaseOffset = sizeof(sysint_t);
+ }
+
+ x86Context._variablesBaseReg = kX86RegIndexEsp;
+ x86Context._variablesBaseOffset = _funcCallStackSize;
+
+ if (!hasFuncFlag(kX86FuncFlagIsEspAdjusted))
+ x86Context._variablesBaseOffset = -_memStackSize16 - _peMovStackSize - _peAdjustStackSize;
+}
+
+void X86CompilerFuncDecl::_dumpFunction(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+ X86Compiler* x86Compiler = getCompiler();
+
+ Logger* logger = x86Compiler->getLogger();
+ ASMJIT_ASSERT(!!logger);
+
+ uint32_t i;
+ char _buf[1024];
+ char* p;
+
+ // Log function prototype.
+ {
+ uint32_t argumentsCount = _x86Decl.getArgumentsCount();
+ bool first = true;
+
+ logger->logString("; Function Prototype:\n");
+ logger->logString(";\n");
+
+ for (i = 0; i < argumentsCount; i++)
+ {
+ const FuncArg& a = _x86Decl.getArgument(i);
+ X86CompilerVar* cv = getVar(i);
+
+ if (first)
+ {
+ logger->logString("; IDX| Type | Sz | Home |\n");
+ logger->logString("; ---+----------+----+----------------+\n");
+ }
+
+ char* memHome = memHome = _buf;
+
+ if (a.hasRegIndex())
+ {
+ Reg regOp(a.getRegIndex() | kX86RegTypeGpz, 0);
+ X86Assembler_dumpOperand(memHome, ®Op, kX86RegTypeGpz, 0)[0] = '\0';
+ }
+ else
+ {
+ Mem memOp;
+ memOp._mem.base = kX86RegIndexEsp;
+ memOp._mem.displacement = a.getStackOffset();
+ X86Assembler_dumpOperand(memHome, &memOp, kX86RegTypeGpz, 0)[0] = '\0';
+ }
+
+ logger->logFormat("; %-3u| %-9s| %-3u| %-15s|\n",
+ // Argument index.
+ i,
+ // Argument type.
+ cv->getType() < kX86VarTypeCount ? x86VarInfo[cv->getType()].getName() : "invalid",
+ // Argument size.
+ cv->getSize(),
+ // Argument memory home.
+ memHome
+ );
+
+ first = false;
+ }
+ logger->logString(";\n");
+ }
+
+ // Log variables.
+ {
+ uint32_t variablesCount = (uint32_t)x86Compiler->_vars.getLength();
+ bool first = true;
+
+ logger->logString("; Variables:\n");
+ logger->logString(";\n");
+
+ for (i = 0; i < variablesCount; i++)
+ {
+ X86CompilerVar* cv = static_cast<X86CompilerVar*>(x86Compiler->_vars[i]);
+
+ // If this variable is not related to this function then skip it.
+ if (cv->funcScope != this)
+ continue;
+
+ // Get some information about variable type.
+ const X86VarInfo& vinfo = x86VarInfo[cv->getType()];
+
+ if (first)
+ {
+ logger->logString("; ID | Type | Sz | Home | Register Access | Memory Access |\n");
+ logger->logString("; ---+----------+----+----------------+-------------------+-------------------+\n");
+ }
+
+ char* memHome = (char*)"[None]";
+ if (cv->homeMemoryData)
+ {
+ VarMemBlock* memBlock = reinterpret_cast<VarMemBlock*>(cv->homeMemoryData);
+ memHome = _buf;
+
+ Mem memOp;
+ if (cv->isMemArgument())
+ {
+ const FuncArg& a = _x86Decl.getArgument(i);
+
+ memOp._mem.base = x86Context._argumentsBaseReg;
+ memOp._mem.displacement += x86Context._argumentsBaseOffset;
+ memOp._mem.displacement += a.getStackOffset();
+ }
+ else
+ {
+ memOp._mem.base = x86Context._variablesBaseReg;
+ memOp._mem.displacement += x86Context._variablesBaseOffset;
+ memOp._mem.displacement += memBlock->offset;
+ }
+ X86Assembler_dumpOperand(memHome, &memOp, kX86RegTypeGpz, 0)[0] = '\0';
+ }
+
+ logger->logFormat("; %-3u| %-9s| %-3u| %-15s| r=%-4uw=%-4ux=%-4u| r=%-4uw=%-4ux=%-4u|\n",
+ // Variable id.
+ (unsigned)(i & kOperandIdValueMask),
+ // Variable type.
+ cv->getType() < kX86VarTypeCount ? vinfo.getName() : "invalid",
+ // Variable size.
+ cv->getSize(),
+ // Variable memory home.
+ memHome,
+ // Register access count.
+ (unsigned int)cv->regReadCount,
+ (unsigned int)cv->regWriteCount,
+ (unsigned int)cv->regRwCount,
+ // Memory access count.
+ (unsigned int)cv->memReadCount,
+ (unsigned int)cv->memWriteCount,
+ (unsigned int)cv->memRwCount
+ );
+ first = false;
+ }
+ logger->logString(";\n");
+ }
+
+ // Log modified registers.
+ {
+ p = _buf;
+
+ uint32_t r;
+ uint32_t modifiedRegisters = 0;
+
+ for (r = 0; r < 3; r++)
+ {
+ bool first = true;
+ uint32_t regs = 0;
+ uint32_t type = 0;
+
+ switch (r)
+ {
+ case 0:
+ regs = x86Context._modifiedGpRegisters;
+ type = kX86RegTypeGpz;
+ p = StringUtil::copy(p, "; GP : ");
+ break;
+ case 1:
+ regs = x86Context._modifiedMmRegisters;
+ type = kX86RegTypeMm;
+ p = StringUtil::copy(p, "; MM : ");
+ break;
+ case 2:
+ regs = x86Context._modifiedXmmRegisters;
+ type = kX86RegTypeXmm;
+ p = StringUtil::copy(p, "; XMM: ");
+ break;
+ default:
+ ASMJIT_ASSERT(0);
+ }
+
+ for (i = 0; i < kX86RegNumBase; i++)
+ {
+ if (regs & IntUtil::maskFromIndex(i))
+ {
+ if (!first) { *p++ = ','; *p++ = ' '; }
+ p = X86Assembler_dumpRegister(p, type, i);
+ first = false;
+ modifiedRegisters++;
+ }
+ }
+ *p++ = '\n';
+ }
+ *p = '\0';
+
+ logger->logFormat("; Modified registers (%u):\n", (unsigned int)modifiedRegisters);
+ logger->logString(_buf);
+ }
+
+ logger->logString("\n");
+}
+
+void X86CompilerFuncDecl::_emitProlog(CompilerContext& cc)
+{
+ X86Compiler* x86Compiler = getCompiler();
+
+ // --------------------------------------------------------------------------
+ // [Init]
+ // --------------------------------------------------------------------------
+
+ uint32_t i, mask;
+ uint32_t preservedGP = _gpModifiedAndPreserved;
+ uint32_t preservedMM = _mmModifiedAndPreserved;
+ uint32_t preservedXMM = _xmmModifiedAndPreserved;
+
+ int32_t stackOffset = _getRequiredStackOffset();
+ int32_t stackPos;
+
+ // --------------------------------------------------------------------------
+ // [Prolog]
+ // --------------------------------------------------------------------------
+
+ if (x86Compiler->getLogger())
+ x86Compiler->comment("Prolog");
+
+ // Emit standard prolog entry code (but don't do it if function is set to be
+ // naked).
+ //
+ // Also see the _prologEpilogStackAdjust variable. If function is naked (so
+ // prolog and epilog will not contain "push ebp" and "mov ebp, esp", we need
+ // to adjust stack by 8 bytes in 64-bit mode (this will give us that stack
+ // will remain aligned to 16 bytes).
+ if (!isNaked())
+ {
+ x86Compiler->emit(kX86InstPush, zbp);
+ x86Compiler->emit(kX86InstMov, zbp, zsp);
+ }
+
+ // Align manually stack-pointer to 16-bytes.
+ if (isPerformed16ByteAlignment())
+ {
+ ASMJIT_ASSERT(!isNaked());
+ x86Compiler->emit(kX86InstAnd, zsp, imm(-16));
+ }
+
+ // --------------------------------------------------------------------------
+ // [Save Gp - Push/Pop]
+ // --------------------------------------------------------------------------
+
+ if (preservedGP && hasFuncFlag(kX86FuncFlagPushPop))
+ {
+ for (i = 0, mask = 1; i < kX86RegNumGp; i++, mask <<= 1)
+ {
+ if (preservedGP & mask)
+ x86Compiler->emit(kX86InstPush, gpz(i));
+ }
+ }
+
+ // --------------------------------------------------------------------------
+ // [Adjust Scack]
+ // --------------------------------------------------------------------------
+
+ if (isEspAdjusted())
+ {
+ stackPos = _memStackSize16 + _funcCallStackSize;
+ if (stackOffset)
+ x86Compiler->emit(kX86InstSub, zsp, imm(stackOffset));
+ }
+ else
+ {
+ stackPos = -(_peMovStackSize + _peAdjustStackSize);
+ //if (_pePushPop) stackPos += IntUtil::bitCount(preservedGP) * sizeof(sysint_t);
+ }
+
+ // --------------------------------------------------------------------------
+ // [Save Xmm - MovDqa/MovDqu]
+ // --------------------------------------------------------------------------
+
+ if (preservedXMM)
+ {
+ for (i = 0, mask = 1; i < kX86RegNumXmm; i++, mask <<= 1)
+ {
+ if (preservedXMM & mask)
+ {
+ x86Compiler->emit(_movDqInstCode, dqword_ptr(zsp, stackPos), xmm(i));
+ stackPos += 16;
+ }
+ }
+ }
+
+ // --------------------------------------------------------------------------
+ // [Save Mm - MovQ]
+ // --------------------------------------------------------------------------
+
+ if (preservedMM)
+ {
+ for (i = 0, mask = 1; i < 8; i++, mask <<= 1)
+ {
+ if (preservedMM & mask)
+ {
+ x86Compiler->emit(kX86InstMovQ, qword_ptr(zsp, stackPos), mm(i));
+ stackPos += 8;
+ }
+ }
+ }
+
+ // --------------------------------------------------------------------------
+ // [Save Gp - Mov]
+ // --------------------------------------------------------------------------
+
+ if (preservedGP && !hasFuncFlag(kX86FuncFlagPushPop))
+ {
+ for (i = 0, mask = 1; i < kX86RegNumGp; i++, mask <<= 1)
+ {
+ if (preservedGP & mask)
+ {
+ x86Compiler->emit(kX86InstMov, sysint_ptr(zsp, stackPos), gpz(i));
+ stackPos += sizeof(sysint_t);
+ }
+ }
+ }
+
+ // --------------------------------------------------------------------------
+ // [...]
+ // --------------------------------------------------------------------------
+
+ if (x86Compiler->getLogger())
+ x86Compiler->comment("Body");
+}
+
+void X86CompilerFuncDecl::_emitEpilog(CompilerContext& cc)
+{
+ X86Compiler* x86Compiler = getCompiler();
+
+ const X86CpuInfo* cpuInfo = X86CpuInfo::getGlobal();
+
+ // --------------------------------------------------------------------------
+ // [Init]
+ // --------------------------------------------------------------------------
+
+ uint32_t i, mask;
+ uint32_t preservedGP = _gpModifiedAndPreserved;
+ uint32_t preservedMM = _mmModifiedAndPreserved;
+ uint32_t preservedXMM = _xmmModifiedAndPreserved;
+
+ int32_t stackOffset = _getRequiredStackOffset();
+ int32_t stackPos;
+
+ if (isEspAdjusted())
+ stackPos = _memStackSize16 + _funcCallStackSize;
+ else
+ stackPos = -(_peMovStackSize + _peAdjustStackSize);
+
+ // --------------------------------------------------------------------------
+ // [Epilog]
+ // --------------------------------------------------------------------------
+
+ if (x86Compiler->getLogger())
+ x86Compiler->comment("Epilog");
+
+ // --------------------------------------------------------------------------
+ // [Restore Xmm - MovDqa/ModDqu]
+ // --------------------------------------------------------------------------
+
+ if (preservedXMM)
+ {
+ for (i = 0, mask = 1; i < kX86RegNumXmm; i++, mask <<= 1)
+ {
+ if (preservedXMM & mask)
+ {
+ x86Compiler->emit(_movDqInstCode, xmm(i), dqword_ptr(zsp, stackPos));
+ stackPos += 16;
+ }
+ }
+ }
+
+ // --------------------------------------------------------------------------
+ // [Restore Mm - MovQ]
+ // --------------------------------------------------------------------------
+
+ if (preservedMM)
+ {
+ for (i = 0, mask = 1; i < 8; i++, mask <<= 1)
+ {
+ if (preservedMM & mask)
+ {
+ x86Compiler->emit(kX86InstMovQ, mm(i), qword_ptr(zsp, stackPos));
+ stackPos += 8;
+ }
+ }
+ }
+
+ // --------------------------------------------------------------------------
+ // [Restore Gp - Mov]
+ // --------------------------------------------------------------------------
+
+ if (preservedGP && !hasFuncFlag(kX86FuncFlagPushPop))
+ {
+ for (i = 0, mask = 1; i < kX86RegNumGp; i++, mask <<= 1)
+ {
+ if (preservedGP & mask)
+ {
+ x86Compiler->emit(kX86InstMov, gpz(i), sysint_ptr(zsp, stackPos));
+ stackPos += sizeof(sysint_t);
+ }
+ }
+ }
+
+ // --------------------------------------------------------------------------
+ // [Adjust Stack]
+ // --------------------------------------------------------------------------
+
+ if (isEspAdjusted() && stackOffset)
+ x86Compiler->emit(kX86InstAdd, zsp, imm(stackOffset));
+
+ // --------------------------------------------------------------------------
+ // [Restore Gp - Push/Pop]
+ // --------------------------------------------------------------------------
+
+ if (preservedGP && hasFuncFlag(kX86FuncFlagPushPop))
+ {
+ for (i = kX86RegNumGp - 1, mask = 1 << i; (int32_t)i >= 0; i--, mask >>= 1)
+ {
+ if (preservedGP & mask)
+ x86Compiler->emit(kX86InstPop, gpz(i));
+ }
+ }
+
+ // --------------------------------------------------------------------------
+ // [Emms]
+ // --------------------------------------------------------------------------
+
+ if (hasFuncFlag(kX86FuncFlagEmitEmms))
+ x86Compiler->emit(kX86InstEmms);
+
+ // --------------------------------------------------------------------------
+ // [MFence/SFence/LFence]
+ // --------------------------------------------------------------------------
+
+ if (hasFuncFlag(kX86FuncFlagEmitSFence) & hasFuncFlag(kX86FuncFlagEmitLFence))
+ x86Compiler->emit(kX86InstMFence);
+ else if (hasFuncFlag(kX86FuncFlagEmitSFence))
+ x86Compiler->emit(kX86InstSFence);
+ else if (hasFuncFlag(kX86FuncFlagEmitLFence))
+ x86Compiler->emit(kX86InstLFence);
+
+ // --------------------------------------------------------------------------
+ // [Epilog]
+ // --------------------------------------------------------------------------
+
+ // Emit standard epilog leave code (if needed).
+ if (!isNaked())
+ {
+ // AMD seems to prefer LEAVE instead of MOV/POP sequence.
+ if (cpuInfo->getVendorId() == kCpuAmd)
+ {
+ x86Compiler->emit(kX86InstLeave);
+ }
+ else
+ {
+ x86Compiler->emit(kX86InstMov, zsp, zbp);
+ x86Compiler->emit(kX86InstPop, zbp);
+ }
+ }
+
+ // Emit return.
+ if (_x86Decl.getCalleePopsStack())
+ x86Compiler->emit(kX86InstRet, imm((int16_t)_x86Decl.getArgumentsStackSize()));
+ else
+ x86Compiler->emit(kX86InstRet);
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerFuncDecl - Function-Call]
+// ============================================================================
+
+void X86CompilerFuncDecl::reserveStackForFunctionCall(int32_t size)
+{
+ size = IntUtil::align<int32_t>(size, 16);
+ if (size > _funcCallStackSize)
+ _funcCallStackSize = size;
+ setFuncFlag(kFuncFlagIsCaller);
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerFuncEnd - Construction / Destruction]
+// ============================================================================
+
+X86CompilerFuncEnd::X86CompilerFuncEnd(X86Compiler* x86Compiler, X86CompilerFuncDecl* func) :
+ CompilerFuncEnd(x86Compiler, func)
+{
+}
+
+X86CompilerFuncEnd::~X86CompilerFuncEnd()
+{
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerFuncEnd - Interface]
+// ============================================================================
+
+void X86CompilerFuncEnd::prepare(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+ _offset = x86Context._currentOffset++;
+}
+
+CompilerItem* X86CompilerFuncEnd::translate(CompilerContext& cc)
+{
+ _isTranslated = true;
+ return nullptr;
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerFuncRet - Construction / Destruction]
+// ============================================================================
+
+X86CompilerFuncRet::X86CompilerFuncRet(X86Compiler* x86Compiler, X86CompilerFuncDecl* func, const Operand* first, const Operand* second) :
+ CompilerFuncRet(x86Compiler, func, first, second)
+{
+/*
+ // TODO:?
+
+ // Check whether the return value is compatible.
+ uint32_t retValType = function->_x86Decl.getReturnType();
+ bool valid = false;
+
+ switch (retValType)
+ {
+ case kX86VarTypeGpd:
+ case kX86VarTypeGpq:
+ if ((_ret[0].isVar() && (reinterpret_cast<const Var&>(_ret[0]).isGpVar())) ||
+ (_ret[0].isImm()))
+ {
+ valid = true;
+ }
+ break;
+
+ case kX86VarTypeX87:
+ case kX86VarTypeX87SS:
+ case kX86VarTypeX87SD:
+ if ((_ret[0].isVar() && (reinterpret_cast<const Var&>(_ret[0]).isX87Var() ||
+ reinterpret_cast<const Var&>(_ret[0]).isXmmVar() )) )
+ {
+ valid = true;
+ }
+ break;
+
+ case kX86VarTypeMm:
+ break;
+
+ case kVarTypeInvalid:
+ if (_ret[0].isNone() &&
+ _ret[1].isNone())
+ {
+ valid = true;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ // Incompatible return value.
+ if (!valid)
+ {
+ c->setError(kErrorIncompatibleReturnType);
+ }
+*/
+}
+
+X86CompilerFuncRet::~X86CompilerFuncRet()
+{
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerFuncRet - Interface]
+// ============================================================================
+
+void X86CompilerFuncRet::prepare(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+ X86Compiler* x86Compiler = x86Context.getCompiler();
+
+ uint32_t retValType = getFunc()->_x86Decl.getReturnType();
+ _offset = x86Context._currentOffset;
+
+ if (retValType != kVarTypeInvalid)
+ {
+ uint32_t i;
+ for (i = 0; i < 2; i++)
+ {
+ Operand& o = _ret[i];
+
+ if (o.isVar())
+ {
+ ASMJIT_ASSERT(o.getId() != kInvalidValue);
+ X86CompilerVar* cv = x86Compiler->_getVar(o.getId());
+ ASMJIT_ASSERT(!!cv);
+
+ // First item (begin of variable scope).
+ if (!cv->firstItem) cv->firstItem = this;
+
+ // Last item (end of variable scope).
+ cv->lastItem = this;
+
+ if (cv->workOffset == _offset) continue;
+ if (!x86Context._isActive(cv)) x86Context._addActive(cv);
+
+ cv->workOffset = _offset;
+ cv->regReadCount++;
+
+ if (X86Util::isVarTypeInt(cv->getType()) && X86Util::isVarTypeInt(retValType))
+ {
+ x86Context._newRegisterHomeIndex(cv, !i ? kX86RegIndexEax : kX86RegIndexEdx);
+ }
+ }
+ }
+ }
+
+ x86Context._currentOffset++;
+}
+
+CompilerItem* X86CompilerFuncRet::translate(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+ X86Compiler* x86Compiler = x86Context.getCompiler();
+
+ // Check whether the return value is compatible.
+ uint32_t retValType = getFunc()->getDecl()->getReturnType();
+ uint32_t i;
+
+ switch (retValType)
+ {
+ case kX86VarTypeGpd:
+ case kX86VarTypeGpq:
+ for (i = 0; i < 2; i++)
+ {
+ uint32_t dstIndex = !i ? kX86RegIndexEax : kX86RegIndexEdx;
+ uint32_t srcIndex;
+
+ if (_ret[i].isVar())
+ {
+ if (reinterpret_cast<const Var&>(_ret[i]).isGpVar())
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(_ret[i].getId());
+ ASMJIT_ASSERT(!!cv);
+
+ srcIndex = cv->regIndex;
+ if (srcIndex == kRegIndexInvalid)
+ x86Compiler->emit(kX86InstMov, gpz(dstIndex), x86Context._getVarMem(cv));
+ else if (dstIndex != srcIndex)
+ x86Compiler->emit(kX86InstMov, gpz(dstIndex), gpz(srcIndex));
+ }
+ }
+ else if (_ret[i].isImm())
+ {
+ x86Compiler->emit(kX86InstMov, gpz(dstIndex), _ret[i]);
+ }
+ }
+ break;
+
+ case kX86VarTypeX87:
+ case kX86VarTypeX87SS:
+ case kX86VarTypeX87SD:
+ // There is case that we need to return two values (Unix-ABI specific):
+ // - FLD #2
+ //- FLD #1
+ i = 2;
+ do {
+ i--;
+ uint32_t srci;
+
+ if (_ret[i].isVar())
+ {
+ if (reinterpret_cast<const Var&>(_ret[i]).isX87Var())
+ {
+ // TODO: X87 Support.
+ }
+ else if (reinterpret_cast<const Var&>(_ret[i]).isXmmVar())
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(_ret[i].getId());
+ ASMJIT_ASSERT(!!cv);
+
+ srci = cv->regIndex;
+ if (srci != kRegIndexInvalid)
+ x86Context.saveXmmVar(cv);
+
+ switch (cv->getType())
+ {
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ x86Compiler->emit(kX86InstFLd, _BaseVarMem(reinterpret_cast<Var&>(_ret[i]), 4));
+ break;
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ x86Compiler->emit(kX86InstFLd, _BaseVarMem(reinterpret_cast<Var&>(_ret[i]), 8));
+ break;
+ }
+ }
+ }
+ } while (i);
+ break;
+
+ case kX86VarTypeMm:
+ for (i = 0; i < 2; i++)
+ {
+ uint32_t dsti = i;
+ uint32_t srci;
+
+ if (_ret[i].isVar())
+ {
+ if (reinterpret_cast<const Var&>(_ret[i]).isGpVar())
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(_ret[i].getId());
+ ASMJIT_ASSERT(!!cv);
+
+ srci = cv->regIndex;
+ uint32_t inst = _ret[i].isRegType(kX86RegTypeGpq) ? kX86InstMovQ : kX86InstMovD;
+
+ if (srci == kRegIndexInvalid)
+ x86Compiler->emit(inst, mm(dsti), x86Context._getVarMem(cv));
+ else
+#if defined(ASMJIT_X86)
+ x86Compiler->emit(inst, mm(dsti), gpd(srci));
+#else
+ x86Compiler->emit(inst, mm(dsti), _ret[i].isRegType(kX86RegTypeGpq) ? gpq(srci) : gpd(srci));
+#endif
+ }
+ else if (reinterpret_cast<const Var&>(_ret[i]).isMmVar())
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(_ret[i].getId());
+ ASMJIT_ASSERT(!!cv);
+
+ srci = cv->regIndex;
+ uint32_t inst = kX86InstMovQ;
+
+ if (srci == kRegIndexInvalid)
+ x86Compiler->emit(inst, mm(dsti), x86Context._getVarMem(cv));
+ else if (dsti != srci)
+ x86Compiler->emit(inst, mm(dsti), mm(srci));
+ }
+ else if (reinterpret_cast<const Var&>(_ret[i]).isXmmVar())
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(_ret[i].getId());
+ ASMJIT_ASSERT(!!cv);
+
+ srci = cv->regIndex;
+ uint32_t inst = kX86InstMovQ;
+ if (reinterpret_cast<const Var&>(_ret[i]).getVarType() == kX86VarTypeXmmSS) inst = kX86InstMovD;
+
+ if (srci == kRegIndexInvalid)
+ x86Compiler->emit(inst, mm(dsti), x86Context._getVarMem(cv));
+ else
+ x86Compiler->emit(inst, mm(dsti), xmm(srci));
+ }
+ }
+ }
+ break;
+
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmPD:
+ for (i = 0; i < 2; i++)
+ {
+ uint32_t dsti = i;
+ uint32_t srci;
+
+ if (_ret[i].isVar())
+ {
+ if (reinterpret_cast<const Var&>(_ret[i]).isGpVar())
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(_ret[i].getId());
+ ASMJIT_ASSERT(!!cv);
+
+ srci = cv->regIndex;
+ uint32_t inst = _ret[i].isRegType(kX86RegTypeGpq) ? kX86InstMovQ : kX86InstMovD;
+
+ if (srci == kRegIndexInvalid)
+ x86Compiler->emit(inst, xmm(dsti), x86Context._getVarMem(cv));
+ else
+#if defined(ASMJIT_X86)
+ x86Compiler->emit(inst, xmm(dsti), gpd(srci));
+#else
+ x86Compiler->emit(inst, xmm(dsti), _ret[i].isRegType(kX86RegTypeGpq) ? gpq(srci) : gpd(srci));
+#endif
+ }
+ else if (reinterpret_cast<const Var&>(_ret[i]).isX87Var())
+ {
+ // TODO: X87 Support.
+ }
+ else if (reinterpret_cast<const Var&>(_ret[i]).isMmVar())
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(_ret[i].getId());
+ ASMJIT_ASSERT(!!cv);
+
+ srci = cv->regIndex;
+ if (srci == kRegIndexInvalid)
+ x86Compiler->emit(kX86InstMovQ, xmm(dsti), x86Context._getVarMem(cv));
+ else
+ x86Compiler->emit(kX86InstMovQ, xmm(dsti), mm(srci));
+ }
+ else if (reinterpret_cast<const Var&>(_ret[i]).isXmmVar())
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(_ret[i].getId());
+ ASMJIT_ASSERT(!!cv);
+
+ srci = cv->regIndex;
+ if (srci == kRegIndexInvalid)
+ x86Compiler->emit(kX86InstMovDQA, xmm(dsti), x86Context._getVarMem(cv));
+ else if (dsti != srci)
+ x86Compiler->emit(kX86InstMovDQA, xmm(dsti), xmm(srci));
+ }
+ }
+ }
+ break;
+
+ case kX86VarTypeXmmSS:
+ for (i = 0; i < 2; i++)
+ {
+ uint32_t dsti = i;
+ uint32_t srci;
+
+ if (_ret[i].isVar())
+ {
+ if (reinterpret_cast<const Var&>(_ret[i]).isX87Var())
+ {
+ // TODO: X87 Support.
+ }
+ else if (reinterpret_cast<const Var&>(_ret[i]).isXmmVar())
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(_ret[i].getId());
+ ASMJIT_ASSERT(!!cv);
+
+ srci = cv->regIndex;
+ switch (cv->getType())
+ {
+ case kX86VarTypeXmm:
+ if (srci == kRegIndexInvalid)
+ x86Compiler->emit(kX86InstMovDQA, xmm(dsti), x86Context._getVarMem(cv));
+ else if (dsti != srci)
+ x86Compiler->emit(kX86InstMovDQA, xmm(dsti), xmm(srci));
+ break;
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ if (srci == kRegIndexInvalid)
+ x86Compiler->emit(kX86InstMovSS, xmm(dsti), x86Context._getVarMem(cv));
+ else
+ x86Compiler->emit(kX86InstMovSS, xmm(dsti), xmm(srci));
+ break;
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ if (srci == kRegIndexInvalid)
+ x86Compiler->emit(kX86InstCvtSD2SS, xmm(dsti), x86Context._getVarMem(cv));
+ else if (dsti != srci)
+ x86Compiler->emit(kX86InstCvtSD2SS, xmm(dsti), xmm(srci));
+ break;
+ }
+ }
+ }
+ }
+ break;
+
+ case kX86VarTypeXmmSD:
+ for (i = 0; i < 2; i++)
+ {
+ uint32_t dsti = i;
+ uint32_t srci;
+
+ if (_ret[i].isVar())
+ {
+ if (reinterpret_cast<const Var&>(_ret[i]).isX87Var())
+ {
+ // TODO: X87 Support.
+ }
+ else if (reinterpret_cast<const Var&>(_ret[i]).isXmmVar())
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(_ret[i].getId());
+ ASMJIT_ASSERT(!!cv);
+
+ srci = cv->regIndex;
+ switch (cv->getType())
+ {
+ case kX86VarTypeXmm:
+ if (srci == kRegIndexInvalid)
+ x86Compiler->emit(kX86InstMovDQA, xmm(dsti), x86Context._getVarMem(cv));
+ else if (dsti != srci)
+ x86Compiler->emit(kX86InstMovDQA, xmm(dsti), xmm(srci));
+ break;
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ if (srci == kRegIndexInvalid)
+ x86Compiler->emit(kX86InstCvtSS2SD, xmm(dsti), x86Context._getVarMem(cv));
+ else
+ x86Compiler->emit(kX86InstCvtSS2SD, xmm(dsti), xmm(srci));
+ break;
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ if (srci == kRegIndexInvalid)
+ x86Compiler->emit(kX86InstMovSD, xmm(dsti), x86Context._getVarMem(cv));
+ else
+ x86Compiler->emit(kX86InstMovSD, xmm(dsti), xmm(srci));
+ break;
+ }
+ }
+ }
+ }
+ break;
+
+ case kInvalidValue:
+ default:
+ break;
+ }
+
+ if (mustEmitJump())
+ {
+ x86Context._isUnreachable = 1;
+ }
+
+ for (i = 0; i < 2; i++)
+ {
+ if (_ret[i].isVar())
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(_ret[i].getId());
+ x86Context._unuseVarOnEndOfScope(this, cv);
+ }
+ }
+
+ return translated();
+}
+
+void X86CompilerFuncRet::emit(Assembler& a)
+{
+ X86Assembler& x86Asm = static_cast<X86Assembler&>(a);
+
+ if (mustEmitJump())
+ x86Asm.jmp(getFunc()->getExitLabel());
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerFuncRet - Misc]
+// ============================================================================
+
+int X86CompilerFuncRet::getMaxSize() const
+{
+ return mustEmitJump() ? 15 : 0;
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerFuncCall - Construction / Destruction]
+// ============================================================================
+
+X86CompilerFuncCall::X86CompilerFuncCall(X86Compiler* x86Compiler, X86CompilerFuncDecl* caller, const Operand* target) :
+ CompilerFuncCall(x86Compiler, caller, target),
+ _gpParams(0),
+ _mmParams(0),
+ _xmmParams(0),
+ _variablesCount(0),
+ _variables(nullptr)
+{
+}
+
+X86CompilerFuncCall::~X86CompilerFuncCall()
+{
+ memset(_argumentToVarRecord, 0, sizeof(VarCallRecord*) * kFuncArgsMax);
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerFuncCall - Interface]
+// ============================================================================
+
+void X86CompilerFuncCall::prepare(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+ X86Compiler* x86Compiler = getCompiler();
+
+ // Prepare is similar to X86CompilerInst::prepare(). We collect unique variables
+ // and update statistics, but we don't use standard alloc/free register calls.
+ //
+ // The calling function is also unique in variable allocator point of view,
+ // because we need to alloc some variables that may be destroyed be the
+ // callee (okay, may not, but this is not guaranteed).
+ _offset = x86Context._currentOffset;
+
+ // Tell EFunction that another function will be called inside. It needs this
+ // information to reserve stack for the call and to mark esp adjustable.
+ getCaller()->reserveStackForFunctionCall(static_cast<int32_t>(_x86Decl.getArgumentsStackSize()));
+
+ uint32_t i;
+ uint32_t argumentsCount = _x86Decl.getArgumentsCount();
+ uint32_t operandsCount = argumentsCount;
+ uint32_t variablesCount = 0;
+
+ // Create registers used as arguments mask.
+ for (i = 0; i < argumentsCount; i++)
+ {
+ const FuncArg& fArg = _x86Decl.getArguments()[i];
+
+ if (fArg.hasRegIndex())
+ {
+ switch (fArg.getVarType())
+ {
+ case kX86VarTypeGpd:
+ case kX86VarTypeGpq:
+ _gpParams |= IntUtil::maskFromIndex(fArg.getRegIndex());
+ break;
+ case kX86VarTypeMm:
+ _mmParams |= IntUtil::maskFromIndex(fArg.getRegIndex());
+ break;
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ _xmmParams |= IntUtil::maskFromIndex(fArg.getRegIndex());
+ break;
+ default:
+ ASMJIT_ASSERT(0);
+ }
+ }
+ else
+ {
+ x86Context.getFunc()->setFuncFlag(kX86FuncFlagIsEspAdjusted);
+ }
+ }
+
+ // Call address.
+ operandsCount++;
+
+ // The first and the second return value.
+ if (!_ret[0].isNone())
+ operandsCount++;
+ if (!_ret[1].isNone())
+ operandsCount++;
+
+#define __GET_VARIABLE(__vardata__) \
+ { \
+ X86CompilerVar* _candidate = __vardata__; \
+ \
+ for (var = cur; ;) \
+ { \
+ if (var == _variables) \
+ { \
+ var = cur++; \
+ var->vdata = _candidate; \
+ break; \
+ } \
+ \
+ var--; \
+ \
+ if (var->vdata == _candidate) \
+ { \
+ break; \
+ } \
+ } \
+ \
+ ASMJIT_ASSERT(!!var); \
+ }
+
+ for (i = 0; i < operandsCount; i++)
+ {
+ Operand& o = (i < argumentsCount)
+ ? (_args[i])
+ : (i == argumentsCount ? _target : _ret[i - argumentsCount - 1]);
+
+ if (o.isVar())
+ {
+ ASMJIT_ASSERT(o.getId() != kInvalidValue);
+ X86CompilerVar* cv = x86Compiler->_getVar(o.getId());
+ ASMJIT_ASSERT(!!cv);
+
+ if (cv->workOffset == _offset) continue;
+ if (!x86Context._isActive(cv)) x86Context._addActive(cv);
+
+ cv->workOffset = _offset;
+ variablesCount++;
+ }
+ else if (o.isMem())
+ {
+ if ((o.getId() & kOperandIdTypeMask) == kOperandIdTypeVar)
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(o.getId());
+ ASMJIT_ASSERT(!!cv);
+
+ x86Context._markMemoryUsed(cv);
+ if (!x86Context._isActive(cv)) x86Context._addActive(cv);
+
+ continue;
+ }
+ else if ((o._mem.base & kOperandIdTypeMask) == kOperandIdTypeVar)
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(o._mem.base);
+ ASMJIT_ASSERT(!!cv);
+
+ if (cv->workOffset == _offset) continue;
+ if (!x86Context._isActive(cv)) x86Context._addActive(cv);
+
+ cv->workOffset = _offset;
+ variablesCount++;
+ }
+
+ if ((o._mem.index & kOperandIdTypeMask) == kOperandIdTypeVar)
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(o._mem.index);
+ ASMJIT_ASSERT(!!cv);
+
+ if (cv->workOffset == _offset) continue;
+ if (!x86Context._isActive(cv)) x86Context._addActive(cv);
+
+ cv->workOffset = _offset;
+ variablesCount++;
+ }
+ }
+ }
+
+ // Traverse all active variables and set their funcCall pointer to this
+ // call. This information can be used to choose between the preserved-first
+ // and preserved-last register allocation.
+ if (x86Context._active)
+ {
+ X86CompilerVar* first = static_cast<X86CompilerVar*>(x86Context._active);
+ X86CompilerVar* active = first;
+ do {
+ if (!active->funcCall)
+ active->funcCall = this;
+ active = active->nextActive;
+ } while (active != first);
+ }
+
+ if (!variablesCount)
+ {
+ x86Context._currentOffset++;
+ return;
+ }
+
+ _variables = reinterpret_cast<VarCallRecord*>(x86Compiler->getZoneMemory().alloc(sizeof(VarCallRecord) * variablesCount));
+ if (!_variables)
+ {
+ x86Compiler->setError(kErrorNoHeapMemory);
+ x86Context._currentOffset++;
+ return;
+ }
+
+ _variablesCount = variablesCount;
+ memset(_variables, 0, sizeof(VarCallRecord) * variablesCount);
+
+ VarCallRecord* cur = _variables;
+ VarCallRecord* var = nullptr;
+
+ for (i = 0; i < operandsCount; i++)
+ {
+ Operand& o = (i < argumentsCount)
+ ? (_args[i])
+ : (i == argumentsCount ? _target : _ret[i - argumentsCount - 1]);
+
+ if (o.isVar())
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(o.getId());
+ ASMJIT_ASSERT(!!cv);
+
+ __GET_VARIABLE(cv)
+ _argumentToVarRecord[i] = var;
+
+ if (i < argumentsCount)
+ {
+ const FuncArg& fArg = _x86Decl.getArgument(i);
+
+ if (fArg.hasRegIndex())
+ {
+ x86Context._newRegisterHomeIndex(cv, fArg.getRegIndex());
+
+ switch (fArg.getVarType())
+ {
+ case kX86VarTypeGpd:
+ case kX86VarTypeGpq:
+ var->flags |= VarCallRecord::kFlagInGp;
+ var->inCount++;
+ break;
+
+ case kX86VarTypeMm:
+ var->flags |= VarCallRecord::kFlagInMm;
+ var->inCount++;
+ break;
+
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ var->flags |= VarCallRecord::kFlagInXmm;
+ var->inCount++;
+ break;
+
+ default:
+ ASMJIT_ASSERT(0);
+ }
+ }
+ else
+ {
+ var->inCount++;
+ }
+
+ cv->regReadCount++;
+ }
+ else if (i == argumentsCount)
+ {
+ uint32_t mask = (~_x86Decl.getGpPreservedMask()) &
+ (~_x86Decl.getGpArgumentsMask()) &
+ (IntUtil::maskUpToIndex(kX86RegNumGp));
+
+ x86Context._newRegisterHomeIndex(cv, IntUtil::findFirstBit(mask));
+ x86Context._newRegisterHomeMask(cv, mask);
+
+ var->flags |= VarCallRecord::kFlagCallReg;
+ cv->regReadCount++;
+ }
+ else
+ {
+ switch (cv->getType())
+ {
+ case kX86VarTypeGpd:
+ case kX86VarTypeGpq:
+ if (i == argumentsCount+1)
+ var->flags |= VarCallRecord::kFlagOutEax;
+ else
+ var->flags |= VarCallRecord::kFlagOutEdx;
+ break;
+
+ case kX86VarTypeX87:
+ case kX86VarTypeX87SS:
+ case kX86VarTypeX87SD:
+#if defined(ASMJIT_X86)
+ if (i == argumentsCount+1)
+ var->flags |= VarCallRecord::kFlagOutSt0;
+ else
+ var->flags |= VarCallRecord::kFlagOutSt1;
+#else
+ if (i == argumentsCount+1)
+ var->flags |= VarCallRecord::kFlagOutXmm0;
+ else
+ var->flags |= VarCallRecord::kFlagOutXmm1;
+#endif
+ break;
+
+ case kX86VarTypeMm:
+ var->flags |= VarCallRecord::kFlagOutMm0;
+ break;
+
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmPD:
+ if (i == argumentsCount+1)
+ var->flags |= VarCallRecord::kFlagOutXmm0;
+ else
+ var->flags |= VarCallRecord::kFlagOutXmm1;
+ break;
+
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmSD:
+#if defined(ASMJIT_X86)
+ if (i == argumentsCount+1)
+ var->flags |= VarCallRecord::kFlagOutSt0;
+ else
+ var->flags |= VarCallRecord::kFlagOutSt1;
+#else
+ if (i == argumentsCount+1)
+ var->flags |= VarCallRecord::kFlagOutXmm0;
+ else
+ var->flags |= VarCallRecord::kFlagOutXmm1;
+#endif
+ break;
+
+ default:
+ ASMJIT_ASSERT(0);
+ }
+
+ cv->regWriteCount++;
+ }
+ }
+ else if (o.isMem())
+ {
+ ASMJIT_ASSERT(i == argumentsCount);
+
+ if ((o.getId() & kOperandIdTypeMask) == kOperandIdTypeVar)
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(o.getId());
+ ASMJIT_ASSERT(!!cv);
+
+ cv->memReadCount++;
+ }
+ else if ((o._mem.base & kOperandIdTypeMask) == kOperandIdTypeVar)
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(reinterpret_cast<Mem&>(o).getBase());
+ ASMJIT_ASSERT(!!cv);
+
+ cv->regReadCount++;
+
+ __GET_VARIABLE(cv)
+ var->flags |= VarCallRecord::kFlagCallReg | VarCallRecord::kFlagCallMem;
+ }
+
+ if ((o._mem.index & kOperandIdTypeMask) == kOperandIdTypeVar)
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(reinterpret_cast<Mem&>(o).getIndex());
+ ASMJIT_ASSERT(!!cv);
+
+ cv->regReadCount++;
+
+ __GET_VARIABLE(cv)
+ var->flags |= VarCallRecord::kFlagCallReg | VarCallRecord::kFlagCallMem;
+ }
+ }
+ }
+
+ // Traverse all variables and update firstItem / lastItem. This
+ // function is called from iterator that scans items using forward
+ // direction so we can use this knowledge to optimize the process.
+ //
+ // Same code is in X86CompilerInst::prepare().
+ for (i = 0; i < _variablesCount; i++)
+ {
+ X86CompilerVar* v = _variables[i].vdata;
+
+ // First item (begin of variable scope).
+ if (!v->firstItem) v->firstItem = this;
+
+ // Last item (end of variable scope).
+ v->lastItem = this;
+ }
+
+ x86Context._currentOffset++;
+
+#undef __GET_VARIABLE
+}
+
+CompilerItem* X86CompilerFuncCall::translate(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+ X86Compiler* x86Compiler = x86Context.getCompiler();
+
+ uint32_t i;
+ uint32_t preserved, mask;
+
+ uint32_t temporaryGpReg;
+ uint32_t temporaryXmmReg;
+
+ uint32_t offset = x86Context._currentOffset;
+
+ // Constants.
+ const FuncArg* targs = _x86Decl.getArguments();
+
+ uint32_t argumentsCount = _x86Decl.getArgumentsCount();
+ uint32_t variablesCount = _variablesCount;
+
+ // Processed arguments kFuncArgsMax.
+ uint8_t processed[kFuncArgsMax] = { 0 };
+
+ x86Compiler->comment("Call");
+
+ // These variables are used by the instruction so we set current offset
+ // to their work offsets -> The getSpillCandidate() method never returns
+ // the variable used by this instruction.
+ for (i = 0; i < variablesCount; i++)
+ {
+ _variables[i].vdata->workOffset = offset;
+
+ // Init back-reference to VarCallRecord.
+ _variables[i].vdata->tPtr = &_variables[i];
+ }
+
+ // --------------------------------------------------------------------------
+ // STEP 1:
+ //
+ // Spill variables which are not used by the function call and have to
+ // be destroyed. These registers may be used by callee.
+ // --------------------------------------------------------------------------
+
+ preserved = _x86Decl.getGpPreservedMask();
+ for (i = 0, mask = 1; i < kX86RegNumGp; i++, mask <<= 1)
+ {
+ X86CompilerVar* cv = x86Context._x86State.gp[i];
+ if (cv && cv->workOffset != offset && !(preserved & mask))
+ x86Context.spillGpVar(cv);
+ }
+
+ preserved = _x86Decl.getMmPreservedMask();
+ for (i = 0, mask = 1; i < kX86RegNumMm; i++, mask <<= 1)
+ {
+ X86CompilerVar* cv = x86Context._x86State.mm[i];
+ if (cv && cv->workOffset != offset && !(preserved & mask))
+ x86Context.spillMmVar(cv);
+ }
+
+ preserved = _x86Decl.getXmmPreservedMask();
+ for (i = 0, mask = 1; i < kX86RegNumXmm; i++, mask <<= 1)
+ {
+ X86CompilerVar* cv = x86Context._x86State.xmm[i];
+ if (cv && cv->workOffset != offset && !(preserved & mask))
+ x86Context.spillXmmVar(cv);
+ }
+
+ // --------------------------------------------------------------------------
+ // STEP 2:
+ //
+ // Move all arguments to the stack which all already in registers.
+ // --------------------------------------------------------------------------
+
+ for (i = 0; i < argumentsCount; i++)
+ {
+ if (processed[i])
+ continue;
+
+ const FuncArg& argType = targs[i];
+ if (argType.hasRegIndex())
+ continue;
+
+ Operand& operand = _args[i];
+
+ if (operand.isVar())
+ {
+ VarCallRecord* rec = _argumentToVarRecord[i];
+ X86CompilerVar* cv = x86Compiler->_getVar(operand.getId());
+
+ if (cv->regIndex != kRegIndexInvalid)
+ {
+ _moveAllocatedVariableToStack(cc,
+ cv, argType);
+
+ rec->inDone++;
+ processed[i] = true;
+ }
+ }
+ }
+
+ // --------------------------------------------------------------------------
+ // STEP 3:
+ //
+ // Spill all non-preserved variables we moved to stack in STEP #2.
+ // --------------------------------------------------------------------------
+
+ for (i = 0; i < argumentsCount; i++)
+ {
+ VarCallRecord* rec = _argumentToVarRecord[i];
+ if (!rec || processed[i])
+ continue;
+
+ if (rec->inDone >= rec->inCount)
+ {
+ X86CompilerVar* cv = rec->vdata;
+ if (cv->regIndex == kRegIndexInvalid)
+ continue;
+
+ if (rec->outCount)
+ {
+ // Variable will be rewritten by function return value, it's not needed
+ // to spill it. It will be allocated again by X86CompilerFuncCall.
+ x86Context.unuseVar(rec->vdata, kVarStateUnused);
+ }
+ else
+ {
+ switch (cv->getType())
+ {
+ case kX86VarTypeGpd:
+ case kX86VarTypeGpq:
+ if (!(_x86Decl.getGpPreservedMask() & IntUtil::maskFromIndex(cv->regIndex)))
+ x86Context.spillGpVar(cv);
+ break;
+ case kX86VarTypeMm:
+ if (!(_x86Decl.getMmPreservedMask() & IntUtil::maskFromIndex(cv->regIndex)))
+ x86Context.spillMmVar(cv);
+ break;
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmPD:
+ if (!(_x86Decl.getXmmPreservedMask() & IntUtil::maskFromIndex(cv->regIndex)))
+ x86Context.spillXmmVar(cv);
+ break;
+ }
+ }
+ }
+ }
+
+ // --------------------------------------------------------------------------
+ // STEP 4:
+ //
+ // Get temporary register that we can use to pass input function arguments.
+ // Now it's safe to do, because the non-needed variables should be spilled.
+ // --------------------------------------------------------------------------
+
+ temporaryGpReg = _findTemporaryGpRegister(cc);
+ temporaryXmmReg = _findTemporaryXmmRegister(cc);
+
+ // If failed to get temporary register then we need just to pick one.
+ if (temporaryGpReg == kRegIndexInvalid)
+ {
+ // TODO.
+ }
+ if (temporaryXmmReg == kRegIndexInvalid)
+ {
+ // TODO.
+ }
+
+ // --------------------------------------------------------------------------
+ // STEP 5:
+ //
+ // Move all remaining arguments to the stack (we can use temporary register).
+ // or allocate it to the primary register. Also move immediates.
+ // --------------------------------------------------------------------------
+
+ for (i = 0; i < argumentsCount; i++)
+ {
+ if (processed[i])
+ continue;
+
+ const FuncArg& argType = targs[i];
+
+ if (argType.hasRegIndex())
+ continue;
+
+ Operand& operand = _args[i];
+
+ if (operand.isVar())
+ {
+ VarCallRecord* rec = _argumentToVarRecord[i];
+ X86CompilerVar* cv = x86Compiler->_getVar(operand.getId());
+
+ _moveSpilledVariableToStack(cc,
+ cv, argType,
+ temporaryGpReg, temporaryXmmReg);
+
+ rec->inDone++;
+ processed[i] = true;
+ }
+ else if (operand.isImm())
+ {
+ // TODO.
+ }
+ }
+
+ // --------------------------------------------------------------------------
+ // STEP 6:
+ //
+ // Allocate arguments to registers.
+ // --------------------------------------------------------------------------
+
+ bool didWork;
+
+ do {
+ didWork = false;
+
+ for (i = 0; i < argumentsCount; i++)
+ {
+ if (processed[i])
+ continue;
+
+ VarCallRecord* rsrc = _argumentToVarRecord[i];
+
+ Operand& osrc = _args[i];
+ ASMJIT_ASSERT(osrc.isVar());
+ X86CompilerVar* vsrc = x86Compiler->_getVar(osrc.getId());
+
+ const FuncArg& srcArgType = targs[i];
+ X86CompilerVar* vdst = _getOverlappingVariable(cc, srcArgType);
+
+ if (vsrc == vdst)
+ {
+ rsrc->inDone++;
+ processed[i] = true;
+
+ didWork = true;
+ continue;
+ }
+ else if (vdst)
+ {
+ VarCallRecord* rdst = reinterpret_cast<VarCallRecord*>(vdst->tPtr);
+
+ if (!rdst)
+ {
+ x86Context.spillVar(vdst);
+ vdst = nullptr;
+ }
+ else if (rdst->inDone >= rdst->inCount && !(rdst->flags & VarCallRecord::kFlagCallReg))
+ {
+ // Safe to spill.
+ if (rdst->outCount || vdst->lastItem == this)
+ x86Context.unuseVar(vdst, kVarStateUnused);
+ else
+ x86Context.spillVar(vdst);
+ vdst = nullptr;
+ }
+ else
+ {
+ uint32_t x = _x86Decl.findArgumentByRegCode(X86Util::getRegCodeFromVarType(vsrc->getType(), vsrc->regIndex));
+ bool doSpill = true;
+
+ if (vdst->getClass() & kX86VarClassGp)
+ {
+ // Try to emit mov to register which is possible for call() operand.
+ if (x == kInvalidValue && (rdst->flags & VarCallRecord::kFlagCallReg))
+ {
+ uint32_t rIndex;
+ uint32_t rBit;
+
+ // The mask which contains registers which are not-preserved
+ // (these that might be clobbered by the callee) and which are
+ // not used to pass function arguments. Each register contained
+ // in this mask is ideal to be used by call() instruction.
+ uint32_t possibleMask = (~_x86Decl.getGpPreservedMask()) &
+ (~_x86Decl.getGpArgumentsMask()) &
+ (IntUtil::maskUpToIndex(kX86RegNumGp));
+
+ if (possibleMask)
+ {
+ for (rIndex = 0, rBit = 1; rIndex < kX86RegNumGp; rIndex++, rBit <<= 1)
+ {
+ if (possibleMask & rBit)
+ {
+ if (!x86Context._x86State.gp[rIndex])
+ {
+ // This is the best possible solution, the register is
+ // free. We do not need to continue with this loop, the
+ // rIndex will be used by the call().
+ break;
+ }
+ else
+ {
+ // Wait until the register is freed or try to find another.
+ doSpill = false;
+ didWork = true;
+ }
+ }
+ }
+ }
+ else
+ {
+ // Try to find a register which is free and which is not used
+ // to pass a function argument.
+ possibleMask = _x86Decl.getGpPreservedMask();
+
+ for (rIndex = 0, rBit = 1; rIndex < kX86RegNumGp; rIndex++, rBit <<= 1)
+ {
+ if (possibleMask & rBit)
+ {
+ // Found one.
+ if (!x86Context._x86State.gp[rIndex]) break;
+ }
+ }
+ }
+
+ if (rIndex < kX86RegNumGp)
+ {
+ if (temporaryGpReg == vsrc->regIndex) temporaryGpReg = rIndex;
+ x86Compiler->emit(kX86InstMov, gpz(rIndex), gpz(vsrc->regIndex));
+
+ x86Context._x86State.gp[vsrc->regIndex] = nullptr;
+ x86Context._x86State.gp[rIndex] = vsrc;
+
+ vsrc->regIndex = rIndex;
+ x86Context._allocatedGpRegister(rIndex);
+
+ doSpill = false;
+ didWork = true;
+ }
+ }
+ // Emit xchg instead of spill/alloc if possible.
+ else if (x != kInvalidValue)
+ {
+ const FuncArg& dstArgType = targs[x];
+ if (X86Util::getVarClassFromVarType(dstArgType.getVarType()) == X86Util::getVarClassFromVarType(srcArgType.getVarType()))
+ {
+ uint32_t dstIndex = vdst->regIndex;
+ uint32_t srcIndex = vsrc->regIndex;
+
+ if (srcIndex == dstArgType.getRegIndex())
+ {
+#if defined(ASMJIT_X64)
+ if (vdst->getType() != kX86VarTypeGpd || vsrc->getType() != kX86VarTypeGpd)
+ x86Compiler->emit(kX86InstXchg, gpq(dstIndex), gpq(srcIndex));
+ else
+#endif
+ x86Compiler->emit(kX86InstXchg, gpd(dstIndex), gpd(srcIndex));
+
+ x86Context._x86State.gp[srcIndex] = vdst;
+ x86Context._x86State.gp[dstIndex] = vsrc;
+
+ vdst->regIndex = srcIndex;
+ vsrc->regIndex = dstIndex;
+
+ rdst->inDone++;
+ rsrc->inDone++;
+
+ processed[i] = true;
+ processed[x] = true;
+
+ doSpill = false;
+ }
+ }
+ }
+ }
+
+ if (doSpill)
+ {
+ x86Context.spillVar(vdst);
+ vdst = nullptr;
+ }
+ }
+ }
+
+ if (!vdst)
+ {
+ VarCallRecord* rec = reinterpret_cast<VarCallRecord*>(vsrc->tPtr);
+
+ _moveSrcVariableToRegister(cc, vsrc, srcArgType);
+
+ switch (srcArgType.getVarType())
+ {
+ case kX86VarTypeGpd:
+ case kX86VarTypeGpq:
+ x86Context._markGpRegisterModified(srcArgType.getRegIndex());
+ break;
+ case kX86VarTypeMm:
+ x86Context._markMmRegisterModified(srcArgType.getRegIndex());
+ break;
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmPD:
+ x86Context._markMmRegisterModified(srcArgType.getRegIndex());
+ break;
+ }
+
+ rec->inDone++;
+ processed[i] = true;
+ }
+ }
+ } while (didWork);
+
+ // --------------------------------------------------------------------------
+ // STEP 7:
+ //
+ // Allocate operand used by CALL instruction.
+ // --------------------------------------------------------------------------
+
+ for (i = 0; i < variablesCount; i++)
+ {
+ VarCallRecord& r = _variables[i];
+ if ((r.flags & VarCallRecord::kFlagCallReg) &&
+ (r.vdata->regIndex == kRegIndexInvalid))
+ {
+ // If the register is not allocated and the call form is 'call reg' then
+ // it's possible to keep it in memory.
+ if (!(r.flags & VarCallRecord::kFlagCallMem))
+ {
+ _target = r.vdata->asGpVar().m();
+ break;
+ }
+
+ if (temporaryGpReg == kRegIndexInvalid)
+ temporaryGpReg = _findTemporaryGpRegister(cc);
+
+ x86Context.allocGpVar(r.vdata,
+ IntUtil::maskFromIndex(temporaryGpReg),
+ kVarAllocRegister | kVarAllocRead);
+ }
+ }
+
+ x86Context.translateOperands(&_target, 1);
+
+ // --------------------------------------------------------------------------
+ // STEP 8:
+ //
+ // Spill all preserved variables.
+ // --------------------------------------------------------------------------
+
+ preserved = _x86Decl.getGpPreservedMask();
+ for (i = 0, mask = 1; i < kX86RegNumGp; i++, mask <<= 1)
+ {
+ X86CompilerVar* vdata = x86Context._x86State.gp[i];
+ if (vdata && !(preserved & mask))
+ {
+ VarCallRecord* rec = reinterpret_cast<VarCallRecord*>(vdata->tPtr);
+ if (rec && (rec->outCount || rec->flags & VarCallRecord::kFlagUnuseAfterUse || vdata->lastItem == this))
+ x86Context.unuseVar(vdata, kVarStateUnused);
+ else
+ x86Context.spillGpVar(vdata);
+ }
+ }
+
+ preserved = _x86Decl.getMmPreservedMask();
+ for (i = 0, mask = 1; i < kX86RegNumMm; i++, mask <<= 1)
+ {
+ X86CompilerVar* vdata = x86Context._x86State.mm[i];
+ if (vdata && !(preserved & mask))
+ {
+ VarCallRecord* rec = reinterpret_cast<VarCallRecord*>(vdata->tPtr);
+ if (rec && (rec->outCount || vdata->lastItem == this))
+ x86Context.unuseVar(vdata, kVarStateUnused);
+ else
+ x86Context.spillMmVar(vdata);
+ }
+ }
+
+ preserved = _x86Decl.getXmmPreservedMask();
+ for (i = 0, mask = 1; i < kX86RegNumXmm; i++, mask <<= 1)
+ {
+ X86CompilerVar* vdata = x86Context._x86State.xmm[i];
+ if (vdata && !(preserved & mask))
+ {
+ VarCallRecord* rec = reinterpret_cast<VarCallRecord*>(vdata->tPtr);
+ if (rec && (rec->outCount || vdata->lastItem == this))
+ x86Context.unuseVar(vdata, kVarStateUnused);
+ else
+ x86Context.spillXmmVar(vdata);
+ }
+ }
+
+ // --------------------------------------------------------------------------
+ // STEP 9:
+ //
+ // Emit CALL instruction.
+ // --------------------------------------------------------------------------
+
+ x86Compiler->emit(kX86InstCall, _target);
+
+ // Restore the stack offset.
+ if (_x86Decl.getCalleePopsStack())
+ {
+ int32_t s = static_cast<int32_t>(_x86Decl.getArgumentsStackSize());
+
+ if (s)
+ x86Compiler->emit(kX86InstSub, zsp, imm(s));
+ }
+
+ // --------------------------------------------------------------------------
+ // STEP 10:
+ //
+ // Prepare others for return value(s) and cleanup.
+ // --------------------------------------------------------------------------
+
+ // Clear temp data, see AsmJit::X86CompilerVar::temp why it's needed.
+ for (i = 0; i < variablesCount; i++)
+ {
+ VarCallRecord* rec = &_variables[i];
+ X86CompilerVar* vdata = rec->vdata;
+
+ if (rec->flags & (VarCallRecord::kFlagOutEax | VarCallRecord::kFlagOutEdx))
+ {
+ if (vdata->getClass() & kX86VarClassGp)
+ {
+ x86Context.allocGpVar(vdata,
+ IntUtil::maskFromIndex((rec->flags & VarCallRecord::kFlagOutEax)
+ ? kX86RegIndexEax
+ : kX86RegIndexEdx),
+ kVarAllocRegister | kVarAllocWrite);
+ vdata->changed = true;
+ }
+ }
+
+ if (rec->flags & (VarCallRecord::kFlagOutMm0))
+ {
+ if (vdata->getClass() & kX86VarClassMm)
+ {
+ x86Context.allocMmVar(vdata, IntUtil::maskFromIndex(kX86RegIndexMm0),
+ kVarAllocRegister | kVarAllocWrite);
+ vdata->changed = true;
+ }
+ }
+
+ if (rec->flags & (VarCallRecord::kFlagOutXmm0 | VarCallRecord::kFlagOutXmm1))
+ {
+ if (vdata->getClass() & kX86VarClassXmm)
+ {
+ x86Context.allocXmmVar(vdata,
+ IntUtil::maskFromIndex((rec->flags & VarCallRecord::kFlagOutXmm0)
+ ? kX86RegIndexXmm0
+ : kX86RegIndexXmm1),
+ kVarAllocRegister | kVarAllocWrite);
+ vdata->changed = true;
+ }
+ }
+
+ if (rec->flags & (VarCallRecord::kFlagOutSt0 | VarCallRecord::kFlagOutSt1))
+ {
+ if (vdata->getClass() & kX86VarClassXmm)
+ {
+ Mem mem(x86Context._getVarMem(vdata));
+ x86Context.unuseVar(vdata, kVarStateMem);
+
+ switch (vdata->getType())
+ {
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ {
+ mem.setSize(4);
+ x86Compiler->emit(kX86InstFStP, mem);
+ break;
+ }
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ {
+ mem.setSize(8);
+ x86Compiler->emit(kX86InstFStP, mem);
+ break;
+ }
+ default:
+ {
+ x86Compiler->comment("*** WARNING: Can't convert float return value to untyped XMM\n");
+ break;
+ }
+ }
+ }
+ }
+
+ // Cleanup.
+ vdata->tPtr = nullptr;
+ }
+
+ for (i = 0; i < variablesCount; i++)
+ {
+ x86Context._unuseVarOnEndOfScope(this, &_variables[i]);
+ }
+
+ return translated();
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerFuncCall - Misc]
+// ============================================================================
+
+int X86CompilerFuncCall::getMaxSize() const
+{
+ // TODO: Instruction max size.
+ return 15;
+}
+
+bool X86CompilerFuncCall::_tryUnuseVar(CompilerVar* _v)
+{
+ X86CompilerVar* cv = static_cast<X86CompilerVar*>(_v);
+
+ for (uint32_t i = 0; i < _variablesCount; i++)
+ {
+ if (_variables[i].vdata == cv)
+ {
+ _variables[i].flags |= VarCallRecord::kFlagUnuseAfterUse;
+ return true;
+ }
+ }
+
+ return false;
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerFuncCall - Helpers]
+// ============================================================================
+
+uint32_t X86CompilerFuncCall::_findTemporaryGpRegister(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+
+ uint32_t i;
+ uint32_t mask;
+
+ uint32_t passedGP = _x86Decl.getGpArgumentsMask();
+ uint32_t candidate = kRegIndexInvalid;
+
+ // Find all registers used to pass function arguments. We shouldn't use these
+ // if possible.
+ for (i = 0, mask = 1; i < kX86RegNumGp; i++, mask <<= 1)
+ {
+ if (!x86Context._x86State.gp[i])
+ {
+ // If this register is used to pass arguments to function, we will mark
+ // it and use it only if there is no other one.
+ if (passedGP & mask)
+ candidate = i;
+ else
+ return i;
+ }
+ }
+
+ return candidate;
+}
+
+uint32_t X86CompilerFuncCall::_findTemporaryXmmRegister(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+
+ uint32_t i;
+ uint32_t mask;
+
+ uint32_t passedXMM = _x86Decl.getXmmArgumentsMask();
+ uint32_t candidate = kRegIndexInvalid;
+
+ // Find all registers used to pass function arguments. We shouldn't use these
+ // if possible.
+ for (i = 0, mask = 1; i < kX86RegNumXmm; i++, mask <<= 1)
+ {
+ if (!x86Context._x86State.xmm[i])
+ {
+ // If this register is used to pass arguments to function, we will mark
+ // it and use it only if there is no other one.
+ if (passedXMM & mask)
+ candidate = i;
+ else
+ return i;
+ }
+ }
+
+ return candidate;
+}
+
+X86CompilerVar* X86CompilerFuncCall::_getOverlappingVariable(CompilerContext& cc, const FuncArg& argType) const
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+ ASMJIT_ASSERT(argType.getVarType() != kVarTypeInvalid);
+
+ switch (argType.getVarType())
+ {
+ case kX86VarTypeGpd:
+ case kX86VarTypeGpq:
+ return x86Context._x86State.gp[argType.getRegIndex()];
+ case kX86VarTypeMm:
+ return x86Context._x86State.mm[argType.getRegIndex()];
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmPD:
+ return x86Context._x86State.xmm[argType.getRegIndex()];
+ }
+
+ return nullptr;
+}
+
+void X86CompilerFuncCall::_moveAllocatedVariableToStack(CompilerContext& cc, X86CompilerVar* vdata, const FuncArg& argType)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+ X86Compiler* x86Compiler = x86Context.getCompiler();
+
+ ASMJIT_ASSERT(!argType.hasRegIndex());
+ ASMJIT_ASSERT(vdata->regIndex != kRegIndexInvalid);
+
+ uint32_t src = vdata->regIndex;
+ Mem dst = ptr(zsp, -(int)sizeof(uintptr_t) + argType.getStackOffset());
+
+ switch (vdata->getType())
+ {
+ case kX86VarTypeGpd:
+ switch (argType.getVarType())
+ {
+ case kX86VarTypeGpd:
+ x86Compiler->emit(kX86InstMov, dst, gpd(src));
+ return;
+#if defined(ASMJIT_X64)
+ case kX86VarTypeGpq:
+ case kX86VarTypeMm:
+ x86Compiler->emit(kX86InstMov, dst, gpq(src));
+ return;
+#endif // ASMJIT_X64
+ }
+ break;
+
+#if defined(ASMJIT_X64)
+ case kX86VarTypeGpq:
+ switch (argType.getVarType())
+ {
+ case kX86VarTypeGpd:
+ x86Compiler->emit(kX86InstMov, dst, gpd(src));
+ return;
+ case kX86VarTypeGpq:
+ x86Compiler->emit(kX86InstMov, dst, gpq(src));
+ return;
+ case kX86VarTypeMm:
+ x86Compiler->emit(kX86InstMovQ, dst, gpq(src));
+ return;
+ }
+ break;
+#endif // ASMJIT_X64
+
+ case kX86VarTypeMm:
+ switch (argType.getVarType())
+ {
+ case kX86VarTypeGpd:
+ case kX86VarTypeX87SS:
+ case kX86VarTypeXmmSS:
+ x86Compiler->emit(kX86InstMovD, dst, mm(src));
+ return;
+ case kX86VarTypeGpq:
+ case kX86VarTypeMm:
+ case kX86VarTypeX87SD:
+ case kX86VarTypeXmmSD:
+ x86Compiler->emit(kX86InstMovQ, dst, mm(src));
+ return;
+ }
+ break;
+
+ // We allow incompatible types here, because the called can convert them
+ // to correct format before function is called.
+
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmPD:
+ switch (argType.getVarType())
+ {
+ case kX86VarTypeXmm:
+ x86Compiler->emit(kX86InstMovDQU, dst, xmm(src));
+ return;
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ x86Compiler->emit(kX86InstMovUPS, dst, xmm(src));
+ return;
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ x86Compiler->emit(kX86InstMovUPD, dst, xmm(src));
+ return;
+ }
+ break;
+
+ case kX86VarTypeXmmSS:
+ switch (argType.getVarType())
+ {
+ case kX86VarTypeX87SS:
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ x86Compiler->emit(kX86InstMovSS, dst, xmm(src));
+ return;
+ }
+ break;
+
+ case kX86VarTypeXmmSD:
+ switch (argType.getVarType())
+ {
+ case kX86VarTypeX87SD:
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ x86Compiler->emit(kX86InstMovSD, dst, xmm(src));
+ return;
+ }
+ break;
+ }
+
+ x86Compiler->setError(kErrorIncompatibleArgumentType);
+}
+
+void X86CompilerFuncCall::_moveSpilledVariableToStack(CompilerContext& cc,
+ X86CompilerVar* cv, const FuncArg& argType,
+ uint32_t temporaryGpReg,
+ uint32_t temporaryXmmReg)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+ X86Compiler* x86Compiler = x86Context.getCompiler();
+
+ ASMJIT_ASSERT(!argType.hasRegIndex());
+ ASMJIT_ASSERT(cv->regIndex == kRegIndexInvalid);
+
+ Mem src = x86Context._getVarMem(cv);
+ Mem dst = ptr(zsp, -(int)sizeof(sysint_t) + argType.getStackOffset());
+
+ switch (cv->getType())
+ {
+ case kX86VarTypeGpd:
+ switch (argType.getVarType())
+ {
+ case kX86VarTypeGpd:
+ x86Compiler->emit(kX86InstMov, gpd(temporaryGpReg), src);
+ x86Compiler->emit(kX86InstMov, dst, gpd(temporaryGpReg));
+ return;
+#if defined(ASMJIT_X64)
+ case kX86VarTypeGpq:
+ case kX86VarTypeMm:
+ x86Compiler->emit(kX86InstMov, gpd(temporaryGpReg), src);
+ x86Compiler->emit(kX86InstMov, dst, gpq(temporaryGpReg));
+ return;
+#endif // ASMJIT_X64
+ }
+ break;
+
+#if defined(ASMJIT_X64)
+ case kX86VarTypeGpq:
+ switch (argType.getVarType())
+ {
+ case kX86VarTypeGpd:
+ x86Compiler->emit(kX86InstMov, gpd(temporaryGpReg), src);
+ x86Compiler->emit(kX86InstMov, dst, gpd(temporaryGpReg));
+ return;
+ case kX86VarTypeGpq:
+ case kX86VarTypeMm:
+ x86Compiler->emit(kX86InstMov, gpq(temporaryGpReg), src);
+ x86Compiler->emit(kX86InstMov, dst, gpq(temporaryGpReg));
+ return;
+ }
+ break;
+#endif // ASMJIT_X64
+
+ case kX86VarTypeMm:
+ switch (argType.getVarType())
+ {
+ case kX86VarTypeGpd:
+ case kX86VarTypeX87SS:
+ case kX86VarTypeXmmSS:
+ x86Compiler->emit(kX86InstMov, gpd(temporaryGpReg), src);
+ x86Compiler->emit(kX86InstMov, dst, gpd(temporaryGpReg));
+ return;
+ case kX86VarTypeGpq:
+ case kX86VarTypeMm:
+ case kX86VarTypeX87SD:
+ case kX86VarTypeXmmSD:
+ // TODO
+ return;
+ }
+ break;
+
+ // We allow incompatible types here, because the caller can convert them
+ // to correct format before function is called.
+
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmPD:
+ switch (argType.getVarType())
+ {
+ case kX86VarTypeXmm:
+ x86Compiler->emit(kX86InstMovDQU, xmm(temporaryXmmReg), src);
+ x86Compiler->emit(kX86InstMovDQU, dst, xmm(temporaryXmmReg));
+ return;
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ x86Compiler->emit(kX86InstMovUPS, xmm(temporaryXmmReg), src);
+ x86Compiler->emit(kX86InstMovUPS, dst, xmm(temporaryXmmReg));
+ return;
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ x86Compiler->emit(kX86InstMovUPD, xmm(temporaryXmmReg), src);
+ x86Compiler->emit(kX86InstMovUPD, dst, xmm(temporaryXmmReg));
+ return;
+ }
+ break;
+
+ case kX86VarTypeXmmSS:
+ switch (argType.getVarType())
+ {
+ case kX86VarTypeX87SS:
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ x86Compiler->emit(kX86InstMovSS, xmm(temporaryXmmReg), src);
+ x86Compiler->emit(kX86InstMovSS, dst, xmm(temporaryXmmReg));
+ return;
+ }
+ break;
+
+ case kX86VarTypeXmmSD:
+ switch (argType.getVarType())
+ {
+ case kX86VarTypeX87SD:
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ x86Compiler->emit(kX86InstMovSD, xmm(temporaryXmmReg), src);
+ x86Compiler->emit(kX86InstMovSD, dst, xmm(temporaryXmmReg));
+ return;
+ }
+ break;
+ }
+
+ x86Compiler->setError(kErrorIncompatibleArgumentType);
+}
+
+void X86CompilerFuncCall::_moveSrcVariableToRegister(CompilerContext& cc,
+ X86CompilerVar* cv, const FuncArg& argType)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+ X86Compiler* x86Compiler = x86Context.getCompiler();
+
+ uint32_t dst = argType.getRegIndex();
+ uint32_t src = cv->regIndex;
+
+ if (src != kRegIndexInvalid)
+ {
+ switch (argType.getVarType())
+ {
+ case kX86VarTypeGpd:
+ switch (cv->getType())
+ {
+ case kX86VarTypeGpd:
+#if defined(ASMJIT_X64)
+ case kX86VarTypeGpq:
+#endif // ASMJIT_X64
+ x86Compiler->emit(kX86InstMov, gpd(dst), gpd(src));
+ return;
+ case kX86VarTypeMm:
+ x86Compiler->emit(kX86InstMovD, gpd(dst), mm(src));
+ return;
+ }
+ break;
+
+#if defined(ASMJIT_X64)
+ case kX86VarTypeGpq:
+ switch (cv->getType())
+ {
+ case kX86VarTypeGpd:
+ x86Compiler->emit(kX86InstMov, gpd(dst), gpd(src));
+ return;
+ case kX86VarTypeGpq:
+ x86Compiler->emit(kX86InstMov, gpq(dst), gpq(src));
+ return;
+ case kX86VarTypeMm:
+ x86Compiler->emit(kX86InstMovQ, gpq(dst), mm(src));
+ return;
+ }
+ break;
+#endif // ASMJIT_X64
+
+ case kX86VarTypeMm:
+ switch (cv->getType())
+ {
+ case kX86VarTypeGpd:
+ x86Compiler->emit(kX86InstMovD, gpd(dst), gpd(src));
+ return;
+#if defined(ASMJIT_X64)
+ case kX86VarTypeGpq:
+ x86Compiler->emit(kX86InstMovQ, gpq(dst), gpq(src));
+ return;
+#endif // ASMJIT_X64
+ case kX86VarTypeMm:
+ x86Compiler->emit(kX86InstMovQ, mm(dst), mm(src));
+ return;
+ }
+ break;
+
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmPD:
+ switch (cv->getType())
+ {
+ case kX86VarTypeGpd:
+ x86Compiler->emit(kX86InstMovD, xmm(dst), gpd(src));
+ return;
+#if defined(ASMJIT_X64)
+ case kX86VarTypeGpq:
+ x86Compiler->emit(kX86InstMovQ, xmm(dst), gpq(src));
+ return;
+#endif // ASMJIT_X64
+ case kX86VarTypeMm:
+ x86Compiler->emit(kX86InstMovQ, xmm(dst), mm(src));
+ return;
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ x86Compiler->emit(kX86InstMovDQA, xmm(dst), xmm(src));
+ return;
+ }
+ break;
+
+ case kX86VarTypeXmmSS:
+ switch (cv->getType())
+ {
+ case kX86VarTypeMm:
+ x86Compiler->emit(kX86InstMovQ, xmm(dst), mm(src));
+ return;
+
+ case kX86VarTypeXmm:
+ x86Compiler->emit(kX86InstMovDQA, xmm(dst), xmm(src));
+ return;
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ x86Compiler->emit(kX86InstMovSS, xmm(dst), xmm(src));
+ return;
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ x86Compiler->emit(kX86InstCvtSD2SS, xmm(dst), xmm(src));
+ return;
+ }
+ break;
+
+ case kX86VarTypeXmmSD:
+ switch (cv->getType())
+ {
+ case kX86VarTypeMm:
+ x86Compiler->emit(kX86InstMovQ, xmm(dst), mm(src));
+ return;
+
+ case kX86VarTypeXmm:
+ x86Compiler->emit(kX86InstMovDQA, xmm(dst), xmm(src));
+ return;
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ x86Compiler->emit(kX86InstCvtSS2SD, xmm(dst), xmm(src));
+ return;
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ x86Compiler->emit(kX86InstMovSD, xmm(dst), xmm(src));
+ return;
+ }
+ break;
+ }
+ }
+ else
+ {
+ Mem mem = x86Context._getVarMem(cv);
+
+ switch (argType.getVarType())
+ {
+ case kX86VarTypeGpd:
+ switch (cv->getType())
+ {
+ case kX86VarTypeGpd:
+#if defined(ASMJIT_X64)
+ case kX86VarTypeGpq:
+#endif // ASMJIT_X64
+ x86Compiler->emit(kX86InstMov, gpd(dst), mem);
+ return;
+ case kX86VarTypeMm:
+ x86Compiler->emit(kX86InstMovD, gpd(dst), mem);
+ return;
+ }
+ break;
+
+#if defined(ASMJIT_X64)
+ case kX86VarTypeGpq:
+ switch (cv->getType())
+ {
+ case kX86VarTypeGpd:
+ x86Compiler->emit(kX86InstMov, gpd(dst), mem);
+ return;
+ case kX86VarTypeGpq:
+ x86Compiler->emit(kX86InstMov, gpq(dst), mem);
+ return;
+ case kX86VarTypeMm:
+ x86Compiler->emit(kX86InstMovQ, gpq(dst), mem);
+ return;
+ }
+ break;
+#endif // ASMJIT_X64
+
+ case kX86VarTypeMm:
+ switch (cv->getType())
+ {
+ case kX86VarTypeGpd:
+ x86Compiler->emit(kX86InstMovD, gpd(dst), mem);
+ return;
+#if defined(ASMJIT_X64)
+ case kX86VarTypeGpq:
+ x86Compiler->emit(kX86InstMovQ, gpq(dst), mem);
+ return;
+#endif // ASMJIT_X64
+ case kX86VarTypeMm:
+ x86Compiler->emit(kX86InstMovQ, mm(dst), mem);
+ return;
+ }
+ break;
+
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmPD:
+ switch (cv->getType())
+ {
+ case kX86VarTypeGpd:
+ x86Compiler->emit(kX86InstMovD, xmm(dst), mem);
+ return;
+#if defined(ASMJIT_X64)
+ case kX86VarTypeGpq:
+ x86Compiler->emit(kX86InstMovQ, xmm(dst), mem);
+ return;
+#endif // ASMJIT_X64
+ case kX86VarTypeMm:
+ x86Compiler->emit(kX86InstMovQ, xmm(dst), mem);
+ return;
+ case kX86VarTypeXmm:
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ x86Compiler->emit(kX86InstMovDQA, xmm(dst), mem);
+ return;
+ }
+ break;
+
+ case kX86VarTypeXmmSS:
+ switch (cv->getType())
+ {
+ case kX86VarTypeMm:
+ x86Compiler->emit(kX86InstMovQ, xmm(dst), mem);
+ return;
+
+ case kX86VarTypeXmm:
+ x86Compiler->emit(kX86InstMovDQA, xmm(dst), mem);
+ return;
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ x86Compiler->emit(kX86InstMovSS, xmm(dst), mem);
+ return;
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ x86Compiler->emit(kX86InstCvtSD2SS, xmm(dst), mem);
+ return;
+ }
+ break;
+
+ case kX86VarTypeXmmSD:
+ switch (cv->getType())
+ {
+ case kX86VarTypeMm:
+ x86Compiler->emit(kX86InstMovQ, xmm(dst), mem);
+ return;
+
+ case kX86VarTypeXmm:
+ x86Compiler->emit(kX86InstMovDQA, xmm(dst), mem);
+ return;
+ case kX86VarTypeXmmSS:
+ case kX86VarTypeXmmPS:
+ x86Compiler->emit(kX86InstCvtSS2SD, xmm(dst), mem);
+ return;
+ case kX86VarTypeXmmSD:
+ case kX86VarTypeXmmPD:
+ x86Compiler->emit(kX86InstMovSD, xmm(dst), mem);
+ return;
+ }
+ break;
+ }
+ }
+
+ x86Compiler->setError(kErrorIncompatibleArgumentType);
+}
+
+// Prototype & Arguments Management.
+void X86CompilerFuncCall::setPrototype(uint32_t callingConvention, uint32_t returnType, const uint32_t* arguments, uint32_t argumentsCount)
+{
+ _x86Decl.setPrototype(callingConvention, returnType, arguments, argumentsCount);
+ _args = reinterpret_cast<Operand*>(
+ getCompiler()->getZoneMemory().alloc(sizeof(Operand) * argumentsCount));
+ memset(_args, 0, sizeof(Operand) * argumentsCount);
+}
+
+bool X86CompilerFuncCall::setArgument(uint32_t i, const Var& var)
+{
+ ASMJIT_ASSERT(i < _x86Decl.getArgumentsCount());
+
+ if (i >= _x86Decl.getArgumentsCount())
+ return false;
+
+ _args[i] = var;
+ return true;
+}
+
+bool X86CompilerFuncCall::setArgument(uint32_t i, const Imm& imm)
+{
+ ASMJIT_ASSERT(i < _x86Decl.getArgumentsCount());
+
+ if (i >= _x86Decl.getArgumentsCount())
+ return false;
+
+ _args[i] = imm;
+ return true;
+}
+
+bool X86CompilerFuncCall::setReturn(const Operand& first, const Operand& second)
+{
+ _ret[0] = first;
+ _ret[1] = second;
+
+ return true;
+}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86/x86compilerfunc.h
@@ -1,1 +1,370 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_X86_X86COMPILERFUNC_H
+#define _ASMJIT_X86_X86COMPILERFUNC_H
+
+// [Dependencies - AsmJit]
+#include "../x86/x86assembler.h"
+#include "../x86/x86compiler.h"
+#include "../x86/x86compileritem.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit {
+
+//! @addtogroup AsmJit_X86
+//! @{
+
+// ============================================================================
+// [AsmJit::X86CompilerFuncDecl]
+// ============================================================================
+
+//! @brief @ref X86Compiler specific function declaration item.
+struct X86CompilerFuncDecl : public CompilerFuncDecl
+{
+ ASMJIT_NO_COPY(X86CompilerFuncDecl)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref X86CompilerFuncDecl instance.
+ ASMJIT_API X86CompilerFuncDecl(X86Compiler* x86Compiler);
+ //! @brief Destroy the @ref X86CompilerFuncDecl instance.
+ ASMJIT_API virtual ~X86CompilerFuncDecl();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get compiler as @ref X86Compiler.
+ X86Compiler* getCompiler() const
+ { return reinterpret_cast<X86Compiler*>(_compiler); }
+
+ //! @brief Get function end item as @ref X86CompilerFuncEnd.
+ X86CompilerFuncEnd* getEnd() const
+ { return reinterpret_cast<X86CompilerFuncEnd*>(_end); }
+
+ //! @brief Get function declaration as @ref X86FuncDecl.
+ X86FuncDecl* getDecl() const
+ { return reinterpret_cast<X86FuncDecl*>(_decl); }
+
+ //! @brief Get function arguments as variables as @ref X86CompilerVar.
+ X86CompilerVar** getVars() const
+ { return reinterpret_cast<X86CompilerVar**>(_vars); }
+
+ //! @brief Get function argument at @a index.
+ X86CompilerVar* getVar(uint32_t index) const
+ {
+ ASMJIT_ASSERT(index < _x86Decl.getArgumentsCount());
+ return reinterpret_cast<X86CompilerVar**>(_vars)[index];
+ }
+
+ //! @brief Get whether it's assumed that stack is aligned to 16 bytes.
+ bool isAssumed16ByteAlignment() const
+ { return hasFuncFlag(kX86FuncFlagAssume16ByteAlignment); }
+
+ //! @brief Get whether it's required to align stack to 16 bytes by function.
+ bool isPerformed16ByteAlignment() const
+ { return hasFuncFlag(kX86FuncFlagPerform16ByteAlignment); }
+
+ //! @brief Get whether the ESP is adjusted.
+ bool isEspAdjusted() const
+ { return hasFuncFlag(kX86FuncFlagIsEspAdjusted); }
+
+ // --------------------------------------------------------------------------
+ // [Interface]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual void prepare(CompilerContext& cc);
+ ASMJIT_API virtual CompilerItem* translate(CompilerContext& cc);
+
+ // --------------------------------------------------------------------------
+ // [Misc]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual int getMaxSize() const;
+
+ // --------------------------------------------------------------------------
+ // [Prototype]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual void setPrototype(
+ uint32_t convention,
+ uint32_t returnType,
+ const uint32_t* arguments,
+ uint32_t argumentsCount);
+
+ // --------------------------------------------------------------------------
+ // [Helpers]
+ // --------------------------------------------------------------------------
+
+ //! @internal
+ //!
+ //! @brief Get required stack offset needed to subtract/add Esp/Rsp in
+ //! prolog/epilog.
+ int32_t _getRequiredStackOffset() const
+ { return _funcCallStackSize + _memStackSize16 + _peMovStackSize + _peAdjustStackSize; }
+
+ //! @brief Create variables from FunctionPrototype declaration. This is just
+ //! parsing what FunctionPrototype generated for current function calling
+ //! convention and arguments.
+ ASMJIT_API void _createVariables();
+
+ //! @brief Prepare variables (ids, names, scope, registers).
+ ASMJIT_API void _prepareVariables(CompilerItem* first);
+
+ //! @brief Allocate variables (setting correct state, changing masks, etc).
+ ASMJIT_API void _allocVariables(CompilerContext& cc);
+
+ ASMJIT_API void _preparePrologEpilog(CompilerContext& cc);
+ ASMJIT_API void _dumpFunction(CompilerContext& cc);
+ ASMJIT_API void _emitProlog(CompilerContext& cc);
+ ASMJIT_API void _emitEpilog(CompilerContext& cc);
+
+ // --------------------------------------------------------------------------
+ // [Function-Call]
+ // --------------------------------------------------------------------------
+
+ //! @brief Reserve stack for calling other function and mark function as
+ //! callee.
+ ASMJIT_API void reserveStackForFunctionCall(int32_t size);
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief X86 function decl.
+ X86FuncDecl _x86Decl;
+
+ //! @brief Modified and preserved GP registers mask.
+ uint32_t _gpModifiedAndPreserved;
+ //! @brief Modified and preserved MM registers mask.
+ uint32_t _mmModifiedAndPreserved;
+ //! @brief Modified and preserved XMM registers mask.
+ uint32_t _xmmModifiedAndPreserved;
+
+ //! @brief Id of MovDQWord instruction (@c kX86InstMovDQA or @c kX86InstMovDQU).
+ //!
+ //! The value is based on stack alignment. If it's guaranteed that stack
+ //! is aligned to 16-bytes then @c kX86InstMovDQA instruction is used, otherwise
+ //! the @c kX86InstMovDQU instruction is used for 16-byte mov.
+ uint32_t _movDqInstCode;
+
+ //! @brief Prolog / epilog stack size for PUSH/POP sequences.
+ int32_t _pePushPopStackSize;
+ //! @brief Prolog / epilog stack size for MOV sequences.
+ int32_t _peMovStackSize;
+ //! @brief Prolog / epilog stack adjust size (to make it 16-byte aligned).
+ int32_t _peAdjustStackSize;
+
+ //! @brief Memory stack size (for all variables and temporary memory).
+ int32_t _memStackSize;
+ //! @brief Like @c _memStackSize, but aligned to 16-bytes.
+ int32_t _memStackSize16;
+};
+
+// ============================================================================
+// [AsmJit::X86CompilerFuncEnd]
+// ============================================================================
+
+//! @brief @ref X86Compiler function end item.
+struct X86CompilerFuncEnd : public CompilerFuncEnd
+{
+ ASMJIT_NO_COPY(X86CompilerFuncEnd)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref X86CompilerFuncEnd instance.
+ ASMJIT_API X86CompilerFuncEnd(X86Compiler* x86Compiler, X86CompilerFuncDecl* func);
+ //! @brief Destroy the @ref X86CompilerFuncEnd instance.
+ ASMJIT_API virtual ~X86CompilerFuncEnd();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get compiler as @ref X86Compiler.
+ X86Compiler* getCompiler() const
+ { return reinterpret_cast<X86Compiler*>(_compiler); }
+
+ //! @brief Get related function as @ref X86CompilerFuncDecl.
+ X86CompilerFuncDecl* getFunc() const
+ { return reinterpret_cast<X86CompilerFuncDecl*>(_func); }
+
+ // --------------------------------------------------------------------------
+ // [Interface]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual void prepare(CompilerContext& cc);
+ ASMJIT_API virtual CompilerItem* translate(CompilerContext& cc);
+};
+
+// ============================================================================
+// [AsmJit::X86CompilerFuncRet]
+// ============================================================================
+
+//! @brief Function return.
+struct X86CompilerFuncRet : public CompilerFuncRet
+{
+ ASMJIT_NO_COPY(X86CompilerFuncRet)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref X86CompilerFuncRet instance.
+ ASMJIT_API X86CompilerFuncRet(X86Compiler* c, X86CompilerFuncDecl* func,
+ const Operand* first, const Operand* second);
+ //! @brief Destroy the @ref X86CompilerFuncRet instance.
+ ASMJIT_API virtual ~X86CompilerFuncRet();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get compiler as @ref X86Compiler.
+ X86Compiler* getCompiler() const
+ { return reinterpret_cast<X86Compiler*>(_compiler); }
+
+ //! @Brief Get related function as @ref X86CompilerFuncDecl.
+ X86CompilerFuncDecl* getFunc() const
+ { return reinterpret_cast<X86CompilerFuncDecl*>(_func); }
+
+ // --------------------------------------------------------------------------
+ // [Interface]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual void prepare(CompilerContext& cc);
+ ASMJIT_API virtual CompilerItem* translate(CompilerContext& cc);
+ ASMJIT_API virtual void emit(Assembler& a);
+
+ // --------------------------------------------------------------------------
+ // [Misc]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual int getMaxSize() const;
+};
+
+// ============================================================================
+// [AsmJit::X86CompilerFuncCall]
+// ============================================================================
+
+//! @brief Compiler function call item.
+struct X86CompilerFuncCall : public CompilerFuncCall
+{
+ ASMJIT_NO_COPY(X86CompilerFuncCall)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref X86CompilerFuncCall instance.
+ ASMJIT_API X86CompilerFuncCall(X86Compiler* x86Compiler, X86CompilerFuncDecl* caller, const Operand* target);
+ //! @brief Destroy the @ref X86CompilerFuncCall instance.
+ ASMJIT_API virtual ~X86CompilerFuncCall();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get compiler as @ref X86Compiler.
+ X86Compiler* getCompiler() const
+ { return reinterpret_cast<X86Compiler*>(_compiler); }
+
+ //! @brief Get caller as @ref X86CompilerFuncDecl.
+ X86CompilerFuncDecl* getCaller() const
+ { return reinterpret_cast<X86CompilerFuncDecl*>(_caller); }
+
+ //! @brief Get function prototype.
+ const X86FuncDecl* getDecl() const
+ { return reinterpret_cast<X86FuncDecl*>(_decl); }
+
+ // --------------------------------------------------------------------------
+ // [Interface]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual void prepare(CompilerContext& cc);
+ ASMJIT_API virtual CompilerItem* translate(CompilerContext& cc);
+
+ // --------------------------------------------------------------------------
+ // [Misc]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual int getMaxSize() const;
+ ASMJIT_API virtual bool _tryUnuseVar(CompilerVar* v);
+
+ // --------------------------------------------------------------------------
+ // [Prototype]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual void setPrototype(uint32_t convention, uint32_t returnType, const uint32_t* arguments, uint32_t argumentsCount);
+
+ //! @brief Set function prototype.
+ void setPrototype(uint32_t convention, const FuncPrototype& func)
+ { setPrototype(convention, func.getReturnType(), func.getArguments(), func.getArgumentsCount()); }
+
+ //! @brief Set return value.
+ ASMJIT_API bool setReturn(const Operand& first, const Operand& second = Operand());
+
+ //! @brief Set function argument @a i to @a var.
+ ASMJIT_API bool setArgument(uint32_t i, const Var& var);
+ //! @brief Set function argument @a i to @a imm.
+ ASMJIT_API bool setArgument(uint32_t i, const Imm& imm);
+
+ // --------------------------------------------------------------------------
+ // [Internal]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API uint32_t _findTemporaryGpRegister(CompilerContext& cc);
+ ASMJIT_API uint32_t _findTemporaryXmmRegister(CompilerContext& cc);
+
+ ASMJIT_API X86CompilerVar* _getOverlappingVariable(CompilerContext& cc, const FuncArg& argType) const;
+
+ ASMJIT_API void _moveAllocatedVariableToStack(CompilerContext& cc, X86CompilerVar* vdata, const FuncArg& argType);
+ ASMJIT_API void _moveSpilledVariableToStack(CompilerContext& cc, X86CompilerVar* vdata, const FuncArg& argType,
+ uint32_t temporaryGpReg,
+ uint32_t temporaryXmmReg);
+ ASMJIT_API void _moveSrcVariableToRegister(CompilerContext& cc, X86CompilerVar* vdata, const FuncArg& argType);
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief X86 declaration.
+ X86FuncDecl _x86Decl;
+
+ //! @brief Mask of GP registers used as function arguments.
+ uint32_t _gpParams;
+ //! @brief Mask of MM registers used as function arguments.
+ uint32_t _mmParams;
+ //! @brief Mask of XMM registers used as function arguments.
+ uint32_t _xmmParams;
+
+ //! @brief Variables count.
+ uint32_t _variablesCount;
+
+ //! @brief Variables (extracted from operands).
+ VarCallRecord* _variables;
+ //! @brief Argument index to @c VarCallRecord.
+ VarCallRecord* _argumentToVarRecord[kFuncArgsMax];
+};
+
+//! @}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_X86_X86COMPILERFUNC_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86/x86compileritem.cpp
@@ -1,1 +1,1829 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/intutil.h"
+#include "../core/stringutil.h"
+
+#include "../x86/x86compiler.h"
+#include "../x86/x86compilercontext.h"
+#include "../x86/x86compilerfunc.h"
+#include "../x86/x86compileritem.h"
+#include "../x86/x86util.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit {
+
+// ============================================================================
+// [AsmJit::X86CompilerAlign - Construction / Destruction]
+// ============================================================================
+
+X86CompilerAlign::X86CompilerAlign(X86Compiler* x86Compiler, uint32_t size) :
+ CompilerAlign(x86Compiler, size)
+{
+}
+
+X86CompilerAlign::~X86CompilerAlign()
+{
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerAlign - Interface]
+// ============================================================================
+
+void X86CompilerAlign::emit(Assembler& a)
+{
+ X86Assembler& x86Asm = static_cast<X86Assembler&>(a);
+
+ x86Asm.align(_size);
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerTarget - Construction / Destruction]
+// ============================================================================
+
+X86CompilerTarget::X86CompilerTarget(X86Compiler* c, const Label& label) :
+ CompilerTarget(c, label)
+{
+}
+
+X86CompilerTarget::~X86CompilerTarget()
+{
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerTarget - Interface]
+// ============================================================================
+
+static X86CompilerTarget* X86CompilerTarget_removeUnreachableItems(X86CompilerTarget* target)
+{
+ CompilerItem* prev = target->getPrev();
+ CompilerItem* item = target->getNext();
+
+ ASMJIT_ASSERT(!!prev);
+ ASMJIT_ASSERT(!!item);
+
+ for (;;)
+ {
+ CompilerItem* next = item->getNext();
+ ASMJIT_ASSERT(!!next);
+
+ if (item->getType() == kCompilerItemTarget)
+ break;
+
+ item->_prev = nullptr;
+ item->_next = nullptr;
+ item->_isUnreachable = true;
+
+ item = next;
+ }
+
+ target->_prev = nullptr;
+ target->_next = nullptr;
+ target->_isTranslated = true;
+
+ prev->_next = item;
+ item->_prev = prev;
+
+ return static_cast<X86CompilerTarget*>(item);
+}
+
+void X86CompilerTarget::prepare(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+ _offset = x86Context._currentOffset++;
+}
+
+CompilerItem* X86CompilerTarget::translate(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+
+ // If this X86CompilerTarget was already translated, it's needed to change
+ // the current state and return NULL to tell CompilerContext to process next
+ // untranslated item.
+ if (_isTranslated)
+ {
+ x86Context._restoreState(getState());
+ return nullptr;
+ }
+
+ if (x86Context._isUnreachable)
+ {
+ // If the context has "isUnreachable" flag set and there is no state then
+ // it means that this code will be never called. This is a problem, because
+ // we are unable to assign a state to current location so we can't allocate
+ // registers for variables used inside. So instead of doing anything wrong
+ // we remove the unreachable code.
+ if (!_state)
+ return X86CompilerTarget_removeUnreachableItems(this);
+
+ // Assign state to the compiler context.
+ x86Context._isUnreachable = 0;
+ x86Context._assignState(getState());
+ }
+ else
+ {
+ _state = x86Context._saveState();
+ }
+
+ return translated();
+}
+
+void X86CompilerTarget::emit(Assembler& a)
+{
+ X86Assembler& x86Asm = static_cast<X86Assembler&>(a);
+ x86Asm.bind(_label);
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerHint - Construction / Destruction]
+// ============================================================================
+
+X86CompilerHint::X86CompilerHint(X86Compiler* compiler, X86CompilerVar* var, uint32_t hintId, uint32_t hintValue) :
+ CompilerHint(compiler, var, hintId, hintValue)
+{
+}
+
+X86CompilerHint::~X86CompilerHint()
+{
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerHint - Interface]
+// ============================================================================
+
+void X86CompilerHint::prepare(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+ X86CompilerVar* var = getVar();
+
+ _offset = x86Context._currentOffset;
+
+ // First item (begin of variable scope).
+ if (!var->firstItem)
+ var->firstItem = this;
+
+ // Last item (end of variable scope).
+ CompilerItem* oldLast = var->lastItem;
+ var->lastItem = this;
+
+ switch (_hintId)
+ {
+ case kVarHintAlloc:
+ case kVarHintSpill:
+ case kVarHintSave:
+ if (!x86Context._isActive(var))
+ x86Context._addActive(var);
+ break;
+
+ case kVarHintSaveAndUnuse:
+ if (!x86Context._isActive(var))
+ x86Context._addActive(var);
+ break;
+
+ case kVarHintUnuse:
+ if (oldLast)
+ oldLast->_tryUnuseVar(var);
+ break;
+ }
+}
+
+CompilerItem* X86CompilerHint::translate(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+ X86CompilerVar* var = getVar();
+
+ switch (_hintId)
+ {
+ case kVarHintAlloc:
+ x86Context.allocVar(var, _hintValue, kVarAllocRead);
+ break;
+
+ case kVarHintSpill:
+ if (var->state == kVarStateReg)
+ x86Context.spillVar(var);
+ break;
+
+ case kVarHintSave:
+ case kVarHintSaveAndUnuse:
+ if (var->state == kVarStateReg && var->changed)
+ {
+ x86Context.emitSaveVar(var, var->regIndex);
+ var->changed = false;
+ }
+ if (_hintId == kVarHintSaveAndUnuse)
+ goto _Unuse;
+ break;
+
+ case kVarHintUnuse:
+_Unuse:
+ x86Context.unuseVar(var, kVarStateUnused);
+ goto _End;
+ }
+
+ x86Context._unuseVarOnEndOfScope(this, var);
+
+_End:
+ return translated();
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerHint - Misc]
+// ============================================================================
+
+int X86CompilerHint::getMaxSize() const
+{
+ // Compiler hint is NOP, but it can generate other items which can do
+ // something - in such more items are added into the stream so we don't need
+ // to worry about this.
+ return 0;
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerInst - Construction / Destruction]
+// ============================================================================
+
+X86CompilerInst::X86CompilerInst(X86Compiler* x86Compiler, uint32_t code, Operand* opData, uint32_t opCount) :
+ CompilerInst(x86Compiler, code, opData, opCount)
+{
+ uint32_t i;
+
+ _memOp = nullptr;
+ _vars = nullptr;
+ _variablesCount = 0;
+
+ for (i = 0; i < opCount; i++)
+ {
+ if (_operands[i].isMem())
+ {
+ _memOp = reinterpret_cast<Mem*>(&_operands[i]);
+ break;
+ }
+ }
+
+ const X86InstInfo* info = &x86InstInfo[_code];
+
+ if (info->isSpecial())
+ setInstFlag(kX86CompilerInstFlagIsSpecial);
+ if (info->isFpu())
+ setInstFlag(kX86CompilerInstFlagIsFpu);
+
+ if (isSpecial())
+ {
+ // ${SPECIAL_INSTRUCTION_HANDLING_BEGIN}
+ switch (_code)
+ {
+ case kX86InstCpuId:
+ // Special...
+ break;
+
+ case kX86InstCbw:
+ case kX86InstCdq:
+ case kX86InstCdqe:
+ case kX86InstCwd:
+ case kX86InstCwde:
+ case kX86InstCqo:
+ // Special...
+ break;
+
+ case kX86InstCmpXCHG:
+ case kX86InstCmpXCHG8B:
+#if defined(ASMJIT_X64)
+ case kX86InstCmpXCHG16B:
+#endif // ASMJIT_X64
+ // Special...
+ break;
+
+#if defined(ASMJIT_X86)
+ case kX86InstDaa:
+ case kX86InstDas:
+ // Special...
+ break;
+#endif // ASMJIT_X86
+
+ case kX86InstIMul:
+ switch (_operandsCount)
+ {
+ case 2:
+ // IMUL dst, src is not special instruction.
+ clearInstFlag(kX86CompilerInstFlagIsSpecial);
+ break;
+ case 3:
+ // Only IMUL dst_hi, dst_lo, reg/mem is special, all others don't.
+ if (!(_operands[0].isVar() && _operands[1].isVar() && _operands[2].isVarMem()))
+ clearInstFlag(kX86CompilerInstFlagIsSpecial);
+ break;
+ }
+ break;
+ case kX86InstMul:
+ case kX86InstIDiv:
+ case kX86InstDiv:
+ // Special...
+ break;
+
+ case kX86InstMovPtr:
+ // Special...
+ break;
+
+ case kX86InstLahf:
+ case kX86InstSahf:
+ // Special...
+ break;
+
+ case kX86InstMaskMovQ:
+ case kX86InstMaskMovDQU:
+ // Special...
+ break;
+
+ case kX86InstEnter:
+ case kX86InstLeave:
+ // Special...
+ break;
+
+ case kX86InstRet:
+ // Special...
+ break;
+
+ case kX86InstMonitor:
+ case kX86InstMWait:
+ // Special...
+ break;
+
+ case kX86InstPop:
+ case kX86InstPopAD:
+ case kX86InstPopFD:
+ case kX86InstPopFQ:
+ // Special...
+ break;
+
+ case kX86InstPush:
+ case kX86InstPushAD:
+ case kX86InstPushFD:
+ case kX86InstPushFQ:
+ // Special...
+ break;
+
+ case kX86InstRcl:
+ case kX86InstRcr:
+ case kX86InstRol:
+ case kX86InstRor:
+ case kX86InstSal:
+ case kX86InstSar:
+ case kX86InstShl:
+ case kX86InstShr:
+ // Rot instruction is special only if last operand is variable (register).
+ if (!_operands[1].isVar())
+ clearInstFlag(kX86CompilerInstFlagIsSpecial);
+ break;
+
+ case kX86InstShld:
+ case kX86InstShrd:
+ // Shld/Shrd instruction is special only if last operand is variable (register).
+ if (!_operands[2].isVar())
+ clearInstFlag(kX86CompilerInstFlagIsSpecial);
+ break;
+
+ case kX86InstRdtsc:
+ case kX86InstRdtscP:
+ // Special...
+ break;
+
+ case kX86InstRepLodSB:
+ case kX86InstRepLodSD:
+ case kX86InstRepLodSQ:
+ case kX86InstRepLodSW:
+ case kX86InstRepMovSB:
+ case kX86InstRepMovSD:
+ case kX86InstRepMovSQ:
+ case kX86InstRepMovSW:
+ case kX86InstRepStoSB:
+ case kX86InstRepStoSD:
+ case kX86InstRepStoSQ:
+ case kX86InstRepStoSW:
+ case kX86InstRepECmpSB:
+ case kX86InstRepECmpSD:
+ case kX86InstRepECmpSQ:
+ case kX86InstRepECmpSW:
+ case kX86InstRepEScaSB:
+ case kX86InstRepEScaSD:
+ case kX86InstRepEScaSQ:
+ case kX86InstRepEScaSW:
+ case kX86InstRepNECmpSB:
+ case kX86InstRepNECmpSD:
+ case kX86InstRepNECmpSQ:
+ case kX86InstRepNECmpSW:
+ case kX86InstRepNEScaSB:
+ case kX86InstRepNEScaSD:
+ case kX86InstRepNEScaSQ:
+ case kX86InstRepNEScaSW:
+ // Special...
+ break;
+
+ default:
+ ASMJIT_ASSERT(0);
+ }
+ // ${SPECIAL_INSTRUCTION_HANDLING_END}
+ }
+}
+
+X86CompilerInst::~X86CompilerInst()
+{
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerInst - Interface]
+// ============================================================================
+
+void X86CompilerInst::prepare(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+ X86Compiler* x86Compiler = getCompiler();
+
+#define __GET_VARIABLE(__vardata__) \
+ { \
+ X86CompilerVar* _candidate = __vardata__; \
+ \
+ for (var = cur; ;) \
+ { \
+ if (var == _vars) \
+ { \
+ var = cur++; \
+ var->vdata = _candidate; \
+ var->vflags = 0; \
+ var->regMask = 0xFFFFFFFF; \
+ break; \
+ } \
+ \
+ var--; \
+ \
+ if (var->vdata == _candidate) \
+ { \
+ break; \
+ } \
+ } \
+ \
+ ASMJIT_ASSERT(!!var); \
+ }
+
+ _offset = x86Context._currentOffset;
+
+ const X86InstInfo* id = &x86InstInfo[_code];
+
+ uint32_t i, len = _operandsCount;
+ uint32_t variablesCount = 0;
+
+ for (i = 0; i < len; i++)
+ {
+ Operand& o = _operands[i];
+
+ if (o.isVar())
+ {
+ ASMJIT_ASSERT(o.getId() != kInvalidValue);
+ X86CompilerVar* vdata = x86Compiler->_getVar(o.getId());
+ ASMJIT_ASSERT(!!vdata);
+
+ if (reinterpret_cast<Var*>(&o)->isGpVar())
+ {
+ if (reinterpret_cast<GpVar*>(&o)->isGpbLo()) { setInstFlag(kX86CompilerInstFlagIsGpbLoUsed); vdata->regGpbLoCount++; };
+ if (reinterpret_cast<GpVar*>(&o)->isGpbHi()) { setInstFlag(kX86CompilerInstFlagIsGpbHiUsed); vdata->regGpbHiCount++; };
+ }
+
+ if (vdata->workOffset != _offset)
+ {
+ if (!x86Context._isActive(vdata)) x86Context._addActive(vdata);
+
+ vdata->workOffset = _offset;
+ variablesCount++;
+ }
+ }
+ else if (o.isMem())
+ {
+ if ((o.getId() & kOperandIdTypeMask) == kOperandIdTypeVar)
+ {
+ X86CompilerVar* vdata = x86Compiler->_getVar(o.getId());
+ ASMJIT_ASSERT(!!vdata);
+
+ x86Context._markMemoryUsed(vdata);
+
+ if (vdata->workOffset != _offset)
+ {
+ if (!x86Context._isActive(vdata)) x86Context._addActive(vdata);
+
+ vdata->workOffset = _offset;
+ variablesCount++;
+ }
+ }
+ else if ((o._mem.base & kOperandIdTypeMask) == kOperandIdTypeVar)
+ {
+ X86CompilerVar* vdata = x86Compiler->_getVar(o._mem.base);
+ ASMJIT_ASSERT(!!vdata);
+
+ if (vdata->workOffset != _offset)
+ {
+ if (!x86Context._isActive(vdata)) x86Context._addActive(vdata);
+
+ vdata->workOffset = _offset;
+ variablesCount++;
+ }
+ }
+
+ if ((o._mem.index & kOperandIdTypeMask) == kOperandIdTypeVar)
+ {
+ X86CompilerVar* vdata = x86Compiler->_getVar(o._mem.index);
+ ASMJIT_ASSERT(!!vdata);
+
+ if (vdata->workOffset != _offset)
+ {
+ if (!x86Context._isActive(vdata)) x86Context._addActive(vdata);
+
+ vdata->workOffset = _offset;
+ variablesCount++;
+ }
+ }
+ }
+ }
+
+ if (!variablesCount)
+ {
+ x86Context._currentOffset++;
+ return;
+ }
+
+ _vars = reinterpret_cast<VarAllocRecord*>(x86Compiler->getZoneMemory().alloc(sizeof(VarAllocRecord) * variablesCount));
+ if (!_vars)
+ {
+ x86Compiler->setError(kErrorNoHeapMemory);
+ x86Context._currentOffset++;
+ return;
+ }
+
+ _variablesCount = variablesCount;
+
+ VarAllocRecord* cur = _vars;
+ VarAllocRecord* var = nullptr;
+
+ bool _isGpbUsed = hasInstFlag(kX86CompilerInstFlagIsGpbLoUsed) |
+ hasInstFlag(kX86CompilerInstFlagIsGpbHiUsed) ;
+ uint32_t gpRestrictMask = IntUtil::maskUpToIndex(kX86RegNumGp);
+
+#if defined(ASMJIT_X64)
+ if (hasInstFlag(kX86CompilerInstFlagIsGpbHiUsed))
+ {
+ gpRestrictMask &= IntUtil::maskFromIndex(kX86RegIndexEax) |
+ IntUtil::maskFromIndex(kX86RegIndexEbx) |
+ IntUtil::maskFromIndex(kX86RegIndexEcx) |
+ IntUtil::maskFromIndex(kX86RegIndexEdx) |
+ IntUtil::maskFromIndex(kX86RegIndexEbp) |
+ IntUtil::maskFromIndex(kX86RegIndexEsi) |
+ IntUtil::maskFromIndex(kX86RegIndexEdi) ;
+ }
+#endif // ASMJIT_X64
+
+ for (i = 0; i < len; i++)
+ {
+ Operand& o = _operands[i];
+
+ if (o.isVar())
+ {
+ X86CompilerVar* vdata = x86Compiler->_getVar(o.getId());
+ ASMJIT_ASSERT(!!vdata);
+
+ __GET_VARIABLE(vdata)
+ var->vflags |= kVarAllocRegister;
+
+ if (_isGpbUsed)
+ {
+#if defined(ASMJIT_X86)
+ if (reinterpret_cast<GpVar*>(&o)->isGpb())
+ {
+ var->regMask &= IntUtil::maskFromIndex(kX86RegIndexEax) |
+ IntUtil::maskFromIndex(kX86RegIndexEbx) |
+ IntUtil::maskFromIndex(kX86RegIndexEcx) |
+ IntUtil::maskFromIndex(kX86RegIndexEdx) ;
+ }
+#else
+ // Restrict all BYTE registers to RAX/RBX/RCX/RDX if HI BYTE register
+ // is used (REX prefix makes HI BYTE addressing unencodable).
+ if (hasInstFlag(kX86CompilerInstFlagIsGpbHiUsed))
+ {
+ if (reinterpret_cast<GpVar*>(&o)->isGpb())
+ {
+ var->regMask &= IntUtil::maskFromIndex(kX86RegIndexEax) |
+ IntUtil::maskFromIndex(kX86RegIndexEbx) |
+ IntUtil::maskFromIndex(kX86RegIndexEcx) |
+ IntUtil::maskFromIndex(kX86RegIndexEdx) ;
+ }
+ }
+#endif // ASMJIT_X86/X64
+ }
+
+ if (isSpecial())
+ {
+ // ${SPECIAL_INSTRUCTION_HANDLING_BEGIN}
+ switch (_code)
+ {
+ case kX86InstCpuId:
+ switch (i)
+ {
+ case 0:
+ vdata->regRwCount++;
+ var->vflags |= kVarAllocReadWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEax);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 1:
+ vdata->regWriteCount++;
+ var->vflags |= kVarAllocWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEbx);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 2:
+ vdata->regWriteCount++;
+ var->vflags |= kVarAllocWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEcx);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 3:
+ vdata->regWriteCount++;
+ var->vflags |= kVarAllocWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEdx);
+ gpRestrictMask &= ~var->regMask;
+ break;
+
+ default:
+ ASMJIT_ASSERT(0);
+ }
+ break;
+
+ case kX86InstCbw:
+ case kX86InstCdqe:
+ case kX86InstCwde:
+ switch (i)
+ {
+ case 0:
+ vdata->regRwCount++;
+ var->vflags |= kVarAllocReadWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEax);
+ gpRestrictMask &= ~var->regMask;
+ break;
+
+ default:
+ ASMJIT_ASSERT(0);
+ }
+ break;
+
+ case kX86InstCdq:
+ case kX86InstCwd:
+ case kX86InstCqo:
+ switch (i)
+ {
+ case 0:
+ vdata->regWriteCount++;
+ var->vflags |= kVarAllocWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEdx);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 1:
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEax);
+ gpRestrictMask &= ~var->regMask;
+ break;
+
+ default:
+ ASMJIT_ASSERT(0);
+ }
+ break;
+
+ case kX86InstCmpXCHG:
+ switch (i)
+ {
+ case 0:
+ vdata->regRwCount++;
+ var->vflags |= kVarAllocReadWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEax);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 1:
+ vdata->regRwCount++;
+ var->vflags |= kVarAllocReadWrite;
+ break;
+ case 2:
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead;
+ break;
+
+ default:
+ ASMJIT_ASSERT(0);
+ }
+ break;
+
+ case kX86InstCmpXCHG8B:
+#if defined(ASMJIT_X64)
+ case kX86InstCmpXCHG16B:
+#endif // ASMJIT_X64
+ switch (i)
+ {
+ case 0:
+ vdata->regRwCount++;
+ var->vflags |= kVarAllocReadWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEdx);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 1:
+ vdata->regRwCount++;
+ var->vflags |= kVarAllocReadWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEax);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 2:
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEcx);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 3:
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEbx);
+ gpRestrictMask &= ~var->regMask;
+ break;
+
+ default:
+ ASMJIT_ASSERT(0);
+ }
+ break;
+
+#if defined(ASMJIT_X86)
+ case kX86InstDaa:
+ case kX86InstDas:
+ ASMJIT_ASSERT(!i);
+ vdata->regRwCount++;
+ var->vflags |= kVarAllocReadWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEax);
+ gpRestrictMask &= ~var->regMask;
+ break;
+#endif // ASMJIT_X86
+
+ case kX86InstIMul:
+ case kX86InstMul:
+ case kX86InstIDiv:
+ case kX86InstDiv:
+ switch (i)
+ {
+ case 0:
+ vdata->regWriteCount++;
+ var->vflags |= kVarAllocWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEdx);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 1:
+ vdata->regRwCount++;
+ var->vflags |= kVarAllocReadWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEax);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 2:
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead;
+ break;
+
+ default:
+ ASMJIT_ASSERT(0);
+ }
+ break;
+
+ case kX86InstMovPtr:
+ switch (i)
+ {
+ case 0:
+ vdata->regWriteCount++;
+ var->vflags |= kVarAllocWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEax);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 1:
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEax);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ default:
+ ASMJIT_ASSERT(0);
+ }
+ break;
+
+ case kX86InstLahf:
+ ASMJIT_ASSERT(!i);
+ vdata->regWriteCount++;
+ var->vflags |= kVarAllocWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEax);
+ gpRestrictMask &= ~var->regMask;
+ break;
+
+ case kX86InstSahf:
+ ASMJIT_ASSERT(!i);
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEax);
+ gpRestrictMask &= ~var->regMask;
+ break;
+
+ case kX86InstMaskMovQ:
+ case kX86InstMaskMovDQU:
+ switch (i)
+ {
+ case 0:
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEdi);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 1:
+ case 2:
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead;
+ break;
+ }
+ break;
+
+ case kX86InstEnter:
+ case kX86InstLeave:
+ // TODO: SPECIAL INSTRUCTION.
+ break;
+
+ case kX86InstRet:
+ // TODO: SPECIAL INSTRUCTION.
+ break;
+
+ case kX86InstMonitor:
+ case kX86InstMWait:
+ // TODO: MONITOR/MWAIT (COMPILER).
+ break;
+
+ case kX86InstPop:
+ // TODO: SPECIAL INSTRUCTION.
+ break;
+
+ case kX86InstPopAD:
+ case kX86InstPopFD:
+ case kX86InstPopFQ:
+ // TODO: SPECIAL INSTRUCTION.
+ break;
+
+ case kX86InstPush:
+ // TODO: SPECIAL INSTRUCTION.
+ break;
+
+ case kX86InstPushAD:
+ case kX86InstPushFD:
+ case kX86InstPushFQ:
+ // TODO: SPECIAL INSTRUCTION.
+ break;
+
+ case kX86InstRcl:
+ case kX86InstRcr:
+ case kX86InstRol:
+ case kX86InstRor:
+ case kX86InstSal:
+ case kX86InstSar:
+ case kX86InstShl:
+ case kX86InstShr:
+ switch (i)
+ {
+ case 0:
+ vdata->regRwCount++;
+ var->vflags |= kVarAllocReadWrite;
+ break;
+ case 1:
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEcx);
+ gpRestrictMask &= ~var->regMask;
+ break;
+
+ default:
+ ASMJIT_ASSERT(0);
+ }
+ break;
+
+ case kX86InstShld:
+ case kX86InstShrd:
+ switch (i)
+ {
+ case 0:
+ vdata->regRwCount++;
+ var->vflags |= kVarAllocReadWrite;
+ break;
+ case 1:
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead;
+ break;
+ case 2:
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEcx);
+ gpRestrictMask &= ~var->regMask;
+ break;
+
+ default:
+ ASMJIT_ASSERT(0);
+ }
+ break;
+
+ case kX86InstRdtsc:
+ case kX86InstRdtscP:
+ switch (i)
+ {
+ case 0:
+ vdata->regWriteCount++;
+ var->vflags |= kVarAllocWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEdx);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 1:
+ vdata->regWriteCount++;
+ var->vflags |= kVarAllocWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEax);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 2:
+ ASMJIT_ASSERT(_code == kX86InstRdtscP);
+ vdata->regWriteCount++;
+ var->vflags |= kVarAllocWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEcx);
+ gpRestrictMask &= ~var->regMask;
+ break;
+
+ default:
+ ASMJIT_ASSERT(0);
+ }
+ break;
+
+ case kX86InstRepLodSB:
+ case kX86InstRepLodSD:
+ case kX86InstRepLodSQ:
+ case kX86InstRepLodSW:
+ switch (i)
+ {
+ case 0:
+ vdata->regWriteCount++;
+ var->vflags |= kVarAllocWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEax);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 1:
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEsi);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 2:
+ vdata->regRwCount++;
+ var->vflags |= kVarAllocReadWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEcx);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ default:
+ ASMJIT_ASSERT(0);
+ }
+ break;
+
+ case kX86InstRepMovSB:
+ case kX86InstRepMovSD:
+ case kX86InstRepMovSQ:
+ case kX86InstRepMovSW:
+ case kX86InstRepECmpSB:
+ case kX86InstRepECmpSD:
+ case kX86InstRepECmpSQ:
+ case kX86InstRepECmpSW:
+ case kX86InstRepNECmpSB:
+ case kX86InstRepNECmpSD:
+ case kX86InstRepNECmpSQ:
+ case kX86InstRepNECmpSW:
+ switch (i)
+ {
+ case 0:
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEdi);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 1:
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEsi);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 2:
+ vdata->regRwCount++;
+ var->vflags |= kVarAllocReadWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEcx);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ default:
+ ASMJIT_ASSERT(0);
+ }
+ break;
+
+ case kX86InstRepStoSB:
+ case kX86InstRepStoSD:
+ case kX86InstRepStoSQ:
+ case kX86InstRepStoSW:
+ switch (i)
+ {
+ case 0:
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEdi);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 1:
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEax);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 2:
+ vdata->regRwCount++;
+ var->vflags |= kVarAllocReadWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEcx);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ default:
+ ASMJIT_ASSERT(0);
+ }
+ break;
+
+ case kX86InstRepEScaSB:
+ case kX86InstRepEScaSD:
+ case kX86InstRepEScaSQ:
+ case kX86InstRepEScaSW:
+ case kX86InstRepNEScaSB:
+ case kX86InstRepNEScaSD:
+ case kX86InstRepNEScaSQ:
+ case kX86InstRepNEScaSW:
+ switch (i)
+ {
+ case 0:
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEdi);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 1:
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEax);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ case 2:
+ vdata->regRwCount++;
+ var->vflags |= kVarAllocReadWrite | kVarAllocSpecial;
+ var->regMask = IntUtil::maskFromIndex(kX86RegIndexEcx);
+ gpRestrictMask &= ~var->regMask;
+ break;
+ default:
+ ASMJIT_ASSERT(0);
+ }
+ break;
+
+ default:
+ ASMJIT_ASSERT(0);
+ }
+ // ${SPECIAL_INSTRUCTION_HANDLING_END}
+ }
+ else
+ {
+ if (!i)
+ {
+ // CMP/TEST instruction.
+ if (id->getCode() == kX86InstCmp || id->getCode() == kX86InstTest)
+ {
+ // Read-only case.
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead;
+ }
+ // CVTTSD2SI/CVTTSS2SI instructions.
+ else if (id->getCode() == kX86InstCvttSD2SI || id->getCode() == kX86InstCvttSS2SI)
+ {
+ // In 32-bit mode the whole destination is replaced. In 64-bit mode
+ // we need to check whether the destination operand size is 64-bits.
+#if defined(ASMJIT_X64)
+ if (_operands[0].isRegType(kX86RegTypeGpq))
+ {
+#endif // ASMJIT_X64
+ // Write-only case.
+ vdata->regWriteCount++;
+ var->vflags |= kVarAllocWrite;
+#if defined(ASMJIT_X64)
+ }
+ else
+ {
+ // Read/Write.
+ vdata->regRwCount++;
+ var->vflags |= kVarAllocReadWrite;
+ }
+#endif // ASMJIT_X64
+ }
+ // MOV/MOVSS/MOVSD instructions.
+ //
+ // If instruction is MOV (source replaces the destination) or
+ // MOVSS/MOVSD and source operand is memory location then register
+ // allocator should know that previous destination value is lost
+ // (write only operation).
+ else if ((id->isMov()) ||
+ ((id->getCode() == kX86InstMovSS || id->getCode() == kX86InstMovSD) /* && _operands[1].isMem() */) ||
+ (id->getCode() == kX86InstIMul && _operandsCount == 3 && !isSpecial()))
+ {
+ // Write-only case.
+ vdata->regWriteCount++;
+ var->vflags |= kVarAllocWrite;
+ }
+ else if (id->getCode() == kX86InstLea)
+ {
+ // Write.
+ vdata->regWriteCount++;
+ var->vflags |= kVarAllocWrite;
+ }
+ else
+ {
+ // Read/Write.
+ vdata->regRwCount++;
+ var->vflags |= kVarAllocReadWrite;
+ }
+ }
+ else
+ {
+ // Second, third, ... operands are read-only.
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRead;
+ }
+
+ if (!_memOp && i < 2 && (id->_opFlags[i] & kX86InstOpMem))
+ {
+ var->vflags |= kVarAllocMem;
+ }
+ }
+
+ // If variable must be in specific register we could add some hint to allocator.
+ if (var->vflags & kVarAllocSpecial)
+ {
+ vdata->prefRegisterMask |= var->regMask;
+ x86Context._newRegisterHomeIndex(vdata, IntUtil::findFirstBit(var->regMask));
+ }
+ }
+ else if (o.isMem())
+ {
+ if ((o.getId() & kOperandIdTypeMask) == kOperandIdTypeVar)
+ {
+ X86CompilerVar* vdata = x86Compiler->_getVar(o.getId());
+ ASMJIT_ASSERT(!!vdata);
+
+ __GET_VARIABLE(vdata)
+
+ if (!i)
+ {
+ // If variable is MOV instruction type (source replaces the destination)
+ // or variable is MOVSS/MOVSD instruction then register allocator should
+ // know that previous destination value is lost (write only operation).
+ if (id->isMov() || ((id->getCode() == kX86InstMovSS || id->getCode() == kX86InstMovSD)))
+ {
+ // Write only case.
+ vdata->memWriteCount++;
+ }
+ else
+ {
+ vdata->memRwCount++;
+ }
+ }
+ else
+ {
+ vdata->memReadCount++;
+ }
+ }
+ else if ((o._mem.base & kOperandIdTypeMask) == kOperandIdTypeVar)
+ {
+ X86CompilerVar* vdata = x86Compiler->_getVar(reinterpret_cast<Mem&>(o).getBase());
+ ASMJIT_ASSERT(!!vdata);
+
+ __GET_VARIABLE(vdata)
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRegister | kVarAllocRead;
+ var->regMask &= gpRestrictMask;
+ }
+
+ if ((o._mem.index & kOperandIdTypeMask) == kOperandIdTypeVar)
+ {
+ X86CompilerVar* vdata = x86Compiler->_getVar(reinterpret_cast<Mem&>(o).getIndex());
+ ASMJIT_ASSERT(!!vdata);
+
+ __GET_VARIABLE(vdata)
+ vdata->regReadCount++;
+ var->vflags |= kVarAllocRegister | kVarAllocRead;
+ var->regMask &= gpRestrictMask;
+ }
+ }
+ }
+
+ // Traverse all variables and update firstItem / lastItem. This
+ // function is called from iterator that scans items using forward
+ // direction so we can use this knowledge to optimize the process.
+ //
+ // Similar to X86CompilerFuncCall::prepare().
+ for (i = 0; i < _variablesCount; i++)
+ {
+ X86CompilerVar* v = _vars[i].vdata;
+
+ // Update GP register allocator restrictions.
+ if (X86Util::isVarTypeInt(v->getType()))
+ {
+ if (_vars[i].regMask == 0xFFFFFFFF) _vars[i].regMask &= gpRestrictMask;
+ }
+
+ // Update first/last item (begin of variable scope).
+ if (!v->firstItem) v->firstItem = this;
+ v->lastItem = this;
+ }
+
+ // There are some instructions that can be used to clear or to set all bits
+ // in a register:
+ //
+ // - andn reg, reg ; Set all bits in reg to 0.
+ // - xor/pxor reg, reg ; Set all bits in reg to 0.
+ // - sub/psub reg, reg ; Set all bits in reg to 0.
+ // - pcmpgt reg, reg ; Set all bits in reg to 0.
+ // - pcmpeq reg, reg ; Set all bits in reg to 1.
+ //
+ // There are also combinations which do nothing:
+ //
+ // - and reg, reg ; Nop.
+ // - or reg, reg ; Nop.
+ // - xchg reg, reg ; Nop.
+
+ if (_variablesCount == 1 && _operandsCount > 1 && _operands[0].isVar() && _operands[1].isVar() && !_memOp)
+ {
+ switch (_code)
+ {
+ // ----------------------------------------------------------------------
+ // [Zeros/Ones]
+ // ----------------------------------------------------------------------
+
+ // ANDN Instructions.
+ case kX86InstPAndN:
+
+ // XOR Instructions.
+ case kX86InstXor:
+ case kX86InstXorPD:
+ case kX86InstXorPS:
+ case kX86InstPXor:
+
+ // SUB Instructions.
+ case kX86InstSub:
+ case kX86InstPSubB:
+ case kX86InstPSubW:
+ case kX86InstPSubD:
+ case kX86InstPSubQ:
+ case kX86InstPSubSB:
+ case kX86InstPSubSW:
+ case kX86InstPSubUSB:
+ case kX86InstPSubUSW:
+
+ // PCMPEQ Instructions.
+ case kX86InstPCmpEqB:
+ case kX86InstPCmpEqW:
+ case kX86InstPCmpEqD:
+ case kX86InstPCmpEqQ:
+
+ // PCMPGT Instructions.
+ case kX86InstPCmpGtB:
+ case kX86InstPCmpGtW:
+ case kX86InstPCmpGtD:
+ case kX86InstPCmpGtQ:
+ // Clear the read flag. This prevents variable alloc/spill.
+ _vars[0].vflags = kVarAllocWrite;
+ _vars[0].vdata->regReadCount--;
+ break;
+
+ // ----------------------------------------------------------------------
+ // [Nop]
+ // ----------------------------------------------------------------------
+
+ // AND Instructions.
+ case kX86InstAnd:
+ case kX86InstAndPD:
+ case kX86InstAndPS:
+ case kX86InstPAnd:
+
+ // OR Instructions.
+ case kX86InstOr:
+ case kX86InstOrPD:
+ case kX86InstOrPS:
+ case kX86InstPOr:
+
+ // XCHG Instruction.
+ case kX86InstXchg:
+
+ // Clear the write flag.
+ _vars[0].vflags = kVarAllocRead;
+ _vars[0].vdata->regWriteCount--;
+ break;
+ }
+ }
+ x86Context._currentOffset++;
+
+#undef __GET_VARIABLE
+}
+
+CompilerItem* X86CompilerInst::translate(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+ X86Compiler* x86Compiler = getCompiler();
+
+ uint32_t i;
+ uint32_t variablesCount = _variablesCount;
+
+ if (variablesCount > 0)
+ {
+ // These variables are used by the instruction and we set current offset
+ // to their work offsets -> getSpillCandidate never return the variable
+ // used this instruction.
+ for (i = 0; i < variablesCount; i++)
+ {
+ _vars[i].vdata->workOffset = x86Context._currentOffset;
+ }
+
+ // Alloc variables used by the instruction (special first).
+ for (i = 0; i < variablesCount; i++)
+ {
+ VarAllocRecord& r = _vars[i];
+ // Alloc variables with specific register first.
+ if (r.vflags & kVarAllocSpecial)
+ x86Context.allocVar(r.vdata, r.regMask, r.vflags);
+ }
+
+ for (i = 0; i < variablesCount; i++)
+ {
+ VarAllocRecord& r = _vars[i];
+ // Alloc variables without specific register last.
+ if (!(r.vflags & kVarAllocSpecial))
+ x86Context.allocVar(r.vdata, r.regMask, r.vflags);
+ }
+
+ x86Context.translateOperands(_operands, _operandsCount);
+ }
+
+ if (_memOp && (_memOp->getId() & kOperandIdTypeMask) == kOperandIdTypeVar)
+ {
+ X86CompilerVar* cv = x86Compiler->_getVar(_memOp->getId());
+ ASMJIT_ASSERT(!!cv);
+
+ switch (cv->state)
+ {
+ case kVarStateUnused:
+ cv->state = kVarStateMem;
+ break;
+ case kVarStateReg:
+ cv->changed = false;
+ x86Context.unuseVar(cv, kVarStateMem);
+ break;
+ }
+ }
+
+ for (i = 0; i < variablesCount; i++)
+ {
+ x86Context._unuseVarOnEndOfScope(this, &_vars[i]);
+ }
+
+ return translated();
+}
+
+void X86CompilerInst::emit(Assembler& a)
+{
+ X86Assembler& x86Asm = static_cast<X86Assembler&>(a);
+
+ x86Asm._inlineComment = _comment;
+ x86Asm._emitOptions = _emitOptions;
+
+ if (isSpecial())
+ {
+ // ${SPECIAL_INSTRUCTION_HANDLING_BEGIN}
+ switch (_code)
+ {
+ case kX86InstCpuId:
+ x86Asm._emitInstruction(_code);
+ return;
+
+ case kX86InstCbw:
+ case kX86InstCdq:
+ case kX86InstCdqe:
+ case kX86InstCwd:
+ case kX86InstCwde:
+ case kX86InstCqo:
+ x86Asm._emitInstruction(_code);
+ return;
+
+ case kX86InstCmpXCHG:
+ x86Asm._emitInstruction(_code, &_operands[1], &_operands[2]);
+ return;
+
+ case kX86InstCmpXCHG8B:
+#if defined(ASMJIT_X64)
+ case kX86InstCmpXCHG16B:
+#endif // ASMJIT_X64
+ x86Asm._emitInstruction(_code, &_operands[4]);
+ return;
+
+#if defined(ASMJIT_X86)
+ case kX86InstDaa:
+ case kX86InstDas:
+ x86Asm._emitInstruction(_code);
+ return;
+#endif // ASMJIT_X86
+
+ case kX86InstIMul:
+ case kX86InstMul:
+ case kX86InstIDiv:
+ case kX86InstDiv:
+ // INST dst_lo (implicit), dst_hi (implicit), src (explicit)
+ ASMJIT_ASSERT(_operandsCount == 3);
+ x86Asm._emitInstruction(_code, &_operands[2]);
+ return;
+
+ case kX86InstMovPtr:
+ break;
+
+ case kX86InstLahf:
+ case kX86InstSahf:
+ x86Asm._emitInstruction(_code);
+ return;
+
+ case kX86InstMaskMovQ:
+ case kX86InstMaskMovDQU:
+ x86Asm._emitInstruction(_code, &_operands[1], &_operands[2]);
+ return;
+
+ case kX86InstEnter:
+ case kX86InstLeave:
+ // TODO: SPECIAL INSTRUCTION.
+ break;
+
+ case kX86InstRet:
+ // TODO: SPECIAL INSTRUCTION.
+ break;
+
+ case kX86InstMonitor:
+ case kX86InstMWait:
+ // TODO: MONITOR/MWAIT (COMPILER).
+ break;
+
+ case kX86InstPop:
+ case kX86InstPopAD:
+ case kX86InstPopFD:
+ case kX86InstPopFQ:
+ // TODO: SPECIAL INSTRUCTION.
+ break;
+
+ case kX86InstPush:
+ case kX86InstPushAD:
+ case kX86InstPushFD:
+ case kX86InstPushFQ:
+ // TODO: SPECIAL INSTRUCTION.
+ break;
+
+ case kX86InstRcl:
+ case kX86InstRcr:
+ case kX86InstRol:
+ case kX86InstRor:
+ case kX86InstSal:
+ case kX86InstSar:
+ case kX86InstShl:
+ case kX86InstShr:
+ x86Asm._emitInstruction(_code, &_operands[0], &cl);
+ return;
+
+ case kX86InstShld:
+ case kX86InstShrd:
+ x86Asm._emitInstruction(_code, &_operands[0], &_operands[1], &cl);
+ return;
+
+ case kX86InstRdtsc:
+ case kX86InstRdtscP:
+ x86Asm._emitInstruction(_code);
+ return;
+
+ case kX86InstRepLodSB:
+ case kX86InstRepLodSD:
+ case kX86InstRepLodSQ:
+ case kX86InstRepLodSW:
+ case kX86InstRepMovSB:
+ case kX86InstRepMovSD:
+ case kX86InstRepMovSQ:
+ case kX86InstRepMovSW:
+ case kX86InstRepStoSB:
+ case kX86InstRepStoSD:
+ case kX86InstRepStoSQ:
+ case kX86InstRepStoSW:
+ case kX86InstRepECmpSB:
+ case kX86InstRepECmpSD:
+ case kX86InstRepECmpSQ:
+ case kX86InstRepECmpSW:
+ case kX86InstRepEScaSB:
+ case kX86InstRepEScaSD:
+ case kX86InstRepEScaSQ:
+ case kX86InstRepEScaSW:
+ case kX86InstRepNECmpSB:
+ case kX86InstRepNECmpSD:
+ case kX86InstRepNECmpSQ:
+ case kX86InstRepNECmpSW:
+ case kX86InstRepNEScaSB:
+ case kX86InstRepNEScaSD:
+ case kX86InstRepNEScaSQ:
+ case kX86InstRepNEScaSW:
+ x86Asm._emitInstruction(_code);
+ return;
+
+ default:
+ ASMJIT_ASSERT(0);
+ }
+ // ${SPECIAL_INSTRUCTION_HANDLING_END}
+ }
+
+ switch (_operandsCount)
+ {
+ case 0:
+ x86Asm._emitInstruction(_code);
+ break;
+ case 1:
+ x86Asm._emitInstruction(_code, &_operands[0]);
+ break;
+ case 2:
+ x86Asm._emitInstruction(_code, &_operands[0], &_operands[1]);
+ break;
+ case 3:
+ x86Asm._emitInstruction(_code, &_operands[0], &_operands[1], &_operands[2]);
+ break;
+ default:
+ ASMJIT_ASSERT(0);
+ break;
+ }
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerInst - Misc]
+// ============================================================================
+
+int X86CompilerInst::getMaxSize() const
+{
+ // TODO: Instruction max size.
+ return 15;
+}
+
+bool X86CompilerInst::_tryUnuseVar(CompilerVar* _v)
+{
+ X86CompilerVar* cv = static_cast<X86CompilerVar*>(_v);
+
+ for (uint32_t i = 0; i < _variablesCount; i++)
+ {
+ if (_vars[i].vdata == cv)
+ {
+ _vars[i].vflags |= kVarAllocUnuseAfterUse;
+ return true;
+ }
+ }
+
+ return false;
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerJmpInst - Construction / Destruction]
+// ============================================================================
+
+X86CompilerJmpInst::X86CompilerJmpInst(X86Compiler* x86Compiler, uint32_t code, Operand* opData, uint32_t opCount) :
+ X86CompilerInst(x86Compiler, code, opData, opCount)
+{
+ _jumpTarget = x86Compiler->_getTarget(_operands[0].getId());
+ _jumpTarget->_jumpsCount++;
+
+ _jumpNext = static_cast<X86CompilerJmpInst*>(_jumpTarget->_from);
+ _jumpTarget->_from = this;
+
+ // The 'jmp' is always taken, conditional jump can contain hint, we detect it.
+ if (getCode() == kX86InstJmp)
+ setInstFlag(kX86CompilerInstFlagIsTaken);
+ else if (opCount > 1 && opData[1].isImm() && reinterpret_cast<Imm*>(&opData[1])->getValue() == kCondHintLikely)
+ setInstFlag(kX86CompilerInstFlagIsTaken);
+}
+
+X86CompilerJmpInst::~X86CompilerJmpInst()
+{
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerJmpInst - Interface]
+// ============================================================================
+
+void X86CompilerJmpInst::prepare(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+ _offset = x86Context._currentOffset;
+
+ // Update _isTaken to true if this is conditional backward jump. This behavior
+ // can be overridden by using kCondHintUnlikely when using the instruction.
+ if (getCode() != kX86InstJmp && _operandsCount == 1 && _jumpTarget->getOffset() < getOffset())
+ {
+ setInstFlag(kX86CompilerInstFlagIsTaken);
+ }
+
+ // Now patch all variables where jump location is in the active range.
+ if (_jumpTarget->getOffset() != kInvalidValue && x86Context._active)
+ {
+ X86CompilerVar* first = static_cast<X86CompilerVar*>(x86Context._active);
+ X86CompilerVar* var = first;
+ uint32_t jumpOffset = _jumpTarget->getOffset();
+
+ do {
+ if (var->firstItem)
+ {
+ ASMJIT_ASSERT(!!var->lastItem);
+ uint32_t start = var->firstItem->getOffset();
+ uint32_t end = var->lastItem->getOffset();
+
+ if (jumpOffset >= start && jumpOffset <= end)
+ var->lastItem = this;
+ }
+ var = var->nextActive;
+ } while (var != first);
+ }
+
+ x86Context._currentOffset++;
+}
+
+CompilerItem* X86CompilerJmpInst::translate(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+
+ // Translate using X86CompilerInst.
+ CompilerItem* ret = X86CompilerInst::translate(cc);
+
+ // We jump with item if its kX86InstJUMP (not based on condiiton) and it
+ // points into yet unknown location.
+ if (_code == kX86InstJmp && !_jumpTarget->isTranslated())
+ {
+ x86Context.addBackwardCode(this);
+ ret = _jumpTarget;
+ }
+ else
+ {
+ _state = x86Context._saveState();
+ if (_jumpTarget->isTranslated())
+ {
+ doJump(cc);
+ }
+ else
+ {
+ // State is not known, so we need to call doJump() later. Compiler will
+ // do it for us.
+ x86Context.addForwardJump(this);
+ _jumpTarget->_state = _state;
+ }
+
+ // Mark next code as unreachable, cleared by a next label (CompilerTarget).
+ if (_code == kX86InstJmp)
+ x86Context._isUnreachable = 1;
+ }
+
+ // Need to traverse over all active variables and unuse them if their scope ends
+ // here.
+ if (x86Context._active)
+ {
+ X86CompilerVar* first = static_cast<X86CompilerVar*>(x86Context._active);
+ X86CompilerVar* var = first;
+
+ do {
+ x86Context._unuseVarOnEndOfScope(this, var);
+ var = var->nextActive;
+ } while (var != first);
+ }
+
+ return ret;
+}
+
+void X86CompilerJmpInst::emit(Assembler& a)
+{
+ static const unsigned MAXIMUM_SHORT_JMP_SIZE = 127;
+
+ // Try to minimize size of jump using SHORT jump (8-bit displacement) by
+ // traversing into the target and calculating the maximum code size. We
+ // end when code size reaches MAXIMUM_SHORT_JMP_SIZE.
+ if (!(_emitOptions & kX86EmitOptionShortJump) && getJumpTarget()->getOffset() > getOffset())
+ {
+ // Calculate the code size.
+ unsigned codeSize = 0;
+ CompilerItem* cur = this->getNext();
+ CompilerItem* target = getJumpTarget();
+
+ while (cur)
+ {
+ if (cur == target)
+ {
+ // Target found, we can tell assembler to generate short form of jump.
+ _emitOptions |= kX86EmitOptionShortJump;
+ goto _End;
+ }
+
+ int s = cur->getMaxSize();
+ if (s == -1) break;
+
+ codeSize += (unsigned)s;
+ if (codeSize > MAXIMUM_SHORT_JMP_SIZE) break;
+
+ cur = cur->getNext();
+ }
+ }
+
+_End:
+ X86CompilerInst::emit(a);
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerJmpInst - DoJump]
+// ============================================================================
+
+void X86CompilerJmpInst::doJump(CompilerContext& cc)
+{
+ X86CompilerContext& x86Context = static_cast<X86CompilerContext&>(cc);
+ X86Compiler* x86Compiler = getCompiler();
+
+ // The state have to be already known. The doJump() method is called by
+ // translate() or by Compiler in case that it's forward jump.
+ ASMJIT_ASSERT(_jumpTarget->getState());
+
+ if (getCode() == kX86InstJmp || (isTaken() && _jumpTarget->getOffset() < getOffset()))
+ {
+ // Instruction type is JMP or conditional jump that should be taken (likely).
+ // We can set state here instead of jumping out, setting state and jumping
+ // to _jumpTarget.
+ //
+ // NOTE: We can't use this technique if instruction is forward conditional
+ // jump. The reason is that when generating code we can't change state here,
+ // because the next instruction depends on it.
+ x86Context._restoreState(_jumpTarget->getState(), _jumpTarget->getOffset());
+ }
+ else
+ {
+ // Instruction type is JMP or conditional jump that should be not normally
+ // taken. If we need add code that will switch between different states we
+ // add it after the end of function body (after epilog, using 'ExtraBlock').
+ CompilerItem* ext = x86Context.getExtraBlock();
+ CompilerItem* old = x86Compiler->setCurrentItem(ext);
+
+ x86Context._restoreState(_jumpTarget->getState(), _jumpTarget->getOffset());
+
+ if (x86Compiler->getCurrentItem() != ext)
+ {
+ // Add the jump to the target.
+ x86Compiler->jmp(_jumpTarget->_label);
+ ext = x86Compiler->getCurrentItem();
+
+ // The x86Context._restoreState() method emitted some instructions so we need to
+ // patch the jump.
+ Label L = x86Compiler->newLabel();
+ x86Compiler->setCurrentItem(x86Context.getExtraBlock());
+ x86Compiler->bind(L);
+
+ // Finally, patch the jump target.
+ ASMJIT_ASSERT(_operandsCount > 0);
+ _operands[0] = L; // Operand part (Label).
+ _jumpTarget = x86Compiler->_getTarget(L.getId()); // Compiler part (CompilerTarget).
+ }
+
+ x86Context.setExtraBlock(ext);
+ x86Compiler->setCurrentItem(old);
+
+ // Assign state back.
+ x86Context._assignState(static_cast<X86CompilerState*>(_state));
+ }
+}
+
+// ============================================================================
+// [AsmJit::X86CompilerJmpInst - GetJumpTarget]
+// ============================================================================
+
+CompilerTarget* X86CompilerJmpInst::getJumpTarget() const
+{
+ return _jumpTarget;
+}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86/x86compileritem.h
@@ -1,1 +1,285 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_X86_X86COMPILERITEM_H
+#define _ASMJIT_X86_X86COMPILERITEM_H
+
+// [Dependencies - AsmJit]
+#include "../x86/x86assembler.h"
+#include "../x86/x86compiler.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit {
+
+//! @addtogroup AsmJit_X86
+//! @{
+
+// ============================================================================
+// [AsmJit::X86CompilerAlign]
+// ============================================================================
+
+//! @brief Compiler align item.
+struct X86CompilerAlign : public CompilerAlign
+{
+ ASMJIT_NO_COPY(X86CompilerAlign)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref CompilerAlign instance.
+ ASMJIT_API X86CompilerAlign(X86Compiler* x86Compiler, uint32_t size = 0);
+ //! @brief Destroy the @ref CompilerAlign instance.
+ ASMJIT_API virtual ~X86CompilerAlign();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get compiler as @ref X86Compiler.
+ X86Compiler* getCompiler() const
+ { return reinterpret_cast<X86Compiler*>(_compiler); }
+
+ // --------------------------------------------------------------------------
+ // [Interface]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual void emit(Assembler& a);
+};
+
+// ============================================================================
+// [AsmJit::X86CompilerHint]
+// ============================================================================
+
+//! @brief @ref X86Compiler variable hint item.
+struct X86CompilerHint : public CompilerHint
+{
+ ASMJIT_NO_COPY(X86CompilerHint)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref X86CompilerHint instance.
+ ASMJIT_API X86CompilerHint(X86Compiler* compiler, X86CompilerVar* var, uint32_t hintId, uint32_t hintValue);
+ //! @brief Destroy the @ref X86CompilerHint instance.
+ ASMJIT_API virtual ~X86CompilerHint();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get variable as @ref X86CompilerVar.
+ X86CompilerVar* getVar() const
+ { return reinterpret_cast<X86CompilerVar*>(_var); }
+
+ // --------------------------------------------------------------------------
+ // [Interface]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual void prepare(CompilerContext& cc);
+ ASMJIT_API virtual CompilerItem* translate(CompilerContext& cc);
+
+ // --------------------------------------------------------------------------
+ // [Misc]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual int getMaxSize() const;
+};
+
+// ============================================================================
+// [AsmJit::X86CompilerTarget]
+// ============================================================================
+
+//! @brief X86Compiler target item.
+struct X86CompilerTarget : public CompilerTarget
+{
+ ASMJIT_NO_COPY(X86CompilerTarget)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref X86CompilerTarget instance.
+ ASMJIT_API X86CompilerTarget(X86Compiler* x86Compiler, const Label& target);
+ //! @brief Destroy the @ref X86CompilerTarget instance.
+ ASMJIT_API virtual ~X86CompilerTarget();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get compiler as @ref X86Compiler.
+ X86Compiler* getCompiler() const
+ { return reinterpret_cast<X86Compiler*>(_compiler); }
+
+ //! @brief Get state as @ref X86CompilerState.
+ X86CompilerState* getState() const
+ { return reinterpret_cast<X86CompilerState*>(_state); }
+
+ // --------------------------------------------------------------------------
+ // [Interface]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual void prepare(CompilerContext& cc);
+ ASMJIT_API virtual CompilerItem* translate(CompilerContext& cc);
+ ASMJIT_API virtual void emit(Assembler& a);
+};
+
+// ============================================================================
+// [AsmJit::X86CompilerInst]
+// ============================================================================
+
+//! @brief @ref X86Compiler instruction item.
+struct X86CompilerInst : public CompilerInst
+{
+ ASMJIT_NO_COPY(X86CompilerInst)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref X86CompilerInst instance.
+ ASMJIT_API X86CompilerInst(X86Compiler* x86Compiler, uint32_t code, Operand* opData, uint32_t opCount);
+ //! @brief Destroy the @ref X86CompilerInst instance.
+ ASMJIT_API virtual ~X86CompilerInst();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get compiler as @ref X86Compiler.
+ X86Compiler* getCompiler() const
+ { return reinterpret_cast<X86Compiler*>(_compiler); }
+
+ //! @brief Get whether the instruction is special.
+ bool isSpecial() const
+ { return !!(_instFlags & kX86CompilerInstFlagIsSpecial); }
+
+ //! @brief Get whether the instruction is FPU.
+ bool isFpu() const
+ { return !!(_instFlags & kX86CompilerInstFlagIsFpu); }
+
+ //! @brief Get whether the instruction is used with GpbLo register.
+ bool isGpbLoUsed() const
+ { return !!(_instFlags & kX86CompilerInstFlagIsGpbLoUsed); }
+
+ //! @brief Get whether the instruction is used with GpbHi register.
+ bool isGpbHiUsed() const
+ { return !!(_instFlags & kX86CompilerInstFlagIsGpbHiUsed); }
+
+ //! @brief Get memory operand.
+ Mem* getMemOp()
+ { return _memOp; }
+
+ //! @brief Set memory operand.
+ void setMemOp(Mem* memOp)
+ { _memOp = memOp; }
+
+ //! @brief Get operands array (3 operands total).
+ VarAllocRecord* getVars()
+ { return _vars; }
+
+ //! @brief Get operands array (3 operands total).
+ const VarAllocRecord* getVars() const
+ { return _vars; }
+
+ // --------------------------------------------------------------------------
+ // [Interface]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual void prepare(CompilerContext& cc);
+ ASMJIT_API virtual CompilerItem* translate(CompilerContext& cc);
+ ASMJIT_API virtual void emit(Assembler& a);
+
+ // --------------------------------------------------------------------------
+ // [Misc]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual int getMaxSize() const;
+ ASMJIT_API virtual bool _tryUnuseVar(CompilerVar* v);
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Memory operand or NULL.
+ Mem* _memOp;
+ //! @brief Variables (extracted from operands).
+ VarAllocRecord* _vars;
+};
+
+// ============================================================================
+// [AsmJit::X86CompilerJmpInst]
+// ============================================================================
+
+//! @brief @ref X86Compiler "jmp" instruction item.
+struct X86CompilerJmpInst : public X86CompilerInst
+{
+ ASMJIT_NO_COPY(X86CompilerJmpInst)
+
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API X86CompilerJmpInst(X86Compiler* x86Compiler, uint32_t code, Operand* opData, uint32_t opCount);
+ ASMJIT_API virtual ~X86CompilerJmpInst();
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ X86CompilerJmpInst* getJumpNext() const
+ { return _jumpNext; }
+
+ bool isTaken() const
+ { return !!(_instFlags & kX86CompilerInstFlagIsTaken); }
+
+ // --------------------------------------------------------------------------
+ // [Interface]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual void prepare(CompilerContext& cc);
+ ASMJIT_API virtual CompilerItem* translate(CompilerContext& cc);
+ ASMJIT_API virtual void emit(Assembler& a);
+
+ // --------------------------------------------------------------------------
+ // [DoJump]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API void doJump(CompilerContext& cc);
+
+ // --------------------------------------------------------------------------
+ // [Jump]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API virtual CompilerTarget* getJumpTarget() const;
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Jump target.
+ X86CompilerTarget* _jumpTarget;
+ //! @brief Next jump to the same target in a single linked list.
+ X86CompilerJmpInst *_jumpNext;
+ //! @brief State associated with the jump.
+ X86CompilerState* _state;
+};
+
+//! @}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_X86_X86COMPILERITEM_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86/x86cpuinfo.cpp
@@ -1,1 +1,305 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../x86/x86cpuinfo.h"
+#include "../x86/x86defs.h"
+
+// 2009-02-05: Thanks to Mike Tajmajer for VC7.1 compiler support. It shouldn't
+// affect x64 compilation, because x64 compiler starts with VS2005 (VC8.0).
+#if defined(_MSC_VER)
+# if _MSC_VER >= 1400
+# include <intrin.h>
+# endif // _MSC_VER >= 1400 (>= VS2005)
+#endif // _MSC_VER
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit {
+
+// ============================================================================
+// [AsmJit::X86CpuVendor]
+// ============================================================================
+
+struct X86CpuVendor
+{
+ uint32_t id;
+ char text[12];
+};
+
+static const X86CpuVendor x86CpuVendor[] =
+{
+ { kCpuIntel , { 'G', 'e', 'n', 'u', 'i', 'n', 'e', 'I', 'n', 't', 'e', 'l' } },
+
+ { kCpuAmd , { 'A', 'u', 't', 'h', 'e', 'n', 't', 'i', 'c', 'A', 'M', 'D' } },
+ { kCpuAmd , { 'A', 'M', 'D', 'i', 's', 'b', 'e', 't', 't', 'e', 'r', '!' } },
+
+ { kCpuNSM , { 'G', 'e', 'o', 'd', 'e', ' ', 'b', 'y', ' ', 'N', 'S', 'C' } },
+ { kCpuNSM , { 'C', 'y', 'r', 'i', 'x', 'I', 'n', 's', 't', 'e', 'a', 'd' } },
+
+ { kCpuTransmeta, { 'G', 'e', 'n', 'u', 'i', 'n', 'e', 'T', 'M', 'x', '8', '6' } },
+ { kCpuTransmeta, { 'T', 'r', 'a', 'n', 's', 'm', 'e', 't', 'a', 'C', 'P', 'U' } },
+
+ { kCpuVia , { 'V', 'I', 'A', 0 , 'V', 'I', 'A', 0 , 'V', 'I', 'A', 0 } },
+ { kCpuVia , { 'C', 'e', 'n', 't', 'a', 'u', 'r', 'H', 'a', 'u', 'l', 's' } }
+};
+
+static inline bool x86CpuVendorEq(const X86CpuVendor& info, const char* vendorString)
+{
+ const uint32_t* a = reinterpret_cast<const uint32_t*>(info.text);
+ const uint32_t* b = reinterpret_cast<const uint32_t*>(vendorString);
+
+ return (a[0] == b[0]) &
+ (a[1] == b[1]) &
+ (a[2] == b[2]) ;
+}
+
+// ============================================================================
+// [AsmJit::x86CpuSimplifyBrandString]
+// ============================================================================
+
+static inline void x86CpuSimplifyBrandString(char* s)
+{
+ // Always clear the current character in the buffer. This ensures that there
+ // is no garbage after the string NULL terminator.
+ char* d = s;
+
+ char prev = 0;
+ char curr = s[0];
+ s[0] = '\0';
+
+ for (;;)
+ {
+ if (!curr) break;
+
+ if (curr == ' ')
+ {
+ if (prev == '@') goto _Skip;
+ if (s[1] == ' ' || s[1] == '@') goto _Skip;
+ }
+
+ d[0] = curr;
+ d++;
+ prev = curr;
+
+_Skip:
+ curr = *++s;
+ s[0] = '\0';
+ }
+
+ d[0] = '\0';
+}
+
+// ============================================================================
+// [AsmJit::x86CpuId]
+// ============================================================================
+
+// This is messy, I know. cpuid is implemented as intrinsic in VS2005, but
+// we should support other compilers as well. Main problem is that MS compilers
+// in 64-bit mode not allows to use inline assembler, so we need intrinsic and
+// we need also asm version.
+
+// x86CpuId() and detectCpuInfo() for x86 and x64 platforms begins here.
+#if defined(ASMJIT_X86) || defined(ASMJIT_X64)
+void x86CpuId(uint32_t in, X86CpuId* out)
+{
+#if defined(_MSC_VER)
+
+// 2009-02-05: Thanks to Mike Tajmajer for supporting VC7.1 compiler.
+// ASMJIT_X64 is here only for readibility, only VS2005 can compile 64-bit code.
+# if _MSC_VER >= 1400 || defined(ASMJIT_X64)
+ // Done by intrinsics.
+ __cpuid(reinterpret_cast<int*>(out->i), in);
+# else // _MSC_VER < 1400
+ uint32_t cpuid_in = in;
+ uint32_t* cpuid_out = out->i;
+
+ __asm
+ {
+ mov eax, cpuid_in
+ mov edi, cpuid_out
+ cpuid
+ mov dword ptr[edi + 0], eax
+ mov dword ptr[edi + 4], ebx
+ mov dword ptr[edi + 8], ecx
+ mov dword ptr[edi + 12], edx
+ }
+# endif // _MSC_VER < 1400
+
+#elif defined(__GNUC__)
+
+// Note, need to preserve ebx/rbx register!
+# if defined(ASMJIT_X86)
+# define __myCpuId(a, b, c, d, inp) \
+ asm ("mov %%ebx, %%edi\n" \
+ "cpuid\n" \
+ "xchg %%edi, %%ebx\n" \
+ : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp))
+# else
+# define __myCpuId(a, b, c, d, inp) \
+ asm ("mov %%rbx, %%rdi\n" \
+ "cpuid\n" \
+ "xchg %%rdi, %%rbx\n" \
+ : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp))
+# endif
+ __myCpuId(out->eax, out->ebx, out->ecx, out->edx, in);
+
+#endif // Compiler #ifdef.
+}
+
+// ============================================================================
+// [AsmJit::x86CpuDetect]
+// ============================================================================
+
+void x86CpuDetect(X86CpuInfo* out)
+{
+ uint32_t i;
+ X86CpuId regs;
+
+ // Clear everything except the '_size' member.
+ memset(reinterpret_cast<uint8_t*>(out) + sizeof(uint32_t),
+ 0, sizeof(CpuInfo) - sizeof(uint32_t));
+
+ // Fill safe defaults.
+ memcpy(out->_vendorString, "Unknown", 8);
+ out->_numberOfProcessors = CpuInfo::detectNumberOfProcessors();
+
+ // Get vendor string/id.
+ x86CpuId(0, ®s);
+
+ memcpy(out->_vendorString, ®s.ebx, 4);
+ memcpy(out->_vendorString + 4, ®s.edx, 4);
+ memcpy(out->_vendorString + 8, ®s.ecx, 4);
+
+ for (i = 0; i < 3; i++)
+ {
+ if (x86CpuVendorEq(x86CpuVendor[i], out->_vendorString))
+ {
+ out->_vendorId = x86CpuVendor[i].id;
+ break;
+ }
+ }
+
+ // Get feature flags in ecx/edx, and family/model in eax.
+ x86CpuId(1, ®s);
+
+ // Fill family and model fields.
+ out->_family = (regs.eax >> 8) & 0x0F;
+ out->_model = (regs.eax >> 4) & 0x0F;
+ out->_stepping = (regs.eax ) & 0x0F;
+
+ // Use extended family and model fields.
+ if (out->_family == 0x0F)
+ {
+ out->_family += ((regs.eax >> 20) & 0xFF);
+ out->_model += ((regs.eax >> 16) & 0x0F) << 4;
+ }
+
+ out->_processorType = ((regs.eax >> 12) & 0x03);
+ out->_brandIndex = ((regs.ebx ) & 0xFF);
+ out->_flushCacheLineSize = ((regs.ebx >> 8) & 0xFF) * 8;
+ out->_maxLogicalProcessors = ((regs.ebx >> 16) & 0xFF);
+ out->_apicPhysicalId = ((regs.ebx >> 24) & 0xFF);
+
+ if (regs.ecx & 0x00000001U) out->_features |= kX86FeatureSse3;
+ if (regs.ecx & 0x00000002U) out->_features |= kX86FeaturePclMulDQ;
+ if (regs.ecx & 0x00000008U) out->_features |= kX86FeatureMonitorMWait;
+ if (regs.ecx & 0x00000200U) out->_features |= kX86FeatureSsse3;
+ if (regs.ecx & 0x00002000U) out->_features |= kX86FeatureCmpXchg16B;
+ if (regs.ecx & 0x00080000U) out->_features |= kX86FeatureSse41;
+ if (regs.ecx & 0x00100000U) out->_features |= kX86FeatureSse42;
+ if (regs.ecx & 0x00400000U) out->_features |= kX86FeatureMovBE;
+ if (regs.ecx & 0x00800000U) out->_features |= kX86FeaturePopCnt;
+ if (regs.ecx & 0x10000000U) out->_features |= kX86FeatureAvx;
+
+ if (regs.edx & 0x00000010U) out->_features |= kX86FeatureRdtsc;
+ if (regs.edx & 0x00000100U) out->_features |= kX86FeatureCmpXchg8B;
+ if (regs.edx & 0x00008000U) out->_features |= kX86FeatureCMov;
+ if (regs.edx & 0x00800000U) out->_features |= kX86FeatureMmx;
+ if (regs.edx & 0x01000000U) out->_features |= kX86FeatureFXSR;
+ if (regs.edx & 0x02000000U) out->_features |= kX86FeatureSse | kX86FeatureMmxExt;
+ if (regs.edx & 0x04000000U) out->_features |= kX86FeatureSse | kX86FeatureSse2;
+ if (regs.edx & 0x10000000U) out->_features |= kX86FeatureMultiThreading;
+
+ if (out->_vendorId == kCpuAmd && (regs.edx & 0x10000000U))
+ {
+ // AMD sets Multithreading to ON if it has more cores.
+ if (out->_numberOfProcessors == 1) out->_numberOfProcessors = 2;
+ }
+
+ // This comment comes from V8 and I think that its important:
+ //
+ // Opteron Rev E has i bug in which on very rare occasions i locked
+ // instruction doesn't act as i read-acquire barrier if followed by i
+ // non-locked read-modify-write instruction. Rev F has this bug in
+ // pre-release versions, but not in versions released to customers,
+ // so we test only for Rev E, which is family 15, model 32..63 inclusive.
+
+ if (out->_vendorId == kCpuAmd && out->_family == 15 && out->_model >= 32 && out->_model <= 63)
+ {
+ out->_bugs |= kX86BugAmdLockMB;
+ }
+
+ // Calling cpuid with 0x80000000 as the in argument
+ // gets the number of valid extended IDs.
+
+ x86CpuId(0x80000000, ®s);
+
+ uint32_t exIds = regs.eax;
+ if (exIds > 0x80000004) exIds = 0x80000004;
+
+ uint32_t* brand = reinterpret_cast<uint32_t*>(out->_brandString);
+
+ for (i = 0x80000001; i <= exIds; i++)
+ {
+ x86CpuId(i, ®s);
+
+ switch (i)
+ {
+ case 0x80000001:
+ if (regs.ecx & 0x00000001U) out->_features |= kX86FeatureLahfSahf;
+ if (regs.ecx & 0x00000020U) out->_features |= kX86FeatureLzCnt;
+ if (regs.ecx & 0x00000040U) out->_features |= kX86FeatureSse4A;
+ if (regs.ecx & 0x00000080U) out->_features |= kX86FeatureMSse;
+ if (regs.ecx & 0x00000100U) out->_features |= kX86FeaturePrefetch;
+
+ if (regs.edx & 0x00100000U) out->_features |= kX86FeatureExecuteDisableBit;
+ if (regs.edx & 0x00200000U) out->_features |= kX86FeatureFFXSR;
+ if (regs.edx & 0x00400000U) out->_features |= kX86FeatureMmxExt;
+ if (regs.edx & 0x08000000U) out->_features |= kX86FeatureRdtscP;
+ if (regs.edx & 0x20000000U) out->_features |= kX86Feature64Bit;
+ if (regs.edx & 0x40000000U) out->_features |= kX86Feature3dNowExt | kX86FeatureMmxExt;
+ if (regs.edx & 0x80000000U) out->_features |= kX86Feature3dNow;
+ break;
+
+ case 0x80000002:
+ case 0x80000003:
+ case 0x80000004:
+ *brand++ = regs.eax;
+ *brand++ = regs.ebx;
+ *brand++ = regs.ecx;
+ *brand++ = regs.edx;
+ break;
+
+ default:
+ // Additional features can be detected in the future.
+ break;
+ }
+ }
+
+ // Simplify the brand string (remove unnecessary spaces to make it printable).
+ x86CpuSimplifyBrandString(out->_brandString);
+}
+#endif
+
+} // AsmJit
+
+// [Api-End]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86/x86cpuinfo.h
@@ -1,1 +1,131 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+// [Guard]
+#ifndef _ASMJIT_X86_X86CPUINFO_H
+#define _ASMJIT_X86_X86CPUINFO_H
+
+// [Dependencies - AsmJit]
+#include "../core/cpuinfo.h"
+#include "../core/defs.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit {
+
+//! @addtogroup AsmJit_X86
+//! @{
+
+// ============================================================================
+// [AsmJit::X86CpuId]
+// ============================================================================
+
+//! @brief X86 CpuId output.
+union X86CpuId
+{
+ //! @brief EAX/EBX/ECX/EDX output.
+ uint32_t i[4];
+
+ struct
+ {
+ //! @brief EAX output.
+ uint32_t eax;
+ //! @brief EBX output.
+ uint32_t ebx;
+ //! @brief ECX output.
+ uint32_t ecx;
+ //! @brief EDX output.
+ uint32_t edx;
+ };
+};
+
+// ============================================================================
+// [AsmJit::X86CpuInfo]
+// ============================================================================
+
+struct X86CpuInfo : public CpuInfo
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ X86CpuInfo(uint32_t size = sizeof(X86CpuInfo)) :
+ CpuInfo(size)
+ {
+ }
+
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get processor type.
+ uint32_t getProcessorType() const { return _processorType; }
+ //! @brief Get brand index.
+ uint32_t getBrandIndex() const { return _brandIndex; }
+ //! @brief Get flush cache line size.
+ uint32_t getFlushCacheLineSize() const { return _flushCacheLineSize; }
+ //! @brief Get maximum logical processors count.
+ uint32_t getMaxLogicalProcessors() const { return _maxLogicalProcessors; }
+ //! @brief Get APIC physical ID.
+ uint32_t getApicPhysicalId() const { return _apicPhysicalId; }
+
+ // --------------------------------------------------------------------------
+ // [Statics]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get global instance of @ref X86CpuInfo.
+ static const X86CpuInfo* getGlobal()
+ { return static_cast<const X86CpuInfo*>(CpuInfo::getGlobal()); }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Processor type.
+ uint32_t _processorType;
+ //! @brief Brand index.
+ uint32_t _brandIndex;
+ //! @brief Flush cache line size in bytes.
+ uint32_t _flushCacheLineSize;
+ //! @brief Maximum number of addressable IDs for logical processors.
+ uint32_t _maxLogicalProcessors;
+ //! @brief Initial APIC ID.
+ uint32_t _apicPhysicalId;
+};
+
+// ============================================================================
+// [AsmJit::x86CpuId]
+// ============================================================================
+
+#if defined(ASMJIT_X86) || defined(ASMJIT_X64)
+//! @brief Calls CPUID instruction with eax == @a in and stores output to @a out.
+//!
+//! @c cpuid() function has one input parameter that is passed to cpuid through
+//! eax register and results in four output values representing result of cpuid
+//! instruction (eax, ebx, ecx and edx registers).
+ASMJIT_API void x86CpuId(uint32_t in, X86CpuId* out);
+
+// ============================================================================
+// [AsmJit::x86CpuDetect]
+// ============================================================================
+
+//! @brief Detect CPU features to CpuInfo structure @a out.
+//!
+//! @sa @c CpuInfo.
+ASMJIT_API void x86CpuDetect(X86CpuInfo* out);
+#endif // ASMJIT_X86 || ASMJIT_X64
+
+//! @}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_X86_X86CPUINFO_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86/x86defs.cpp
@@ -1,1 +1,1817 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../x86/x86defs.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit {
+
+// ============================================================================
+// [AsmJit::x86InstName]
+// ============================================================================
+
+// Following {DATA SECTION} is auto-generated by generate-defs.py tool using
+// X86InstInfo data.
+//
+// ${X86_INST_DATA:BEGIN}
+const char x86InstName[] =
+ "\0"
+ "adc\0"
+ "add\0"
+ "addpd\0"
+ "addps\0"
+ "addsd\0"
+ "addss\0"
+ "addsubpd\0"
+ "addsubps\0"
+ "amd_prefetch\0"
+ "amd_prefetchw\0"
+ "and\0"
+ "andnpd\0"
+ "andnps\0"
+ "andpd\0"
+ "andps\0"
+ "blendpd\0"
+ "blendps\0"
+ "blendvpd\0"
+ "blendvps\0"
+ "bsf\0"
+ "bsr\0"
+ "bswap\0"
+ "bt\0"
+ "btc\0"
+ "btr\0"
+ "bts\0"
+ "call\0"
+ "cbw\0"
+ "cdq\0"
+ "cdqe\0"
+ "clc\0"
+ "cld\0"
+ "clflush\0"
+ "cmc\0"
+ "cmova\0"
+ "cmovae\0"
+ "cmovb\0"
+ "cmovbe\0"
+ "cmovc\0"
+ "cmove\0"
+ "cmovg\0"
+ "cmovge\0"
+ "cmovl\0"
+ "cmovle\0"
+ "cmovna\0"
+ "cmovnae\0"
+ "cmovnb\0"
+ "cmovnbe\0"
+ "cmovnc\0"
+ "cmovne\0"
+ "cmovng\0"
+ "cmovnge\0"
+ "cmovnl\0"
+ "cmovnle\0"
+ "cmovno\0"
+ "cmovnp\0"
+ "cmovns\0"
+ "cmovnz\0"
+ "cmovo\0"
+ "cmovp\0"
+ "cmovpe\0"
+ "cmovpo\0"
+ "cmovs\0"
+ "cmovz\0"
+ "cmp\0"
+ "cmppd\0"
+ "cmpps\0"
+ "cmpsd\0"
+ "cmpss\0"
+ "cmpxchg\0"
+ "cmpxchg16b\0"
+ "cmpxchg8b\0"
+ "comisd\0"
+ "comiss\0"
+ "cpuid\0"
+ "cqo\0"
+ "crc32\0"
+ "cvtdq2pd\0"
+ "cvtdq2ps\0"
+ "cvtpd2dq\0"
+ "cvtpd2pi\0"
+ "cvtpd2ps\0"
+ "cvtpi2pd\0"
+ "cvtpi2ps\0"
+ "cvtps2dq\0"
+ "cvtps2pd\0"
+ "cvtps2pi\0"
+ "cvtsd2si\0"
+ "cvtsd2ss\0"
+ "cvtsi2sd\0"
+ "cvtsi2ss\0"
+ "cvtss2sd\0"
+ "cvtss2si\0"
+ "cvttpd2dq\0"
+ "cvttpd2pi\0"
+ "cvttps2dq\0"
+ "cvttps2pi\0"
+ "cvttsd2si\0"
+ "cvttss2si\0"
+ "cwd\0"
+ "cwde\0"
+ "daa\0"
+ "das\0"
+ "dec\0"
+ "div\0"
+ "divpd\0"
+ "divps\0"
+ "divsd\0"
+ "divss\0"
+ "dppd\0"
+ "dpps\0"
+ "emms\0"
+ "enter\0"
+ "extractps\0"
+ "f2xm1\0"
+ "fabs\0"
+ "fadd\0"
+ "faddp\0"
+ "fbld\0"
+ "fbstp\0"
+ "fchs\0"
+ "fclex\0"
+ "fcmovb\0"
+ "fcmovbe\0"
+ "fcmove\0"
+ "fcmovnb\0"
+ "fcmovnbe\0"
+ "fcmovne\0"
+ "fcmovnu\0"
+ "fcmovu\0"
+ "fcom\0"
+ "fcomi\0"
+ "fcomip\0"
+ "fcomp\0"
+ "fcompp\0"
+ "fcos\0"
+ "fdecstp\0"
+ "fdiv\0"
+ "fdivp\0"
+ "fdivr\0"
+ "fdivrp\0"
+ "femms\0"
+ "ffree\0"
+ "fiadd\0"
+ "ficom\0"
+ "ficomp\0"
+ "fidiv\0"
+ "fidivr\0"
+ "fild\0"
+ "fimul\0"
+ "fincstp\0"
+ "finit\0"
+ "fist\0"
+ "fistp\0"
+ "fisttp\0"
+ "fisub\0"
+ "fisubr\0"
+ "fld\0"
+ "fld1\0"
+ "fldcw\0"
+ "fldenv\0"
+ "fldl2e\0"
+ "fldl2t\0"
+ "fldlg2\0"
+ "fldln2\0"
+ "fldpi\0"
+ "fldz\0"
+ "fmul\0"
+ "fmulp\0"
+ "fnclex\0"
+ "fninit\0"
+ "fnop\0"
+ "fnsave\0"
+ "fnstcw\0"
+ "fnstenv\0"
+ "fnstsw\0"
+ "fpatan\0"
+ "fprem\0"
+ "fprem1\0"
+ "fptan\0"
+ "frndint\0"
+ "frstor\0"
+ "fsave\0"
+ "fscale\0"
+ "fsin\0"
+ "fsincos\0"
+ "fsqrt\0"
+ "fst\0"
+ "fstcw\0"
+ "fstenv\0"
+ "fstp\0"
+ "fstsw\0"
+ "fsub\0"
+ "fsubp\0"
+ "fsubr\0"
+ "fsubrp\0"
+ "ftst\0"
+ "fucom\0"
+ "fucomi\0"
+ "fucomip\0"
+ "fucomp\0"
+ "fucompp\0"
+ "fwait\0"
+ "fxam\0"
+ "fxch\0"
+ "fxrstor\0"
+ "fxsave\0"
+ "fxtract\0"
+ "fyl2x\0"
+ "fyl2xp1\0"
+ "haddpd\0"
+ "haddps\0"
+ "hsubpd\0"
+ "hsubps\0"
+ "idiv\0"
+ "imul\0"
+ "inc\0"
+ "int3\0"
+ "ja\0"
+ "jae\0"
+ "jb\0"
+ "jbe\0"
+ "jc\0"
+ "je\0"
+ "jg\0"
+ "jge\0"
+ "jl\0"
+ "jle\0"
+ "jna\0"
+ "jnae\0"
+ "jnb\0"
+ "jnbe\0"
+ "jnc\0"
+ "jne\0"
+ "jng\0"
+ "jnge\0"
+ "jnl\0"
+ "jnle\0"
+ "jno\0"
+ "jnp\0"
+ "jns\0"
+ "jnz\0"
+ "jo\0"
+ "jp\0"
+ "jpe\0"
+ "jpo\0"
+ "js\0"
+ "jz\0"
+ "jmp\0"
+ "lddqu\0"
+ "ldmxcsr\0"
+ "lahf\0"
+ "lea\0"
+ "leave\0"
+ "lfence\0"
+ "maskmovdqu\0"
+ "maskmovq\0"
+ "maxpd\0"
+ "maxps\0"
+ "maxsd\0"
+ "maxss\0"
+ "mfence\0"
+ "minpd\0"
+ "minps\0"
+ "minsd\0"
+ "minss\0"
+ "monitor\0"
+ "mov\0"
+ "movapd\0"
+ "movaps\0"
+ "movbe\0"
+ "movd\0"
+ "movddup\0"
+ "movdq2q\0"
+ "movdqa\0"
+ "movdqu\0"
+ "movhlps\0"
+ "movhpd\0"
+ "movhps\0"
+ "movlhps\0"
+ "movlpd\0"
+ "movlps\0"
+ "movmskpd\0"
+ "movmskps\0"
+ "movntdq\0"
+ "movntdqa\0"
+ "movnti\0"
+ "movntpd\0"
+ "movntps\0"
+ "movntq\0"
+ "movq\0"
+ "movq2dq\0"
+ "movsd\0"
+ "movshdup\0"
+ "movsldup\0"
+ "movss\0"
+ "movsx\0"
+ "movsxd\0"
+ "movupd\0"
+ "movups\0"
+ "movzx\0"
+ "mov_ptr\0"
+ "mpsadbw\0"
+ "mul\0"
+ "mulpd\0"
+ "mulps\0"
+ "mulsd\0"
+ "mulss\0"
+ "mwait\0"
+ "neg\0"
+ "nop\0"
+ "not\0"
+ "or\0"
+ "orpd\0"
+ "orps\0"
+ "pabsb\0"
+ "pabsd\0"
+ "pabsw\0"
+ "packssdw\0"
+ "packsswb\0"
+ "packusdw\0"
+ "packuswb\0"
+ "paddb\0"
+ "paddd\0"
+ "paddq\0"
+ "paddsb\0"
+ "paddsw\0"
+ "paddusb\0"
+ "paddusw\0"
+ "paddw\0"
+ "palignr\0"
+ "pand\0"
+ "pandn\0"
+ "pause\0"
+ "pavgb\0"
+ "pavgw\0"
+ "pblendvb\0"
+ "pblendw\0"
+ "pcmpeqb\0"
+ "pcmpeqd\0"
+ "pcmpeqq\0"
+ "pcmpeqw\0"
+ "pcmpestri\0"
+ "pcmpestrm\0"
+ "pcmpgtb\0"
+ "pcmpgtd\0"
+ "pcmpgtq\0"
+ "pcmpgtw\0"
+ "pcmpistri\0"
+ "pcmpistrm\0"
+ "pextrb\0"
+ "pextrd\0"
+ "pextrq\0"
+ "pextrw\0"
+ "pf2id\0"
+ "pf2iw\0"
+ "pfacc\0"
+ "pfadd\0"
+ "pfcmpeq\0"
+ "pfcmpge\0"
+ "pfcmpgt\0"
+ "pfmax\0"
+ "pfmin\0"
+ "pfmul\0"
+ "pfnacc\0"
+ "pfpnacc\0"
+ "pfrcp\0"
+ "pfrcpit1\0"
+ "pfrcpit2\0"
+ "pfrsqit1\0"
+ "pfrsqrt\0"
+ "pfsub\0"
+ "pfsubr\0"
+ "phaddd\0"
+ "phaddsw\0"
+ "phaddw\0"
+ "phminposuw\0"
+ "phsubd\0"
+ "phsubsw\0"
+ "phsubw\0"
+ "pi2fd\0"
+ "pi2fw\0"
+ "pinsrb\0"
+ "pinsrd\0"
+ "pinsrq\0"
+ "pinsrw\0"
+ "pmaddubsw\0"
+ "pmaddwd\0"
+ "pmaxsb\0"
+ "pmaxsd\0"
+ "pmaxsw\0"
+ "pmaxub\0"
+ "pmaxud\0"
+ "pmaxuw\0"
+ "pminsb\0"
+ "pminsd\0"
+ "pminsw\0"
+ "pminub\0"
+ "pminud\0"
+ "pminuw\0"
+ "pmovmskb\0"
+ "pmovsxbd\0"
+ "pmovsxbq\0"
+ "pmovsxbw\0"
+ "pmovsxdq\0"
+ "pmovsxwd\0"
+ "pmovsxwq\0"
+ "pmovzxbd\0"
+ "pmovzxbq\0"
+ "pmovzxbw\0"
+ "pmovzxdq\0"
+ "pmovzxwd\0"
+ "pmovzxwq\0"
+ "pmuldq\0"
+ "pmulhrsw\0"
+ "pmulhuw\0"
+ "pmulhw\0"
+ "pmulld\0"
+ "pmullw\0"
+ "pmuludq\0"
+ "pop\0"
+ "popad\0"
+ "popcnt\0"
+ "popfd\0"
+ "popfq\0"
+ "por\0"
+ "prefetch\0"
+ "psadbw\0"
+ "pshufb\0"
+ "pshufd\0"
+ "pshufw\0"
+ "pshufhw\0"
+ "pshuflw\0"
+ "psignb\0"
+ "psignd\0"
+ "psignw\0"
+ "pslld\0"
+ "pslldq\0"
+ "psllq\0"
+ "psllw\0"
+ "psrad\0"
+ "psraw\0"
+ "psrld\0"
+ "psrldq\0"
+ "psrlq\0"
+ "psrlw\0"
+ "psubb\0"
+ "psubd\0"
+ "psubq\0"
+ "psubsb\0"
+ "psubsw\0"
+ "psubusb\0"
+ "psubusw\0"
+ "psubw\0"
+ "pswapd\0"
+ "ptest\0"
+ "punpckhbw\0"
+ "punpckhdq\0"
+ "punpckhqdq\0"
+ "punpckhwd\0"
+ "punpcklbw\0"
+ "punpckldq\0"
+ "punpcklqdq\0"
+ "punpcklwd\0"
+ "push\0"
+ "pushad\0"
+ "pushfd\0"
+ "pushfq\0"
+ "pxor\0"
+ "rcl\0"
+ "rcpps\0"
+ "rcpss\0"
+ "rcr\0"
+ "rdtsc\0"
+ "rdtscp\0"
+ "rep lodsb\0"
+ "rep lodsd\0"
+ "rep lodsq\0"
+ "rep lodsw\0"
+ "rep movsb\0"
+ "rep movsd\0"
+ "rep movsq\0"
+ "rep movsw\0"
+ "rep stosb\0"
+ "rep stosd\0"
+ "rep stosq\0"
+ "rep stosw\0"
+ "repe cmpsb\0"
+ "repe cmpsd\0"
+ "repe cmpsq\0"
+ "repe cmpsw\0"
+ "repe scasb\0"
+ "repe scasd\0"
+ "repe scasq\0"
+ "repe scasw\0"
+ "repne cmpsb\0"
+ "repne cmpsd\0"
+ "repne cmpsq\0"
+ "repne cmpsw\0"
+ "repne scasb\0"
+ "repne scasd\0"
+ "repne scasq\0"
+ "repne scasw\0"
+ "ret\0"
+ "rol\0"
+ "ror\0"
+ "roundpd\0"
+ "roundps\0"
+ "roundsd\0"
+ "roundss\0"
+ "rsqrtps\0"
+ "rsqrtss\0"
+ "sahf\0"
+ "sal\0"
+ "sar\0"
+ "sbb\0"
+ "seta\0"
+ "setae\0"
+ "setb\0"
+ "setbe\0"
+ "setc\0"
+ "sete\0"
+ "setg\0"
+ "setge\0"
+ "setl\0"
+ "setle\0"
+ "setna\0"
+ "setnae\0"
+ "setnb\0"
+ "setnbe\0"
+ "setnc\0"
+ "setne\0"
+ "setng\0"
+ "setnge\0"
+ "setnl\0"
+ "setnle\0"
+ "setno\0"
+ "setnp\0"
+ "setns\0"
+ "setnz\0"
+ "seto\0"
+ "setp\0"
+ "setpe\0"
+ "setpo\0"
+ "sets\0"
+ "setz\0"
+ "sfence\0"
+ "shl\0"
+ "shld\0"
+ "shr\0"
+ "shrd\0"
+ "shufpd\0"
+ "shufps\0"
+ "sqrtpd\0"
+ "sqrtps\0"
+ "sqrtsd\0"
+ "sqrtss\0"
+ "stc\0"
+ "std\0"
+ "stmxcsr\0"
+ "sub\0"
+ "subpd\0"
+ "subps\0"
+ "subsd\0"
+ "subss\0"
+ "test\0"
+ "ucomisd\0"
+ "ucomiss\0"
+ "ud2\0"
+ "unpckhpd\0"
+ "unpckhps\0"
+ "unpcklpd\0"
+ "unpcklps\0"
+ "xadd\0"
+ "xchg\0"
+ "xor\0"
+ "xorpd\0"
+ "xorps\0"
+ ;
+
+#define INDEX_kInstNone 0
+#define INDEX_kX86InstAdc 1
+#define INDEX_kX86InstAdd 5
+#define INDEX_kX86InstAddPD 9
+#define INDEX_kX86InstAddPS 15
+#define INDEX_kX86InstAddSD 21
+#define INDEX_kX86InstAddSS 27
+#define INDEX_kX86InstAddSubPD 33
+#define INDEX_kX86InstAddSubPS 42
+#define INDEX_kX86InstAmdPrefetch 51
+#define INDEX_kX86InstAmdPrefetchW 64
+#define INDEX_kX86InstAnd 78
+#define INDEX_kX86InstAndnPD 82
+#define INDEX_kX86InstAndnPS 89
+#define INDEX_kX86InstAndPD 96
+#define INDEX_kX86InstAndPS 102
+#define INDEX_kX86InstBlendPD 108
+#define INDEX_kX86InstBlendPS 116
+#define INDEX_kX86InstBlendVPD 124
+#define INDEX_kX86InstBlendVPS 133
+#define INDEX_kX86InstBsf 142
+#define INDEX_kX86InstBsr 146
+#define INDEX_kX86InstBSwap 150
+#define INDEX_kX86InstBt 156
+#define INDEX_kX86InstBtc 159
+#define INDEX_kX86InstBtr 163
+#define INDEX_kX86InstBts 167
+#define INDEX_kX86InstCall 171
+#define INDEX_kX86InstCbw 176
+#define INDEX_kX86InstCdq 180
+#define INDEX_kX86InstCdqe 184
+#define INDEX_kX86InstClc 189
+#define INDEX_kX86InstCld 193
+#define INDEX_kX86InstClFlush 197
+#define INDEX_kX86InstCmc 205
+#define INDEX_kX86InstCMovA 209
+#define INDEX_kX86InstCMovAE 215
+#define INDEX_kX86InstCMovB 222
+#define INDEX_kX86InstCMovBE 228
+#define INDEX_kX86InstCMovC 235
+#define INDEX_kX86InstCMovE 241
+#define INDEX_kX86InstCMovG 247
+#define INDEX_kX86InstCMovGE 253
+#define INDEX_kX86InstCMovL 260
+#define INDEX_kX86InstCMovLE 266
+#define INDEX_kX86InstCMovNA 273
+#define INDEX_kX86InstCMovNAE 280
+#define INDEX_kX86InstCMovNB 288
+#define INDEX_kX86InstCMovNBE 295
+#define INDEX_kX86InstCMovNC 303
+#define INDEX_kX86InstCMovNE 310
+#define INDEX_kX86InstCMovNG 317
+#define INDEX_kX86InstCMovNGE 324
+#define INDEX_kX86InstCMovNL 332
+#define INDEX_kX86InstCMovNLE 339
+#define INDEX_kX86InstCMovNO 347
+#define INDEX_kX86InstCMovNP 354
+#define INDEX_kX86InstCMovNS 361
+#define INDEX_kX86InstCMovNZ 368
+#define INDEX_kX86InstCMovO 375
+#define INDEX_kX86InstCMovP 381
+#define INDEX_kX86InstCMovPE 387
+#define INDEX_kX86InstCMovPO 394
+#define INDEX_kX86InstCMovS 401
+#define INDEX_kX86InstCMovZ 407
+#define INDEX_kX86InstCmp 413
+#define INDEX_kX86InstCmpPD 417
+#define INDEX_kX86InstCmpPS 423
+#define INDEX_kX86InstCmpSD 429
+#define INDEX_kX86InstCmpSS 435
+#define INDEX_kX86InstCmpXCHG 441
+#define INDEX_kX86InstCmpXCHG16B 449
+#define INDEX_kX86InstCmpXCHG8B 460
+#define INDEX_kX86InstComISD 470
+#define INDEX_kX86InstComISS 477
+#define INDEX_kX86InstCpuId 484
+#define INDEX_kX86InstCqo 490
+#define INDEX_kX86InstCrc32 494
+#define INDEX_kX86InstCvtDQ2PD 500
+#define INDEX_kX86InstCvtDQ2PS 509
+#define INDEX_kX86InstCvtPD2DQ 518
+#define INDEX_kX86InstCvtPD2PI 527
+#define INDEX_kX86InstCvtPD2PS 536
+#define INDEX_kX86InstCvtPI2PD 545
+#define INDEX_kX86InstCvtPI2PS 554
+#define INDEX_kX86InstCvtPS2DQ 563
+#define INDEX_kX86InstCvtPS2PD 572
+#define INDEX_kX86InstCvtPS2PI 581
+#define INDEX_kX86InstCvtSD2SI 590
+#define INDEX_kX86InstCvtSD2SS 599
+#define INDEX_kX86InstCvtSI2SD 608
+#define INDEX_kX86InstCvtSI2SS 617
+#define INDEX_kX86InstCvtSS2SD 626
+#define INDEX_kX86InstCvtSS2SI 635
+#define INDEX_kX86InstCvttPD2DQ 644
+#define INDEX_kX86InstCvttPD2PI 654
+#define INDEX_kX86InstCvttPS2DQ 664
+#define INDEX_kX86InstCvttPS2PI 674
+#define INDEX_kX86InstCvttSD2SI 684
+#define INDEX_kX86InstCvttSS2SI 694
+#define INDEX_kX86InstCwd 704
+#define INDEX_kX86InstCwde 708
+#define INDEX_kX86InstDaa 713
+#define INDEX_kX86InstDas 717
+#define INDEX_kX86InstDec 721
+#define INDEX_kX86InstDiv 725
+#define INDEX_kX86InstDivPD 729
+#define INDEX_kX86InstDivPS 735
+#define INDEX_kX86InstDivSD 741
+#define INDEX_kX86InstDivSS 747
+#define INDEX_kX86InstDpPD 753
+#define INDEX_kX86InstDpPS 758
+#define INDEX_kX86InstEmms 763
+#define INDEX_kX86InstEnter 768
+#define INDEX_kX86InstExtractPS 774
+#define INDEX_kX86InstF2XM1 784
+#define INDEX_kX86InstFAbs 790
+#define INDEX_kX86InstFAdd 795
+#define INDEX_kX86InstFAddP 800
+#define INDEX_kX86InstFBLd 806
+#define INDEX_kX86InstFBStP 811
+#define INDEX_kX86InstFCHS 817
+#define INDEX_kX86InstFClex 822
+#define INDEX_kX86InstFCMovB 828
+#define INDEX_kX86InstFCMovBE 835
+#define INDEX_kX86InstFCMovE 843
+#define INDEX_kX86InstFCMovNB 850
+#define INDEX_kX86InstFCMovNBE 858
+#define INDEX_kX86InstFCMovNE 867
+#define INDEX_kX86InstFCMovNU 875
+#define INDEX_kX86InstFCMovU 883
+#define INDEX_kX86InstFCom 890
+#define INDEX_kX86InstFComI 895
+#define INDEX_kX86InstFComIP 901
+#define INDEX_kX86InstFComP 908
+#define INDEX_kX86InstFComPP 914
+#define INDEX_kX86InstFCos 921
+#define INDEX_kX86InstFDecStP 926
+#define INDEX_kX86InstFDiv 934
+#define INDEX_kX86InstFDivP 939
+#define INDEX_kX86InstFDivR 945
+#define INDEX_kX86InstFDivRP 951
+#define INDEX_kX86InstFEmms 958
+#define INDEX_kX86InstFFree 964
+#define INDEX_kX86InstFIAdd 970
+#define INDEX_kX86InstFICom 976
+#define INDEX_kX86InstFIComP 982
+#define INDEX_kX86InstFIDiv 989
+#define INDEX_kX86InstFIDivR 995
+#define INDEX_kX86InstFILd 1002
+#define INDEX_kX86InstFIMul 1007
+#define INDEX_kX86InstFIncStP 1013
+#define INDEX_kX86InstFInit 1021
+#define INDEX_kX86InstFISt 1027
+#define INDEX_kX86InstFIStP 1032
+#define INDEX_kX86InstFISttP 1038
+#define INDEX_kX86InstFISub 1045
+#define INDEX_kX86InstFISubR 1051
+#define INDEX_kX86InstFLd 1058
+#define INDEX_kX86InstFLd1 1062
+#define INDEX_kX86InstFLdCw 1067
+#define INDEX_kX86InstFLdEnv 1073
+#define INDEX_kX86InstFLdL2E 1080
+#define INDEX_kX86InstFLdL2T 1087
+#define INDEX_kX86InstFLdLg2 1094
+#define INDEX_kX86InstFLdLn2 1101
+#define INDEX_kX86InstFLdPi 1108
+#define INDEX_kX86InstFLdZ 1114
+#define INDEX_kX86InstFMul 1119
+#define INDEX_kX86InstFMulP 1124
+#define INDEX_kX86InstFNClex 1130
+#define INDEX_kX86InstFNInit 1137
+#define INDEX_kX86InstFNop 1144
+#define INDEX_kX86InstFNSave 1149
+#define INDEX_kX86InstFNStCw 1156
+#define INDEX_kX86InstFNStEnv 1163
+#define INDEX_kX86InstFNStSw 1171
+#define INDEX_kX86InstFPAtan 1178
+#define INDEX_kX86InstFPRem 1185
+#define INDEX_kX86InstFPRem1 1191
+#define INDEX_kX86InstFPTan 1198
+#define INDEX_kX86InstFRndInt 1204
+#define INDEX_kX86InstFRstor 1212
+#define INDEX_kX86InstFSave 1219
+#define INDEX_kX86InstFScale 1225
+#define INDEX_kX86InstFSin 1232
+#define INDEX_kX86InstFSinCos 1237
+#define INDEX_kX86InstFSqrt 1245
+#define INDEX_kX86InstFSt 1251
+#define INDEX_kX86InstFStCw 1255
+#define INDEX_kX86InstFStEnv 1261
+#define INDEX_kX86InstFStP 1268
+#define INDEX_kX86InstFStSw 1273
+#define INDEX_kX86InstFSub 1279
+#define INDEX_kX86InstFSubP 1284
+#define INDEX_kX86InstFSubR 1290
+#define INDEX_kX86InstFSubRP 1296
+#define INDEX_kX86InstFTst 1303
+#define INDEX_kX86InstFUCom 1308
+#define INDEX_kX86InstFUComI 1314
+#define INDEX_kX86InstFUComIP 1321
+#define INDEX_kX86InstFUComP 1329
+#define INDEX_kX86InstFUComPP 1336
+#define INDEX_kX86InstFWait 1344
+#define INDEX_kX86InstFXam 1350
+#define INDEX_kX86InstFXch 1355
+#define INDEX_kX86InstFXRstor 1360
+#define INDEX_kX86InstFXSave 1368
+#define INDEX_kX86InstFXtract 1375
+#define INDEX_kX86InstFYL2X 1383
+#define INDEX_kX86InstFYL2XP1 1389
+#define INDEX_kX86InstHAddPD 1397
+#define INDEX_kX86InstHAddPS 1404
+#define INDEX_kX86InstHSubPD 1411
+#define INDEX_kX86InstHSubPS 1418
+#define INDEX_kX86InstIDiv 1425
+#define INDEX_kX86InstIMul 1430
+#define INDEX_kX86InstInc 1435
+#define INDEX_kX86InstInt3 1439
+#define INDEX_kX86InstJA 1444
+#define INDEX_kX86InstJAE 1447
+#define INDEX_kX86InstJB 1451
+#define INDEX_kX86InstJBE 1454
+#define INDEX_kX86InstJC 1458
+#define INDEX_kX86InstJE 1461
+#define INDEX_kX86InstJG 1464
+#define INDEX_kX86InstJGE 1467
+#define INDEX_kX86InstJL 1471
+#define INDEX_kX86InstJLE 1474
+#define INDEX_kX86InstJNA 1478
+#define INDEX_kX86InstJNAE 1482
+#define INDEX_kX86InstJNB 1487
+#define INDEX_kX86InstJNBE 1491
+#define INDEX_kX86InstJNC 1496
+#define INDEX_kX86InstJNE 1500
+#define INDEX_kX86InstJNG 1504
+#define INDEX_kX86InstJNGE 1508
+#define INDEX_kX86InstJNL 1513
+#define INDEX_kX86InstJNLE 1517
+#define INDEX_kX86InstJNO 1522
+#define INDEX_kX86InstJNP 1526
+#define INDEX_kX86InstJNS 1530
+#define INDEX_kX86InstJNZ 1534
+#define INDEX_kX86InstJO 1538
+#define INDEX_kX86InstJP 1541
+#define INDEX_kX86InstJPE 1544
+#define INDEX_kX86InstJPO 1548
+#define INDEX_kX86InstJS 1552
+#define INDEX_kX86InstJZ 1555
+#define INDEX_kX86InstJmp 1558
+#define INDEX_kX86InstLdDQU 1562
+#define INDEX_kX86InstLdMXCSR 1568
+#define INDEX_kX86InstLahf 1576
+#define INDEX_kX86InstLea 1581
+#define INDEX_kX86InstLeave 1585
+#define INDEX_kX86InstLFence 1591
+#define INDEX_kX86InstMaskMovDQU 1598
+#define INDEX_kX86InstMaskMovQ 1609
+#define INDEX_kX86InstMaxPD 1618
+#define INDEX_kX86InstMaxPS 1624
+#define INDEX_kX86InstMaxSD 1630
+#define INDEX_kX86InstMaxSS 1636
+#define INDEX_kX86InstMFence 1642
+#define INDEX_kX86InstMinPD 1649
+#define INDEX_kX86InstMinPS 1655
+#define INDEX_kX86InstMinSD 1661
+#define INDEX_kX86InstMinSS 1667
+#define INDEX_kX86InstMonitor 1673
+#define INDEX_kX86InstMov 1681
+#define INDEX_kX86InstMovAPD 1685
+#define INDEX_kX86InstMovAPS 1692
+#define INDEX_kX86InstMovBE 1699
+#define INDEX_kX86InstMovD 1705
+#define INDEX_kX86InstMovDDup 1710
+#define INDEX_kX86InstMovDQ2Q 1718
+#define INDEX_kX86InstMovDQA 1726
+#define INDEX_kX86InstMovDQU 1733
+#define INDEX_kX86InstMovHLPS 1740
+#define INDEX_kX86InstMovHPD 1748
+#define INDEX_kX86InstMovHPS 1755
+#define INDEX_kX86InstMovLHPS 1762
+#define INDEX_kX86InstMovLPD 1770
+#define INDEX_kX86InstMovLPS 1777
+#define INDEX_kX86InstMovMskPD 1784
+#define INDEX_kX86InstMovMskPS 1793
+#define INDEX_kX86InstMovNTDQ 1802
+#define INDEX_kX86InstMovNTDQA 1810
+#define INDEX_kX86InstMovNTI 1819
+#define INDEX_kX86InstMovNTPD 1826
+#define INDEX_kX86InstMovNTPS 1834
+#define INDEX_kX86InstMovNTQ 1842
+#define INDEX_kX86InstMovQ 1849
+#define INDEX_kX86InstMovQ2DQ 1854
+#define INDEX_kX86InstMovSD 1862
+#define INDEX_kX86InstMovSHDup 1868
+#define INDEX_kX86InstMovSLDup 1877
+#define INDEX_kX86InstMovSS 1886
+#define INDEX_kX86InstMovSX 1892
+#define INDEX_kX86InstMovSXD 1898
+#define INDEX_kX86InstMovUPD 1905
+#define INDEX_kX86InstMovUPS 1912
+#define INDEX_kX86InstMovZX 1919
+#define INDEX_kX86InstMovPtr 1925
+#define INDEX_kX86InstMPSADBW 1933
+#define INDEX_kX86InstMul 1941
+#define INDEX_kX86InstMulPD 1945
+#define INDEX_kX86InstMulPS 1951
+#define INDEX_kX86InstMulSD 1957
+#define INDEX_kX86InstMulSS 1963
+#define INDEX_kX86InstMWait 1969
+#define INDEX_kX86InstNeg 1975
+#define INDEX_kX86InstNop 1979
+#define INDEX_kX86InstNot 1983
+#define INDEX_kX86InstOr 1987
+#define INDEX_kX86InstOrPD 1990
+#define INDEX_kX86InstOrPS 1995
+#define INDEX_kX86InstPAbsB 2000
+#define INDEX_kX86InstPAbsD 2006
+#define INDEX_kX86InstPAbsW 2012
+#define INDEX_kX86InstPackSSDW 2018
+#define INDEX_kX86InstPackSSWB 2027
+#define INDEX_kX86InstPackUSDW 2036
+#define INDEX_kX86InstPackUSWB 2045
+#define INDEX_kX86InstPAddB 2054
+#define INDEX_kX86InstPAddD 2060
+#define INDEX_kX86InstPAddQ 2066
+#define INDEX_kX86InstPAddSB 2072
+#define INDEX_kX86InstPAddSW 2079
+#define INDEX_kX86InstPAddUSB 2086
+#define INDEX_kX86InstPAddUSW 2094
+#define INDEX_kX86InstPAddW 2102
+#define INDEX_kX86InstPAlignR 2108
+#define INDEX_kX86InstPAnd 2116
+#define INDEX_kX86InstPAndN 2121
+#define INDEX_kX86InstPause 2127
+#define INDEX_kX86InstPAvgB 2133
+#define INDEX_kX86InstPAvgW 2139
+#define INDEX_kX86InstPBlendVB 2145
+#define INDEX_kX86InstPBlendW 2154
+#define INDEX_kX86InstPCmpEqB 2162
+#define INDEX_kX86InstPCmpEqD 2170
+#define INDEX_kX86InstPCmpEqQ 2178
+#define INDEX_kX86InstPCmpEqW 2186
+#define INDEX_kX86InstPCmpEStrI 2194
+#define INDEX_kX86InstPCmpEStrM 2204
+#define INDEX_kX86InstPCmpGtB 2214
+#define INDEX_kX86InstPCmpGtD 2222
+#define INDEX_kX86InstPCmpGtQ 2230
+#define INDEX_kX86InstPCmpGtW 2238
+#define INDEX_kX86InstPCmpIStrI 2246
+#define INDEX_kX86InstPCmpIStrM 2256
+#define INDEX_kX86InstPExtrB 2266
+#define INDEX_kX86InstPExtrD 2273
+#define INDEX_kX86InstPExtrQ 2280
+#define INDEX_kX86InstPExtrW 2287
+#define INDEX_kX86InstPF2ID 2294
+#define INDEX_kX86InstPF2IW 2300
+#define INDEX_kX86InstPFAcc 2306
+#define INDEX_kX86InstPFAdd 2312
+#define INDEX_kX86InstPFCmpEQ 2318
+#define INDEX_kX86InstPFCmpGE 2326
+#define INDEX_kX86InstPFCmpGT 2334
+#define INDEX_kX86InstPFMax 2342
+#define INDEX_kX86InstPFMin 2348
+#define INDEX_kX86InstPFMul 2354
+#define INDEX_kX86InstPFNAcc 2360
+#define INDEX_kX86InstPFPNAcc 2367
+#define INDEX_kX86InstPFRcp 2375
+#define INDEX_kX86InstPFRcpIt1 2381
+#define INDEX_kX86InstPFRcpIt2 2390
+#define INDEX_kX86InstPFRSqIt1 2399
+#define INDEX_kX86InstPFRSqrt 2408
+#define INDEX_kX86InstPFSub 2416
+#define INDEX_kX86InstPFSubR 2422
+#define INDEX_kX86InstPHAddD 2429
+#define INDEX_kX86InstPHAddSW 2436
+#define INDEX_kX86InstPHAddW 2444
+#define INDEX_kX86InstPHMinPOSUW 2451
+#define INDEX_kX86InstPHSubD 2462
+#define INDEX_kX86InstPHSubSW 2469
+#define INDEX_kX86InstPHSubW 2477
+#define INDEX_kX86InstPI2FD 2484
+#define INDEX_kX86InstPI2FW 2490
+#define INDEX_kX86InstPInsRB 2496
+#define INDEX_kX86InstPInsRD 2503
+#define INDEX_kX86InstPInsRQ 2510
+#define INDEX_kX86InstPInsRW 2517
+#define INDEX_kX86InstPMAddUBSW 2524
+#define INDEX_kX86InstPMAddWD 2534
+#define INDEX_kX86InstPMaxSB 2542
+#define INDEX_kX86InstPMaxSD 2549
+#define INDEX_kX86InstPMaxSW 2556
+#define INDEX_kX86InstPMaxUB 2563
+#define INDEX_kX86InstPMaxUD 2570
+#define INDEX_kX86InstPMaxUW 2577
+#define INDEX_kX86InstPMinSB 2584
+#define INDEX_kX86InstPMinSD 2591
+#define INDEX_kX86InstPMinSW 2598
+#define INDEX_kX86InstPMinUB 2605
+#define INDEX_kX86InstPMinUD 2612
+#define INDEX_kX86InstPMinUW 2619
+#define INDEX_kX86InstPMovMskB 2626
+#define INDEX_kX86InstPMovSXBD 2635
+#define INDEX_kX86InstPMovSXBQ 2644
+#define INDEX_kX86InstPMovSXBW 2653
+#define INDEX_kX86InstPMovSXDQ 2662
+#define INDEX_kX86InstPMovSXWD 2671
+#define INDEX_kX86InstPMovSXWQ 2680
+#define INDEX_kX86InstPMovZXBD 2689
+#define INDEX_kX86InstPMovZXBQ 2698
+#define INDEX_kX86InstPMovZXBW 2707
+#define INDEX_kX86InstPMovZXDQ 2716
+#define INDEX_kX86InstPMovZXWD 2725
+#define INDEX_kX86InstPMovZXWQ 2734
+#define INDEX_kX86InstPMulDQ 2743
+#define INDEX_kX86InstPMulHRSW 2750
+#define INDEX_kX86InstPMulHUW 2759
+#define INDEX_kX86InstPMulHW 2767
+#define INDEX_kX86InstPMulLD 2774
+#define INDEX_kX86InstPMulLW 2781
+#define INDEX_kX86InstPMulUDQ 2788
+#define INDEX_kX86InstPop 2796
+#define INDEX_kX86InstPopAD 2800
+#define INDEX_kX86InstPopCnt 2806
+#define INDEX_kX86InstPopFD 2813
+#define INDEX_kX86InstPopFQ 2819
+#define INDEX_kX86InstPOr 2825
+#define INDEX_kX86InstPrefetch 2829
+#define INDEX_kX86InstPSADBW 2838
+#define INDEX_kX86InstPShufB 2845
+#define INDEX_kX86InstPShufD 2852
+#define INDEX_kX86InstPShufW 2859
+#define INDEX_kX86InstPShufHW 2866
+#define INDEX_kX86InstPShufLW 2874
+#define INDEX_kX86InstPSignB 2882
+#define INDEX_kX86InstPSignD 2889
+#define INDEX_kX86InstPSignW 2896
+#define INDEX_kX86InstPSllD 2903
+#define INDEX_kX86InstPSllDQ 2909
+#define INDEX_kX86InstPSllQ 2916
+#define INDEX_kX86InstPSllW 2922
+#define INDEX_kX86InstPSraD 2928
+#define INDEX_kX86InstPSraW 2934
+#define INDEX_kX86InstPSrlD 2940
+#define INDEX_kX86InstPSrlDQ 2946
+#define INDEX_kX86InstPSrlQ 2953
+#define INDEX_kX86InstPSrlW 2959
+#define INDEX_kX86InstPSubB 2965
+#define INDEX_kX86InstPSubD 2971
+#define INDEX_kX86InstPSubQ 2977
+#define INDEX_kX86InstPSubSB 2983
+#define INDEX_kX86InstPSubSW 2990
+#define INDEX_kX86InstPSubUSB 2997
+#define INDEX_kX86InstPSubUSW 3005
+#define INDEX_kX86InstPSubW 3013
+#define INDEX_kX86InstPSwapD 3019
+#define INDEX_kX86InstPTest 3026
+#define INDEX_kX86InstPunpckHBW 3032
+#define INDEX_kX86InstPunpckHDQ 3042
+#define INDEX_kX86InstPunpckHQDQ 3052
+#define INDEX_kX86InstPunpckHWD 3063
+#define INDEX_kX86InstPunpckLBW 3073
+#define INDEX_kX86InstPunpckLDQ 3083
+#define INDEX_kX86InstPunpckLQDQ 3093
+#define INDEX_kX86InstPunpckLWD 3104
+#define INDEX_kX86InstPush 3114
+#define INDEX_kX86InstPushAD 3119
+#define INDEX_kX86InstPushFD 3126
+#define INDEX_kX86InstPushFQ 3133
+#define INDEX_kX86InstPXor 3140
+#define INDEX_kX86InstRcl 3145
+#define INDEX_kX86InstRcpPS 3149
+#define INDEX_kX86InstRcpSS 3155
+#define INDEX_kX86InstRcr 3161
+#define INDEX_kX86InstRdtsc 3165
+#define INDEX_kX86InstRdtscP 3171
+#define INDEX_kX86InstRepLodSB 3178
+#define INDEX_kX86InstRepLodSD 3188
+#define INDEX_kX86InstRepLodSQ 3198
+#define INDEX_kX86InstRepLodSW 3208
+#define INDEX_kX86InstRepMovSB 3218
+#define INDEX_kX86InstRepMovSD 3228
+#define INDEX_kX86InstRepMovSQ 3238
+#define INDEX_kX86InstRepMovSW 3248
+#define INDEX_kX86InstRepStoSB 3258
+#define INDEX_kX86InstRepStoSD 3268
+#define INDEX_kX86InstRepStoSQ 3278
+#define INDEX_kX86InstRepStoSW 3288
+#define INDEX_kX86InstRepECmpSB 3298
+#define INDEX_kX86InstRepECmpSD 3309
+#define INDEX_kX86InstRepECmpSQ 3320
+#define INDEX_kX86InstRepECmpSW 3331
+#define INDEX_kX86InstRepEScaSB 3342
+#define INDEX_kX86InstRepEScaSD 3353
+#define INDEX_kX86InstRepEScaSQ 3364
+#define INDEX_kX86InstRepEScaSW 3375
+#define INDEX_kX86InstRepNECmpSB 3386
+#define INDEX_kX86InstRepNECmpSD 3398
+#define INDEX_kX86InstRepNECmpSQ 3410
+#define INDEX_kX86InstRepNECmpSW 3422
+#define INDEX_kX86InstRepNEScaSB 3434
+#define INDEX_kX86InstRepNEScaSD 3446
+#define INDEX_kX86InstRepNEScaSQ 3458
+#define INDEX_kX86InstRepNEScaSW 3470
+#define INDEX_kX86InstRet 3482
+#define INDEX_kX86InstRol 3486
+#define INDEX_kX86InstRor 3490
+#define INDEX_kX86InstRoundPD 3494
+#define INDEX_kX86InstRoundPS 3502
+#define INDEX_kX86InstRoundSD 3510
+#define INDEX_kX86InstRoundSS 3518
+#define INDEX_kX86InstRSqrtPS 3526
+#define INDEX_kX86InstRSqrtSS 3534
+#define INDEX_kX86InstSahf 3542
+#define INDEX_kX86InstSal 3547
+#define INDEX_kX86InstSar 3551
+#define INDEX_kX86InstSbb 3555
+#define INDEX_kX86InstSetA 3559
+#define INDEX_kX86InstSetAE 3564
+#define INDEX_kX86InstSetB 3570
+#define INDEX_kX86InstSetBE 3575
+#define INDEX_kX86InstSetC 3581
+#define INDEX_kX86InstSetE 3586
+#define INDEX_kX86InstSetG 3591
+#define INDEX_kX86InstSetGE 3596
+#define INDEX_kX86InstSetL 3602
+#define INDEX_kX86InstSetLE 3607
+#define INDEX_kX86InstSetNA 3613
+#define INDEX_kX86InstSetNAE 3619
+#define INDEX_kX86InstSetNB 3626
+#define INDEX_kX86InstSetNBE 3632
+#define INDEX_kX86InstSetNC 3639
+#define INDEX_kX86InstSetNE 3645
+#define INDEX_kX86InstSetNG 3651
+#define INDEX_kX86InstSetNGE 3657
+#define INDEX_kX86InstSetNL 3664
+#define INDEX_kX86InstSetNLE 3670
+#define INDEX_kX86InstSetNO 3677
+#define INDEX_kX86InstSetNP 3683
+#define INDEX_kX86InstSetNS 3689
+#define INDEX_kX86InstSetNZ 3695
+#define INDEX_kX86InstSetO 3701
+#define INDEX_kX86InstSetP 3706
+#define INDEX_kX86InstSetPE 3711
+#define INDEX_kX86InstSetPO 3717
+#define INDEX_kX86InstSetS 3723
+#define INDEX_kX86InstSetZ 3728
+#define INDEX_kX86InstSFence 3733
+#define INDEX_kX86InstShl 3740
+#define INDEX_kX86InstShld 3744
+#define INDEX_kX86InstShr 3749
+#define INDEX_kX86InstShrd 3753
+#define INDEX_kX86InstShufPD 3758
+#define INDEX_kX86InstShufPS 3765
+#define INDEX_kX86InstSqrtPD 3772
+#define INDEX_kX86InstSqrtPS 3779
+#define INDEX_kX86InstSqrtSD 3786
+#define INDEX_kX86InstSqrtSS 3793
+#define INDEX_kX86InstStc 3800
+#define INDEX_kX86InstStd 3804
+#define INDEX_kX86InstStMXCSR 3808
+#define INDEX_kX86InstSub 3816
+#define INDEX_kX86InstSubPD 3820
+#define INDEX_kX86InstSubPS 3826
+#define INDEX_kX86InstSubSD 3832
+#define INDEX_kX86InstSubSS 3838
+#define INDEX_kX86InstTest 3844
+#define INDEX_kX86InstUComISD 3849
+#define INDEX_kX86InstUComISS 3857
+#define INDEX_kX86InstUd2 3865
+#define INDEX_kX86InstUnpckHPD 3869
+#define INDEX_kX86InstUnpckHPS 3878
+#define INDEX_kX86InstUnpckLPD 3887
+#define INDEX_kX86InstUnpckLPS 3896
+#define INDEX_kX86InstXadd 3905
+#define INDEX_kX86InstXchg 3910
+#define INDEX_kX86InstXor 3915
+#define INDEX_kX86InstXorPD 3919
+#define INDEX_kX86InstXorPS 3925
+// ${X86_INST_DATA:END}
+
+// ============================================================================
+// [AsmJit::x86InstInfo]
+// ============================================================================
+
+#define INST(_Code_, _Name_, _Group_, _Flags_, _OpFlags0_, _OpFlags1_, _OpReg_, _OpCode0_, _OpCode1_) \
+ { _Code_, INDEX_##_Code_, _Group_, _Flags_, { _OpFlags0_, _OpFlags1_ }, _OpReg_, { _OpCode0_, _OpCode1_ } }
+
+#define G(_Group_) kX86InstGroup##_Group_
+#define F(_Flags_) kX86InstFlag##_Flags_
+#define O(_Op_) kX86InstOp##_Op_
+
+const X86InstInfo x86InstInfo[] =
+{
+ // Instruction code | Instruction name | Instruction group| Instruction flags| Operand flags[0] | Operand flags[1] | r| opCode[0] | opcode[1]
+ INST(kInstNone , "" , G(None) , F(None) , 0 , 0 , 0, 0 , 0),
+ INST(kX86InstAdc , "adc" , G(Arith) , F(Lockable) , O(GqdwbMem) , O(GqdwbMem)|O(Imm) , 2, 0x00000010, 0x00000080),
+ INST(kX86InstAdd , "add" , G(Arith) , F(Lockable) , O(GqdwbMem) , O(GqdwbMem)|O(Imm) , 0, 0x00000000, 0x00000080),
+ INST(kX86InstAddPD , "addpd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000F58, 0),
+ INST(kX86InstAddPS , "addps" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x00000F58, 0),
+ INST(kX86InstAddSD , "addsd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF2000F58, 0),
+ INST(kX86InstAddSS , "addss" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF3000F58, 0),
+ INST(kX86InstAddSubPD , "addsubpd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000FD0, 0),
+ INST(kX86InstAddSubPS , "addsubps" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF2000FD0, 0),
+ INST(kX86InstAmdPrefetch , "amd_prefetch" , G(Mem) , F(None) , O(Mem) , 0 , 0, 0x00000F0D, 0),
+ INST(kX86InstAmdPrefetchW , "amd_prefetchw" , G(Mem) , F(None) , O(Mem) , 0 , 1, 0x00000F0D, 0),
+ INST(kX86InstAnd , "and" , G(Arith) , F(Lockable) , O(GqdwbMem) , O(GqdwbMem)|O(Imm) , 4, 0x00000020, 0x00000080),
+ INST(kX86InstAndnPD , "andnpd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000F55, 0),
+ INST(kX86InstAndnPS , "andnps" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x00000F55, 0),
+ INST(kX86InstAndPD , "andpd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000F54, 0),
+ INST(kX86InstAndPS , "andps" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x00000F54, 0),
+ INST(kX86InstBlendPD , "blendpd" , G(MmuRmImm8) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3A0D, 0),
+ INST(kX86InstBlendPS , "blendps" , G(MmuRmImm8) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3A0C, 0),
+ INST(kX86InstBlendVPD , "blendvpd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3815, 0),
+ INST(kX86InstBlendVPS , "blendvps" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3814, 0),
+ INST(kX86InstBsf , "bsf" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000FBC, 0),
+ INST(kX86InstBsr , "bsr" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000FBD, 0),
+ INST(kX86InstBSwap , "bswap" , G(BSwap) , F(None) , O(Gqd) , 0 , 0, 0 , 0),
+ INST(kX86InstBt , "bt" , G(BTest) , F(None) , O(Gqdw)|O(Mem) , O(Gqdw)|O(Imm) , 4, 0x00000FA3, 0x00000FBA),
+ INST(kX86InstBtc , "btc" , G(BTest) , F(Lockable) , O(Gqdw)|O(Mem) , O(Gqdw)|O(Imm) , 7, 0x00000FBB, 0x00000FBA),
+ INST(kX86InstBtr , "btr" , G(BTest) , F(Lockable) , O(Gqdw)|O(Mem) , O(Gqdw)|O(Imm) , 6, 0x00000FB3, 0x00000FBA),
+ INST(kX86InstBts , "bts" , G(BTest) , F(Lockable) , O(Gqdw)|O(Mem) , O(Gqdw)|O(Imm) , 5, 0x00000FAB, 0x00000FBA),
+ INST(kX86InstCall , "call" , G(Call) , F(Jump) , O(Gqd) |O(Mem) , 0 , 0, 0 , 0),
+ INST(kX86InstCbw , "cbw" , G(Emit) , F(Special) , 0 , 0 , 0, 0x66000098, 0),
+ INST(kX86InstCdq , "cdq" , G(Emit) , F(Special) , 0 , 0 , 0, 0x00000099, 0),
+ INST(kX86InstCdqe , "cdqe" , G(Emit) , F(Special) , 0 , 0 , 0, 0x48000098, 0),
+ INST(kX86InstClc , "clc" , G(Emit) , F(None) , 0 , 0 , 0, 0x000000F8, 0),
+ INST(kX86InstCld , "cld" , G(Emit) , F(None) , 0 , 0 , 0, 0x000000FC, 0),
+ INST(kX86InstClFlush , "clflush" , G(Mem) , F(None) , O(Mem) , 0 , 7, 0x00000FAE, 0),
+ INST(kX86InstCmc , "cmc" , G(Emit) , F(None) , 0 , 0 , 0, 0x000000F5, 0),
+ INST(kX86InstCMovA , "cmova" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F47, 0),
+ INST(kX86InstCMovAE , "cmovae" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F43, 0),
+ INST(kX86InstCMovB , "cmovb" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F42, 0),
+ INST(kX86InstCMovBE , "cmovbe" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F46, 0),
+ INST(kX86InstCMovC , "cmovc" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F42, 0),
+ INST(kX86InstCMovE , "cmove" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F44, 0),
+ INST(kX86InstCMovG , "cmovg" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F4F, 0),
+ INST(kX86InstCMovGE , "cmovge" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F4D, 0),
+ INST(kX86InstCMovL , "cmovl" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F4C, 0),
+ INST(kX86InstCMovLE , "cmovle" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F4E, 0),
+ INST(kX86InstCMovNA , "cmovna" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F46, 0),
+ INST(kX86InstCMovNAE , "cmovnae" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F42, 0),
+ INST(kX86InstCMovNB , "cmovnb" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F43, 0),
+ INST(kX86InstCMovNBE , "cmovnbe" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F47, 0),
+ INST(kX86InstCMovNC , "cmovnc" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F43, 0),
+ INST(kX86InstCMovNE , "cmovne" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F45, 0),
+ INST(kX86InstCMovNG , "cmovng" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F4E, 0),
+ INST(kX86InstCMovNGE , "cmovnge" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F4C, 0),
+ INST(kX86InstCMovNL , "cmovnl" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F4D, 0),
+ INST(kX86InstCMovNLE , "cmovnle" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F4F, 0),
+ INST(kX86InstCMovNO , "cmovno" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F41, 0),
+ INST(kX86InstCMovNP , "cmovnp" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F4B, 0),
+ INST(kX86InstCMovNS , "cmovns" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F49, 0),
+ INST(kX86InstCMovNZ , "cmovnz" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F45, 0),
+ INST(kX86InstCMovO , "cmovo" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F40, 0),
+ INST(kX86InstCMovP , "cmovp" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F4A, 0),
+ INST(kX86InstCMovPE , "cmovpe" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F4A, 0),
+ INST(kX86InstCMovPO , "cmovpo" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F4B, 0),
+ INST(kX86InstCMovS , "cmovs" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F48, 0),
+ INST(kX86InstCMovZ , "cmovz" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0x00000F44, 0),
+ INST(kX86InstCmp , "cmp" , G(Arith) , F(None) , O(GqdwbMem) , O(GqdwbMem)|O(Imm) , 7, 0x00000038, 0x00000080),
+ INST(kX86InstCmpPD , "cmppd" , G(MmuRmImm8) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000FC2, 0),
+ INST(kX86InstCmpPS , "cmpps" , G(MmuRmImm8) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x00000FC2, 0),
+ INST(kX86InstCmpSD , "cmpsd" , G(MmuRmImm8) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF2000FC2, 0),
+ INST(kX86InstCmpSS , "cmpss" , G(MmuRmImm8) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF3000FC2, 0),
+ INST(kX86InstCmpXCHG , "cmpxchg" , G(RmReg) , F(Special)|F(Lockable), 0 , 0 , 0, 0x00000FB0, 0),
+ INST(kX86InstCmpXCHG16B , "cmpxchg16b" , G(Mem) , F(Special) , O(Mem) , 0 , 1, 0x00000FC7, 1 /* RexW */),
+ INST(kX86InstCmpXCHG8B , "cmpxchg8b" , G(Mem) , F(Special) , O(Mem) , 0 , 1, 0x00000FC7, 0),
+ INST(kX86InstComISD , "comisd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000F2F, 0),
+ INST(kX86InstComISS , "comiss" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x00000F2F, 0),
+ INST(kX86InstCpuId , "cpuid" , G(Emit) , F(Special) , 0 , 0 , 0, 0x00000FA2, 0),
+ INST(kX86InstCqo , "cqo" , G(Emit) , F(Special) , 0 , 0 , 0, 0x48000099, 0), // TODO, set RexW bit instead?
+ INST(kX86InstCrc32 , "crc32" , G(Crc32) , F(None) , O(Gqd) , O(GqdwbMem) , 0, 0xF20F38F0, 0),
+ INST(kX86InstCvtDQ2PD , "cvtdq2pd" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0xF3000FE6, 0),
+ INST(kX86InstCvtDQ2PS , "cvtdq2ps" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x00000F5B, 0),
+ INST(kX86InstCvtPD2DQ , "cvtpd2dq" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0xF2000FE6, 0),
+ INST(kX86InstCvtPD2PI , "cvtpd2pi" , G(MmuRmI) , F(Mov) , O(Mm) , O(XmmMem) , 0, 0x66000F2D, 0),
+ INST(kX86InstCvtPD2PS , "cvtpd2ps" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x66000F5A, 0),
+ INST(kX86InstCvtPI2PD , "cvtpi2pd" , G(MmuRmI) , F(Mov) , O(Xmm) , O(MmMem) , 0, 0x66000F2A, 0),
+ INST(kX86InstCvtPI2PS , "cvtpi2ps" , G(MmuRmI) , F(None) , O(Xmm) , O(MmMem) , 0, 0x00000F2A, 0),
+ INST(kX86InstCvtPS2DQ , "cvtps2dq" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x66000F5B, 0),
+ INST(kX86InstCvtPS2PD , "cvtps2pd" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x00000F5A, 0),
+ INST(kX86InstCvtPS2PI , "cvtps2pi" , G(MmuRmI) , F(Mov) , O(Mm) , O(XmmMem) , 0, 0x00000F2D, 0),
+ INST(kX86InstCvtSD2SI , "cvtsd2si" , G(MmuRmI) , F(Mov) , O(Gqd) , O(XmmMem) , 0, 0xF2000F2D, 0),
+ INST(kX86InstCvtSD2SS , "cvtsd2ss" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF2000F5A, 0),
+ INST(kX86InstCvtSI2SD , "cvtsi2sd" , G(MmuRmI) , F(None) , O(Xmm) , O(Gqd)|O(Mem) , 0, 0xF2000F2A, 0),
+ INST(kX86InstCvtSI2SS , "cvtsi2ss" , G(MmuRmI) , F(None) , O(Xmm) , O(Gqd)|O(Mem) , 0, 0xF3000F2A, 0),
+ INST(kX86InstCvtSS2SD , "cvtss2sd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF3000F5A, 0),
+ INST(kX86InstCvtSS2SI , "cvtss2si" , G(MmuRmI) , F(None) , O(Gqd) , O(XmmMem) , 0, 0xF3000F2D, 0),
+ INST(kX86InstCvttPD2DQ , "cvttpd2dq" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x66000FE6, 0),
+ INST(kX86InstCvttPD2PI , "cvttpd2pi" , G(MmuRmI) , F(Mov) , O(Mm) , O(XmmMem) , 0, 0x66000F2C, 0),
+ INST(kX86InstCvttPS2DQ , "cvttps2dq" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0xF3000F5B, 0),
+ INST(kX86InstCvttPS2PI , "cvttps2pi" , G(MmuRmI) , F(Mov) , O(Mm) , O(XmmMem) , 0, 0x00000F2C, 0),
+ INST(kX86InstCvttSD2SI , "cvttsd2si" , G(MmuRmI) , F(None) , O(Gqd) , O(XmmMem) , 0, 0xF2000F2C, 0),
+ INST(kX86InstCvttSS2SI , "cvttss2si" , G(MmuRmI) , F(None) , O(Gqd) , O(XmmMem) , 0, 0xF3000F2C, 0),
+ INST(kX86InstCwd , "cwd" , G(Emit) , F(Special) , 0 , 0 , 0, 0x66000099, 0),
+ INST(kX86InstCwde , "cwde" , G(Emit) , F(Special) , 0 , 0 , 0, 0x00000098, 0),
+ INST(kX86InstDaa , "daa" , G(Emit) , F(Special) , 0 , 0 , 0, 0x00000027, 0),
+ INST(kX86InstDas , "das" , G(Emit) , F(Special) , 0 , 0 , 0, 0x0000002F, 0),
+ INST(kX86InstDec , "dec" , G(IncDec) , F(Lockable) , O(GqdwbMem) , 0 , 1, 0x00000048, 0x000000FE),
+ INST(kX86InstDiv , "div" , G(Rm) , F(Special) , 0 , 0 , 6, 0x000000F6, 0),
+ INST(kX86InstDivPD , "divpd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000F5E, 0),
+ INST(kX86InstDivPS , "divps" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x00000F5E, 0),
+ INST(kX86InstDivSD , "divsd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF2000F5E, 0),
+ INST(kX86InstDivSS , "divss" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF3000F5E, 0),
+ INST(kX86InstDpPD , "dppd" , G(MmuRmImm8) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3A41, 0),
+ INST(kX86InstDpPS , "dpps" , G(MmuRmImm8) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3A40, 0),
+ INST(kX86InstEmms , "emms" , G(Emit) , F(None) , 0 , 0 , 0, 0x00000F77, 0),
+ INST(kX86InstEnter , "enter" , G(Enter) , F(Special) , 0 , 0 , 0, 0x000000C8, 0),
+ INST(kX86InstExtractPS , "extractps" , G(MmuRmImm8) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3A17, 0),
+ INST(kX86InstF2XM1 , "f2xm1" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9F0, 0),
+ INST(kX86InstFAbs , "fabs" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9E1, 0),
+ INST(kX86InstFAdd , "fadd" , G(X87StM) , F(Fpu) , 0 , 0 , 0, 0xD8DCC0C0, 0),
+ INST(kX86InstFAddP , "faddp" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DEC0, 0),
+ INST(kX86InstFBLd , "fbld" , G(Mem) , F(Fpu) , O(Mem) , 0 , 4, 0x000000DF, 0),
+ INST(kX86InstFBStP , "fbstp" , G(Mem) , F(Fpu) , O(Mem) , 0 , 6, 0x000000DF, 0),
+ INST(kX86InstFCHS , "fchs" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9E0, 0),
+ INST(kX86InstFClex , "fclex" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x9B00DBE2, 0),
+ INST(kX86InstFCMovB , "fcmovb" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DAC0, 0),
+ INST(kX86InstFCMovBE , "fcmovbe" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DAD0, 0),
+ INST(kX86InstFCMovE , "fcmove" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DAC8, 0),
+ INST(kX86InstFCMovNB , "fcmovnb" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DBC0, 0),
+ INST(kX86InstFCMovNBE , "fcmovnbe" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DBD0, 0),
+ INST(kX86InstFCMovNE , "fcmovne" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DBC8, 0),
+ INST(kX86InstFCMovNU , "fcmovnu" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DBD8, 0),
+ INST(kX86InstFCMovU , "fcmovu" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DAD8, 0),
+ INST(kX86InstFCom , "fcom" , G(X87StM) , F(Fpu) , 0 , 0 , 2, 0xD8DCD0D0, 0),
+ INST(kX86InstFComI , "fcomi" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DBF0, 0),
+ INST(kX86InstFComIP , "fcomip" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DFF0, 0),
+ INST(kX86InstFComP , "fcomp" , G(X87StM) , F(Fpu) , 0 , 0 , 3, 0xD8DCD8D8, 0),
+ INST(kX86InstFComPP , "fcompp" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000DED9, 0),
+ INST(kX86InstFCos , "fcos" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9FF, 0),
+ INST(kX86InstFDecStP , "fdecstp" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9F6, 0),
+ INST(kX86InstFDiv , "fdiv" , G(X87StM) , F(Fpu) , 0 , 0 , 6, 0xD8DCF0F8, 0),
+ INST(kX86InstFDivP , "fdivp" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DEF8, 0),
+ INST(kX86InstFDivR , "fdivr" , G(X87StM) , F(Fpu) , 0 , 0 , 7, 0xD8DCF8F0, 0),
+ INST(kX86InstFDivRP , "fdivrp" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DEF0, 0),
+ INST(kX86InstFEmms , "femms" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x00000F0E, 0),
+ INST(kX86InstFFree , "ffree" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DDC0, 0),
+ INST(kX86InstFIAdd , "fiadd" , G(X87Mem) , F(Fpu) , O(StM2_4) , 0 , 0, 0xDEDA0000, 0),
+ INST(kX86InstFICom , "ficom" , G(X87Mem) , F(Fpu) , O(StM2_4) , 0 , 2, 0xDEDA0000, 0),
+ INST(kX86InstFIComP , "ficomp" , G(X87Mem) , F(Fpu) , O(StM2_4) , 0 , 3, 0xDEDA0000, 0),
+ INST(kX86InstFIDiv , "fidiv" , G(X87Mem) , F(Fpu) , O(StM2_4) , 0 , 6, 0xDEDA0000, 0),
+ INST(kX86InstFIDivR , "fidivr" , G(X87Mem) , F(Fpu) , O(StM2_4) , 0 , 7, 0xDEDA0000, 0),
+ INST(kX86InstFILd , "fild" , G(X87Mem) , F(Fpu) , O(StM2_4_8) , 0 , 0, 0xDFDBDF05, 0),
+ INST(kX86InstFIMul , "fimul" , G(X87Mem) , F(Fpu) , O(StM2_4) , 0 , 1, 0xDEDA0000, 0),
+ INST(kX86InstFIncStP , "fincstp" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9F7, 0),
+ INST(kX86InstFInit , "finit" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x9B00DBE3, 0),
+ INST(kX86InstFISt , "fist" , G(X87Mem) , F(Fpu) , O(StM2_4) , 0 , 2, 0xDFDB0000, 0),
+ INST(kX86InstFIStP , "fistp" , G(X87Mem) , F(Fpu) , O(StM2_4_8) , 0 , 3, 0xDFDBDF07, 0),
+ INST(kX86InstFISttP , "fisttp" , G(X87Mem) , F(Fpu) , O(StM2_4_8) , 0 , 1, 0xDFDBDD01, 0),
+ INST(kX86InstFISub , "fisub" , G(X87Mem) , F(Fpu) , O(StM2_4) , 0 , 4, 0xDEDA0000, 0),
+ INST(kX86InstFISubR , "fisubr" , G(X87Mem) , F(Fpu) , O(StM2_4) , 0 , 5, 0xDEDA0000, 0),
+ INST(kX86InstFLd , "fld" , G(X87FldFst) , F(Fpu) , O(StM4_8_10) , 0 , 0, 0x00D9DD00, 0xD9C0DB05),
+ INST(kX86InstFLd1 , "fld1" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9E8, 0),
+ INST(kX86InstFLdCw , "fldcw" , G(Mem) , F(Fpu) , O(Mem) , 0 , 5, 0x000000D9, 0),
+ INST(kX86InstFLdEnv , "fldenv" , G(Mem) , F(Fpu) , O(Mem) , 0 , 4, 0x000000D9, 0),
+ INST(kX86InstFLdL2E , "fldl2e" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9EA, 0),
+ INST(kX86InstFLdL2T , "fldl2t" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9E9, 0),
+ INST(kX86InstFLdLg2 , "fldlg2" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9EC, 0),
+ INST(kX86InstFLdLn2 , "fldln2" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9ED, 0),
+ INST(kX86InstFLdPi , "fldpi" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9EB, 0),
+ INST(kX86InstFLdZ , "fldz" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9EE, 0),
+ INST(kX86InstFMul , "fmul" , G(X87StM) , F(Fpu) , 0 , 0 , 1, 0xD8DCC8C8, 0),
+ INST(kX86InstFMulP , "fmulp" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DEC8, 0),
+ INST(kX86InstFNClex , "fnclex" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000DBE2, 0),
+ INST(kX86InstFNInit , "fninit" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000DBE3, 0),
+ INST(kX86InstFNop , "fnop" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9D0, 0),
+ INST(kX86InstFNSave , "fnsave" , G(Mem) , F(Fpu) , O(Mem) , 0 , 6, 0x000000DD, 0),
+ INST(kX86InstFNStCw , "fnstcw" , G(Mem) , F(Fpu) , O(Mem) , 0 , 7, 0x000000D9, 0),
+ INST(kX86InstFNStEnv , "fnstenv" , G(Mem) , F(Fpu) , O(Mem) , 0 , 6, 0x000000D9, 0),
+ INST(kX86InstFNStSw , "fnstsw" , G(X87Status) , F(Fpu) , O(Mem) , 0 , 7, 0x000000DD, 0x0000DFE0),
+ INST(kX86InstFPAtan , "fpatan" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9F3, 0),
+ INST(kX86InstFPRem , "fprem" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9F8, 0),
+ INST(kX86InstFPRem1 , "fprem1" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9F5, 0),
+ INST(kX86InstFPTan , "fptan" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9F2, 0),
+ INST(kX86InstFRndInt , "frndint" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9FC, 0),
+ INST(kX86InstFRstor , "frstor" , G(Mem) , F(Fpu) , O(Mem) , 0 , 4, 0x000000DD, 0),
+ INST(kX86InstFSave , "fsave" , G(Mem) , F(Fpu) , O(Mem) , 0 , 6, 0x9B0000DD, 0),
+ INST(kX86InstFScale , "fscale" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9FD, 0),
+ INST(kX86InstFSin , "fsin" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9FE, 0),
+ INST(kX86InstFSinCos , "fsincos" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9FB, 0),
+ INST(kX86InstFSqrt , "fsqrt" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9FA, 0),
+ INST(kX86InstFSt , "fst" , G(X87FldFst) , F(Fpu) , O(StM4_8) , 0 , 2, 0x00D9DD02, 0xDDD00000),
+ INST(kX86InstFStCw , "fstcw" , G(Mem) , F(Fpu) , O(Mem) , 0 , 7, 0x9B0000D9, 0),
+ INST(kX86InstFStEnv , "fstenv" , G(Mem) , F(Fpu) , O(Mem) , 0 , 6, 0x9B0000D9, 0),
+ INST(kX86InstFStP , "fstp" , G(X87FldFst) , F(Fpu) , O(StM4_8_10) , 0 , 3, 0x00D9DD03, 0xDDD8DB07),
+ INST(kX86InstFStSw , "fstsw" , G(X87Status) , F(Fpu) , O(Mem) , 0 , 7, 0x9B0000DD, 0x9B00DFE0),
+ INST(kX86InstFSub , "fsub" , G(X87StM) , F(Fpu) , 0 , 0 , 4, 0xD8DCE0E8, 0),
+ INST(kX86InstFSubP , "fsubp" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DEE8, 0),
+ INST(kX86InstFSubR , "fsubr" , G(X87StM) , F(Fpu) , 0 , 0 , 5, 0xD8DCE8E0, 0),
+ INST(kX86InstFSubRP , "fsubrp" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DEE0, 0),
+ INST(kX86InstFTst , "ftst" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9E4, 0),
+ INST(kX86InstFUCom , "fucom" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DDE0, 0),
+ INST(kX86InstFUComI , "fucomi" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DBE8, 0),
+ INST(kX86InstFUComIP , "fucomip" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DFE8, 0),
+ INST(kX86InstFUComP , "fucomp" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000DDE8, 0),
+ INST(kX86InstFUComPP , "fucompp" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000DAE9, 0),
+ INST(kX86InstFWait , "fwait" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x000000DB, 0),
+ INST(kX86InstFXam , "fxam" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9E5, 0),
+ INST(kX86InstFXch , "fxch" , G(X87StI) , F(Fpu) , 0 , 0 , 0, 0x0000D9C8, 0),
+ INST(kX86InstFXRstor , "fxrstor" , G(Mem) , F(Fpu) , 0 , 0 , 1, 0x00000FAE, 0),
+ INST(kX86InstFXSave , "fxsave" , G(Mem) , F(Fpu) , 0 , 0 , 0, 0x00000FAE, 0),
+ INST(kX86InstFXtract , "fxtract" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9F4, 0),
+ INST(kX86InstFYL2X , "fyl2x" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9F1, 0),
+ INST(kX86InstFYL2XP1 , "fyl2xp1" , G(Emit) , F(Fpu) , 0 , 0 , 0, 0x0000D9F9, 0),
+ INST(kX86InstHAddPD , "haddpd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000F7C, 0),
+ INST(kX86InstHAddPS , "haddps" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF2000F7C, 0),
+ INST(kX86InstHSubPD , "hsubpd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000F7D, 0),
+ INST(kX86InstHSubPS , "hsubps" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF2000F7D, 0),
+ INST(kX86InstIDiv , "idiv" , G(Rm) , F(Special) , 0 , 0 , 7, 0x000000F6, 0),
+ INST(kX86InstIMul , "imul" , G(IMul) , F(Special) , 0 , 0 , 0, 0 , 0),
+ INST(kX86InstInc , "inc" , G(IncDec) , F(Lockable) , O(GqdwbMem) , 0 , 0, 0x00000040, 0x000000FE),
+ INST(kX86InstInt3 , "int3" , G(Emit) , F(None) , 0 , 0 , 0, 0x000000CC, 0),
+ INST(kX86InstJA , "ja" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0x7 , 0),
+ INST(kX86InstJAE , "jae" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0x3 , 0),
+ INST(kX86InstJB , "jb" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0x2 , 0),
+ INST(kX86InstJBE , "jbe" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0x6 , 0),
+ INST(kX86InstJC , "jc" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0x2 , 0),
+ INST(kX86InstJE , "je" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0x4 , 0),
+ INST(kX86InstJG , "jg" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0xF , 0),
+ INST(kX86InstJGE , "jge" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0xD , 0),
+ INST(kX86InstJL , "jl" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0xC , 0),
+ INST(kX86InstJLE , "jle" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0xE , 0),
+ INST(kX86InstJNA , "jna" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0x6 , 0),
+ INST(kX86InstJNAE , "jnae" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0x2 , 0),
+ INST(kX86InstJNB , "jnb" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0x3 , 0),
+ INST(kX86InstJNBE , "jnbe" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0x7 , 0),
+ INST(kX86InstJNC , "jnc" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0x3 , 0),
+ INST(kX86InstJNE , "jne" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0x5 , 0),
+ INST(kX86InstJNG , "jng" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0xE , 0),
+ INST(kX86InstJNGE , "jnge" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0xC , 0),
+ INST(kX86InstJNL , "jnl" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0xD , 0),
+ INST(kX86InstJNLE , "jnle" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0xF , 0),
+ INST(kX86InstJNO , "jno" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0x1 , 0),
+ INST(kX86InstJNP , "jnp" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0xB , 0),
+ INST(kX86InstJNS , "jns" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0x9 , 0),
+ INST(kX86InstJNZ , "jnz" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0x5 , 0),
+ INST(kX86InstJO , "jo" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0x0 , 0),
+ INST(kX86InstJP , "jp" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0xA , 0),
+ INST(kX86InstJPE , "jpe" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0xA , 0),
+ INST(kX86InstJPO , "jpo" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0xB , 0),
+ INST(kX86InstJS , "js" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0x8 , 0),
+ INST(kX86InstJZ , "jz" , G(Jcc) , F(Jump) , 0 , 0 , 0, 0x4 , 0),
+ INST(kX86InstJmp , "jmp" , G(Jmp) , F(Jump) , 0 , 0 , 0, 0 , 0),
+ INST(kX86InstLdDQU , "lddqu" , G(MmuRmI) , F(None) , O(Xmm) , O(Mem) , 0, 0xF2000FF0, 0),
+ INST(kX86InstLdMXCSR , "ldmxcsr" , G(Mem) , F(None) , O(Mem) , 0 , 2, 0x00000FAE, 0),
+ INST(kX86InstLahf , "lahf" , G(Emit) , F(Special) , 0 , 0 , 0, 0x0000009F, 0),
+ INST(kX86InstLea , "lea" , G(Lea) , F(None) , O(Gqd) , O(Mem) , 0, 0 , 0),
+ INST(kX86InstLeave , "leave" , G(Emit) , F(Special) , 0 , 0 , 0, 0x000000C9, 0),
+ INST(kX86InstLFence , "lfence" , G(Emit) , F(None) , 0 , 0 , 0, 0x000FAEE8, 0),
+ INST(kX86InstMaskMovDQU , "maskmovdqu" , G(MmuRmI) , F(Special) , O(Xmm) , O(Xmm) , 0, 0x66000F57, 0),
+ INST(kX86InstMaskMovQ , "maskmovq" , G(MmuRmI) , F(Special) , O(Mm) , O(Mm) , 0, 0x00000FF7, 0),
+ INST(kX86InstMaxPD , "maxpd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000F5F, 0),
+ INST(kX86InstMaxPS , "maxps" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x00000F5F, 0),
+ INST(kX86InstMaxSD , "maxsd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF2000F5F, 0),
+ INST(kX86InstMaxSS , "maxss" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF3000F5F, 0),
+ INST(kX86InstMFence , "mfence" , G(Emit) , F(None) , 0 , 0 , 0, 0x000FAEF0, 0),
+ INST(kX86InstMinPD , "minpd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000F5D, 0),
+ INST(kX86InstMinPS , "minps" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x00000F5D, 0),
+ INST(kX86InstMinSD , "minsd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF2000F5D, 0),
+ INST(kX86InstMinSS , "minss" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF3000F5D, 0),
+ INST(kX86InstMonitor , "monitor" , G(Emit) , F(Special) , 0 , 0 , 0, 0x000F01C8, 0),
+ INST(kX86InstMov , "mov" , G(Mov) , F(Mov) , O(GqdwbMem) , O(GqdwbMem)|O(Imm) , 0, 0 , 0),
+ INST(kX86InstMovAPD , "movapd" , G(MmuMov) , F(Mov) , O(XmmMem) , O(XmmMem) , 0, 0x66000F28, 0x66000F29),
+ INST(kX86InstMovAPS , "movaps" , G(MmuMov) , F(Mov) , O(XmmMem) , O(XmmMem) , 0, 0x00000F28, 0x00000F29),
+ INST(kX86InstMovBE , "movbe" , G(MovBE) , F(Mov) , O(Gqdw)|O(Mem) , O(Gqdw)|O(Mem) , 0, 0x000F38F0, 0x000F38F1),
+ INST(kX86InstMovD , "movd" , G(MmuMovD) , F(Mov) , O(Gd)|O(MmXmmMem) , O(Gd)|O(MmXmmMem) , 0, 0 , 0),
+ INST(kX86InstMovDDup , "movddup" , G(MmuMov) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0xF2000F12, 0),
+ INST(kX86InstMovDQ2Q , "movdq2q" , G(MmuMov) , F(Mov) , O(Mm) , O(Xmm) , 0, 0xF2000FD6, 0),
+ INST(kX86InstMovDQA , "movdqa" , G(MmuMov) , F(Mov) , O(XmmMem) , O(XmmMem) , 0, 0x66000F6F, 0x66000F7F),
+ INST(kX86InstMovDQU , "movdqu" , G(MmuMov) , F(Mov) , O(XmmMem) , O(XmmMem) , 0, 0xF3000F6F, 0xF3000F7F),
+ INST(kX86InstMovHLPS , "movhlps" , G(MmuMov) , F(None) , O(Xmm) , O(Xmm) , 0, 0x00000F12, 0),
+ INST(kX86InstMovHPD , "movhpd" , G(MmuMov) , F(None) , O(XmmMem) , O(XmmMem) , 0, 0x66000F16, 0x66000F17),
+ INST(kX86InstMovHPS , "movhps" , G(MmuMov) , F(None) , O(XmmMem) , O(XmmMem) , 0, 0x00000F16, 0x00000F17),
+ INST(kX86InstMovLHPS , "movlhps" , G(MmuMov) , F(None) , O(Xmm) , O(Xmm) , 0, 0x00000F16, 0),
+ INST(kX86InstMovLPD , "movlpd" , G(MmuMov) , F(None) , O(XmmMem) , O(XmmMem) , 0, 0x66000F12, 0x66000F13),
+ INST(kX86InstMovLPS , "movlps" , G(MmuMov) , F(None) , O(XmmMem) , O(XmmMem) , 0, 0x00000F12, 0x00000F13),
+ INST(kX86InstMovMskPD , "movmskpd" , G(MmuMov) , F(Mov) , O(Gqd)|O(NoRex) , O(Xmm) , 0, 0x66000F50, 0),
+ INST(kX86InstMovMskPS , "movmskps" , G(MmuMov) , F(Mov) , O(Gqd)|O(NoRex) , O(Xmm) , 0, 0x00000F50, 0),
+ INST(kX86InstMovNTDQ , "movntdq" , G(MmuMov) , F(None) , O(Mem) , O(Xmm) , 0, 0 , 0x66000FE7),
+ INST(kX86InstMovNTDQA , "movntdqa" , G(MmuMov) , F(Mov) , O(Xmm) , O(Mem) , 0, 0x660F382A, 0),
+ INST(kX86InstMovNTI , "movnti" , G(MmuMov) , F(Mov) , O(Mem) , O(Gqd) , 0, 0 , 0x00000FC3),
+ INST(kX86InstMovNTPD , "movntpd" , G(MmuMov) , F(None) , O(Mem) , O(Xmm) , 0, 0 , 0x66000F2B),
+ INST(kX86InstMovNTPS , "movntps" , G(MmuMov) , F(None) , O(Mem) , O(Xmm) , 0, 0 , 0x00000F2B),
+ INST(kX86InstMovNTQ , "movntq" , G(MmuMov) , F(None) , O(Mem) , O(Mm) , 0, 0 , 0x00000FE7),
+ INST(kX86InstMovQ , "movq" , G(MmuMovQ) , F(Mov) , O(Gq)|O(MmXmmMem) , O(Gq)|O(MmXmmMem) , 0, 0 , 0),
+ INST(kX86InstMovQ2DQ , "movq2dq" , G(MmuRmI) , F(Mov) , O(Xmm) , O(Mm) , 0, 0xF3000FD6, 0),
+ INST(kX86InstMovSD , "movsd" , G(MmuMov) , F(None) , O(XmmMem) , O(XmmMem) , 0, 0xF2000F10, 0xF2000F11),
+ INST(kX86InstMovSHDup , "movshdup" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0xF3000F16, 0),
+ INST(kX86InstMovSLDup , "movsldup" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0xF3000F12, 0),
+ INST(kX86InstMovSS , "movss" , G(MmuMov) , F(None) , O(XmmMem) , O(XmmMem) , 0, 0xF3000F10, 0xF3000F11),
+ INST(kX86InstMovSX , "movsx" , G(MovSxMovZx) , F(None) , O(Gqdw) , O(GwbMem) , 0, 0x00000FBE, 0),
+ INST(kX86InstMovSXD , "movsxd" , G(MovSxD) , F(None) , O(Gq) , O(GdMem) , 0, 0 , 0),
+ INST(kX86InstMovUPD , "movupd" , G(MmuMov) , F(Mov) , O(XmmMem) , O(XmmMem) , 0, 0x66000F10, 0x66000F11),
+ INST(kX86InstMovUPS , "movups" , G(MmuMov) , F(Mov) , O(XmmMem) , O(XmmMem) , 0, 0x00000F10, 0x00000F11),
+ INST(kX86InstMovZX , "movzx" , G(MovSxMovZx) , F(Mov) , O(Gqdw) , O(GwbMem) , 0, 0x00000FB6, 0),
+ INST(kX86InstMovPtr , "mov_ptr" , G(MovPtr) , F(Mov)|F(Special), O(Gqdwb) , O(Imm) , 0, 0 , 0),
+ INST(kX86InstMPSADBW , "mpsadbw" , G(MmuRmImm8) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3A42, 0),
+ INST(kX86InstMul , "mul" , G(Rm) , F(Special) , 0 , 0 , 4, 0x000000F6, 0),
+ INST(kX86InstMulPD , "mulpd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000F59, 0),
+ INST(kX86InstMulPS , "mulps" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x00000F59, 0),
+ INST(kX86InstMulSD , "mulsd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF2000F59, 0),
+ INST(kX86InstMulSS , "mulss" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF3000F59, 0),
+ INST(kX86InstMWait , "mwait" , G(Emit) , F(Special) , 0 , 0 , 0, 0x000F01C9, 0),
+ INST(kX86InstNeg , "neg" , G(Rm) , F(Lockable) , O(GqdwbMem) , 0 , 3, 0x000000F6, 0),
+ INST(kX86InstNop , "nop" , G(Emit) , F(None) , 0 , 0 , 0, 0x00000090, 0),
+ INST(kX86InstNot , "not" , G(Rm) , F(Lockable) , O(GqdwbMem) , 0 , 2, 0x000000F6, 0),
+ INST(kX86InstOr , "or" , G(Arith) , F(Lockable) , O(GqdwbMem) , O(GqdwbMem)|O(Imm) , 1, 0x00000008, 0x00000080),
+ INST(kX86InstOrPD , "orpd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000F56, 0),
+ INST(kX86InstOrPS , "orps" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x00000F56, 0),
+ INST(kX86InstPAbsB , "pabsb" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x000F381C, 0),
+ INST(kX86InstPAbsD , "pabsd" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x000F381E, 0),
+ INST(kX86InstPAbsW , "pabsw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x000F381D, 0),
+ INST(kX86InstPackSSDW , "packssdw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000F6B, 0),
+ INST(kX86InstPackSSWB , "packsswb" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000F63, 0),
+ INST(kX86InstPackUSDW , "packusdw" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F382B, 0),
+ INST(kX86InstPackUSWB , "packuswb" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000F67, 0),
+ INST(kX86InstPAddB , "paddb" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FFC, 0),
+ INST(kX86InstPAddD , "paddd" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FFE, 0),
+ INST(kX86InstPAddQ , "paddq" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FD4, 0),
+ INST(kX86InstPAddSB , "paddsb" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FEC, 0),
+ INST(kX86InstPAddSW , "paddsw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FED, 0),
+ INST(kX86InstPAddUSB , "paddusb" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FDC, 0),
+ INST(kX86InstPAddUSW , "paddusw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FDD, 0),
+ INST(kX86InstPAddW , "paddw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FFD, 0),
+ INST(kX86InstPAlignR , "palignr" , G(MmuRmImm8) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x000F3A0F, 0),
+ INST(kX86InstPAnd , "pand" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FDB, 0),
+ INST(kX86InstPAndN , "pandn" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FDF, 0),
+ INST(kX86InstPause , "pause" , G(Emit) , F(None) , 0 , 0 , 0, 0xF3000090, 0),
+ INST(kX86InstPAvgB , "pavgb" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FE0, 0),
+ INST(kX86InstPAvgW , "pavgw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FE3, 0),
+ INST(kX86InstPBlendVB , "pblendvb" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3810, 0),
+ INST(kX86InstPBlendW , "pblendw" , G(MmuRmImm8) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3A0E, 0),
+ INST(kX86InstPCmpEqB , "pcmpeqb" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000F74, 0),
+ INST(kX86InstPCmpEqD , "pcmpeqd" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000F76, 0),
+ INST(kX86InstPCmpEqQ , "pcmpeqq" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3829, 0),
+ INST(kX86InstPCmpEqW , "pcmpeqw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000F75, 0),
+ INST(kX86InstPCmpEStrI , "pcmpestri" , G(MmuRmImm8) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3A61, 0),
+ INST(kX86InstPCmpEStrM , "pcmpestrm" , G(MmuRmImm8) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3A60, 0),
+ INST(kX86InstPCmpGtB , "pcmpgtb" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000F64, 0),
+ INST(kX86InstPCmpGtD , "pcmpgtd" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000F66, 0),
+ INST(kX86InstPCmpGtQ , "pcmpgtq" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3837, 0),
+ INST(kX86InstPCmpGtW , "pcmpgtw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000F65, 0),
+ INST(kX86InstPCmpIStrI , "pcmpistri" , G(MmuRmImm8) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3A63, 0),
+ INST(kX86InstPCmpIStrM , "pcmpistrm" , G(MmuRmImm8) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3A62, 0),
+ INST(kX86InstPExtrB , "pextrb" , G(MmuExtract) , F(None) , O(Gd)|O(Gb)|O(Mem) , O(Xmm) , 0, 0x000F3A14, 0),
+ INST(kX86InstPExtrD , "pextrd" , G(MmuExtract) , F(None) , O(Gd) |O(Mem) , O(Xmm) , 0, 0x000F3A16, 0),
+ INST(kX86InstPExtrQ , "pextrq" , G(MmuExtract) , F(None) , O(Gqd) |O(Mem) , O(Xmm) , 1, 0x000F3A16, 0),
+ INST(kX86InstPExtrW , "pextrw" , G(MmuExtract) , F(None) , O(Gd) |O(Mem) , O(MmXmm) , 0, 0x000F3A15, 0),
+ INST(kX86InstPF2ID , "pf2id" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0x1D),
+ INST(kX86InstPF2IW , "pf2iw" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0x1C),
+ INST(kX86InstPFAcc , "pfacc" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0xAE),
+ INST(kX86InstPFAdd , "pfadd" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0x9E),
+ INST(kX86InstPFCmpEQ , "pfcmpeq" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0xB0),
+ INST(kX86InstPFCmpGE , "pfcmpge" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0x90),
+ INST(kX86InstPFCmpGT , "pfcmpgt" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0xA0),
+ INST(kX86InstPFMax , "pfmax" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0xA4),
+ INST(kX86InstPFMin , "pfmin" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0x94),
+ INST(kX86InstPFMul , "pfmul" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0xB4),
+ INST(kX86InstPFNAcc , "pfnacc" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0x8A),
+ INST(kX86InstPFPNAcc , "pfpnacc" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0x8E),
+ INST(kX86InstPFRcp , "pfrcp" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0x96),
+ INST(kX86InstPFRcpIt1 , "pfrcpit1" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0xA6),
+ INST(kX86InstPFRcpIt2 , "pfrcpit2" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0xB6),
+ INST(kX86InstPFRSqIt1 , "pfrsqit1" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0xA7),
+ INST(kX86InstPFRSqrt , "pfrsqrt" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0x97),
+ INST(kX86InstPFSub , "pfsub" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0x9A),
+ INST(kX86InstPFSubR , "pfsubr" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0xAA),
+ INST(kX86InstPHAddD , "phaddd" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x000F3802, 0),
+ INST(kX86InstPHAddSW , "phaddsw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x000F3803, 0),
+ INST(kX86InstPHAddW , "phaddw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x000F3801, 0),
+ INST(kX86InstPHMinPOSUW , "phminposuw" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3841, 0),
+ INST(kX86InstPHSubD , "phsubd" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x000F3806, 0),
+ INST(kX86InstPHSubSW , "phsubsw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x000F3807, 0),
+ INST(kX86InstPHSubW , "phsubw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x000F3805, 0),
+ INST(kX86InstPI2FD , "pi2fd" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0x0D),
+ INST(kX86InstPI2FW , "pi2fw" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0x0C),
+ INST(kX86InstPInsRB , "pinsrb" , G(MmuRmImm8) , F(None) , O(Xmm) , O(Gd) | O(Mem) , 0, 0x660F3A20, 0),
+ INST(kX86InstPInsRD , "pinsrd" , G(MmuRmImm8) , F(None) , O(Xmm) , O(Gd) | O(Mem) , 0, 0x660F3A22, 0),
+ INST(kX86InstPInsRQ , "pinsrq" , G(MmuRmImm8) , F(None) , O(Xmm) , O(Gq) | O(Mem) , 0, 0x660F3A22, 0),
+ INST(kX86InstPInsRW , "pinsrw" , G(MmuRmImm8) , F(None) , O(MmXmm) , O(Gd) | O(Mem) , 0, 0x00000FC4, 0),
+ INST(kX86InstPMAddUBSW , "pmaddubsw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x000F3804, 0),
+ INST(kX86InstPMAddWD , "pmaddwd" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FF5, 0),
+ INST(kX86InstPMaxSB , "pmaxsb" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F383C, 0),
+ INST(kX86InstPMaxSD , "pmaxsd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F383D, 0),
+ INST(kX86InstPMaxSW , "pmaxsw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FEE, 0),
+ INST(kX86InstPMaxUB , "pmaxub" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FDE, 0),
+ INST(kX86InstPMaxUD , "pmaxud" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F383F, 0),
+ INST(kX86InstPMaxUW , "pmaxuw" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F383E, 0),
+ INST(kX86InstPMinSB , "pminsb" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3838, 0),
+ INST(kX86InstPMinSD , "pminsd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3839, 0),
+ INST(kX86InstPMinSW , "pminsw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FEA, 0),
+ INST(kX86InstPMinUB , "pminub" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FDA, 0),
+ INST(kX86InstPMinUD , "pminud" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F383B, 0),
+ INST(kX86InstPMinUW , "pminuw" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F383A, 0),
+ INST(kX86InstPMovMskB , "pmovmskb" , G(MmuRmI) , F(Mov) , O(Gqd) , O(MmXmm) , 0, 0x00000FD7, 0),
+ INST(kX86InstPMovSXBD , "pmovsxbd" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x660F3821, 0),
+ INST(kX86InstPMovSXBQ , "pmovsxbq" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x660F3822, 0),
+ INST(kX86InstPMovSXBW , "pmovsxbw" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x660F3820, 0),
+ INST(kX86InstPMovSXDQ , "pmovsxdq" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x660F3825, 0),
+ INST(kX86InstPMovSXWD , "pmovsxwd" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x660F3823, 0),
+ INST(kX86InstPMovSXWQ , "pmovsxwq" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x660F3824, 0),
+ INST(kX86InstPMovZXBD , "pmovzxbd" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x660F3831, 0),
+ INST(kX86InstPMovZXBQ , "pmovzxbq" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x660F3832, 0),
+ INST(kX86InstPMovZXBW , "pmovzxbw" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x660F3830, 0),
+ INST(kX86InstPMovZXDQ , "pmovzxdq" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x660F3835, 0),
+ INST(kX86InstPMovZXWD , "pmovzxwd" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x660F3833, 0),
+ INST(kX86InstPMovZXWQ , "pmovzxwq" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x660F3834, 0),
+ INST(kX86InstPMulDQ , "pmuldq" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3828, 0),
+ INST(kX86InstPMulHRSW , "pmulhrsw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x000F380B, 0),
+ INST(kX86InstPMulHUW , "pmulhuw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FE4, 0),
+ INST(kX86InstPMulHW , "pmulhw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FE5, 0),
+ INST(kX86InstPMulLD , "pmulld" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3840, 0),
+ INST(kX86InstPMulLW , "pmullw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FD5, 0),
+ INST(kX86InstPMulUDQ , "pmuludq" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FF4, 0),
+ INST(kX86InstPop , "pop" , G(Pop) , F(Special) , 0 , 0 , 0, 0x00000058, 0x0000008F),
+ INST(kX86InstPopAD , "popad" , G(Emit) , F(Special) , 0 , 0 , 0, 0x00000061, 0),
+ INST(kX86InstPopCnt , "popcnt" , G(RegRm) , F(None) , O(Gqdw) , O(GqdwMem) , 0, 0xF3000FB8, 0),
+ INST(kX86InstPopFD , "popfd" , G(Emit) , F(Special) , 0 , 0 , 0, 0x0000009D, 0),
+ INST(kX86InstPopFQ , "popfq" , G(Emit) , F(Special) , 0 , 0 , 0, 0x0000009D, 0),
+ INST(kX86InstPOr , "por" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FEB, 0),
+ INST(kX86InstPrefetch , "prefetch" , G(MmuPrefetch) , F(None) , O(Mem) , O(Imm) , 0, 0 , 0),
+ INST(kX86InstPSADBW , "psadbw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FF6, 0),
+ INST(kX86InstPShufB , "pshufb" , G(MmuRmI) , F(Mov) , O(MmXmm) , O(MmXmmMem) , 0, 0x000F3800, 0),
+ INST(kX86InstPShufD , "pshufd" , G(MmuRmImm8) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x66000F70, 0),
+ INST(kX86InstPShufW , "pshufw" , G(MmuRmImm8) , F(Mov) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000F70, 0),
+ INST(kX86InstPShufHW , "pshufhw" , G(MmuRmImm8) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0xF3000F70, 0),
+ INST(kX86InstPShufLW , "pshuflw" , G(MmuRmImm8) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0xF2000F70, 0),
+ INST(kX86InstPSignB , "psignb" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x000F3808, 0),
+ INST(kX86InstPSignD , "psignd" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x000F380A, 0),
+ INST(kX86InstPSignW , "psignw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x000F3809, 0),
+ INST(kX86InstPSllD , "pslld" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem)|O(Imm) , 6, 0x00000FF2, 0x00000F72),
+ INST(kX86InstPSllDQ , "pslldq" , G(MmuRmI) , F(None) , O(Xmm) , O(Imm) , 7, 0 , 0x66000F73),
+ INST(kX86InstPSllQ , "psllq" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem)|O(Imm) , 6, 0x00000FF3, 0x00000F73),
+ INST(kX86InstPSllW , "psllw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem)|O(Imm) , 6, 0x00000FF1, 0x00000F71),
+ INST(kX86InstPSraD , "psrad" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem)|O(Imm) , 4, 0x00000FE2, 0x00000F72),
+ INST(kX86InstPSraW , "psraw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem)|O(Imm) , 4, 0x00000FE1, 0x00000F71),
+ INST(kX86InstPSrlD , "psrld" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem)|O(Imm) , 2, 0x00000FD2, 0x00000F72),
+ INST(kX86InstPSrlDQ , "psrldq" , G(MmuRmI) , F(None) , O(Xmm) , O(Imm) , 3, 0 , 0x66000F73),
+ INST(kX86InstPSrlQ , "psrlq" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem)|O(Imm) , 2, 0x00000FD3, 0x00000F73),
+ INST(kX86InstPSrlW , "psrlw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem)|O(Imm) , 2, 0x00000FD1, 0x00000F71),
+ INST(kX86InstPSubB , "psubb" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FF8, 0),
+ INST(kX86InstPSubD , "psubd" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FFA, 0),
+ INST(kX86InstPSubQ , "psubq" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FFB, 0),
+ INST(kX86InstPSubSB , "psubsb" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FE8, 0),
+ INST(kX86InstPSubSW , "psubsw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FE9, 0),
+ INST(kX86InstPSubUSB , "psubusb" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FD8, 0),
+ INST(kX86InstPSubUSW , "psubusw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FD9, 0),
+ INST(kX86InstPSubW , "psubw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FF9, 0),
+ INST(kX86InstPSwapD , "pswapd" , G(MmuRm3dNow) , F(None) , O(Mm) , O(MmMem) , 0, 0x00000F0F, 0xBB),
+ INST(kX86InstPTest , "ptest" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3817, 0),
+ INST(kX86InstPunpckHBW , "punpckhbw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000F68, 0),
+ INST(kX86InstPunpckHDQ , "punpckhdq" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000F6A, 0),
+ INST(kX86InstPunpckHQDQ , "punpckhqdq" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000F6D, 0),
+ INST(kX86InstPunpckHWD , "punpckhwd" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000F69, 0),
+ INST(kX86InstPunpckLBW , "punpcklbw" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000F60, 0),
+ INST(kX86InstPunpckLDQ , "punpckldq" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000F62, 0),
+ INST(kX86InstPunpckLQDQ , "punpcklqdq" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000F6C, 0),
+ INST(kX86InstPunpckLWD , "punpcklwd" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000F61, 0),
+ INST(kX86InstPush , "push" , G(Push) , F(Special) , 0 , 0 , 6, 0x00000050, 0x000000FF),
+ INST(kX86InstPushAD , "pushad" , G(Emit) , F(Special) , 0 , 0 , 0, 0x00000060, 0),
+ INST(kX86InstPushFD , "pushfd" , G(Emit) , F(Special) , 0 , 0 , 0, 0x0000009C, 0),
+ INST(kX86InstPushFQ , "pushfq" , G(Emit) , F(Special) , 0 , 0 , 0, 0x0000009C, 0),
+ INST(kX86InstPXor , "pxor" , G(MmuRmI) , F(None) , O(MmXmm) , O(MmXmmMem) , 0, 0x00000FEF, 0),
+ INST(kX86InstRcl , "rcl" , G(Rot) , F(Special) , O(GqdwbMem) , O(Gb)|O(Imm) , 2, 0 , 0),
+ INST(kX86InstRcpPS , "rcpps" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x00000F53, 0),
+ INST(kX86InstRcpSS , "rcpss" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0xF3000F53, 0),
+ INST(kX86InstRcr , "rcr" , G(Rot) , F(Special) , O(GqdwbMem) , O(Gb)|O(Imm) , 3, 0 , 0),
+ INST(kX86InstRdtsc , "rdtsc" , G(Emit) , F(Special) , 0 , 0 , 0, 0x00000F31, 0),
+ INST(kX86InstRdtscP , "rdtscp" , G(Emit) , F(Special) , 0 , 0 , 0, 0x000F01F9, 0),
+ INST(kX86InstRepLodSB , "rep lodsb" , G(Rep) , F(Special) , O(Mem) , 0 , 0, 0xF30000AC, 1 /* Size of mem */),
+ INST(kX86InstRepLodSD , "rep lodsd" , G(Rep) , F(Special) , O(Mem) , 0 , 0, 0xF30000AC, 4 /* Size of mem */),
+ INST(kX86InstRepLodSQ , "rep lodsq" , G(Rep) , F(Special) , O(Mem) , 0 , 0, 0xF30000AC, 8 /* Size of mem */),
+ INST(kX86InstRepLodSW , "rep lodsw" , G(Rep) , F(Special) , O(Mem) , 0 , 0, 0xF30000AC, 2 /* Size of mem */),
+ INST(kX86InstRepMovSB , "rep movsb" , G(Rep) , F(Special) , O(Mem) , O(Mem) , 0, 0xF30000A4, 1 /* Size of mem */),
+ INST(kX86InstRepMovSD , "rep movsd" , G(Rep) , F(Special) , O(Mem) , O(Mem) , 0, 0xF30000A4, 4 /* Size of mem */),
+ INST(kX86InstRepMovSQ , "rep movsq" , G(Rep) , F(Special) , O(Mem) , O(Mem) , 0, 0xF30000A4, 8 /* Size of mem */),
+ INST(kX86InstRepMovSW , "rep movsw" , G(Rep) , F(Special) , O(Mem) , O(Mem) , 0, 0xF30000A4, 2 /* Size of mem */),
+ INST(kX86InstRepStoSB , "rep stosb" , G(Rep) , F(Special) , O(Mem) , 0 , 0, 0xF30000AA, 1 /* Size of mem */),
+ INST(kX86InstRepStoSD , "rep stosd" , G(Rep) , F(Special) , O(Mem) , 0 , 0, 0xF30000AA, 4 /* Size of mem */),
+ INST(kX86InstRepStoSQ , "rep stosq" , G(Rep) , F(Special) , O(Mem) , 0 , 0, 0xF30000AA, 8 /* Size of mem */),
+ INST(kX86InstRepStoSW , "rep stosw" , G(Rep) , F(Special) , O(Mem) , 0 , 0, 0xF30000AA, 2 /* Size of mem */),
+ INST(kX86InstRepECmpSB , "repe cmpsb" , G(Rep) , F(Special) , O(Mem) , O(Mem) , 0, 0xF30000A6, 1 /* Size of mem */),
+ INST(kX86InstRepECmpSD , "repe cmpsd" , G(Rep) , F(Special) , O(Mem) , O(Mem) , 0, 0xF30000A6, 4 /* Size of mem */),
+ INST(kX86InstRepECmpSQ , "repe cmpsq" , G(Rep) , F(Special) , O(Mem) , O(Mem) , 0, 0xF30000A6, 8 /* Size of mem */),
+ INST(kX86InstRepECmpSW , "repe cmpsw" , G(Rep) , F(Special) , O(Mem) , O(Mem) , 0, 0xF30000A6, 2 /* Size of mem */),
+ INST(kX86InstRepEScaSB , "repe scasb" , G(Rep) , F(Special) , O(Mem) , O(Mem) , 0, 0xF30000AE, 1 /* Size of mem */),
+ INST(kX86InstRepEScaSD , "repe scasd" , G(Rep) , F(Special) , O(Mem) , O(Mem) , 0, 0xF30000AE, 4 /* Size of mem */),
+ INST(kX86InstRepEScaSQ , "repe scasq" , G(Rep) , F(Special) , O(Mem) , O(Mem) , 0, 0xF30000AE, 8 /* Size of mem */),
+ INST(kX86InstRepEScaSW , "repe scasw" , G(Rep) , F(Special) , O(Mem) , O(Mem) , 0, 0xF30000AE, 2 /* Size of mem */),
+ INST(kX86InstRepNECmpSB , "repne cmpsb" , G(Rep) , F(Special) , O(Mem) , O(Mem) , 0, 0xF20000A6, 1 /* Size of mem */),
+ INST(kX86InstRepNECmpSD , "repne cmpsd" , G(Rep) , F(Special) , O(Mem) , O(Mem) , 0, 0xF20000A6, 4 /* Size of mem */),
+ INST(kX86InstRepNECmpSQ , "repne cmpsq" , G(Rep) , F(Special) , O(Mem) , O(Mem) , 0, 0xF20000A6, 8 /* Size of mem */),
+ INST(kX86InstRepNECmpSW , "repne cmpsw" , G(Rep) , F(Special) , O(Mem) , O(Mem) , 0, 0xF20000A6, 2 /* Size of mem */),
+ INST(kX86InstRepNEScaSB , "repne scasb" , G(Rep) , F(Special) , O(Mem) , O(Mem) , 0, 0xF20000AE, 1 /* Size of mem */),
+ INST(kX86InstRepNEScaSD , "repne scasd" , G(Rep) , F(Special) , O(Mem) , O(Mem) , 0, 0xF20000AE, 4 /* Size of mem */),
+ INST(kX86InstRepNEScaSQ , "repne scasq" , G(Rep) , F(Special) , O(Mem) , O(Mem) , 0, 0xF20000AE, 8 /* Size of mem */),
+ INST(kX86InstRepNEScaSW , "repne scasw" , G(Rep) , F(Special) , O(Mem) , O(Mem) , 0, 0xF20000AE, 2 /* Size of mem */),
+ INST(kX86InstRet , "ret" , G(Ret) , F(Special) , 0 , 0 , 0, 0 , 0),
+ INST(kX86InstRol , "rol" , G(Rot) , F(Special) , O(GqdwbMem) , O(Gb)|O(Imm) , 0, 0 , 0),
+ INST(kX86InstRor , "ror" , G(Rot) , F(Special) , O(GqdwbMem) , O(Gb)|O(Imm) , 1, 0 , 0),
+ INST(kX86InstRoundPD , "roundpd" , G(MmuRmImm8) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x660F3A09, 0),
+ INST(kX86InstRoundPS , "roundps" , G(MmuRmImm8) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x660F3A08, 0),
+ INST(kX86InstRoundSD , "roundsd" , G(MmuRmImm8) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3A0B, 0),
+ INST(kX86InstRoundSS , "roundss" , G(MmuRmImm8) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x660F3A0A, 0),
+ INST(kX86InstRSqrtPS , "rsqrtps" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x00000F52, 0),
+ INST(kX86InstRSqrtSS , "rsqrtss" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF3000F52, 0),
+ INST(kX86InstSahf , "sahf" , G(Emit) , F(Special) , 0 , 0 , 0, 0x0000009E, 0),
+ INST(kX86InstSal , "sal" , G(Rot) , F(Special) , O(GqdwbMem) , O(Gb)|O(Imm) , 4, 0 , 0),
+ INST(kX86InstSar , "sar" , G(Rot) , F(Special) , O(GqdwbMem) , O(Gb)|O(Imm) , 7, 0 , 0),
+ INST(kX86InstSbb , "sbb" , G(Arith) , F(Lockable) , O(GqdwbMem) , O(GqdwbMem)|O(Imm) , 3, 0x00000018, 0x00000080),
+ INST(kX86InstSetA , "seta" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F97, 0),
+ INST(kX86InstSetAE , "setae" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F93, 0),
+ INST(kX86InstSetB , "setb" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F92, 0),
+ INST(kX86InstSetBE , "setbe" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F96, 0),
+ INST(kX86InstSetC , "setc" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F92, 0),
+ INST(kX86InstSetE , "sete" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F94, 0),
+ INST(kX86InstSetG , "setg" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F9F, 0),
+ INST(kX86InstSetGE , "setge" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F9D, 0),
+ INST(kX86InstSetL , "setl" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F9C, 0),
+ INST(kX86InstSetLE , "setle" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F9E, 0),
+ INST(kX86InstSetNA , "setna" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F96, 0),
+ INST(kX86InstSetNAE , "setnae" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F92, 0),
+ INST(kX86InstSetNB , "setnb" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F93, 0),
+ INST(kX86InstSetNBE , "setnbe" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F97, 0),
+ INST(kX86InstSetNC , "setnc" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F93, 0),
+ INST(kX86InstSetNE , "setne" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F95, 0),
+ INST(kX86InstSetNG , "setng" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F9E, 0),
+ INST(kX86InstSetNGE , "setnge" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F9C, 0),
+ INST(kX86InstSetNL , "setnl" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F9D, 0),
+ INST(kX86InstSetNLE , "setnle" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F9F, 0),
+ INST(kX86InstSetNO , "setno" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F91, 0),
+ INST(kX86InstSetNP , "setnp" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F9B, 0),
+ INST(kX86InstSetNS , "setns" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F99, 0),
+ INST(kX86InstSetNZ , "setnz" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F95, 0),
+ INST(kX86InstSetO , "seto" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F90, 0),
+ INST(kX86InstSetP , "setp" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F9A, 0),
+ INST(kX86InstSetPE , "setpe" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F9A, 0),
+ INST(kX86InstSetPO , "setpo" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F9B, 0),
+ INST(kX86InstSetS , "sets" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F98, 0),
+ INST(kX86InstSetZ , "setz" , G(RmByte) , F(None) , O(GbMem) , 0 , 0, 0x00000F94, 0),
+ INST(kX86InstSFence , "sfence" , G(Emit) , F(None) , 0 , 0 , 0, 0x000FAEF8, 0),
+ INST(kX86InstShl , "shl" , G(Rot) , F(Special) , O(GqdwbMem) , O(Gb)|O(Imm) , 4, 0 , 0),
+ INST(kX86InstShld , "shld" , G(ShldShrd) , F(Special) , O(GqdwbMem) , O(Gb) , 0, 0x00000FA4, 0),
+ INST(kX86InstShr , "shr" , G(Rot) , F(Special) , O(GqdwbMem) , O(Gb)|O(Imm) , 5, 0 , 0),
+ INST(kX86InstShrd , "shrd" , G(ShldShrd) , F(Special) , O(GqdwbMem) , O(Gqdwb) , 0, 0x00000FAC, 0),
+ INST(kX86InstShufPD , "shufpd" , G(MmuRmImm8) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000FC6, 0),
+ INST(kX86InstShufPS , "shufps" , G(MmuRmImm8) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x00000FC6, 0),
+ INST(kX86InstSqrtPD , "sqrtpd" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x66000F51, 0),
+ INST(kX86InstSqrtPS , "sqrtps" , G(MmuRmI) , F(Mov) , O(Xmm) , O(XmmMem) , 0, 0x00000F51, 0),
+ INST(kX86InstSqrtSD , "sqrtsd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF2000F51, 0),
+ INST(kX86InstSqrtSS , "sqrtss" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF3000F51, 0),
+ INST(kX86InstStc , "stc" , G(Emit) , F(None) , 0 , 0 , 0, 0x000000F9, 0),
+ INST(kX86InstStd , "std" , G(Emit) , F(None) , 0 , 0 , 0, 0x000000FD, 0),
+ INST(kX86InstStMXCSR , "stmxcsr" , G(Mem) , F(None) , O(Mem) , 0 , 3, 0x00000FAE, 0),
+ INST(kX86InstSub , "sub" , G(Arith) , F(Lockable) , O(GqdwbMem) , O(GqdwbMem)|O(Imm) , 5, 0x00000028, 0x00000080),
+ INST(kX86InstSubPD , "subpd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000F5C, 0),
+ INST(kX86InstSubPS , "subps" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x00000F5C, 0),
+ INST(kX86InstSubSD , "subsd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF2000F5C, 0),
+ INST(kX86InstSubSS , "subss" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0xF3000F5C, 0),
+ INST(kX86InstTest , "test" , G(Test) , F(None) , O(GqdwbMem) , O(Gqdwb)|O(Imm) , 0, 0 , 0),
+ INST(kX86InstUComISD , "ucomisd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000F2E, 0),
+ INST(kX86InstUComISS , "ucomiss" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x00000F2E, 0),
+ INST(kX86InstUd2 , "ud2" , G(Emit) , F(None) , 0 , 0 , 0, 0x00000F0B, 0),
+ INST(kX86InstUnpckHPD , "unpckhpd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000F15, 0),
+ INST(kX86InstUnpckHPS , "unpckhps" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x00000F15, 0),
+ INST(kX86InstUnpckLPD , "unpcklpd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000F14, 0),
+ INST(kX86InstUnpckLPS , "unpcklps" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x00000F14, 0),
+ INST(kX86InstXadd , "xadd" , G(RmReg) , F(Lockable) , O(GqdwbMem) , O(Gqdwb) , 0, 0x00000FC0, 0),
+ INST(kX86InstXchg , "xchg" , G(Xchg) , F(Lockable) , O(GqdwbMem) , O(Gqdwb) , 0, 0 , 0),
+ INST(kX86InstXor , "xor" , G(Arith) , F(Lockable) , O(GqdwbMem) , O(GqdwbMem)|O(Imm) , 6, 0x00000030, 0x00000080),
+ INST(kX86InstXorPD , "xorpd" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x66000F57, 0),
+ INST(kX86InstXorPS , "xorps" , G(MmuRmI) , F(None) , O(Xmm) , O(XmmMem) , 0, 0x00000F57, 0)
+};
+
+#undef G
+#undef F
+#undef O
+
+#undef INST
+
+// ============================================================================
+// [AsmJit::x86VarInfo]
+// ============================================================================
+
+#define C(_Class_) kX86VarClass##_Class_
+#define F(_Flag_) kX86VarFlag##_Flag_
+
+const X86VarInfo x86VarInfo[] =
+{
+ /* 0 */ { kX86RegTypeGpd , 4 , C(Gp) , 0 , "Gpd" },
+ /* 1 */ { kX86RegTypeGpq , 8 , C(Gp) , 0 , "Gpq" },
+ /* 2 */ { kX86RegTypeX87 , 4 , C(X87), F(SP) , "X87" },
+ /* 3 */ { kX86RegTypeX87 , 4 , C(X87), F(SP) , "X87.SS" },
+ /* 4 */ { kX86RegTypeX87 , 8 , C(X87), F(DP) , "X87.SD" },
+ /* 5 */ { kX86RegTypeMm , 8 , C(Mm) , 0 , "Mm" },
+ /* 6 */ { kX86RegTypeXmm , 16, C(Xmm), 0 , "Xmm" },
+ /* 7 */ { kX86RegTypeXmm , 4 , C(Xmm), F(SP) , "Xmm.SS" },
+ /* 8 */ { kX86RegTypeXmm , 8 , C(Xmm), F(DP) , "Xmm.SD" },
+ /* 9 */ { kX86RegTypeXmm , 16, C(Xmm), F(SP) | F(Packed), "Xmm.PS" },
+ /* 10 */ { kX86RegTypeXmm , 16, C(Xmm), F(DP) | F(Packed), "Xmm.PD" }
+};
+
+#undef F
+#undef C
+
+} // AsmJit namespace
+
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86/x86defs.h
@@ -1,1 +1,2204 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_X86_X86DEFS_H
+#define _ASMJIT_X86_X86DEFS_H
+
+// [Dependencies - AsmJit]
+#include "../core/assert.h"
+#include "../core/defs.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+//! @addtogroup AsmJit_X86
+//! @{
+
+// ============================================================================
+// [AsmJit::kX86Feature]
+// ============================================================================
+
+//! @brief X86 CPU features.
+enum kX86Feature
+{
+ //! @brief Cpu has RDTSC instruction.
+ kX86FeatureRdtsc = 1U,
+ //! @brief Cpu has RDTSCP instruction.
+ kX86FeatureRdtscP = 1U << 1,
+ //! @brief Cpu has CMOV instruction (conditional move)
+ kX86FeatureCMov = 1U << 2,
+ //! @brief Cpu has CMPXCHG8B instruction
+ kX86FeatureCmpXchg8B = 1U << 3,
+ //! @brief Cpu has CMPXCHG16B instruction (64-bit processors)
+ kX86FeatureCmpXchg16B = 1U << 4,
+ //! @brief Cpu has CLFUSH instruction
+ kX86FeatureClFlush = 1U << 5,
+ //! @brief Cpu has PREFETCH instruction
+ kX86FeaturePrefetch = 1U << 6,
+ //! @brief Cpu supports LAHF and SAHF instrictions.
+ kX86FeatureLahfSahf = 1U << 7,
+ //! @brief Cpu supports FXSAVE and FXRSTOR instructions.
+ kX86FeatureFXSR = 1U << 8,
+ //! @brief Cpu supports FXSAVE and FXRSTOR instruction optimizations (FFXSR).
+ kX86FeatureFFXSR = 1U << 9,
+ //! @brief Cpu has MMX.
+ kX86FeatureMmx = 1U << 10,
+ //! @brief Cpu has extended MMX.
+ kX86FeatureMmxExt = 1U << 11,
+ //! @brief Cpu has 3dNow!
+ kX86Feature3dNow = 1U << 12,
+ //! @brief Cpu has enchanced 3dNow!
+ kX86Feature3dNowExt = 1U << 13,
+ //! @brief Cpu has SSE.
+ kX86FeatureSse = 1U << 14,
+ //! @brief Cpu has SSE2.
+ kX86FeatureSse2 = 1U << 15,
+ //! @brief Cpu has SSE3.
+ kX86FeatureSse3 = 1U << 16,
+ //! @brief Cpu has Supplemental SSE3 (SSSE3).
+ kX86FeatureSsse3 = 1U << 17,
+ //! @brief Cpu has SSE4.A.
+ kX86FeatureSse4A = 1U << 18,
+ //! @brief Cpu has SSE4.1.
+ kX86FeatureSse41 = 1U << 19,
+ //! @brief Cpu has SSE4.2.
+ kX86FeatureSse42 = 1U << 20,
+ //! @brief Cpu has AVX.
+ kX86FeatureAvx = 1U << 22,
+ //! @brief Cpu has Misaligned SSE (MSSE).
+ kX86FeatureMSse = 1U << 23,
+ //! @brief Cpu supports MONITOR and MWAIT instructions.
+ kX86FeatureMonitorMWait = 1U << 24,
+ //! @brief Cpu supports MOVBE instruction.
+ kX86FeatureMovBE = 1U << 25,
+ //! @brief Cpu supports POPCNT instruction.
+ kX86FeaturePopCnt = 1U << 26,
+ //! @brief Cpu supports LZCNT instruction.
+ kX86FeatureLzCnt = 1U << 27,
+ //! @brief Cpu supports PCLMULDQ set of instructions.
+ kX86FeaturePclMulDQ = 1U << 28,
+ //! @brief Cpu supports multithreading.
+ kX86FeatureMultiThreading = 1U << 29,
+ //! @brief Cpu supports execute disable bit (execute protection).
+ kX86FeatureExecuteDisableBit = 1U << 30,
+ //! @brief 64-bit CPU.
+ kX86Feature64Bit = 1U << 31
+};
+
+// ============================================================================
+// [AsmJit::kX86Bug]
+// ============================================================================
+
+//! @brief X86 CPU bugs.
+enum kX86Bug
+{
+ //! @brief Whether the processor contains bug seen in some
+ //! AMD-Opteron processors.
+ kX86BugAmdLockMB = 1U << 0
+};
+
+// ============================================================================
+// [AsmJit::kX86Property]
+// ============================================================================
+
+//! @brief @ref X86Assembler and @ref X86Compiler properties.
+enum kX86Property
+{
+ //! @brief Optimize align for current processor.
+ //!
+ //! Default: @c true.
+ kX86PropertyOptimizedAlign = 0,
+
+ //! @brief Emit hints added to jcc() instructions.
+ //!
+ //! Default: @c true.
+ kX86PropertyJumpHints = 1
+};
+
+// ============================================================================
+// [AsmJit::kX86Seg]
+// ============================================================================
+
+//! @brief X86 segment codes.
+enum kX86Seg
+{
+ // DO NOT MODIFY INDEX CODES - They are used by _emitSegmentPrefix() and
+ // by logger in the following order:
+
+ //! @brief ES segment.
+ kX86SegEs = 0,
+ //! @brief CS segment.
+ kX86SegCs = 1,
+ //! @brief SS segment.
+ kX86SegSs = 2,
+ //! @brief DS segment.
+ kX86SegDs = 3,
+ //! @brief FS segment.
+ kX86SegFs = 4,
+ //! @brief GS segment.
+ kX86SegGs = 5,
+ //! @brief Count of segments.
+ kX86SegCount = 6,
+
+ //! @brief No segment override prefix.
+ kX86SegNone = 0xF
+};
+
+// ============================================================================
+// [AsmJit::kX86RegNum]
+// ============================================================================
+
+//! @brief X86 registers count.
+//!
+//! Count of general purpose registers and XMM registers depends on current
+//! mode. If application is compiled for 32-bit platform then this number is 8,
+//! 64-bit platforms have 8 extra general purpose and XMM registers (16 total).
+enum kX86RegNum
+{
+ //! @var kX86RegNumBase
+ //!
+ //! Count of general purpose registers and XMM registers depends on current
+ //! bit-mode. If application is compiled for 32-bit platform then this number
+ //! is 8, 64-bit platforms have 8 extra general purpose and XMM registers (16
+ //! total).
+#ifdef ASMJIT_X86
+ kX86RegNumBase = 8,
+#else
+ kX86RegNumBase = 16,
+#endif // ASMJIT
+
+ //! @brief Count of general purpose registers.
+ //!
+ //! 8 in 32-bit mode and 16 in 64-bit mode.
+ kX86RegNumGp = kX86RegNumBase,
+
+ //! @brief Count of FPU stack registers (always 8).
+ kX86RegNumX87 = 8,
+ //! @brief Count of MM registers (always 8).
+ kX86RegNumMm = 8,
+
+ //! @brief Count of XMM registers.
+ //!
+ //! 8 in 32-bit mode and 16 in 64-bit mode.
+ kX86RegNumXmm = kX86RegNumBase,
+ //! @brief Count of YMM registers.
+ //!
+ //! 8 in 32-bit mode and 16 in 64-bit mode.
+ kX86RegNumYmm = kX86RegNumBase,
+
+ //! @brief Count of segment registers, including no segment (AsmJit specific).
+ //!
+ //! @note There are 6 segment registers, but AsmJit uses 0 as no segment, and
+ //! 1...6 as segment registers, this means that there are 7 segment registers
+ //! in AsmJit API, but only 6 can be used through @c Assembler or @c Compiler
+ //! API.
+ kX86RegNumSeg = 7
+};
+
+//! @brief X86 register types.
+enum kX86RegType
+{
+ // First byte contains register type (mask 0xFF00), Second byte contains
+ // register index code.
+
+ // --------------------------------------------------------------------------
+ // [GP Register Types]
+ // --------------------------------------------------------------------------
+
+ //! @brief 8-bit general purpose register type (LO).
+ kX86RegTypeGpbLo = 0x0100,
+ //! @brief 8-bit general purpose register type (HI, only AH, BH, CH, DH).
+ kX86RegTypeGpbHi = 0x0200,
+ //! @brief 16-bit general purpose register type.
+ kX86RegTypeGpw = 0x1000,
+ //! @brief 32-bit general purpose register type.
+ kX86RegTypeGpd = 0x2000,
+ //! @brief 64-bit general purpose register type.
+ kX86RegTypeGpq = 0x3000,
+
+ //! @var kX86RegTypeGpz
+ //! @brief 32-bit or 64-bit general purpose register type.
+#ifdef ASMJIT_X86
+ kX86RegTypeGpz = kX86RegTypeGpd,
+#else
+ kX86RegTypeGpz = kX86RegTypeGpq,
+#endif
+
+ //! @brief X87 (FPU) register type.
+ kX86RegTypeX87 = 0x5000,
+ //! @brief 64-bit MM register type.
+ kX86RegTypeMm = 0x6000,
+
+ //! @brief 128-bit XMM register type.
+ kX86RegTypeXmm = 0x7000,
+ //! @brief 256-bit YMM register type.
+ kX86RegTypeYmm = 0x8000,
+
+ //! @brief 16-bit segment register type.
+ kX86RegTypeSeg = 0xD000
+};
+
+// ============================================================================
+// [AsmJit::kX86RegIndex]
+// ============================================================================
+
+//! @brief X86 register indices.
+//!
+//! These codes are real, don't miss with @c REG enum! and don't use these
+//! values if you are not writing AsmJit code.
+enum kX86RegIndex
+{
+ //! @brief ID for AX/EAX/RAX registers.
+ kX86RegIndexEax = 0,
+ //! @brief ID for CX/ECX/RCX registers.
+ kX86RegIndexEcx = 1,
+ //! @brief ID for DX/EDX/RDX registers.
+ kX86RegIndexEdx = 2,
+ //! @brief ID for BX/EBX/RBX registers.
+ kX86RegIndexEbx = 3,
+ //! @brief ID for SP/ESP/RSP registers.
+ kX86RegIndexEsp = 4,
+ //! @brief ID for BP/EBP/RBP registers.
+ kX86RegIndexEbp = 5,
+ //! @brief ID for SI/ESI/RSI registers.
+ kX86RegIndexEsi = 6,
+ //! @brief ID for DI/EDI/RDI registers.
+ kX86RegIndexEdi = 7,
+
+ //! @brief ID for AX/EAX/RAX registers.
+ kX86RegIndexRax = 0,
+ //! @brief ID for CX/ECX/RCX registers.
+ kX86RegIndexRcx = 1,
+ //! @brief ID for DX/EDX/RDX registers.
+ kX86RegIndexRdx = 2,
+ //! @brief ID for BX/EBX/RBX registers.
+ kX86RegIndexRbx = 3,
+ //! @brief ID for SP/ESP/RSP registers.
+ kX86RegIndexRsp = 4,
+ //! @brief ID for BP/EBP/RBP registers.
+ kX86RegIndexRbp = 5,
+ //! @brief ID for SI/ESI/RSI registers.
+ kX86RegIndexRsi = 6,
+ //! @brief ID for DI/EDI/RDI registers.
+ kX86RegIndexRdi = 7,
+
+ //! @brief ID for r8 register (additional register introduced by 64-bit architecture).
+ kX86RegIndexR8 = 8,
+ //! @brief ID for R9 register (additional register introduced by 64-bit architecture).
+ kX86RegIndexR9 = 9,
+ //! @brief ID for R10 register (additional register introduced by 64-bit architecture).
+ kX86RegIndexR10 = 10,
+ //! @brief ID for R11 register (additional register introduced by 64-bit architecture).
+ kX86RegIndexR11 = 11,
+ //! @brief ID for R12 register (additional register introduced by 64-bit architecture).
+ kX86RegIndexR12 = 12,
+ //! @brief ID for R13 register (additional register introduced by 64-bit architecture).
+ kX86RegIndexR13 = 13,
+ //! @brief ID for R14 register (additional register introduced by 64-bit architecture).
+ kX86RegIndexR14 = 14,
+ //! @brief ID for R15 register (additional register introduced by 64-bit architecture).
+ kX86RegIndexR15 = 15,
+
+ //! @brief ID for mm0 register.
+ kX86RegIndexMm0 = 0,
+ //! @brief ID for mm1 register.
+ kX86RegIndexMm1 = 1,
+ //! @brief ID for mm2 register.
+ kX86RegIndexMm2 = 2,
+ //! @brief ID for mm3 register.
+ kX86RegIndexMm3 = 3,
+ //! @brief ID for mm4 register.
+ kX86RegIndexMm4 = 4,
+ //! @brief ID for mm5 register.
+ kX86RegIndexMm5 = 5,
+ //! @brief ID for mm6 register.
+ kX86RegIndexMm6 = 6,
+ //! @brief ID for mm7 register.
+ kX86RegIndexMm7 = 7,
+
+ //! @brief ID for xmm0 register.
+ kX86RegIndexXmm0 = 0,
+ //! @brief ID for xmm1 register.
+ kX86RegIndexXmm1 = 1,
+ //! @brief ID for xmm2 register.
+ kX86RegIndexXmm2 = 2,
+ //! @brief ID for xmm3 register.
+ kX86RegIndexXmm3 = 3,
+ //! @brief ID for xmm4 register.
+ kX86RegIndexXmm4 = 4,
+ //! @brief ID for xmm5 register.
+ kX86RegIndexXmm5 = 5,
+ //! @brief ID for xmm6 register.
+ kX86RegIndexXmm6 = 6,
+ //! @brief ID for xmm7 register.
+ kX86RegIndexXmm7 = 7,
+
+ //! @brief ID for xmm8 register (additional register introduced by 64-bit architecture).
+ kX86RegIndexXmm8 = 8,
+ //! @brief ID for xmm9 register (additional register introduced by 64-bit architecture).
+ kX86RegIndexXmm9 = 9,
+ //! @brief ID for xmm10 register (additional register introduced by 64-bit architecture).
+ kX86RegIndexXmm10 = 10,
+ //! @brief ID for xmm11 register (additional register introduced by 64-bit architecture).
+ kX86RegIndexXmm11 = 11,
+ //! @brief ID for xmm12 register (additional register introduced by 64-bit architecture).
+ kX86RegIndexXmm12 = 12,
+ //! @brief ID for xmm13 register (additional register introduced by 64-bit architecture).
+ kX86RegIndexXmm13 = 13,
+ //! @brief ID for xmm14 register (additional register introduced by 64-bit architecture).
+ kX86RegIndexXmm14 = 14,
+ //! @brief ID for xmm15 register (additional register introduced by 64-bit architecture).
+ kX86RegIndexXmm15 = 15,
+
+ //! @brief ID for ES segment register.
+ kX86RegIndexEs = 0,
+ //! @brief ID for CS segment register.
+ kX86RegIndexCs = 1,
+ //! @brief ID for SS segment register.
+ kX86RegIndexSs = 2,
+ //! @brief ID for DS segment register.
+ kX86RegIndexDs = 3,
+ //! @brief ID for FS segment register.
+ kX86RegIndexFs = 4,
+ //! @brief ID for GS segment register.
+ kX86RegIndexGs = 5
+};
+
+// ============================================================================
+// [AsmJit::kX86RegCode]
+// ============================================================================
+
+//! @brief X86 pseudo (not real X86) register codes used for generating opcodes.
+//!
+//! From this register code can be generated real x86 register ID, type of
+//! register and size of register.
+enum kX86RegCode
+{
+ // --------------------------------------------------------------------------
+ // [8-bit Registers]
+ // --------------------------------------------------------------------------
+
+ kX86RegAl = kX86RegTypeGpbLo,
+ kX86RegCl,
+ kX86RegDl,
+ kX86RegBl,
+#if defined(ASMJIT_X64)
+ kX86RegSpl,
+ kX86RegBpl,
+ kX86RegSil,
+ kX86RegDil,
+#endif // ASMJIT_X64
+
+#if defined(ASMJIT_X64)
+ kX86RegR8b,
+ kX86RegR9b,
+ kX86RegR10b,
+ kX86RegR11b,
+ kX86RegR12b,
+ kX86RegR13b,
+ kX86RegR14b,
+ kX86RegR15b,
+#endif // ASMJIT_X64
+
+ kX86RegAh = kX86RegTypeGpbHi,
+ kX86RegCh,
+ kX86RegDh,
+ kX86RegBh,
+
+ // --------------------------------------------------------------------------
+ // [16-bit Registers]
+ // --------------------------------------------------------------------------
+
+ kX86RegAx = kX86RegTypeGpw,
+ kX86RegCx,
+ kX86RegDx,
+ kX86RegBx,
+ kX86RegSp,
+ kX86RegBp,
+ kX86RegSi,
+ kX86RegDi,
+#if defined(ASMJIT_X64)
+ kX86RegR8w,
+ kX86RegR9w,
+ kX86RegR10w,
+ kX86RegR11w,
+ kX86RegR12w,
+ kX86RegR13w,
+ kX86RegR14w,
+ kX86RegR15w,
+#endif // ASMJIT_X64
+
+ // --------------------------------------------------------------------------
+ // [32-bit Registers]
+ // --------------------------------------------------------------------------
+
+ kX86RegEax = kX86RegTypeGpd,
+ kX86RegEcx,
+ kX86RegEdx,
+ kX86RegEbx,
+ kX86RegEsp,
+ kX86RegEbp,
+ kX86RegEsi,
+ kX86RegEdi,
+#if defined(ASMJIT_X64)
+ kX86RegR8d,
+ kX86RegR9d,
+ kX86RegR10d,
+ kX86RegR11d,
+ kX86RegR12d,
+ kX86RegR13d,
+ kX86RegR14d,
+ kX86RegR15d,
+#endif // ASMJIT_X64
+
+ // --------------------------------------------------------------------------
+ // [64-bit Registers]
+ // --------------------------------------------------------------------------
+
+#if defined(ASMJIT_X64)
+ kX86RegRax = kX86RegTypeGpq,
+ kX86RegRcx,
+ kX86RegRdx,
+ kX86RegRbx,
+ kX86RegRsp,
+ kX86RegRbp,
+ kX86RegRsi,
+ kX86RegRdi,
+ kX86RegR8,
+ kX86RegR9,
+ kX86RegR10,
+ kX86RegR11,
+ kX86RegR12,
+ kX86RegR13,
+ kX86RegR14,
+ kX86RegR15,
+#endif // ASMJIT_X64
+
+ // --------------------------------------------------------------------------
+ // [MM Registers]
+ // --------------------------------------------------------------------------
+
+ kX86RegMm0 = kX86RegTypeMm,
+ kX86RegMm1,
+ kX86RegMm2,
+ kX86RegMm3,
+ kX86RegMm4,
+ kX86RegMm5,
+ kX86RegMm6,
+ kX86RegMm7,
+
+ // --------------------------------------------------------------------------
+ // [XMM Registers]
+ // --------------------------------------------------------------------------
+
+ kX86RegXmm0 = kX86RegTypeXmm,
+ kX86RegXmm1,
+ kX86RegXmm2,
+ kX86RegXmm3,
+ kX86RegXmm4,
+ kX86RegXmm5,
+ kX86RegXmm6,
+ kX86RegXmm7,
+#if defined(ASMJIT_X64)
+ kX86RegXmm8,
+ kX86RegXmm9,
+ kX86RegXmm10,
+ kX86RegXmm11,
+ kX86RegXmm12,
+ kX86RegXmm13,
+ kX86RegXmm14,
+ kX86RegXmm15,
+#endif // ASMJIT_X64
+
+ // --------------------------------------------------------------------------
+ // [Native registers (depends on 32-bit or 64-bit mode)]
+ // --------------------------------------------------------------------------
+
+ kX86RegZax = kX86RegTypeGpz,
+ kX86RegZcx,
+ kX86RegZdx,
+ kX86RegZbx,
+ kX86RegZsp,
+ kX86RegZbp,
+ kX86RegZsi,
+ kX86RegZdi,
+
+ // --------------------------------------------------------------------------
+ // [Segment registers]
+ // --------------------------------------------------------------------------
+
+ //! @brief ES segment register.
+ kX86RegEs = kX86RegTypeSeg,
+ //! @brief CS segment register.
+ kX86RegCs,
+ //! @brief SS segment register.
+ kX86RegSs,
+ //! @brief DS segment register.
+ kX86RegDs,
+ //! @brief FS segment register.
+ kX86RegFs,
+ //! @brief GS segment register.
+ kX86RegGs
+};
+
+// ============================================================================
+// [AsmJit::kX86Cond]
+// ============================================================================
+
+//! @brief X86 Condition codes.
+enum kX86Cond
+{
+ // Condition codes from processor manuals.
+ kX86CondA = 0x07,
+ kX86CondAE = 0x03,
+ kX86CondB = 0x02,
+ kX86CondBE = 0x06,
+ kX86CondC = 0x02,
+ kX86CondE = 0x04,
+ kX86CondG = 0x0F,
+ kX86CondGE = 0x0D,
+ kX86CondL = 0x0C,
+ kX86CondLE = 0x0E,
+ kX86CondNA = 0x06,
+ kX86CondNAE = 0x02,
+ kX86CondNB = 0x03,
+ kX86CondNBE = 0x07,
+ kX86CondNC = 0x03,
+ kX86CondNE = 0x05,
+ kX86CondNG = 0x0E,
+ kX86CondNGE = 0x0C,
+ kX86CondNL = 0x0D,
+ kX86CondNLE = 0x0F,
+ kX86CondNO = 0x01,
+ kX86CondNP = 0x0B,
+ kX86CondNS = 0x09,
+ kX86CondNZ = 0x05,
+ kX86CondO = 0x00,
+ kX86CondP = 0x0A,
+ kX86CondPE = 0x0A,
+ kX86CondPO = 0x0B,
+ kX86CondS = 0x08,
+ kX86CondZ = 0x04,
+
+ // Simplified condition codes.
+ kX86CondOverflow = 0x00,
+ kX86CondNotOverflow = 0x01,
+ kX86CondBelow = 0x02,
+ kX86CondAboveEqual = 0x03,
+ kX86CondEqual = 0x04,
+ kX86CondNotEqual = 0x05,
+ kX86CondBelowEqual = 0x06,
+ kX86CondAbove = 0x07,
+ kX86CondSign = 0x08,
+ kX86CondNotSign = 0x09,
+ kX86CondParityEven = 0x0A,
+ kX86CondParityOdd = 0x0B,
+ kX86CondLess = 0x0C,
+ kX86CondGreaterEqual = 0x0D,
+ kX86CondLessEqual = 0x0E,
+ kX86CondGreater = 0x0F,
+
+ // Aliases.
+ kX86CondZero = 0x04,
+ kX86CondNotZero = 0x05,
+ kX86CondNegative = 0x08,
+ kX86CondPositive = 0x09,
+
+ // X87 floating point only.
+ kX86CondFpuUnordered = 0x10,
+ kX86CondFpuNotUnordered = 0x11,
+
+ //! @brief No condition code.
+ kX86CondNone = 0x12
+};
+
+// ============================================================================
+// [AsmJit::kX86CondPrefix]
+// ============================================================================
+
+//! @brief X86 condition hint prefix code, see @ref kCondHint.
+enum kX86CondPrefix
+{
+ //! @brief Condition is likely to be taken.
+ kX86CondPrefixLikely = 0x3E,
+ //! @brief Condition is unlikely to be taken.
+ kX86CondPrefixUnlikely = 0x2E
+};
+
+// ============================================================================
+// [AsmJit::kX86PrefetchHint]
+// ============================================================================
+
+//! @brief X86 Prefetch hints.
+enum kX86PrefetchHint
+{
+ //! @brief Prefetch using NT hint.
+ kX86PrefetchNta = 0,
+ //! @brief Prefetch to L0 cache.
+ kX86PrefetchT0 = 1,
+ //! @brief Prefetch to L1 cache.
+ kX86PrefetchT1 = 2,
+ //! @brief Prefetch to L2 cache.
+ kX86PrefetchT2 = 3
+};
+
+// ============================================================================
+// [AsmJit::kX86FPSW]
+// ============================================================================
+
+//! @brief X86 FPU status-word.
+enum kX86FPSW
+{
+ kX86FPSW_Invalid = 0x0001,
+ kX86FPSW_Denormalized = 0x0002,
+ kX86FPSW_DivByZero = 0x0004,
+ kX86FPSW_Overflow = 0x0008,
+ kX86FPSW_Underflow = 0x0010,
+ kX86FPSW_Precision = 0x0020,
+ kX86FPSW_StackFault = 0x0040,
+ kX86FPSW_Interrupt = 0x0080,
+ kX86FPSW_C0 = 0x0100,
+ kX86FPSW_C1 = 0x0200,
+ kX86FPSW_C2 = 0x0400,
+ kX86FPSW_Top = 0x3800,
+ kX86FPSW_C3 = 0x4000,
+ kX86FPSW_Busy = 0x8000
+};
+
+// ============================================================================
+// [AsmJit::kX86FPCW]
+// ============================================================================
+
+//! @brief X86 FPU control-word.
+enum kX86FPCW
+{
+ // --------------------------------------------------------------------------
+ // [Exception-Mask]
+ // --------------------------------------------------------------------------
+
+ kX86FPCW_EM_Mask = 0x003F, // Bits 0-5.
+
+ kX86FPCW_EM_Invalid = 0x0001,
+ kX86FPCW_EM_Denormal = 0x0002,
+ kX86FPCW_EM_DivByZero = 0x0004,
+ kX86FPCW_EM_Overflow = 0x0008,
+ kX86FPCW_EM_Underflow = 0x0010,
+ kX86FPCW_EM_Inexact = 0x0020,
+
+ // --------------------------------------------------------------------------
+ // [Precision-Control]
+ // --------------------------------------------------------------------------
+
+ kX86FPCW_PC_Mask = 0x0300, // Bits 8-9.
+
+ kX86FPCW_PC_Float = 0x0000,
+ kX86FPCW_PC_Reserved = 0x0100,
+ kX86FPCW_PC_Double = 0x0200,
+ kX86FPCW_PC_Extended = 0x0300,
+
+ // --------------------------------------------------------------------------
+ // [Rounding-Control]
+ // --------------------------------------------------------------------------
+
+ kX86FPCW_RC_Mask = 0x0C00, // Bits 10-11.
+
+ kX86FPCW_RC_Nearest = 0x0000,
+ kX86FPCW_RC_Down = 0x0400,
+ kX86FPCW_RC_Up = 0x0800,
+ kX86FPCW_RC_Truncate = 0x0C00,
+
+ // --------------------------------------------------------------------------
+ // [Infinity-Control]
+ // --------------------------------------------------------------------------
+
+ kX86FPCW_IC_Mask = 0x1000, // Bit 12.
+
+ kX86FPCW_IC_Projective = 0x0000,
+ kX86FPCW_IC_Affine = 0x1000
+};
+
+// ============================================================================
+// [AsmJit::kX86EmitOption]
+// ============================================================================
+
+//! @brief Emit options, mainly for internal purposes.
+enum kX86EmitOption
+{
+ //! @brief Force REX prefix to be emitted.
+ //!
+ //! This option should be used carefully, because there are unencodable
+ //! combinations. If you want to access ah, bh, ch or dh registers then you
+ //! can't emit REX prefix and it will cause an illegal instruction error.
+ kX86EmitOptionRex = 0x1,
+
+ //! @brief Tell @c Assembler or @c Compiler to emit and validate lock prefix.
+ //!
+ //! If this option is used and instruction doesn't support LOCK prefix then
+ //! invalid instruction error is generated.
+ kX86EmitOptionLock = 0x2,
+
+ //! @brief Emit short/near jump or conditional jump instead of far one to
+ //! some bytes.
+ //!
+ //! @note This option could be dangerous in case that the short jump is not
+ //! possible (displacement can't fit into signed 8-bit integer). AsmJit can
+ //! automatically generate back short jumps, but always generates long forward
+ //! jumps, because the information about the code size between the instruction
+ //! and target is not known.
+ kX86EmitOptionShortJump = 0x4,
+
+ //! @brief Emit full immediate instead of BYTE in all cases.
+ //!
+ //! @note AsmJit is able to emit both forms of immediate value. In case that
+ //! the instruction supports short form and immediate can fit into a signed
+ //! 8-bit integer short for is preferred, but if for any reason the full form
+ //! is required it can be overridden by using this option.
+ kX86EmitOptionFullImmediate = 0x8
+};
+
+// ============================================================================
+// [AsmJit::kX86InstCode]
+// ============================================================================
+
+//! @brief X86 instruction codes.
+//!
+//! Note that these instruction codes are AsmJit specific. Each instruction is
+//! unique ID into AsmJit instruction table. Instruction codes are used together
+//! with AsmJit::Assembler and you can also use instruction codes to serialize
+//! instructions by @ref Assembler::_emitInstruction() or
+//! @ref Compiler::_emitInstruction()
+enum kX86InstCode
+{
+ kX86InstAdc = 1, // X86/X64
+ kX86InstAdd, // X86/X64
+ kX86InstAddPD, // SSE2
+ kX86InstAddPS, // SSE
+ kX86InstAddSD, // SSE2
+ kX86InstAddSS, // SSE
+ kX86InstAddSubPD, // SSE3
+ kX86InstAddSubPS, // SSE3
+ kX86InstAmdPrefetch, // 3dNow!
+ kX86InstAmdPrefetchW, // 3dNow!
+ kX86InstAnd, // X86/X64
+ kX86InstAndnPD, // SSE2
+ kX86InstAndnPS, // SSE
+ kX86InstAndPD, // SSE2
+ kX86InstAndPS, // SSE
+ kX86InstBlendPD, // SSE4.1
+ kX86InstBlendPS, // SSE4.1
+ kX86InstBlendVPD, // SSE4.1
+ kX86InstBlendVPS, // SSE4.1
+ kX86InstBsf, // X86/X64
+ kX86InstBsr, // X86/X64
+ kX86InstBSwap, // X86/X64 (i486)
+ kX86InstBt, // X86/X64
+ kX86InstBtc, // X86/X64
+ kX86InstBtr, // X86/X64
+ kX86InstBts, // X86/X64
+ kX86InstCall, // X86/X64
+ kX86InstCbw, // X86/X64
+ kX86InstCdq, // X86/X64
+ kX86InstCdqe, // X64 only
+ kX86InstClc, // X86/X64
+ kX86InstCld, // X86/X64
+ kX86InstClFlush, // SSE2
+ kX86InstCmc, // X86/X64
+
+ kX86InstCMov, // Begin (cmovcc) (i586)
+ kX86InstCMovA=kX86InstCMov,//X86/X64 (cmovcc) (i586)
+ kX86InstCMovAE, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovB, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovBE, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovC, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovE, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovG, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovGE, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovL, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovLE, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovNA, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovNAE, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovNB, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovNBE, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovNC, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovNE, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovNG, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovNGE, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovNL, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovNLE, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovNO, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovNP, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovNS, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovNZ, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovO, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovP, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovPE, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovPO, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovS, // X86/X64 (cmovcc) (i586)
+ kX86InstCMovZ, // X86/X64 (cmovcc) (i586)
+
+ kX86InstCmp, // X86/X64
+ kX86InstCmpPD, // SSE2
+ kX86InstCmpPS, // SSE
+ kX86InstCmpSD, // SSE2
+ kX86InstCmpSS, // SSE
+ kX86InstCmpXCHG, // X86/X64 (i486)
+ kX86InstCmpXCHG16B, // X64 only
+ kX86InstCmpXCHG8B, // X86/X64 (i586)
+ kX86InstComISD, // SSE2
+ kX86InstComISS, // SSE
+ kX86InstCpuId, // X86/X64 (i486)
+ kX86InstCqo, // X64 only
+ kX86InstCrc32, // SSE4.2
+ kX86InstCvtDQ2PD, // SSE2
+ kX86InstCvtDQ2PS, // SSE2
+ kX86InstCvtPD2DQ, // SSE2
+ kX86InstCvtPD2PI, // SSE2
+ kX86InstCvtPD2PS, // SSE2
+ kX86InstCvtPI2PD, // SSE2
+ kX86InstCvtPI2PS, // SSE
+ kX86InstCvtPS2DQ, // SSE2
+ kX86InstCvtPS2PD, // SSE2
+ kX86InstCvtPS2PI, // SSE
+ kX86InstCvtSD2SI, // SSE2
+ kX86InstCvtSD2SS, // SSE2
+ kX86InstCvtSI2SD, // SSE2
+ kX86InstCvtSI2SS, // SSE
+ kX86InstCvtSS2SD, // SSE2
+ kX86InstCvtSS2SI, // SSE
+ kX86InstCvttPD2DQ, // SSE2
+ kX86InstCvttPD2PI, // SSE2
+ kX86InstCvttPS2DQ, // SSE2
+ kX86InstCvttPS2PI, // SSE
+ kX86InstCvttSD2SI, // SSE2
+ kX86InstCvttSS2SI, // SSE
+ kX86InstCwd, // X86/X64
+ kX86InstCwde, // X86/X64
+ kX86InstDaa, // X86 only
+ kX86InstDas, // X86 only
+ kX86InstDec, // X86/X64
+ kX86InstDiv, // X86/X64
+ kX86InstDivPD, // SSE2
+ kX86InstDivPS, // SSE
+ kX86InstDivSD, // SSE2
+ kX86InstDivSS, // SSE
+ kX86InstDpPD, // SSE4.1
+ kX86InstDpPS, // SSE4.1
+ kX86InstEmms, // MMX
+ kX86InstEnter, // X86/X64
+ kX86InstExtractPS, // SSE4.1
+ kX86InstF2XM1, // X87
+ kX86InstFAbs, // X87
+ kX86InstFAdd, // X87
+ kX86InstFAddP, // X87
+ kX86InstFBLd, // X87
+ kX86InstFBStP, // X87
+ kX86InstFCHS, // X87
+ kX86InstFClex, // X87
+ kX86InstFCMovB, // X87
+ kX86InstFCMovBE, // X87
+ kX86InstFCMovE, // X87
+ kX86InstFCMovNB, // X87
+ kX86InstFCMovNBE, // X87
+ kX86InstFCMovNE, // X87
+ kX86InstFCMovNU, // X87
+ kX86InstFCMovU, // X87
+ kX86InstFCom, // X87
+ kX86InstFComI, // X87
+ kX86InstFComIP, // X87
+ kX86InstFComP, // X87
+ kX86InstFComPP, // X87
+ kX86InstFCos, // X87
+ kX86InstFDecStP, // X87
+ kX86InstFDiv, // X87
+ kX86InstFDivP, // X87
+ kX86InstFDivR, // X87
+ kX86InstFDivRP, // X87
+ kX86InstFEmms, // 3dNow!
+ kX86InstFFree, // X87
+ kX86InstFIAdd, // X87
+ kX86InstFICom, // X87
+ kX86InstFIComP, // X87
+ kX86InstFIDiv, // X87
+ kX86InstFIDivR, // X87
+ kX86InstFILd, // X87
+ kX86InstFIMul, // X87
+ kX86InstFIncStP, // X87
+ kX86InstFInit, // X87
+ kX86InstFISt, // X87
+ kX86InstFIStP, // X87
+ kX86InstFISttP, // SSE3
+ kX86InstFISub, // X87
+ kX86InstFISubR, // X87
+ kX86InstFLd, // X87
+ kX86InstFLd1, // X87
+ kX86InstFLdCw, // X87
+ kX86InstFLdEnv, // X87
+ kX86InstFLdL2E, // X87
+ kX86InstFLdL2T, // X87
+ kX86InstFLdLg2, // X87
+ kX86InstFLdLn2, // X87
+ kX86InstFLdPi, // X87
+ kX86InstFLdZ, // X87
+ kX86InstFMul, // X87
+ kX86InstFMulP, // X87
+ kX86InstFNClex, // X87
+ kX86InstFNInit, // X87
+ kX86InstFNop, // X87
+ kX86InstFNSave, // X87
+ kX86InstFNStCw, // X87
+ kX86InstFNStEnv, // X87
+ kX86InstFNStSw, // X87
+ kX86InstFPAtan, // X87
+ kX86InstFPRem, // X87
+ kX86InstFPRem1, // X87
+ kX86InstFPTan, // X87
+ kX86InstFRndInt, // X87
+ kX86InstFRstor, // X87
+ kX86InstFSave, // X87
+ kX86InstFScale, // X87
+ kX86InstFSin, // X87
+ kX86InstFSinCos, // X87
+ kX86InstFSqrt, // X87
+ kX86InstFSt, // X87
+ kX86InstFStCw, // X87
+ kX86InstFStEnv, // X87
+ kX86InstFStP, // X87
+ kX86InstFStSw, // X87
+ kX86InstFSub, // X87
+ kX86InstFSubP, // X87
+ kX86InstFSubR, // X87
+ kX86InstFSubRP, // X87
+ kX86InstFTst, // X87
+ kX86InstFUCom, // X87
+ kX86InstFUComI, // X87
+ kX86InstFUComIP, // X87
+ kX86InstFUComP, // X87
+ kX86InstFUComPP, // X87
+ kX86InstFWait, // X87
+ kX86InstFXam, // X87
+ kX86InstFXch, // X87
+ kX86InstFXRstor, // X87
+ kX86InstFXSave, // X87
+ kX86InstFXtract, // X87
+ kX86InstFYL2X, // X87
+ kX86InstFYL2XP1, // X87
+ kX86InstHAddPD, // SSE3
+ kX86InstHAddPS, // SSE3
+ kX86InstHSubPD, // SSE3
+ kX86InstHSubPS, // SSE3
+ kX86InstIDiv, // X86/X64
+ kX86InstIMul, // X86/X64
+ kX86InstInc, // X86/X64
+ kX86InstInt3, // X86/X64
+ kX86InstJ, // Begin (jcc)
+ kX86InstJA = kX86InstJ, // X86/X64 (jcc)
+ kX86InstJAE, // X86/X64 (jcc)
+ kX86InstJB, // X86/X64 (jcc)
+ kX86InstJBE, // X86/X64 (jcc)
+ kX86InstJC, // X86/X64 (jcc)
+ kX86InstJE, // X86/X64 (jcc)
+ kX86InstJG, // X86/X64 (jcc)
+ kX86InstJGE, // X86/X64 (jcc)
+ kX86InstJL, // X86/X64 (jcc)
+ kX86InstJLE, // X86/X64 (jcc)
+ kX86InstJNA, // X86/X64 (jcc)
+ kX86InstJNAE, // X86/X64 (jcc)
+ kX86InstJNB, // X86/X64 (jcc)
+ kX86InstJNBE, // X86/X64 (jcc)
+ kX86InstJNC, // X86/X64 (jcc)
+ kX86InstJNE, // X86/X64 (jcc)
+ kX86InstJNG, // X86/X64 (jcc)
+ kX86InstJNGE, // X86/X64 (jcc)
+ kX86InstJNL, // X86/X64 (jcc)
+ kX86InstJNLE, // X86/X64 (jcc)
+ kX86InstJNO, // X86/X64 (jcc)
+ kX86InstJNP, // X86/X64 (jcc)
+ kX86InstJNS, // X86/X64 (jcc)
+ kX86InstJNZ, // X86/X64 (jcc)
+ kX86InstJO, // X86/X64 (jcc)
+ kX86InstJP, // X86/X64 (jcc)
+ kX86InstJPE, // X86/X64 (jcc)
+ kX86InstJPO, // X86/X64 (jcc)
+ kX86InstJS, // X86/X64 (jcc)
+ kX86InstJZ, // X86/X64 (jcc)
+ kX86InstJmp, // X86/X64 (jmp)
+ kX86InstLdDQU, // SSE3
+ kX86InstLdMXCSR, // SSE
+ kX86InstLahf, // X86/X64 (CPUID NEEDED)
+ kX86InstLea, // X86/X64
+ kX86InstLeave, // X86/X64
+ kX86InstLFence, // SSE2
+ kX86InstMaskMovDQU, // SSE2
+ kX86InstMaskMovQ, // MMX-Ext
+ kX86InstMaxPD, // SSE2
+ kX86InstMaxPS, // SSE
+ kX86InstMaxSD, // SSE2
+ kX86InstMaxSS, // SSE
+ kX86InstMFence, // SSE2
+ kX86InstMinPD, // SSE2
+ kX86InstMinPS, // SSE
+ kX86InstMinSD, // SSE2
+ kX86InstMinSS, // SSE
+ kX86InstMonitor, // SSE3
+ kX86InstMov, // X86/X64
+ kX86InstMovAPD, // SSE2
+ kX86InstMovAPS, // SSE
+ kX86InstMovBE, // SSE3 - Intel-Atom
+ kX86InstMovD, // MMX/SSE2
+ kX86InstMovDDup, // SSE3
+ kX86InstMovDQ2Q, // SSE2
+ kX86InstMovDQA, // SSE2
+ kX86InstMovDQU, // SSE2
+ kX86InstMovHLPS, // SSE
+ kX86InstMovHPD, // SSE2
+ kX86InstMovHPS, // SSE
+ kX86InstMovLHPS, // SSE
+ kX86InstMovLPD, // SSE2
+ kX86InstMovLPS, // SSE
+ kX86InstMovMskPD, // SSE2
+ kX86InstMovMskPS, // SSE2
+ kX86InstMovNTDQ, // SSE2
+ kX86InstMovNTDQA, // SSE4.1
+ kX86InstMovNTI, // SSE2
+ kX86InstMovNTPD, // SSE2
+ kX86InstMovNTPS, // SSE
+ kX86InstMovNTQ, // MMX-Ext
+ kX86InstMovQ, // MMX/SSE/SSE2
+ kX86InstMovQ2DQ, // SSE2
+ kX86InstMovSD, // SSE2
+ kX86InstMovSHDup, // SSE3
+ kX86InstMovSLDup, // SSE3
+ kX86InstMovSS, // SSE
+ kX86InstMovSX, // X86/X64
+ kX86InstMovSXD, // X86/X64
+ kX86InstMovUPD, // SSE2
+ kX86InstMovUPS, // SSE
+ kX86InstMovZX, // X86/X64
+ kX86InstMovPtr, // X86/X64
+ kX86InstMPSADBW, // SSE4.1
+ kX86InstMul, // X86/X64
+ kX86InstMulPD, // SSE2
+ kX86InstMulPS, // SSE
+ kX86InstMulSD, // SSE2
+ kX86InstMulSS, // SSE
+ kX86InstMWait, // SSE3
+ kX86InstNeg, // X86/X64
+ kX86InstNop, // X86/X64
+ kX86InstNot, // X86/X64
+ kX86InstOr, // X86/X64
+ kX86InstOrPD, // SSE2
+ kX86InstOrPS, // SSE
+ kX86InstPAbsB, // SSSE3
+ kX86InstPAbsD, // SSSE3
+ kX86InstPAbsW, // SSSE3
+ kX86InstPackSSDW, // MMX/SSE2
+ kX86InstPackSSWB, // MMX/SSE2
+ kX86InstPackUSDW, // SSE4.1
+ kX86InstPackUSWB, // MMX/SSE2
+ kX86InstPAddB, // MMX/SSE2
+ kX86InstPAddD, // MMX/SSE2
+ kX86InstPAddQ, // SSE2
+ kX86InstPAddSB, // MMX/SSE2
+ kX86InstPAddSW, // MMX/SSE2
+ kX86InstPAddUSB, // MMX/SSE2
+ kX86InstPAddUSW, // MMX/SSE2
+ kX86InstPAddW, // MMX/SSE2
+ kX86InstPAlignR, // SSSE3
+ kX86InstPAnd, // MMX/SSE2
+ kX86InstPAndN, // MMX/SSE2
+ kX86InstPause, // SSE2.
+ kX86InstPAvgB, // MMX-Ext
+ kX86InstPAvgW, // MMX-Ext
+ kX86InstPBlendVB, // SSE4.1
+ kX86InstPBlendW, // SSE4.1
+ kX86InstPCmpEqB, // MMX/SSE2
+ kX86InstPCmpEqD, // MMX/SSE2
+ kX86InstPCmpEqQ, // SSE4.1
+ kX86InstPCmpEqW, // MMX/SSE2
+ kX86InstPCmpEStrI, // SSE4.2
+ kX86InstPCmpEStrM, // SSE4.2
+ kX86InstPCmpGtB, // MMX/SSE2
+ kX86InstPCmpGtD, // MMX/SSE2
+ kX86InstPCmpGtQ, // SSE4.2
+ kX86InstPCmpGtW, // MMX/SSE2
+ kX86InstPCmpIStrI, // SSE4.2
+ kX86InstPCmpIStrM, // SSE4.2
+ kX86InstPExtrB, // SSE4.1
+ kX86InstPExtrD, // SSE4.1
+ kX86InstPExtrQ, // SSE4.1
+ kX86InstPExtrW, // MMX-Ext/SSE2
+ kX86InstPF2ID, // 3dNow!
+ kX86InstPF2IW, // Enhanced 3dNow!
+ kX86InstPFAcc, // 3dNow!
+ kX86InstPFAdd, // 3dNow!
+ kX86InstPFCmpEQ, // 3dNow!
+ kX86InstPFCmpGE, // 3dNow!
+ kX86InstPFCmpGT, // 3dNow!
+ kX86InstPFMax, // 3dNow!
+ kX86InstPFMin, // 3dNow!
+ kX86InstPFMul, // 3dNow!
+ kX86InstPFNAcc, // Enhanced 3dNow!
+ kX86InstPFPNAcc, // Enhanced 3dNow!
+ kX86InstPFRcp, // 3dNow!
+ kX86InstPFRcpIt1, // 3dNow!
+ kX86InstPFRcpIt2, // 3dNow!
+ kX86InstPFRSqIt1, // 3dNow!
+ kX86InstPFRSqrt, // 3dNow!
+ kX86InstPFSub, // 3dNow!
+ kX86InstPFSubR, // 3dNow!
+ kX86InstPHAddD, // SSSE3
+ kX86InstPHAddSW, // SSSE3
+ kX86InstPHAddW, // SSSE3
+ kX86InstPHMinPOSUW, // SSE4.1
+ kX86InstPHSubD, // SSSE3
+ kX86InstPHSubSW, // SSSE3
+ kX86InstPHSubW, // SSSE3
+ kX86InstPI2FD, // 3dNow!
+ kX86InstPI2FW, // Enhanced 3dNow!
+ kX86InstPInsRB, // SSE4.1
+ kX86InstPInsRD, // SSE4.1
+ kX86InstPInsRQ, // SSE4.1
+ kX86InstPInsRW, // MMX-Ext
+ kX86InstPMAddUBSW, // SSSE3
+ kX86InstPMAddWD, // MMX/SSE2
+ kX86InstPMaxSB, // SSE4.1
+ kX86InstPMaxSD, // SSE4.1
+ kX86InstPMaxSW, // MMX-Ext
+ kX86InstPMaxUB, // MMX-Ext
+ kX86InstPMaxUD, // SSE4.1
+ kX86InstPMaxUW, // SSE4.1
+ kX86InstPMinSB, // SSE4.1
+ kX86InstPMinSD, // SSE4.1
+ kX86InstPMinSW, // MMX-Ext
+ kX86InstPMinUB, // MMX-Ext
+ kX86InstPMinUD, // SSE4.1
+ kX86InstPMinUW, // SSE4.1
+ kX86InstPMovMskB, // MMX-Ext
+ kX86InstPMovSXBD, // SSE4.1
+ kX86InstPMovSXBQ, // SSE4.1
+ kX86InstPMovSXBW, // SSE4.1
+ kX86InstPMovSXDQ, // SSE4.1
+ kX86InstPMovSXWD, // SSE4.1
+ kX86InstPMovSXWQ, // SSE4.1
+ kX86InstPMovZXBD, // SSE4.1
+ kX86InstPMovZXBQ, // SSE4.1
+ kX86InstPMovZXBW, // SSE4.1
+ kX86InstPMovZXDQ, // SSE4.1
+ kX86InstPMovZXWD, // SSE4.1
+ kX86InstPMovZXWQ, // SSE4.1
+ kX86InstPMulDQ, // SSE4.1
+ kX86InstPMulHRSW, // SSSE3
+ kX86InstPMulHUW, // MMX-Ext
+ kX86InstPMulHW, // MMX/SSE2
+ kX86InstPMulLD, // SSE4.1
+ kX86InstPMulLW, // MMX/SSE2
+ kX86InstPMulUDQ, // SSE2
+ kX86InstPop, // X86/X64
+ kX86InstPopAD, // X86 only
+ kX86InstPopCnt, // SSE4.2
+ kX86InstPopFD, // X86 only
+ kX86InstPopFQ, // X64 only
+ kX86InstPOr, // MMX/SSE2
+ kX86InstPrefetch, // MMX-Ext
+ kX86InstPSADBW, // MMX-Ext
+ kX86InstPShufB, // SSSE3
+ kX86InstPShufD, // SSE2
+ kX86InstPShufW, // MMX-Ext
+ kX86InstPShufHW, // SSE2
+ kX86InstPShufLW, // SSE2
+ kX86InstPSignB, // SSSE3
+ kX86InstPSignD, // SSSE3
+ kX86InstPSignW, // SSSE3
+ kX86InstPSllD, // MMX/SSE2
+ kX86InstPSllDQ, // SSE2
+ kX86InstPSllQ, // MMX/SSE2
+ kX86InstPSllW, // MMX/SSE2
+ kX86InstPSraD, // MMX/SSE2
+ kX86InstPSraW, // MMX/SSE2
+ kX86InstPSrlD, // MMX/SSE2
+ kX86InstPSrlDQ, // SSE2
+ kX86InstPSrlQ, // MMX/SSE2
+ kX86InstPSrlW, // MMX/SSE2
+ kX86InstPSubB, // MMX/SSE2
+ kX86InstPSubD, // MMX/SSE2
+ kX86InstPSubQ, // SSE2
+ kX86InstPSubSB, // MMX/SSE2
+ kX86InstPSubSW, // MMX/SSE2
+ kX86InstPSubUSB, // MMX/SSE2
+ kX86InstPSubUSW, // MMX/SSE2
+ kX86InstPSubW, // MMX/SSE2
+ kX86InstPSwapD, // Enhanced 3dNow!
+ kX86InstPTest, // SSE4.1
+ kX86InstPunpckHBW, // MMX/SSE2
+ kX86InstPunpckHDQ, // MMX/SSE2
+ kX86InstPunpckHQDQ, // SSE2
+ kX86InstPunpckHWD, // MMX/SSE2
+ kX86InstPunpckLBW, // MMX/SSE2
+ kX86InstPunpckLDQ, // MMX/SSE2
+ kX86InstPunpckLQDQ, // SSE2
+ kX86InstPunpckLWD, // MMX/SSE2
+ kX86InstPush, // X86/X64
+ kX86InstPushAD, // X86 only
+ kX86InstPushFD, // X86 only
+ kX86InstPushFQ, // X64 only
+ kX86InstPXor, // MMX/SSE2
+ kX86InstRcl, // X86/X64
+ kX86InstRcpPS, // SSE
+ kX86InstRcpSS, // SSE
+ kX86InstRcr, // X86/X64
+ kX86InstRdtsc, // X86/X64
+ kX86InstRdtscP, // X86/X64
+ kX86InstRepLodSB, // X86/X64 (REP)
+ kX86InstRepLodSD, // X86/X64 (REP)
+ kX86InstRepLodSQ, // X64 only (REP)
+ kX86InstRepLodSW, // X86/X64 (REP)
+ kX86InstRepMovSB, // X86/X64 (REP)
+ kX86InstRepMovSD, // X86/X64 (REP)
+ kX86InstRepMovSQ, // X64 only (REP)
+ kX86InstRepMovSW, // X86/X64 (REP)
+ kX86InstRepStoSB, // X86/X64 (REP)
+ kX86InstRepStoSD, // X86/X64 (REP)
+ kX86InstRepStoSQ, // X64 only (REP)
+ kX86InstRepStoSW, // X86/X64 (REP)
+ kX86InstRepECmpSB, // X86/X64 (REP)
+ kX86InstRepECmpSD, // X86/X64 (REP)
+ kX86InstRepECmpSQ, // X64 only (REP)
+ kX86InstRepECmpSW, // X86/X64 (REP)
+ kX86InstRepEScaSB, // X86/X64 (REP)
+ kX86InstRepEScaSD, // X86/X64 (REP)
+ kX86InstRepEScaSQ, // X64 only (REP)
+ kX86InstRepEScaSW, // X86/X64 (REP)
+ kX86InstRepNECmpSB, // X86/X64 (REP)
+ kX86InstRepNECmpSD, // X86/X64 (REP)
+ kX86InstRepNECmpSQ, // X64 only (REP)
+ kX86InstRepNECmpSW, // X86/X64 (REP)
+ kX86InstRepNEScaSB, // X86/X64 (REP)
+ kX86InstRepNEScaSD, // X86/X64 (REP)
+ kX86InstRepNEScaSQ, // X64 only (REP)
+ kX86InstRepNEScaSW, // X86/X64 (REP)
+ kX86InstRet, // X86/X64
+ kX86InstRol, // X86/X64
+ kX86InstRor, // X86/X64
+ kX86InstRoundPD, // SSE4.1
+ kX86InstRoundPS, // SSE4.1
+ kX86InstRoundSD, // SSE4.1
+ kX86InstRoundSS, // SSE4.1
+ kX86InstRSqrtPS, // SSE
+ kX86InstRSqrtSS, // SSE
+ kX86InstSahf, // X86/X64 (CPUID NEEDED)
+ kX86InstSal, // X86/X64
+ kX86InstSar, // X86/X64
+ kX86InstSbb, // X86/X64
+ kX86InstSet, // Begin (setcc)
+ kX86InstSetA=kX86InstSet,// X86/X64 (setcc)
+ kX86InstSetAE, // X86/X64 (setcc)
+ kX86InstSetB, // X86/X64 (setcc)
+ kX86InstSetBE, // X86/X64 (setcc)
+ kX86InstSetC, // X86/X64 (setcc)
+ kX86InstSetE, // X86/X64 (setcc)
+ kX86InstSetG, // X86/X64 (setcc)
+ kX86InstSetGE, // X86/X64 (setcc)
+ kX86InstSetL, // X86/X64 (setcc)
+ kX86InstSetLE, // X86/X64 (setcc)
+ kX86InstSetNA, // X86/X64 (setcc)
+ kX86InstSetNAE, // X86/X64 (setcc)
+ kX86InstSetNB, // X86/X64 (setcc)
+ kX86InstSetNBE, // X86/X64 (setcc)
+ kX86InstSetNC, // X86/X64 (setcc)
+ kX86InstSetNE, // X86/X64 (setcc)
+ kX86InstSetNG, // X86/X64 (setcc)
+ kX86InstSetNGE, // X86/X64 (setcc)
+ kX86InstSetNL, // X86/X64 (setcc)
+ kX86InstSetNLE, // X86/X64 (setcc)
+ kX86InstSetNO, // X86/X64 (setcc)
+ kX86InstSetNP, // X86/X64 (setcc)
+ kX86InstSetNS, // X86/X64 (setcc)
+ kX86InstSetNZ, // X86/X64 (setcc)
+ kX86InstSetO, // X86/X64 (setcc)
+ kX86InstSetP, // X86/X64 (setcc)
+ kX86InstSetPE, // X86/X64 (setcc)
+ kX86InstSetPO, // X86/X64 (setcc)
+ kX86InstSetS, // X86/X64 (setcc)
+ kX86InstSetZ, // X86/X64 (setcc)
+ kX86InstSFence, // MMX-Ext/SSE
+ kX86InstShl, // X86/X64
+ kX86InstShld, // X86/X64
+ kX86InstShr, // X86/X64
+ kX86InstShrd, // X86/X64
+ kX86InstShufPD, // SSE2
+ kX86InstShufPS, // SSE
+ kX86InstSqrtPD, // SSE2
+ kX86InstSqrtPS, // SSE
+ kX86InstSqrtSD, // SSE2
+ kX86InstSqrtSS, // SSE
+ kX86InstStc, // X86/X64
+ kX86InstStd, // X86/X64
+ kX86InstStMXCSR, // SSE
+ kX86InstSub, // X86/X64
+ kX86InstSubPD, // SSE2
+ kX86InstSubPS, // SSE
+ kX86InstSubSD, // SSE2
+ kX86InstSubSS, // SSE
+ kX86InstTest, // X86/X64
+ kX86InstUComISD, // SSE2
+ kX86InstUComISS, // SSE
+ kX86InstUd2, // X86/X64
+ kX86InstUnpckHPD, // SSE2
+ kX86InstUnpckHPS, // SSE
+ kX86InstUnpckLPD, // SSE2
+ kX86InstUnpckLPS, // SSE
+ kX86InstXadd, // X86/X64 (i486)
+ kX86InstXchg, // X86/X64 (i386)
+ kX86InstXor, // X86/X64
+ kX86InstXorPD, // SSE2
+ kX86InstXorPS, // SSE
+
+ _kX86InstCount,
+
+ _kX86InstJBegin = kX86InstJ,
+ _kX86InstJEnd = kX86InstJmp
+};
+
+// ============================================================================
+// [AsmJit::kX86InstGroup]
+// ============================================================================
+
+//! @brief X86 instruction groups.
+//!
+//! This should be only used by assembler, because it's @c AsmJit::Assembler
+//! specific grouping. Each group represents one 'case' in the Assembler's
+//! main emit method.
+enum kX86InstGroup
+{
+ // Group categories.
+ kX86InstGroupNone,
+ kX86InstGroupEmit,
+
+ kX86InstGroupArith,
+ kX86InstGroupBSwap,
+ kX86InstGroupBTest,
+ kX86InstGroupCall,
+ kX86InstGroupCrc32,
+ kX86InstGroupEnter,
+ kX86InstGroupIMul,
+ kX86InstGroupIncDec,
+ kX86InstGroupJcc,
+ kX86InstGroupJmp,
+ kX86InstGroupLea,
+ kX86InstGroupMem,
+ kX86InstGroupMov,
+ kX86InstGroupMovPtr,
+ kX86InstGroupMovSxMovZx,
+ kX86InstGroupMovSxD,
+ kX86InstGroupPush,
+ kX86InstGroupPop,
+ kX86InstGroupRegRm,
+ kX86InstGroupRm,
+ kX86InstGroupRmByte,
+ kX86InstGroupRmReg,
+ kX86InstGroupRep,
+ kX86InstGroupRet,
+ kX86InstGroupRot,
+ kX86InstGroupShldShrd,
+ kX86InstGroupTest,
+ kX86InstGroupXchg,
+
+ // Group for x87 FP instructions in format mem or st(i), st(i) (fadd, fsub, fdiv, ...)
+ kX86InstGroupX87StM,
+ // Group for x87 FP instructions in format st(i), st(i)
+ kX86InstGroupX87StI,
+ // Group for fld/fst/fstp instruction, internally uses @ref kX86InstGroupX87StM group.
+ kX86InstGroupX87FldFst,
+ // Group for x87 FP instructions that uses Word, DWord, QWord or TWord memory pointer.
+ kX86InstGroupX87Mem,
+ // Group for x87 FSTSW/FNSTSW instructions
+ kX86InstGroupX87Status,
+
+ // Group for movbe instruction
+ kX86InstGroupMovBE,
+
+ // Group for MMX/SSE instructions in format (X)MM|Reg|Mem <- (X)MM|Reg|Mem,
+ // 0x66 prefix must be set manually in opcodes.
+ // - Primary opcode is used for instructions in (X)MM <- (X)MM/Mem format,
+ // - Secondary opcode is used for instructions in (X)MM/Mem <- (X)MM format.
+ kX86InstGroupMmuMov,
+ kX86InstGroupMmuMovD,
+ kX86InstGroupMmuMovQ,
+
+ // Group for pextrd, pextrq and pextrw instructions (it's special instruction
+ // not similar to others)
+ kX86InstGroupMmuExtract,
+ // Group for prefetch instruction
+ kX86InstGroupMmuPrefetch,
+
+ // Group for MMX/SSE instructions in format (X)MM|Reg <- (X)MM|Reg|Mem|Imm,
+ // 0x66 prefix is added for MMX instructions that used by SSE2 registers.
+ // - Primary opcode is used for instructions in (X)MM|Reg <- (X)MM|Reg|Mem format,
+ // - Secondary opcode is iused for instructions in (X)MM|Reg <- Imm format.
+ kX86InstGroupMmuRmI,
+ kX86InstGroupMmuRmImm8,
+ // Group for 3dNow instructions
+ kX86InstGroupMmuRm3dNow
+};
+
+// ============================================================================
+// [AsmJit::kX86InstFlags]
+// ============================================================================
+
+//! @brief X86 instruction type flags.
+enum kX86InstFlags
+{
+ //! @brief No flags.
+ kX86InstFlagNone = 0x00,
+
+ //! @brief Instruction is jump, conditional jump, call or ret.
+ kX86InstFlagJump = 0x01,
+
+ //! @brief Instruction will overwrite first operand - o[0].
+ kX86InstFlagMov = 0x02,
+
+ //! @brief Instruction is X87 FPU.
+ kX86InstFlagFpu = 0x04,
+
+ //! @brief Instruction can be prepended using LOCK prefix
+ //! (usable for multithreaded applications).
+ kX86InstFlagLockable = 0x08,
+
+ //! @brief Instruction is special, this is for @c Compiler.
+ kX86InstFlagSpecial = 0x10,
+
+ //! @brief Instruction always performs memory access.
+ //!
+ //! This flag is always combined with @c kX86InstFlagSpecial and signalizes
+ //! that there is an implicit address which is accessed (usually EDI/RDI or
+ //! ESI/EDI).
+ kX86InstFlagSpecialMem = 0x20
+};
+
+// ============================================================================
+// [AsmJit::kX86InstOp]
+// ============================================================================
+
+//! @brief X86 instruction operand flags.
+enum kX86InstOp
+{
+ // X86, MM, XMM
+ kX86InstOpGb = 0x0001,
+ kX86InstOpGw = 0x0002,
+ kX86InstOpGd = 0x0004,
+ kX86InstOpGq = 0x0008,
+ kX86InstOpMm = 0x0010,
+ kX86InstOpXmm = 0x0020,
+ kX86InstOpMem = 0x0040,
+ kX86InstOpImm = 0x0080,
+
+ kX86InstOpGbMem = kX86InstOpGb | kX86InstOpMem,
+ kX86InstOpGwMem = kX86InstOpGw | kX86InstOpMem,
+ kX86InstOpGdMem = kX86InstOpGd | kX86InstOpMem,
+ kX86InstOpGqMem = kX86InstOpGq | kX86InstOpMem,
+
+ kX86InstOpGqdwb = kX86InstOpGq | kX86InstOpGd | kX86InstOpGw | kX86InstOpGb,
+ kX86InstOpGqdw = kX86InstOpGq | kX86InstOpGd | kX86InstOpGw,
+ kX86InstOpGqd = kX86InstOpGq | kX86InstOpGd,
+ kX86InstOpGwb = kX86InstOpGw | kX86InstOpGb,
+
+ kX86InstOpGqdwbMem = kX86InstOpGqdwb | kX86InstOpMem,
+ kX86InstOpGqdwMem = kX86InstOpGqdw | kX86InstOpMem,
+ kX86InstOpGqdMem = kX86InstOpGqd | kX86InstOpMem,
+ kX86InstOpGwbMem = kX86InstOpGwb | kX86InstOpMem,
+
+ // MMX/XMM.
+ kX86InstOpMmMem = kX86InstOpMm | kX86InstOpMem,
+ kX86InstOpXmmMem = kX86InstOpXmm | kX86InstOpMem,
+ kX86InstOpMmXmm = kX86InstOpMm | kX86InstOpXmm,
+ kX86InstOpMmXmmMem = kX86InstOpMmXmm | kX86InstOpMem,
+
+ // X87.
+ kX86InstOpStM2 = kX86InstOpMem | 0x0100,
+ kX86InstOpStM4 = kX86InstOpMem | 0x0200,
+ kX86InstOpStM8 = kX86InstOpMem | 0x0400,
+ kX86InstOpStM10 = kX86InstOpMem | 0x0800,
+
+ kX86InstOpStM2_4 = kX86InstOpStM2 | kX86InstOpStM4,
+ kX86InstOpStM2_4_8 = kX86InstOpStM2_4 | kX86InstOpStM8,
+ kX86InstOpStM4_8 = kX86InstOpStM4 | kX86InstOpStM8,
+ kX86InstOpStM4_8_10 = kX86InstOpStM4_8 | kX86InstOpStM10,
+
+ // Don't emit REX prefix.
+ kX86InstOpNoRex = 0x2000
+};
+
+// ============================================================================
+// [AsmJit::x86InstName]
+// ============================================================================
+
+//! @internal
+//!
+//! @brief X86 instruction names.
+ASMJIT_VAR const char x86InstName[];
+
+// ============================================================================
+// [AsmJit::X86InstInfo]
+// ============================================================================
+
+//! @brief X86 instruction information.
+struct X86InstInfo
+{
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get instruction code, see @ref kX86InstCode.
+ uint32_t getCode() const
+ { return _code; }
+
+ //! @brief Get instruction name string (null terminated string).
+ const char* getName() const
+ { return x86InstName + static_cast<uint32_t>(_nameIndex); }
+
+ //! @brief Get instruction name index (index to @ref x86InstName array).
+ uint32_t getNameIndex() const
+ { return _nameIndex; }
+
+ //! @brief Get instruction group, see @ref kX86InstGroup.
+ uint32_t getGroup() const
+ { return _group; }
+
+ //! @brief Get instruction flags, see @ref kX86InstFlags.
+ uint32_t getFlags() const
+ { return _group; }
+
+ //! @brief Get whether the instruction is conditional or standard jump.
+ bool isJump() const
+ { return !!(_flags & kX86InstFlagJump); }
+
+ //! @brief Get whether the instruction is MOV type.
+ bool isMov() const
+ { return !!(_flags & kX86InstFlagMov); }
+
+ //! @brief Get whether the instruction is X87 FPU type.
+ bool isFpu() const
+ { return !!(_flags & kX86InstFlagFpu); }
+
+ //! @brief Get whether the instruction can be prefixed by LOCK prefix.
+ bool isLockable() const
+ { return !!(_flags & kX86InstFlagLockable); }
+
+ //! @brief Get whether the instruction is special type (this is used by
+ //! @c Compiler to manage additional variables or functionality).
+ bool isSpecial() const
+ { return !!(_flags & kX86InstFlagSpecial); }
+
+ //! @brief Get whether the instruction is special type and it performs
+ //! memory access.
+ bool isSpecialMem() const
+ { return !!(_flags & kX86InstFlagSpecialMem); }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Instruction code.
+ uint16_t _code;
+ //! @brief Instruction name index in x86InstName[] array.
+ uint16_t _nameIndex;
+ //! @brief Instruction group, used also by @c Compiler.
+ uint8_t _group;
+ //! @brief Instruction type flags.
+ uint8_t _flags;
+
+ //! @brief First and second operand flags (some groups depends on these settings, used also by @c Compiler).
+ uint16_t _opFlags[2];
+ //! @brief If instruction has only memory operand, this is register opcode.
+ uint16_t _opCodeR;
+ //! @brief Primary and secondary opcodes.
+ uint32_t _opCode[2];
+};
+
+// ============================================================================
+// [AsmJit::x86InstInfo]
+// ============================================================================
+
+ASMJIT_VAR const X86InstInfo x86InstInfo[];
+
+// ============================================================================
+// [AsmJit::kX86FuncConv]
+// ============================================================================
+
+//! @brief X86 function calling conventions.
+//!
+//! Calling convention is scheme how function arguments are passed into
+//! function and how functions returns values. In assembler programming
+//! it's needed to always comply with function calling conventions, because
+//! even small inconsistency can cause undefined behavior or crash.
+//!
+//! List of calling conventions for 32-bit x86 mode:
+//! - @c kX86FuncConvCDecl - Calling convention for C runtime.
+//! - @c kX86FuncConvStdCall - Calling convention for WinAPI functions.
+//! - @c kX86FuncConvMsThisCall - Calling convention for C++ members under
+//! Windows (produced by MSVC and all MSVC compatible compilers).
+//! - @c kX86FuncConvMsFastCall - Fastest calling convention that can be used
+//! by MSVC compiler.
+//! - @c kX86FuncConv_BORNANDFASTCALL - Borland fastcall convention.
+//! - @c kX86FuncConvGccFastCall - GCC fastcall convention (2 register arguments).
+//! - @c kX86FuncConvGccRegParm1 - GCC regparm(1) convention.
+//! - @c kX86FuncConvGccRegParm2 - GCC regparm(2) convention.
+//! - @c kX86FuncConvGccRegParm3 - GCC regparm(3) convention.
+//!
+//! List of calling conventions for 64-bit x86 mode (x64):
+//! - @c kX86FuncConvX64W - Windows 64-bit calling convention (WIN64 ABI).
+//! - @c kX86FuncConvX64U - Unix 64-bit calling convention (AMD64 ABI).
+//!
+//! There is also @c kX86FuncConvDefault that is defined to fit best to your
+//! compiler.
+//!
+//! These types are used together with @c AsmJit::Compiler::newFunc()
+//! method.
+enum kX86FuncConv
+{
+ // --------------------------------------------------------------------------
+ // [X64]
+ // --------------------------------------------------------------------------
+
+ //! @brief X64 calling convention for Windows platform (WIN64 ABI).
+ //!
+ //! For first four arguments are used these registers:
+ //! - 1. 32/64-bit integer or floating point argument - rcx/xmm0
+ //! - 2. 32/64-bit integer or floating point argument - rdx/xmm1
+ //! - 3. 32/64-bit integer or floating point argument - r8/xmm2
+ //! - 4. 32/64-bit integer or floating point argument - r9/xmm3
+ //!
+ //! Note first four arguments here means arguments at positions from 1 to 4
+ //! (included). For example if second argument is not passed by register then
+ //! rdx/xmm1 register is unused.
+ //!
+ //! All other arguments are pushed on the stack in right-to-left direction.
+ //! Stack is aligned by 16 bytes. There is 32-byte shadow space on the stack
+ //! that can be used to save up to four 64-bit registers (probably designed to
+ //! be used to save first four arguments passed in registers).
+ //!
+ //! Arguments direction:
+ //! - Right to Left (except for first 4 parameters that's in registers)
+ //!
+ //! Stack is cleaned by:
+ //! - Caller.
+ //!
+ //! Return value:
+ //! - Integer types - RAX register.
+ //! - Floating points - XMM0 register.
+ //!
+ //! Stack is always aligned by 16 bytes.
+ //!
+ //! More information about this calling convention can be found on MSDN:
+ //! http://msdn.microsoft.com/en-us/library/9b372w95.aspx .
+ kX86FuncConvX64W = 1,
+
+ //! @brief X64 calling convention for Unix platforms (AMD64 ABI).
+ //!
+ //! First six 32 or 64-bit integer arguments are passed in rdi, rsi, rdx,
+ //! rcx, r8, r9 registers. First eight floating point or XMM arguments
+ //! are passed in xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7 registers.
+ //! This means that in registers can be transferred up to 14 arguments total.
+ //!
+ //! There is also RED ZONE below the stack pointer that can be used for
+ //! temporary storage. The red zone is the space from [rsp-128] to [rsp-8].
+ //!
+ //! Arguments direction:
+ //! - Right to Left (Except for arguments passed in registers).
+ //!
+ //! Stack is cleaned by:
+ //! - Caller.
+ //!
+ //! Return value:
+ //! - Integer types - RAX register.
+ //! - Floating points - XMM0 register.
+ //!
+ //! Stack is always aligned by 16 bytes.
+ kX86FuncConvX64U = 2,
+
+ // --------------------------------------------------------------------------
+ // [X86]
+ // --------------------------------------------------------------------------
+
+ //! @brief Cdecl calling convention (used by C runtime).
+ //!
+ //! Compatible across MSVC and GCC.
+ //!
+ //! Arguments direction:
+ //! - Right to Left
+ //!
+ //! Stack is cleaned by:
+ //! - Caller.
+ kX86FuncConvCDecl = 3,
+
+ //! @brief Stdcall calling convention (used by WinAPI).
+ //!
+ //! Compatible across MSVC and GCC.
+ //!
+ //! Arguments direction:
+ //! - Right to Left
+ //!
+ //! Stack is cleaned by:
+ //! - Callee.
+ //!
+ //! Return value:
+ //! - Integer types - EAX:EDX registers.
+ //! - Floating points - st(0) register.
+ kX86FuncConvStdCall = 4,
+
+ //! @brief MSVC specific calling convention used by MSVC/Intel compilers
+ //! for struct/class methods.
+ //!
+ //! This is MSVC (and Intel) only calling convention used in Windows
+ //! world for C++ class methods. Implicit 'this' pointer is stored in
+ //! ECX register instead of storing it on the stack.
+ //!
+ //! Arguments direction:
+ //! - Right to Left (except this pointer in ECX)
+ //!
+ //! Stack is cleaned by:
+ //! - Callee.
+ //!
+ //! Return value:
+ //! - Integer types - EAX:EDX registers.
+ //! - Floating points - st(0) register.
+ //!
+ //! C++ class methods that have variable count of arguments uses different
+ //! calling convention called cdecl.
+ //!
+ //! @note This calling convention is always used by MSVC for class methods,
+ //! it's implicit and there is no way how to override it.
+ kX86FuncConvMsThisCall = 5,
+
+ //! @brief MSVC specific fastcall.
+ //!
+ //! Two first parameters (evaluated from left-to-right) are in ECX:EDX
+ //! registers, all others on the stack in right-to-left order.
+ //!
+ //! Arguments direction:
+ //! - Right to Left (except to first two integer arguments in ECX:EDX)
+ //!
+ //! Stack is cleaned by:
+ //! - Callee.
+ //!
+ //! Return value:
+ //! - Integer types - EAX:EDX registers.
+ //! - Floating points - st(0) register.
+ //!
+ //! @note This calling convention differs to GCC one in stack cleaning
+ //! mechanism.
+ kX86FuncConvMsFastCall = 6,
+
+ //! @brief Borland specific fastcall with 2 parameters in registers.
+ //!
+ //! Two first parameters (evaluated from left-to-right) are in ECX:EDX
+ //! registers, all others on the stack in left-to-right order.
+ //!
+ //! Arguments direction:
+ //! - Left to Right (except to first two integer arguments in ECX:EDX)
+ //!
+ //! Stack is cleaned by:
+ //! - Callee.
+ //!
+ //! Return value:
+ //! - Integer types - EAX:EDX registers.
+ //! - Floating points - st(0) register.
+ //!
+ //! @note Arguments on the stack are in left-to-right order that differs
+ //! to other fastcall conventions used in different compilers.
+ kX86FuncConvBorlandFastCall = 7,
+
+ //! @brief GCC specific fastcall convention.
+ //!
+ //! Two first parameters (evaluated from left-to-right) are in ECX:EDX
+ //! registers, all others on the stack in right-to-left order.
+ //!
+ //! Arguments direction:
+ //! - Right to Left (except to first two integer arguments in ECX:EDX)
+ //!
+ //! Stack is cleaned by:
+ //! - Callee.
+ //!
+ //! Return value:
+ //! - Integer types - EAX:EDX registers.
+ //! - Floating points - st(0) register.
+ //!
+ //! @note This calling convention should be compatible to
+ //! @c kX86FuncConvMsFastCall.
+ kX86FuncConvGccFastCall = 8,
+
+ //! @brief GCC specific regparm(1) convention.
+ //!
+ //! The first parameter (evaluated from left-to-right) is in EAX register,
+ //! all others on the stack in right-to-left order.
+ //!
+ //! Arguments direction:
+ //! - Right to Left (except to first one integer argument in EAX)
+ //!
+ //! Stack is cleaned by:
+ //! - Caller.
+ //!
+ //! Return value:
+ //! - Integer types - EAX:EDX registers.
+ //! - Floating points - st(0) register.
+ kX86FuncConvGccRegParm1 = 9,
+
+ //! @brief GCC specific regparm(2) convention.
+ //!
+ //! Two first parameters (evaluated from left-to-right) are in EAX:EDX
+ //! registers, all others on the stack in right-to-left order.
+ //!
+ //! Arguments direction:
+ //! - Right to Left (except to first two integer arguments in EAX:EDX)
+ //!
+ //! Stack is cleaned by:
+ //! - Caller.
+ //!
+ //! Return value:
+ //! - Integer types - EAX:EDX registers.
+ //! - Floating points - st(0) register.
+ kX86FuncConvGccRegParm2 = 10,
+
+ //! @brief GCC specific fastcall with 3 parameters in registers.
+ //!
+ //! Three first parameters (evaluated from left-to-right) are in
+ //! EAX:EDX:ECX registers, all others on the stack in right-to-left order.
+ //!
+ //! Arguments direction:
+ //! - Right to Left (except to first three integer arguments in EAX:EDX:ECX)
+ //!
+ //! Stack is cleaned by:
+ //! - Caller.
+ //!
+ //! Return value:
+ //! - Integer types - EAX:EDX registers.
+ //! - Floating points - st(0) register.
+ kX86FuncConvGccRegParm3 = 11,
+
+ // --------------------------------------------------------------------------
+ // [Detect]
+ // --------------------------------------------------------------------------
+
+ //! @def kX86FuncConvDefault
+ //! @brief Default calling convention for current platform / operating system.
+
+ //! @def kX86FuncConvCompatFastCall
+ //! @brief Compatibility for __fastcall calling convention.
+ //!
+ //! @note This enumeration is always set to a value which is compatible to
+ //! current compilers __fastcall calling convention. In 64-bit mode the value
+ //! is compatible to @ref kX86FuncConvX64W or @ref kX86FuncConvX64U.
+
+ //! @def kX86FuncConvCompatStdCall
+ //! @brief Compatibility for __stdcall calling convention.
+ //!
+ //! @note This enumeration is always set to a value which is compatible to
+ //! current compilers __stdcall calling convention. In 64-bit mode the value
+ //! is compatible to @ref kX86FuncConvX64W or @ref kX86FuncConvX64U.
+
+ //! @def kX86FuncConvCompatCDecl
+ //! @brief Default C calling convention based on current compiler's settings.
+
+#if defined(ASMJIT_X86)
+
+ kX86FuncConvDefault = kX86FuncConvCDecl,
+
+# if defined(_MSC_VER)
+ kX86FuncConvCompatFastCall = kX86FuncConvMsFastCall,
+# elif defined(__GNUC__)
+ kX86FuncConvCompatFastCall = kX86FuncConvGccFastCall,
+# elif defined(__BORLANDC__)
+ kX86FuncConvCompatFastCall = kX86FuncConvBorlandFastCall,
+# else
+# error "AsmJit::kX86FuncConvCompatFastCall not supported."
+# endif
+
+ kX86FuncConvCompatStdCall = kX86FuncConvStdCall,
+ kX86FuncConvCompatCDecl = kX86FuncConvCDecl
+
+#else
+
+# if defined(ASMJIT_WINDOWS)
+ kX86FuncConvDefault = kX86FuncConvX64W,
+# else
+ kX86FuncConvDefault = kX86FuncConvX64U,
+# endif
+
+ kX86FuncConvCompatFastCall = kX86FuncConvDefault,
+ kX86FuncConvCompatStdCall = kX86FuncConvDefault,
+ kX86FuncConvCompatCDecl = kX86FuncConvDefault
+
+#endif // ASMJIT_X86
+};
+
+// ============================================================================
+// [AsmJit::kX86FuncHint]
+// ============================================================================
+
+//! @brief X86 function hints.
+enum kX86FuncHint
+{
+ //! @brief Use push/pop sequences instead of mov sequences in function prolog
+ //! and epilog.
+ kX86FuncHintPushPop = 8,
+ //! @brief Add emms instruction to the function epilog.
+ kX86FuncHintEmms = 9,
+ //! @brief Add sfence instruction to the function epilog.
+ kX86FuncHintSFence = 10,
+ //! @brief Add lfence instruction to the function epilog.
+ kX86FuncHintLFence = 11,
+ //! @brief Assume that stack is aligned to 16-bytes.
+ kX86FuncHintAssume16ByteAlignment = 12,
+ //! @brief Perform 16-byte stack alignmend by function.
+ kX86FuncHintPerform16ByteAlignment = 13
+};
+
+// ============================================================================
+// [AsmJit::kX86FuncFlags]
+// ============================================================================
+
+//! @brief X86 function flags.
+enum kX86FuncFlags
+{
+ //! @brief Whether to emit prolog / epilog sequence using push & pop
+ //! instructions (the default).
+ kX86FuncFlagPushPop = (1U << 8),
+
+ //! @brief Whether to emit EMMS instruction in epilog (auto-detected).
+ kX86FuncFlagEmitEmms = (1U << 9),
+
+ //! @brief Whether to emit SFence instruction in epilog (auto-detected).
+ //!
+ //! @note @ref kX86FuncFlagEmitSFence and @ref kX86FuncFlagEmitLFence
+ //! combination will result in emitting mfence.
+ kX86FuncFlagEmitSFence = (1U << 10),
+
+ //! @brief Whether to emit LFence instruction in epilog (auto-detected).
+ //!
+ //! @note @ref kX86FuncFlagEmitSFence and @ref kX86FuncFlagEmitLFence
+ //! combination will result in emitting mfence.
+ kX86FuncFlagEmitLFence = (1U << 11),
+
+ //! @brief Whether the function stack is aligned by 16-bytes by OS.
+ //!
+ //! This is always true for 64-bit mode and for linux.
+ kX86FuncFlagAssume16ByteAlignment = (1U << 12),
+
+ //! @brief Whether the function stack (for variables) is aligned manually
+ //! by function to 16-bytes.
+ //!
+ //! This makes sense only if @ref kX86FuncFlagAssume16ByteAlignment is
+ //! false and MOVDQA instruction or other SSE/SSE2 instructions are used to
+ //! work with variables stored on the stack.
+ //!
+ //! Value is determined automatically by these factors, expectations are:
+ //!
+ //! 1. There is 16-byte wide variable which address was used (alloc, spill,
+ //! op).
+ //! 2. Function can't be naked.
+ kX86FuncFlagPerform16ByteAlignment = (1U << 13),
+
+ //! @brief Whether the ESP register is adjusted by the stack size needed
+ //! to save registers and function variables.
+ //!
+ //! Esp is adjusted by 'sub' instruction in prolog and by add function in
+ //! epilog (only if function is not naked).
+ kX86FuncFlagIsEspAdjusted = (1U << 14)
+};
+
+// ============================================================================
+// [AsmJit::kX86CompilerInst]
+// ============================================================================
+
+//! @brief Instruction flags used by @ref X86CompilerInst item.
+enum kX86CompilerInstFlag
+{
+ //! @brief Whether the instruction is special.
+ kX86CompilerInstFlagIsSpecial = (1U << 0),
+ //! @brief Whether the instruction is FPU.
+ kX86CompilerInstFlagIsFpu = (1U << 1),
+ //! @brief Whether the one of the operands is GPB.Lo register.
+ kX86CompilerInstFlagIsGpbLoUsed = (1U << 2),
+ //! @brief Whether the one of the operands is GPB.Hi register.
+ kX86CompilerInstFlagIsGpbHiUsed = (1U << 3),
+
+ //! @brief Whether the jmp/jcc is likely to be taken.
+ kX86CompilerInstFlagIsTaken = (1U << 7)
+};
+
+// ============================================================================
+// [AsmJit::kX86VarClass]
+// ============================================================================
+
+//! @brief X86 variable class.
+enum kX86VarClass
+{
+ //! @brief No class (used internally).
+ kX86VarClassNone = 0,
+ //! @brief General purpose register.
+ kX86VarClassGp = 1,
+ //! @brief X87 floating point.
+ kX86VarClassX87 = 2,
+ //! @brief MMX register.
+ kX86VarClassMm = 3,
+ //! @brief XMM register.
+ kX86VarClassXmm = 4,
+
+ //! @brief Count of X86 variable classes.
+ kX86VarClassCount = 5
+};
+
+// ============================================================================
+// [AsmJit::kX86VarFlags]
+// ============================================================================
+
+//! @brief X86 variable class.
+enum kX86VarFlags
+{
+ //! @brief Variable contains single-precision floating-point(s).
+ kX86VarFlagSP = 0x10,
+ //! @brief Variable contains double-precision floating-point(s).
+ kX86VarFlagDP = 0x20,
+ //! @brief Variable is packed (for example float4x, double2x, ...).
+ kX86VarFlagPacked = 0x40
+};
+
+// ============================================================================
+// [AsmJit::kX86VarType]
+// ============================================================================
+
+//! @brief X86 variable type.
+enum kX86VarType
+{
+ // --------------------------------------------------------------------------
+ // [Platform Dependent]
+ // --------------------------------------------------------------------------
+
+ //! @brief Variable is 32-bit general purpose register.
+ kX86VarTypeGpd = 0,
+ //! @brief Variable is 64-bit general purpose register.
+ kX86VarTypeGpq = 1,
+
+ //! @var kX86VarTypeGpz
+ //! @brief Variable is system wide general purpose register (32-bit or 64-bit).
+#if defined(ASMJIT_X86)
+ kX86VarTypeGpz = kX86VarTypeGpd,
+#else
+ kX86VarTypeGpz = kX86VarTypeGpq,
+#endif
+
+ //! @brief Variable is X87 (FPU).
+ kX86VarTypeX87 = 2,
+ //! @brief Variable is X87 (FPU) SP-FP number (float).
+ kX86VarTypeX87SS = 3,
+ //! @brief Variable is X87 (FPU) DP-FP number (double).
+ kX86VarTypeX87SD = 4,
+
+ //! @brief Variable is MM register / memory location.
+ kX86VarTypeMm = 5,
+ //! @brief Variable is XMM register / memory location.
+ kX86VarTypeXmm = 6,
+
+ //! @brief Variable is SSE scalar SP-FP number.
+ kX86VarTypeXmmSS = 7,
+ //! @brief Variable is SSE packed SP-FP number (4 floats).
+ kX86VarTypeXmmPS = 8,
+
+ //! @brief Variable is SSE2 scalar DP-FP number.
+ kX86VarTypeXmmSD = 9,
+ //! @brief Variable is SSE2 packed DP-FP number (2 doubles).
+ kX86VarTypeXmmPD = 10,
+
+ //! @brief Count of variable types.
+ kX86VarTypeCount = 11,
+
+ // --------------------------------------------------------------------------
+ // [Platform Independent]
+ // --------------------------------------------------------------------------
+
+ //! @brief Variable is 32-bit integer.
+ kX86VarTypeInt32 = kX86VarTypeGpd,
+ //! @brief Variable is 64-bit integer.
+ kX86VarTypeInt64 = kX86VarTypeGpq,
+ //! @brief Variable is system dependent integer / pointer.
+ kX86VarTypeIntPtr = kX86VarTypeGpz,
+
+#if defined(ASMJIT_X86)
+ kX86VarTypeFloat = kX86VarTypeX87SS,
+ kX86VarTypeDouble = kX86VarTypeX87SD
+#else
+ kX86VarTypeFloat = kX86VarTypeXmmSS,
+ kX86VarTypeDouble = kX86VarTypeXmmSD
+#endif
+};
+
+// ============================================================================
+// [AsmJit::X86VarInfo]
+// ============================================================================
+
+//! @brief X86 variable information.
+struct X86VarInfo
+{
+ // --------------------------------------------------------------------------
+ // [Accessors]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get register code base, see @ref kX86RegCode.
+ uint32_t getCode() const
+ { return _code; }
+
+ //! @brief Get register size in bytes.
+ uint32_t getSize() const
+ { return _size; }
+
+ //! @brief Get variable class, see @ref kX86VarClass.
+ uint32_t getClass() const
+ { return _class; }
+
+ //! @brief Get variable flags, see @ref kX86VarFlags.
+ uint32_t getFlags() const
+ { return _flags; }
+
+ //! @brief Get variable type name.
+ const char* getName() const
+ { return _name; }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Register code base, see @ref kX86RegCode.
+ uint32_t _code;
+ //! @brief Register size in bytes.
+ uint16_t _size;
+ //! @brief Variable class, see @ref kX86VarClass.
+ uint8_t _class;
+ //! @brief Variable flags, see @ref kX86VarFlags.
+ uint8_t _flags;
+ //! @brief Variable type name.
+ char _name[8];
+};
+
+// ============================================================================
+// [AsmJit::x86VarInfo]
+// ============================================================================
+
+ASMJIT_VAR const X86VarInfo x86VarInfo[];
+
+//! @}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_X86_X86DEFS_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86/x86func.cpp
@@ -1,1 +1,645 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../core/assert.h"
+#include "../core/intutil.h"
+#include "../core/stringutil.h"
+
+#include "../x86/x86defs.h"
+#include "../x86/x86func.h"
+#include "../x86/x86util.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit {
+
+// ============================================================================
+// [AsmJit::X86FuncDecl - Accessors]
+// ============================================================================
+
+uint32_t X86FuncDecl::findArgumentByRegCode(uint32_t regCode) const
+{
+ uint32_t type = regCode & kRegTypeMask;
+ uint32_t idx = regCode & kRegIndexMask;
+
+ uint32_t clazz;
+
+ switch (type)
+ {
+ case kX86RegTypeGpd:
+ case kX86RegTypeGpq:
+ clazz = kX86VarClassGp;
+ break;
+
+ case kX86RegTypeX87:
+ clazz = kX86VarClassX87;
+ break;
+
+ case kX86RegTypeMm:
+ clazz = kX86VarClassMm;
+ break;
+
+ case kX86RegTypeXmm:
+ clazz = kX86VarClassXmm;
+ break;
+
+ default:
+ return kInvalidValue;
+ }
+
+ for (uint32_t i = 0; i < _argumentsCount; i++)
+ {
+ const FuncArg& arg = _arguments[i];
+
+ if (arg.getRegIndex() == idx && (X86Util::getVarClassFromVarType(arg.getVarType()) & clazz))
+ return i;
+ }
+
+ return kInvalidValue;
+}
+
+// ============================================================================
+// [AsmJit::X86FuncDecl - SetPrototype - InitCallingConvention]
+// ============================================================================
+
+static void X86FuncDecl_initCallingConvention(X86FuncDecl* self, uint32_t convention)
+{
+ uint32_t i;
+
+ // --------------------------------------------------------------------------
+ // [Inir]
+ // --------------------------------------------------------------------------
+
+ self->_convention = convention;
+ self->_calleePopsStack = false;
+ self->_argumentsDirection = kFuncArgsRTL;
+
+ for (i = 0; i < ASMJIT_ARRAY_SIZE(self->_gpList); i++)
+ self->_gpList[i] = kRegIndexInvalid;
+
+ for (i = 0; i < ASMJIT_ARRAY_SIZE(self->_xmmList); i++)
+ self->_xmmList[i] = kRegIndexInvalid;
+
+ self->_gpListMask = 0x0;
+ self->_mmListMask = 0x0;
+ self->_xmmListMask = 0x0;
+
+ self->_gpPreservedMask = 0x0;
+ self->_mmPreservedMask = 0x0;
+ self->_xmmPreservedMask = 0x0;
+
+ // --------------------------------------------------------------------------
+ // [X86 Calling Conventions]
+ // --------------------------------------------------------------------------
+
+#if defined(ASMJIT_X86)
+ self->_gpPreservedMask = static_cast<uint16_t>(
+ IntUtil::maskFromIndex(kX86RegIndexEbx) |
+ IntUtil::maskFromIndex(kX86RegIndexEsp) |
+ IntUtil::maskFromIndex(kX86RegIndexEbp) |
+ IntUtil::maskFromIndex(kX86RegIndexEsi) |
+ IntUtil::maskFromIndex(kX86RegIndexEdi));
+ self->_xmmPreservedMask = 0;
+
+ switch (convention)
+ {
+ // ------------------------------------------------------------------------
+ // [CDecl]
+ // ------------------------------------------------------------------------
+
+ case kX86FuncConvCDecl:
+ break;
+
+ // ------------------------------------------------------------------------
+ // [StdCall]
+ // ------------------------------------------------------------------------
+
+ case kX86FuncConvStdCall:
+ self->_calleePopsStack = true;
+ break;
+
+ // ------------------------------------------------------------------------
+ // [MS-ThisCall]
+ // ------------------------------------------------------------------------
+
+ case kX86FuncConvMsThisCall:
+ self->_calleePopsStack = true;
+
+ self->_gpList[0] = kX86RegIndexEcx;
+
+ self->_gpListMask = static_cast<uint16_t>(
+ IntUtil::maskFromIndex(kX86RegIndexEcx));
+ break;
+
+ // ------------------------------------------------------------------------
+ // [MS-FastCall]
+ // ------------------------------------------------------------------------
+
+ case kX86FuncConvMsFastCall:
+ self->_calleePopsStack = true;
+
+ self->_gpList[0] = kX86RegIndexEcx;
+ self->_gpList[1] = kX86RegIndexEdx;
+
+ self->_gpListMask = static_cast<uint16_t>(
+ IntUtil::maskFromIndex(kX86RegIndexEcx) |
+ IntUtil::maskFromIndex(kX86RegIndexEdx));
+ break;
+
+ // ------------------------------------------------------------------------
+ // [Borland-FastCall]
+ // ------------------------------------------------------------------------
+
+ case kX86FuncConvBorlandFastCall:
+ self->_calleePopsStack = true;
+ self->_argumentsDirection = kFuncArgsLTR;
+
+ self->_gpList[0] = kX86RegIndexEax;
+ self->_gpList[1] = kX86RegIndexEdx;
+ self->_gpList[2] = kX86RegIndexEcx;
+
+ self->_gpListMask = static_cast<uint16_t>(
+ IntUtil::maskFromIndex(kX86RegIndexEax) |
+ IntUtil::maskFromIndex(kX86RegIndexEdx) |
+ IntUtil::maskFromIndex(kX86RegIndexEcx));
+ break;
+
+ // ------------------------------------------------------------------------
+ // [Gcc-FastCall]
+ // ------------------------------------------------------------------------
+
+ case kX86FuncConvGccFastCall:
+ self->_calleePopsStack = true;
+
+ self->_gpList[0] = kX86RegIndexEcx;
+ self->_gpList[1] = kX86RegIndexEdx;
+
+ self->_gpListMask = static_cast<uint16_t>(
+ IntUtil::maskFromIndex(kX86RegIndexEcx) |
+ IntUtil::maskFromIndex(kX86RegIndexEdx));
+ break;
+
+ // ------------------------------------------------------------------------
+ // [Gcc-Regparm(1)]
+ // ------------------------------------------------------------------------
+
+ case kX86FuncConvGccRegParm1:
+ self->_calleePopsStack = false;
+
+ self->_gpList[0] = kX86RegIndexEax;
+ self->_gpListMask = static_cast<uint16_t>(
+ IntUtil::maskFromIndex(kX86RegIndexEax));
+ break;
+
+ // ------------------------------------------------------------------------
+ // [Gcc-Regparm(2)]
+ // ------------------------------------------------------------------------
+
+ case kX86FuncConvGccRegParm2:
+ self->_calleePopsStack = false;
+
+ self->_gpList[0] = kX86RegIndexEax;
+ self->_gpList[1] = kX86RegIndexEdx;
+
+ self->_gpListMask = static_cast<uint16_t>(
+ IntUtil::maskFromIndex(kX86RegIndexEax) |
+ IntUtil::maskFromIndex(kX86RegIndexEdx));
+ break;
+
+ // ------------------------------------------------------------------------
+ // [Gcc-Regparm(3)]
+ // ------------------------------------------------------------------------
+
+ case kX86FuncConvGccRegParm3:
+ self->_calleePopsStack = false;
+
+ self->_gpList[0] = kX86RegIndexEax;
+ self->_gpList[1] = kX86RegIndexEdx;
+ self->_gpList[2] = kX86RegIndexEcx;
+
+ self->_gpListMask = static_cast<uint16_t>(
+ IntUtil::maskFromIndex(kX86RegIndexEax) |
+ IntUtil::maskFromIndex(kX86RegIndexEdx) |
+ IntUtil::maskFromIndex(kX86RegIndexEcx));
+ break;
+
+ // ------------------------------------------------------------------------
+ // [Illegal]
+ // ------------------------------------------------------------------------
+
+ default:
+ // Illegal calling convention.
+ ASMJIT_ASSERT(0);
+ }
+#endif // ASMJIT_X86
+
+ // --------------------------------------------------------------------------
+ // [X64 Calling Conventions]
+ // --------------------------------------------------------------------------
+
+#if defined(ASMJIT_X64)
+ switch (convention)
+ {
+ // ------------------------------------------------------------------------
+ // [X64-Windows]
+ // ------------------------------------------------------------------------
+
+ case kX86FuncConvX64W:
+ self->_gpList[0] = kX86RegIndexRcx;
+ self->_gpList[1] = kX86RegIndexRdx;
+ self->_gpList[2] = kX86RegIndexR8;
+ self->_gpList[3] = kX86RegIndexR9;
+
+ self->_xmmList[0] = kX86RegIndexXmm0;
+ self->_xmmList[1] = kX86RegIndexXmm1;
+ self->_xmmList[2] = kX86RegIndexXmm2;
+ self->_xmmList[3] = kX86RegIndexXmm3;
+
+ self->_gpListMask = static_cast<uint16_t>(
+ IntUtil::maskFromIndex(kX86RegIndexRcx ) |
+ IntUtil::maskFromIndex(kX86RegIndexRdx ) |
+ IntUtil::maskFromIndex(kX86RegIndexR8 ) |
+ IntUtil::maskFromIndex(kX86RegIndexR9 ));
+
+ self->_xmmListMask = static_cast<uint16_t>(
+ IntUtil::maskFromIndex(kX86RegIndexXmm0 ) |
+ IntUtil::maskFromIndex(kX86RegIndexXmm1 ) |
+ IntUtil::maskFromIndex(kX86RegIndexXmm2 ) |
+ IntUtil::maskFromIndex(kX86RegIndexXmm3 ));
+
+ self->_gpPreservedMask = static_cast<uint16_t>(
+ IntUtil::maskFromIndex(kX86RegIndexRbx ) |
+ IntUtil::maskFromIndex(kX86RegIndexRsp ) |
+ IntUtil::maskFromIndex(kX86RegIndexRbp ) |
+ IntUtil::maskFromIndex(kX86RegIndexRsi ) |
+ IntUtil::maskFromIndex(kX86RegIndexRdi ) |
+ IntUtil::maskFromIndex(kX86RegIndexR12 ) |
+ IntUtil::maskFromIndex(kX86RegIndexR13 ) |
+ IntUtil::maskFromIndex(kX86RegIndexR14 ) |
+ IntUtil::maskFromIndex(kX86RegIndexR15 ));
+
+ self->_xmmPreservedMask = static_cast<uint16_t>(
+ IntUtil::maskFromIndex(kX86RegIndexXmm6 ) |
+ IntUtil::maskFromIndex(kX86RegIndexXmm7 ) |
+ IntUtil::maskFromIndex(kX86RegIndexXmm8 ) |
+ IntUtil::maskFromIndex(kX86RegIndexXmm9 ) |
+ IntUtil::maskFromIndex(kX86RegIndexXmm10) |
+ IntUtil::maskFromIndex(kX86RegIndexXmm11) |
+ IntUtil::maskFromIndex(kX86RegIndexXmm12) |
+ IntUtil::maskFromIndex(kX86RegIndexXmm13) |
+ IntUtil::maskFromIndex(kX86RegIndexXmm14) |
+ IntUtil::maskFromIndex(kX86RegIndexXmm15));
+ break;
+
+ // ------------------------------------------------------------------------
+ // [X64-Unix]
+ // ------------------------------------------------------------------------
+
+ case kX86FuncConvX64U:
+ self->_gpList[0] = kX86RegIndexRdi;
+ self->_gpList[1] = kX86RegIndexRsi;
+ self->_gpList[2] = kX86RegIndexRdx;
+ self->_gpList[3] = kX86RegIndexRcx;
+ self->_gpList[4] = kX86RegIndexR8;
+ self->_gpList[5] = kX86RegIndexR9;
+
+ self->_xmmList[0] = kX86RegIndexXmm0;
+ self->_xmmList[1] = kX86RegIndexXmm1;
+ self->_xmmList[2] = kX86RegIndexXmm2;
+ self->_xmmList[3] = kX86RegIndexXmm3;
+ self->_xmmList[4] = kX86RegIndexXmm4;
+ self->_xmmList[5] = kX86RegIndexXmm5;
+ self->_xmmList[6] = kX86RegIndexXmm6;
+ self->_xmmList[7] = kX86RegIndexXmm7;
+
+ self->_gpListMask = static_cast<uint16_t>(
+ IntUtil::maskFromIndex(kX86RegIndexRdi ) |
+ IntUtil::maskFromIndex(kX86RegIndexRsi ) |
+ IntUtil::maskFromIndex(kX86RegIndexRdx ) |
+ IntUtil::maskFromIndex(kX86RegIndexRcx ) |
+ IntUtil::maskFromIndex(kX86RegIndexR8 ) |
+ IntUtil::maskFromIndex(kX86RegIndexR9 ));
+
+ self->_xmmListMask = static_cast<uint16_t>(
+ IntUtil::maskFromIndex(kX86RegIndexXmm0 ) |
+ IntUtil::maskFromIndex(kX86RegIndexXmm1 ) |
+ IntUtil::maskFromIndex(kX86RegIndexXmm2 ) |
+ IntUtil::maskFromIndex(kX86RegIndexXmm3 ) |
+ IntUtil::maskFromIndex(kX86RegIndexXmm4 ) |
+ IntUtil::maskFromIndex(kX86RegIndexXmm5 ) |
+ IntUtil::maskFromIndex(kX86RegIndexXmm6 ) |
+ IntUtil::maskFromIndex(kX86RegIndexXmm7 ));
+
+ self->_gpPreservedMask = static_cast<uint16_t>(
+ IntUtil::maskFromIndex(kX86RegIndexRbx ) |
+ IntUtil::maskFromIndex(kX86RegIndexRsp ) |
+ IntUtil::maskFromIndex(kX86RegIndexRbp ) |
+ IntUtil::maskFromIndex(kX86RegIndexR12 ) |
+ IntUtil::maskFromIndex(kX86RegIndexR13 ) |
+ IntUtil::maskFromIndex(kX86RegIndexR14 ) |
+ IntUtil::maskFromIndex(kX86RegIndexR15 ));
+ break;
+
+ // ------------------------------------------------------------------------
+ // [Illegal]
+ // ------------------------------------------------------------------------
+
+ default:
+ // Illegal calling convention.
+ ASMJIT_ASSERT(0);
+ }
+#endif // ASMJIT_X64
+}
+
+// ============================================================================
+// [AsmJit::X86FuncDecl - SetPrototype - InitDefinition]
+// ============================================================================
+
+static void X86FuncDecl_initDefinition(X86FuncDecl* self,
+ uint32_t returnType, const uint32_t* argumentsData, uint32_t argumentsCount)
+{
+ ASMJIT_ASSERT(argumentsCount <= kFuncArgsMax);
+
+ // --------------------------------------------------------------------------
+ // [Init]
+ // --------------------------------------------------------------------------
+
+ int32_t i = 0;
+ int32_t gpPos = 0;
+ int32_t stackOffset = 0;
+
+ self->_returnType = returnType;
+ self->_argumentsCount = static_cast<uint8_t>(argumentsCount);
+
+ while (i < static_cast<int32_t>(argumentsCount))
+ {
+ FuncArg& arg = self->_arguments[i];
+
+ arg._varType = static_cast<uint8_t>(argumentsData[i]);
+ arg._regIndex = kRegIndexInvalid;
+ arg._stackOffset = kFuncStackInvalid;
+
+ i++;
+ }
+
+ while (i < kFuncArgsMax)
+ {
+ FuncArg& arg = self->_arguments[i];
+ arg.reset();
+
+ i++;
+ }
+
+ self->_argumentsStackSize = 0;
+ self->_gpArgumentsMask = 0x0;
+ self->_mmArgumentsMask = 0x0;
+ self->_xmmArgumentsMask = 0x0;
+
+ if (!self->_argumentsCount)
+ return;
+
+ // --------------------------------------------------------------------------
+ // [X86 Calling Conventions (32-bit)]
+ // --------------------------------------------------------------------------
+
+#if defined(ASMJIT_X86)
+ // Register arguments (Integer), always left-to-right.
+ for (i = 0; i != static_cast<int32_t>(argumentsCount); i++)
+ {
+ FuncArg& arg = self->_arguments[i];
+ uint32_t varType = arg.getVarType();
+
+ if (X86Util::isVarTypeInt(varType) && gpPos < 16 && self->_gpList[gpPos] != kRegIndexInvalid)
+ {
+ arg._regIndex = self->_gpList[gpPos++];
+ self->_gpArgumentsMask |= static_cast<uint16_t>(IntUtil::maskFromIndex(arg.getRegIndex()));
+ }
+ }
+
+ // Stack arguments.
+ int32_t iStart = static_cast<int32_t>(argumentsCount - 1);
+ int32_t iEnd = -1;
+ int32_t iStep = -1;
+
+ if (self->_argumentsDirection == kFuncArgsLTR)
+ {
+ iStart = 0;
+ iEnd = static_cast<int32_t>(argumentsCount);
+ iStep = 1;
+ }
+
+ for (i = iStart; i != iEnd; i += iStep)
+ {
+ FuncArg& arg = self->_arguments[i];
+ uint32_t varType = arg.getVarType();
+
+ if (arg.hasRegIndex())
+ continue;
+
+ if (X86Util::isVarTypeInt(varType))
+ {
+ stackOffset -= 4;
+ arg._stackOffset = static_cast<int16_t>(stackOffset);
+ }
+ else if (X86Util::isVarTypeFloat(varType))
+ {
+ int32_t size = static_cast<int32_t>(x86VarInfo[varType].getSize());
+ stackOffset -= size;
+ arg._stackOffset = static_cast<int16_t>(stackOffset);
+ }
+ }
+#endif // ASMJIT_X86
+
+ // --------------------------------------------------------------------------
+ // [X64 Calling Conventions (64-bit)]
+ // --------------------------------------------------------------------------
+
+#if defined(ASMJIT_X64)
+ // Windows 64-bit specific.
+ if (self->_convention == kX86FuncConvX64W)
+ {
+ int32_t max = argumentsCount < 4 ? argumentsCount : 4;
+
+ // Register arguments (Integer / FP), always left-to-right.
+ for (i = 0; i != max; i++)
+ {
+ FuncArg& arg = self->_arguments[i];
+ uint32_t varType = arg.getVarType();
+
+ if (X86Util::isVarTypeInt(varType))
+ {
+ arg._regIndex = self->_gpList[i];
+ self->_gpArgumentsMask |= static_cast<uint16_t>(IntUtil::maskFromIndex(arg.getRegIndex()));
+ }
+ else if (X86Util::isVarTypeFloat(varType))
+ {
+ arg._regIndex = self->_xmmList[i];
+ self->_xmmArgumentsMask |= static_cast<uint16_t>(IntUtil::maskFromIndex(arg.getRegIndex()));
+ }
+ }
+
+ // Stack arguments (always right-to-left).
+ for (i = argumentsCount - 1; i != -1; i--)
+ {
+ FuncArg& arg = self->_arguments[i];
+ uint32_t varType = arg.getVarType();
+
+ if (arg.isAssigned())
+ continue;
+
+ if (X86Util::isVarTypeInt(varType))
+ {
+ stackOffset -= 8; // Always 8 bytes.
+ arg._stackOffset = stackOffset;
+ }
+ else if (X86Util::isVarTypeFloat(varType))
+ {
+ int32_t size = static_cast<int32_t>(x86VarInfo[varType].getSize());
+ stackOffset -= size;
+ arg._stackOffset = stackOffset;
+ }
+ }
+
+ // 32 bytes shadow space (X64W calling convention specific).
+ stackOffset -= 4 * 8;
+ }
+ // Linux/Unix 64-bit (AMD64 calling convention).
+ else
+ {
+ // Register arguments (Integer), always left-to-right.
+ for (i = 0; i != static_cast<int32_t>(argumentsCount); i++)
+ {
+ FuncArg& arg = self->_arguments[i];
+ uint32_t varType = arg.getVarType();
+
+ if (X86Util::isVarTypeInt(varType) && gpPos < 32 && self->_gpList[gpPos] != kRegIndexInvalid)
+ {
+ arg._regIndex = self->_gpList[gpPos++];
+ self->_gpArgumentsMask |= static_cast<uint16_t>(IntUtil::maskFromIndex(arg.getRegIndex()));
+ }
+ }
+
+ // Register arguments (FP), always left-to-right.
+ for (i = 0; i != static_cast<int32_t>(argumentsCount); i++)
+ {
+ FuncArg& arg = self->_arguments[i];
+ uint32_t varType = arg.getVarType();
+
+ if (X86Util::isVarTypeFloat(varType))
+ {
+ arg._regIndex = self->_xmmList[xmmPos++];
+ self->_xmmArgumentsMask |= static_cast<uint16_t>(IntUtil::maskFromIndex(arg.getRegIndex()));
+ }
+ }
+
+ // Stack arguments.
+ for (i = argumentsCount - 1; i != -1; i--)
+ {
+ FuncArg& arg = self->_arguments[i];
+ uint32_t varType = arg.getVarType();
+
+ if (arg.isAssigned())
+ continue;
+
+ if (X86Util::isVarTypeInt(varType))
+ {
+ stackOffset -= 8;
+ arg._stackOffset = static_cast<int16_t>(stackOffset);
+ }
+ else if (X86Util::isVarTypeFloat(varType))
+ {
+ int32_t size = (int32_t)x86VarInfo[varType].getSize();
+
+ stackOffset -= size;
+ arg._stackOffset = static_cast<int16_t>(stackOffset);
+ }
+ }
+ }
+#endif // ASMJIT_X64
+
+ // Modify stack offset (all function parameters will be in positive stack
+ // offset that is never zero).
+ for (i = 0; i < (int32_t)argumentsCount; i++)
+ {
+ FuncArg& arg = self->_arguments[i];
+ if (!arg.hasRegIndex())
+ {
+ arg._stackOffset += static_cast<uint16_t>(static_cast<int32_t>(sizeof(uintptr_t)) - stackOffset);
+ }
+ }
+
+ self->_argumentsStackSize = (uint32_t)(-stackOffset);
+}
+
+void X86FuncDecl::setPrototype(uint32_t convention, uint32_t returnType, const uint32_t* arguments, uint32_t argumentsCount)
+{
+ // Limit maximum function arguments to kFuncArgsMax.
+ if (argumentsCount > kFuncArgsMax)
+ argumentsCount = kFuncArgsMax;
+
+ X86FuncDecl_initCallingConvention(this, convention);
+ X86FuncDecl_initDefinition(this, returnType, arguments, argumentsCount);
+}
+
+// ============================================================================
+// [AsmJit::X86FuncDecl - Reset]
+// ============================================================================
+
+void X86FuncDecl::reset()
+{
+ uint32_t i;
+
+ // --------------------------------------------------------------------------
+ // [Core]
+ // --------------------------------------------------------------------------
+
+ _returnType = kVarTypeInvalid;
+ _argumentsCount = 0;
+
+ _reserved0[0] = 0;
+ _reserved0[1] = 0;
+
+ for (i = 0; i < ASMJIT_ARRAY_SIZE(_arguments); i++)
+ _arguments[i].reset();
+
+ _argumentsStackSize = 0;
+ _gpArgumentsMask = 0x0;
+ _mmArgumentsMask = 0x0;
+ _xmmArgumentsMask = 0x0;
+
+ // --------------------------------------------------------------------------
+ // [Convention]
+ // --------------------------------------------------------------------------
+
+ _convention = kFuncConvNone;
+ _calleePopsStack = false;
+ _argumentsDirection = kFuncArgsRTL;
+ _reserved1 = 0;
+
+ for (i = 0; i < ASMJIT_ARRAY_SIZE(_gpList); i++)
+ _gpList[i] = kRegIndexInvalid;
+
+ for (i = 0; i < ASMJIT_ARRAY_SIZE(_xmmList); i++)
+ _xmmList[i] = kRegIndexInvalid;
+
+ _gpListMask = 0x0;
+ _mmListMask = 0x0;
+ _xmmListMask = 0x0;
+
+ _gpPreservedMask = 0x0;
+ _mmPreservedMask = 0x0;
+ _xmmPreservedMask = 0x0;
+}
+
+} // AsmJit namespace
+
+// [Api-Begin]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86/x86func.h
@@ -1,1 +1,242 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_X86_X86FUNC_H
+#define _ASMJIT_X86_X86FUNC_H
+
+// [Dependencies - AsmJit]
+#include "../core/defs.h"
+#include "../core/func.h"
+
+#include "../x86/x86defs.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+//! @addtogroup AsmJit_X86
+//! @{
+
+// ============================================================================
+// [AsmJit::TypeId]
+// ============================================================================
+
+ASMJIT_DECLARE_TYPE_CORE(kX86VarTypeIntPtr);
+ASMJIT_DECLARE_TYPE_ID(void, kVarTypeInvalid);
+
+ASMJIT_DECLARE_TYPE_ID(int8_t, kX86VarTypeGpd);
+ASMJIT_DECLARE_TYPE_ID(uint8_t, kX86VarTypeGpd);
+
+ASMJIT_DECLARE_TYPE_ID(int16_t, kX86VarTypeGpd);
+ASMJIT_DECLARE_TYPE_ID(uint16_t, kX86VarTypeGpd);
+
+ASMJIT_DECLARE_TYPE_ID(int32_t, kX86VarTypeGpd);
+ASMJIT_DECLARE_TYPE_ID(uint32_t, kX86VarTypeGpd);
+
+#ifdef ASMJIT_X64
+ASMJIT_DECLARE_TYPE_ID(int64_t, kX86VarTypeGpq);
+ASMJIT_DECLARE_TYPE_ID(uint64_t, kX86VarTypeGpq);
+#endif // ASMJIT_X64
+
+ASMJIT_DECLARE_TYPE_ID(float, kX86VarTypeFloat);
+ASMJIT_DECLARE_TYPE_ID(double, kX86VarTypeDouble);
+
+// ============================================================================
+// [AsmJit::X86FuncDecl]
+// ============================================================================
+
+//! @brief X86 function, including calling convention, arguments and their
+//! register indices or stack positions.
+struct X86FuncDecl : public FuncDecl
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create a new @ref FunctionX86 instance.
+ X86FuncDecl() { this->reset(); }
+
+ // --------------------------------------------------------------------------
+ // [Accessors - Core]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get stack size needed for function arguments passed on the stack.
+ uint32_t getArgumentsStackSize() const { return this->_argumentsStackSize; }
+
+ //! @brief Get bit-mask of GP registers used to pass function arguments.
+ uint32_t getGpArgumentsMask() const { return this->_gpArgumentsMask; }
+
+ //! @brief Get bit-mask of MM registers used to pass function arguments.
+ uint32_t getMmArgumentsMask() const { return this->_mmArgumentsMask; }
+
+ //! @brief Get bit-mask of XMM registers used to pass function arguments.
+ uint32_t getXmmArgumentsMask() const { return this->_xmmArgumentsMask; }
+
+ // --------------------------------------------------------------------------
+ // [Accessors - Convention]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get function calling convention, see @c kX86FuncConv.
+ uint32_t getConvention() const { return this->_convention; }
+
+ //! @brief Get whether the callee pops the stack.
+ uint32_t getCalleePopsStack() const { return this->_calleePopsStack; }
+
+ //! @brief Get direction of arguments passed on the stack.
+ //!
+ //! Direction should be always @c kFuncArgsRTL.
+ //!
+ //! @note This is related to used calling convention, it's not affected by
+ //! number of function arguments or their types.
+ uint32_t getArgumentsDirection() const { return this->_argumentsDirection; }
+
+ //! @brief Get registers used to pass first integer parameters by current
+ //! calling convention.
+ //!
+ //! @note This is related to used calling convention, it's not affected by
+ //! number of function arguments or their types.
+ const uint8_t *getGpList() const { return this->_gpList; }
+
+ //! @brief Get registers used to pass first SP-FP or DP-FPparameters by
+ //! current calling convention.
+ //!
+ //! @note This is related to used calling convention, it's not affected by
+ //! number of function arguments or their types.
+ const uint8_t *getXmmList() const { return this->_xmmList; }
+
+ //! @brief Get bit-mask of GP registers which might be used for arguments.
+ uint32_t getGpListMask() const { return this->_gpListMask; }
+
+ //! @brief Get bit-mask of MM registers which might be used for arguments.
+ uint32_t getMmListMask() const { return this->_mmListMask; }
+
+ //! @brief Get bit-mask of XMM registers which might be used for arguments.
+ uint32_t getXmmListMask() const { return this->_xmmListMask; }
+
+ //! @brief Get bit-mask of general purpose registers that's preserved
+ //! (non-volatile).
+ //!
+ //! @note This is related to used calling convention, it's not affected by
+ //! number of function arguments or their types.
+ uint32_t getGpPreservedMask() const { return this->_gpPreservedMask; }
+
+ //! @brief Get bit-mask of MM registers that's preserved (non-volatile).
+ //!
+ //! @note No standardized calling function is not preserving MM registers.
+ //! This member is here for extension writers who need for some reason custom
+ //! calling convention that can be called through code generated by AsmJit
+ //! (or other runtime code generator).
+ uint32_t getMmPreservedMask() const { return this->_mmPreservedMask; }
+
+ //! @brief Get bit-mask of XMM registers that's preserved (non-volatile).
+ //!
+ //! @note This is related to used calling convention, it's not affected by
+ //! number of function arguments or their types.
+ uint32_t getXmmPreservedMask() const { return this->_xmmPreservedMask; }
+
+ // --------------------------------------------------------------------------
+ // [Methods]
+ // --------------------------------------------------------------------------
+
+ //! @brief Find argument ID by the register code.
+ ASMJIT_API uint32_t findArgumentByRegCode(uint32_t regCode) const;
+
+ // --------------------------------------------------------------------------
+ // [SetPrototype]
+ // --------------------------------------------------------------------------
+
+ //! @brief Set function prototype.
+ //!
+ //! This will set function calling convention and setup arguments variables.
+ //!
+ //! @note This function will allocate variables, it can be called only once.
+ ASMJIT_API void setPrototype(uint32_t convention, uint32_t returnType, const uint32_t *arguments, uint32_t argumentsCount);
+
+ // --------------------------------------------------------------------------
+ // [Reset]
+ // --------------------------------------------------------------------------
+
+ ASMJIT_API void reset();
+
+ // --------------------------------------------------------------------------
+ // [Members - Core]
+ // --------------------------------------------------------------------------
+
+ //! @brief Count of bytes consumed by arguments on the stack.
+ uint16_t _argumentsStackSize;
+ //! @brief Bitmask for GP registers used as passed function arguments.
+ uint16_t _gpArgumentsMask;
+ //! @brief Bitmask for MM registers used as passed function arguments.
+ uint16_t _mmArgumentsMask;
+ //! @brief Bitmask for XMM registers used as passed function arguments.
+ uint16_t _xmmArgumentsMask;
+
+ // --------------------------------------------------------------------------
+ // [Membes - Convention]
+ //
+ // This section doesn't depend on function arguments or return type. It
+ // depends only on function calling convention and it's filled according to
+ // that value.
+ // --------------------------------------------------------------------------
+
+ //! @brief Calling convention.
+ uint8_t _convention;
+ //! @brief Whether a callee pops stack.
+ uint8_t _calleePopsStack;
+ //! @brief Direction for arguments passed on the stack, see @c kFuncArgsDirection.
+ uint8_t _argumentsDirection;
+ //! @brief Reserved for future use #1 (alignment).
+ uint8_t _reserved1;
+
+ //! @brief List of register IDs used for GP arguments (order is important).
+ //!
+ //! @note All registers in _gpList are also specified in @ref _gpListMask.
+ //! Unused fields are filled by @ref kRegIndexInvalid.
+ uint8_t _gpList[16];
+ //! @brief List of register IDs used for XMM arguments (order is important).
+ //!
+ //! @note All registers in _gpList are also specified in @ref _xmmListMask.
+ //! Unused fields are filled by @ref kRegIndexInvalid.
+ uint8_t _xmmList[16];
+
+ //! @brief Bitmask for GP registers which might be used by arguments.
+ //!
+ //! @note All registers in _gpListMask are also specified in @ref _gpList.
+ uint16_t _gpListMask;
+ //! @brief Bitmask for MM registers which might be used by arguments.
+ uint16_t _mmListMask;
+ //! @brief Bitmask for XMM registers which might be used by arguments.
+ //!
+ //! @note All registers in _xmmListMask are also specified in @ref _xmmList.
+ uint16_t _xmmListMask;
+
+ //! @brief Bitmask for GP registers preserved across the function call.
+ //!
+ //! @note Preserved register mask is complement to @ref _gpListMask.
+ uint16_t _gpPreservedMask;
+ //! @brief Bitmask for MM registers preserved across the function call.
+ //!
+ //! @note Preserved register mask is complement to @ref _mmListMask.
+ uint16_t _mmPreservedMask;
+ //! @brief Bitmask for XMM registers preserved across the function call.
+ //!
+ //! @note Preserved register mask is complement to @ref _xmmListMask.
+ uint16_t _xmmPreservedMask;
+};
+
+//! @}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_X86_X86FUNC_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86/x86operand.cpp
@@ -1,1 +1,386 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../x86/x86defs.h"
+#include "../x86/x86operand.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit {
+
+// ============================================================================
+// [AsmJit::Registers - no_reg]
+// ============================================================================
+
+const GpReg no_reg(_Initialize(), kInvalidValue);
+
+// ============================================================================
+// [AsmJit::Registers - 8-bit]
+// ============================================================================
+
+const GpReg al(_Initialize(), kX86RegAl);
+const GpReg cl(_Initialize(), kX86RegCl);
+const GpReg dl(_Initialize(), kX86RegDl);
+const GpReg bl(_Initialize(), kX86RegBl);
+
+#if defined(ASMJIT_X64)
+const GpReg spl(_Initialize(), kX86RegSpl);
+const GpReg bpl(_Initialize(), kX86RegBpl);
+const GpReg sil(_Initialize(), kX86RegSil);
+const GpReg dil(_Initialize(), kX86RegDil);
+
+const GpReg r8b(_Initialize(), kX86RegR8b);
+const GpReg r9b(_Initialize(), kX86RegR9b);
+const GpReg r10b(_Initialize(), kX86RegR10b);
+const GpReg r11b(_Initialize(), kX86RegR11b);
+const GpReg r12b(_Initialize(), kX86RegR12b);
+const GpReg r13b(_Initialize(), kX86RegR13b);
+const GpReg r14b(_Initialize(), kX86RegR14b);
+const GpReg r15b(_Initialize(), kX86RegR15b);
+#endif // ASMJIT_X64
+
+const GpReg ah(_Initialize(), kX86RegAh);
+const GpReg ch(_Initialize(), kX86RegCh);
+const GpReg dh(_Initialize(), kX86RegDh);
+const GpReg bh(_Initialize(), kX86RegBh);
+
+// ============================================================================
+// [AsmJit::Registers - 16-bit]
+// ============================================================================
+
+const GpReg ax(_Initialize(), kX86RegAx);
+const GpReg cx(_Initialize(), kX86RegCx);
+const GpReg dx(_Initialize(), kX86RegDx);
+const GpReg bx(_Initialize(), kX86RegBx);
+const GpReg sp(_Initialize(), kX86RegSp);
+const GpReg bp(_Initialize(), kX86RegBp);
+const GpReg si(_Initialize(), kX86RegSi);
+const GpReg di(_Initialize(), kX86RegDi);
+
+#if defined(ASMJIT_X64)
+const GpReg r8w(_Initialize(), kX86RegR8w);
+const GpReg r9w(_Initialize(), kX86RegR9w);
+const GpReg r10w(_Initialize(), kX86RegR10w);
+const GpReg r11w(_Initialize(), kX86RegR11w);
+const GpReg r12w(_Initialize(), kX86RegR12w);
+const GpReg r13w(_Initialize(), kX86RegR13w);
+const GpReg r14w(_Initialize(), kX86RegR14w);
+const GpReg r15w(_Initialize(), kX86RegR15w);
+#endif // ASMJIT_X64
+
+// ============================================================================
+// [AsmJit::Registers - 32-bit]
+// ============================================================================
+
+const GpReg eax(_Initialize(), kX86RegEax);
+const GpReg ecx(_Initialize(), kX86RegEcx);
+const GpReg edx(_Initialize(), kX86RegEdx);
+const GpReg ebx(_Initialize(), kX86RegEbx);
+const GpReg esp(_Initialize(), kX86RegEsp);
+const GpReg ebp(_Initialize(), kX86RegEbp);
+const GpReg esi(_Initialize(), kX86RegEsi);
+const GpReg edi(_Initialize(), kX86RegEdi);
+
+#if defined(ASMJIT_X64)
+const GpReg r8d(_Initialize(), kX86RegR8d);
+const GpReg r9d(_Initialize(), kX86RegR9d);
+const GpReg r10d(_Initialize(), kX86RegR10d);
+const GpReg r11d(_Initialize(), kX86RegR11d);
+const GpReg r12d(_Initialize(), kX86RegR12d);
+const GpReg r13d(_Initialize(), kX86RegR13d);
+const GpReg r14d(_Initialize(), kX86RegR14d);
+const GpReg r15d(_Initialize(), kX86RegR15d);
+#endif // ASMJIT_X64
+
+// ============================================================================
+// [AsmJit::Registers - 64-bit]
+// ============================================================================
+
+#if defined(ASMJIT_X64)
+const GpReg rax(_Initialize(), kX86RegRax);
+const GpReg rcx(_Initialize(), kX86RegRcx);
+const GpReg rdx(_Initialize(), kX86RegRdx);
+const GpReg rbx(_Initialize(), kX86RegRbx);
+const GpReg rsp(_Initialize(), kX86RegRsp);
+const GpReg rbp(_Initialize(), kX86RegRbp);
+const GpReg rsi(_Initialize(), kX86RegRsi);
+const GpReg rdi(_Initialize(), kX86RegRdi);
+
+const GpReg r8(_Initialize(), kX86RegR8);
+const GpReg r9(_Initialize(), kX86RegR9);
+const GpReg r10(_Initialize(), kX86RegR10);
+const GpReg r11(_Initialize(), kX86RegR11);
+const GpReg r12(_Initialize(), kX86RegR12);
+const GpReg r13(_Initialize(), kX86RegR13);
+const GpReg r14(_Initialize(), kX86RegR14);
+const GpReg r15(_Initialize(), kX86RegR15);
+#endif // ASMJIT_X64
+
+// ============================================================================
+// [AsmJit::Registers - Native (AsmJit extension)]
+// ============================================================================
+
+const GpReg zax(_Initialize(), kX86RegZax);
+const GpReg zcx(_Initialize(), kX86RegZcx);
+const GpReg zdx(_Initialize(), kX86RegZdx);
+const GpReg zbx(_Initialize(), kX86RegZbx);
+const GpReg zsp(_Initialize(), kX86RegZsp);
+const GpReg zbp(_Initialize(), kX86RegZbp);
+const GpReg zsi(_Initialize(), kX86RegZsi);
+const GpReg zdi(_Initialize(), kX86RegZdi);
+
+// ============================================================================
+// [AsmJit::Registers - MM]
+// ============================================================================
+
+const MmReg mm0(_Initialize(), kX86RegMm0);
+const MmReg mm1(_Initialize(), kX86RegMm1);
+const MmReg mm2(_Initialize(), kX86RegMm2);
+const MmReg mm3(_Initialize(), kX86RegMm3);
+const MmReg mm4(_Initialize(), kX86RegMm4);
+const MmReg mm5(_Initialize(), kX86RegMm5);
+const MmReg mm6(_Initialize(), kX86RegMm6);
+const MmReg mm7(_Initialize(), kX86RegMm7);
+
+// ============================================================================
+// [AsmJit::Registers - XMM]
+// ============================================================================
+
+const XmmReg xmm0(_Initialize(), kX86RegXmm0);
+const XmmReg xmm1(_Initialize(), kX86RegXmm1);
+const XmmReg xmm2(_Initialize(), kX86RegXmm2);
+const XmmReg xmm3(_Initialize(), kX86RegXmm3);
+const XmmReg xmm4(_Initialize(), kX86RegXmm4);
+const XmmReg xmm5(_Initialize(), kX86RegXmm5);
+const XmmReg xmm6(_Initialize(), kX86RegXmm6);
+const XmmReg xmm7(_Initialize(), kX86RegXmm7);
+
+#if defined(ASMJIT_X64)
+const XmmReg xmm8(_Initialize(), kX86RegXmm8);
+const XmmReg xmm9(_Initialize(), kX86RegXmm9);
+const XmmReg xmm10(_Initialize(), kX86RegXmm10);
+const XmmReg xmm11(_Initialize(), kX86RegXmm11);
+const XmmReg xmm12(_Initialize(), kX86RegXmm12);
+const XmmReg xmm13(_Initialize(), kX86RegXmm13);
+const XmmReg xmm14(_Initialize(), kX86RegXmm14);
+const XmmReg xmm15(_Initialize(), kX86RegXmm15);
+#endif // ASMJIT_X64
+
+// ============================================================================
+// [AsmJit::Registers - Segment]
+// ============================================================================
+
+const SegmentReg cs(_Initialize(), kX86RegCs);
+const SegmentReg ss(_Initialize(), kX86RegSs);
+const SegmentReg ds(_Initialize(), kX86RegDs);
+const SegmentReg es(_Initialize(), kX86RegEs);
+const SegmentReg fs(_Initialize(), kX86RegFs);
+const SegmentReg gs(_Initialize(), kX86RegGs);
+
+// ============================================================================
+// [AsmJit::Var]
+// ============================================================================
+
+Mem _BaseVarMem(const Var& var, uint32_t size)
+{
+ Mem m; //(_DontInitialize());
+
+ m._mem.op = kOperandMem;
+ m._mem.size = static_cast<uint8_t>(size == kInvalidValue ? var.getSize() : size);
+ m._mem.type = kOperandMemNative;
+ m._mem.segment = kX86SegNone;
+ m._mem.sizePrefix = 0;
+ m._mem.shift = 0;
+
+ m._mem.id = var.getId();
+ m._mem.base = kInvalidValue;
+ m._mem.index = kInvalidValue;
+
+ m._mem.target = nullptr;
+ m._mem.displacement = 0;
+
+ return m;
+}
+
+
+Mem _BaseVarMem(const Var& var, uint32_t size, sysint_t disp)
+{
+ Mem m; //(_DontInitialize());
+
+ m._mem.op = kOperandMem;
+ m._mem.size = static_cast<uint8_t>(size == kInvalidValue ? var.getSize() : size);
+ m._mem.type = kOperandMemNative;
+ m._mem.segment = kX86SegNone;
+ m._mem.sizePrefix = 0;
+ m._mem.shift = 0;
+
+ m._mem.id = var.getId();
+
+ m._mem.base = kInvalidValue;
+ m._mem.index = kInvalidValue;
+
+ m._mem.target = nullptr;
+ m._mem.displacement = disp;
+
+ return m;
+}
+
+Mem _BaseVarMem(const Var& var, uint32_t size, const GpVar& index, uint32_t shift, sysint_t disp)
+{
+ Mem m; //(_DontInitialize());
+
+ m._mem.op = kOperandMem;
+ m._mem.size = static_cast<uint8_t>(size == kInvalidValue ? var.getSize() : size);
+ m._mem.type = kOperandMemNative;
+ m._mem.segment = kX86SegNone;
+ m._mem.sizePrefix = 0;
+ m._mem.shift = shift;
+
+ m._mem.id = var.getId();
+
+ m._mem.base = kInvalidValue;
+ m._mem.index = index.getId();
+
+ m._mem.target = nullptr;
+ m._mem.displacement = disp;
+
+ return m;
+}
+
+// ============================================================================
+// [AsmJit::Mem - ptr[]]
+// ============================================================================
+
+Mem ptr(const Label& label, sysint_t disp, uint32_t size)
+{
+ return Mem(label, disp, size);
+}
+
+Mem ptr(const Label& label, const GpReg& index, uint32_t shift, sysint_t disp, uint32_t size)
+{
+ Mem m(label, disp, size);
+
+ m._mem.index = index.getRegIndex();
+ m._mem.shift = shift;
+
+ return m;
+}
+
+Mem ptr(const Label& label, const GpVar& index, uint32_t shift, sysint_t disp, uint32_t size)
+{
+ Mem m(label, disp, size);
+
+ m._mem.index = index.getId();
+ m._mem.shift = shift;
+
+ return m;
+}
+
+// ============================================================================
+// [AsmJit::Mem - ptr[] - Absolute Addressing]
+// ============================================================================
+
+ASMJIT_API Mem ptr_abs(void* target, sysint_t disp, uint32_t size)
+{
+ Mem m;
+
+ m._mem.size = size;
+ m._mem.type = kOperandMemAbsolute;
+ m._mem.segment = kX86SegNone;
+
+ m._mem.target = target;
+ m._mem.displacement = disp;
+
+ return m;
+}
+
+ASMJIT_API Mem ptr_abs(void* target, const GpReg& index, uint32_t shift, sysint_t disp, uint32_t size)
+{
+ Mem m;// (_DontInitialize());
+
+ m._mem.op = kOperandMem;
+ m._mem.size = size;
+ m._mem.type = kOperandMemAbsolute;
+ m._mem.segment = kX86SegNone;
+
+#if defined(ASMJIT_X86)
+ m._mem.sizePrefix = index.getSize() != 4;
+#else
+ m._mem.sizePrefix = index.getSize() != 8;
+#endif
+
+ m._mem.shift = shift;
+
+ m._mem.id = kInvalidValue;
+ m._mem.base = kInvalidValue;
+ m._mem.index = index.getRegIndex();
+
+ m._mem.target = target;
+ m._mem.displacement = disp;
+
+ return m;
+}
+
+ASMJIT_API Mem ptr_abs(void* target, const GpVar& index, uint32_t shift, sysint_t disp, uint32_t size)
+{
+ Mem m;// (_DontInitialize());
+
+ m._mem.op = kOperandMem;
+ m._mem.size = size;
+ m._mem.type = kOperandMemAbsolute;
+ m._mem.segment = kX86SegNone;
+
+#if defined(ASMJIT_X86)
+ m._mem.sizePrefix = index.getSize() != 4;
+#else
+ m._mem.sizePrefix = index.getSize() != 8;
+#endif
+
+ m._mem.shift = shift;
+
+ m._mem.id = kInvalidValue;
+ m._mem.base = kInvalidValue;
+ m._mem.index = index.getId();
+
+ m._mem.target = target;
+ m._mem.displacement = disp;
+
+ return m;
+}
+
+// ============================================================================
+// [AsmJit::Mem - ptr[base + displacement]]
+// ============================================================================
+
+Mem ptr(const GpReg& base, sysint_t disp, uint32_t size)
+{
+ return Mem(base, disp, size);
+}
+
+Mem ptr(const GpReg& base, const GpReg& index, uint32_t shift, sysint_t disp, uint32_t size)
+{
+ return Mem(base, index, shift, disp, size);
+}
+
+Mem ptr(const GpVar& base, sysint_t disp, uint32_t size)
+{
+ return Mem(base, disp, size);
+}
+
+Mem ptr(const GpVar& base, const GpVar& index, uint32_t shift, sysint_t disp, uint32_t size)
+{
+ return Mem(base, index, shift, disp, size);
+}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86/x86operand.h
@@ -1,1 +1,1781 @@
-
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+
+// [Guard]
+#ifndef _ASMJIT_X86_X86OPERAND_H
+#define _ASMJIT_X86_X86OPERAND_H
+
+// [Dependencies - AsmJit]
+#include "../core/defs.h"
+#include "../core/operand.h"
+
+#include "../x86/x86defs.h"
+
+namespace AsmJit
+{
+
+// ============================================================================
+// [Forward Declarations]
+// ============================================================================
+
+struct GpReg;
+struct GpVar;
+struct Mem;
+struct MmReg;
+struct MmVar;
+struct Var;
+struct X87Reg;
+struct X87Var;
+struct XmmReg;
+struct XmmVar;
+
+struct SegmentReg;
+
+//! @addtogroup AsmJit_X86
+//! @{
+
+// ============================================================================
+// [AsmJit::MmData]
+// ============================================================================
+
+//! @brief Structure used for MMX specific data (64-bit).
+//!
+//! This structure can be used to load / store data from / to MMX register.
+union MmData
+{
+ // --------------------------------------------------------------------------
+ // [Methods]
+ // --------------------------------------------------------------------------
+
+ //! @brief Set all eight signed 8-bit integers.
+ void setSB(int8_t x0, int8_t x1, int8_t x2, int8_t x3, int8_t x4, int8_t x5, int8_t x6, int8_t x7)
+ {
+ this->sb[0] = x0;
+ this->sb[1] = x1;
+ this->sb[2] = x2;
+ this->sb[3] = x3;
+ this->sb[4] = x4;
+ this->sb[5] = x5;
+ this->sb[6] = x6;
+ this->sb[7] = x7;
+ }
+
+ //! @brief Set all eight unsigned 8-bit integers.
+ void setUB(uint8_t x0, uint8_t x1, uint8_t x2, uint8_t x3, uint8_t x4, uint8_t x5, uint8_t x6, uint8_t x7)
+ {
+ this->ub[0] = x0;
+ this->ub[1] = x1;
+ this->ub[2] = x2;
+ this->ub[3] = x3;
+ this->ub[4] = x4;
+ this->ub[5] = x5;
+ this->ub[6] = x6;
+ this->ub[7] = x7;
+ }
+
+ //! @brief Set all four signed 16-bit integers.
+ void setSW(int16_t x0, int16_t x1, int16_t x2, int16_t x3)
+ {
+ this->sw[0] = x0;
+ this->sw[1] = x1;
+ this->sw[2] = x2;
+ this->sw[3] = x3;
+ }
+
+ //! @brief Set all four unsigned 16-bit integers.
+ void setUW(uint16_t x0, uint16_t x1, uint16_t x2, uint16_t x3)
+ {
+ this->uw[0] = x0;
+ this->uw[1] = x1;
+ this->uw[2] = x2;
+ this->uw[3] = x3;
+ }
+
+ //! @brief Set all two signed 32-bit integers.
+ void setSD(int32_t x0, int32_t x1)
+ {
+ this->sd[0] = x0;
+ this->sd[1] = x1;
+ }
+
+ //! @brief Set all two unsigned 32-bit integers.
+ void setUD(uint32_t x0, uint32_t x1)
+ {
+ this->ud[0] = x0;
+ this->ud[1] = x1;
+ }
+
+ //! @brief Set signed 64-bit integer.
+ void setSQ(int64_t x0)
+ {
+ this->sq[0] = x0;
+ }
+
+ //! @brief Set unsigned 64-bit integer.
+ void setUQ(uint64_t x0)
+ {
+ this->uq[0] = x0;
+ }
+
+ //! @brief Set all two SP-FP values.
+ void setSF(float x0, float x1)
+ {
+ this->sf[0] = x0;
+ this->sf[1] = x1;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Array of eight signed 8-bit integers.
+ int8_t sb[8];
+ //! @brief Array of eight unsigned 8-bit integers.
+ uint8_t ub[8];
+ //! @brief Array of four signed 16-bit integers.
+ int16_t sw[4];
+ //! @brief Array of four unsigned 16-bit integers.
+ uint16_t uw[4];
+ //! @brief Array of two signed 32-bit integers.
+ int32_t sd[2];
+ //! @brief Array of two unsigned 32-bit integers.
+ uint32_t ud[2];
+ //! @brief Array of one signed 64-bit integer.
+ int64_t sq[1];
+ //! @brief Array of one unsigned 64-bit integer.
+ uint64_t uq[1];
+
+ //! @brief Array of two SP-FP values.
+ float sf[2];
+};
+
+// ============================================================================
+// [AsmJit::XmmData]
+// ============================================================================
+
+//! @brief Structure used for SSE specific data (128-bit).
+//!
+//! This structure can be used to load / store data from / to SSE register.
+//!
+//! @note Always align SSE data to 16-bytes.
+union XmmData
+{
+ // --------------------------------------------------------------------------
+ // [Methods]
+ // --------------------------------------------------------------------------
+
+ //! @brief Set all sixteen signed 8-bit integers.
+ void setSB(int8_t x0, int8_t x1, int8_t x2, int8_t x3, int8_t x4, int8_t x5, int8_t x6, int8_t x7, int8_t x8, int8_t x9, int8_t x10, int8_t x11, int8_t x12, int8_t x13, int8_t x14, int8_t x15)
+ {
+ this->sb[0] = x0;
+ this->sb[1] = x1;
+ this->sb[2] = x2;
+ this->sb[3] = x3;
+ this->sb[4] = x4;
+ this->sb[5] = x5;
+ this->sb[6] = x6;
+ this->sb[7] = x7;
+ this->sb[8] = x8;
+ this->sb[9] = x9;
+ this->sb[10] = x10;
+ this->sb[11] = x11;
+ this->sb[12] = x12;
+ this->sb[13] = x13;
+ this->sb[14] = x14;
+ this->sb[15] = x15;
+ }
+
+ //! @brief Set all sixteen unsigned 8-bit integers.
+ void setUB(uint8_t x0, uint8_t x1, uint8_t x2, uint8_t x3, uint8_t x4, uint8_t x5, uint8_t x6, uint8_t x7, uint8_t x8, uint8_t x9, uint8_t x10, uint8_t x11, uint8_t x12, uint8_t x13, uint8_t x14, uint8_t x15)
+ {
+ this->ub[0] = x0;
+ this->ub[1] = x1;
+ this->ub[2] = x2;
+ this->ub[3] = x3;
+ this->ub[4] = x4;
+ this->ub[5] = x5;
+ this->ub[6] = x6;
+ this->ub[7] = x7;
+ this->ub[8] = x8;
+ this->ub[9] = x9;
+ this->ub[10] = x10;
+ this->ub[11] = x11;
+ this->ub[12] = x12;
+ this->ub[13] = x13;
+ this->ub[14] = x14;
+ this->ub[15] = x15;
+ }
+
+ //! @brief Set all eight signed 16-bit integers.
+ void setSW(int16_t x0, int16_t x1, int16_t x2, int16_t x3, int16_t x4, int16_t x5, int16_t x6, int16_t x7)
+ {
+ this->sw[0] = x0;
+ this->sw[1] = x1;
+ this->sw[2] = x2;
+ this->sw[3] = x3;
+ this->sw[4] = x4;
+ this->sw[5] = x5;
+ this->sw[6] = x6;
+ this->sw[7] = x7;
+ }
+
+ //! @brief Set all eight unsigned 16-bit integers.
+ void setUW(uint16_t x0, uint16_t x1, uint16_t x2, uint16_t x3, uint16_t x4, uint16_t x5, uint16_t x6, uint16_t x7)
+ {
+ this->uw[0] = x0;
+ this->uw[1] = x1;
+ this->uw[2] = x2;
+ this->uw[3] = x3;
+ this->uw[4] = x4;
+ this->uw[5] = x5;
+ this->uw[6] = x6;
+ this->uw[7] = x7;
+ }
+
+ //! @brief Set all four signed 32-bit integers.
+ void setSD(int32_t x0, int32_t x1, int32_t x2, int32_t x3)
+ {
+ this->sd[0] = x0;
+ this->sd[1] = x1;
+ this->sd[2] = x2;
+ this->sd[3] = x3;
+ }
+
+ //! @brief Set all four unsigned 32-bit integers.
+ void setUD(uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3)
+ {
+ this->ud[0] = x0;
+ this->ud[1] = x1;
+ this->ud[2] = x2;
+ ud[3] = x3;
+ }
+
+ //! @brief Set all two signed 64-bit integers.
+ void setSQ(int64_t x0, int64_t x1)
+ {
+ this->sq[0] = x0;
+ this->sq[1] = x1;
+ }
+
+ //! @brief Set all two unsigned 64-bit integers.
+ void setUQ(uint64_t x0, uint64_t x1)
+ {
+ this->uq[0] = x0;
+ this->uq[1] = x1;
+ }
+
+ //! @brief Set all four SP-FP floats.
+ void setSF(float x0, float x1, float x2, float x3)
+ {
+ this->sf[0] = x0;
+ this->sf[1] = x1;
+ this->sf[2] = x2;
+ this->sf[3] = x3;
+ }
+
+ //! @brief Set all two DP-FP floats.
+ void setDF(double x0, double x1)
+ {
+ this->df[0] = x0;
+ this->df[1] = x1;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Members]
+ // --------------------------------------------------------------------------
+
+ //! @brief Array of sixteen signed 8-bit integers.
+ int8_t sb[16];
+ //! @brief Array of sixteen unsigned 8-bit integers.
+ uint8_t ub[16];
+ //! @brief Array of eight signed 16-bit integers.
+ int16_t sw[8];
+ //! @brief Array of eight unsigned 16-bit integers.
+ uint16_t uw[8];
+ //! @brief Array of four signed 32-bit integers.
+ int32_t sd[4];
+ //! @brief Array of four unsigned 32-bit integers.
+ uint32_t ud[4];
+ //! @brief Array of two signed 64-bit integers.
+ int64_t sq[2];
+ //! @brief Array of two unsigned 64-bit integers.
+ uint64_t uq[2];
+
+ //! @brief Array of four 32-bit single precision floating points.
+ float sf[4];
+ //! @brief Array of two 64-bit double precision floating points.
+ double df[2];
+};
+
+// ============================================================================
+// [AsmJit::GpReg]
+// ============================================================================
+
+//! @brief General purpose register.
+//!
+//! This class is for all general purpose registers (64, 32, 16 and 8-bit).
+struct GpReg : public Reg
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create non-initialized general purpose register.
+ GpReg() : Reg(kInvalidValue, 0) { }
+ //! @brief Create a reference to @a other general purpose register.
+ GpReg(const GpReg &other) : Reg(other) { }
+
+#ifndef ASMJIT_NODOC
+ GpReg(const _DontInitialize &dontInitialize) : Reg(dontInitialize) { }
+ GpReg(const _Initialize &, uint32_t code) : Reg(code, static_cast<uint32_t>(1U << ((code & kRegTypeMask) >> 12))) { }
+#endif // ASMJIT_NODOC
+
+ // --------------------------------------------------------------------------
+ // [Reg Specific]
+ // --------------------------------------------------------------------------
+
+ //! @brief Set register code to @a code.
+ GpReg &setCode(uint32_t code)
+ {
+ this->_reg.code = code;
+ return *this;
+ }
+
+ //! @brief Set register size to @a size.
+ GpReg &setSize(uint32_t size)
+ {
+ this->_reg.size = static_cast<uint8_t>(size);
+ return *this;
+ }
+
+ // --------------------------------------------------------------------------
+ // [GpReg Specific]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get whether the general purpose register is BYTE (8-bit) type.
+ bool isGpb() const { return (this->_reg.code & kRegTypeMask) <= kX86RegTypeGpbHi; }
+ //! @brief Get whether the general purpose register is LO-BYTE (8-bit) type.
+ bool isGpbLo() const { return (this->_reg.code & kRegTypeMask) == kX86RegTypeGpbLo; }
+ //! @brief Get whether the general purpose register is HI-BYTE (8-bit) type.
+ bool isGpbHi() const { return (this->_reg.code & kRegTypeMask) == kX86RegTypeGpbHi; }
+
+ //! @brief Get whether the general purpose register is WORD (16-bit) type.
+ bool isGpw() const { return (this->_reg.code & kRegTypeMask) == kX86RegTypeGpw; }
+ //! @brief Get whether the general purpose register is DWORD (32-bit) type.
+ //!
+ //! This is default type for 32-bit platforms.
+ bool isGpd() const { return (this->_reg.code & kRegTypeMask) == kX86RegTypeGpd; }
+ //! @brief Get whether the general purpose register is QWORD (64-bit) type.
+ //!
+ //! This is default type for 64-bit platforms.
+ bool isGpq() const { return (this->_reg.code & kRegTypeMask) == kX86RegTypeGpq; }
+
+ // --------------------------------------------------------------------------
+ // [Operator Overload]
+ // --------------------------------------------------------------------------
+
+#ifndef ASMJIT_NODOC
+ GpReg &operator=(const GpReg &other) { this->_copy(other); return *this; }
+ bool operator==(const GpReg &other) const { return this->getRegCode() == other.getRegCode(); }
+ bool operator!=(const GpReg &other) const { return this->getRegCode() != other.getRegCode(); }
+#endif // ASMJIT_NODOC
+};
+
+// ============================================================================
+// [AsmJit::X87Reg]
+// ============================================================================
+
+//! @brief 80-bit x87 floating point register.
+//!
+//! To create instance of x87 register, use @c st() function.
+struct X87Reg : public Reg
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create non-initialized x87 register.
+ X87Reg() : Reg(kInvalidValue, 10) { }
+ //! @brief Create a reference to @a other x87 register.
+ X87Reg(const X87Reg &other) : Reg(other) { }
+
+#ifndef ASMJIT_NODOC
+ X87Reg(const _DontInitialize &dontInitialize) : Reg(dontInitialize) { }
+ X87Reg(const _Initialize &, uint32_t code) : Reg(code | kX86RegTypeX87, 10) { }
+#endif // ASMJIT_NODOC
+
+ // --------------------------------------------------------------------------
+ // [Reg Specific]
+ // --------------------------------------------------------------------------
+
+ //! @brief Set register code to @a code.
+ X87Reg &setCode(uint32_t code)
+ {
+ this->_reg.code = code;
+ return *this;
+ }
+
+ //! @brief Set register size to @a size.
+ X87Reg &setSize(uint32_t size)
+ {
+ this->_reg.size = static_cast<uint8_t>(size);
+ return *this;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Operator Overload]
+ // --------------------------------------------------------------------------
+
+#ifndef ASMJIT_NODOC
+ X87Reg &operator=(const X87Reg &other) { this->_copy(other); return *this; }
+ bool operator==(const X87Reg &other) const { return this->getRegCode() == other.getRegCode(); }
+ bool operator!=(const X87Reg &other) const { return this->getRegCode() != other.getRegCode(); }
+#endif // ASMJIT_NODOC
+};
+
+// ============================================================================
+// [AsmJit::MmReg]
+// ============================================================================
+
+//! @brief 64-bit MMX register.
+struct MmReg : public Reg
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create non-initialized MM register.
+ MmReg() : Reg(kInvalidValue, 8) { }
+ //! @brief Create a reference to @a other MM register.
+ MmReg(const MmReg &other) : Reg(other) { }
+
+#ifndef ASMJIT_NODOC
+ MmReg(const _DontInitialize &dontInitialize) : Reg(dontInitialize) { }
+ MmReg(const _Initialize &, uint32_t code) : Reg(code, 8) { }
+#endif // ASMJIT_NODOC
+
+ // --------------------------------------------------------------------------
+ // [Reg Specific]
+ // --------------------------------------------------------------------------
+
+ //! @brief Set register code to @a code.
+ MmReg &setCode(uint32_t code)
+ {
+ this->_reg.code = code;
+ return *this;
+ }
+
+ //! @brief Set register size to @a size.
+ MmReg &setSize(uint32_t size)
+ {
+ this->_reg.size = static_cast<uint8_t>(size);
+ return *this;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Operator Overload]
+ // --------------------------------------------------------------------------
+
+#ifndef ASMJIT_NODOC
+ MmReg &operator=(const MmReg &other) { this->_copy(other); return *this; }
+ bool operator==(const MmReg &other) const { return this->getRegCode() == other.getRegCode(); }
+ bool operator!=(const MmReg &other) const { return this->getRegCode() != other.getRegCode(); }
+#endif // ASMJIT_NODOC
+};
+
+// ============================================================================
+// [AsmJit::XmmReg]
+// ============================================================================
+
+//! @brief 128-bit SSE register.
+struct XmmReg : public Reg
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create non-initialized XMM register.
+ XmmReg() : Reg(kInvalidValue, 16) { }
+ //! @brief Create a reference to @a other XMM register.
+ XmmReg(const _Initialize &, uint32_t code) : Reg(code, 16) { }
+
+#ifndef ASMJIT_NODOC
+ XmmReg(const _DontInitialize &dontInitialize) : Reg(dontInitialize) { }
+ XmmReg(const XmmReg &other) : Reg(other) { }
+#endif // ASMJIT_NODOC
+
+ // --------------------------------------------------------------------------
+ // [Reg Specific]
+ // --------------------------------------------------------------------------
+
+ //! @brief Set register code to @a code.
+ XmmReg &setCode(uint32_t code)
+ {
+ this->_reg.code = code;
+ return *this;
+ }
+
+ //! @brief Set register size to @a size.
+ XmmReg &setSize(uint32_t size)
+ {
+ this->_reg.size = static_cast<uint8_t>(size);
+ return *this;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Operator Overload]
+ // --------------------------------------------------------------------------
+
+#ifndef ASMJIT_NODOC
+ XmmReg &operator=(const XmmReg &other) { this->_copy(other); return *this; }
+ bool operator==(const XmmReg &other) const { return this->getRegCode() == other.getRegCode(); }
+ bool operator!=(const XmmReg &other) const { return this->getRegCode() != other.getRegCode(); }
+#endif // ASMJIT_NODOC
+};
+
+// ============================================================================
+// [AsmJit::SegmentReg]
+// ============================================================================
+
+//! @brief Segment register.
+struct SegmentReg : public Reg
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create non-initialized segment register.
+ SegmentReg() : Reg(kInvalidValue, 2) { }
+ //! @brief Create a reference to @a other segment register.
+ SegmentReg(const _Initialize &, uint32_t code) : Reg(code, 2) { }
+
+#ifndef ASMJIT_NODOC
+ SegmentReg(const _DontInitialize &dontInitialize) : Reg(dontInitialize) { }
+ SegmentReg(const SegmentReg &other) : Reg(other) { }
+#endif // ASMJIT_NODOC
+
+ // --------------------------------------------------------------------------
+ // [Reg Specific]
+ // --------------------------------------------------------------------------
+
+ //! @brief Set register code to @a code.
+ SegmentReg &setCode(uint32_t code)
+ {
+ this->_reg.code = code;
+ return *this;
+ }
+
+ //! @brief Set register size to @a size.
+ SegmentReg &setSize(uint32_t size)
+ {
+ this->_reg.size = static_cast<uint8_t>(size);
+ return *this;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Operator Overload]
+ // --------------------------------------------------------------------------
+
+#ifndef ASMJIT_NODOC
+ SegmentReg &operator=(const SegmentReg &other) { this->_copy(other); return *this; }
+ bool operator==(const SegmentReg &other) const { return this->getRegCode() == other.getRegCode(); }
+ bool operator!=(const SegmentReg &other) const { return this->getRegCode() != other.getRegCode(); }
+#endif // ASMJIT_NODOC
+};
+
+// ============================================================================
+// [AsmJit::Registers - no_reg]
+// ============================================================================
+
+//! @brief No register, can be used only in @c Mem operand.
+ASMJIT_VAR const GpReg no_reg;
+
+// ============================================================================
+// [AsmJit::Registers - 8-bit]
+// ============================================================================
+
+//! @brief 8-bit General purpose register.
+ASMJIT_VAR const GpReg al;
+//! @brief 8-bit General purpose register.
+ASMJIT_VAR const GpReg cl;
+//! @brief 8-bit General purpose register.
+ASMJIT_VAR const GpReg dl;
+//! @brief 8-bit General purpose register.
+ASMJIT_VAR const GpReg bl;
+
+#ifdef ASMJIT_X64
+//! @brief 8-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg spl;
+//! @brief 8-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg bpl;
+//! @brief 8-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg sil;
+//! @brief 8-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg dil;
+
+//! @brief 8-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r8b;
+//! @brief 8-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r9b;
+//! @brief 8-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r10b;
+//! @brief 8-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r11b;
+//! @brief 8-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r12b;
+//! @brief 8-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r13b;
+//! @brief 8-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r14b;
+//! @brief 8-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r15b;
+#endif // ASMJIT_X64
+
+//! @brief 8-bit General purpose register.
+ASMJIT_VAR const GpReg ah;
+//! @brief 8-bit General purpose register.
+ASMJIT_VAR const GpReg ch;
+//! @brief 8-bit General purpose register.
+ASMJIT_VAR const GpReg dh;
+//! @brief 8-bit General purpose register.
+ASMJIT_VAR const GpReg bh;
+
+// ============================================================================
+// [AsmJit::Registers - 16-bit]
+// ============================================================================
+
+//! @brief 16-bit General purpose register.
+ASMJIT_VAR const GpReg ax;
+//! @brief 16-bit General purpose register.
+ASMJIT_VAR const GpReg cx;
+//! @brief 16-bit General purpose register.
+ASMJIT_VAR const GpReg dx;
+//! @brief 16-bit General purpose register.
+ASMJIT_VAR const GpReg bx;
+//! @brief 16-bit General purpose register.
+ASMJIT_VAR const GpReg sp;
+//! @brief 16-bit General purpose register.
+ASMJIT_VAR const GpReg bp;
+//! @brief 16-bit General purpose register.
+ASMJIT_VAR const GpReg si;
+//! @brief 16-bit General purpose register.
+ASMJIT_VAR const GpReg di;
+
+#ifdef ASMJIT_X64
+//! @brief 16-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r8w;
+//! @brief 16-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r9w;
+//! @brief 16-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r10w;
+//! @brief 16-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r11w;
+//! @brief 16-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r12w;
+//! @brief 16-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r13w;
+//! @brief 16-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r14w;
+//! @brief 16-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r15w;
+#endif // ASMJIT_X64
+
+// ============================================================================
+// [AsmJit::Registers - 32-bit]
+// ============================================================================
+
+//! @brief 32-bit General purpose register.
+ASMJIT_VAR const GpReg eax;
+//! @brief 32-bit General purpose register.
+ASMJIT_VAR const GpReg ecx;
+//! @brief 32-bit General purpose register.
+ASMJIT_VAR const GpReg edx;
+//! @brief 32-bit General purpose register.
+ASMJIT_VAR const GpReg ebx;
+//! @brief 32-bit General purpose register.
+ASMJIT_VAR const GpReg esp;
+//! @brief 32-bit General purpose register.
+ASMJIT_VAR const GpReg ebp;
+//! @brief 32-bit General purpose register.
+ASMJIT_VAR const GpReg esi;
+//! @brief 32-bit General purpose register.
+ASMJIT_VAR const GpReg edi;
+
+#ifdef ASMJIT_X64
+//! @brief 32-bit General purpose register.
+ASMJIT_VAR const GpReg r8d;
+//! @brief 32-bit General purpose register.
+ASMJIT_VAR const GpReg r9d;
+//! @brief 32-bit General purpose register.
+ASMJIT_VAR const GpReg r10d;
+//! @brief 32-bit General purpose register.
+ASMJIT_VAR const GpReg r11d;
+//! @brief 32-bit General purpose register.
+ASMJIT_VAR const GpReg r12d;
+//! @brief 32-bit General purpose register.
+ASMJIT_VAR const GpReg r13d;
+//! @brief 32-bit General purpose register.
+ASMJIT_VAR const GpReg r14d;
+//! @brief 32-bit General purpose register.
+ASMJIT_VAR const GpReg r15d;
+#endif // ASMJIT_X64
+
+// ============================================================================
+// [AsmJit::Registers - 64-bit]
+// ============================================================================
+
+#ifdef ASMJIT_X64
+//! @brief 64-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg rax;
+//! @brief 64-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg rcx;
+//! @brief 64-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg rdx;
+//! @brief 64-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg rbx;
+//! @brief 64-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg rsp;
+//! @brief 64-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg rbp;
+//! @brief 64-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg rsi;
+//! @brief 64-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg rdi;
+
+//! @brief 64-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r8;
+//! @brief 64-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r9;
+//! @brief 64-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r10;
+//! @brief 64-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r11;
+//! @brief 64-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r12;
+//! @brief 64-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r13;
+//! @brief 64-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r14;
+//! @brief 64-bit General purpose register (64-bit mode only).
+ASMJIT_VAR const GpReg r15;
+#endif // ASMJIT_X64
+
+// ============================================================================
+// [AsmJit::Registers - Native (AsmJit extension)]
+// ============================================================================
+
+//! @brief 32-bit or 64-bit General purpose register.
+ASMJIT_VAR const GpReg zax;
+//! @brief 32-bit or 64-bit General purpose register.
+ASMJIT_VAR const GpReg zcx;
+//! @brief 32-bit or 64-bit General purpose register.
+ASMJIT_VAR const GpReg zdx;
+//! @brief 32-bit or 64-bit General purpose register.
+ASMJIT_VAR const GpReg zbx;
+//! @brief 32-bit or 64-bit General purpose register.
+ASMJIT_VAR const GpReg zsp;
+//! @brief 32-bit or 64-bit General purpose register.
+ASMJIT_VAR const GpReg zbp;
+//! @brief 32-bit or 64-bit General purpose register.
+ASMJIT_VAR const GpReg zsi;
+//! @brief 32-bit or 64-bit General purpose register.
+ASMJIT_VAR const GpReg zdi;
+
+// ============================================================================
+// [AsmJit::Registers - MM]
+// ============================================================================
+
+//! @brief 64-bit MM register.
+ASMJIT_VAR const MmReg mm0;
+//! @brief 64-bit MM register.
+ASMJIT_VAR const MmReg mm1;
+//! @brief 64-bit MM register.
+ASMJIT_VAR const MmReg mm2;
+//! @brief 64-bit MM register.
+ASMJIT_VAR const MmReg mm3;
+//! @brief 64-bit MM register.
+ASMJIT_VAR const MmReg mm4;
+//! @brief 64-bit MM register.
+ASMJIT_VAR const MmReg mm5;
+//! @brief 64-bit MM register.
+ASMJIT_VAR const MmReg mm6;
+//! @brief 64-bit MM register.
+ASMJIT_VAR const MmReg mm7;
+
+// ============================================================================
+// [AsmJit::Registers - XMM]
+// ============================================================================
+
+//! @brief 128-bit XMM register.
+ASMJIT_VAR const XmmReg xmm0;
+//! @brief 128-bit XMM register.
+ASMJIT_VAR const XmmReg xmm1;
+//! @brief 128-bit XMM register.
+ASMJIT_VAR const XmmReg xmm2;
+//! @brief 128-bit XMM register.
+ASMJIT_VAR const XmmReg xmm3;
+//! @brief 128-bit XMM register.
+ASMJIT_VAR const XmmReg xmm4;
+//! @brief 128-bit XMM register.
+ASMJIT_VAR const XmmReg xmm5;
+//! @brief 128-bit XMM register.
+ASMJIT_VAR const XmmReg xmm6;
+//! @brief 128-bit XMM register.
+ASMJIT_VAR const XmmReg xmm7;
+
+#ifdef ASMJIT_X64
+//! @brief 128-bit XMM register (64-bit mode only).
+ASMJIT_VAR const XmmReg xmm8;
+//! @brief 128-bit XMM register (64-bit mode only).
+ASMJIT_VAR const XmmReg xmm9;
+//! @brief 128-bit XMM register (64-bit mode only).
+ASMJIT_VAR const XmmReg xmm10;
+//! @brief 128-bit XMM register (64-bit mode only).
+ASMJIT_VAR const XmmReg xmm11;
+//! @brief 128-bit XMM register (64-bit mode only).
+ASMJIT_VAR const XmmReg xmm12;
+//! @brief 128-bit XMM register (64-bit mode only).
+ASMJIT_VAR const XmmReg xmm13;
+//! @brief 128-bit XMM register (64-bit mode only).
+ASMJIT_VAR const XmmReg xmm14;
+//! @brief 128-bit XMM register (64-bit mode only).
+ASMJIT_VAR const XmmReg xmm15;
+#endif // ASMJIT_X64
+
+// ============================================================================
+// [AsmJit::Registers - Segment]
+// ============================================================================
+
+//! @brief CS segment register.
+ASMJIT_VAR const SegmentReg cs;
+//! @brief SS segment register.
+ASMJIT_VAR const SegmentReg ss;
+//! @brief DS segment register.
+ASMJIT_VAR const SegmentReg ds;
+//! @brief ES segment register.
+ASMJIT_VAR const SegmentReg es;
+//! @brief FS segment register.
+ASMJIT_VAR const SegmentReg fs;
+//! @brief GS segment register.
+ASMJIT_VAR const SegmentReg gs;
+
+// ============================================================================
+// [AsmJit::Registers - Register From Index]
+// ============================================================================
+
+//! @brief Get general purpose register of byte size.
+inline GpReg gpb_lo(uint32_t index) { return GpReg(_Initialize(), index | kX86RegTypeGpbLo); }
+
+//! @brief Get general purpose register of byte size.
+inline GpReg gpb_hi(uint32_t index) { return GpReg(_Initialize(), index | kX86RegTypeGpbHi); }
+
+//! @brief Get general purpose register of word size.
+inline GpReg gpw(uint32_t index) { return GpReg(_Initialize(), index | kX86RegTypeGpw); }
+
+//! @brief Get general purpose register of dword size.
+inline GpReg gpd(uint32_t index) { return GpReg(_Initialize(), index | kX86RegTypeGpd); }
+
+#ifdef ASMJIT_X64
+//! @brief Get general purpose register of qword size (64-bit only).
+inline GpReg gpq(uint32_t index) { return GpReg(_Initialize(), index | kX86RegTypeGpq); }
+#endif
+
+//! @brief Get general purpose dword/qword register (depending to architecture).
+inline GpReg gpz(uint32_t index) { return GpReg(_Initialize(), index | kX86RegTypeGpz); }
+
+//! @brief Get MMX (MM) register .
+inline MmReg mm(uint32_t index) { return MmReg(_Initialize(), index | kX86RegTypeMm); }
+
+//! @brief Get SSE (XMM) register.
+inline XmmReg xmm(uint32_t index) { return XmmReg(_Initialize(), index | kX86RegTypeXmm); }
+
+//! @brief Get x87 register with index @a i.
+inline X87Reg st(uint32_t i)
+{
+ ASMJIT_ASSERT(i < 8);
+ return X87Reg(_Initialize(), i);
+}
+
+// ============================================================================
+// [AsmJit::Mem]
+// ============================================================================
+
+//! @brief Memory operand.
+struct Mem : public Operand
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ Mem() : Operand(_DontInitialize())
+ {
+ this->_mem.op = kOperandMem;
+ this->_mem.size = 0;
+ this->_mem.type = kOperandMemNative;
+ this->_mem.segment = kX86SegNone;
+ this->_mem.sizePrefix = 0;
+ this->_mem.shift = 0;
+
+ this->_mem.id = kInvalidValue;
+ this->_mem.base = kInvalidValue;
+ this->_mem.index = kInvalidValue;
+
+ this->_mem.target = nullptr;
+ this->_mem.displacement = 0;
+ }
+
+ Mem(const Label &label, sysint_t displacement, uint32_t size = 0) : Operand(_DontInitialize())
+ {
+ this->_mem.op = kOperandMem;
+ this->_mem.size = static_cast<uint8_t>(size);
+ this->_mem.type = kOperandMemLabel;
+ this->_mem.segment = kX86SegNone;
+ this->_mem.sizePrefix = 0;
+ this->_mem.shift = 0;
+
+ this->_mem.id = kInvalidValue;
+ this->_mem.base = reinterpret_cast<const Operand &>(label)._base.id;
+ _mem.index = kInvalidValue;
+
+ _mem.target = nullptr;
+ _mem.displacement = displacement;
+ }
+
+ Mem(const GpReg &base, sysint_t displacement, uint32_t size = 0) : Operand(_DontInitialize())
+ {
+ this->_mem.op = kOperandMem;
+ this->_mem.size = static_cast<uint8_t>(size);
+ this->_mem.type = kOperandMemNative;
+ this->_mem.segment = kX86SegNone;
+
+#ifdef ASMJIT_X86
+ this->_mem.sizePrefix = base.getSize() != 4;
+#else
+ this->_mem.sizePrefix = base.getSize() != 8;
+#endif
+
+ this->_mem.shift = 0;
+
+ this->_mem.id = kInvalidValue;
+ this->_mem.base = base.getRegCode() & kRegIndexMask;
+ this->_mem.index = kInvalidValue;
+
+ this->_mem.target = nullptr;
+ this->_mem.displacement = displacement;
+ }
+
+ Mem(const GpVar &base, sysint_t displacement, uint32_t size = 0) : Operand(_DontInitialize())
+ {
+ this->_mem.op = kOperandMem;
+ this->_mem.size = static_cast<uint8_t>(size);
+ this->_mem.type = kOperandMemNative;
+ this->_mem.segment = kX86SegNone;
+
+#ifdef ASMJIT_X86
+ this->_mem.sizePrefix = (reinterpret_cast<const Operand &>(base)._var.size) != 4;
+#else
+ this->_mem.sizePrefix = (reinterpret_cast<const Operand &>(base)._var.size) != 8;
+#endif
+
+ this->_mem.shift = 0;
+
+ this->_mem.id = kInvalidValue;
+ this->_mem.base = reinterpret_cast<const Operand &>(base).getId();
+ this->_mem.index = kInvalidValue;
+
+ this->_mem.target = nullptr;
+ this->_mem.displacement = displacement;
+ }
+
+ Mem(const GpReg &base, const GpReg &index, uint32_t shift, sysint_t displacement, uint32_t size = 0) : Operand(_DontInitialize())
+ {
+ ASMJIT_ASSERT(shift <= 3);
+
+ this->_mem.op = kOperandMem;
+ this->_mem.size = static_cast<uint8_t>(size);
+ this->_mem.type = kOperandMemNative;
+ this->_mem.segment = kX86SegNone;
+
+#ifdef ASMJIT_X86
+ this->_mem.sizePrefix = (base.getSize() | index.getSize()) != 4;
+#else
+ this->_mem.sizePrefix = (base.getSize() | index.getSize()) != 8;
+#endif
+
+ this->_mem.shift = static_cast<uint8_t>(shift);
+
+ this->_mem.id = kInvalidValue;
+ this->_mem.base = base.getRegIndex();
+ this->_mem.index = index.getRegIndex();
+
+ this->_mem.target = nullptr;
+ this->_mem.displacement = displacement;
+ }
+
+ Mem(const GpVar &base, const GpVar &index, uint32_t shift, sysint_t displacement, uint32_t size = 0) : Operand(_DontInitialize())
+ {
+ ASMJIT_ASSERT(shift <= 3);
+
+ this->_mem.op = kOperandMem;
+ this->_mem.size = static_cast<uint8_t>(size);
+ this->_mem.type = kOperandMemNative;
+ this->_mem.segment = kX86SegNone;
+
+#ifdef ASMJIT_X86
+ this->_mem.sizePrefix = (reinterpret_cast<const Operand &>(base)._var.size | reinterpret_cast<const Operand &>(index)._var.size) != 4;
+#else
+ this->_mem.sizePrefix = (reinterpret_cast<const Operand &>(base)._var.size | reinterpret_cast<const Operand &>(index)._var.size) != 8;
+#endif
+
+ this->_mem.shift = static_cast<uint8_t>(shift);
+
+ this->_mem.id = kInvalidValue;
+ this->_mem.base = reinterpret_cast<const Operand &>(base).getId();
+ this->_mem.index = reinterpret_cast<const Operand &>(index).getId();
+
+ this->_mem.target = nullptr;
+ this->_mem.displacement = displacement;
+ }
+
+ Mem(const Mem &other) : Operand(other) { }
+
+ Mem(const _DontInitialize &dontInitialize) : Operand(dontInitialize) { }
+
+ // --------------------------------------------------------------------------
+ // [Mem Specific]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get type of memory operand, see @c kOperandMemType.
+ uint32_t getMemType() const { return this->_mem.type; }
+
+ //! @brief Get memory operand segment, see @c kX86Seg.
+ uint32_t getSegment() const { return this->_mem.segment; }
+
+ //! @brief Set memory operand segment, see @c kX86Seg.
+ Mem &setSegment(uint32_t seg)
+ {
+ this->_mem.segment = static_cast<uint8_t>(seg);
+ return *this;
+ }
+
+ //! @brief Set memory operand segment, see @c kX86Seg.
+ Mem &setSegment(const SegmentReg &seg)
+ {
+ this->_mem.segment = static_cast<uint8_t>(seg.getRegIndex());
+ return *this;
+ }
+
+ //! @brief Get whether the memory operand has segment override prefix.
+ bool hasSegment() const { return this->_mem.segment >= kX86SegCount; }
+
+ //! @brief Get whether the memory operand has base register.
+ bool hasBase() const { return this->_mem.base != kInvalidValue; }
+
+ //! @brief Get whether the memory operand has index.
+ bool hasIndex() const { return this->_mem.index != kInvalidValue; }
+
+ //! @brief Get whether the memory operand has shift used.
+ bool hasShift() const { return !!this->_mem.shift; }
+
+ //! @brief Get memory operand base register or @c kInvalidValue.
+ uint32_t getBase() const { return this->_mem.base; }
+
+ //! @brief Get memory operand index register or @c kInvalidValue.
+ uint32_t getIndex() const { return this->_mem.index; }
+
+ //! @brief Get memory operand index scale (0, 1, 2 or 3).
+ uint32_t getShift() const { return this->_mem.shift; }
+
+ //! @brief Get whether to use size-override prefix.
+ //!
+ //! @note This is useful only for MOV and LEA type of instructions.
+ bool getSizePrefix() const { return !!this->_mem.sizePrefix; }
+
+ //! @brief Set whether to use size-override prefix.
+ Mem &setSizePrefix(bool b)
+ {
+ this->_mem.sizePrefix = b;
+ return *this;
+ }
+
+ //! @brief Get absolute target address.
+ //!
+ //! @note You should always check if operand contains address by @c getMemType().
+ void *getTarget() const { return this->_mem.target; }
+
+ //! @brief Set absolute target address.
+ Mem &setTarget(void *target)
+ {
+ this->_mem.target = target;
+ return *this;
+ }
+
+ //! @brief Set memory operand size.
+ Mem &setSize(uint32_t size)
+ {
+ this->_mem.size = size;
+ return *this;
+ }
+
+ //! @brief Get memory operand relative displacement.
+ sysint_t getDisplacement() const { return this->_mem.displacement; }
+
+ //! @brief Set memory operand relative displacement.
+ Mem &setDisplacement(sysint_t displacement)
+ {
+ this->_mem.displacement = displacement;
+ return *this;
+ }
+
+ //! @brief Adjust memory operand relative displacement by @a displacement.
+ Mem &adjust(sysint_t displacement)
+ {
+ this->_mem.displacement += displacement;
+ return *this;
+ }
+
+ //! @brief Get new memory operand adjusted by @a displacement.
+ Mem adjusted(sysint_t displacement) const
+ {
+ Mem result(*this);
+ result.adjust(displacement);
+ return result;
+ }
+
+ // --------------------------------------------------------------------------
+ // [Operator Overload]
+ // --------------------------------------------------------------------------
+
+#ifndef ASMJIT_NODOC
+ Mem &operator=(const Mem &other) { this->_copy(other); return *this; }
+
+ bool operator==(const Mem &other) const
+ {
+ return this->_bin.u32[0] == other._bin.u32[0] && this->_bin.u32[1] == other._bin.u32[1] && this->_bin.u32[2] == other._bin.u32[2] && this->_bin.u32[3] == other._bin.u32[3] &&
+ this->_bin.uptr[0] == other._bin.uptr[0] && this->_bin.uptr[1] == other._bin.uptr[1];
+ }
+
+ bool operator!=(const Mem &other) const
+ {
+ return !(*this == other);
+ }
+#endif // ASMJIT_NODOC
+};
+
+// ============================================================================
+// [AsmJit::Var]
+// ============================================================================
+
+ASMJIT_API Mem _BaseVarMem(const Var &var, uint32_t size);
+ASMJIT_API Mem _BaseVarMem(const Var &var, uint32_t size, sysint_t disp);
+ASMJIT_API Mem _BaseVarMem(const Var &var, uint32_t size, const GpVar &index, uint32_t shift, sysint_t disp);
+
+//! @brief Base class for all variables.
+struct Var : public Operand
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+#ifndef ASMJIT_NODOC
+ Var(const _DontInitialize &dontInitialize) : Operand(dontInitialize) { }
+#endif // ASMJIT_NODOC
+
+ Var() : Operand(_DontInitialize())
+ {
+ this->_var.op = kOperandVar;
+ this->_var.size = 0;
+ this->_var.regCode = kInvalidValue;
+ this->_var.varType = kInvalidValue;
+ this->_var.id = kInvalidValue;
+ }
+
+ Var(const Var &other) : Operand(other) { }
+
+ // --------------------------------------------------------------------------
+ // [Type]
+ // --------------------------------------------------------------------------
+
+ uint32_t getVarType() const { return this->_var.varType; }
+
+ bool isGpVar() const { return this->_var.varType <= kX86VarTypeGpq; }
+
+ bool isX87Var() const { return this->_var.varType >= kX86VarTypeX87 && this->_var.varType <= kX86VarTypeX87SD; }
+
+ bool isMmVar() const { return this->_var.varType == kX86VarTypeMm; }
+
+ bool isXmmVar() const { return this->_var.varType >= kX86VarTypeXmm && this->_var.varType <= kX86VarTypeXmmPD; }
+
+ // --------------------------------------------------------------------------
+ // [Memory Cast]
+ // --------------------------------------------------------------------------
+
+ //! @brief Cast this variable to memory operand.
+ //!
+ //! @note Size of operand depends on native variable type, you can use other
+ //! variants if you want specific one.
+ Mem m() const { return _BaseVarMem(*this, kInvalidValue); }
+
+ //! @overload.
+ Mem m(sysint_t disp) const { return _BaseVarMem(*this, kInvalidValue, disp); }
+
+ //! @overload.
+ Mem m(const GpVar &index, uint32_t shift = 0, sysint_t disp = 0) const { return _BaseVarMem(*this, kInvalidValue, index, shift, disp); }
+
+ //! @brief Cast this variable to 8-bit memory operand.
+ Mem m8() const { return _BaseVarMem(*this, 1); }
+
+ //! @overload.
+ Mem m8(sysint_t disp) const { return _BaseVarMem(*this, 1, disp); }
+
+ //! @overload.
+ Mem m8(const GpVar &index, uint32_t shift = 0, sysint_t disp = 0) const { return _BaseVarMem(*this, 1, index, shift, disp); }
+
+ //! @brief Cast this variable to 16-bit memory operand.
+ Mem m16() const { return _BaseVarMem(*this, 2); }
+
+ //! @overload.
+ Mem m16(sysint_t disp) const { return _BaseVarMem(*this, 2, disp); }
+
+ //! @overload.
+ Mem m16(const GpVar &index, uint32_t shift = 0, sysint_t disp = 0) const { return _BaseVarMem(*this, 2, index, shift, disp); }
+
+ //! @brief Cast this variable to 32-bit memory operand.
+ Mem m32() const { return _BaseVarMem(*this, 4); }
+
+ //! @overload.
+ Mem m32(sysint_t disp) const { return _BaseVarMem(*this, 4, disp); }
+
+ //! @overload.
+ Mem m32(const GpVar &index, uint32_t shift = 0, sysint_t disp = 0) const { return _BaseVarMem(*this, 4, index, shift, disp); }
+
+ //! @brief Cast this variable to 64-bit memory operand.
+ Mem m64() const { return _BaseVarMem(*this, 8); }
+
+ //! @overload.
+ Mem m64(sysint_t disp) const { return _BaseVarMem(*this, 8, disp); }
+
+ //! @overload.
+ Mem m64(const GpVar &index, uint32_t shift = 0, sysint_t disp = 0) const { return _BaseVarMem(*this, 8, index, shift, disp); }
+
+ //! @brief Cast this variable to 80-bit memory operand (long double).
+ Mem m80() const { return _BaseVarMem(*this, 10); }
+
+ //! @overload.
+ Mem m80(sysint_t disp) const { return _BaseVarMem(*this, 10, disp); }
+
+ //! @overload.
+ Mem m80(const GpVar &index, uint32_t shift = 0, sysint_t disp = 0) const { return _BaseVarMem(*this, 10, index, shift, disp); }
+
+ //! @brief Cast this variable to 128-bit memory operand.
+ Mem m128() const { return _BaseVarMem(*this, 16); }
+
+ //! @overload.
+ Mem m128(sysint_t disp) const { return _BaseVarMem(*this, 16, disp); }
+
+ //! @overload.
+ Mem m128(const GpVar &index, uint32_t shift = 0, sysint_t disp = 0) const { return _BaseVarMem(*this, 16, index, shift, disp); }
+
+ // --------------------------------------------------------------------------
+ // [Operator Overload]
+ // --------------------------------------------------------------------------
+
+#ifndef ASMJIT_NODOC
+ Var &operator=(const Var &other) { this->_copy(other); return *this; }
+
+ bool operator==(const Var &other) const { return this->_base.id == other._base.id && this->_var.regCode == other._var.regCode; }
+ bool operator!=(const Var &other) const { return this->_base.id != other._base.id || this->_var.regCode != other._var.regCode; }
+#endif // ASMJIT_NODOC
+
+ // --------------------------------------------------------------------------
+ // [Private]
+ // --------------------------------------------------------------------------
+
+protected:
+ Var(const Var &other, uint32_t regCode, uint32_t size) : Operand(_DontInitialize())
+ {
+ this->_var.op = kOperandVar;
+ this->_var.size = static_cast<uint8_t>(size);
+ this->_var.id = other._base.id;
+ this->_var.regCode = regCode;
+ this->_var.varType = other._var.varType;
+ }
+};
+
+// ============================================================================
+// [AsmJit::X87Var]
+// ============================================================================
+
+//! @brief X87 Variable operand.
+struct X87Var : public Var
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ X87Var(const _DontInitialize &dontInitialize) : Var(dontInitialize) { }
+
+ X87Var() : Var(_DontInitialize())
+ {
+ this->_var.op = kOperandVar;
+ this->_var.size = 12;
+ this->_var.id = kInvalidValue;
+
+ this->_var.regCode = kX86RegTypeX87;
+ this->_var.varType = kX86VarTypeX87;
+ }
+
+ X87Var(const X87Var &other) : Var(other) { }
+
+ // --------------------------------------------------------------------------
+ // [Operator Overload]
+ // --------------------------------------------------------------------------
+
+#ifndef ASMJIT_NODOC
+ X87Var &operator=(const X87Var &other) { this->_copy(other); return *this; }
+
+ bool operator==(const X87Var &other) const { return this->_base.id == other._base.id; }
+ bool operator!=(const X87Var &other) const { return this->_base.id != other._base.id; }
+#endif // ASMJIT_NODOC
+};
+
+// ============================================================================
+// [AsmJit::GpVar]
+// ============================================================================
+
+//! @brief GP variable operand.
+struct GpVar : public Var
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create new uninitialized @c GpVar instance (internal constructor).
+ GpVar(const _DontInitialize &dontInitialize) : Var(dontInitialize) { }
+
+ //! @brief Create new uninitialized @c GpVar instance.
+ GpVar() : Var(_DontInitialize())
+ {
+ this->_var.op = kOperandVar;
+ this->_var.size = sizeof(sysint_t);
+ this->_var.id = kInvalidValue;
+
+ this->_var.regCode = kX86RegTypeGpz;
+ this->_var.varType = kX86VarTypeGpz;
+ }
+
+ //! @brief Create new @c GpVar instance using @a other.
+ //!
+ //! Note this will not create a different variable, use @c Compiler::newGpVar()
+ //! if you want to do so. This is only copy-constructor that allows to store
+ //! the same variable in different places.
+ GpVar(const GpVar &other) : Var(other) { }
+
+ // --------------------------------------------------------------------------
+ // [GpVar Specific]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get whether this variable is general purpose BYTE register.
+ bool isGpb() const { return (this->_var.regCode & kRegTypeMask) <= kX86RegTypeGpbHi; }
+ //! @brief Get whether this variable is general purpose BYTE.LO register.
+ bool isGpbLo() const { return (this->_var.regCode & kRegTypeMask) == kX86RegTypeGpbLo; }
+ //! @brief Get whether this variable is general purpose BYTE.HI register.
+ bool isGpbHi() const { return (this->_var.regCode & kRegTypeMask) == kX86RegTypeGpbHi; }
+
+ //! @brief Get whether this variable is general purpose WORD register.
+ bool isGpw() const { return (this->_var.regCode & kRegTypeMask) == kX86RegTypeGpw; }
+ //! @brief Get whether this variable is general purpose DWORD register.
+ bool isGpd() const { return (this->_var.regCode & kRegTypeMask) == kX86RegTypeGpd; }
+ //! @brief Get whether this variable is general purpose QWORD (only 64-bit) register.
+ bool isGpq() const { return (this->_var.regCode & kRegTypeMask) == kX86RegTypeGpq; }
+
+ // --------------------------------------------------------------------------
+ // [GpVar Cast]
+ // --------------------------------------------------------------------------
+
+ //! @brief Cast this variable to 8-bit (LO) part of variable
+ GpVar r8() const { return GpVar(*this, kX86RegTypeGpbLo, 1); }
+ //! @brief Cast this variable to 8-bit (LO) part of variable
+ GpVar r8Lo() const { return GpVar(*this, kX86RegTypeGpbLo, 1); }
+ //! @brief Cast this variable to 8-bit (HI) part of variable
+ GpVar r8Hi() const { return GpVar(*this, kX86RegTypeGpbHi, 1); }
+
+ //! @brief Cast this variable to 16-bit part of variable
+ GpVar r16() const { return GpVar(*this, kX86RegTypeGpw, 2); }
+ //! @brief Cast this variable to 32-bit part of variable
+ GpVar r32() const { return GpVar(*this, kX86RegTypeGpd, 4); }
+#ifdef ASMJIT_X64
+ //! @brief Cast this variable to 64-bit part of variable
+ GpVar r64() const { return GpVar(*this, kX86RegTypeGpq, 8); }
+#endif // ASMJIT_X64
+
+ // --------------------------------------------------------------------------
+ // [Operator Overload]
+ // --------------------------------------------------------------------------
+
+#ifndef ASMJIT_NODOC
+ GpVar &operator=(const GpVar &other) { this->_copy(other); return *this; }
+
+ bool operator==(const GpVar &other) const { return this->_base.id == other._base.id && this->_var.regCode == other._var.regCode; }
+ bool operator!=(const GpVar &other) const { return this->_base.id != other._base.id || this->_var.regCode != other._var.regCode; }
+#endif // ASMJIT_NODOC
+
+ // --------------------------------------------------------------------------
+ // [Private]
+ // --------------------------------------------------------------------------
+
+protected:
+ GpVar(const GpVar &other, uint32_t regCode, uint32_t size) : Var(other, regCode, size) { }
+};
+
+// ============================================================================
+// [AsmJit::MmVar]
+// ============================================================================
+
+//! @brief MM variable operand.
+struct MmVar : public Var
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ //! @brief Create new uninitialized @c MmVar instance (internal constructor).
+ MmVar(const _DontInitialize &dontInitialize) : Var(dontInitialize) { }
+
+ //! @brief Create new uninitialized @c MmVar instance.
+ MmVar() : Var(_DontInitialize())
+ {
+ this->_var.op = kOperandVar;
+ this->_var.size = 8;
+ this->_var.id = kInvalidValue;
+
+ this->_var.regCode = kX86RegTypeMm;
+ this->_var.varType = kX86VarTypeMm;
+ }
+
+ //! @brief Create new @c MmVar instance using @a other.
+ //!
+ //! Note this will not create a different variable, use @c Compiler::newMmVar()
+ //! if you want to do so. This is only copy-constructor that allows to store
+ //! the same variable in different places.
+ MmVar(const MmVar &other) : Var(other) { }
+
+ // --------------------------------------------------------------------------
+ // [MmVar Cast]
+ // --------------------------------------------------------------------------
+
+ // --------------------------------------------------------------------------
+ // [Operator Overload]
+ // --------------------------------------------------------------------------
+
+#ifndef ASMJIT_NODOC
+ MmVar &operator=(const MmVar &other) { this->_copy(other); return *this; }
+
+ bool operator==(const MmVar &other) const { return this->_base.id == other._base.id; }
+ bool operator!=(const MmVar &other) const { return this->_base.id != other._base.id; }
+#endif // ASMJIT_NODOC
+};
+
+// ============================================================================
+// [AsmJit::XmmVar]
+// ============================================================================
+
+//! @brief XMM Variable operand.
+struct XmmVar : public Var
+{
+ // --------------------------------------------------------------------------
+ // [Construction / Destruction]
+ // --------------------------------------------------------------------------
+
+ XmmVar(const _DontInitialize &dontInitialize) : Var(dontInitialize) { }
+
+ XmmVar() : Var(_DontInitialize())
+ {
+ this->_var.op = kOperandVar;
+ this->_var.size = 16;
+ this->_var.id = kInvalidValue;
+
+ this->_var.regCode = kX86RegTypeXmm;
+ this->_var.varType = kX86VarTypeXmm;
+ }
+
+ XmmVar(const XmmVar &other) : Var(other) { }
+
+ // --------------------------------------------------------------------------
+ // [XmmVar Access]
+ // --------------------------------------------------------------------------
+
+ // --------------------------------------------------------------------------
+ // [Operator Overload]
+ // --------------------------------------------------------------------------
+
+#ifndef ASMJIT_NODOC
+ XmmVar &operator=(const XmmVar &other) { this->_copy(other); return *this; }
+
+ bool operator==(const XmmVar &other) const { return this->_base.id == other._base.id; }
+ bool operator!=(const XmmVar &other) const { return this->_base.id != other._base.id; }
+#endif // ASMJIT_NODOC
+};
+
+// ============================================================================
+// [AsmJit::Mem - [label + displacement]]
+// ============================================================================
+
+//! @brief Create a custom pointer operand.
+ASMJIT_API Mem ptr(const Label &label, sysint_t disp = 0, uint32_t size = 0);
+//! @brief Create a byte pointer operand.
+inline Mem byte_ptr(const Label &label, sysint_t disp = 0) { return ptr(label, disp, kSizeByte); }
+//! @brief Create a word pointer operand.
+inline Mem word_ptr(const Label &label, sysint_t disp = 0) { return ptr(label, disp, kSizeWord); }
+//! @brief Create a dword pointer operand.
+inline Mem dword_ptr(const Label &label, sysint_t disp = 0) { return ptr(label, disp, kSizeDWord); }
+//! @brief Create a qword pointer operand.
+inline Mem qword_ptr(const Label &label, sysint_t disp = 0) { return ptr(label, disp, kSizeQWord); }
+//! @brief Create a tword pointer operand.
+inline Mem tword_ptr(const Label &label, sysint_t disp = 0) { return ptr(label, disp, kSizeTWord); }
+//! @brief Create a dqword pointer operand.
+inline Mem dqword_ptr(const Label &label, sysint_t disp = 0) { return ptr(label, disp, kSizeDQWord); }
+//! @brief Create a mmword pointer operand.
+inline Mem mmword_ptr(const Label &label, sysint_t disp = 0) { return ptr(label, disp, kSizeQWord); }
+//! @brief Create a xmmword pointer operand.
+inline Mem xmmword_ptr(const Label &label, sysint_t disp = 0) { return ptr(label, disp, kSizeDQWord); }
+//! @brief Create an intptr_t pointer operand.
+inline Mem sysint_ptr(const Label &label, sysint_t disp = 0) { return ptr(label, disp, sizeof(sysint_t)); }
+
+// ============================================================================
+// [AsmJit::Mem - [label + index << shift + displacement]]
+// ============================================================================
+
+//! @brief Create a custom pointer operand.
+ASMJIT_API Mem ptr(const Label &label, const GpReg &index, uint32_t shift, sysint_t disp = 0, uint32_t size = 0);
+//! @brief Create a byte pointer operand.
+inline Mem byte_ptr(const Label &label, const GpReg &index, uint32_t shift, sysint_t disp = 0) { return ptr(label, index, shift, disp, kSizeByte); }
+//! @brief Create a word pointer operand.
+inline Mem word_ptr(const Label &label, const GpReg &index, uint32_t shift, sysint_t disp = 0) { return ptr(label, index, shift, disp, kSizeWord); }
+//! @brief Create a dword pointer operand.
+inline Mem dword_ptr(const Label &label, const GpReg &index, uint32_t shift, sysint_t disp = 0) { return ptr(label, index, shift, disp, kSizeDWord); }
+//! @brief Create a qword pointer operand.
+inline Mem qword_ptr(const Label &label, const GpReg &index, uint32_t shift, sysint_t disp = 0) { return ptr(label, index, shift, disp, kSizeQWord); }
+//! @brief Create a tword pointer operand.
+inline Mem tword_ptr(const Label &label, const GpReg &index, uint32_t shift, sysint_t disp = 0) { return ptr(label, index, shift, disp, kSizeTWord); }
+//! @brief Create a dqword pointer operand.
+inline Mem dqword_ptr(const Label &label, const GpReg &index, uint32_t shift, sysint_t disp = 0) { return ptr(label, index, shift, disp, kSizeDQWord); }
+//! @brief Create a mmword pointer operand.
+inline Mem mmword_ptr(const Label &label, const GpReg &index, uint32_t shift, sysint_t disp = 0) { return ptr(label, index, shift, disp, kSizeQWord); }
+//! @brief Create a xmmword pointer operand.
+inline Mem xmmword_ptr(const Label &label, const GpReg &index, uint32_t shift, sysint_t disp = 0) { return ptr(label, index, shift, disp, kSizeDQWord); }
+//! @brief Create an intptr_t pointer operand.
+inline Mem sysint_ptr(const Label &label, const GpReg &index, uint32_t shift, sysint_t disp = 0) { return ptr(label, index, shift, disp, sizeof(sysint_t)); }
+
+//! @brief Create a custom pointer operand.
+ASMJIT_API Mem ptr(const Label &label, const GpVar &index, uint32_t shift, sysint_t disp = 0, uint32_t size = 0);
+//! @brief Create a byte pointer operand.
+inline Mem byte_ptr(const Label &label, const GpVar &index, uint32_t shift, sysint_t disp = 0) { return ptr(label, index, shift, disp, kSizeByte); }
+//! @brief Create a word pointer operand.
+inline Mem word_ptr(const Label &label, const GpVar &index, uint32_t shift, sysint_t disp = 0) { return ptr(label, index, shift, disp, kSizeWord); }
+//! @brief Create a dword pointer operand.
+inline Mem dword_ptr(const Label &label, const GpVar &index, uint32_t shift, sysint_t disp = 0) { return ptr(label, index, shift, disp, kSizeDWord); }
+//! @brief Create a qword pointer operand.
+inline Mem qword_ptr(const Label &label, const GpVar &index, uint32_t shift, sysint_t disp = 0) { return ptr(label, index, shift, disp, kSizeQWord); }
+//! @brief Create a tword pointer operand.
+inline Mem tword_ptr(const Label &label, const GpVar &index, uint32_t shift, sysint_t disp = 0) { return ptr(label, index, shift, disp, kSizeTWord); }
+//! @brief Create a dqword pointer operand.
+inline Mem dqword_ptr(const Label &label, const GpVar &index, uint32_t shift, sysint_t disp = 0) { return ptr(label, index, shift, disp, kSizeDQWord); }
+//! @brief Create a mmword pointer operand.
+inline Mem mmword_ptr(const Label &label, const GpVar &index, uint32_t shift, sysint_t disp = 0) { return ptr(label, index, shift, disp, kSizeQWord); }
+//! @brief Create a xmmword pointer operand.
+inline Mem xmmword_ptr(const Label &label, const GpVar &index, uint32_t shift, sysint_t disp = 0) { return ptr(label, index, shift, disp, kSizeDQWord); }
+//! @brief Create an intptr_t pointer operand.
+inline Mem sysint_ptr(const Label &label, const GpVar &index, uint32_t shift, sysint_t disp = 0) { return ptr(label, index, shift, disp, sizeof(sysint_t)); }
+
+// ============================================================================
+// [AsmJit::Mem - segment[target + displacement]
+// ============================================================================
+
+//! @brief Create a custom pointer operand.
+ASMJIT_API Mem ptr_abs(void *target, sysint_t disp = 0, uint32_t size = 0);
+//! @brief Create a byte pointer operand.
+inline Mem byte_ptr_abs(void *target, sysint_t disp = 0) { return ptr_abs(target, disp, kSizeByte); }
+//! @brief Create a word pointer operand.
+inline Mem word_ptr_abs(void *target, sysint_t disp = 0) { return ptr_abs(target, disp, kSizeWord); }
+//! @brief Create a dword pointer operand.
+inline Mem dword_ptr_abs(void *target, sysint_t disp = 0) { return ptr_abs(target, disp, kSizeDWord); }
+//! @brief Create a qword pointer operand.
+inline Mem qword_ptr_abs(void *target, sysint_t disp = 0) { return ptr_abs(target, disp, kSizeQWord); }
+//! @brief Create a tword pointer operand (used for 80-bit floating points).
+inline Mem tword_ptr_abs(void *target, sysint_t disp = 0) { return ptr_abs(target, disp, kSizeTWord); }
+//! @brief Create a dqword pointer operand.
+inline Mem dqword_ptr_abs(void *target, sysint_t disp = 0) { return ptr_abs(target, disp, kSizeDQWord); }
+//! @brief Create a mmword pointer operand.
+inline Mem mmword_ptr_abs(void *target, sysint_t disp = 0) { return ptr_abs(target, disp, kSizeQWord); }
+//! @brief Create a xmmword pointer operand.
+inline Mem xmmword_ptr_abs(void *target, sysint_t disp = 0) { return ptr_abs(target, disp, kSizeDQWord); }
+//! @brief Create an intptr_t pointer operand.
+inline Mem sysint_ptr_abs(void *target, sysint_t disp = 0) { return ptr_abs(target, disp, sizeof(sysint_t)); }
+
+// ============================================================================
+// [AsmJit::Mem - segment[target + index << shift + displacement]
+// ============================================================================
+
+//! @brief Create a custom pointer operand.
+ASMJIT_API Mem ptr_abs(void *target, const GpReg &index, uint32_t shift, sysint_t disp = 0, uint32_t size = 0);
+//! @brief Create a byte pointer operand.
+inline Mem byte_ptr_abs(void *target, const GpReg &index, uint32_t shift, sysint_t disp = 0) { return ptr_abs(target, index, shift, disp, kSizeByte); }
+//! @brief Create a word pointer operand.
+inline Mem word_ptr_abs(void *target, const GpReg &index, uint32_t shift, sysint_t disp = 0) { return ptr_abs(target, index, shift, disp, kSizeWord); }
+//! @brief Create a dword pointer operand.
+inline Mem dword_ptr_abs(void *target, const GpReg &index, uint32_t shift, sysint_t disp = 0) { return ptr_abs(target, index, shift, disp, kSizeDWord); }
+//! @brief Create a qword pointer operand.
+inline Mem qword_ptr_abs(void *target, const GpReg &index, uint32_t shift, sysint_t disp = 0) { return ptr_abs(target, index, shift, disp, kSizeQWord); }
+//! @brief Create a tword pointer operand.
+inline Mem tword_ptr_abs(void *target, const GpReg &index, uint32_t shift, sysint_t disp = 0) { return ptr_abs(target, index, shift, disp, kSizeTWord); }
+//! @brief Create a dqword pointer operand.
+inline Mem dqword_ptr_abs(void *target, const GpReg &index, uint32_t shift, sysint_t disp = 0) { return ptr_abs(target, index, shift, disp, kSizeDQWord); }
+//! @brief Create a mmword pointer operand.
+inline Mem mmword_ptr_abs(void *target, const GpReg &index, uint32_t shift, sysint_t disp = 0) { return ptr_abs(target, index, shift, disp, kSizeQWord); }
+//! @brief Create a xmmword pointer operand.
+inline Mem xmmword_ptr_abs(void *target, const GpReg &index, uint32_t shift, sysint_t disp = 0) { return ptr_abs(target, index, shift, disp, kSizeDQWord); }
+//! @brief Create an intptr_t pointer operand.
+inline Mem sysint_ptr_abs(void *target, const GpReg &index, uint32_t shift, sysint_t disp = 0) { return ptr_abs(target, index, shift, disp, sizeof(sysint_t)); }
+
+//! @brief Create a custom pointer operand.
+ASMJIT_API Mem ptr_abs(void *target, const GpVar &index, uint32_t shift, sysint_t disp = 0, uint32_t size = 0);
+//! @brief Create a byte pointer operand.
+inline Mem byte_ptr_abs(void *target, const GpVar &index, uint32_t shift, sysint_t disp = 0) { return ptr_abs(target, index, shift, disp, kSizeByte); }
+//! @brief Create a word pointer operand.
+inline Mem word_ptr_abs(void *target, const GpVar &index, uint32_t shift, sysint_t disp = 0) { return ptr_abs(target, index, shift, disp, kSizeWord); }
+//! @brief Create a dword pointer operand.
+inline Mem dword_ptr_abs(void *target, const GpVar &index, uint32_t shift, sysint_t disp = 0) { return ptr_abs(target, index, shift, disp, kSizeDWord); }
+//! @brief Create a qword pointer operand.
+inline Mem qword_ptr_abs(void *target, const GpVar &index, uint32_t shift, sysint_t disp = 0) { return ptr_abs(target, index, shift, disp, kSizeQWord); }
+//! @brief Create a tword pointer operand.
+inline Mem tword_ptr_abs(void *target, const GpVar &index, uint32_t shift, sysint_t disp = 0) { return ptr_abs(target, index, shift, disp, kSizeTWord); }
+//! @brief Create a dqword pointer operand.
+inline Mem dqword_ptr_abs(void *target, const GpVar &index, uint32_t shift, sysint_t disp = 0) { return ptr_abs(target, index, shift, disp, kSizeDQWord); }
+//! @brief Create a mmword pointer operand.
+inline Mem mmword_ptr_abs(void *target, const GpVar &index, uint32_t shift, sysint_t disp = 0) { return ptr_abs(target, index, shift, disp, kSizeQWord); }
+//! @brief Create a xmmword pointer operand.
+inline Mem xmmword_ptr_abs(void *target, const GpVar &index, uint32_t shift, sysint_t disp = 0) { return ptr_abs(target, index, shift, disp, kSizeDQWord); }
+//! @brief Create an intptr_t pointer operand.
+inline Mem sysint_ptr_abs(void *target, const GpVar &index, uint32_t shift, sysint_t disp = 0) { return ptr_abs(target, index, shift, disp, sizeof(sysint_t)); }
+
+// ============================================================================
+// [AsmJit::Mem - ptr[base + displacement]]
+// ============================================================================
+
+//! @brief Create a custom pointer operand.
+ASMJIT_API Mem ptr(const GpReg &base, sysint_t disp = 0, uint32_t size = 0);
+//! @brief Create a byte pointer operand.
+inline Mem byte_ptr(const GpReg &base, sysint_t disp = 0) { return ptr(base, disp, kSizeByte); }
+//! @brief Create a word pointer operand.
+inline Mem word_ptr(const GpReg &base, sysint_t disp = 0) { return ptr(base, disp, kSizeWord); }
+//! @brief Create a dword pointer operand.
+inline Mem dword_ptr(const GpReg &base, sysint_t disp = 0) { return ptr(base, disp, kSizeDWord); }
+//! @brief Create a qword pointer operand.
+inline Mem qword_ptr(const GpReg &base, sysint_t disp = 0) { return ptr(base, disp, kSizeQWord); }
+//! @brief Create a tword pointer operand.
+inline Mem tword_ptr(const GpReg &base, sysint_t disp = 0) { return ptr(base, disp, kSizeTWord); }
+//! @brief Create a dqword pointer operand.
+inline Mem dqword_ptr(const GpReg &base, sysint_t disp = 0) { return ptr(base, disp, kSizeDQWord); }
+//! @brief Create a mmword pointer operand.
+inline Mem mmword_ptr(const GpReg &base, sysint_t disp = 0) { return ptr(base, disp, kSizeQWord); }
+//! @brief Create a xmmword pointer operand.
+inline Mem xmmword_ptr(const GpReg &base, sysint_t disp = 0) { return ptr(base, disp, kSizeDQWord); }
+//! @brief Create an intptr_t pointer operand.
+inline Mem sysint_ptr(const GpReg &base, sysint_t disp = 0) { return ptr(base, disp, sizeof(sysint_t)); }
+
+//! @brief Create a custom pointer operand.
+ASMJIT_API Mem ptr(const GpVar &base, sysint_t disp = 0, uint32_t size = 0);
+//! @brief Create a byte pointer operand.
+inline Mem byte_ptr(const GpVar &base, sysint_t disp = 0) { return ptr(base, disp, kSizeByte); }
+//! @brief Create a word pointer operand.
+inline Mem word_ptr(const GpVar &base, sysint_t disp = 0) { return ptr(base, disp, kSizeWord); }
+//! @brief Create a dword pointer operand.
+inline Mem dword_ptr(const GpVar &base, sysint_t disp = 0) { return ptr(base, disp, kSizeDWord); }
+//! @brief Create a qword pointer operand.
+inline Mem qword_ptr(const GpVar &base, sysint_t disp = 0) { return ptr(base, disp, kSizeQWord); }
+//! @brief Create a tword pointer operand.
+inline Mem tword_ptr(const GpVar &base, sysint_t disp = 0) { return ptr(base, disp, kSizeTWord); }
+//! @brief Create a dqword pointer operand.
+inline Mem dqword_ptr(const GpVar &base, sysint_t disp = 0) { return ptr(base, disp, kSizeDQWord); }
+//! @brief Create a mmword pointer operand.
+inline Mem mmword_ptr(const GpVar &base, sysint_t disp = 0) { return ptr(base, disp, kSizeQWord); }
+//! @brief Create a xmmword pointer operand.
+inline Mem xmmword_ptr(const GpVar &base, sysint_t disp = 0) { return ptr(base, disp, kSizeDQWord); }
+//! @brief Create an intptr_t pointer operand.
+inline Mem sysint_ptr(const GpVar &base, sysint_t disp = 0) { return ptr(base, disp, sizeof(sysint_t)); }
+
+// ============================================================================
+// [AsmJit::Mem - ptr[base + (index << shift) + displacement]]
+// ============================================================================
+
+//! @brief Create a custom pointer operand.
+ASMJIT_API Mem ptr(const GpReg &base, const GpReg &index, uint32_t shift = 0, sysint_t disp = 0, uint32_t size = 0);
+//! @brief Create a byte pointer operand.
+inline Mem byte_ptr(const GpReg &base, const GpReg &index, uint32_t shift = 0, sysint_t disp = 0) { return ptr(base, index, shift, disp, kSizeByte); }
+//! @brief Create a word pointer operand.
+inline Mem word_ptr(const GpReg &base, const GpReg &index, uint32_t shift = 0, sysint_t disp = 0) { return ptr(base, index, shift, disp, kSizeWord); }
+//! @brief Create a dword pointer operand.
+inline Mem dword_ptr(const GpReg &base, const GpReg &index, uint32_t shift = 0, sysint_t disp = 0) { return ptr(base, index, shift, disp, kSizeDWord); }
+//! @brief Create a qword pointer operand.
+inline Mem qword_ptr(const GpReg &base, const GpReg &index, uint32_t shift = 0, sysint_t disp = 0) { return ptr(base, index, shift, disp, kSizeQWord); }
+//! @brief Create a tword pointer operand.
+inline Mem tword_ptr(const GpReg &base, const GpReg &index, uint32_t shift = 0, sysint_t disp = 0) { return ptr(base, index, shift, disp, kSizeTWord); }
+//! @brief Create a dqword pointer operand.
+inline Mem dqword_ptr(const GpReg &base, const GpReg &index, uint32_t shift = 0, sysint_t disp = 0) { return ptr(base, index, shift, disp, kSizeDQWord); }
+//! @brief Create a mmword pointer operand.
+inline Mem mmword_ptr(const GpReg &base, const GpReg &index, uint32_t shift = 0, sysint_t disp = 0) { return ptr(base, index, shift, disp, kSizeQWord); }
+//! @brief Create a xmmword pointer operand.
+inline Mem xmmword_ptr(const GpReg &base, const GpReg &index, uint32_t shift = 0, sysint_t disp = 0) { return ptr(base, index, shift, disp, kSizeDQWord); }
+//! @brief Create an intptr_t pointer operand.
+inline Mem sysint_ptr(const GpReg &base, const GpReg &index, uint32_t shift = 0, sysint_t disp = 0) { return ptr(base, index, shift, disp, sizeof(sysint_t)); }
+
+//! @brief Create a custom pointer operand.
+ASMJIT_API Mem ptr(const GpVar &base, const GpVar &index, uint32_t shift = 0, sysint_t disp = 0, uint32_t size = 0);
+//! @brief Create a byte pointer operand.
+inline Mem byte_ptr(const GpVar &base, const GpVar &index, uint32_t shift = 0, sysint_t disp = 0) { return ptr(base, index, shift, disp, kSizeByte); }
+//! @brief Create a word pointer operand.
+inline Mem word_ptr(const GpVar &base, const GpVar &index, uint32_t shift = 0, sysint_t disp = 0) { return ptr(base, index, shift, disp, kSizeWord); }
+//! @brief Create a dword pointer operand.
+inline Mem dword_ptr(const GpVar &base, const GpVar &index, uint32_t shift = 0, sysint_t disp = 0) { return ptr(base, index, shift, disp, kSizeDWord); }
+//! @brief Create a qword pointer operand.
+inline Mem qword_ptr(const GpVar &base, const GpVar &index, uint32_t shift = 0, sysint_t disp = 0) { return ptr(base, index, shift, disp, kSizeQWord); }
+//! @brief Create a tword pointer operand.
+inline Mem tword_ptr(const GpVar &base, const GpVar &index, uint32_t shift = 0, sysint_t disp = 0) { return ptr(base, index, shift, disp, kSizeTWord); }
+//! @brief Create a dqword pointer operand.
+inline Mem dqword_ptr(const GpVar &base, const GpVar &index, uint32_t shift = 0, sysint_t disp = 0) { return ptr(base, index, shift, disp, kSizeDQWord); }
+//! @brief Create a mmword pointer operand.
+inline Mem mmword_ptr(const GpVar &base, const GpVar &index, uint32_t shift = 0, sysint_t disp = 0) { return ptr(base, index, shift, disp, kSizeQWord); }
+//! @brief Create a xmmword pointer operand.
+inline Mem xmmword_ptr(const GpVar &base, const GpVar &index, uint32_t shift = 0, sysint_t disp = 0) { return ptr(base, index, shift, disp, kSizeDQWord); }
+//! @brief Create an intptr_t pointer operand.
+inline Mem sysint_ptr(const GpVar &base, const GpVar &index, uint32_t shift = 0, sysint_t disp = 0) { return ptr(base, index, shift, disp, sizeof(sysint_t)); }
+
+// ============================================================================
+// [AsmJit::Macros]
+// ============================================================================
+
+//! @brief Create Shuffle Constant for MMX/SSE shuffle instrutions.
+//! @param z First component position, number at interval [0, 3] inclusive.
+//! @param x Second component position, number at interval [0, 3] inclusive.
+//! @param y Third component position, number at interval [0, 3] inclusive.
+//! @param w Fourth component position, number at interval [0, 3] inclusive.
+//!
+//! Shuffle constants can be used to make immediate value for these intrinsics:
+//! - @ref X86Assembler::pshufw()
+//! - @ref X86Assembler::pshufd()
+//! - @ref X86Assembler::pshufhw()
+//! - @ref X86Assembler::pshuflw()
+//! - @ref X86Assembler::shufps()
+inline uint8_t mm_shuffle(uint8_t z, uint8_t y, uint8_t x, uint8_t w) { return (z << 6) | (y << 4) | (x << 2) | w; }
+
+//! @}
+
+} // AsmJit namespace
+
+// [Guard]
+#endif // _ASMJIT_X86_X86OPERAND_H
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86/x86util.cpp
@@ -1,1 +1,139 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+#define ASMJIT_EXPORTS
+
+// [Dependencies - AsmJit]
+#include "../x86/x86defs.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit {
+
+// ============================================================================
+// [AsmJit::_x86UtilJccFromCond]
+// ============================================================================
+
+const uint32_t _x86UtilJccFromCond[20] =
+{
+ kX86InstJO,
+ kX86InstJNO,
+ kX86InstJB,
+ kX86InstJAE,
+ kX86InstJE,
+ kX86InstJNE,
+ kX86InstJBE,
+ kX86InstJA,
+ kX86InstJS,
+ kX86InstJNS,
+ kX86InstJPE,
+ kX86InstJPO,
+ kX86InstJL,
+ kX86InstJGE,
+ kX86InstJLE,
+ kX86InstJG,
+
+ kInstNone,
+ kInstNone,
+ kInstNone,
+ kInstNone
+};
+
+// ============================================================================
+// [AsmJit::_x86UtilMovccFromCond]
+// ============================================================================
+
+const uint32_t _x86UtilMovccFromCond[20] =
+{
+ kX86InstCMovO,
+ kX86InstCMovNO,
+ kX86InstCMovB,
+ kX86InstCMovAE,
+ kX86InstCMovE,
+ kX86InstCMovNE,
+ kX86InstCMovBE,
+ kX86InstCMovA,
+ kX86InstCMovS,
+ kX86InstCMovNS,
+ kX86InstCMovPE,
+ kX86InstCMovPO,
+ kX86InstCMovL,
+ kX86InstCMovGE,
+ kX86InstCMovLE,
+ kX86InstCMovG,
+
+ kInstNone,
+ kInstNone,
+ kInstNone,
+ kInstNone
+};
+
+// ============================================================================
+// [AsmJit::_x86UtilSetccFromCond]
+// ============================================================================
+
+const uint32_t _x86UtilSetccFromCond[20] =
+{
+ kX86InstSetO,
+ kX86InstSetNO,
+ kX86InstSetB,
+ kX86InstSetAE,
+ kX86InstSetE,
+ kX86InstSetNE,
+ kX86InstSetBE,
+ kX86InstSetA,
+ kX86InstSetS,
+ kX86InstSetNS,
+ kX86InstSetPE,
+ kX86InstSetPO,
+ kX86InstSetL,
+ kX86InstSetGE,
+ kX86InstSetLE,
+ kX86InstSetG,
+
+ kInstNone,
+ kInstNone,
+ kInstNone,
+ kInstNone
+};
+
+// ============================================================================
+// [AsmJit::_x86UtilReversedCond]
+// ============================================================================
+
+const uint32_t _x86UtilReversedCond[20] =
+{
+ /* x86CondO -> */ kX86CondO,
+ /* x86CondNO -> */ kX86CondNO,
+ /* x86CondB -> */ kX86CondA,
+ /* x86CondAE -> */ kX86CondBE,
+ /* x86CondE -> */ kX86CondE,
+ /* x86CondNE -> */ kX86CondNE,
+ /* x86CondBE -> */ kX86CondAE,
+ /* x86CondA -> */ kX86CondB,
+ /* x86CondS -> */ kX86CondS,
+ /* x86CondNS -> */ kX86CondNS,
+ /* x86CondPE -> */ kX86CondPE,
+ /* x86CondPO -> */ kX86CondPO,
+
+ /* x86CondL -> */ kX86CondG,
+ /* x86CondGE -> */ kX86CondLE,
+
+ /* x86CondLE -> */ kX86CondGE,
+ /* x86CondG -> */ kX86CondL,
+
+ /* kX86CondFpuUnordered -> */ kX86CondFpuUnordered,
+ /* kX86CondFpuNotUnordered -> */ kX86CondFpuNotUnordered,
+
+ 0x12,
+ 0x13
+};
+
+} // AsmJit namespace
+
+#include "../core/apiend.h"
+
--- /dev/null
+++ b/src/in_2sf/desmume/utils/AsmJit/x86/x86util.h
@@ -1,1 +1,124 @@
+// [AsmJit]
+// Complete JIT Assembler for C++ Language.
+//
+// [License]
+// Zlib - See COPYING file in this package.
+// [Guard]
+#ifndef _ASMJIT_X86_X86UTIL_H
+#define _ASMJIT_X86_X86UTIL_H
+
+// [Dependencies - AsmJit]
+#include "../x86/x86defs.h"
+#include "../x86/x86operand.h"
+
+// [Api-Begin]
+#include "../core/apibegin.h"
+
+namespace AsmJit
+{
+
+//! @addtogroup AsmJit_X86
+//! @{
+
+// ============================================================================
+// [AsmJit::X86Util]
+// ============================================================================
+
+//! @brief Map condition code to "jcc" group of instructions.
+ASMJIT_VAR const uint32_t _x86UtilJccFromCond[20];
+//! @brief Map condition code to "cmovcc" group of instructions.
+ASMJIT_VAR const uint32_t _x86UtilMovccFromCond[20];
+//! @brief Map condition code to "setcc" group of instructions.
+ASMJIT_VAR const uint32_t _x86UtilSetccFromCond[20];
+//! @brief Map condition code to reversed condition code.
+ASMJIT_VAR const uint32_t _x86UtilReversedCond[20];
+
+struct X86Util
+{
+ // --------------------------------------------------------------------------
+ // [Condition Codes]
+ // --------------------------------------------------------------------------
+
+ //! @brief Get the equivalent of negated condition code.
+ static uint32_t getNegatedCond(uint32_t cond)
+ {
+ return static_cast<kX86Cond>(cond ^ static_cast<uint32_t>(cond < kX86CondNone));
+ }
+
+ //! @brief Corresponds to transposing the operands of a comparison.
+ static uint32_t getReversedCond(uint32_t cond)
+ {
+ ASMJIT_ASSERT(static_cast<uint32_t>(cond) < ASMJIT_ARRAY_SIZE(_x86UtilReversedCond));
+ return _x86UtilReversedCond[cond];
+ }
+
+ //! @brief Translate condition code @a cc to jcc instruction code.
+ //! @sa @c kX86InstCode, @c kX86InstJ.
+ static uint32_t getJccInstFromCond(uint32_t cond)
+ {
+ ASMJIT_ASSERT(static_cast<uint32_t>(cond) < ASMJIT_ARRAY_SIZE(_x86UtilJccFromCond));
+ return _x86UtilJccFromCond[cond];
+ }
+
+ //! @brief Translate condition code @a cc to cmovcc instruction code.
+ //! @sa @c kX86InstCode, @c kX86InstCMov.
+ static uint32_t getCMovccInstFromCond(uint32_t cond)
+ {
+ ASMJIT_ASSERT(static_cast<uint32_t>(cond) < ASMJIT_ARRAY_SIZE(_x86UtilMovccFromCond));
+ return _x86UtilMovccFromCond[cond];
+ }
+
+ //! @brief Translate condition code @a cc to setcc instruction code.
+ //! @sa @c kX86InstCode, @c kX86InstSet.
+ static uint32_t getSetccInstFromCond(uint32_t cond)
+ {
+ ASMJIT_ASSERT(static_cast<uint32_t>(cond) < ASMJIT_ARRAY_SIZE(_x86UtilSetccFromCond));
+ return _x86UtilSetccFromCond[cond];
+ }
+
+ // --------------------------------------------------------------------------
+ // [Variables]
+ // --------------------------------------------------------------------------
+
+ static uint32_t getVarClassFromVarType(uint32_t varType)
+ {
+ ASMJIT_ASSERT(varType < kX86VarTypeCount);
+ return x86VarInfo[varType].getClass();
+ }
+
+ static uint32_t getVarSizeFromVarType(uint32_t varType)
+ {
+ ASMJIT_ASSERT(varType < kX86VarTypeCount);
+ return x86VarInfo[varType].getSize();
+ }
+
+ static uint32_t getRegCodeFromVarType(uint32_t varType, uint32_t regIndex)
+ {
+ ASMJIT_ASSERT(varType < kX86VarTypeCount);
+ return x86VarInfo[varType].getCode() | regIndex;
+ }
+
+ static bool isVarTypeInt(uint32_t varType)
+ {
+ ASMJIT_ASSERT(varType < kX86VarTypeCount);
+ return !!(x86VarInfo[varType].getClass() & kX86VarClassGp);
+ }
+
+ static bool isVarTypeFloat(uint32_t varType)
+ {
+ ASMJIT_ASSERT(varType < kX86VarTypeCount);
+ return !!(x86VarInfo[varType].getFlags() & (kX86VarFlagSP | kX86VarFlagDP));
+ }
+};
+
+//! @}
+
+} // AsmJit namespace
+
+// [Api-End]
+#include "../core/apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_X86_X86UTIL_H
+
--- a/src/in_2sf/desmume/utils/dlditool.cpp
+++ b/src/in_2sf/desmume/utils/dlditool.cpp
@@ -62,46 +62,41 @@
#include "pstdint.h"
#ifndef _MSC_VER
-//#include <stdint.h>
-#include <unistd.h>
-#include <sys/param.h>
+# include <unistd.h>
+# include <sys/param.h>
#else
-//typedef int int32_t;
-#define MAXPATHLEN 1024
+#define MAXPATHLEN 1024
#endif
#include <sys/stat.h>
namespace DLDI
{
-
-//#ifndef bool
-// typedef enum {false = 0, true = !0} bool;
-//#endif
typedef int32_t addr_t;
typedef unsigned char data_t;
-#define FEATURE_MEDIUM_CANREAD 0x00000001
-#define FEATURE_MEDIUM_CANWRITE 0x00000002
-#define FEATURE_SLOT_GBA 0x00000010
-#define FEATURE_SLOT_NDS 0x00000020
+#define FEATURE_MEDIUM_CANREAD 0x00000001
+#define FEATURE_MEDIUM_CANWRITE 0x00000002
+#define FEATURE_SLOT_GBA 0x00000010
+#define FEATURE_SLOT_NDS 0x00000020
#define MAGIC_TOKEN 0xBF8DA5ED
-#define FIX_ALL 0x01
-#define FIX_GLUE 0x02
-#define FIX_GOT 0x04
-#define FIX_BSS 0x08
+#define FIX_ALL 0x01
+#define FIX_GLUE 0x02
+#define FIX_GOT 0x04
+#define FIX_BSS 0x08
#define DLDI_VERSION 1
#define EXIT_NO_DLDI_SECTION 2
-enum DldiOffsets {
- DO_magicString = 0x00, // "\xED\xA5\x8D\xBF Chishm"
- DO_magicToken = 0x00, // 0xBF8DA5ED
- DO_magicShortString = 0x04, // " Chishm"
+enum DldiOffsets
+{
+ DO_magicString = 0x00, // "\xED\xA5\x8D\xBF Chishm"
+ DO_magicToken = 0x00, // 0xBF8DA5ED
+ DO_magicShortString = 0x04, // " Chishm"
DO_version = 0x0C,
DO_driverSize = 0x0D,
DO_fixSections = 0x0E,
@@ -109,14 +104,14 @@
DO_friendlyName = 0x10,
- DO_text_start = 0x40, // Data start
- DO_data_end = 0x44, // Data end
- DO_glue_start = 0x48, // Interworking glue start -- Needs address fixing
- DO_glue_end = 0x4C, // Interworking glue end
- DO_got_start = 0x50, // GOT start -- Needs address fixing
- DO_got_end = 0x54, // GOT end
- DO_bss_start = 0x58, // bss start -- Needs setting to zero
- DO_bss_end = 0x5C, // bss end
+ DO_text_start = 0x40, // Data start
+ DO_data_end = 0x44, // Data end
+ DO_glue_start = 0x48, // Interworking glue start -- Needs address fixing
+ DO_glue_end = 0x4C, // Interworking glue end
+ DO_got_start = 0x50, // GOT start -- Needs address fixing
+ DO_got_end = 0x54, // GOT end
+ DO_bss_start = 0x58, // bss start -- Needs setting to zero
+ DO_bss_end = 0x5C, // bss end
// IO_INTERFACE data
DO_ioType = 0x60,
@@ -133,385 +128,170 @@
const data_t dldiMagicString[] = "\xED\xA5\x8D\xBF Chishm";
const char dldiFileExtension[] = ".dldi";
-
-void printUsage (char* programName) {
- printf ("Usage:\n");
- printf ("%s <dldi> <app>\n", programName);
- printf (" <dldi> the dldi patch file to apply\n");
- printf (" <app> the application binary to apply the patch to\n");
- return;
-}
-
-addr_t readAddr (data_t *mem, addr_t offset) {
- return (addr_t)(
- (mem[offset + 0] << 0) |
- (mem[offset + 1] << 8) |
- (mem[offset + 2] << 16) |
- (mem[offset + 3] << 24)
- );
-}
-
-void writeAddr (data_t *mem, addr_t offset, addr_t value) {
- mem[offset + 0] = (data_t)(value >> 0);
- mem[offset + 1] = (data_t)(value >> 8);
- mem[offset + 2] = (data_t)(value >> 16);
- mem[offset + 3] = (data_t)(value >> 24);
-}
-
-int stringCaseInsensitiveCompare (const char *str1, const char *str2) {
- while (tolower(*str1) == tolower(*str2)) {
- if (*str1 == '\0') {
+addr_t readAddr(data_t *mem, addr_t offset)
+{
+ return static_cast<addr_t>(mem[offset + 0] | (mem[offset + 1] << 8) | (mem[offset + 2] << 16) | (mem[offset + 3] << 24));
+}
+
+void writeAddr(data_t *mem, addr_t offset, addr_t value)
+{
+ mem[offset + 0] = static_cast<data_t>(value);
+ mem[offset + 1] = static_cast<data_t>(value >> 8);
+ mem[offset + 2] = static_cast<data_t>(value >> 16);
+ mem[offset + 3] = static_cast<data_t>(value >> 24);
+}
+
+int stringCaseInsensitiveCompare(const char *str1, const char *str2)
+{
+ while (tolower(*str1) == tolower(*str2))
+ {
+ if (!*str1)
return 0;
+ ++str1;
+ ++str2;
+ }
+ return tolower(*str1) - tolower(*str2);
+}
+
+bool stringEndsWith(const char *str, const char *end)
+{
+ if (strlen(str) < strlen(end))
+ return false;
+ const char *strEnd = &str[strlen (str) - strlen(end)];
+ return !stringCaseInsensitiveCompare(strEnd, end);
+}
+
+bool stringStartsWith(const char *str, const char *start)
+{
+ return strstr(str, start) == str;
+}
+
+addr_t quickFind(const data_t *data, const data_t *search, size_t dataLen, size_t searchLen)
+{
+ const int32_t *dataChunk = reinterpret_cast<const int32_t *>(data);
+ int searchChunk = reinterpret_cast<const int32_t *>(search)[0];
+ addr_t dataChunkEnd = static_cast<addr_t>(dataLen / sizeof(int32_t));
+
+ for (addr_t i = 0; i < dataChunkEnd; ++i)
+ {
+ if (dataChunk[i] == searchChunk)
+ {
+ if (i * sizeof(int32_t) + searchLen > dataLen)
+ return -1;
+ if (!memcmp(&data[i * sizeof(int32_t)], search, searchLen))
+ return i * sizeof(int32_t);
}
- str1++;
- str2++;
- }
- return tolower(*str1) - tolower(*str2);
-}
-
-bool stringEndsWith (const char *str, const char *end) {
- const char* strEnd;
- if (strlen (str) < strlen(end)) {
- return false;
- }
- strEnd = &str[strlen (str) - strlen(end)];
- return stringCaseInsensitiveCompare (strEnd, end) == 0;
-}
-
-bool stringStartsWith (const char *str, const char *start) {
- return strstr (str, start) == str;
-}
-
-addr_t quickFind (const data_t* data, const data_t* search, size_t dataLen, size_t searchLen) {
- const int32_t* dataChunk = (const int32_t*) data;
- int searchChunk = ((const int32_t*)search)[0];
- addr_t i;
- addr_t dataChunkEnd = (addr_t)(dataLen / sizeof(int32_t));
-
- for ( i = 0; i < dataChunkEnd; i++) {
- if (dataChunk[i] == searchChunk) {
- if ((i*sizeof(int32_t) + searchLen) > dataLen) {
- return -1;
- }
- if (memcmp (&data[i*sizeof(int32_t)], search, searchLen) == 0) {
- return i*sizeof(int32_t);
- }
- }
}
return -1;
}
-FILE *openDLDIFile(const char *argv0, char *dldiFileName ) {
-
-
- FILE *dldiFile;
- char *dldiPATH;
- char appPath[MAXPATHLEN];
- char appName[MAXPATHLEN];
- char appPathName[MAXPATHLEN];
-
- char *ptr, *lastSlash;
- struct stat buf;
-
+FILE *openDLDIFile(const char *argv0, char *dldiFileName )
+{
// add .dldi extension to filename
- if (!stringEndsWith (dldiFileName, dldiFileExtension)) {
- strcat (dldiFileName, dldiFileExtension);
- }
-
- printf ("Trying \"%s\"\n", dldiFileName);
+ if (!stringEndsWith(dldiFileName, dldiFileExtension))
+ strcat(dldiFileName, dldiFileExtension);
+
+ printf("Trying \"%s\"\n", dldiFileName);
// try opening from current directory
- dldiFile = fopen(dldiFileName,"rb");
-
- if ( NULL != dldiFile ) return dldiFile;
+ FILE *dldiFile = fopen(dldiFileName, "rb");
+
+ if (dldiFile)
+ return dldiFile;
// check if the filename has a path component
// check both slash varieties, win32 understands both
// if we have a directory separator don't bother with search paths
- if ( NULL != strstr(dldiFileName,"\\") ) return NULL;
- if ( NULL != strstr(dldiFileName,"/") ) return NULL;
+ if (strstr(dldiFileName, "\\"))
+ return nullptr;
+ if (strstr(dldiFileName ,"/"))
+ return nullptr;
// check for DLDIPATH in environment
- dldiPATH = getenv("DLDIPATH");
-
-
- if ( NULL != dldiPATH ) {
- strcpy(appPath,dldiPATH);
- if ( appPath[strlen(appPath)] != '\\' && appPath[strlen(appPath)] != '/' )
- strcat(appPath,"/");
- strcat ( appPath, dldiFileName );
-
- printf ("Trying \"%s\"\n", appPath);
+ char *dldiPATH = getenv("DLDIPATH");
+
+ char appPath[MAXPATHLEN];
+ if (dldiPATH)
+ {
+ strcpy(appPath, dldiPATH);
+ if (appPath[strlen(appPath)] != '\\' && appPath[strlen(appPath)] != '/')
+ strcat(appPath, "/");
+ strcat(appPath, dldiFileName);
+
+ printf("Trying \"%s\"\n", appPath);
dldiFile = fopen(appPath,"rb");
- if ( NULL != dldiFile ) return dldiFile;
-
- }
-
-
- lastSlash = NULL;
- ptr = const_cast<char *>(argv0);
-
- while ( *(ptr++) != 0 ) {
- if ( *ptr == '\\' || * ptr == '/' )
+ if (dldiFile)
+ return dldiFile;
+ }
+
+ char *lastSlash = nullptr;
+ char *ptr = const_cast<char *>(argv0);
+
+ while (*(ptr++))
+ if (*ptr == '\\' || * ptr == '/')
lastSlash = ptr;
- }
-
- if ( NULL != lastSlash ) {
+
+ char appName[MAXPATHLEN];
+ char appPathName[MAXPATHLEN];
+ if (lastSlash)
+ {
*(lastSlash++) = '\0';
strcpy(appPath, argv0);
strcpy(appName, lastSlash);
strcat(appPath, "/");
- } else {
+ }
+ else
+ {
strcpy(appPath, "");
strcpy(appName, argv0);
}
-
// finally try in the application path
// if argv0 contains a directory separator we have a path component
- if ( NULL == strstr(appPath,"\\") && NULL == strstr(appPath,"/") ) {
-
+ if (!strstr(appPath,"\\") && !strstr(appPath,"/"))
+ {
// no path in argv0 so search system path
char *sysPATH = getenv("PATH");
- char *nextPATH;
char *thisPATH = sysPATH;
- printf("Searching system path\n%s\n",sysPATH);
-
- while(1) {
- nextPATH = strstr(thisPATH, ":" ); // find next PATH separator
-
- if ( NULL != nextPATH )
+ printf("Searching system path\n%s\n", sysPATH);
+
+ while (1)
+ {
+ char *nextPATH = strstr(thisPATH, ":" ); // find next PATH separator
+
+ if (nextPATH)
*(nextPATH++) = '\0'; // terminate string, point to next component
- strcpy(appPath,thisPATH);
- strcat(appPath,"/");
- strcpy(appPathName,appPath);
- strcat(appPathName,appName); // add application name
-
- if ( stat(appPathName,&buf) == 0 ) // if it exists we found the path
+ strcpy(appPath, thisPATH);
+ strcat(appPath, "/");
+ strcpy(appPathName, appPath);
+ strcat(appPathName, appName); // add application name
+
+ struct stat buf;
+ if (!stat(appPathName, &buf)) // if it exists we found the path
break;
thisPATH = nextPATH;
- strcpy(appPath,""); // empty path
- if ( thisPATH == NULL) break;
+ strcpy(appPath, "");// empty path
+ if (!thisPATH)
+ break;
}
}
- strcat(appPath,"dldi/"); // add dldi folder
- strcat(appPath,dldiFileName); // add dldi filename to path
- printf ("Trying \"%s\"\n", appPath);
-
- return fopen(appPath,"rb"); // no more places to check, just return this handle
-}
-
-//int main(int argc, char* argv[])
-//{
-//
-// char *dldiFileName = NULL;
-// char *appFileName = NULL;
-//
-// addr_t memOffset; // Offset of DLDI after the file is loaded into memory
-// addr_t patchOffset; // Position of patch destination in the file
-// addr_t relocationOffset; // Value added to all offsets within the patch to fix it properly
-// addr_t ddmemOffset; // Original offset used in the DLDI file
-// addr_t ddmemStart; // Start of range that offsets can be in the DLDI file
-// addr_t ddmemEnd; // End of range that offsets can be in the DLDI file
-// addr_t ddmemSize; // Size of range that offsets can be in the DLDI file
-//
-// addr_t addrIter;
-//
-// FILE* dldiFile;
-// FILE* appFile;
-//
-// data_t *pDH;
-// data_t *pAH;
-//
-// data_t *appFileData = NULL;
-// size_t appFileSize = 0;
-// data_t *dldiFileData = NULL;
-// size_t dldiFileSize = 0;
-//
-// int i;
-//
-// printf ("Dynamically Linked Disk Interface patch tool " VERSION " by Michael Chisholm (Chishm)\n\n");
-//
-// for (i = 1; i < argc; i++) {
-// if (dldiFileName == NULL) {
-// dldiFileName = (char*) malloc (strlen (argv[i]) + 1 + sizeof(dldiFileExtension));
-// if (!dldiFileName) {
-// return EXIT_FAILURE;
-// }
-// strcpy (dldiFileName, argv[i]);
-// } else if (appFileName == NULL) {
-// appFileName = (char*) malloc (strlen (argv[i]) + 1);
-// if (!appFileName) {
-// return EXIT_FAILURE;
-// }
-// strcpy (appFileName, argv[i]);
-// } else {
-// printUsage (argv[0]);
-// return EXIT_FAILURE;
-// }
-// }
-//
-// if ((dldiFileName == NULL) || (appFileName == NULL)) {
-// printUsage (argv[0]);
-// return EXIT_FAILURE;
-// }
-//
-// if (!(dldiFile = openDLDIFile(argv[0],dldiFileName))) {
-// printf ("Cannot open \"%s\" - %s\n", dldiFileName, strerror(errno));
-// return EXIT_FAILURE;
-// }
-//
-// if (!(appFile = fopen (appFileName, "rb+"))) {
-// printf ("Cannot open \"%s\" - %s\n", appFileName, strerror(errno));
-// return EXIT_FAILURE;
-// }
-//
-// // Load the app file and the DLDI patch file
-// fseek (appFile, 0, SEEK_END);
-// appFileSize = ftell(appFile);
-// appFileData = (data_t*) malloc (appFileSize);
-// fseek (appFile, 0, SEEK_SET);
-//
-// fseek (dldiFile, 0, SEEK_END);
-// dldiFileSize = ftell(dldiFile);
-// dldiFileData = (data_t*) malloc (dldiFileSize);
-// fseek (dldiFile, 0, SEEK_SET);
-//
-// if (!appFileData || !dldiFileData) {
-// fclose (appFile);
-// fclose (dldiFile);
-// if (appFileData) free (appFileData);
-// if (dldiFileData) free (dldiFileData);
-// printf ("Out of memory\n");
-// return EXIT_FAILURE;
-// }
-//
-// fread (appFileData, 1, appFileSize, appFile);
-// fread (dldiFileData, 1, dldiFileSize, dldiFile);
-// fclose (dldiFile);
-//
-// // Find the DSDI reserved space in the file
-// patchOffset = quickFind (appFileData, dldiMagicString, appFileSize, sizeof(dldiMagicString)/sizeof(char));
-//
-// if (patchOffset < 0) {
-// printf ("%s does not have a DLDI section\n", appFileName);
-// return EXIT_NO_DLDI_SECTION;
-// }
-//
-// pDH = dldiFileData;
-// pAH = &appFileData[patchOffset];
-//
-// // Make sure the DLDI file is valid and usable
-// if (strcmp ((char*)dldiMagicString, (char*)&pDH[DO_magicString]) != 0) {
-// printf ("Invalid DLDI file\n");
-// return EXIT_FAILURE;
-// }
-// if (pDH[DO_version] != DLDI_VERSION) {
-// printf ("Incorrect DLDI file version. Expected %d, found %d.\n", DLDI_VERSION, pDH[DO_version]);
-// return EXIT_FAILURE;
-// }
-// if (pDH[DO_driverSize] > pAH[DO_allocatedSpace]) {
-// printf ("Not enough space for patch. Available %d bytes, need %d bytes\n", ( 1 << pAH[DO_allocatedSpace]), ( 1 << pDH[DO_driverSize]) );
-// return EXIT_FAILURE;
-// }
-//
-// memOffset = readAddr (pAH, DO_text_start);
-// if (memOffset == 0) {
-// memOffset = readAddr (pAH, DO_startup) - DO_code;
-// }
-// ddmemOffset = readAddr (pDH, DO_text_start);
-// relocationOffset = memOffset - ddmemOffset;
-//
-// printf ("Old driver: %s\n", &pAH[DO_friendlyName]);
-// printf ("New driver: %s\n", &pDH[DO_friendlyName]);
-// printf ("\n");
-// printf ("Position in file: 0x%08X\n", patchOffset);
-// printf ("Position in memory: 0x%08X\n", memOffset);
-// printf ("Patch base address: 0x%08X\n", ddmemOffset);
-// printf ("Relocation offset: 0x%08X\n", relocationOffset);
-// printf ("\n");
-//
-// ddmemStart = readAddr (pDH, DO_text_start);
-// ddmemSize = (1 << pDH[DO_driverSize]);
-// ddmemEnd = ddmemStart + ddmemSize;
-//
-// // Remember how much space is actually reserved
-// pDH[DO_allocatedSpace] = pAH[DO_allocatedSpace];
-// // Copy the DLDI patch into the application
-// memcpy (pAH, pDH, dldiFileSize);
-//
-// // Fix the section pointers in the header
-// writeAddr (pAH, DO_text_start, readAddr (pAH, DO_text_start) + relocationOffset);
-// writeAddr (pAH, DO_data_end, readAddr (pAH, DO_data_end) + relocationOffset);
-// writeAddr (pAH, DO_glue_start, readAddr (pAH, DO_glue_start) + relocationOffset);
-// writeAddr (pAH, DO_glue_end, readAddr (pAH, DO_glue_end) + relocationOffset);
-// writeAddr (pAH, DO_got_start, readAddr (pAH, DO_got_start) + relocationOffset);
-// writeAddr (pAH, DO_got_end, readAddr (pAH, DO_got_end) + relocationOffset);
-// writeAddr (pAH, DO_bss_start, readAddr (pAH, DO_bss_start) + relocationOffset);
-// writeAddr (pAH, DO_bss_end, readAddr (pAH, DO_bss_end) + relocationOffset);
-// // Fix the function pointers in the header
-// writeAddr (pAH, DO_startup, readAddr (pAH, DO_startup) + relocationOffset);
-// writeAddr (pAH, DO_isInserted, readAddr (pAH, DO_isInserted) + relocationOffset);
-// writeAddr (pAH, DO_readSectors, readAddr (pAH, DO_readSectors) + relocationOffset);
-// writeAddr (pAH, DO_writeSectors, readAddr (pAH, DO_writeSectors) + relocationOffset);
-// writeAddr (pAH, DO_clearStatus, readAddr (pAH, DO_clearStatus) + relocationOffset);
-// writeAddr (pAH, DO_shutdown, readAddr (pAH, DO_shutdown) + relocationOffset);
-//
-// if (pDH[DO_fixSections] & FIX_ALL) {
-// // Search through and fix pointers within the data section of the file
-// for (addrIter = (readAddr(pDH, DO_text_start) - ddmemStart); addrIter < (readAddr(pDH, DO_data_end) - ddmemStart); addrIter++) {
-// if ((ddmemStart <= readAddr(pAH, addrIter)) && (readAddr(pAH, addrIter) < ddmemEnd)) {
-// writeAddr (pAH, addrIter, readAddr(pAH, addrIter) + relocationOffset);
-// }
-// }
-// }
-//
-// if (pDH[DO_fixSections] & FIX_GLUE) {
-// // Search through and fix pointers within the glue section of the file
-// for (addrIter = (readAddr(pDH, DO_glue_start) - ddmemStart); addrIter < (readAddr(pDH, DO_glue_end) - ddmemStart); addrIter++) {
-// if ((ddmemStart <= readAddr(pAH, addrIter)) && (readAddr(pAH, addrIter) < ddmemEnd)) {
-// writeAddr (pAH, addrIter, readAddr(pAH, addrIter) + relocationOffset);
-// }
-// }
-// }
-//
-// if (pDH[DO_fixSections] & FIX_GOT) {
-// // Search through and fix pointers within the Global Offset Table section of the file
-// for (addrIter = (readAddr(pDH, DO_got_start) - ddmemStart); addrIter < (readAddr(pDH, DO_got_end) - ddmemStart); addrIter++) {
-// if ((ddmemStart <= readAddr(pAH, addrIter)) && (readAddr(pAH, addrIter) < ddmemEnd)) {
-// writeAddr (pAH, addrIter, readAddr(pAH, addrIter) + relocationOffset);
-// }
-// }
-// }
-//
-// if (pDH[DO_fixSections] & FIX_BSS) {
-// // Initialise the BSS to 0
-// memset (&pAH[readAddr(pDH, DO_bss_start) - ddmemStart] , 0, readAddr(pDH, DO_bss_end) - readAddr(pDH, DO_bss_start));
-// }
-//
-// // Write the patch back to the file
-// fseek (appFile, patchOffset, SEEK_SET);
-// fwrite (pAH, 1, ddmemSize, appFile);
-// fclose (appFile);
-//
-// free (appFileData);
-// free (dldiFileData);
-//
-// printf ("Patched successfully\n");
-//
-// return EXIT_SUCCESS;
-//}
+ strcat(appPath, "dldi/"); // add dldi folder
+ strcat(appPath, dldiFileName); // add dldi filename to path
+ printf("Trying \"%s\"\n", appPath);
+
+ return fopen(appPath, "rb"); // no more places to check, just return this handle
+}
// Source File: mpcf.dldi
// Time: 6/14/2010 9:38 PM
// Orig. Offset: 0 / 0x00000000
// Length: 1876 / 0x00000754 (bytes)
-data_t mpcf_dldi[1876] =
+data_t mpcf_dldi[] =
{
0xED, 0xA5, 0x8D, 0xBF, 0x20, 0x43, 0x68, 0x69, 0x73, 0x68, 0x6D, 0x00, 0x01, 0x0B, 0x0C, 0x00,
0x47, 0x42, 0x41, 0x20, 0x4D, 0x6F, 0x76, 0x69, 0x65, 0x20, 0x50, 0x6C, 0x61, 0x79, 0x65, 0x72,
@@ -633,24 +413,25 @@
0x00, 0x00, 0x00, 0x00,
}; //unsigned char mpcf_dldi[1876]
-bool tryPatch(void* data, size_t size)
+bool tryPatch(void *data, size_t size)
{
// Find the DSDI reserved space in the file
- addr_t patchOffset = quickFind ((data_t*)data, dldiMagicString, size, sizeof(dldiMagicString)/sizeof(char));
-
- //no DLDI section
+ addr_t patchOffset = quickFind(static_cast<data_t *>(data), dldiMagicString, size, sizeof(dldiMagicString) / sizeof(char));
+
+ // no DLDI section
if (patchOffset < 0)
return false;
data_t *pDH = mpcf_dldi;
- data_t *pAH = (data_t*)data + patchOffset;
-
- if (pDH[DO_driverSize] > pAH[DO_allocatedSpace]) {
- printf ("Not enough space for patch. Available %d bytes, need %d bytes\n", ( 1 << pAH[DO_allocatedSpace]), ( 1 << pDH[DO_driverSize]) );
+ data_t *pAH = static_cast<data_t *>(data) + patchOffset;
+
+ if (pDH[DO_driverSize] > pAH[DO_allocatedSpace])
+ {
+ printf("Not enough space for patch. Available %d bytes, need %d bytes\n", 1 << pAH[DO_allocatedSpace], 1 << pDH[DO_driverSize]);
return false;
}
- if(memcmp(&pAH[DO_friendlyName],"Default (No interface)",22))
+ if (memcmp(&pAH[DO_friendlyName], "Default (No interface)", 22))
{
printf("Would have been a candidate for auto-patch DLDI, but there was already a patch installed.");
return false;
@@ -658,90 +439,78 @@
//----should be able to patch OK-----
- addr_t memOffset; // Offset of DLDI after the file is loaded into memory
- addr_t relocationOffset; // Value added to all offsets within the patch to fix it properly
- addr_t ddmemOffset; // Original offset used in the DLDI file
- addr_t ddmemStart; // Start of range that offsets can be in the DLDI file
- addr_t ddmemEnd; // End of range that offsets can be in the DLDI file
- addr_t ddmemSize; // Size of range that offsets can be in the DLDI file
+ addr_t memOffset; // Offset of DLDI after the file is loaded into memory
+ addr_t relocationOffset; // Value added to all offsets within the patch to fix it properly
+ addr_t ddmemOffset; // Original offset used in the DLDI file
+ addr_t ddmemStart; // Start of range that offsets can be in the DLDI file
+ addr_t ddmemEnd; // End of range that offsets can be in the DLDI file
+ addr_t ddmemSize; // Size of range that offsets can be in the DLDI file
addr_t addrIter;
-
- memOffset = readAddr (pAH, DO_text_start);
- if (memOffset == 0) {
- memOffset = readAddr (pAH, DO_startup) - DO_code;
- }
- ddmemOffset = readAddr (pDH, DO_text_start);
+ memOffset = readAddr(pAH, DO_text_start);
+ if (!memOffset)
+ memOffset = readAddr(pAH, DO_startup) - DO_code;
+ ddmemOffset = readAddr(pDH, DO_text_start);
relocationOffset = memOffset - ddmemOffset;
- printf ("AUTO-PATCHING DLDI to MPCF! Lucky you!\n\n");
- printf ("Old driver: %s\n", &pAH[DO_friendlyName]);
- printf ("New driver: %s\n", &pDH[DO_friendlyName]);
- printf ("\n");
- printf ("Position in file: 0x%08X\n", patchOffset);
- printf ("Position in memory: 0x%08X\n", memOffset);
- printf ("Patch base address: 0x%08X\n", ddmemOffset);
- printf ("Relocation offset: 0x%08X\n", relocationOffset);
- printf ("\n");
-
- ddmemStart = readAddr (pDH, DO_text_start);
- ddmemSize = (1 << pDH[DO_driverSize]);
+ printf("AUTO-PATCHING DLDI to MPCF! Lucky you!\n\n");
+ printf("Old driver: %s\n", &pAH[DO_friendlyName]);
+ printf("New driver: %s\n", &pDH[DO_friendlyName]);
+ printf("\n");
+ printf("Position in file: 0x%08X\n", patchOffset);
+ printf("Position in memory: 0x%08X\n", memOffset);
+ printf("Patch base address: 0x%08X\n", ddmemOffset);
+ printf("Relocation offset: 0x%08X\n", relocationOffset);
+ printf("\n");
+
+ ddmemStart = readAddr(pDH, DO_text_start);
+ ddmemSize = 1 << pDH[DO_driverSize];
ddmemEnd = ddmemStart + ddmemSize;
// Remember how much space is actually reserved
pDH[DO_allocatedSpace] = pAH[DO_allocatedSpace];
// Copy the DLDI patch into the application
- memcpy (pAH, pDH, sizeof(mpcf_dldi));
+ memcpy(pAH, pDH, sizeof(mpcf_dldi));
// Fix the section pointers in the header
- writeAddr (pAH, DO_text_start, readAddr (pAH, DO_text_start) + relocationOffset);
- writeAddr (pAH, DO_data_end, readAddr (pAH, DO_data_end) + relocationOffset);
- writeAddr (pAH, DO_glue_start, readAddr (pAH, DO_glue_start) + relocationOffset);
- writeAddr (pAH, DO_glue_end, readAddr (pAH, DO_glue_end) + relocationOffset);
- writeAddr (pAH, DO_got_start, readAddr (pAH, DO_got_start) + relocationOffset);
- writeAddr (pAH, DO_got_end, readAddr (pAH, DO_got_end) + relocationOffset);
- writeAddr (pAH, DO_bss_start, readAddr (pAH, DO_bss_start) + relocationOffset);
- writeAddr (pAH, DO_bss_end, readAddr (pAH, DO_bss_end) + relocationOffset);
+ writeAddr(pAH, DO_text_start, readAddr(pAH, DO_text_start) + relocationOffset);
+ writeAddr(pAH, DO_data_end, readAddr(pAH, DO_data_end) + relocationOffset);
+ writeAddr(pAH, DO_glue_start, readAddr(pAH, DO_glue_start) + relocationOffset);
+ writeAddr(pAH, DO_glue_end, readAddr(pAH, DO_glue_end) + relocationOffset);
+ writeAddr(pAH, DO_got_start, readAddr(pAH, DO_got_start) + relocationOffset);
+ writeAddr(pAH, DO_got_end, readAddr(pAH, DO_got_end) + relocationOffset);
+ writeAddr(pAH, DO_bss_start, readAddr(pAH, DO_bss_start) + relocationOffset);
+ writeAddr(pAH, DO_bss_end, readAddr(pAH, DO_bss_end) + relocationOffset);
// Fix the function pointers in the header
- writeAddr (pAH, DO_startup, readAddr (pAH, DO_startup) + relocationOffset);
- writeAddr (pAH, DO_isInserted, readAddr (pAH, DO_isInserted) + relocationOffset);
- writeAddr (pAH, DO_readSectors, readAddr (pAH, DO_readSectors) + relocationOffset);
- writeAddr (pAH, DO_writeSectors, readAddr (pAH, DO_writeSectors) + relocationOffset);
- writeAddr (pAH, DO_clearStatus, readAddr (pAH, DO_clearStatus) + relocationOffset);
- writeAddr (pAH, DO_shutdown, readAddr (pAH, DO_shutdown) + relocationOffset);
-
- if (pDH[DO_fixSections] & FIX_ALL) {
+ writeAddr(pAH, DO_startup, readAddr(pAH, DO_startup) + relocationOffset);
+ writeAddr(pAH, DO_isInserted, readAddr(pAH, DO_isInserted) + relocationOffset);
+ writeAddr(pAH, DO_readSectors, readAddr(pAH, DO_readSectors) + relocationOffset);
+ writeAddr(pAH, DO_writeSectors, readAddr(pAH, DO_writeSectors) + relocationOffset);
+ writeAddr(pAH, DO_clearStatus, readAddr(pAH, DO_clearStatus) + relocationOffset);
+ writeAddr(pAH, DO_shutdown, readAddr(pAH, DO_shutdown) + relocationOffset);
+
+ if (pDH[DO_fixSections] & FIX_ALL)
// Search through and fix pointers within the data section of the file
- for (addrIter = (readAddr(pDH, DO_text_start) - ddmemStart); addrIter < (readAddr(pDH, DO_data_end) - ddmemStart); addrIter++) {
- if ((ddmemStart <= readAddr(pAH, addrIter)) && (readAddr(pAH, addrIter) < ddmemEnd)) {
- writeAddr (pAH, addrIter, readAddr(pAH, addrIter) + relocationOffset);
- }
- }
- }
-
- if (pDH[DO_fixSections] & FIX_GLUE) {
+ for (addrIter = readAddr(pDH, DO_text_start) - ddmemStart; addrIter < readAddr(pDH, DO_data_end) - ddmemStart; ++addrIter)
+ if (ddmemStart <= readAddr(pAH, addrIter) && readAddr(pAH, addrIter) < ddmemEnd)
+ writeAddr(pAH, addrIter, readAddr(pAH, addrIter) + relocationOffset);
+
+ if (pDH[DO_fixSections] & FIX_GLUE)
// Search through and fix pointers within the glue section of the file
- for (addrIter = (readAddr(pDH, DO_glue_start) - ddmemStart); addrIter < (readAddr(pDH, DO_glue_end) - ddmemStart); addrIter++) {
- if ((ddmemStart <= readAddr(pAH, addrIter)) && (readAddr(pAH, addrIter) < ddmemEnd)) {
- writeAddr (pAH, addrIter, readAddr(pAH, addrIter) + relocationOffset);
- }
- }
- }
-
- if (pDH[DO_fixSections] & FIX_GOT) {
+ for (addrIter = readAddr(pDH, DO_glue_start) - ddmemStart; addrIter < readAddr(pDH, DO_glue_end) - ddmemStart; ++addrIter)
+ if (ddmemStart <= readAddr(pAH, addrIter) && readAddr(pAH, addrIter) < ddmemEnd)
+ writeAddr(pAH, addrIter, readAddr(pAH, addrIter) + relocationOffset);
+
+ if (pDH[DO_fixSections] & FIX_GOT)
// Search through and fix pointers within the Global Offset Table section of the file
- for (addrIter = (readAddr(pDH, DO_got_start) - ddmemStart); addrIter < (readAddr(pDH, DO_got_end) - ddmemStart); addrIter++) {
- if ((ddmemStart <= readAddr(pAH, addrIter)) && (readAddr(pAH, addrIter) < ddmemEnd)) {
- writeAddr (pAH, addrIter, readAddr(pAH, addrIter) + relocationOffset);
- }
- }
- }
-
- if (pDH[DO_fixSections] & FIX_BSS) {
+ for (addrIter = readAddr(pDH, DO_got_start) - ddmemStart; addrIter < readAddr(pDH, DO_got_end) - ddmemStart; ++addrIter)
+ if (ddmemStart <= readAddr(pAH, addrIter) && readAddr(pAH, addrIter) < ddmemEnd)
+ writeAddr(pAH, addrIter, readAddr(pAH, addrIter) + relocationOffset);
+
+ if (pDH[DO_fixSections] & FIX_BSS)
// Initialise the BSS to 0
- memset (&pAH[readAddr(pDH, DO_bss_start) - ddmemStart] , 0, readAddr(pDH, DO_bss_end) - readAddr(pDH, DO_bss_start));
- }
+ memset(&pAH[readAddr(pDH, DO_bss_start) - ddmemStart] , 0, readAddr(pDH, DO_bss_end) - readAddr(pDH, DO_bss_start));
return true;
}
--- a/src/in_2sf/desmume/utils/xstring.cpp
+++ b/src/in_2sf/desmume/utils/xstring.cpp
@@ -23,725 +23,26 @@
#include "xstring.h"
-//a vc-style substring operation (very kind and lenient)
-/*std::string strsub(const std::string& str, int pos, int len) {
- int strlen = str.size();
+std::vector<std::string> tokenize_str(const std::string &str, const std::string &delims = ", \t")
+{
+ // Skip delims at beginning, find start of first token
+ auto lastPos = str.find_first_not_of(delims, 0);
+ // Find next delimiter @ end of token
+ auto pos = str.find_first_of(delims, lastPos);
- if(strlen==0) return str; //empty strings always return empty strings
- if(pos>=strlen) return str; //if you start past the end of the string, return the entire string. this is unusual, but there you have it
+ // output vector
+ std::vector<std::string> tokens;
- //clipping
- if(pos<0) {
- len += pos;
- pos = 0;
+ while (pos != std::string::npos || lastPos != std::string::npos)
+ {
+ // Found a token, add it to the vector.
+ tokens.push_back(str.substr(lastPos, pos - lastPos));
+ // Skip delims. Note the "not_of". this is beginning of token
+ lastPos = str.find_first_not_of(delims, pos);
+ // Find next delimiter at end of token.
+ pos = str.find_first_of(delims, lastPos);
}
- if (pos+len>=strlen)
- len=strlen-pos+1;
-
- //return str.str().substr(pos,len);
- return str.substr(pos,len);
-}*/
-
-//std::string strmid(const std::string& str, int pos, int len) { return strsub(str,pos,len); }
-//std::string strleft(const std::string& str, int len) { return strsub(str,0,len); }
-//std::string strright(const std::string& str, int len) { return len ? strsub(str,str.size()-len,len) : ""; }
-/*std::string toupper(const std::string& str)
-{
- std::string ret = str;
- for(uint32_t i=0;i<str.size();i++)
- ret[i] = toupper(ret[i]);
- return ret;
-}*/
-
-///Upper case routine. Returns number of characters modified
-/*int str_ucase(char *str) {
- uint32_t i=0,j=0;
-
- while (i < strlen(str)) {
- if ((str[i] >= 'a') && (str[i] <= 'z')) {
- str[i] &= ~0x20;
- j++;
- }
- i++;
- }
- return j;
-}*/
-
-
-///Lower case routine. Returns number of characters modified
-/*int str_lcase(char *str) {
- uint32_t i=0,j=0;
-
- while (i < strlen(str)) {
- if ((str[i] >= 'A') && (str[i] <= 'Z')) {
- str[i] |= 0x20;
- j++;
- }
- i++;
- }
- return j;
-}*/
-
-
-///White space-trimming routine
-
-///Removes whitespace from left side of string, depending on the flags set (See STRIP_x definitions in xstring.h)
-///Returns number of characters removed
-/*int str_ltrim(char *str, int flags) {
- uint32_t i=0;
-
- while (str[0]) {
- if ((str[0] != ' ') || (str[0] != '\t') || (str[0] != '\r') || (str[0] != '\n')) break;
-
- if ((flags & STRIP_SP) && (str[0] == ' ')) {
- i++;
- strcpy(str,str+1);
- }
- if ((flags & STRIP_TAB) && (str[0] == '\t')) {
- i++;
- strcpy(str,str+1);
- }
- if ((flags & STRIP_CR) && (str[0] == '\r')) {
- i++;
- strcpy(str,str+1);
- }
- if ((flags & STRIP_LF) && (str[0] == '\n')) {
- i++;
- strcpy(str,str+1);
- }
- }
- return i;
-}*/
-
-
-///White space-trimming routine
-
-///Removes whitespace from right side of string, depending on the flags set (See STRIP_x definitions in xstring.h)
-///Returns number of characters removed
-/*int str_rtrim(char *str, int flags) {
- uint32_t i=0;
-
- while (strlen(str)) {
- if ((str[strlen(str)-1] != ' ') ||
- (str[strlen(str)-1] != '\t') ||
- (str[strlen(str)-1] != '\r') ||
- (str[strlen(str)-1] != '\n')) break;
-
- if ((flags & STRIP_SP) && (str[0] == ' ')) {
- i++;
- str[strlen(str)-1] = 0;
- }
- if ((flags & STRIP_TAB) && (str[0] == '\t')) {
- i++;
- str[strlen(str)-1] = 0;
- }
- if ((flags & STRIP_CR) && (str[0] == '\r')) {
- i++;
- str[strlen(str)-1] = 0;
- }
- if ((flags & STRIP_LF) && (str[0] == '\n')) {
- i++;
- str[strlen(str)-1] = 0;
- }
- }
- return i;
-}*/
-
-
-///White space-stripping routine
-
-///Removes whitespace depending on the flags set (See STRIP_x definitions in xstring.h)
-///Returns number of characters removed, or -1 on error
-/*int str_strip(char *str, int flags) {
- uint32_t i=0,j=0;
- char *astr,chr;
-
- if (!strlen(str)) return -1;
- if (!(flags & (STRIP_SP|STRIP_TAB|STRIP_CR|STRIP_LF))) return -1;
- if (!(astr = (char*)malloc(strlen(str)+1))) return -1;
- while (i < strlen(str)) {
- chr = str[i++];
- if ((flags & STRIP_SP) && (chr == ' ')) chr = 0;
- if ((flags & STRIP_TAB) && (chr == '\t')) chr = 0;
- if ((flags & STRIP_CR) && (chr == '\r')) chr = 0;
- if ((flags & STRIP_LF) && (chr == '\n')) chr = 0;
-
- if (chr) astr[j++] = chr;
- }
- astr[j] = 0;
- strcpy(str,astr);
- free(astr);
- return j;
-}*/
-
-
-///Character replacement routine
-
-///Replaces all instances of 'search' with 'replace'
-///Returns number of characters modified
-/*int chr_replace(char *str, char search, char replace) {
- uint32_t i=0,j=0;
-
- while (i < strlen(str)) {
- if (str[i] == search) {
- str[i] = replace;
- j++;
- }
- i++;
- }
- return j;
-}*/
-
-
-///Sub-String replacement routine
-
-///Replaces all instances of 'search' with 'replace'
-///Returns number of sub-strings modified, or -1 on error
-/*int str_replace(char *str, char *search, char *replace) {
- uint32_t i=0,j=0;
- int searchlen,replacelen;
- char *astr;
-
- searchlen = strlen(search);
- replacelen = strlen(replace);
- if ((!strlen(str)) || (!searchlen)) return -1; //note: allow *replace to have a length of zero!
- if (!(astr = (char*)malloc(strlen(str)+1))) return -1;
- while (i < strlen(str)) {
- if (!strncmp(str+i,search,searchlen)) {
- if (replacelen) memcpy(astr+j,replace,replacelen);
- i += searchlen;
- j += replacelen;
- }
- else astr[j++] = str[i++];
- }
- astr[j] = 0;
- strcpy(str,astr);
- free(astr);
- return j;
-}*/
-
-/*static const struct Base64Table
-{
- Base64Table()
- {
- size_t a=0;
- for(a=0; a<256; ++a) data[a] = 0xFF; // mark everything as invalid by default
- // create value->ascii mapping
- a=0;
- for(unsigned char c='A'; c<='Z'; ++c) data[a++] = c; // 0..25
- for(unsigned char c='a'; c<='z'; ++c) data[a++] = c; // 26..51
- for(unsigned char c='0'; c<='9'; ++c) data[a++] = c; // 52..61
- data[62] = '+'; // 62
- data[63] = '/'; // 63
- // create ascii->value mapping (but due to overlap, write it to highbit region)
- for(a=0; a<64; ++a) data[data[a]^0x80] = a; //
- data[((unsigned char)'=') ^ 0x80] = 0;
- }
- unsigned char operator[] (size_t pos) const { return data[pos]; }
-private:
- unsigned char data[256];
-} Base64Table;*/
-
-/*std::string u32ToHexString(uint32_t val)
-{
- char temp[16];
- sprintf(temp,"%08X",val);
- return temp;
-}*/
-
-///Converts the provided data to a string in a standard, user-friendly, round-trippable format
-/*std::string BytesToString(const void* data, int len)
-{
- char temp[16];
- if(len==1) {
- sprintf(temp,"%d",*(const unsigned char*)data);
- return temp;
- } else if(len==2) {
- sprintf(temp,"%d",*(const unsigned short*)data);
- return temp;
- } else if(len==4) {
- sprintf(temp,"%d",*(const unsigned int*)data);
- return temp;
- }
-
- std::string ret;
- if(1) // use base64
- {
- const unsigned char* src = (const unsigned char*)data;
- ret = "base64:";
- for(int n; len > 0; len -= n)
- {
- unsigned char input[3] = {0,0,0};
- for(n=0; n<3 && n<len; ++n)
- input[n] = *src++;
- unsigned char output[4] =
- {
- Base64Table[ input[0] >> 2 ],
- Base64Table[ ((input[0] & 0x03) << 4) | (input[1] >> 4) ],
- n<2 ? '=' : Base64Table[ ((input[1] & 0x0F) << 2) | (input[2] >> 6) ],
- n<3 ? '=' : Base64Table[ input[2] & 0x3F ]
- };
- ret.append(output, output+4);
- }
- }
- else // use hex
- {
- ret.resize(len*2+2);
- ret[0] = '0';
- ret[1] = 'x';
- for(int i=0;i<len;i++)
- {
- int a = (((const unsigned char*)data)[i]>>4);
- int b = (((const unsigned char*)data)[i])&15;
- if(a>9) a += 'A'-10;
- else a += '0';
- if(b>9) b += 'A'-10;
- else b += '0';
- ret[2+i*2] = a;
- ret[2+i*2+1] = b;
- }
- }
- return ret;
-}*/
-
-///returns -1 if this is not a hex string
-/*int HexStringToBytesLength(const std::string& str)
-{
- if(str.size()>2 && str[0] == '0' && toupper(str[1]) == 'X')
- return str.size()/2-1;
- else return -1;
-}*/
-
-/*int Base64StringToBytesLength(const std::string& str)
-{
- if(str.size() < 7 || (str.size()-7) % 4 || str.substr(0,7) != "base64:") return -1;
-
- size_t c = ((str.size() - 7) / 4) * 3;
- if(str[str.size()-1] == '=') { --c;
- if(str[str.size()-2] == '=') --c; }
- return c;
-}*/
-
-///parses a string in the same format as BytesToString
-///returns true if success.
-/*bool StringToBytes(const std::string& str, void* data, int len)
-{
- if(str.substr(0,7) == "base64:")
- {
- // base64
- unsigned char* tgt = (unsigned char*)data;
- for(size_t pos = 7; pos < str.size() && len > 0; )
- {
- unsigned char input[4], converted[4];
- for(int i=0; i<4; ++i)
- {
- if(pos >= str.size() && i > 0) return false; // invalid data
- input[i] = str[pos++];
- if(input[i] & 0x80) return false; // illegal character
- converted[i] = Base64Table[input[i]^0x80];
- if(converted[i] & 0x80) return false; // illegal character
- }
- unsigned char outpacket[3] =
- {
- (converted[0] << 2) | (converted[1] >> 4),
- (converted[1] << 4) | (converted[2] >> 2),
- (converted[2] << 6) | (converted[3])
- };
- int outlen = (input[2] == '=') ? 1 : (input[3] == '=' ? 2 : 3);
- if(outlen > len) outlen = len;
- memcpy(tgt, outpacket, outlen);
- tgt += outlen;
- len -= outlen;
- }
- return true;
- }
- if(str.size()>2 && str[0] == '0' && toupper(str[1]) == 'X')
- {
- // hex
- int amt = len;
- int bytesAvailable = str.size()/2;
- if(bytesAvailable < amt)
- amt = bytesAvailable;
- const char* cstr = str.c_str()+2;
- for(int i=0;i<amt;i++) {
- char a = toupper(cstr[i*2]);
- char b = toupper(cstr[i*2+1]);
- if(a>='A') a=a-'A'+10;
- else a-='0';
- if(b>='A') b=b-'A'+10;
- else b-='0';
- unsigned char val = ((unsigned char)a<<4)|(unsigned char)b;
- ((unsigned char*)data)[i] = val;
- }
- return true;
- }
-
- if(len==1) {
- int x = atoi(str.c_str());
- *(unsigned char*)data = x;
- return true;
- } else if(len==2) {
- int x = atoi(str.c_str());
- *(unsigned short*)data = x;
- return true;
- } else if(len==4) {
- int x = atoi(str.c_str());
- *(unsigned int*)data = x;
- return true;
- }
- //we can't handle it
- return false;
-}*/
-
-/// \brief convert input string into vector of string tokens
-///
-/// \note consecutive delimiters will be treated as single delimiter
-/// \note delimiters are _not_ included in return data
-///
-/// \param input string to be parsed
-/// \param delims list of delimiters.
-
-std::vector<std::string> tokenize_str(const std::string & str,
- const std::string & delims=", \t")
-{
- using namespace std;
- // Skip delims at beginning, find start of first token
- string::size_type lastPos = str.find_first_not_of(delims, 0);
- // Find next delimiter @ end of token
- string::size_type pos = str.find_first_of(delims, lastPos);
-
- // output vector
- vector<string> tokens;
-
- while (string::npos != pos || string::npos != lastPos)
- {
- // Found a token, add it to the vector.
- tokens.push_back(str.substr(lastPos, pos - lastPos));
- // Skip delims. Note the "not_of". this is beginning of token
- lastPos = str.find_first_not_of(delims, pos);
- // Find next delimiter at end of token.
- pos = str.find_first_of(delims, lastPos);
- }
-
- return tokens;
+ return tokens;
}
-//this code was taken from WINE (LGPL)
-//http://google.com/codesearch?hl=en&q=+lang:c+splitpath+show:CPvw9Z-euls:_RSotQzmLeU:KGzljMEYFbY&sa=N&cd=9&ct=rc&cs_p=http://gentoo.osuosl.org/distfiles/Wine-20050524.tar.gz&cs_f=wine-20050524/programs/winefile/splitpath.c
-/*void splitpath(const char* path, char* drv, char* dir, char* name, char* ext)
-{
- const char* end;*/ /* end of processed string */
- //const char* p; /* search pointer */
- //const char* s; /* copy pointer */
-
- /* extract drive name */
- /*if (path[0] && path[1]==':') {
- if (drv) {
- *drv++ = *path++;
- *drv++ = *path++;
- *drv = '\0';
- } else path+=2;
- } else if (drv)
- *drv = '\0';*/
-
- /* search for end of string or stream separator */
- /*for(end=path; *end && *end!=':'; )
- end++;*/
-
- /* search for begin of file extension */
- /*for(p=end; p>path && *--p!='\\' && *p!='/'; )
- if (*p == '.') {
- end = p;
- break;
- }
-
- if (ext)
- for(s=end; (*ext=*s++); )
- ext++;
- else
- for(s=end; *s++; ) {}*/
-
- /* search for end of directory name */
- /*for(p=end; p>path; )
- if (*--p=='\\' || *p=='/') {
- p++;
- break;
- }
-
- if (name) {
- for(s=p; s<end; )
- *name++ = *s++;
-
- *name = '\0';
- } else
- for(s=p; s<end; )
- s++;
-
- if (dir) {
- for(s=path; s<p; )
- *dir++ = *s++;
-
- *dir = '\0';
- }
-}*/
-
-//mbg 5/12/08
-//for the curious, I tested U16ToHexStr and it was 10x faster than printf.
-//so the author of these dedicated functions is not insane, and I will leave them.
-
-//static char TempArray[11];
-
-/*uint16_t FastStrToU16(char* s, bool& valid)
-{
- int i;
- uint16_t v=0;
- for(i=0; i < 4; i++)
- {
- if(s[i] == 0) return v;
- v<<=4;
- if(s[i] >= '0' && s[i] <= '9')
- {
- v+=s[i]-'0';
- }
- else if(s[i] >= 'a' && s[i] <= 'f')
- {
- v+=s[i]-'a'+10;
- }
- else if(s[i] >= 'A' && s[i] <= 'F')
- {
- v+=s[i]-'A'+10;
- }
- else
- {
- valid = false;
- return 0xFFFF;
- }
- }
- valid = true;
- return v;
-}*/
-
-/*char *U8ToDecStr(uint8_t a)
-{
- TempArray[0] = '0' + a/100;
- TempArray[1] = '0' + (a%100)/10;
- TempArray[2] = '0' + (a%10);
- TempArray[3] = 0;
- return TempArray;
-}*/
-
-/*char *U16ToDecStr(uint16_t a)
-{
- TempArray[0] = '0' + a/10000;
- TempArray[1] = '0' + (a%10000)/1000;
- TempArray[2] = '0' + (a%1000)/100;
- TempArray[3] = '0' + (a%100)/10;
- TempArray[4] = '0' + (a%10);
- TempArray[5] = 0;
- return TempArray;
-}*/
-
-/*char *U32ToDecStr(char* buf, uint32_t a)
-{
- buf[0] = '0' + a/1000000000;
- buf[1] = '0' + (a%1000000000)/100000000;
- buf[2] = '0' + (a%100000000)/10000000;
- buf[3] = '0' + (a%10000000)/1000000;
- buf[4] = '0' + (a%1000000)/100000;
- buf[5] = '0' + (a%100000)/10000;
- buf[6] = '0' + (a%10000)/1000;
- buf[7] = '0' + (a%1000)/100;
- buf[8] = '0' + (a%100)/10;
- buf[9] = '0' + (a%10);
- buf[10] = 0;
- return buf;
-}*/
-/*char *U32ToDecStr(uint32_t a)
-{
- return U32ToDecStr(TempArray,a);
-}*/
-
-/*char *U16ToHexStr(uint16_t a)
-{
- TempArray[0] = a/4096 > 9?'A'+a/4096-10:'0' + a/4096;
- TempArray[1] = (a%4096)/256 > 9?'A'+(a%4096)/256 - 10:'0' + (a%4096)/256;
- TempArray[2] = (a%256)/16 > 9?'A'+(a%256)/16 - 10:'0' + (a%256)/16;
- TempArray[3] = a%16 > 9?'A'+(a%16) - 10:'0' + (a%16);
- TempArray[4] = 0;
- return TempArray;
-}*/
-
-/*char *U8ToHexStr(uint8_t a)
-{
- TempArray[0] = a/16 > 9?'A'+a/16 - 10:'0' + a/16;
- TempArray[1] = a%16 > 9?'A'+(a%16) - 10:'0' + (a%16);
- TempArray[2] = 0;
- return TempArray;
-}*/
-
-/*std::string stditoa(int n)
-{
- char tempbuf[16];
- sprintf(tempbuf, "%d", n);
- return tempbuf;
-}*/
-
-
-/*std::string readNullTerminatedAscii(std::istream* is)
-{
- std::string ret;
- ret.reserve(50);
- for(;;)
- {
- int c = is->get();
- if(c == 0) break;
- else ret += (char)c;
- }
- return ret;
-}*/
-
-// replace all instances of victim with replacement
-/*std::string mass_replace(const std::string &source, const std::string &victim, const std::string &replacement)
-{
- std::string answer = source;
- std::string::size_type j = 0;
- while ((j = answer.find(victim, j)) != std::string::npos )
- {
- answer.replace(j, victim.length(), replacement);
- j+= replacement.length();
- }
- return answer;
-}*/
-
-//http://www.codeproject.com/KB/string/UtfConverter.aspx
-/*#include "ConvertUTF.h"
-namespace UtfConverter
-{
- static std::wstring FromUtf8(const std::string& utf8string)
- {
- size_t widesize = utf8string.length();
- if (sizeof(wchar_t) == 2)
- {
- wchar_t* widestringnative = new wchar_t[widesize+1];
- const UTF8* sourcestart = reinterpret_cast<const UTF8*>(utf8string.c_str());
- const UTF8* sourceend = sourcestart + widesize;
- UTF16* targetstart = reinterpret_cast<UTF16*>(widestringnative);
- UTF16* targetend = targetstart + widesize+1;
- ConversionResult res = ConvertUTF8toUTF16(&sourcestart, sourceend, &targetstart, targetend, strictConversion);
- if (res != conversionOK)
- {
- delete [] widestringnative;
- throw std::exception();
- }
- *targetstart = 0;
- std::wstring resultstring(widestringnative);
- delete [] widestringnative;
- return resultstring;
- }
- else if (sizeof(wchar_t) == 4)
- {
- wchar_t* widestringnative = new wchar_t[widesize+1];
- const UTF8* sourcestart = reinterpret_cast<const UTF8*>(utf8string.c_str());
- const UTF8* sourceend = sourcestart + widesize;
- UTF32* targetstart = reinterpret_cast<UTF32*>(widestringnative);
- UTF32* targetend = targetstart + widesize;
- ConversionResult res = ConvertUTF8toUTF32(&sourcestart, sourceend, &targetstart, targetend, strictConversion);
- if (res != conversionOK)
- {
- delete [] widestringnative;
- throw std::exception();
- }
- *targetstart = 0;
- std::wstring resultstring(widestringnative);
- delete [] widestringnative;
- return resultstring;
- }
- else
- {
- throw std::exception();
- }
- return L"";
- }
-
- static std::string ToUtf8(const std::wstring& widestring)
- {
- size_t widesize = widestring.length();
-
- if (sizeof(wchar_t) == 2)
- {
- size_t utf8size = 3 * widesize + 1;
- char* utf8stringnative = new char[utf8size];
- const UTF16* sourcestart = reinterpret_cast<const UTF16*>(widestring.c_str());
- const UTF16* sourceend = sourcestart + widesize;
- UTF8* targetstart = reinterpret_cast<UTF8*>(utf8stringnative);
- UTF8* targetend = targetstart + utf8size;
- ConversionResult res = ConvertUTF16toUTF8(&sourcestart, sourceend, &targetstart, targetend, strictConversion);
- if (res != conversionOK)
- {
- delete [] utf8stringnative;
- throw std::exception();
- }
- *targetstart = 0;
- std::string resultstring(utf8stringnative);
- delete [] utf8stringnative;
- return resultstring;
- }
- else if (sizeof(wchar_t) == 4)
- {
- size_t utf8size = 4 * widesize + 1;
- char* utf8stringnative = new char[utf8size];
- const UTF32* sourcestart = reinterpret_cast<const UTF32*>(widestring.c_str());
- const UTF32* sourceend = sourcestart + widesize;
- UTF8* targetstart = reinterpret_cast<UTF8*>(utf8stringnative);
- UTF8* targetend = targetstart + utf8size;
- ConversionResult res = ConvertUTF32toUTF8(&sourcestart, sourceend, &targetstart, targetend, strictConversion);
- if (res != conversionOK)
- {
- delete [] utf8stringnative;
- throw std::exception();
- }
- *targetstart = 0;
- std::string resultstring(utf8stringnative);
- delete [] utf8stringnative;
- return resultstring;
- }
- else
- {
- throw std::exception();
- }
- return "";
- }
-}*/
-
-//convert a std::string to std::wstring
-/*std::wstring mbstowcs(std::string str)
-{
- try {
- return UtfConverter::FromUtf8(str);
- } catch(std::exception) {
- return L"(failed UTF-8 conversion)";
- }
-}*/
-
-/*std::string wcstombs(std::wstring str)
-{
- return UtfConverter::ToUtf8(str);
-}*/
-
-
-//TODO - dont we already have another function that can do this
-/*std::string getExtension(const char* input) {
- char buf[1024];
- strcpy(buf,input);
- char* dot=strrchr(buf,'.');
- if(!dot)
- return "";
- char ext [512];
- strcpy(ext, dot+1);
- int k, extlen=strlen(ext);
- for(k=0;k<extlen;k++)
- ext[k]=tolower(ext[k]);
- return ext;
-}*/
-
--- a/src/in_2sf/desmume/utils/xstring.h
+++ b/src/in_2sf/desmume/utils/xstring.h
@@ -23,113 +23,8 @@
#include <string>
#include <vector>
-//#include <iostream>
-//#include <cstdio>
-//#include <cstring>
-//#include <cstdlib>
-//#include "../types.h"
-//#include "emufile.h"
-
-//definitions for str_strip() flags
-//static const int STRIP_SP = 0x01; // space
-//static const int STRIP_TAB = 0x02; // tab
-//static const int STRIP_CR = 0x04; // carriage return
-//static const int STRIP_LF = 0x08; // line feed
-
-//int str_ucase(char *str);
-//int str_lcase(char *str);
-//int str_ltrim(char *str, int flags);
-//int str_rtrim(char *str, int flags);
-//int str_strip(char *str, int flags);
-//int chr_replace(char *str, char search, char replace);
-//int str_replace(char *str, char *search, char *replace);
-
-//std::string strsub(const std::string &str, int pos, int len);
-//std::string strmid(const std::string &str, int pos, int len);
-//std::string strleft(const std::string &str, int len);
-//std::string strright(const std::string &str, int len);
-//std::string toupper(const std::string &str);
-
-//int HexStringToBytesLength(const std::string &str);
-//int Base64StringToBytesLength(const std::string &str);
-//std::string u32ToHexString(uint32_t val);
-//std::string BytesToString(const void *data, int len);
-//bool StringToBytes(const std::string &str, void *data, int len);
-
-std::vector<std::string> tokenize_str(const std::string &str,const std::string &delims);
-//void splitpath(const char *path, char *drv, char *dir, char *name, char *ext);
-
-//uint16_t FastStrToU16(char *s, bool &valid);
-//char *U16ToDecStr(uint16_t a);
-//char *U32ToDecStr(uint32_t a);
-//char *U32ToDecStr(char *buf, uint32_t a);
-//char *U8ToDecStr(uint8_t a);
-//char *U8ToHexStr(uint8_t a);
-//char *U16ToHexStr(uint16_t a);
-
-//std::string stditoa(int n);
-
-//std::string readNullTerminatedAscii(std::istream *is);
-
-// extracts a decimal uint from an istream
-/*template<typename T> T templateIntegerDecFromIstream(EMUFILE *is)
-{
- unsigned int ret = 0;
- bool pre = true;
-
- for (;;)
- {
- int c = is->fgetc();
- if (c == -1)
- return ret;
- int d = c - '0';
- if (d < 0 || d > 9)
- {
- if (!pre)
- break;
- }
- else
- {
- pre = false;
- ret *= 10;
- ret += d;
- }
- }
- is->unget();
- return ret;
-}*/
-
-//inline uint32_t u32DecFromIstream(EMUFILE *is) { return templateIntegerDecFromIstream<uint32_t>(is); }
-//inline uint64_t u64DecFromIstream(EMUFILE *is) { return templateIntegerDecFromIstream<uint64_t>(is); }
-
-//puts an optionally 0-padded decimal integer of type T into the ostream (0-padding is quicker)
-/*template<typename T, int DIGITS, bool PAD> void putdec(EMUFILE *os, T dec)
-{
- char temp[DIGITS];
- int ctr = 0;
- for(int i = 0; i < DIGITS; ++i)
- {
- int quot = dec / 10;
- int rem = dec % 10;
- temp[DIGITS - 1 - i] = '0' + rem;
- if (!PAD && rem)
- ctr = i;
- dec = quot;
- }
- if (!PAD)
- os->fwrite(temp + DIGITS - ctr - 1, ctr + 1);
- else
- os->fwrite(temp, DIGITS);
-}*/
-
-//std::string mass_replace(const std::string &source, const std::string &victim, const std::string &replacement);
-
-//std::wstring mbstowcs(std::string str);
-//std::string wcstombs(std::wstring str);
-
-// TODO - dont we already have another function that can do this
-//std::string getExtension(const char *input);
+std::vector<std::string> tokenize_str(const std::string &str, const std::string &delims);
#endif
--- a/src/in_2sf/desmume/version.cpp
+++ b/src/in_2sf/desmume/version.cpp
@@ -1,5 +1,5 @@
/*
- Copyright (C) 2009-2011 DeSmuME team
+ Copyright (C) 2009-2012 DeSmuME team
This file is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -15,76 +15,83 @@
along with the this software. If not, see <http://www.gnu.org/licenses/>.
*/
-#include "types.h"
#include "version.h"
-//todo - everyone will want to support this eventually, i suppose
-/*#if defined(_WINDOWS) && !defined(WXPORT)
-#include "svnrev.h"
-#else*/
-/*#ifdef SVN_REV
-#define SVN_REV_STR SVN_REV
+// Helper macros to convert numerics to strings
+#if defined(_MSC_VER)
+// re: http://72.14.203.104/search?q=cache:HG-okth5NGkJ:mail.python.org/pipermail/python-checkins/2002-November/030704.html+_msc_ver+compiler+version+string&hl=en&gl=us&ct=clnk&cd=5
+# define _Py_STRINGIZE(X) _Py_STRINGIZE1((X))
+# define _Py_STRINGIZE1(X) _Py_STRINGIZE2 ## X
+# define _Py_STRINGIZE2(X) #X
+
+# define TOSTRING(X) _Py_STRINGIZE(X) // Alias _Py_STRINGIZE so that we have a common macro name
#else
-#define SVN_REV_STR ""
-#endif*/
-//#endif
+# define STRINGIFY(x) #x
+# define TOSTRING(x) STRINGIFY(x)
+#endif
#define DESMUME_NAME "DeSmuME"
-#if defined(_WIN64)
-#define DESMUME_PLATFORM_STRING " x64"
-#elif defined(_WIN32)
-#define DESMUME_PLATFORM_STRING " x86"
+#if defined(__x86_64__) || defined(__LP64) || defined(__IA64__) || defined(_M_X64) || defined(_WIN64)
+# define DESMUME_PLATFORM_STRING " x64"
+#elif defined(__i386__) || defined(_M_IX86) || defined(_WIN32)
+# define DESMUME_PLATFORM_STRING " x86"
+#elif defined(__arm__)
+# define DESMUME_PLATFORM_STRING " ARM"
+#elif defined(__thumb__)
+# define DESMUME_PLATFORM_STRING " ARM-Thumb"
+#elif defined(__ppc__) || defined(_M_PPC)
+# define DESMUME_PLATFORM_STRING " PowerPC"
#else
-#define DESMUME_PLATFORM_STRING ""
+# define DESMUME_PLATFORM_STRING ""
#endif
#ifndef ENABLE_SSE2
- #ifndef ENABLE_SSE
- #define DESMUME_CPUEXT_STRING " NOSSE"
- #else
- #define DESMUME_CPUEXT_STRING " NOSSE2"
- #endif
+# ifndef ENABLE_SSE
+# define DESMUME_CPUEXT_STRING " NOSSE"
+# else
+# define DESMUME_CPUEXT_STRING " NOSSE2"
+# endif
#else
-#define DESMUME_CPUEXT_STRING ""
+# define DESMUME_CPUEXT_STRING ""
#endif
-/*#ifdef DEVELOPER
-#define DESMUME_FEATURE_STRING " dev+"
+#define DESMUME_SUBVERSION_STRING " svn 4598"
+
+#ifdef __INTEL_COMPILER
+# define DESMUME_COMPILER " (Intel)"
+# define DESMUME_COMPILER_DETAIL " (Intel v" TOSTRING(__INTEL_COMPILER) ")"
+#elif defined(_MSC_VER)
+# define DESMUME_COMPILER " (MSVC)"
+# define DESMUME_COMPILER_DETAIL " (MSVC v" TOSTRING(_MSC_VER) ")"
+#elif defined(__clang__)
+# define DESMUME_COMPILER " (LLVM-Clang)"
+# define DESMUME_COMPILER_DETAIL " (LLVM-Clang v" TOSTRING(__clang_major__) "." TOSTRING(__clang_minor__) "." TOSTRING(__clang_patchlevel__) ")"
+#elif defined(__llvm__)
+# define DESMUME_COMPILER " (LLVM)"
+# define DESMUME_COMPILER_DETAIL " (LLVM)"
+#elif defined(__GNUC__) // Always make GCC the last check, since other compilers, such as Clang, may define __GNUC__ internally.
+# define DESMUME_COMPILER " (GCC)"
+
+# if defined(__GNUC_PATCHLEVEL__)
+# define DESMUME_COMPILER_DETAIL " (GCC v" TOSTRING(__GNUC__) "." TOSTRING(__GNUC_MINOR__) "." TOSTRING(__GNUC_PATCHLEVEL__) ")"
+# else
+# define DESMUME_COMPILER_DETAIL " (GCC v" TOSTRING(__GNUC__) "." TOSTRING(__GNUC_MINOR__) ")"
+# endif
#else
-#define DESMUME_FEATURE_STRING ""
-#endif*/
-
-/*#if defined(DEBUG)
-#define DESMUME_SUBVERSION_STRING " debug"
-#elif defined(PUBLIC_RELEASE)
-#define DESMUME_SUBVERSION_STRING ""
-#else
-#define DESMUME_SUBVERSION_STRING " svn" SVN_REV_STR
-#endif*/
-
-#if defined(__INTEL_COMPILER)
-#define DESMUME_COMPILER " (Intel) "
-//#define DESMUME_COMPILER_DETAIL " (Intel) "
-#elif defined(_MSC_VER)
-#define DESMUME_COMPILER ""
-//#define DESMUME_COMPILER_DETAIL " msvc " _Py_STRINGIZE(_MSC_VER)
-//#define _Py_STRINGIZE(X) _Py_STRINGIZE1((X))
-//#define _Py_STRINGIZE1(X) _Py_STRINGIZE2 ## X
-//#define _Py_STRINGIZE2(X) #X
-//re: http://72.14.203.104/search?q=cache:HG-okth5NGkJ:mail.python.org/pipermail/python-checkins/2002-November/030704.html+_msc_ver+compiler+version+string&hl=en&gl=us&ct=clnk&cd=5
-#else
-// TODO: make for others compilers
-#define DESMUME_COMPILER ""
-//#define DESMUME_COMPILER_DETAIL ""
+# define DESMUME_COMPILER ""
+# define DESMUME_COMPILER_DETAIL ""
#endif
-//#define DESMUME_VERSION_NUMERIC 90800
-#define DESMUME_VERSION_STRING " 0.9.8" /*DESMUME_SUBVERSION_STRING*/ /*DESMUME_FEATURE_STRING*/ DESMUME_PLATFORM_STRING DESMUME_CPUEXT_STRING DESMUME_COMPILER
+#ifdef HAVE_JIT
+# define DESMUME_JIT "-JIT"
+#else
+# define DESMUME_JIT ""
+#endif
+
+#define DESMUME_VERSION_STRING " " "0.9.9" DESMUME_SUBVERSION_STRING DESMUME_PLATFORM_STRING DESMUME_JIT DESMUME_CPUEXT_STRING
#define DESMUME_NAME_AND_VERSION DESMUME_NAME DESMUME_VERSION_STRING
-//uint32_t EMU_DESMUME_VERSION_NUMERIC() { return DESMUME_VERSION_NUMERIC; }
-const char* EMU_DESMUME_VERSION_STRING() { return DESMUME_VERSION_STRING; }
-const char* EMU_DESMUME_NAME_AND_VERSION() { return DESMUME_NAME_AND_VERSION; }
-//const char* EMU_DESMUME_COMPILER_DETAIL() { return DESMUME_COMPILER_DETAIL; }
+const char *EMU_DESMUME_VERSION_STRING() { return DESMUME_VERSION_STRING; }
+const char *EMU_DESMUME_NAME_AND_VERSION() { return DESMUME_NAME_AND_VERSION; }
--- a/src/in_2sf/desmume/version.h
+++ b/src/in_2sf/desmume/version.h
@@ -15,12 +15,11 @@
along with the this software. If not, see <http://www.gnu.org/licenses/>.
*/
-#include <string>
+#ifndef VERSION_H
+#define VERSION_H
-#include "types.h"
-
-//uint32_t EMU_DESMUME_VERSION_NUMERIC();
const char *EMU_DESMUME_VERSION_STRING();
const char *EMU_DESMUME_NAME_AND_VERSION();
-//const char *EMU_DESMUME_COMPILER_DETAIL();
+#endif
+