Updating the VBA-M code to revision 1231.
--- a/src/in_gsf/in_gsf.vcxproj
+++ b/src/in_gsf/in_gsf.vcxproj
@@ -49,7 +49,7 @@
<ClCompile>
<WarningLevel>Level4</WarningLevel>
<Optimization>Disabled</Optimization>
- <PreprocessorDefinitions>WIN32;_WINDOWS;_USRDLL;IN_GSF_EXPORTS;_CRT_SECURE_NO_WARNINGS;WINAMP_PLUGIN;NO_DEBUGGER;FINAL_VERSION;C_CORE;_DEBUG;_ITERATOR_DEBUG_LEVEL=0;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <PreprocessorDefinitions>WIN32;_WINDOWS;_USRDLL;IN_GSF_EXPORTS;_CRT_SECURE_NO_WARNINGS;WINAMP_PLUGIN;_DEBUG;_ITERATOR_DEBUG_LEVEL=0;%(PreprocessorDefinitions)</PreprocessorDefinitions>
<AdditionalIncludeDirectories>G:\Code\my_xsf\src;$(zlibRootDir)\include;$(WinampSDKDir);%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
<DisableSpecificWarnings>4100;4127;4189;4244;4291;4310;4512;4800;%(DisableSpecificWarnings)</DisableSpecificWarnings>
</ClCompile>
@@ -66,7 +66,7 @@
<Optimization>MaxSpeed</Optimization>
<FunctionLevelLinking>true</FunctionLevelLinking>
<IntrinsicFunctions>true</IntrinsicFunctions>
- <PreprocessorDefinitions>WIN32;_WINDOWS;_USRDLL;IN_GSF_EXPORTS;_CRT_SECURE_NO_WARNINGS;WINAMP_PLUGIN;NO_DEBUGGER;FINAL_VERSION;C_CORE;NDEBUG;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <PreprocessorDefinitions>WIN32;_WINDOWS;_USRDLL;IN_GSF_EXPORTS;_CRT_SECURE_NO_WARNINGS;WINAMP_PLUGIN;NDEBUG;%(PreprocessorDefinitions)</PreprocessorDefinitions>
<AdditionalIncludeDirectories>G:\Code\my_xsf\src;$(zlibRootDir)\include;$(WinampSDKDir);%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
<DisableSpecificWarnings>4100;4127;4189;4244;4291;4310;4512;4800;%(DisableSpecificWarnings)</DisableSpecificWarnings>
</ClCompile>
--- a/src/in_gsf/vbam/apu/Blip_Buffer.cpp
+++ b/src/in_gsf/vbam/apu/Blip_Buffer.cpp
@@ -1,10 +1,9 @@
// Blip_Buffer 0.4.1. http://www.slack.net/~ant/
+#include <limits>
#include <numeric>
-#include <cassert>
#include <cmath>
#include <cstring>
-#include <cstdlib>
#include "Blip_Buffer.h"
/* Copyright (C) 2003-2007 Shay Green. This module is free software; you
@@ -22,7 +21,7 @@
Blip_Buffer::Blip_Buffer()
{
- this->factor_ = static_cast<uint32_t>(LONG_MAX);
+ this->factor_ = static_cast<uint32_t>(std::numeric_limits<long>::max());
this->buffer_.clear();
this->buffer_size_ = 0;
this->sample_rate_ = 0;
@@ -71,7 +70,7 @@
if (s < new_size)
new_size = s;
else
- assert(0); // fails if requested buffer length exceeds limit
+ assert(false); // fails if requested buffer length exceeds limit
}
if (this->buffer_size_ != new_size)
@@ -131,7 +130,7 @@
{
if (!this->factor_)
{
- assert(0); // sample rate and clock rates must be set first
+ assert(false); // sample rate and clock rates must be set first
return 0;
}
@@ -149,8 +148,8 @@
// copy remaining samples to beginning and clear old samples
long remain = this->samples_avail() + blip_buffer_extra_;
- memmove(&this->buffer_[0], &this->buffer_[count], remain * sizeof(this->buffer_[0]));
- memset(&this->buffer_[remain], 0, count * sizeof(this->buffer_[0]));
+ memmove(&this->buffer_[0], &this->buffer_[count], remain * sizeof(buf_t_));
+ memset(&this->buffer_[remain], 0, count * sizeof(buf_t_));
}
}
@@ -159,8 +158,7 @@
Blip_Synth_Fast_::Blip_Synth_Fast_()
{
this->buf = nullptr;
- this->last_amp = 0;
- this->delta_factor = 0;
+ this->last_amp = this->delta_factor = 0;
}
void Blip_Synth_Fast_::volume_unit(double new_unit)
@@ -175,8 +173,7 @@
this->volume_unit_ = 0.0;
this->kernel_unit = 0;
this->buf = nullptr;
- this->last_amp = 0;
- this->delta_factor = 0;
+ this->last_amp = this->delta_factor = 0;
}
#ifndef M_PI
@@ -193,10 +190,10 @@
if (treble > 5.0)
treble = 5.0;
- double const maxh = 4096.0;
- double const rolloff = std::pow(10.0, 1.0 / (maxh * 20.0) * treble / (1.0 - cutoff));
- double const pow_a_n = std::pow(rolloff, maxh - maxh * cutoff);
- double const to_angle = M_PI / 2 / maxh / oversample;
+ static const double maxh = 4096.0;
+ double rolloff = std::pow(10.0, 1.0 / (maxh * 20.0) * treble / (1.0 - cutoff));
+ double pow_a_n = std::pow(rolloff, maxh - maxh * cutoff);
+ double to_angle = M_PI / 2 / maxh / oversample;
for (int i = 0; i < count; ++i)
{
double angle = ((i - count) * 2 + 1) * to_angle;
@@ -226,10 +223,10 @@
gen_sinc(out, count, blip_res * oversample, this->treble, cutoff);
- // apply (half of) hann window
+ // apply (half of) hamming window
double to_fraction = M_PI / (count - 1);
for (int i = count; i--; )
- out[i] *= 0.5f * (1.0f - static_cast<float>(std::cos(i * to_fraction)));
+ out[i] *= 0.54f - 0.46f * static_cast<float>(std::cos(i * to_fraction));
}
void Blip_Synth_::adjust_impulse()
@@ -245,7 +242,7 @@
if (p == p2)
error /= 2; // phase = 0.5 impulse uses same half for both sides
this->impulses[size - blip_res + p] += static_cast<short>(error);
- //printf("error: %ld\n", error);
+ //printf( "error: %ld\n", error );
}
//for (int i = blip_res; i--; printf("\n"))
@@ -336,7 +333,7 @@
}
}
this->delta_factor = static_cast<int>(std::floor(factor + 0.5));
- //printf("delta_factor: %d, kernel_unit: %d\n", this->delta_factor, this->kernel_unit);
+ //printf( "delta_factor: %d, kernel_unit: %d\n", delta_factor, kernel_unit );
}
}
#endif
@@ -349,10 +346,10 @@
if (count)
{
- int bass = BLIP_READER_BASS(*this);
+ int bass = BLIP_READER_BASS(this);
BLIP_READER_BEGIN(reader, *this);
BLIP_READER_ADJ_(reader, count);
- auto out = out_ + count;
+ auto out = &out_[count];
int32_t offset = static_cast<int32_t>(-count);
do
--- a/src/in_gsf/vbam/apu/Blip_Buffer.h
+++ b/src/in_gsf/vbam/apu/Blip_Buffer.h
@@ -1,8 +1,7 @@
// Band-limited sound synthesis buffer
// Blip_Buffer 0.4.1
-#ifndef BLIP_BUFFER_H
-#define BLIP_BUFFER_H
+#pragma once
#include <vector>
#include <cstdint>
@@ -11,7 +10,7 @@
typedef int32_t blip_time_t;
// Output samples are 16-bit signed, with a range of -32768 to 32767
-typedef short blip_sample_t;
+typedef int16_t blip_sample_t;
enum { blip_sample_max = 32767 };
class Blip_Buffer
@@ -20,7 +19,7 @@
// Sets output sample rate and buffer length in milliseconds (1/1000 sec, defaults
// to 1/4 second) and clears buffer. If there isn't enough memory, leaves buffer
// untouched and returns "Out of memory", otherwise returns NULL.
- void set_sample_rate(long samples_per_sec, int msec_length = 1000 / 4);
+ void set_sample_rate(long samples_per_sec, int msec_length = 250);
// Sets number of source time units per second
void clock_rate(long clocks_per_sec);
@@ -89,11 +88,9 @@
blip_resampled_time_t resampled_duration(int t) const { return t * this->factor_; }
blip_resampled_time_t resampled_time(blip_time_t t) const { return t * this->factor_ + this->offset_; }
blip_resampled_time_t clock_rate_factor(long clock_rate) const;
+
Blip_Buffer();
virtual ~Blip_Buffer();
-
- // Deprecated
- typedef blip_resampled_time_t resampled_time_t;
private:
// noncopyable
Blip_Buffer(const Blip_Buffer &);
@@ -116,22 +113,28 @@
// Number of bits in resample ratio fraction. Higher values give a more accurate ratio
// but reduce maximum buffer size.
-const int BLIP_BUFFER_ACCURACY = 16;
+enum { BLIP_BUFFER_ACCURACY = 16 };
// Number bits in phase offset. Fewer than 6 bits (64 phase offsets) results in
// noticeable broadband noise when synthesizing high frequency square waves.
// Affects size of Blip_Synth objects since they store the waveform directly.
+enum
+{
#if BLIP_BUFFER_FAST
-const int BLIP_PHASE_BITS = 8;
+ BLIP_PHASE_BITS = 8
#else
-const int BLIP_PHASE_BITS = 6;
+ BLIP_PHASE_BITS = 6
#endif
+};
// Internal
typedef uint32_t blip_resampled_time_t;
-const int blip_widest_impulse_ = 16;
-const int blip_buffer_extra_ = blip_widest_impulse_ + 2;
-const int blip_res = 1 << BLIP_PHASE_BITS;
+enum
+{
+ blip_widest_impulse_ = 16,
+ blip_buffer_extra_ = blip_widest_impulse_ + 2,
+ blip_res = 1 << BLIP_PHASE_BITS
+};
class blip_eq_t;
class Blip_Synth_Fast_
@@ -166,9 +169,12 @@
};
// Quality level, better = slower. In general, use blip_good_quality.
-const int blip_med_quality = 8;
-const int blip_good_quality = 12;
-const int blip_high_quality = 16;
+enum
+{
+ blip_med_quality = 8,
+ blip_good_quality = 12,
+ blip_high_quality = 16
+};
// Range specifies the greatest expected change in amplitude. Calculate it
// by finding the difference between the maximum and minimum expected
@@ -216,7 +222,7 @@
Blip_Synth_Fast_ impl;
#else
Blip_Synth_ impl;
- typedef short imp_t;
+ typedef int16_t imp_t;
imp_t impulses[blip_res * (quality / 2) + 1];
public:
Blip_Synth() : impl(impulses, quality) { }
@@ -243,21 +249,21 @@
friend class Blip_Synth_;
};
-const int blip_sample_bits = 30;
+enum { blip_sample_bits = 30 };
// Optimized reading from Blip_Buffer, for use in custom sample output
// Begins reading from buffer. Name should be unique to the current block.
#define BLIP_READER_BEGIN(name, blip_buffer) \
- auto name##_reader_buf = &(blip_buffer).buffer_[0]; \
+ const Blip_Buffer::buf_t_ *name##_reader_buf = &(blip_buffer).buffer_[0]; \
int32_t name##_reader_accum = (blip_buffer).reader_accum_
// Gets value to pass to BLIP_READER_NEXT()
-inline int BLIP_READER_BASS(const Blip_Buffer &blip_buffer) { return blip_buffer.bass_shift_; }
+inline int BLIP_READER_BASS(const Blip_Buffer *blip_buffer) { return blip_buffer->bass_shift_; }
// Constant value to use instead of BLIP_READER_BASS(), for slightly more optimal
// code at the cost of having no bass control
-const int blip_reader_default_bass = 9;
+enum { blip_reader_default_bass = 9 };
// Current sample
#define BLIP_READER_READ(name) (name##_reader_accum >> (blip_sample_bits - 16))
@@ -281,12 +287,6 @@
{ \
name##_reader_accum -= name##_reader_accum >> (bass); \
name##_reader_accum += name##_reader_buf[(idx)]; \
-}
-
-#define BLIP_READER_NEXT_RAW_IDX_(name, bass, idx) \
-{ \
- name##_reader_accum -= name##_reader_accum >> (bass); \
- name##_reader_accum += *reinterpret_cast<const Blip_Buffer::buf_t_ *>(reinterpret_cast<const char *>(name##_reader_buf) + (idx)); \
}
#if defined(_M_IX86) || defined(_M_IA64) || defined(__i486__) || defined(__x86_64__) || defined(__ia64__) || defined(__i386__)
@@ -304,9 +304,7 @@
// End of public interface
-#ifndef assert
-# include <cassert>
-#endif
+#include <cassert>
template<int quality, int range> inline void Blip_Synth<quality, range>::offset_resampled(blip_resampled_time_t time, int delta, Blip_Buffer *blip_buf) const
{
@@ -316,7 +314,7 @@
delta *= this->impl.delta_factor;
auto buf = &blip_buf->buffer_[time >> BLIP_BUFFER_ACCURACY];
- int phase = static_cast<int>((time >> (BLIP_BUFFER_ACCURACY - BLIP_PHASE_BITS)) & (blip_res - 1));
+ int phase = static_cast<int>(time >> (BLIP_BUFFER_ACCURACY - BLIP_PHASE_BITS) & (blip_res - 1));
#if BLIP_BUFFER_FAST
int32_t left = buf[0] + delta;
@@ -335,12 +333,12 @@
int rev = fwd + quality - 2;
int mid = quality / 2 - 1;
- auto imp = this->impulses + blip_res - phase;
+ auto imp = &this->impulses[blip_res - phase];
# if defined(_M_IX86) || defined(_M_IA64) || defined(__i486__) || defined(__x86_64__) || defined(__ia64__) || defined(__i386__)
// this straight forward version gave in better code on GCC for x86
- auto ADD_IMP = [&](int out, int in) { buf[out] += static_cast<int32_t>(imp[blip_res * in] * delta); };
+ auto ADD_IMP = [&](int out, int in) { buf[out] += static_cast<int32_t>(imp[blip_res * in]) * delta; };
auto BLIP_FWD = [&](int i) { ADD_IMP(fwd + i, i); ADD_IMP(fwd + 1 + i, i + 1); };
auto BLIP_REV = [&](int r) { ADD_IMP(rev - r, r + 1); ADD_IMP(rev + 1 - r, r); };
@@ -352,7 +350,7 @@
BLIP_FWD(4);
ADD_IMP(fwd + mid - 1, mid - 1);
ADD_IMP(fwd + mid, mid);
- imp = this->impulses + phase;
+ imp = &this->impulses[phase];
if (quality > 12)
BLIP_REV(6);
if (quality > 8)
@@ -390,7 +388,7 @@
BLIP_FWD(4);
int32_t t0 = i0 * delta + buf[fwd + mid - 1];
int32_t t1 = imp[blip_res * mid] * delta + buf[fwd + mid];
- imp = this->impulses + phase;
+ imp = &this->impulses[phase];
i0 = imp[blip_res * mid];
buf[fwd + mid - 1] = t0;
buf[fwd + mid] = t1;
@@ -442,8 +440,9 @@
return this->reader_accum_ >> (blip_sample_bits - 16);
}
-const int blip_max_length = 0;
-const int blip_default_length = 250; // 1/4 second
-
-#endif
-
+enum
+{
+ blip_max_length = 0,
+ blip_default_length = 250 // 1/4 second
+};
+
--- a/src/in_gsf/vbam/apu/Gb_Apu.cpp
+++ b/src/in_gsf/vbam/apu/Gb_Apu.cpp
@@ -30,7 +30,7 @@
int Gb_Apu::calc_output(int osc) const
{
int bits = this->regs[stereo_reg - start_addr] >> osc;
- return ((bits >> 3) & 2) | (bits & 1);
+ return (bits >> 3 & 2) | (bits & 1);
}
void Gb_Apu::set_output(Blip_Buffer *center, Blip_Buffer *left, Blip_Buffer *right, int osc)
@@ -65,7 +65,7 @@
// TODO: Doesn't handle differing left and right volumes (panning).
// Not worth the complexity.
int data = this->regs[vol_reg - start_addr];
- int left = (data >> 4) & 7;
+ int left = data >> 4 & 7;
int right = data & 7;
//if ( data & 0x88 ) dprintf( "Vin: %02X\n", data & 0x88 );
//if ( left != right ) dprintf( "l: %d r: %d\n", left, right );
@@ -83,8 +83,7 @@
void Gb_Apu::reset_regs()
{
- for (int i = 0; i < 0x20; ++i)
- this->regs[i] = 0;
+ std::fill(&this->regs[0], &this->regs[0x20], 0);
this->square1.reset();
this->square2.reset();
@@ -173,11 +172,7 @@
{
auto &o = *this->oscs[i];
o.regs = &this->regs[i * 5];
- o.output = nullptr;
- o.outputs[0] = nullptr;
- o.outputs[1] = nullptr;
- o.outputs[2] = nullptr;
- o.outputs[3] = nullptr;
+ o.output = o.outputs[0] = o.outputs[1] = o.outputs[2] = o.outputs[3] = nullptr;
o.good_synth = &this->good_synth;
o.med_synth = &this->med_synth;
}
@@ -190,7 +185,7 @@
void Gb_Apu::run_until_(blip_time_t end_time)
{
- while (1)
+ while (true)
{
// run oscillators
blip_time_t time = end_time;
--- a/src/in_gsf/vbam/apu/Gb_Apu.h
+++ b/src/in_gsf/vbam/apu/Gb_Apu.h
@@ -1,8 +1,7 @@
// Nintendo Game Boy sound hardware emulator with save state support
// Gb_Snd_Emu 0.2.0
-#ifndef GB_APU_H
-#define GB_APU_H
+#pragma once
#include "Gb_Oscs.h"
@@ -64,7 +63,7 @@
// Treble and bass values for various hardware.
enum
{
- speaker_treble = -47, // speaker on system
+ speaker_treble = -47, // speaker on system
speaker_bass = 2000,
dmg_treble = 0, // headphones on each system
dmg_bass = 30,
@@ -114,11 +113,8 @@
void run_until(blip_time_t);
void silence_osc(Gb_Osc &);
void write_osc(int index, int reg, int old_data, int data);
- friend class Gb_Apu_Tester;
public:
int read_status();
};
-#endif
-
--- a/src/in_gsf/vbam/apu/Gb_Oscs.cpp
+++ b/src/in_gsf/vbam/apu/Gb_Oscs.cpp
@@ -22,8 +22,7 @@
void Gb_Osc::reset()
{
this->output = nullptr;
- this->last_amp = 0;
- this->delay = 0;
+ this->last_amp = this->delay = 0;
this->phase = 0;
this->enabled = false;
}
@@ -90,7 +89,7 @@
this->sweep_freq = freq;
this->regs[3] = freq & 0xFF;
- this->regs[4] = (this->regs[4] & ~0x07) | ((freq >> 8) & 0x07);
+ this->regs[4] = (this->regs[4] & ~0x07) | (freq >> 8 & 0x07);
}
}
@@ -441,7 +440,7 @@
{
// won't fully replace upper 8 bits, so have to do the unoptimized way
while (--count >= 0)
- s = ((s >> 1) | mask) ^ (mask & (0 - ((s - 1) & 2)));
+ s = (s >> 1 | mask) ^ (mask & (0 - ((s - 1) & 2)));
}
else
{
@@ -453,7 +452,7 @@
}
// Need to keep one extra bit of history
- s = (s << 1) & 0xFF;
+ s = s << 1 & 0xFF;
// Convert from Fibonacci to Galois configuration,
// shifted left 2 bits
@@ -471,7 +470,7 @@
// Convert back to Fibonacci configuration and
// repeat last 8 bits above significant 7
- s = ((s << 7) & 0x7F80) | ((s >> 1) & 0x7F);
+ s = (s << 7 & 0x7F80) | (s >> 1 & 0x7F);
}
return s;
@@ -514,15 +513,13 @@
// Run timer and calculate time of next LFSR clock
static const uint8_t period1s[] = { 1, 2, 4, 6, 8, 10, 12, 14 };
int period1 = period1s[this->regs[3] & 7] * clk_mul;
- {
- int extra = (end_time - time) - this->delay;
- int per2 = this->period2();
- time += this->delay + ((this->divider ^ (per2 >> 1)) & (per2 - 1)) * period1;
-
- int count = extra < 0 ? 0 : (extra + period1 - 1) / period1;
- this->divider = (this->divider - count) & period2_mask;
- this->delay = count * period1 - extra;
- }
+ int extra = (end_time - time) - this->delay;
+ int per2 = this->period2();
+ time += this->delay + ((this->divider ^ (per2 >> 1)) & (per2 - 1)) * period1;
+
+ int count = extra < 0 ? 0 : (extra + period1 - 1) / period1;
+ this->divider = (this->divider - count) & period2_mask;
+ this->delay = count * period1 - extra;
// Generate wave
if (time < end_time)
@@ -547,7 +544,7 @@
do
{
unsigned changed = bits + 1;
- bits = (bits >> 1) & mask;
+ bits = bits >> 1 & mask;
if (changed & 2)
{
bits |= ~mask;
@@ -569,11 +566,11 @@
// Calc volume
static const uint8_t volumes[] = { 0, 4, 2, 1, 3, 3, 3, 3 };
static const int volume_shift = 2;
- int volume_idx = (this->regs[2] >> 5) & (this->agb_mask | 3); // 2 bits on DMG/CGB, 3 on AGB
+ int volume_idx = this->regs[2] >> 5 & (this->agb_mask | 3); // 2 bits on DMG/CGB, 3 on AGB
int volume_mul = volumes[volume_idx];
// Determine what will be generated
- int playing = false;
+ int playing = 0;
auto out = this->output;
if (out)
{
@@ -587,9 +584,9 @@
if (this->frequency() <= 0x7FB || this->delay > 15 * clk_mul)
{
if (volume_mul)
- playing = this->enabled;
-
- amp = (this->sample_buf << ((this->phase << 2) & 4) & 0xF0) * playing;
+ playing = static_cast<int>(this->enabled);
+
+ amp = (this->sample_buf << (this->phase << 2 & 4) & 0xF0) * playing;
}
amp = ((amp * volume_mul) >> (volume_shift + 4)) - dac_bias;
@@ -632,7 +629,7 @@
do
{
// Extract nybble
- int nybble = (wave[ph >> 1] << ((ph << 2) & 4)) & 0xF0;
+ int nybble = wave[ph >> 1] << (ph << 2 & 4) & 0xF0;
ph = (ph + 1) & wave_mask;
// Scale by volume
--- a/src/in_gsf/vbam/apu/Gb_Oscs.h
+++ b/src/in_gsf/vbam/apu/Gb_Oscs.h
@@ -1,8 +1,7 @@
// Private oscillators used by Gb_Apu
// Gb_Snd_Emu 0.2.0
-#ifndef GB_OSCS_H
-#define GB_OSCS_H
+#pragma once
#include "blargg_common.h"
#include "Blip_Buffer.h"
@@ -170,7 +169,7 @@
void corrupt_wave();
- uint8_t *wave_bank() const { return &this->wave_ram[((~this->regs[0] & bank40_mask) >> 2) & agb_mask]; }
+ uint8_t *wave_bank() const { return &this->wave_ram[(~this->regs[0] & bank40_mask) >> 2 & this->agb_mask]; }
// Wave index that would be accessed, or -1 if no access would occur
int access(unsigned addr) const;
@@ -189,5 +188,3 @@
this->wave_bank()[index] = data;
}
-#endif
-
--- a/src/in_gsf/vbam/apu/Multi_Buffer.cpp
+++ b/src/in_gsf/vbam/apu/Multi_Buffer.cpp
@@ -13,10 +13,6 @@
details. You should have received a copy of the GNU Lesser General Public
License along with this module; if not, write to the Free Software Foundation,
Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
-
-#ifdef BLARGG_ENABLE_OPTIMIZER
-# include BLARGG_ENABLE_OPTIMIZER
-#endif
Multi_Buffer::Multi_Buffer(int spf) : samples_per_frame_(spf)
{
@@ -177,7 +173,7 @@
void Stereo_Mixer::mix_mono(blip_sample_t *out_, int count)
{
- int bass = BLIP_READER_BASS(*this->bufs[2]);
+ int bass = BLIP_READER_BASS(this->bufs[2]);
BLIP_READER_BEGIN(center, *this->bufs[2]);
BLIP_READER_ADJ_(center, this->samples_read);
@@ -198,16 +194,16 @@
void Stereo_Mixer::mix_stereo(blip_sample_t *out_, int count)
{
- auto out = out_ + count * stereo;
+ auto out = &out_[count * stereo];
// do left + center and right + center separately to reduce register load
auto buf = &this->bufs[2];
- while (1) // loop runs twice
+ while (true) // loop runs twice
{
--buf;
--out;
- int bass = BLIP_READER_BASS(*this->bufs[2]);
+ int bass = BLIP_READER_BASS(this->bufs[2]);
BLIP_READER_BEGIN(side, **buf);
BLIP_READER_BEGIN(center, *this->bufs[2]);
--- a/src/in_gsf/vbam/apu/Multi_Buffer.h
+++ b/src/in_gsf/vbam/apu/Multi_Buffer.h
@@ -1,8 +1,7 @@
// Multi-channel sound buffer interface, and basic mono and stereo buffers
// Blip_Buffer 0.4.1
-#ifndef MULTI_BUFFER_H
-#define MULTI_BUFFER_H
+#pragma once
#include "blargg_common.h"
#include "Blip_Buffer.h"
@@ -19,7 +18,7 @@
// (type information used by Effects_Buffer)
enum { type_index_mask = 0xFF };
enum { wave_type = 0x100, noise_type = 0x200, mixed_type = wave_type | noise_type };
- virtual void set_channel_count(int, const int* types = nullptr);
+ virtual void set_channel_count(int, const int *types = nullptr);
int channel_count() const { return this->channel_count_; }
// Gets indexed channel, from 0 to channel count - 1
@@ -153,5 +152,3 @@
this->channel_types_ = types;
}
-#endif
-
--- a/src/in_gsf/vbam/apu/blargg_common.h
+++ b/src/in_gsf/vbam/apu/blargg_common.h
@@ -2,18 +2,12 @@
// To change configuration options, modify blargg_config.h, not this file.
// Gb_Snd_Emu 0.2.0
-#ifndef BLARGG_COMMON_H
-#define BLARGG_COMMON_H
+#pragma once
#include <cstdlib>
#include <cassert>
#include <cstdint>
-
-#undef BLARGG_COMMON_H
-// allow blargg_config.h to #include blargg_common.h
#include "blargg_config.h"
-#ifndef BLARGG_COMMON_H
-#define BLARGG_COMMON_H
// BLARGG_COMPILER_HAS_BOOL: If 0, provides bool support for old compiler. If 1,
// compiler is assumed to support bool. If undefined, availability is determined.
@@ -39,6 +33,3 @@
const bool false = 0;
#endif
-#endif
-#endif
-
--- a/src/in_gsf/vbam/apu/blargg_config.h
+++ b/src/in_gsf/vbam/apu/blargg_config.h
@@ -1,7 +1,6 @@
// $package user configuration file. Don't replace when updating library.
-#ifndef BLARGG_CONFIG_H
-#define BLARGG_CONFIG_H
+#pragma once
// Uncomment to have Gb_Apu run at 4x normal clock rate (16777216 Hz), useful in
// a Game Boy Advance emulator.
@@ -10,5 +9,3 @@
// Uncomment if you get errors in the bool section of blargg_common.h
//#define BLARGG_COMPILER_HAS_BOOL 1
-#endif
-
--- a/src/in_gsf/vbam/common/Port.h
+++ b/src/in_gsf/vbam/common/Port.h
@@ -1,28 +1,25 @@
-#ifndef PORT_H
-#define PORT_H
+#pragma once
#include <cstdint>
#ifdef WORDS_BIGENDIAN
-#if defined(__GNUC__) && defined(__ppc__)
+# if defined(__GNUC__) && defined(__ppc__)
#define READ16LE(base) \
- ({ \
- unsigned short lhbrxResult; \
- __asm__("lhbrx %0, 0, %1" : "=r" (lhbrxResult) : "r" (base) : "memory"); \
- lhbrxResult; \
- })
+ ({ unsigned short lhbrxResult; \
+ __asm__ ("lhbrx %0, 0, %1" : "=r" (lhbrxResult) : "r" (base) : "memory"); \
+ lhbrxResult; })
#define READ32LE(base) \
- ({ \
- unsigned long lwbrxResult; \
- __asm__("lwbrx %0, 0, %1" : "=r" (lwbrxResult) : "r" (base) : "memory"); \
- lwbrxResult; \
- })
+ ({ unsigned long lwbrxResult; \
+ __asm__ ("lwbrx %0, 0, %1" : "=r" (lwbrxResult) : "r" (base) : "memory"); \
+ lwbrxResult; })
-#define WRITE16LE(base, value) __asm__("sthbrx %0, 0, %1" : : "r" (value), "r" (base) : "memory")
+#define WRITE16LE(base, value) \
+ __asm__ ("sthbrx %0, 0, %1" : : "r" (value), "r" (base) : "memory")
-#define WRITE32LE(base, value) __asm__("stwbrx %0, 0, %1" : : "r" (value), "r" (base) : "memory")
-#else
+#define WRITE32LE(base, value) \
+ __asm__ ("stwbrx %0, 0, %1" : : "r" (value), "r" (base) : "memory")
+# else
// swaps a 16-bit value
inline uint16_t swap16(uint16_t v)
{
@@ -35,17 +32,15 @@
return (v << 24) | ((v << 8) & 0xff0000) | ((v >> 8) & 0xff00) | (v >> 24);
}
-template<typename T> inline uint16_t READ16LE(T *x) { return swap16(*reinterpret_cast<uint16_t *>(x)); }
-template<typename T> inline uint32_t READ32LE(T *x) { return swap32(*reinterpret_cast<uint32_t *>(x)); }
+template<typename T> inline uint16_t READ16LE(const T *x) { return swap16(*reinterpret_cast<const uint16_t *>(x)); }
+template<typename T> inline uint32_t READ32LE(const T *x) { return swap32(*reinterpret_cast<const uint32_t *>(x)); }
template<typename T> inline void WRITE16LE(T *x, uint16_t v) { *reinterpret_cast<uint16_t *>(x) = swap16(v); }
template<typename T> inline void WRITE32LE(T *x, uint32_t v) { *reinterpret_cast<uint32_t *>(x) = swap32(v); }
-#endif
+# endif
#else
-template<typename T> inline uint16_t READ16LE(T *x) { return *reinterpret_cast<uint16_t *>(x); }
-template<typename T> inline uint32_t READ32LE(T *x) { return *reinterpret_cast<uint32_t *>(x); }
+template<typename T> inline uint16_t READ16LE(const T *x) { return *reinterpret_cast<const uint16_t *>(x); }
+template<typename T> inline uint32_t READ32LE(const T *x) { return *reinterpret_cast<const uint32_t *>(x); }
template<typename T> inline void WRITE16LE(T *x, uint16_t v) { *reinterpret_cast<uint16_t *>(x) = v; }
template<typename T> inline void WRITE32LE(T *x, uint32_t v) { *reinterpret_cast<uint32_t *>(x) = v; }
#endif
-#endif // PORT_H
-
--- a/src/in_gsf/vbam/common/SoundDriver.h
+++ b/src/in_gsf/vbam/common/SoundDriver.h
@@ -15,8 +15,7 @@
// along with this program; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-#ifndef __VBA_SOUND_DRIVER_H__
-#define __VBA_SOUND_DRIVER_H__
+#pragma once
#include <cstdint>
@@ -61,5 +60,3 @@
virtual void setThrottle(unsigned short throttle) { }
};
-#endif // __VBA_SOUND_DRIVER_H__
-
--- a/src/in_gsf/vbam/gba/GBA-arm.cpp
+++ b/src/in_gsf/vbam/gba/GBA-arm.cpp
@@ -52,578 +52,6 @@
// RRX_OFFSET: Used to rotate (RRX) the `offset' parameter for LDR and
// STR instructions.
-#ifndef C_CORE
-# if 0 // definitions have changed
-//#ifdef __POWERPC__
-# define OP_SUBS \
-{ \
- register int Flags; \
- register int Result; \
- asm volatile("subco. %0, %2, %3\n" \
- "mcrxr cr1\n" \
- "mfcr %1\n" \
- : "=r" (Result), \
- "=r" (Flags) \
- : "r" (reg[base].I), \
- "r" (value) \
- ); \
- reg[dest].I = Result; \
- Z_FLAG = (Flags >> 29) & 1; \
- N_FLAG = (Flags >> 31) & 1; \
- C_FLAG = (Flags >> 25) & 1; \
- V_FLAG = (Flags >> 26) & 1; \
-}
-# define OP_RSBS \
-{ \
- register int Flags; \
- register int Result; \
- asm volatile("subfco. %0, %2, %3\n" \
- "mcrxr cr1\n" \
- "mfcr %1\n" \
- : "=r" (Result), \
- "=r" (Flags) \
- : "r" (reg[base].I), \
- "r" (value) \
- ); \
- reg[dest].I = Result; \
- Z_FLAG = (Flags >> 29) & 1; \
- N_FLAG = (Flags >> 31) & 1; \
- C_FLAG = (Flags >> 25) & 1; \
- V_FLAG = (Flags >> 26) & 1; \
-}
-# define OP_ADDS \
-{ \
- register int Flags; \
- register int Result; \
- asm volatile("addco. %0, %2, %3\n" \
- "mcrxr cr1\n" \
- "mfcr %1\n" \
- : "=r" (Result), \
- "=r" (Flags) \
- : "r" (reg[base].I), \
- "r" (value) \
- ); \
- reg[dest].I = Result; \
- Z_FLAG = (Flags >> 29) & 1; \
- N_FLAG = (Flags >> 31) & 1; \
- C_FLAG = (Flags >> 25) & 1; \
- V_FLAG = (Flags >> 26) & 1; \
-}
-# define OP_ADCS \
-{ \
- register int Flags; \
- register int Result; \
- asm volatile("mtspr xer, %4\n" \
- "addeo. %0, %2, %3\n" \
- "mcrxr cr1\n" \
- "mfcr %1\n" \
- : "=r" (Result), \
- "=r" (Flags) \
- : "r" (reg[base].I), \
- "r" (value), \
- "r" (C_FLAG << 29) \
- ); \
- reg[dest].I = Result; \
- Z_FLAG = (Flags >> 29) & 1; \
- N_FLAG = (Flags >> 31) & 1; \
- C_FLAG = (Flags >> 25) & 1; \
- V_FLAG = (Flags >> 26) & 1; \
-}
-# define OP_SBCS \
-{ \
- register int Flags; \
- register int Result; \
- asm volatile("mtspr xer, %4\n" \
- "subfeo. %0, %3, %2\n" \
- "mcrxr cr1\n" \
- "mfcr %1\n" \
- : "=r" (Result), \
- "=r" (Flags) \
- : "r" (reg[base].I), \
- "r" (value), \
- "r" (C_FLAG << 29) \
- ); \
- reg[dest].I = Result; \
- Z_FLAG = (Flags >> 29) & 1; \
- N_FLAG = (Flags >> 31) & 1; \
- C_FLAG = (Flags >> 25) & 1; \
- V_FLAG = (Flags >> 26) & 1; \
-}
-# define OP_RSCS \
-{ \
- register int Flags; \
- register int Result; \
- asm volatile("mtspr xer, %4\n"\
- "subfeo. %0, %2, %3\n" \
- "mcrxr cr1\n" \
- "mfcr %1\n" \
- : "=r" (Result), \
- "=r" (Flags) \
- : "r" (reg[base].I), \
- "r" (value), \
- "r" (C_FLAG << 29) \
- ); \
- reg[dest].I = Result; \
- Z_FLAG = (Flags >> 29) & 1; \
- N_FLAG = (Flags >> 31) & 1; \
- C_FLAG = (Flags >> 25) & 1; \
- V_FLAG = (Flags >> 26) & 1; \
-}
-# define OP_CMP \
-{ \
- register int Flags; \
- register int Result; \
- asm volatile("subco. %0, %2, %3\n" \
- "mcrxr cr1\n" \
- "mfcr %1\n" \
- : "=r" (Result), \
- "=r" (Flags) \
- : "r" (reg[base].I), \
- "r" (value) \
- ); \
- Z_FLAG = (Flags >> 29) & 1; \
- N_FLAG = (Flags >> 31) & 1; \
- C_FLAG = (Flags >> 25) & 1; \
- V_FLAG = (Flags >> 26) & 1; \
-}
-# define OP_CMN \
-{ \
- register int Flags; \
- register int Result; \
- asm volatile("addco. %0, %2, %3\n" \
- "mcrxr cr1\n" \
- "mfcr %1\n" \
- : "=r" (Result), \
- "=r" (Flags) \
- : "r" (reg[base].I), \
- "r" (value) \
- ); \
- Z_FLAG = (Flags >> 29) & 1; \
- N_FLAG = (Flags >> 31) & 1; \
- C_FLAG = (Flags >> 25) & 1; \
- V_FLAG = (Flags >> 26) & 1; \
-}
-# else // !__POWERPC__
-// Macros to emit instructions in the format used by the particular compiler.
-// We use GNU assembler syntax: "op src, dest" rather than "op dest, src"
-
-# ifdef __GNUC__
-# define ALU_HEADER asm("mov %%ecx, %%edi; "
-# define ALU_TRAILER : "=D" (opcode) : "c" (opcode) : "eax", "ebx", "edx", "esi")
-# define EMIT0(op) #op "; "
-# define EMIT1(op, arg) #op " " arg "; "
-# define EMIT2(op, src, dest) #op " " src ", " dest "; "
-# define KONST(val) "$" #val
-# define ASMVAR(cvar) ASMVAR2(__USER_LABEL_PREFIX__, cvar)
-# define ASMVAR2(prefix, cvar) STRING(prefix) cvar
-# define STRING(x) #x
-# define VAR(var) ASMVAR(#var)
-# define VARL(var) ASMVAR(#var)
-# define REGREF1(index) ASMVAR("reg(" index ")")
-# define REGREF2(index, scale) ASMVAR("reg(," index "," #scale ")")
-# define LABEL(n) #n ": "
-# define LABELREF(n, dir) #n#dir
-# define al "%%al"
-# define ah "%%ah"
-# define eax "%%eax"
-# define bl "%%bl"
-# define bh "%%bh"
-# define ebx "%%ebx"
-# define cl "%%cl"
-# define ch "%%ch"
-# define ecx "%%ecx"
-# define dl "%%dl"
-# define dh "%%dh"
-# define edx "%%edx"
-# define esp "%%esp"
-# define ebp "%%ebp"
-# define esi "%%esi"
-# define edi "%%edi"
-# define movzx movzb
-# else
-# define ALU_HEADER __asm { __asm mov ecx, opcode
-# define ALU_TRAILER }
-# define EMIT0(op) __asm op
-# define EMIT1(op, arg) __asm op arg
-# define EMIT2(op, src, dest) __asm op dest, src
-# define KONST(val) val
-# define VAR(var) var
-# define VARL(var) dword ptr var
-# define REGREF1(index) reg[index]
-# define REGREF2(index, scale) reg[index * scale]
-# define LABEL(n) __asm l##n:
-# define LABELREF(n, dir) l##n
-# endif
-
-//X//#ifndef _MSC_VER
-// ALU op register usage:
-// EAX -> 2nd operand value, result (RSB/RSC)
-// EBX -> C_OUT (carry flag from shift/rotate)
-// ECX -> opcode (input), shift/rotate count
-// EDX -> Rn (base) value, result (all except RSB/RSC)
-// ESI -> Rd (destination) index * 4
-
-// Helper macros for loading value / shift count
-# define VALUE_LOAD_IMM \
- EMIT2(and, KONST(0x0F), eax) \
- EMIT2(mov, REGREF2(eax, 4), eax) \
- EMIT2(shr, KONST(7), ecx) \
- EMIT2(and, KONST(0x1F), ecx)
-# define VALUE_LOAD_REG \
- EMIT2(and, KONST(0x0F), eax) \
- EMIT2(cmp, KONST(0x0F), eax) \
- EMIT2(mov, REGREF2(eax, 4), eax) \
- EMIT1(jne, LABELREF(3, f)) \
- EMIT2(add, KONST(4), eax) \
- LABEL(3) \
- EMIT2(movzx, ch, ecx) \
- EMIT2(and, KONST(0x0F), ecx) \
- EMIT2(mov, REGREF2(ecx, 4), ecx)
-
-// Helper macros for setting flags
-# define SETCOND_LOGICAL \
- EMIT1(sets, VAR(N_FLAG)) \
- EMIT1(setz, VAR(Z_FLAG)) \
- EMIT2(mov, bl, VAR(C_FLAG))
-# define SETCOND_ADD \
- EMIT1(sets, VAR(N_FLAG)) \
- EMIT1(setz, VAR(Z_FLAG)) \
- EMIT1(seto, VAR(V_FLAG)) \
- EMIT1(setc, VAR(C_FLAG))
-# define SETCOND_SUB \
- EMIT1(sets, VAR(N_FLAG)) \
- EMIT1(setz, VAR(Z_FLAG)) \
- EMIT1(seto, VAR(V_FLAG)) \
- EMIT1(setnc, VAR(C_FLAG))
-
-// ALU initialization
-# define ALU_INIT(LOAD_C_FLAG) \
- ALU_HEADER \
- LOAD_C_FLAG \
- EMIT2(mov, ecx, edx) \
- EMIT2(shr, KONST(14), edx) \
- EMIT2(mov, ecx, eax) \
- EMIT2(mov, ecx, esi) \
- EMIT2(shr, KONST(10), esi) \
- EMIT2(and, KONST(0x3C), edx) \
- EMIT2(mov, REGREF1(edx), edx) \
- EMIT2(and, KONST(0x3C), esi)
-
-# define LOAD_C_FLAG_YES EMIT2(mov, VAR(C_FLAG), bl)
-# define LOAD_C_FLAG_NO /*nothing*/
-# define ALU_INIT_C ALU_INIT(LOAD_C_FLAG_YES)
-# define ALU_INIT_NC ALU_INIT(LOAD_C_FLAG_NO)
-
-// Macros to load the value operand for an ALU op; these all set N/Z
-// according to the value
-
-// OP Rd,Rb,Rm LSL #
-# define VALUE_LSL_IMM_C \
- VALUE_LOAD_IMM \
- EMIT1(jnz, LABELREF(1, f)) \
- EMIT1(jmp, LABELREF(0, f)) \
- LABEL(1) \
- EMIT2(shl, cl, eax) \
- EMIT1(setc, bl) \
- LABEL(0)
-# define VALUE_LSL_IMM_NC \
- VALUE_LOAD_IMM \
- EMIT2(shl, cl, eax)
-
-// OP Rd,Rb,Rm LSL Rs
-# define VALUE_LSL_REG_C \
- VALUE_LOAD_REG \
- EMIT2(test, cl, cl) \
- EMIT1(jz, LABELREF(0, f)) \
- EMIT2(cmp, KONST(0x20), cl) \
- EMIT1(je, LABELREF(1, f)) \
- EMIT1(ja, LABELREF(2, f)) \
- EMIT2(shl, cl, eax) \
- EMIT1(setc, bl) \
- EMIT1(jmp, LABELREF(0, f)) \
- LABEL(1) \
- EMIT2(test, KONST(1), al) \
- EMIT1(setnz, bl) \
- EMIT2(xor, eax, eax) \
- EMIT1(jmp, LABELREF(0, f)) \
- LABEL(2) \
- EMIT2(xor, ebx, ebx) \
- EMIT2(xor, eax, eax) \
- LABEL(0)
-# define VALUE_LSL_REG_NC \
- VALUE_LOAD_REG \
- EMIT2(cmp, KONST(0x20), cl) \
- EMIT1(jae, LABELREF(1, f)) \
- EMIT2(shl, cl, eax) \
- EMIT1(jmp, LABELREF(0, f)) \
- LABEL(1) \
- EMIT2(xor, eax, eax) \
- LABEL(0)
-
-// OP Rd,Rb,Rm LSR #
-# define VALUE_LSR_IMM_C \
- VALUE_LOAD_IMM \
- EMIT1(jz, LABELREF(1, f)) \
- EMIT2(shr, cl, eax) \
- EMIT1(setc, bl) \
- EMIT1(jmp, LABELREF(0, f)) \
- LABEL(1) \
- EMIT2(test, eax, eax) \
- EMIT1(sets, bl) \
- EMIT2(xor, eax, eax) \
- LABEL(0)
-# define VALUE_LSR_IMM_NC \
- VALUE_LOAD_IMM \
- EMIT1(jz, LABELREF(1, f)) \
- EMIT2(shr, cl, eax) \
- EMIT1(jmp, LABELREF(0, f)) \
- LABEL(1) \
- EMIT2(xor, eax, eax) \
- LABEL(0)
-
-// OP Rd,Rb,Rm LSR Rs
-# define VALUE_LSR_REG_C \
- VALUE_LOAD_REG \
- EMIT2(test, cl, cl) \
- EMIT1(jz, LABELREF(0, f)) \
- EMIT2(cmp, KONST(0x20), cl) \
- EMIT1(je, LABELREF(1, f)) \
- EMIT1(ja, LABELREF(2, f)) \
- EMIT2(shr, cl, eax) \
- EMIT1(setc, bl) \
- EMIT1(jmp, LABELREF(0, f)) \
- LABEL(1) \
- EMIT2(test, eax, eax) \
- EMIT1(sets, bl) \
- EMIT2(xor, eax, eax) \
- EMIT1(jmp, LABELREF(0, f)) \
- LABEL(2) \
- EMIT2(xor, ebx, ebx) \
- EMIT2(xor, eax, eax) \
- LABEL(0)
-# define VALUE_LSR_REG_NC \
- VALUE_LOAD_REG \
- EMIT2(cmp, KONST(0x20), cl) \
- EMIT1(jae, LABELREF(1, f)) \
- EMIT2(shr, cl, eax) \
- EMIT1(jmp, LABELREF(0, f)) \
- LABEL(1) \
- EMIT2(xor, eax, eax) \
- LABEL(0)
-
-// OP Rd,Rb,Rm ASR #
-# define VALUE_ASR_IMM_C \
- VALUE_LOAD_IMM \
- EMIT1(jz, LABELREF(1, f)) \
- EMIT2(sar, cl, eax) \
- EMIT1(setc, bl) \
- EMIT1(jmp, LABELREF(0, f)) \
- LABEL(1) \
- EMIT2(sar, KONST(31), eax) \
- EMIT1(sets, bl) \
- LABEL(0)
-# define VALUE_ASR_IMM_NC \
- VALUE_LOAD_IMM \
- EMIT1(jz, LABELREF(1, f)) \
- EMIT2(sar, cl, eax) \
- EMIT1(jmp, LABELREF(0, f)) \
- LABEL(1) \
- EMIT2(sar, KONST(31), eax) \
- LABEL(0)
-
-// OP Rd,Rb,Rm ASR Rs
-# define VALUE_ASR_REG_C \
- VALUE_LOAD_REG \
- EMIT2(test, cl, cl) \
- EMIT1(jz, LABELREF(0, f)) \
- EMIT2(cmp, KONST(0x20), cl) \
- EMIT1(jae, LABELREF(1, f)) \
- EMIT2(sar, cl, eax) \
- EMIT1(setc, bl) \
- EMIT1(jmp, LABELREF(0, f)) \
- LABEL(1) \
- EMIT2(sar, KONST(31), eax) \
- EMIT1(sets, bl) \
- LABEL(0)
-# define VALUE_ASR_REG_NC \
- VALUE_LOAD_REG \
- EMIT2(cmp, KONST(0x20), cl) \
- EMIT1(jae, LABELREF(1, f)) \
- EMIT2(sar, cl, eax) \
- EMIT1(jmp, LABELREF(0, f)) \
- LABEL(1) \
- EMIT2(sar, KONST(31), eax) \
- LABEL(0)
-
-// OP Rd,Rb,Rm ROR #
-# define VALUE_ROR_IMM_C \
- VALUE_LOAD_IMM \
- EMIT1(jz, LABELREF(1, f)) \
- EMIT2(ror, cl, eax) \
- EMIT1(jmp, LABELREF(0, f)) \
- LABEL(1) \
- EMIT2(bt, KONST(0), ebx) \
- EMIT2(rcr, KONST(1), eax) \
- LABEL(0) \
- EMIT1(setc, bl)
-# define VALUE_ROR_IMM_NC \
- VALUE_LOAD_IMM \
- EMIT1(jz, LABELREF(1, f)) \
- EMIT2(ror, cl, eax) \
- EMIT1(jmp, LABELREF(0, f)) \
- LABEL(1) \
- EMIT2(bt, KONST(0), VARL(C_FLAG)) \
- EMIT2(rcr, KONST(1), eax) \
- LABEL(0)
-
-// OP Rd,Rb,Rm ROR Rs
-# define VALUE_ROR_REG_C \
- VALUE_LOAD_REG \
- EMIT2(bt, KONST(0), ebx) \
- EMIT2(ror, cl, eax) \
- EMIT1(setc, bl)
-# define VALUE_ROR_REG_NC \
- VALUE_LOAD_REG \
- EMIT2(ror, cl, eax)
-
-// OP Rd,Rb,# ROR #
-# define VALUE_IMM_C \
- EMIT2(movzx, ch, ecx) \
- EMIT2(add, ecx, ecx) \
- EMIT2(movzx, al, eax) \
- EMIT2(bt, KONST(0), ebx) \
- EMIT2(ror, cl, eax) \
- EMIT1(setc, bl)
-# define VALUE_IMM_NC \
- EMIT2(movzx, ch, ecx) \
- EMIT2(add, ecx, ecx) \
- EMIT2(movzx, al, eax) \
- EMIT2(ror, cl, eax)
-
-// Macros to perform ALU ops
-
-// Set condition codes iff the destination register is not R15 (PC)
-# define CHECK_PC(OP, SETCOND) \
- EMIT2(cmp, KONST(0x3C), esi) \
- EMIT1(je, LABELREF(8, f)) \
- OP SETCOND \
- EMIT1(jmp, LABELREF(9, f)) \
- LABEL(8) \
- OP \
- LABEL(9)
-
-# define OP_AND \
- EMIT2(and, eax, edx) \
- EMIT2(mov, edx, REGREF1(esi))
-# define OP_ANDS CHECK_PC(OP_AND, SETCOND_LOGICAL)
-# define OP_EOR \
- EMIT2(xor, eax, edx) \
- EMIT2(mov, edx, REGREF1(esi))
-# define OP_EORS CHECK_PC(OP_EOR, SETCOND_LOGICAL)
-# define OP_SUB \
- EMIT2(sub, eax, edx) \
- EMIT2(mov, edx, REGREF1(esi))
-# define OP_SUBS CHECK_PC(OP_SUB, SETCOND_SUB)
-# define OP_RSB \
- EMIT2(sub, edx, eax) \
- EMIT2(mov, eax, REGREF1(esi))
-# define OP_RSBS CHECK_PC(OP_RSB, SETCOND_SUB)
-# define OP_ADD \
- EMIT2(add, eax, edx) \
- EMIT2(mov, edx, REGREF1(esi))
-# define OP_ADDS CHECK_PC(OP_ADD, SETCOND_ADD)
-# define OP_ADC \
- EMIT2(bt, KONST(0), VARL(C_FLAG)) \
- EMIT2(adc, eax, edx) \
- EMIT2(mov, edx, REGREF1(esi))
-# define OP_ADCS CHECK_PC(OP_ADC, SETCOND_ADD)
-# define OP_SBC \
- EMIT2(bt, KONST(0), VARL(C_FLAG)) \
- EMIT0(cmc) \
- EMIT2(sbb, eax, edx) \
- EMIT2(mov, edx, REGREF1(esi))
-# define OP_SBCS CHECK_PC(OP_SBC, SETCOND_SUB)
-# define OP_RSC \
- EMIT2(bt, KONST(0), VARL(C_FLAG)) \
- EMIT0(cmc) \
- EMIT2(sbb, edx, eax) \
- EMIT2(mov, eax, REGREF1(esi))
-# define OP_RSCS CHECK_PC(OP_RSC, SETCOND_SUB)
-# define OP_TST \
- EMIT2(and, eax, edx) \
- SETCOND_LOGICAL
-# define OP_TEQ \
- EMIT2(xor, eax, edx) \
- SETCOND_LOGICAL
-# define OP_CMP \
- EMIT2(sub, eax, edx) \
- SETCOND_SUB
-# define OP_CMN \
- EMIT2(add, eax, edx) \
- SETCOND_ADD
-# define OP_ORR \
- EMIT2(or, eax, edx) \
- EMIT2(mov, edx, REGREF1(esi))
-# define OP_ORRS CHECK_PC(OP_ORR, SETCOND_LOGICAL)
-# define OP_MOV \
- EMIT2(mov, eax, REGREF1(esi))
-# define OP_MOVS CHECK_PC(EMIT2(test, eax, eax) EMIT2(mov, eax, REGREF1(esi)), SETCOND_LOGICAL)
-# define OP_BIC \
- EMIT1(not, eax) \
- EMIT2(and, eax, edx) \
- EMIT2(mov, edx, REGREF1(esi))
-# define OP_BICS CHECK_PC(OP_BIC, SETCOND_LOGICAL)
-# define OP_MVN \
- EMIT1(not, eax) \
- EMIT2(mov, eax, REGREF1(esi))
-# define OP_MVNS CHECK_PC(OP_MVN EMIT2(test, eax, eax), SETCOND_LOGICAL)
-
-// ALU cleanup macro
-# define ALU_FINISH ALU_TRAILER
-
-// End of ALU macros
-//X//#endif //_MSC_VER
-# ifdef __GNUC__
-# define ROR_IMM_MSR \
- asm("ror %%cl, %%eax;" \
- : "=a" (value) \
- : "a" (opcode & 0xFF), "c" (shift));
-
-# define ROR_OFFSET \
- asm("ror %%cl, %0" \
- : "=r" (offset) \
- : "0" (offset), "c" (shift));
-
-# define RRX_OFFSET \
- asm(EMIT2(btl, KONST(0), VAR(C_FLAG)) \
- "rcr $1, %0" \
- : "=r" (offset) \
- : "0" (offset));
-# else // !__GNUC__, i.e. Visual C++
-# define ROR_IMM_MSR \
- __asm \
- { \
- __asm mov ecx, shift \
- __asm ror value, cl \
- }
-
-# define ROR_OFFSET \
- __asm \
- { \
- __asm mov ecx, shift \
- __asm ror offset, cl \
- }
-
-# define RRX_OFFSET \
- __asm \
- { \
- __asm bt dword ptr C_FLAG, 0 \
- __asm rcr offset, 1 \
- }
-# endif // !__GNUC__
-# endif // !__POWERPC__
-#endif // !C_CORE
-
// C core
#define C_SETCOND_LOGICAL \
@@ -641,15 +69,12 @@
V_FLAG = !!((NEG(lhs) & POS(rhs) & POS(res)) | (POS(lhs) & NEG(rhs) & NEG(res))); \
C_FLAG = !!((NEG(lhs) & POS(rhs)) | (NEG(lhs) & POS(res)) | (POS(rhs) & POS(res)));
-#ifndef ALU_INIT_C
-# define ALU_INIT_C \
+#define ALU_INIT_C \
int dest = (opcode >> 12) & 15; \
bool C_OUT = C_FLAG; \
uint32_t value;
-#endif
// OP Rd,Rb,Rm LSL #
-#ifndef VALUE_LSL_IMM_C
-# define VALUE_LSL_IMM_C \
+#define VALUE_LSL_IMM_C \
unsigned shift = (opcode >> 7) & 0x1F; \
if (LIKELY(!shift)) /* LSL #0 most common? */ \
value = reg[opcode & 0x0F].I; \
@@ -659,10 +84,8 @@
C_OUT = !!((v >> (32 - shift)) & 1); \
value = v << shift; \
}
-#endif
// OP Rd,Rb,Rm LSL Rs
-#ifndef VALUE_LSL_REG_C
-# define VALUE_LSL_REG_C \
+#define VALUE_LSL_REG_C \
uint32_t shift = reg[(opcode >> 8) & 15].B.B0; \
uint32_t rm = reg[opcode & 0x0F].I; \
if ((opcode & 0x0F) == 15) \
@@ -688,10 +111,8 @@
} \
else \
value = rm;
-#endif
// OP Rd,Rb,Rm LSR #
-#ifndef VALUE_LSR_IMM_C
-# define VALUE_LSR_IMM_C \
+#define VALUE_LSR_IMM_C \
uint32_t shift = (opcode >> 7) & 0x1F; \
if (LIKELY(shift)) \
{ \
@@ -704,10 +125,8 @@
value = 0; \
C_OUT = !!(reg[opcode & 0x0F].I & 0x80000000); \
}
-#endif
// OP Rd,Rb,Rm LSR Rs
-#ifndef VALUE_LSR_REG_C
-# define VALUE_LSR_REG_C \
+#define VALUE_LSR_REG_C \
unsigned shift = reg[(opcode >> 8) & 15].B.B0; \
uint32_t rm = reg[opcode & 0x0F].I; \
if ((opcode & 0x0F) == 15) \
@@ -733,10 +152,8 @@
} \
else \
value = rm;
-#endif
// OP Rd,Rb,Rm ASR #
-#ifndef VALUE_ASR_IMM_C
-# define VALUE_ASR_IMM_C \
+#define VALUE_ASR_IMM_C \
unsigned shift = (opcode >> 7) & 0x1F; \
if (LIKELY(shift)) \
{ \
@@ -758,10 +175,8 @@
C_OUT = false; \
} \
}
-#endif
// OP Rd,Rb,Rm ASR Rs
-#ifndef VALUE_ASR_REG_C
-# define VALUE_ASR_REG_C \
+#define VALUE_ASR_REG_C \
unsigned shift = reg[(opcode >> 8) & 15].B.B0; \
uint32_t rm = reg[opcode & 0x0F].I; \
if ((opcode & 0x0F) == 15) \
@@ -790,10 +205,8 @@
C_OUT = false; \
} \
}
-#endif
// OP Rd,Rb,Rm ROR #
-#ifndef VALUE_ROR_IMM_C
-# define VALUE_ROR_IMM_C \
+#define VALUE_ROR_IMM_C \
unsigned shift = (opcode >> 7) & 0x1F; \
uint32_t v = reg[opcode & 0x0F].I; \
if (LIKELY(shift)) \
@@ -806,10 +219,8 @@
C_OUT = !!(v & 1); \
value = (v >> 1) | (C_FLAG << 31); \
}
-#endif
// OP Rd,Rb,Rm ROR Rs
-#ifndef VALUE_ROR_REG_C
-# define VALUE_ROR_REG_C \
+#define VALUE_ROR_REG_C \
unsigned shift = reg[(opcode >> 8) & 15].B.B0; \
uint32_t rm = reg[opcode & 0x0F].I; \
if ((opcode & 0x0F) == 15) \
@@ -826,10 +237,8 @@
if (shift) \
C_OUT = !!(value & 0x80000000); \
}
-#endif
// OP Rd,Rb,# ROR #
-#ifndef VALUE_IMM_C
-# define VALUE_IMM_C \
+#define VALUE_IMM_C \
int shift = (opcode & 0xF00) >> 7; \
if (UNLIKELY(shift)) \
{ \
@@ -839,206 +248,115 @@
} \
else \
value = opcode & 0xFF;
-#endif
// Make the non-carry versions default to the carry versions
// (this is fine for C--the compiler will optimize the dead code out)
-#ifndef ALU_INIT_NC
-# define ALU_INIT_NC ALU_INIT_C
-#endif
-#ifndef VALUE_LSL_IMM_NC
-# define VALUE_LSL_IMM_NC VALUE_LSL_IMM_C
-#endif
-#ifndef VALUE_LSL_REG_NC
-# define VALUE_LSL_REG_NC VALUE_LSL_REG_C
-#endif
-#ifndef VALUE_LSR_IMM_NC
-# define VALUE_LSR_IMM_NC VALUE_LSR_IMM_C
-#endif
-#ifndef VALUE_LSR_REG_NC
-# define VALUE_LSR_REG_NC VALUE_LSR_REG_C
-#endif
-#ifndef VALUE_ASR_IMM_NC
-# define VALUE_ASR_IMM_NC VALUE_ASR_IMM_C
-#endif
-#ifndef VALUE_ASR_REG_NC
-# define VALUE_ASR_REG_NC VALUE_ASR_REG_C
-#endif
-#ifndef VALUE_ROR_IMM_NC
-# define VALUE_ROR_IMM_NC VALUE_ROR_IMM_C
-#endif
-#ifndef VALUE_ROR_REG_NC
-# define VALUE_ROR_REG_NC VALUE_ROR_REG_C
-#endif
-#ifndef VALUE_IMM_NC
-# define VALUE_IMM_NC VALUE_IMM_C
-#endif
+#define ALU_INIT_NC ALU_INIT_C
+#define VALUE_LSL_IMM_NC VALUE_LSL_IMM_C
+#define VALUE_LSL_REG_NC VALUE_LSL_REG_C
+#define VALUE_LSR_IMM_NC VALUE_LSR_IMM_C
+#define VALUE_LSR_REG_NC VALUE_LSR_REG_C
+#define VALUE_ASR_IMM_NC VALUE_ASR_IMM_C
+#define VALUE_ASR_REG_NC VALUE_ASR_REG_C
+#define VALUE_ROR_IMM_NC VALUE_ROR_IMM_C
+#define VALUE_ROR_REG_NC VALUE_ROR_REG_C
+#define VALUE_IMM_NC VALUE_IMM_C
#define C_CHECK_PC(SETCOND) if (LIKELY(dest != 15)) { SETCOND }
-#ifndef OP_AND
-# define OP_AND \
+#define OP_AND \
uint32_t res = reg[(opcode >> 16) & 15].I & value; \
- reg[dest].I = res;
-#endif
-#ifndef OP_ANDS
-# define OP_ANDS OP_AND C_CHECK_PC(C_SETCOND_LOGICAL)
-#endif
-#ifndef OP_EOR
-# define OP_EOR \
+ reg[dest].I = res;
+#define OP_ANDS OP_AND C_CHECK_PC(C_SETCOND_LOGICAL)
+#define OP_EOR \
uint32_t res = reg[(opcode >> 16) & 15].I ^ value; \
reg[dest].I = res;
-#endif
-#ifndef OP_EORS
-# define OP_EORS OP_EOR C_CHECK_PC(C_SETCOND_LOGICAL)
-#endif
-#ifndef OP_SUB
-# define OP_SUB \
+#define OP_EORS OP_EOR C_CHECK_PC(C_SETCOND_LOGICAL)
+#define OP_SUB \
uint32_t lhs = reg[(opcode >> 16) & 15].I; \
uint32_t rhs = value; \
uint32_t res = lhs - rhs; \
reg[dest].I = res;
-#endif
-#ifndef OP_SUBS
-# define OP_SUBS OP_SUB C_CHECK_PC(C_SETCOND_SUB)
-#endif
-#ifndef OP_RSB
-# define OP_RSB \
+#define OP_SUBS OP_SUB C_CHECK_PC(C_SETCOND_SUB)
+#define OP_RSB \
uint32_t lhs = value; \
uint32_t rhs = reg[(opcode >> 16) & 15].I; \
uint32_t res = lhs - rhs; \
reg[dest].I = res;
-#endif
-#ifndef OP_RSBS
-# define OP_RSBS OP_RSB C_CHECK_PC(C_SETCOND_SUB)
-#endif
-#ifndef OP_ADD
-# define OP_ADD \
+#define OP_RSBS OP_RSB C_CHECK_PC(C_SETCOND_SUB)
+#define OP_ADD \
uint32_t lhs = reg[(opcode >> 16) & 15].I; \
uint32_t rhs = value; \
uint32_t res = lhs + rhs; \
reg[dest].I = res;
-#endif
-#ifndef OP_ADDS
-# define OP_ADDS OP_ADD C_CHECK_PC(C_SETCOND_ADD)
-#endif
-#ifndef OP_ADC
-# define OP_ADC \
+#define OP_ADDS OP_ADD C_CHECK_PC(C_SETCOND_ADD)
+#define OP_ADC \
uint32_t lhs = reg[(opcode >> 16) & 15].I; \
uint32_t rhs = value; \
uint32_t res = lhs + rhs + static_cast<uint32_t>(C_FLAG); \
reg[dest].I = res;
-#endif
-#ifndef OP_ADCS
-# define OP_ADCS OP_ADC C_CHECK_PC(C_SETCOND_ADD)
-#endif
-#ifndef OP_SBC
-# define OP_SBC \
+#define OP_ADCS OP_ADC C_CHECK_PC(C_SETCOND_ADD)
+#define OP_SBC \
uint32_t lhs = reg[(opcode >> 16) & 15].I; \
uint32_t rhs = value; \
uint32_t res = lhs - rhs - !static_cast<uint32_t>(C_FLAG); \
reg[dest].I = res;
-#endif
-#ifndef OP_SBCS
-# define OP_SBCS OP_SBC C_CHECK_PC(C_SETCOND_SUB)
-#endif
-#ifndef OP_RSC
-# define OP_RSC \
+#define OP_SBCS OP_SBC C_CHECK_PC(C_SETCOND_SUB)
+#define OP_RSC \
uint32_t lhs = value; \
uint32_t rhs = reg[(opcode >> 16) & 15].I; \
uint32_t res = lhs - rhs - !static_cast<uint32_t>(C_FLAG); \
reg[dest].I = res;
-#endif
-#ifndef OP_RSCS
-# define OP_RSCS OP_RSC C_CHECK_PC(C_SETCOND_SUB)
-#endif
-#ifndef OP_TST
-# define OP_TST \
+#define OP_RSCS OP_RSC C_CHECK_PC(C_SETCOND_SUB)
+#define OP_TST \
uint32_t res = reg[(opcode >> 16) & 0x0F].I & value; \
C_SETCOND_LOGICAL;
-#endif
-#ifndef OP_TEQ
-# define OP_TEQ \
+#define OP_TEQ \
uint32_t res = reg[(opcode >> 16) & 0x0F].I ^ value; \
C_SETCOND_LOGICAL;
-#endif
-#ifndef OP_CMP
-# define OP_CMP \
+#define OP_CMP \
uint32_t lhs = reg[(opcode >> 16) & 15].I; \
uint32_t rhs = value; \
uint32_t res = lhs - rhs; \
C_SETCOND_SUB;
-#endif
-#ifndef OP_CMN
-# define OP_CMN \
+#define OP_CMN \
uint32_t lhs = reg[(opcode >> 16) & 15].I; \
uint32_t rhs = value; \
uint32_t res = lhs + rhs; \
C_SETCOND_ADD;
-#endif
-#ifndef OP_ORR
-# define OP_ORR \
+#define OP_ORR \
uint32_t res = reg[(opcode >> 16) & 0x0F].I | value; \
reg[dest].I = res;
-#endif
-#ifndef OP_ORRS
-# define OP_ORRS OP_ORR C_CHECK_PC(C_SETCOND_LOGICAL)
-#endif
-#ifndef OP_MOV
-# define OP_MOV \
+#define OP_ORRS OP_ORR C_CHECK_PC(C_SETCOND_LOGICAL)
+#define OP_MOV \
uint32_t res = value; \
reg[dest].I = res;
-#endif
-#ifndef OP_MOVS
-# define OP_MOVS OP_MOV C_CHECK_PC(C_SETCOND_LOGICAL)
-#endif
-#ifndef OP_BIC
-# define OP_BIC \
+#define OP_MOVS OP_MOV C_CHECK_PC(C_SETCOND_LOGICAL)
+#define OP_BIC \
uint32_t res = reg[(opcode >> 16) & 0x0F].I & ~value; \
reg[dest].I = res;
-#endif
-#ifndef OP_BICS
-# define OP_BICS OP_BIC C_CHECK_PC(C_SETCOND_LOGICAL)
-#endif
-#ifndef OP_MVN
-# define OP_MVN \
+#define OP_BICS OP_BIC C_CHECK_PC(C_SETCOND_LOGICAL)
+#define OP_MVN \
uint32_t res = ~value; \
reg[dest].I = res;
-#endif
-#ifndef OP_MVNS
-# define OP_MVNS OP_MVN C_CHECK_PC(C_SETCOND_LOGICAL)
-#endif
-
-#ifndef SETCOND_NONE
-# define SETCOND_NONE /*nothing*/
-#endif
-#ifndef SETCOND_MUL
-# define SETCOND_MUL \
+#define OP_MVNS OP_MVN C_CHECK_PC(C_SETCOND_LOGICAL)
+
+#define SETCOND_NONE /*nothing*/
+#define SETCOND_MUL \
N_FLAG = static_cast<int32_t>(reg[dest].I) < 0; \
Z_FLAG = !reg[dest].I;
-#endif
-#ifndef SETCOND_MULL
-# define SETCOND_MULL \
+#define SETCOND_MULL \
N_FLAG = !!(reg[dest].I & 0x80000000); \
Z_FLAG = !(reg[dest].I || reg[acc].I);
-#endif
-
-#ifndef ALU_FINISH
-# define ALU_FINISH /*nothing*/
-#endif
-
-#ifndef ROR_IMM_MSR
-# define ROR_IMM_MSR \
+
+#define ALU_FINISH /*nothing*/
+
+#define ROR_IMM_MSR \
uint32_t v = opcode & 0xff; \
value = (v << (32 - shift)) | (v >> shift);
-#endif
-#ifndef ROR_OFFSET
-# define ROR_OFFSET \
+#define ROR_OFFSET \
offset = (offset << (32 - shift)) | (offset >> shift);
-#endif
-#ifndef RRX_OFFSET
-# define RRX_OFFSET \
+#define RRX_OFFSET \
offset = (offset >> 1) | (static_cast<int>(C_FLAG) << 31);
-#endif
// ALU ops (except multiply) //////////////////////////////////////////////
@@ -1461,13 +779,9 @@
int shift = (opcode >> 7) & 31; \
uint32_t offset = reg[opcode & 15].I; \
if (shift) \
- { \
- ROR_OFFSET; \
- } \
+ ROR_OFFSET \
else \
- { \
- RRX_OFFSET; \
- }
+ RRX_OFFSET
#define ADDRESS_POST (reg[base].I)
#define ADDRESS_PREDEC (reg[base].I - offset)
@@ -2241,9 +1555,9 @@
if (!busPrefetchCount)
busPrefetch = busPrefetchEnable;
int base = (opcode & 0x000F0000) >> 16;
+ uint32_t address = reg[base].I & 0xFFFFFFFC;
+ int count = 0;
uint32_t temp = reg[base].I + 4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]);
- uint32_t address = reg[base].I & 0xFFFFFFFC;
- int count = 0;
STMW_ALL;
clockTicks += 1 + codeTicksAccess32(armNextPC);
}
@@ -2294,9 +1608,9 @@
if (!busPrefetchCount)
busPrefetch = busPrefetchEnable;
int base = (opcode & 0x000F0000) >> 16;
+ uint32_t address = reg[base].I & 0xFFFFFFFC;
+ int count = 0;
uint32_t temp = reg[base].I + 4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]);
- uint32_t address = reg[base].I & 0xFFFFFFFC;
- int count = 0;
STMW_ALL_2;
clockTicks += 1 + codeTicksAccess32(armNextPC);
}
@@ -2457,9 +1771,9 @@
if (!busPrefetchCount)
busPrefetch = busPrefetchEnable;
int base = (opcode & 0x000F0000) >> 16;
+ uint32_t address = (reg[base].I + 4) & 0xFFFFFFFC;
+ int count = 0;
uint32_t temp = reg[base].I + 4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]);
- uint32_t address = (reg[base].I + 4) & 0xFFFFFFFC;
- int count = 0;
STMW_ALL;
clockTicks += 1 + codeTicksAccess32(armNextPC);
}
@@ -2510,9 +1824,9 @@
if (!busPrefetchCount)
busPrefetch = busPrefetchEnable;
int base = (opcode & 0x000F0000) >> 16;
+ uint32_t address = (reg[base].I + 4) & 0xFFFFFFFC;
+ int count = 0;
uint32_t temp = reg[base].I + 4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]);
- uint32_t address = (reg[base].I + 4) & 0xFFFFFFFC;
- int count = 0;
STMW_ALL_2;
clockTicks += 1 + codeTicksAccess32(armNextPC);
}
@@ -2766,7 +2080,7 @@
REP16(arm_UI),REP16(arm_UI),REP16(arm_UI),REP16(arm_UI), // E80
REP16(arm_UI),REP16(arm_UI),REP16(arm_UI),REP16(arm_UI), // EC0
- REP256(armF00), // F00
+ REP256(armF00) // F00
};
// Wrapper routine (execution loop) ///////////////////////////////////////
--- a/src/in_gsf/vbam/gba/GBA-thumb.cpp
+++ b/src/in_gsf/vbam/gba/GBA-thumb.cpp
@@ -19,671 +19,27 @@
template<typename T> static inline T NEG(const T &i) { return i >> 31; }
template<typename T> static inline T POS(const T &i) { return ~i >> 31; }
-#ifndef C_CORE
-# ifdef __GNUC__
-# ifdef __POWERPC__
-# define ADD_RD_RS_RN(N) \
-{ \
- register int Flags; \
- register int Result; \
- asm volatile("addco. %0, %2, %3\n" \
- "mcrxr cr1\n" \
- "mfcr %1\n" \
- : "=r" (Result), \
- "=r" (Flags) \
- : "r" (reg[source].I), \
- "r" (reg[N].I) \
- ); \
- reg[dest].I = Result; \
- Z_FLAG = (Flags >> 29) & 1; \
- N_FLAG = (Flags >> 31) & 1; \
- C_FLAG = (Flags >> 25) & 1; \
- V_FLAG = (Flags >> 26) & 1; \
-}
-# define ADD_RD_RS_O3(N) \
-{ \
- register int Flags; \
- register int Result; \
- asm volatile("addco. %0, %2, %3\n" \
- "mcrxr cr1\n" \
- "mfcr %1\n" \
- : "=r" (Result), \
- "=r" (Flags) \
- : "r" (reg[source].I), \
- "r" (N) \
- ); \
- reg[dest].I = Result; \
- Z_FLAG = (Flags >> 29) & 1; \
- N_FLAG = (Flags >> 31) & 1; \
- C_FLAG = (Flags >> 25) & 1; \
- V_FLAG = (Flags >> 26) & 1; \
-}
-# define ADD_RD_RS_O3_0 ADD_RD_RS_O3
-# define ADD_RN_O8(d) \
-{ \
- register int Flags; \
- register int Result; \
- asm volatile("addco. %0, %2, %3\n" \
- "mcrxr cr1\n" \
- "mfcr %1\n" \
- : "=r" (Result), \
- "=r" (Flags) \
- : "r" (reg[(d)].I), \
- "r" (opcode & 255) \
- ); \
- reg[(d)].I = Result; \
- Z_FLAG = (Flags >> 29) & 1; \
- N_FLAG = (Flags >> 31) & 1; \
- C_FLAG = (Flags >> 25) & 1; \
- V_FLAG = (Flags >> 26) & 1; \
-}
-# define CMN_RD_RS \
-{ \
- register int Flags; \
- register int Result; \
- asm volatile("addco. %0, %2, %3\n" \
- "mcrxr cr1\n" \
- "mfcr %1\n" \
- : "=r" (Result), \
- "=r" (Flags) \
- : "r" (reg[dest].I), \
- "r" (value) \
- ); \
- Z_FLAG = (Flags >> 29) & 1; \
- N_FLAG = (Flags >> 31) & 1; \
- C_FLAG = (Flags >> 25) & 1; \
- V_FLAG = (Flags >> 26) & 1; \
-}
-# define ADC_RD_RS \
-{ \
- register int Flags; \
- register int Result; \
- asm volatile("mtspr 1, %4\n" \ /* reg 1 is xer */
- "addeo. %0, %2, %3\n" \
- "mcrxr cr1\n" \
- "mfcr %1\n" \
- : "=r" (Result), \
- "=r" (Flags) \
- : "r" (reg[dest].I), \
- "r" (value), \
- "r" (C_FLAG << 29) \
- ); \
- reg[dest].I = Result; \
- Z_FLAG = (Flags >> 29) & 1; \
- N_FLAG = (Flags >> 31) & 1; \
- C_FLAG = (Flags >> 25) & 1; \
- V_FLAG = (Flags >> 26) & 1; \
-}
-# define SUB_RD_RS_RN(N) \
-{ \
- register int Flags; \
- register int Result; \
- asm volatile("subco. %0, %2, %3\n" \
- "mcrxr cr1\n" \
- "mfcr %1\n" \
- : "=r" (Result), \
- "=r" (Flags) \
- : "r" (reg[source].I), \
- "r" (reg[N].I) \
- ); \
- reg[dest].I = Result; \
- Z_FLAG = (Flags >> 29) & 1; \
- N_FLAG = (Flags >> 31) & 1; \
- C_FLAG = (Flags >> 25) & 1; \
- V_FLAG = (Flags >> 26) & 1; \
-}
-# define SUB_RD_RS_O3(N) \
-{ \
- register int Flags; \
- register int Result; \
- asm volatile("subco. %0, %2, %3\n" \
- "mcrxr cr1\n" \
- "mfcr %1\n" \
- : "=r" (Result), \
- "=r" (Flags) \
- : "r" (reg[source].I), \
- "r" (N) \
- ); \
- reg[dest].I = Result; \
- Z_FLAG = (Flags >> 29) & 1; \
- N_FLAG = (Flags >> 31) & 1; \
- C_FLAG = (Flags >> 25) & 1; \
- V_FLAG = (Flags >> 26) & 1; \
-}
-# define SUB_RD_RS_O3_0 SUB_RD_RS_O3
-# define SUB_RN_O8(d) \
-{ \
- register int Flags; \
- register int Result; \
- asm volatile("subco. %0, %2, %3\n" \
- "mcrxr cr1\n" \
- "mfcr %1\n" \
- : "=r" (Result), \
- "=r" (Flags) \
- : "r" (reg[(d)].I), \
- "r" (opcode & 255) \
- ); \
- reg[(d)].I = Result; \
- Z_FLAG = (Flags >> 29) & 1; \
- N_FLAG = (Flags >> 31) & 1; \
- C_FLAG = (Flags >> 25) & 1; \
- V_FLAG = (Flags >> 26) & 1; \
-}
-# define CMP_RN_O8(d) \
-{ \
- register int Flags; \
- register int Result; \
- asm volatile("subco. %0, %2, %3\n" \
- "mcrxr cr1\n" \
- "mfcr %1\n" \
- : "=r" (Result), \
- "=r" (Flags) \
- : "r" (reg[(d)].I), \
- "r" (opcode & 255) \
- ); \
- Z_FLAG = (Flags >> 29) & 1; \
- N_FLAG = (Flags >> 31) & 1; \
- C_FLAG = (Flags >> 25) & 1; \
- V_FLAG = (Flags >> 26) & 1; \
-}
-# define SBC_RD_RS \
-{ \
- register int Flags; \
- register int Result; \
- asm volatile("mtspr 1, %4\n" \ /* reg 1 is xer */
- "subfeo. %0, %3, %2\n" \
- "mcrxr cr1\n" \
- "mfcr %1\n" \
- : "=r" (Result), \
- "=r" (Flags) \
- : "r" (reg[dest].I), \
- "r" (value), \
- "r" (C_FLAG << 29) \
- ); \
- reg[dest].I = Result; \
- Z_FLAG = (Flags >> 29) & 1; \
- N_FLAG = (Flags >> 31) & 1; \
- C_FLAG = (Flags >> 25) & 1; \
- V_FLAG = (Flags >> 26) & 1; \
-}
-# define NEG_RD_RS \
-{ \
- register int Flags; \
- register int Result; \
- asm volatile("subfco. %0, %2, %3\n" \
- "mcrxr cr1\n" \
- "mfcr %1\n" \
- : "=r" (Result), \
- "=r" (Flags) \
- : "r" (reg[source].I), \
- "r" (0) \
- ); \
- reg[dest].I = Result; \
- Z_FLAG = (Flags >> 29) & 1; \
- N_FLAG = (Flags >> 31) & 1; \
- C_FLAG = (Flags >> 25) & 1; \
- V_FLAG = (Flags >> 26) & 1; \
-}
-# define CMP_RD_RS \
-{ \
- register int Flags; \
- register int Result; \
- asm volatile("subco. %0, %2, %3\n" \
- "mcrxr cr1\n" \
- "mfcr %1\n" \
- : "=r" (Result), \
- "=r" (Flags) \
- : "r" (reg[dest].I), \
- "r" (value) \
- ); \
- Z_FLAG = (Flags >> 29) & 1; \
- N_FLAG = (Flags >> 31) & 1; \
- C_FLAG = (Flags >> 25) & 1; \
- V_FLAG = (Flags >> 26) & 1; \
-}
-# else
-# define EMIT1(op, arg) #op " " arg "; "
-# define EMIT2(op, src, dest) #op " " src ", " dest "; "
-# define KONST(val) "$" #val
-# define ASMVAR(cvar) ASMVAR2(__USER_LABEL_PREFIX__, cvar)
-# define ASMVAR2(prefix, cvar) STRING(prefix) cvar
-# define STRING(x) #x
-# define VAR(var) ASMVAR(#var)
-# define REGREF1(index) ASMVAR("reg(" index ")")
-# define REGREF2(index, scale) ASMVAR("reg(," index "," #scale ")")
-# define eax "%%eax"
-# define ecx "%%ecx"
-# define edx "%%edx"
-# define ADD_RN_O8(d) \
- asm("andl $0xFF, %%eax;" \
- "addl %%eax, %0;" \
- EMIT1(setsb, VAR(N_FLAG)) \
- EMIT1(setzb, VAR(Z_FLAG)) \
- EMIT1(setcb, VAR(C_FLAG)) \
- EMIT1(setob, VAR(V_FLAG)) \
- : "=m" (reg[(d)].I));
-# define CMN_RD_RS \
- asm("add %0, %1;" \
- EMIT1(setsb, VAR(N_FLAG)) \
- EMIT1(setzb, VAR(Z_FLAG)) \
- EMIT1(setcb, VAR(C_FLAG)) \
- EMIT1(setob, VAR(V_FLAG)) \
- : \
- : "r" (value), "r" (reg[dest].I) : "1");
-# define ADC_RD_RS \
- asm(EMIT2(bt, KONST(0), VAR(C_FLAG)) \
- "adc %1, %%ebx;" \
- EMIT1(setsb, VAR(N_FLAG)) \
- EMIT1(setzb, VAR(Z_FLAG)) \
- EMIT1(setcb, VAR(C_FLAG)) \
- EMIT1(setob, VAR(V_FLAG)) \
- : "=b" (reg[dest].I) \
- : "r" (value), "b" (reg[dest].I));
-# define SUB_RN_O8(d) \
- asm("andl $0xFF, %%eax;" \
- "subl %%eax, %0;" \
- EMIT1(setsb, VAR(N_FLAG)) \
- EMIT1(setzb, VAR(Z_FLAG)) \
- EMIT1(setncb, VAR(C_FLAG)) \
- EMIT1(setob, VAR(V_FLAG)) \
- : "=m" (reg[(d)].I));
-# define MOV_RN_O8(d) \
- asm("andl $0xFF, %%eax;" \
- EMIT2(movb, KONST(0), VAR(N_FLAG)) \
- "movl %%eax, %0;" \
- EMIT1(setzb, VAR(Z_FLAG)) \
- : "=m" (reg[(d)].I));
-# define CMP_RN_O8(d) \
- asm("andl $0xFF, %%eax;" \
- "cmpl %%eax, %0;" \
- EMIT1(setsb, VAR(N_FLAG)) \
- EMIT1(setzb, VAR(Z_FLAG)) \
- EMIT1(setncb, VAR(C_FLAG)) \
- EMIT1(setob, VAR(V_FLAG)) \
- : \
- : "m" (reg[(d)].I));
-# define SBC_RD_RS \
- asm volatile(EMIT2(bt, KONST(0), VAR(C_FLAG)) \
- "cmc;" \
- "sbb %1, %%ebx;" \
- EMIT1(setsb, VAR(N_FLAG)) \
- EMIT1(setzb, VAR(Z_FLAG)) \
- EMIT1(setncb, VAR(C_FLAG)) \
- EMIT1(setob, VAR(V_FLAG)) \
- : "=b" (reg[dest].I) \
- : "r" (value), "b" (reg[dest].I) : "cc", "memory");
-# define LSL_RD_RS \
- asm("shl %%cl, %%eax;" \
- EMIT1(setcb, VAR(C_FLAG)) \
- : "=a" (value) \
- : "a" (reg[dest].I), "c" (value));
-# define LSR_RD_RS \
- asm("shr %%cl, %%eax;" \
- EMIT1(setcb, VAR(C_FLAG)) \
- : "=a" (value) \
- : "a" (reg[dest].I), "c" (value));
-# define ASR_RD_RS \
- asm("sar %%cl, %%eax;" \
- EMIT1(setcb, VAR(C_FLAG)) \
- : "=a" (value) \
- : "a" (reg[dest].I), "c" (value));
-# define ROR_RD_RS \
- asm("ror %%cl, %%eax;" \
- EMIT1(setcb, VAR(C_FLAG)) \
- : "=a" (value) \
- : "a" (reg[dest].I), "c" (value));
-# define NEG_RD_RS \
- asm("neg %%ebx;" \
- EMIT1(setsb, VAR(N_FLAG)) \
- EMIT1(setzb, VAR(Z_FLAG)) \
- EMIT1(setncb, VAR(C_FLAG)) \
- EMIT1(setob, VAR(V_FLAG)) \
- : "=b" (reg[dest].I) \
- : "b" (reg[source].I));
-# define CMP_RD_RS \
- asm("sub %0, %1;" \
- EMIT1(setsb, VAR(N_FLAG)) \
- EMIT1(setzb, VAR(Z_FLAG)) \
- EMIT1(setncb, VAR(C_FLAG)) \
- EMIT1(setob, VAR(V_FLAG)) \
- : \
- : "r" (value), "r" (reg[dest].I) : "1");
-# define IMM5_INSN(OP, N) \
- asm("movl %%eax,%%ecx;" \
- "shrl $1,%%eax;" \
- "andl $7,%%ecx;" \
- "andl $0x1C,%%eax;" \
- EMIT2(movl, REGREF1(eax), edx) \
- OP \
- EMIT1(setsb, VAR(N_FLAG)) \
- EMIT1(setzb, VAR(Z_FLAG)) \
- EMIT2(movl, edx, REGREF2(ecx, 4)) \
- : : "i" (N))
-# define IMM5_INSN_0(OP) \
- asm("movl %%eax,%%ecx;" \
- "shrl $1,%%eax;" \
- "andl $7,%%ecx;" \
- "andl $0x1C,%%eax;" \
- EMIT2(movl, REGREF1(eax), edx) \
- OP \
- EMIT1(setsb, VAR(N_FLAG)) \
- EMIT1(setzb, VAR(Z_FLAG)) \
- EMIT2(movl, edx, REGREF2(ecx, 4)) \
- : : )
-# define IMM5_LSL \
- "shll %0,%%edx;" \
- EMIT1(setcb, VAR(C_FLAG))
-# define IMM5_LSL_0 \
- "testl %%edx,%%edx;"
-# define IMM5_LSR \
- "shrl %0,%%edx;" \
- EMIT1(setcb, VAR(C_FLAG))
-# define IMM5_LSR_0 \
- "testl %%edx,%%edx;" \
- EMIT1(setsb, VAR(C_FLAG)) \
- "xorl %%edx,%%edx;"
-# define IMM5_ASR \
- "sarl %0,%%edx;" \
- EMIT1(setcb, VAR(C_FLAG))
-# define IMM5_ASR_0 \
- "sarl $31,%%edx;" \
- EMIT1(setsb, VAR(C_FLAG))
-# define THREEARG_INSN(OP, N) \
- asm("movl %%eax,%%edx;" \
- "shrl $1,%%edx;" \
- "andl $0x1C,%%edx;" \
- "andl $7,%%eax;" \
- EMIT2(movl, REGREF1(edx), ecx) \
- OP(N) \
- EMIT1(setsb, VAR(N_FLAG)) \
- EMIT1(setzb, VAR(Z_FLAG)) \
- EMIT2(movl, ecx, REGREF2(eax, 4)) \
- : : )
-# define ADD_RD_RS_RN(N) \
- EMIT2(add, VAR(reg) "+" #N "*4", ecx) \
- EMIT1(setcb, VAR(C_FLAG)) \
- EMIT1(setob, VAR(V_FLAG))
-# define ADD_RD_RS_O3(N) \
- "add $" #N ",%%ecx;" \
- EMIT1(setcb, VAR(C_FLAG)) \
- EMIT1(setob, VAR(V_FLAG))
-# define ADD_RD_RS_O3_0(N) \
- EMIT2(movb, KONST(0), VAR(C_FLAG)) \
- "add $0,%%ecx;" \
- EMIT2(movb, KONST(0), VAR(V_FLAG))
-# define SUB_RD_RS_RN(N) \
- EMIT2(sub, VAR(reg) "+" #N "*4", ecx) \
- EMIT1(setncb, VAR(C_FLAG)) \
- EMIT1(setob, VAR(V_FLAG))
-# define SUB_RD_RS_O3(N) \
- "sub $" #N ",%%ecx;" \
- EMIT1(setncb, VAR(C_FLAG)) \
- EMIT1(setob, VAR(V_FLAG))
-# define SUB_RD_RS_O3_0(N) \
- EMIT2(movb, KONST(1), VAR(C_FLAG)) \
- "sub $0,%%ecx;" \
- EMIT2(movb, KONST(0), VAR(V_FLAG))
-# endif
-# else // !__GNUC__
-# define ADD_RD_RS_RN(N) \
-{ \
- __asm mov eax, source \
- __asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
- __asm add ebx, dword ptr [OFFSET reg + 4 * N] \
- __asm mov eax, dest \
- __asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
- __asm sets byte ptr N_FLAG \
- __asm setz byte ptr Z_FLAG \
- __asm setc byte ptr C_FLAG \
- __asm seto byte ptr V_FLAG \
-}
-# define ADD_RD_RS_O3(N) \
-{ \
- __asm mov eax, source \
- __asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
- __asm add ebx, N \
- __asm mov eax, dest \
- __asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
- __asm sets byte ptr N_FLAG \
- __asm setz byte ptr Z_FLAG \
- __asm setc byte ptr C_FLAG \
- __asm seto byte ptr V_FLAG \
-}
-# define ADD_RD_RS_O3_0 \
-{ \
- __asm mov eax, source \
- __asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
- __asm add ebx, 0 \
- __asm mov eax, dest \
- __asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
- __asm sets byte ptr N_FLAG \
- __asm setz byte ptr Z_FLAG \
- __asm mov byte ptr C_FLAG, 0 \
- __asm mov byte ptr V_FLAG, 0 \
-}
-# define ADD_RN_O8(d) \
-{ \
- __asm mov ebx, opcode \
- __asm and ebx, 255 \
- __asm add dword ptr [OFFSET reg + 4 * (d)], ebx \
- __asm sets byte ptr N_FLAG \
- __asm setz byte ptr Z_FLAG \
- __asm setc byte ptr C_FLAG \
- __asm seto byte ptr V_FLAG \
-}
-# define CMN_RD_RS \
-{ \
- __asm mov eax, dest \
- __asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
- __asm add ebx, value \
- __asm sets byte ptr N_FLAG \
- __asm setz byte ptr Z_FLAG \
- __asm setc byte ptr C_FLAG \
- __asm seto byte ptr V_FLAG \
-}
-# define ADC_RD_RS \
-{ \
- __asm mov ebx, dest \
- __asm mov ebx, dword ptr [OFFSET reg + 4 * ebx] \
- __asm bt word ptr C_FLAG, 0 \
- __asm adc ebx, value \
- __asm mov eax, dest \
- __asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
- __asm sets byte ptr N_FLAG \
- __asm setz byte ptr Z_FLAG \
- __asm setc byte ptr C_FLAG \
- __asm seto byte ptr V_FLAG \
-}
-# define SUB_RD_RS_RN(N) \
-{ \
- __asm mov eax, source \
- __asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
- __asm sub ebx, dword ptr [OFFSET reg + 4 * N] \
- __asm mov eax, dest \
- __asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
- __asm sets byte ptr N_FLAG \
- __asm setz byte ptr Z_FLAG \
- __asm setnc byte ptr C_FLAG \
- __asm seto byte ptr V_FLAG \
-}
-# define SUB_RD_RS_O3(N) \
-{ \
- __asm mov eax, source \
- __asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
- __asm sub ebx, N \
- __asm mov eax, dest \
- __asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
- __asm sets byte ptr N_FLAG \
- __asm setz byte ptr Z_FLAG \
- __asm setnc byte ptr C_FLAG \
- __asm seto byte ptr V_FLAG \
-}
-# define SUB_RD_RS_O3_0 \
-{ \
- __asm mov eax, source \
- __asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
- __asm sub ebx, 0 \
- __asm mov eax, dest \
- __asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
- __asm sets byte ptr N_FLAG \
- __asm setz byte ptr Z_FLAG \
- __asm mov byte ptr C_FLAG, 1 \
- __asm mov byte ptr V_FLAG, 0 \
-}
-# define SUB_RN_O8(d) \
-{ \
- __asm mov ebx, opcode \
- __asm and ebx, 255 \
- __asm sub dword ptr [OFFSET reg + 4 * (d)], ebx \
- __asm sets byte ptr N_FLAG \
- __asm setz byte ptr Z_FLAG \
- __asm setnc byte ptr C_FLAG \
- __asm seto byte ptr V_FLAG \
-}
-# define MOV_RN_O8(d) \
-{ \
- __asm mov eax, opcode \
- __asm and eax, 255 \
- __asm mov dword ptr [OFFSET reg + 4 * (d)], eax \
- __asm sets byte ptr N_FLAG \
- __asm setz byte ptr Z_FLAG \
-}
-# define CMP_RN_O8(d) \
-{ \
- __asm mov eax, dword ptr [OFFSET reg + 4 * (d)] \
- __asm mov ebx, opcode \
- __asm and ebx, 255 \
- __asm sub eax, ebx \
- __asm sets byte ptr N_FLAG \
- __asm setz byte ptr Z_FLAG \
- __asm setnc byte ptr C_FLAG \
- __asm seto byte ptr V_FLAG \
-}
-# define SBC_RD_RS \
-{ \
- __asm mov ebx, dest \
- __asm mov ebx, dword ptr [OFFSET reg + 4 * ebx] \
- __asm mov eax, value \
- __asm bt word ptr C_FLAG, 0 \
- __asm cmc \
- __asm sbb ebx, eax \
- __asm mov eax, dest \
- __asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
- __asm sets byte ptr N_FLAG \
- __asm setz byte ptr Z_FLAG \
- __asm setnc byte ptr C_FLAG \
- __asm seto byte ptr V_FLAG \
-}
-# define LSL_RD_RM_I5 \
-{ \
- __asm mov eax, source \
- __asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
- __asm mov cl, byte ptr shift \
- __asm shl eax, cl \
- __asm mov value, eax \
- __asm setc byte ptr C_FLAG \
-}
-# define LSL_RD_RS \
-{ \
- __asm mov eax, dest \
- __asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
- __asm mov cl, byte ptr value \
- __asm shl eax, cl \
- __asm mov value, eax \
- __asm setc byte ptr C_FLAG \
-}
-# define LSR_RD_RM_I5 \
-{ \
- __asm mov eax, source \
- __asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
- __asm mov cl, byte ptr shift \
- __asm shr eax, cl \
- __asm mov value, eax \
- __asm setc byte ptr C_FLAG \
-}
-# define LSR_RD_RS \
-{ \
- __asm mov eax, dest \
- __asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
- __asm mov cl, byte ptr value \
- __asm shr eax, cl \
- __asm mov value, eax \
- __asm setc byte ptr C_FLAG \
-}
-# define ASR_RD_RM_I5 \
-{ \
- __asm mov eax, source \
- __asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
- __asm mov cl, byte ptr shift \
- __asm sar eax, cl \
- __asm mov value, eax \
- __asm setc byte ptr C_FLAG \
-}
-# define ASR_RD_RS \
-{ \
- __asm mov eax, dest \
- __asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
- __asm mov cl, byte ptr value \
- __asm sar eax, cl \
- __asm mov value, eax \
- __asm setc byte ptr C_FLAG \
-}
-# define ROR_RD_RS \
-{ \
- __asm mov eax, dest \
- __asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
- __asm mov cl, byte ptr value \
- __asm ror eax, cl \
- __asm mov value, eax \
- __asm setc byte ptr C_FLAG \
-}
-# define NEG_RD_RS \
-{ \
- __asm mov ebx, source \
- __asm mov ebx, dword ptr [OFFSET reg + 4 * ebx] \
- __asm neg ebx \
- __asm mov eax, dest \
- __asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
- __asm sets byte ptr N_FLAG \
- __asm setz byte ptr Z_FLAG \
- __asm setnc byte ptr C_FLAG \
- __asm seto byte ptr V_FLAG \
-}
-# define CMP_RD_RS \
-{ \
- __asm mov eax, dest \
- __asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
- __asm sub ebx, value \
- __asm sets byte ptr N_FLAG \
- __asm setz byte ptr Z_FLAG \
- __asm setnc byte ptr C_FLAG \
- __asm seto byte ptr V_FLAG \
-}
-# endif
-#endif
-
// C core
-static inline void ADDCARRY(uint32_t a, uint32_t b, uint32_t c)
+auto ADDCARRY = [](uint32_t a, uint32_t b, uint32_t c)
{
C_FLAG = !!((NEG(a) & NEG(b)) | (NEG(a) & POS(c)) | (NEG(b) & POS(c)));
-}
-static inline void ADDOVERFLOW(uint32_t a, uint32_t b, uint32_t c)
+};
+auto ADDOVERFLOW = [](uint32_t a, uint32_t b, uint32_t c)
{
V_FLAG = !!((NEG(a) & NEG(b) & POS(c)) | (POS(a) & POS(b) & NEG(c)));
-}
-static inline void SUBCARRY(uint32_t a, uint32_t b, uint32_t c)
+};
+auto SUBCARRY = [](uint32_t a, uint32_t b, uint32_t c)
{
C_FLAG = !!((NEG(a) & POS(b)) | (NEG(a) & POS(c)) | (POS(b) & POS(c)));
-}
-static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c)
+};
+auto SUBOVERFLOW = [](uint32_t a, uint32_t b, uint32_t c)
{
V_FLAG = !!((NEG(a) & POS(b) & POS(c)) | (POS(a) & NEG(b) & NEG(c)));
-}
-#ifndef ADD_RD_RS_RN
-# define ADD_RD_RS_RN(N) \
+};
+#define ADD_RD_RS_RN(N) \
{ \
uint32_t lhs = reg[source].I; \
- uint32_t rhs = reg[N].I; \
+ uint32_t rhs = reg[(N)].I; \
uint32_t res = lhs + rhs; \
reg[dest].I = res; \
Z_FLAG = !res; \
@@ -691,12 +47,10 @@
ADDCARRY(lhs, rhs, res); \
ADDOVERFLOW(lhs, rhs, res); \
}
-#endif
-#ifndef ADD_RD_RS_O3
-# define ADD_RD_RS_O3(N) \
+#define ADD_RD_RS_O3(N) \
{ \
uint32_t lhs = reg[source].I; \
- uint32_t rhs = N; \
+ uint32_t rhs = (N); \
uint32_t res = lhs + rhs; \
reg[dest].I = res; \
Z_FLAG = !res; \
@@ -704,12 +58,8 @@
ADDCARRY(lhs, rhs, res); \
ADDOVERFLOW(lhs, rhs, res); \
}
-#endif
-#ifndef ADD_RD_RS_O3_0
-# define ADD_RD_RS_O3_0 ADD_RD_RS_O3
-#endif
-#ifndef ADD_RN_O8
-# define ADD_RN_O8(d) \
+#define ADD_RD_RS_O3_0 ADD_RD_RS_O3
+#define ADD_RN_O8(d) \
{ \
uint32_t lhs = reg[(d)].I; \
uint32_t rhs = opcode & 255; \
@@ -720,9 +70,7 @@
ADDCARRY(lhs, rhs, res); \
ADDOVERFLOW(lhs, rhs, res); \
}
-#endif
-#ifndef CMN_RD_RS
-# define CMN_RD_RS \
+#define CMN_RD_RS \
{ \
uint32_t lhs = reg[dest].I; \
uint32_t rhs = value; \
@@ -732,9 +80,7 @@
ADDCARRY(lhs, rhs, res); \
ADDOVERFLOW(lhs, rhs, res); \
}
-#endif
-#ifndef ADC_RD_RS
-# define ADC_RD_RS \
+#define ADC_RD_RS \
{ \
uint32_t lhs = reg[dest].I; \
uint32_t rhs = value; \
@@ -745,12 +91,10 @@
ADDCARRY(lhs, rhs, res); \
ADDOVERFLOW(lhs, rhs, res); \
}
-#endif
-#ifndef SUB_RD_RS_RN
-# define SUB_RD_RS_RN(N) \
+#define SUB_RD_RS_RN(N) \
{ \
uint32_t lhs = reg[source].I; \
- uint32_t rhs = reg[N].I; \
+ uint32_t rhs = reg[(N)].I; \
uint32_t res = lhs - rhs; \
reg[dest].I = res; \
Z_FLAG = !res; \
@@ -758,25 +102,19 @@
SUBCARRY(lhs, rhs, res); \
SUBOVERFLOW(lhs, rhs, res); \
}
-#endif
-#ifndef SUB_RD_RS_O3
-# define SUB_RD_RS_O3(N) \
+#define SUB_RD_RS_O3(N) \
{ \
uint32_t lhs = reg[source].I; \
- uint32_t rhs = N; \
+ uint32_t rhs = (N); \
uint32_t res = lhs - rhs; \
- reg[dest].I = res; \
+ reg[dest].I = res;\
Z_FLAG = !res; \
N_FLAG = !!NEG(res); \
SUBCARRY(lhs, rhs, res); \
SUBOVERFLOW(lhs, rhs, res); \
}
-#endif
-#ifndef SUB_RD_RS_O3_0
-# define SUB_RD_RS_O3_0 SUB_RD_RS_O3
-#endif
-#ifndef SUB_RN_O8
-# define SUB_RN_O8(d) \
+#define SUB_RD_RS_O3_0 SUB_RD_RS_O3
+#define SUB_RN_O8(d) \
{ \
uint32_t lhs = reg[(d)].I; \
uint32_t rhs = opcode & 255; \
@@ -787,17 +125,13 @@
SUBCARRY(lhs, rhs, res); \
SUBOVERFLOW(lhs, rhs, res); \
}
-#endif
-#ifndef MOV_RN_O8
-# define MOV_RN_O8(d) \
-{ \
- reg[d].I = opcode & 255; \
+#define MOV_RN_O8(d) \
+{ \
+ reg[(d)].I = opcode & 255; \
N_FLAG = false; \
Z_FLAG = !reg[d].I; \
}
-#endif
-#ifndef CMP_RN_O8
-# define CMP_RN_O8(d) \
+#define CMP_RN_O8(d) \
{ \
uint32_t lhs = reg[(d)].I; \
uint32_t rhs = opcode & 255; \
@@ -807,9 +141,7 @@
SUBCARRY(lhs, rhs, res); \
SUBOVERFLOW(lhs, rhs, res); \
}
-#endif
-#ifndef SBC_RD_RS
-# define SBC_RD_RS \
+#define SBC_RD_RS \
{ \
uint32_t lhs = reg[dest].I; \
uint32_t rhs = value; \
@@ -820,58 +152,42 @@
SUBCARRY(lhs, rhs, res); \
SUBOVERFLOW(lhs, rhs, res); \
}
-#endif
-#ifndef LSL_RD_RM_I5
-# define LSL_RD_RM_I5 \
+#define LSL_RD_RM_I5 \
{ \
C_FLAG = !!((reg[source].I >> (32 - shift)) & 1); \
value = reg[source].I << shift; \
}
-#endif
-#ifndef LSL_RD_RS
-# define LSL_RD_RS \
+#define LSL_RD_RS \
{ \
C_FLAG = !!((reg[dest].I >> (32 - value)) & 1); \
value = reg[dest].I << value; \
}
-#endif
-#ifndef LSR_RD_RM_I5
-# define LSR_RD_RM_I5 \
+#define LSR_RD_RM_I5 \
{ \
C_FLAG = !!((reg[source].I >> (shift - 1)) & 1); \
value = reg[source].I >> shift; \
}
-#endif
-#ifndef LSR_RD_RS
-# define LSR_RD_RS \
+#define LSR_RD_RS \
{ \
C_FLAG = !!((reg[dest].I >> (value - 1)) & 1); \
value = reg[dest].I >> value; \
}
-#endif
-#ifndef ASR_RD_RM_I5
-# define ASR_RD_RM_I5 \
+#define ASR_RD_RM_I5 \
{ \
C_FLAG = !!((static_cast<int32_t>(reg[source].I) >> static_cast<int>(shift - 1)) & 1); \
value = static_cast<int32_t>(reg[source].I) >> static_cast<int>(shift); \
}
-#endif
-#ifndef ASR_RD_RS
-# define ASR_RD_RS \
+#define ASR_RD_RS \
{ \
C_FLAG = !!((static_cast<int32_t>(reg[dest].I) >> static_cast<int>(value - 1)) & 1); \
value = static_cast<int32_t>(reg[dest].I) >> static_cast<int>(value); \
}
-#endif
-#ifndef ROR_RD_RS
-# define ROR_RD_RS \
+#define ROR_RD_RS \
{ \
C_FLAG = !!((reg[dest].I >> (value - 1)) & 1); \
value = (reg[dest].I << (32 - value)) | (reg[dest].I >> value); \
-}
-#endif
-#ifndef NEG_RD_RS
-# define NEG_RD_RS \
+ }
+#define NEG_RD_RS \
{ \
uint32_t lhs = reg[source].I; \
uint32_t rhs = 0; \
@@ -882,9 +198,7 @@
SUBCARRY(rhs, lhs, res); \
SUBOVERFLOW(rhs, lhs, res); \
}
-#endif
-#ifndef CMP_RD_RS
-# define CMP_RD_RS \
+#define CMP_RD_RS \
{ \
uint32_t lhs = reg[dest].I; \
uint32_t rhs = value; \
@@ -894,17 +208,15 @@
SUBCARRY(lhs, rhs, res); \
SUBOVERFLOW(lhs, rhs, res); \
}
-#endif
-#ifndef IMM5_INSN
-# define IMM5_INSN(OP, N) \
+#define IMM5_INSN(OP, N) \
int dest = opcode & 0x07; \
int source = (opcode >> 3) & 0x07; \
uint32_t value; \
- OP(N); \
+ OP((N)); \
reg[dest].I = value; \
N_FLAG = !!(value & 0x80000000); \
Z_FLAG = !value;
-# define IMM5_INSN_0(OP) \
+#define IMM5_INSN_0(OP) \
int dest = opcode & 0x07; \
int source = (opcode >> 3) & 0x07; \
uint32_t value; \
@@ -912,21 +224,21 @@
reg[dest].I = value; \
N_FLAG = !!(value & 0x80000000); \
Z_FLAG = !value;
-# define IMM5_LSL(N) \
- int shift = N; \
+#define IMM5_LSL(N) \
+ int shift = (N); \
LSL_RD_RM_I5;
-# define IMM5_LSL_0 \
+#define IMM5_LSL_0 \
value = reg[source].I;
-# define IMM5_LSR(N) \
- int shift = N; \
+#define IMM5_LSR(N) \
+ int shift = (N); \
LSR_RD_RM_I5;
-# define IMM5_LSR_0 \
+#define IMM5_LSR_0 \
C_FLAG = !!(reg[source].I & 0x80000000); \
value = 0;
-# define IMM5_ASR(N) \
- int shift = N; \
+#define IMM5_ASR(N) \
+ int shift = (N); \
ASR_RD_RM_I5;
-# define IMM5_ASR_0 \
+#define IMM5_ASR_0 \
if (reg[source].I & 0x80000000) \
{ \
value = 0xFFFFFFFF; \
@@ -937,13 +249,10 @@
value = 0; \
C_FLAG = false; \
}
-#endif
-#ifndef THREEARG_INSN
-# define THREEARG_INSN(OP, N) \
+#define THREEARG_INSN(OP, N) \
int dest = opcode & 0x07; \
int source = (opcode >> 3) & 0x07; \
- OP(N);
-#endif
+ OP((N));
// Shift instructions /////////////////////////////////////////////////////
@@ -958,28 +267,28 @@
static INSN_REGPARM void thumb##BASE##_07(uint32_t opcode) { IMM5_INSN(OP, 7); } \
static INSN_REGPARM void thumb##BASE##_08(uint32_t opcode) { IMM5_INSN(OP, 8); } \
static INSN_REGPARM void thumb##BASE##_09(uint32_t opcode) { IMM5_INSN(OP, 9); } \
- static INSN_REGPARM void thumb##BASE##_0A(uint32_t opcode) { IMM5_INSN(OP, 10); } \
- static INSN_REGPARM void thumb##BASE##_0B(uint32_t opcode) { IMM5_INSN(OP, 11); } \
- static INSN_REGPARM void thumb##BASE##_0C(uint32_t opcode) { IMM5_INSN(OP, 12); } \
- static INSN_REGPARM void thumb##BASE##_0D(uint32_t opcode) { IMM5_INSN(OP, 13); } \
- static INSN_REGPARM void thumb##BASE##_0E(uint32_t opcode) { IMM5_INSN(OP, 14); } \
- static INSN_REGPARM void thumb##BASE##_0F(uint32_t opcode) { IMM5_INSN(OP, 15); } \
- static INSN_REGPARM void thumb##BASE##_10(uint32_t opcode) { IMM5_INSN(OP, 16); } \
- static INSN_REGPARM void thumb##BASE##_11(uint32_t opcode) { IMM5_INSN(OP, 17); } \
- static INSN_REGPARM void thumb##BASE##_12(uint32_t opcode) { IMM5_INSN(OP, 18); } \
- static INSN_REGPARM void thumb##BASE##_13(uint32_t opcode) { IMM5_INSN(OP, 19); } \
- static INSN_REGPARM void thumb##BASE##_14(uint32_t opcode) { IMM5_INSN(OP, 20); } \
- static INSN_REGPARM void thumb##BASE##_15(uint32_t opcode) { IMM5_INSN(OP, 21); } \
- static INSN_REGPARM void thumb##BASE##_16(uint32_t opcode) { IMM5_INSN(OP, 22); } \
- static INSN_REGPARM void thumb##BASE##_17(uint32_t opcode) { IMM5_INSN(OP, 23); } \
- static INSN_REGPARM void thumb##BASE##_18(uint32_t opcode) { IMM5_INSN(OP, 24); } \
- static INSN_REGPARM void thumb##BASE##_19(uint32_t opcode) { IMM5_INSN(OP, 25); } \
- static INSN_REGPARM void thumb##BASE##_1A(uint32_t opcode) { IMM5_INSN(OP, 26); } \
- static INSN_REGPARM void thumb##BASE##_1B(uint32_t opcode) { IMM5_INSN(OP, 27); } \
- static INSN_REGPARM void thumb##BASE##_1C(uint32_t opcode) { IMM5_INSN(OP, 28); } \
- static INSN_REGPARM void thumb##BASE##_1D(uint32_t opcode) { IMM5_INSN(OP, 29); } \
- static INSN_REGPARM void thumb##BASE##_1E(uint32_t opcode) { IMM5_INSN(OP, 30); } \
- static INSN_REGPARM void thumb##BASE##_1F(uint32_t opcode) { IMM5_INSN(OP, 31); }
+ static INSN_REGPARM void thumb##BASE##_0A(uint32_t opcode) { IMM5_INSN(OP,10); } \
+ static INSN_REGPARM void thumb##BASE##_0B(uint32_t opcode) { IMM5_INSN(OP,11); } \
+ static INSN_REGPARM void thumb##BASE##_0C(uint32_t opcode) { IMM5_INSN(OP,12); } \
+ static INSN_REGPARM void thumb##BASE##_0D(uint32_t opcode) { IMM5_INSN(OP,13); } \
+ static INSN_REGPARM void thumb##BASE##_0E(uint32_t opcode) { IMM5_INSN(OP,14); } \
+ static INSN_REGPARM void thumb##BASE##_0F(uint32_t opcode) { IMM5_INSN(OP,15); } \
+ static INSN_REGPARM void thumb##BASE##_10(uint32_t opcode) { IMM5_INSN(OP,16); } \
+ static INSN_REGPARM void thumb##BASE##_11(uint32_t opcode) { IMM5_INSN(OP,17); } \
+ static INSN_REGPARM void thumb##BASE##_12(uint32_t opcode) { IMM5_INSN(OP,18); } \
+ static INSN_REGPARM void thumb##BASE##_13(uint32_t opcode) { IMM5_INSN(OP,19); } \
+ static INSN_REGPARM void thumb##BASE##_14(uint32_t opcode) { IMM5_INSN(OP,20); } \
+ static INSN_REGPARM void thumb##BASE##_15(uint32_t opcode) { IMM5_INSN(OP,21); } \
+ static INSN_REGPARM void thumb##BASE##_16(uint32_t opcode) { IMM5_INSN(OP,22); } \
+ static INSN_REGPARM void thumb##BASE##_17(uint32_t opcode) { IMM5_INSN(OP,23); } \
+ static INSN_REGPARM void thumb##BASE##_18(uint32_t opcode) { IMM5_INSN(OP,24); } \
+ static INSN_REGPARM void thumb##BASE##_19(uint32_t opcode) { IMM5_INSN(OP,25); } \
+ static INSN_REGPARM void thumb##BASE##_1A(uint32_t opcode) { IMM5_INSN(OP,26); } \
+ static INSN_REGPARM void thumb##BASE##_1B(uint32_t opcode) { IMM5_INSN(OP,27); } \
+ static INSN_REGPARM void thumb##BASE##_1C(uint32_t opcode) { IMM5_INSN(OP,28); } \
+ static INSN_REGPARM void thumb##BASE##_1D(uint32_t opcode) { IMM5_INSN(OP,29); } \
+ static INSN_REGPARM void thumb##BASE##_1E(uint32_t opcode) { IMM5_INSN(OP,30); } \
+ static INSN_REGPARM void thumb##BASE##_1F(uint32_t opcode) { IMM5_INSN(OP,31); }
// LSL Rd, Rm, #Imm 5
DEFINE_IMM5_INSN(IMM5_LSL, 00)
@@ -991,24 +300,24 @@
// 3-argument ADD/SUB /////////////////////////////////////////////////////
#define DEFINE_REG3_INSN(OP, BASE) \
- static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP, 0); } \
- static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP, 1); } \
- static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP, 2); } \
- static INSN_REGPARM void thumb##BASE##_3(uint32_t opcode) { THREEARG_INSN(OP, 3); } \
- static INSN_REGPARM void thumb##BASE##_4(uint32_t opcode) { THREEARG_INSN(OP, 4); } \
- static INSN_REGPARM void thumb##BASE##_5(uint32_t opcode) { THREEARG_INSN(OP, 5); } \
- static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP, 6); } \
- static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP, 7); }
+ static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP,0); } \
+ static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP,1); } \
+ static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP,2); } \
+ static INSN_REGPARM void thumb##BASE##_3(uint32_t opcode) { THREEARG_INSN(OP,3); } \
+ static INSN_REGPARM void thumb##BASE##_4(uint32_t opcode) { THREEARG_INSN(OP,4); } \
+ static INSN_REGPARM void thumb##BASE##_5(uint32_t opcode) { THREEARG_INSN(OP,5); } \
+ static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP,6); } \
+ static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP,7); }
#define DEFINE_IMM3_INSN(OP, BASE) \
- static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP##_0, 0); } \
- static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP, 1); } \
- static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP, 2); } \
- static INSN_REGPARM void thumb##BASE##_3(uint32_t opcode) { THREEARG_INSN(OP, 3); } \
- static INSN_REGPARM void thumb##BASE##_4(uint32_t opcode) { THREEARG_INSN(OP, 4); } \
- static INSN_REGPARM void thumb##BASE##_5(uint32_t opcode) { THREEARG_INSN(OP, 5); } \
- static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP, 6); } \
- static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP, 7); }
+ static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP##_0,0); } \
+ static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP,1); } \
+ static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP,2); } \
+ static INSN_REGPARM void thumb##BASE##_3(uint32_t opcode) { THREEARG_INSN(OP,3); } \
+ static INSN_REGPARM void thumb##BASE##_4(uint32_t opcode) { THREEARG_INSN(OP,4); } \
+ static INSN_REGPARM void thumb##BASE##_5(uint32_t opcode) { THREEARG_INSN(OP,5); } \
+ static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP,6); } \
+ static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP,7); }
// ADD Rd, Rs, Rn
DEFINE_REG3_INSN(ADD_RD_RS_RN, 18)
@@ -1122,9 +431,7 @@
C_FLAG = !!(reg[dest].I & 1);
}
else if (value < 32)
- {
- LSL_RD_RS;
- }
+ LSL_RD_RS
else
{
value = 0;
@@ -1150,9 +457,7 @@
C_FLAG = !!(reg[dest].I & 0x80000000);
}
else if (value < 32)
- {
- LSR_RD_RS;
- }
+ LSR_RD_RS
else
{
value = 0;
@@ -1220,7 +525,7 @@
if (value)
{
- value = value & 0x1f;
+ value &= 0x1f;
if (!value)
C_FLAG = !!(reg[dest].I & 0x80000000);
else
@@ -1229,9 +534,9 @@
reg[dest].I = value;
}
}
+ clockTicks = codeTicksAccess16(armNextPC) + 2;
N_FLAG = !!(reg[dest].I & 0x80000000);
Z_FLAG = !reg[dest].I;
- clockTicks = codeTicksAccess16(armNextPC) + 2;
}
// TST Rd, Rs
@@ -1271,8 +576,8 @@
{
int dest = opcode & 7;
reg[dest].I |= reg[(opcode >> 3) & 7].I;
+ Z_FLAG = !reg[dest].I;
N_FLAG = !!(reg[dest].I & 0x80000000);
- Z_FLAG = !reg[dest].I;
}
// MUL Rd, Rs
@@ -1293,9 +598,9 @@
else
clockTicks += 3;
busPrefetchCount = (busPrefetchCount << clockTicks) | (0xFF >> (8 - clockTicks));
+ clockTicks += codeTicksAccess16(armNextPC) + 1;
+ Z_FLAG = !reg[dest].I;
N_FLAG = !!(reg[dest].I & 0x80000000);
- Z_FLAG = !reg[dest].I;
- clockTicks += codeTicksAccess16(armNextPC) + 1;
}
// BIC Rd, Rs
@@ -1303,8 +608,8 @@
{
int dest = opcode & 7;
reg[dest].I &= ~reg[(opcode >> 3) & 7].I;
+ Z_FLAG = !reg[dest].I;
N_FLAG = !!(reg[dest].I & 0x80000000);
- Z_FLAG = !reg[dest].I;
}
// MVN Rd, Rs
@@ -1312,8 +617,8 @@
{
int dest = opcode & 7;
reg[dest].I = ~reg[(opcode >> 3) & 7].I;
+ Z_FLAG = !reg[dest].I;
N_FLAG = !!(reg[dest].I & 0x80000000);
- Z_FLAG = !reg[dest].I;
}
// High-register instructions and BX //////////////////////////////////////
@@ -1321,7 +626,7 @@
// ADD Rd, Hs
static INSN_REGPARM void thumb44_1(uint32_t opcode)
{
- reg[opcode & 7].I += reg[((opcode >> 3) & 7) + 8].I;
+ reg[opcode&7].I += reg[((opcode >> 3) & 7) + 8].I;
}
// ADD Hd, Rs
@@ -1379,7 +684,7 @@
// MOV Rd, Rs
static INSN_REGPARM void thumb46_0(uint32_t opcode)
{
- reg[opcode & 7].I = reg[(opcode >> 3) & 7].I;
+ reg[opcode & 7].I = reg[((opcode >> 3) & 7)].I;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
}
@@ -1650,29 +955,33 @@
// Push and pop ///////////////////////////////////////////////////////////
-#define PUSH_REG(val, r) \
- if (opcode & (val)) \
- { \
- CPUWriteMemory(address, reg[(r)].I); \
- if (!count) \
- clockTicks += 1 + dataTicksAccess32(address); \
- else \
- clockTicks += 1 + dataTicksAccessSeq32(address); \
- ++count; \
- address += 4; \
- }
-
-#define POP_REG(val, r) \
- if (opcode & (val)) \
- { \
- reg[(r)].I = CPUReadMemory(address); \
- if (!count) \
- clockTicks += 1 + dataTicksAccess32(address); \
- else \
- clockTicks += 1 + dataTicksAccessSeq32(address); \
- ++count; \
- address += 4; \
- }
+auto PUSH_REG = [](uint32_t opcode, uint32_t &address, int &count, uint32_t val, uint32_t r)
+{
+ if (opcode & val)
+ {
+ CPUWriteMemory(address, reg[r].I);
+ if (!count)
+ clockTicks += 1 + dataTicksAccess32(address);
+ else
+ clockTicks += 1 + dataTicksAccessSeq32(address);
+ ++count;
+ address += 4;
+ }
+};
+
+auto POP_REG = [](uint32_t opcode, uint32_t &address, int &count, uint32_t val, uint32_t r)
+{
+ if (opcode & val)
+ {
+ reg[r].I = CPUReadMemory(address);
+ if (!count)
+ clockTicks += 1 + dataTicksAccess32(address);
+ else
+ clockTicks += 1 + dataTicksAccessSeq32(address);
+ ++count;
+ address += 4;
+ }
+};
// PUSH {Rlist}
static INSN_REGPARM void thumbB4(uint32_t opcode)
@@ -1682,14 +991,14 @@
int count = 0;
uint32_t temp = reg[13].I - 4 * cpuBitsSet[opcode & 0xff];
uint32_t address = temp & 0xFFFFFFFC;
- PUSH_REG(1, 0);
- PUSH_REG(2, 1);
- PUSH_REG(4, 2);
- PUSH_REG(8, 3);
- PUSH_REG(16, 4);
- PUSH_REG(32, 5);
- PUSH_REG(64, 6);
- PUSH_REG(128, 7);
+ PUSH_REG(opcode, address, count, 1, 0);
+ PUSH_REG(opcode, address, count, 2, 1);
+ PUSH_REG(opcode, address, count, 4, 2);
+ PUSH_REG(opcode, address, count, 8, 3);
+ PUSH_REG(opcode, address, count, 16, 4);
+ PUSH_REG(opcode, address, count, 32, 5);
+ PUSH_REG(opcode, address, count, 64, 6);
+ PUSH_REG(opcode, address, count, 128, 7);
clockTicks += 1 + codeTicksAccess16(armNextPC);
reg[13].I = temp;
}
@@ -1702,15 +1011,15 @@
int count = 0;
uint32_t temp = reg[13].I - 4 - 4 * cpuBitsSet[opcode & 0xff];
uint32_t address = temp & 0xFFFFFFFC;
- PUSH_REG(1, 0);
- PUSH_REG(2, 1);
- PUSH_REG(4, 2);
- PUSH_REG(8, 3);
- PUSH_REG(16, 4);
- PUSH_REG(32, 5);
- PUSH_REG(64, 6);
- PUSH_REG(128, 7);
- PUSH_REG(256, 14);
+ PUSH_REG(opcode, address, count, 1, 0);
+ PUSH_REG(opcode, address, count, 2, 1);
+ PUSH_REG(opcode, address, count, 4, 2);
+ PUSH_REG(opcode, address, count, 8, 3);
+ PUSH_REG(opcode, address, count, 16, 4);
+ PUSH_REG(opcode, address, count, 32, 5);
+ PUSH_REG(opcode, address, count, 64, 6);
+ PUSH_REG(opcode, address, count, 128, 7);
+ PUSH_REG(opcode, address, count, 256, 14);
clockTicks += 1 + codeTicksAccess16(armNextPC);
reg[13].I = temp;
}
@@ -1723,14 +1032,14 @@
int count = 0;
uint32_t address = reg[13].I & 0xFFFFFFFC;
uint32_t temp = reg[13].I + 4 * cpuBitsSet[opcode & 0xFF];
- POP_REG(1, 0);
- POP_REG(2, 1);
- POP_REG(4, 2);
- POP_REG(8, 3);
- POP_REG(16, 4);
- POP_REG(32, 5);
- POP_REG(64, 6);
- POP_REG(128, 7);
+ POP_REG(opcode, address, count, 1, 0);
+ POP_REG(opcode, address, count, 2, 1);
+ POP_REG(opcode, address, count, 4, 2);
+ POP_REG(opcode, address, count, 8, 3);
+ POP_REG(opcode, address, count, 16, 4);
+ POP_REG(opcode, address, count, 32, 5);
+ POP_REG(opcode, address, count, 64, 6);
+ POP_REG(opcode, address, count, 128, 7);
reg[13].I = temp;
clockTicks = 2 + codeTicksAccess16(armNextPC);
}
@@ -1743,14 +1052,14 @@
int count = 0;
uint32_t address = reg[13].I & 0xFFFFFFFC;
uint32_t temp = reg[13].I + 4 + 4 * cpuBitsSet[opcode & 0xFF];
- POP_REG(1, 0);
- POP_REG(2, 1);
- POP_REG(4, 2);
- POP_REG(8, 3);
- POP_REG(16, 4);
- POP_REG(32, 5);
- POP_REG(64, 6);
- POP_REG(128, 7);
+ POP_REG(opcode, address, count, 1, 0);
+ POP_REG(opcode, address, count, 2, 1);
+ POP_REG(opcode, address, count, 4, 2);
+ POP_REG(opcode, address, count, 8, 3);
+ POP_REG(opcode, address, count, 16, 4);
+ POP_REG(opcode, address, count, 32, 5);
+ POP_REG(opcode, address, count, 64, 6);
+ POP_REG(opcode, address, count, 128, 7);
reg[15].I = CPUReadMemory(address) & 0xFFFFFFFE;
if (!count)
clockTicks += 1 + dataTicksAccess32(address);
@@ -1777,7 +1086,7 @@
uint32_t temp = reg[regist].I + 4 * cpuBitsSet[opcode & 0xff];
int count = 0;
// store
- auto THUMB_STM_REG = [&](int val, int r, uint8_t b)
+ auto THUMB_STM_REG = [&](uint32_t val, uint32_t r, uint8_t b)
{
if (opcode & val)
{
@@ -1812,7 +1121,7 @@
uint32_t temp = reg[regist].I + 4 * cpuBitsSet[opcode & 0xFF];
int count = 0;
// load
- auto THUMB_LDM_REG = [&](int val, int r)
+ auto THUMB_LDM_REG = [&](uint32_t val, uint32_t r)
{
if (opcode & val)
{
@@ -2055,6 +1364,8 @@
// SWI #comment
static INSN_REGPARM void thumbDF(uint32_t opcode)
{
+ uint32_t address = 0;
+ //clockTicks = codeTicksAccessSeq16(address) * 2 + codeTicksAccess16(address) + 3;
clockTicks = 3;
busPrefetchCount = 0;
CPUSoftwareInterrupt(opcode & 0xFF);
@@ -2238,7 +1549,7 @@
thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8, // F8
thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,
thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,
- thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,
+ thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8
};
// Wrapper routine (execution loop) ///////////////////////////////////////
@@ -2247,6 +1558,9 @@
{
do
{
+ //if ((armNextPC & 0x0803FFFF) == 0x08020000)
+ // busPrefetchCount = 0x100;
+
uint32_t opcode = cpuPrefetch[0];
cpuPrefetch[0] = cpuPrefetch[1];
--- a/src/in_gsf/vbam/gba/GBA.cpp
+++ b/src/in_gsf/vbam/gba/GBA.cpp
@@ -1,6 +1,4 @@
#include <algorithm>
-#include <cstdlib>
-#include <cstring>
#include "GBA.h"
#include "GBAcpu.h"
#include "GBAinline.h"
@@ -19,7 +17,8 @@
bool busPrefetchEnable = false;
uint32_t busPrefetchCount = 0;
static int cpuDmaTicksToUpdate = 0;
-static uint32_t cpuDmaLast = 0;
+bool cpuDmaHack = false;
+uint32_t cpuDmaLast = 0;
static int dummyAddress = 0;
int cpuNextEvent = 0;
@@ -27,7 +26,6 @@
static bool intState = false;
bool stopState = false;
bool holdState = false;
-int holdType = 0;
uint32_t cpuPrefetch[2];
@@ -63,8 +61,6 @@
uint32_t dma2Dest = 0;
uint32_t dma3Source = 0;
uint32_t dma3Dest = 0;
-char buffer[1024];
-int count = 0;
static const int TIMER_TICKS[] = { 0, 6, 8, 10 };
@@ -79,6 +75,14 @@
uint8_t memoryWait32[] = { 0, 0, 5, 0, 0, 1, 1, 0, 7, 7, 9, 9, 13, 13, 4, 0 };
uint8_t memoryWaitSeq[] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4, 0 };
uint8_t memoryWaitSeq32[] = { 0, 0, 5, 0, 0, 1, 1, 0, 5, 5, 9, 9, 17, 17, 4, 0 };
+
+// The videoMemoryWait constants are used to add some waitstates
+// if the opcode access video memory data outside of vblank/hblank
+// It seems to happen on only one ticks for each pixel.
+// Not used for now (too problematic with current code).
+//const u8 videoMemoryWait[16] =
+// {0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
uint8_t biosProtected[4];
@@ -294,17 +298,18 @@
{
romSize = 0x2000000;
+ memset(&rom[0], 0, 0x2000000);
memset(&workRAM[0], 0, 0x40000);
if (cpuIsMultiBoot)
- mapgsf(workRAM, 0x40000, romSize);
+ mapgsf(&workRAM[0], 0x40000, romSize);
else
- mapgsf(rom, 0x2000000, romSize);
-
- uint16_t *temp = reinterpret_cast<uint16_t *>(rom + ((romSize + 1) & ~1));
+ mapgsf(&rom[0], 0x2000000, romSize);
+
+ auto temp = reinterpret_cast<uint16_t *>(&rom[(romSize + 1) & ~1]);
for (int i = (romSize + 1) & ~1; i < 0x2000000; i += 2)
{
- WRITE16LE(temp, (i >> 1) & 0xFFFF);
+ WRITE16LE(&temp[0], (i >> 1) & 0xFFFF);
++temp;
}
@@ -353,6 +358,9 @@
void CPUSwitchMode(int mode, bool saveState, bool breakLoop)
{
+ //if(armMode == mode)
+ // return;
+
CPUUpdateCPSR();
switch (armMode)
@@ -505,7 +513,6 @@
break;
case 0x02:
holdState = true;
- holdType = -1;
cpuNextEvent = cpuTotalTicks;
break;
case 0x03:
@@ -526,41 +533,41 @@
BIOS_ArcTan2();
break;
case 0x0B:
- {
- int len = (reg[2].I & 0x1FFFFF) >> 1;
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + len) & 0xe000000)))
- {
- if ((reg[2].I >> 24) & 1)
+ {
+ int len = (reg[2].I & 0x1FFFFF) >> 1;
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + len) & 0xe000000)))
{
- if ((reg[2].I >> 26) & 1)
- SWITicks = (7 + memoryWait32[(reg[1].I >> 24) & 0xF]) * (len >> 1);
+ if ((reg[2].I >> 24) & 1)
+ {
+ if ((reg[2].I >> 26) & 1)
+ SWITicks = (7 + memoryWait32[(reg[1].I >> 24) & 0xF]) * (len >> 1);
+ else
+ SWITicks = (8 + memoryWait[(reg[1].I >> 24) & 0xF]) * len;
+ }
else
- SWITicks = (8 + memoryWait[(reg[1].I >> 24) & 0xF]) * len;
+ {
+ if ((reg[2].I >> 26) & 1)
+ SWITicks = (10 + memoryWait32[(reg[0].I >> 24) & 0xF] + memoryWait32[(reg[1].I >> 24) & 0xF]) * (len >> 1);
+ else
+ SWITicks = (11 + memoryWait[(reg[0].I >> 24) & 0xF] + memoryWait[(reg[1].I >> 24) & 0xF]) * len;
+ }
}
- else
+ }
+ BIOS_CpuSet();
+ break;
+ case 0x0C:
+ {
+ int len = (reg[2].I & 0x1FFFFF) >> 5;
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + len) & 0xe000000)))
{
- if ((reg[2].I >> 26) & 1)
- SWITicks = (10 + memoryWait32[(reg[0].I >> 24) & 0xF] + memoryWait32[(reg[1].I >> 24) & 0xF]) * (len >> 1);
+ if ((reg[2].I >> 24) & 1)
+ SWITicks = (6 + memoryWait32[(reg[1].I >> 24) & 0xF] + 7 * (memoryWaitSeq32[(reg[1].I >> 24) & 0xF] + 1)) * len;
else
- SWITicks = (11 + memoryWait[(reg[0].I >> 24) & 0xF] + memoryWait[(reg[1].I >> 24) & 0xF]) * len;
+ SWITicks = (9 + memoryWait32[(reg[0].I >> 24) & 0xF] + memoryWait32[(reg[1].I >> 24) & 0xF] + 7 * (memoryWaitSeq32[(reg[0].I >> 24) & 0xF] + memoryWaitSeq32[(reg[1].I >> 24) & 0xF] + 2)) * len;
}
}
- BIOS_CpuSet();
- break;
- }
- case 0x0C:
- {
- int len = (reg[2].I & 0x1FFFFF) >> 5;
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + len) & 0xe000000)))
- {
- if ((reg[2].I >> 24) & 1)
- SWITicks = (6 + memoryWait32[(reg[1].I >> 24) & 0xF] + 7 * (memoryWaitSeq32[(reg[1].I >> 24) & 0xF] + 1)) * len;
- else
- SWITicks = (9 + memoryWait32[(reg[0].I >> 24) & 0xF] + memoryWait32[(reg[1].I >> 24) & 0xF] + 7 * (memoryWaitSeq32[(reg[0].I >> 24) & 0xF] + memoryWaitSeq32[(reg[1].I >> 24) & 0xF] + 2)) * len;
- }
BIOS_CpuFastSet();
break;
- }
case 0x0D:
BIOS_GetBiosChecksum();
break;
@@ -571,77 +578,77 @@
BIOS_ObjAffineSet();
break;
case 0x10:
- {
- int len = CPUReadHalfWord(reg[2].I);
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + len) & 0xe000000)))
- SWITicks = (32 + memoryWait[(reg[0].I >> 24) & 0xF]) * len;
+ {
+ int len = CPUReadHalfWord(reg[2].I);
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + len) & 0xe000000)))
+ SWITicks = (32 + memoryWait[(reg[0].I >> 24) & 0xF]) * len;
+ }
BIOS_BitUnPack();
break;
- }
case 0x11:
- {
- uint32_t len = CPUReadMemory(reg[0].I) >> 8;
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000)))
- SWITicks = (9 + memoryWait[(reg[1].I >> 24) & 0xF]) * len;
+ {
+ uint32_t len = CPUReadMemory(reg[0].I) >> 8;
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000)))
+ SWITicks = (9 + memoryWait[(reg[1].I >> 24) & 0xF]) * len;
+ }
BIOS_LZ77UnCompWram();
break;
- }
case 0x12:
- {
- uint32_t len = CPUReadMemory(reg[0].I) >> 8;
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000)))
- SWITicks = (19 + memoryWait[(reg[1].I >> 24) & 0xF]) * len;
+ {
+ uint32_t len = CPUReadMemory(reg[0].I) >> 8;
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000)))
+ SWITicks = (19 + memoryWait[(reg[1].I >> 24) & 0xF]) * len;
+ }
BIOS_LZ77UnCompVram();
break;
- }
case 0x13:
- {
- uint32_t len = CPUReadMemory(reg[0].I) >> 8;
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000)))
- SWITicks = (29 + (memoryWait[(reg[0].I >> 24) & 0xF] << 1)) * len;
+ {
+ uint32_t len = CPUReadMemory(reg[0].I) >> 8;
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000)))
+ SWITicks = (29 + (memoryWait[(reg[0].I >> 24) & 0xF] << 1)) * len;
+ }
BIOS_HuffUnComp();
break;
- }
case 0x14:
- {
- uint32_t len = CPUReadMemory(reg[0].I) >> 8;
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000)))
- SWITicks = (11 + memoryWait[(reg[0].I >> 24) & 0xF] + memoryWait[(reg[1].I >> 24) & 0xF]) * len;
+ {
+ uint32_t len = CPUReadMemory(reg[0].I) >> 8;
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000)))
+ SWITicks = (11 + memoryWait[(reg[0].I >> 24) & 0xF] + memoryWait[(reg[1].I >> 24) & 0xF]) * len;
+ }
BIOS_RLUnCompWram();
break;
- }
case 0x15:
- {
- uint32_t len = CPUReadMemory(reg[0].I) >> 9;
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000)))
- SWITicks = (34 + (memoryWait[(reg[0].I >> 24) & 0xF] << 1) + memoryWait[(reg[1].I >> 24) & 0xF]) * len;
+ {
+ uint32_t len = CPUReadMemory(reg[0].I) >> 9;
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000)))
+ SWITicks = (34 + (memoryWait[(reg[0].I >> 24) & 0xF] << 1) + memoryWait[(reg[1].I >> 24) & 0xF]) * len;
+ }
BIOS_RLUnCompVram();
break;
- }
case 0x16:
- {
- uint32_t len = CPUReadMemory(reg[0].I) >> 8;
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000)))
- SWITicks = (13 + memoryWait[(reg[0].I >> 24) & 0xF] + memoryWait[(reg[1].I >> 24) & 0xF]) * len;
+ {
+ uint32_t len = CPUReadMemory(reg[0].I) >> 8;
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000)))
+ SWITicks = (13 + memoryWait[(reg[0].I >> 24) & 0xF] + memoryWait[(reg[1].I >> 24) & 0xF]) * len;
+ }
BIOS_Diff8bitUnFilterWram();
break;
- }
case 0x17:
- {
- uint32_t len = CPUReadMemory(reg[0].I) >> 9;
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000)))
- SWITicks = (39 + (memoryWait[(reg[0].I >> 24) & 0xF] << 1) + memoryWait[(reg[1].I >> 24) & 0xF]) * len;
+ {
+ uint32_t len = CPUReadMemory(reg[0].I) >> 9;
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000)))
+ SWITicks = (39 + (memoryWait[(reg[0].I >> 24) & 0xF] << 1) + memoryWait[(reg[1].I >> 24) & 0xF]) * len;
+ }
BIOS_Diff8bitUnFilterVram();
break;
- }
case 0x18:
- {
- uint32_t len = CPUReadMemory(reg[0].I) >> 9;
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000)))
- SWITicks = (13 + memoryWait[(reg[0].I >> 24) & 0xF] + memoryWait[(reg[1].I >> 24) & 0xF]) * len;
+ {
+ uint32_t len = CPUReadMemory(reg[0].I) >> 9;
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000)))
+ SWITicks = (13 + memoryWait[(reg[0].I >> 24) & 0xF] + memoryWait[(reg[1].I >> 24) & 0xF]) * len;
+ }
BIOS_Diff16bitUnFilter();
break;
- }
case 0x19:
if (reg[0].I)
soundPause();
@@ -657,7 +664,7 @@
}
}
-void CPUCompareVCOUNT()
+static void CPUCompareVCOUNT()
{
if (VCOUNT == (DISPSTAT >> 8))
{
@@ -683,7 +690,7 @@
}
}
-void doDMA(uint32_t &s, uint32_t &d, uint32_t si, uint32_t di, uint32_t c, int transfer32)
+static void doDMA(uint32_t &s, uint32_t &d, uint32_t si, uint32_t di, uint32_t c, int transfer32)
{
int sm = s >> 24;
int dm = d >> 24;
@@ -691,11 +698,15 @@
int dw = 0;
int sc = c;
+ cpuDmaHack = true;
// This is done to get the correct waitstates.
if (sm > 15)
sm = 15;
if (dm > 15)
dm = 15;
+
+ //if ((sm>=0x05) && (sm<=0x07) || (dm>=0x05) && (dm <=0x07))
+ // blank = (((DISPSTAT | ((DISPSTAT>>1)&1))==1) ? true : false);
if (transfer32)
{
@@ -765,185 +776,174 @@
}
cpuDmaTicksToUpdate += totalTicks;
+ cpuDmaHack = false;
}
void CPUCheckDMA(int reason, int dmamask)
{
// DMA 0
- if ((DM0CNT_H & 0x8000) && (dmamask & 1))
- {
- if (((DM0CNT_H >> 12) & 3) == reason)
- {
- uint32_t sourceIncrement = 4;
- uint32_t destIncrement = 4;
- switch ((DM0CNT_H >> 7) & 3)
- {
- case 1:
- sourceIncrement = static_cast<uint32_t>(-4);
- break;
- case 2:
- sourceIncrement = 0;
- }
- switch ((DM0CNT_H >> 5) & 3)
- {
- case 1:
- destIncrement = static_cast<uint32_t>(-4);
- break;
- case 2:
- destIncrement = 0;
- }
- doDMA(dma0Source, dma0Dest, sourceIncrement, destIncrement, DM0CNT_L ? DM0CNT_L : 0x4000, DM0CNT_H & 0x0400);
-
- if (DM0CNT_H & 0x4000)
- {
- IF |= 0x0100;
- UPDATE_REG(0x202, IF);
- cpuNextEvent = cpuTotalTicks;
- }
-
- if (((DM0CNT_H >> 5) & 3) == 3)
- dma0Dest = DM0DAD_L | (DM0DAD_H << 16);
-
- if (!(DM0CNT_H & 0x0200) || !reason)
- {
- DM0CNT_H &= 0x7FFF;
- UPDATE_REG(0xBA, DM0CNT_H);
- }
+ if ((DM0CNT_H & 0x8000) && (dmamask & 1) && ((DM0CNT_H >> 12) & 3) == reason)
+ {
+ uint32_t sourceIncrement = 4;
+ uint32_t destIncrement = 4;
+ switch ((DM0CNT_H >> 7) & 3)
+ {
+ case 1:
+ sourceIncrement = static_cast<uint32_t>(-4);
+ break;
+ case 2:
+ sourceIncrement = 0;
+ }
+ switch ((DM0CNT_H >> 5) & 3)
+ {
+ case 1:
+ destIncrement = static_cast<uint32_t>(-4);
+ break;
+ case 2:
+ destIncrement = 0;
+ }
+ doDMA(dma0Source, dma0Dest, sourceIncrement, destIncrement, DM0CNT_L ? DM0CNT_L : 0x4000, DM0CNT_H & 0x0400);
+
+ if (DM0CNT_H & 0x4000)
+ {
+ IF |= 0x0100;
+ UPDATE_REG(0x202, IF);
+ cpuNextEvent = cpuTotalTicks;
+ }
+
+ if (((DM0CNT_H >> 5) & 3) == 3)
+ dma0Dest = DM0DAD_L | (DM0DAD_H << 16);
+
+ if (!(DM0CNT_H & 0x0200) || !reason)
+ {
+ DM0CNT_H &= 0x7FFF;
+ UPDATE_REG(0xBA, DM0CNT_H);
}
}
// DMA 1
- if ((DM1CNT_H & 0x8000) && (dmamask & 2))
- {
- if (((DM1CNT_H >> 12) & 3) == reason)
- {
- uint32_t sourceIncrement = 4;
- uint32_t destIncrement = 4;
- switch ((DM1CNT_H >> 7) & 3)
- {
- case 1:
- sourceIncrement = static_cast<uint32_t>(-4);
- break;
- case 2:
- sourceIncrement = 0;
- }
- switch ((DM1CNT_H >> 5) & 3)
- {
- case 1:
- destIncrement = static_cast<uint32_t>(-4);
- break;
- case 2:
- destIncrement = 0;
- }
- if (reason == 3)
- doDMA(dma1Source, dma1Dest, sourceIncrement, 0, 4, 0x0400);
- else
- doDMA(dma1Source, dma1Dest, sourceIncrement, destIncrement, DM1CNT_L ? DM1CNT_L : 0x4000, DM1CNT_H & 0x0400);
-
- if (DM1CNT_H & 0x4000)
- {
- IF |= 0x0200;
- UPDATE_REG(0x202, IF);
- cpuNextEvent = cpuTotalTicks;
- }
-
- if (((DM1CNT_H >> 5) & 3) == 3)
- dma1Dest = DM1DAD_L | (DM1DAD_H << 16);
-
- if (!(DM1CNT_H & 0x0200) || !reason)
- {
- DM1CNT_H &= 0x7FFF;
- UPDATE_REG(0xC6, DM1CNT_H);
- }
+ if ((DM1CNT_H & 0x8000) && (dmamask & 2) && ((DM1CNT_H >> 12) & 3) == reason)
+ {
+ uint32_t sourceIncrement = 4;
+ uint32_t destIncrement = 4;
+ switch ((DM1CNT_H >> 7) & 3)
+ {
+ case 1:
+ sourceIncrement = static_cast<uint32_t>(-4);
+ break;
+ case 2:
+ sourceIncrement = 0;
+ }
+ switch ((DM1CNT_H >> 5) & 3)
+ {
+ case 1:
+ destIncrement = static_cast<uint32_t>(-4);
+ break;
+ case 2:
+ destIncrement = 0;
+ }
+ if (reason == 3)
+ doDMA(dma1Source, dma1Dest, sourceIncrement, 0, 4, 0x0400);
+ else
+ doDMA(dma1Source, dma1Dest, sourceIncrement, destIncrement, DM1CNT_L ? DM1CNT_L : 0x4000, DM1CNT_H & 0x0400);
+
+ if (DM1CNT_H & 0x4000)
+ {
+ IF |= 0x0200;
+ UPDATE_REG(0x202, IF);
+ cpuNextEvent = cpuTotalTicks;
+ }
+
+ if (((DM1CNT_H >> 5) & 3) == 3)
+ dma1Dest = DM1DAD_L | (DM1DAD_H << 16);
+
+ if (!(DM1CNT_H & 0x0200) || !reason)
+ {
+ DM1CNT_H &= 0x7FFF;
+ UPDATE_REG(0xC6, DM1CNT_H);
}
}
// DMA 2
- if ((DM2CNT_H & 0x8000) && (dmamask & 4))
- {
- if (((DM2CNT_H >> 12) & 3) == reason)
- {
- uint32_t sourceIncrement = 4;
- uint32_t destIncrement = 4;
- switch ((DM2CNT_H >> 7) & 3)
- {
- case 1:
- sourceIncrement = static_cast<uint32_t>(-4);
- break;
- case 2:
- sourceIncrement = 0;
- }
- switch ((DM2CNT_H >> 5) & 3)
- {
- case 1:
- destIncrement = static_cast<uint32_t>(-4);
- break;
- case 2:
- destIncrement = 0;
- }
- if (reason == 3)
- doDMA(dma2Source, dma2Dest, sourceIncrement, 0, 4, 0x0400);
- else
- doDMA(dma2Source, dma2Dest, sourceIncrement, destIncrement, DM2CNT_L ? DM2CNT_L : 0x4000, DM2CNT_H & 0x0400);
-
- if (DM2CNT_H & 0x4000)
- {
- IF |= 0x0400;
- UPDATE_REG(0x202, IF);
- cpuNextEvent = cpuTotalTicks;
- }
-
- if (((DM2CNT_H >> 5) & 3) == 3)
- dma2Dest = DM2DAD_L | (DM2DAD_H << 16);
-
- if (!(DM2CNT_H & 0x0200) || !reason)
- {
- DM2CNT_H &= 0x7FFF;
- UPDATE_REG(0xD2, DM2CNT_H);
- }
+ if ((DM2CNT_H & 0x8000) && (dmamask & 4) && ((DM2CNT_H >> 12) & 3) == reason)
+ {
+ uint32_t sourceIncrement = 4;
+ uint32_t destIncrement = 4;
+ switch ((DM2CNT_H >> 7) & 3)
+ {
+ case 1:
+ sourceIncrement = static_cast<uint32_t>(-4);
+ break;
+ case 2:
+ sourceIncrement = 0;
+ }
+ switch ((DM2CNT_H >> 5) & 3)
+ {
+ case 1:
+ destIncrement = static_cast<uint32_t>(-4);
+ break;
+ case 2:
+ destIncrement = 0;
+ }
+ if (reason == 3)
+ doDMA(dma2Source, dma2Dest, sourceIncrement, 0, 4, 0x0400);
+ else
+ doDMA(dma2Source, dma2Dest, sourceIncrement, destIncrement, DM2CNT_L ? DM2CNT_L : 0x4000, DM2CNT_H & 0x0400);
+
+ if (DM2CNT_H & 0x4000)
+ {
+ IF |= 0x0400;
+ UPDATE_REG(0x202, IF);
+ cpuNextEvent = cpuTotalTicks;
+ }
+
+ if (((DM2CNT_H >> 5) & 3) == 3)
+ dma2Dest = DM2DAD_L | (DM2DAD_H << 16);
+
+ if (!(DM2CNT_H & 0x0200) || !reason)
+ {
+ DM2CNT_H &= 0x7FFF;
+ UPDATE_REG(0xD2, DM2CNT_H);
}
}
// DMA 3
- if ((DM3CNT_H & 0x8000) && (dmamask & 8))
- {
- if (((DM3CNT_H >> 12) & 3) == reason)
- {
- uint32_t sourceIncrement = 4;
- uint32_t destIncrement = 4;
- switch ((DM3CNT_H >> 7) & 3)
- {
- case 1:
- sourceIncrement = static_cast<uint32_t>(-4);
- break;
- case 2:
- sourceIncrement = 0;
- }
- switch ((DM3CNT_H >> 5) & 3)
- {
- case 1:
- destIncrement = static_cast<uint32_t>(-4);
- break;
- case 2:
- destIncrement = 0;
- }
- doDMA(dma3Source, dma3Dest, sourceIncrement, destIncrement, DM3CNT_L ? DM3CNT_L : 0x10000, DM3CNT_H & 0x0400);
-
- if (DM3CNT_H & 0x4000)
- {
- IF |= 0x0800;
- UPDATE_REG(0x202, IF);
- cpuNextEvent = cpuTotalTicks;
- }
-
- if (((DM3CNT_H >> 5) & 3) == 3)
- dma3Dest = DM3DAD_L | (DM3DAD_H << 16);
-
- if (!(DM3CNT_H & 0x0200) || !reason)
- {
- DM3CNT_H &= 0x7FFF;
- UPDATE_REG(0xDE, DM3CNT_H);
- }
+ if ((DM3CNT_H & 0x8000) && (dmamask & 8) && ((DM3CNT_H >> 12) & 3) == reason)
+ {
+ uint32_t sourceIncrement = 4;
+ uint32_t destIncrement = 4;
+ switch ((DM3CNT_H >> 7) & 3)
+ {
+ case 1:
+ sourceIncrement = static_cast<uint32_t>(-4);
+ break;
+ case 2:
+ sourceIncrement = 0;
+ }
+ switch ((DM3CNT_H >> 5) & 3)
+ {
+ case 1:
+ destIncrement = static_cast<uint32_t>(-4);
+ break;
+ case 2:
+ destIncrement = 0;
+ }
+ doDMA(dma3Source, dma3Dest, sourceIncrement, destIncrement, DM3CNT_L ? DM3CNT_L : 0x10000, DM3CNT_H & 0x0400);
+
+ if (DM3CNT_H & 0x4000)
+ {
+ IF |= 0x0800;
+ UPDATE_REG(0x202, IF);
+ cpuNextEvent = cpuTotalTicks;
+ }
+
+ if (((DM3CNT_H >> 5) & 3) == 3)
+ dma3Dest = DM3DAD_L | (DM3DAD_H << 16);
+
+ if (!(DM3CNT_H & 0x0200) || !reason)
+ {
+ DM3CNT_H &= 0x7FFF;
+ UPDATE_REG(0xDE, DM3CNT_H);
}
}
}
@@ -953,41 +953,41 @@
switch (address)
{
case 0x00:
- {
- if ((value & 7) > 5)
- // display modes above 0-5 are prohibited
- DISPCNT = value & 7;
- bool change = !!((DISPCNT ^ value) & 0x80);
- uint16_t changeBGon = (~DISPCNT & value) & 0x0F00; // these layers are being activated
-
- DISPCNT = value & 0xFFF7; // bit 3 can only be accessed by the BIOS to enable GBC mode
- UPDATE_REG(0x00, DISPCNT);
-
- if (changeBGon)
- {
- layerEnableDelay = 4;
- layerEnable = layerSettings & value & ~changeBGon;
- }
- else
- {
- layerEnable = layerSettings & value;
- //CPUUpdateTicks();
- }
-
- if (change && !(value & 0x80))
- {
- if (!(DISPSTAT & 1))
+ {
+ if ((value & 7) > 5)
+ // display modes above 0-5 are prohibited
+ DISPCNT = value & 7;
+ bool change = !!((DISPCNT ^ value) & 0x80);
+ uint16_t changeBGon = (~DISPCNT & value) & 0x0F00; // these layers are being activated
+
+ DISPCNT = value & 0xFFF7; // bit 3 can only be accessed by the BIOS to enable GBC mode
+ UPDATE_REG(0x00, DISPCNT);
+
+ if (changeBGon)
{
- lcdTicks = 1008;
- //VCOUNT = 0;
- //UPDATE_REG(0x06, VCOUNT);
- DISPSTAT &= 0xFFFC;
- UPDATE_REG(0x04, DISPSTAT);
- CPUCompareVCOUNT();
+ layerEnableDelay = 4;
+ layerEnable = layerSettings & value & ~changeBGon;
}
- }
- break;
- }
+ else
+ {
+ layerEnable = layerSettings & value;
+ // CPUUpdateTicks();
+ }
+
+ if (change && !(value & 0x80))
+ {
+ if (!(DISPSTAT & 1))
+ {
+ //lcdTicks = 1008;
+ //VCOUNT = 0;
+ //UPDATE_REG(0x06, VCOUNT);
+ DISPSTAT &= 0xFFFC;
+ UPDATE_REG(0x04, DISPSTAT);
+ CPUCompareVCOUNT();
+ }
+ }
+ }
+ break;
case 0x04:
DISPSTAT = (value & 0xFF38) | (DISPSTAT & 7);
UPDATE_REG(0x04, DISPSTAT);
@@ -1199,21 +1199,21 @@
UPDATE_REG(0xB8, 0);
break;
case 0xBA:
- {
- bool start = !!((DM0CNT_H ^ value) & 0x8000);
- value &= 0xF7E0;
-
- DM0CNT_H = value;
- UPDATE_REG(0xBA, DM0CNT_H);
-
- if (start && (value & 0x8000))
- {
- dma0Source = DM0SAD_L | (DM0SAD_H << 16);
- dma0Dest = DM0DAD_L | (DM0DAD_H << 16);
- CPUCheckDMA(0, 1);
- }
- break;
- }
+ {
+ bool start = !!((DM0CNT_H ^ value) & 0x8000);
+ value &= 0xF7E0;
+
+ DM0CNT_H = value;
+ UPDATE_REG(0xBA, DM0CNT_H);
+
+ if (start && (value & 0x8000))
+ {
+ dma0Source = DM0SAD_L | (DM0SAD_H << 16);
+ dma0Dest = DM0DAD_L | (DM0DAD_H << 16);
+ CPUCheckDMA(0, 1);
+ }
+ }
+ break;
case 0xBC:
DM1SAD_L = value;
UPDATE_REG(0xBC, DM1SAD_L);
@@ -1235,21 +1235,21 @@
UPDATE_REG(0xC4, 0);
break;
case 0xC6:
- {
- bool start = !!((DM1CNT_H ^ value) & 0x8000);
- value &= 0xF7E0;
-
- DM1CNT_H = value;
- UPDATE_REG(0xC6, DM1CNT_H);
-
- if (start && (value & 0x8000))
- {
- dma1Source = DM1SAD_L | (DM1SAD_H << 16);
- dma1Dest = DM1DAD_L | (DM1DAD_H << 16);
- CPUCheckDMA(0, 2);
- }
- break;
- }
+ {
+ bool start = !!((DM1CNT_H ^ value) & 0x8000);
+ value &= 0xF7E0;
+
+ DM1CNT_H = value;
+ UPDATE_REG(0xC6, DM1CNT_H);
+
+ if (start && (value & 0x8000))
+ {
+ dma1Source = DM1SAD_L | (DM1SAD_H << 16);
+ dma1Dest = DM1DAD_L | (DM1DAD_H << 16);
+ CPUCheckDMA(0, 2);
+ }
+ }
+ break;
case 0xC8:
DM2SAD_L = value;
UPDATE_REG(0xC8, DM2SAD_L);
@@ -1271,21 +1271,21 @@
UPDATE_REG(0xD0, 0);
break;
case 0xD2:
- {
- bool start = !!((DM2CNT_H ^ value) & 0x8000);
- value &= 0xF7E0;
-
- DM2CNT_H = value;
- UPDATE_REG(0xD2, DM2CNT_H);
-
- if (start && (value & 0x8000))
- {
- dma2Source = DM2SAD_L | (DM2SAD_H << 16);
- dma2Dest = DM2DAD_L | (DM2DAD_H << 16);
- CPUCheckDMA(0, 4);
- }
- break;
- }
+ {
+ bool start = !!((DM2CNT_H ^ value) & 0x8000);
+ value &= 0xF7E0;
+
+ DM2CNT_H = value;
+ UPDATE_REG(0xD2, DM2CNT_H);
+
+ if (start && (value & 0x8000))
+ {
+ dma2Source = DM2SAD_L | (DM2SAD_H << 16);
+ dma2Dest = DM2DAD_L | (DM2DAD_H << 16);
+ CPUCheckDMA(0, 4);
+ }
+ }
+ break;
case 0xD4:
DM3SAD_L = value;
UPDATE_REG(0xD4, DM3SAD_L);
@@ -1307,21 +1307,21 @@
UPDATE_REG(0xDC, 0);
break;
case 0xDE:
- {
- bool start = !!((DM3CNT_H ^ value) & 0x8000);
- value &= 0xFFE0;
-
- DM3CNT_H = value;
- UPDATE_REG(0xDE, DM3CNT_H);
-
- if (start && (value & 0x8000))
- {
- dma3Source = DM3SAD_L | (DM3SAD_H << 16);
- dma3Dest = DM3DAD_L | (DM3DAD_H << 16);
- CPUCheckDMA(0, 8);
- }
- break;
- }
+ {
+ bool start = !!((DM3CNT_H ^ value) & 0x8000);
+ value &= 0xFFE0;
+
+ DM3CNT_H = value;
+ UPDATE_REG(0xDE, DM3CNT_H);
+
+ if (start && (value & 0x8000))
+ {
+ dma3Source = DM3SAD_L | (DM3SAD_H << 16);
+ dma3Dest = DM3DAD_L | (DM3DAD_H << 16);
+ CPUCheckDMA(0, 8);
+ }
+ }
+ break;
case 0x100:
timer0Reload = value;
break;
@@ -1396,7 +1396,6 @@
busPrefetch = false;
busPrefetchCount = 0;
UPDATE_REG(0x204, value & 0x7FFF);
-
break;
case 0x208:
IME = value & 1;
@@ -1414,7 +1413,7 @@
}
}
-void applyTimer()
+static void applyTimer()
{
if (timerOnOffDelay & 1)
{
@@ -1478,7 +1477,6 @@
}
uint8_t cpuBitsSet[256];
-uint8_t cpuLowestBitSet[256];
void CPUInit()
{
@@ -1491,7 +1489,7 @@
}
#endif
- memcpy(&bios[0], &myROM[0], sizeof(myROM));
+ memcpy(&bios[0], myROM, sizeof(myROM));
biosProtected[0] = 0x00;
biosProtected[1] = 0xf0;
@@ -1501,16 +1499,10 @@
for (int i = 0; i < 256; ++i)
{
int count = 0;
- int j;
- for (j = 0; j < 8; ++j)
+ for (int j = 0; j < 8; ++j)
if (i & (1 << j))
++count;
cpuBitsSet[i] = count;
-
- for (j = 0; j < 8; ++j)
- if (i & (1 << j))
- break;
- cpuLowestBitSet[i] = j;
}
std::fill(&ioReadable[0], &ioReadable[0x304], true);
@@ -1658,7 +1650,6 @@
// reset internal state
holdState = false;
- holdType = 0;
biosProtected[0] = 0x00;
biosProtected[1] = 0xf0;
@@ -1728,10 +1719,12 @@
ARM_PREFETCH();
+ cpuDmaHack = false;
+
SWITicks = 0;
}
-void CPUInterrupt()
+static void CPUInterrupt()
{
uint32_t PC = reg[15].I;
bool savedState = armState;
@@ -1747,7 +1740,7 @@
reg[15].I += 4;
ARM_PREFETCH();
- //if(!holdState)
+ //if (!holdState)
biosProtected[0] = 0x02;
biosProtected[1] = 0xc0;
biosProtected[2] = 0x5e;
@@ -1801,7 +1794,6 @@
cpuTotalTicks = 0;
updateLoop:
-
if (IRQTicks)
{
IRQTicks -= clockTicks;
@@ -1837,7 +1829,7 @@
}
}
- if (VCOUNT >= 228) //Reaching last line
+ if (VCOUNT > 227) //Reaching last line
{
DISPSTAT &= 0xFFFC;
UPDATE_REG(0x04, DISPSTAT);
@@ -1858,10 +1850,6 @@
DISPSTAT &= 0xFFFD;
if (VCOUNT == 160)
{
- ++count;
- if (count == 60)
- count = 0;
-
DISPSTAT |= 1;
DISPSTAT &= 0xFFFD;
UPDATE_REG(0x04, DISPSTAT);
@@ -2070,7 +2058,6 @@
intState = false;
holdState = false;
stopState = false;
- holdType = 0;
}
}
else
@@ -2087,7 +2074,6 @@
CPUInterrupt();
holdState = false;
stopState = false;
- holdType = 0;
}
}
--- a/src/in_gsf/vbam/gba/GBA.h
+++ b/src/in_gsf/vbam/gba/GBA.h
@@ -1,5 +1,4 @@
-#ifndef GBA_H
-#define GBA_H
+#pragma once
#include <cstdint>
@@ -42,9 +41,7 @@
#endif
};
-#ifndef NO_GBA_MAP
extern memoryMap map[256];
-#endif
extern reg_pair reg[45];
extern uint8_t biosProtected[4];
@@ -57,37 +54,38 @@
extern bool armState;
extern int armMode;
-extern int CPULoadRom();
-extern void CPUUpdateRegister(uint32_t, uint16_t);
-extern void CPUInit();
-extern void CPUReset();
-extern void CPULoop(int);
-extern void CPUCheckDMA(int, int);
+int CPULoadRom();
+void CPUUpdateRegister(uint32_t, uint16_t);
+void CPUInit();
+void CPUReset();
+void CPULoop(int);
+void CPUCheckDMA(int, int);
-const uint32_t R13_IRQ = 18;
-const uint32_t R14_IRQ = 19;
-const uint32_t SPSR_IRQ = 20;
-const uint32_t R13_USR = 26;
-const uint32_t R14_USR = 27;
-const uint32_t R13_SVC = 28;
-const uint32_t R14_SVC = 29;
-const uint32_t SPSR_SVC = 30;
-const uint32_t R13_ABT = 31;
-const uint32_t R14_ABT = 32;
-const uint32_t SPSR_ABT = 33;
-const uint32_t R13_UND = 34;
-const uint32_t R14_UND = 35;
-const uint32_t SPSR_UND = 36;
-const uint32_t R8_FIQ = 37;
-const uint32_t R9_FIQ = 38;
-const uint32_t R10_FIQ = 39;
-const uint32_t R11_FIQ = 40;
-const uint32_t R12_FIQ = 41;
-const uint32_t R13_FIQ = 42;
-const uint32_t R14_FIQ = 43;
-const uint32_t SPSR_FIQ = 44;
+enum
+{
+ R13_IRQ = 18,
+ R14_IRQ,
+ SPSR_IRQ,
+ R13_USR = 26,
+ R14_USR,
+ R13_SVC,
+ R14_SVC,
+ SPSR_SVC,
+ R13_ABT,
+ R14_ABT,
+ SPSR_ABT,
+ R13_UND,
+ R14_UND,
+ SPSR_UND,
+ R8_FIQ,
+ R9_FIQ,
+ R10_FIQ,
+ R11_FIQ,
+ R12_FIQ,
+ R13_FIQ,
+ R14_FIQ,
+ SPSR_FIQ
+};
#include "Globals.h"
-#endif // GBA_H
-
--- a/src/in_gsf/vbam/gba/GBAcpu.h
+++ b/src/in_gsf/vbam/gba/GBAcpu.h
@@ -1,10 +1,9 @@
-#ifndef GBACPU_H
-#define GBACPU_H
+#pragma once
#include "GBAinline.h"
-extern int armExecute();
-extern int thumbExecute();
+int armExecute();
+int thumbExecute();
#ifdef __GNUC__
# ifndef __APPLE__
@@ -12,8 +11,8 @@
# else
# define INSN_REGPARM /*nothing*/
# endif
-# define LIKELY(x) __builtin_expect(!!(x),1)
-# define UNLIKELY(x) __builtin_expect(!!(x),0)
+# define LIKELY(x) __builtin_expect(!!(x), 1)
+# define UNLIKELY(x) __builtin_expect(!!(x), 0)
#else
# define INSN_REGPARM /*nothing*/
# define LIKELY(x) (x)
@@ -49,11 +48,12 @@
extern uint8_t memoryWaitSeq[16];
extern uint8_t memoryWaitSeq32[16];
extern uint8_t cpuBitsSet[256];
-extern void CPUSwitchMode(int mode, bool saveState, bool breakLoop = true);
-extern void CPUUpdateCPSR();
-extern void CPUUpdateFlags(bool breakLoop = true);
-extern void CPUUndefinedException();
-extern void CPUSoftwareInterrupt(int comment);
+
+void CPUSwitchMode(int mode, bool saveState, bool breakLoop = true);
+void CPUUpdateCPSR();
+void CPUUpdateFlags(bool breakLoop = true);
+void CPUUndefinedException();
+void CPUSoftwareInterrupt(int comment);
// Waitstates when accessing data
inline int dataTicksAccess16(uint32_t address) // DATA 8/16bits NON SEQ
@@ -81,27 +81,6 @@
{
int addr = (address >> 24) & 15;
int value = memoryWait32[addr];
-
- if (addr >= 0x08 || addr < 0x02)
- {
- busPrefetchCount = 0;
- busPrefetch = false;
- }
- else if (busPrefetch)
- {
- int waitState = value;
- if (!waitState)
- waitState = 1;
- busPrefetchCount = ((busPrefetchCount + 1) << waitState) - 1;
- }
-
- return value;
-}
-
-inline int dataTicksAccessSeq16(uint32_t address) // DATA 8/16bits SEQ
-{
- int addr = (address >> 24) & 15;
- int value = memoryWaitSeq[addr];
if (addr >= 0x08 || addr < 0x02)
{
@@ -253,5 +232,3 @@
return memoryWaitSeq32[addr];
}
-#endif // GBACPU_H
-
--- a/src/in_gsf/vbam/gba/GBAinline.h
+++ b/src/in_gsf/vbam/gba/GBAinline.h
@@ -1,5 +1,4 @@
-#ifndef GBAINLINE_H
-#define GBAINLINE_H
+#pragma once
#include "../common/Port.h"
#include "Sound.h"
@@ -8,8 +7,9 @@
extern bool stopState;
extern bool holdState;
-extern int holdType;
extern int cpuNextEvent;
+extern bool cpuDmaHack;
+extern uint32_t cpuDmaLast;
extern bool timer0On;
extern int timer0Ticks;
extern int timer0ClockReload;
@@ -24,6 +24,8 @@
extern int timer3ClockReload;
extern int cpuTotalTicks;
+inline uint8_t CPUReadByteQuick(uint32_t addr) { return map[addr >> 24].address[addr & map[addr >> 24].mask]; }
+
inline uint16_t CPUReadHalfWordQuick(uint32_t addr) { return READ16LE(&map[addr >> 24].address[addr & map[addr >> 24].mask]); }
inline uint32_t CPUReadMemoryQuick(uint32_t addr) { return READ32LE(&map[addr >> 24].address[addr & map[addr >> 24].mask]); }
@@ -42,7 +44,7 @@
if (reg[15].I >> 24)
{
if (address < 0x4000)
- value = READ32LE(&biosProtected);
+ value = READ32LE(&biosProtected[0]);
else
goto unreadable;
}
@@ -92,44 +94,31 @@
break;
case 13:
case 14:
- return 0;
+ case 15:
+ value = 0;
+ break;
// default
default:
unreadable:
- if (armState)
- return CPUReadMemoryQuick(reg[15].I);
- else
- return CPUReadHalfWordQuick(reg[15].I) | (CPUReadHalfWordQuick(reg[15].I) << 16);
+ if (cpuDmaHack)
+ value = cpuDmaLast;
+ else
+ {
+ if (armState)
+ return CPUReadMemoryQuick(reg[15].I);
+ else
+ return CPUReadHalfWordQuick(reg[15].I) | CPUReadHalfWordQuick(reg[15].I) << 16;
+ }
}
if (oldAddress & 3)
{
-#ifdef C_CORE
int shift = (oldAddress & 3) << 3;
value = (value >> shift) | (value << (32 - shift));
-#else
-# ifdef __GNUC__
- asm("and $3, %%ecx;"
- "shl $3 ,%%ecx;"
- "ror %%cl, %0"
- : "=r" (value)
- : "r" (value), "c" (oldAddress));
-# else
- __asm
- {
- mov ecx, oldAddress;
- and ecx, 3;
- shl ecx, 3;
- ror [dword ptr value], cl;
- }
-# endif
-#endif
}
return value;
}
-
-extern uint32_t myROM[];
inline uint32_t CPUReadHalfWord(uint32_t address)
{
@@ -174,6 +163,8 @@
value = 0xFFFF - ((timer3Ticks - cpuTotalTicks) >> timer3ClockReload);
}
}
+ else if (address < 0x4000400 && ioReadable[address & 0x3fc])
+ value = 0;
else
goto unreadable;
break;
@@ -204,12 +195,24 @@
else
value = READ16LE(&rom[address & 0x1FFFFFE]);
break;
+ case 13:
+ case 14:
+ case 15:
+ value = 0;
+ break;
+ // default
default:
unreadable:
- if (armState)
- return CPUReadMemoryQuick(reg[15].I);
- else
- return CPUReadHalfWordQuick(reg[15].I) | (CPUReadHalfWordQuick(reg[15].I) << 16);
+ if (cpuDmaHack)
+ value = cpuDmaLast & 0xFFFF;
+ else
+ {
+ if (armState)
+ value = CPUReadHalfWordQuick(reg[15].I + (address & 2));
+ else
+ value = CPUReadHalfWordQuick(reg[15].I);
+ }
+ return value;
}
if (oldAddress & 1)
@@ -220,13 +223,7 @@
inline int16_t CPUReadHalfWordSigned(uint32_t address)
{
- uint32_t oldAddress = address;
- if (address & 1)
- address &= ~0x01;
- int16_t value = static_cast<int16_t>(CPUReadHalfWord(address));
- if (oldAddress & 1)
- value = static_cast<int8_t>(value);
- return value;
+ return static_cast<int16_t>(CPUReadHalfWord(address));
}
inline uint8_t CPUReadByte(uint32_t address)
@@ -239,7 +236,7 @@
if (address < 0x4000)
return biosProtected[address & 3];
else
- goto unreadable;
+ break;
}
return bios[address & 0x3FFF];
case 2:
@@ -250,7 +247,7 @@
if (address < 0x4000400 && ioReadable[address & 0x3ff])
return ioMem[address & 0x3ff];
else
- goto unreadable;
+ break;
case 5:
return paletteRAM[address & 0x3ff];
case 6:
@@ -268,12 +265,19 @@
case 11:
case 12:
return rom[address & 0x1FFFFFF];
- default:
- unreadable:
- if (armState)
- return CPUReadMemoryQuick(reg[15].I);
- else
- return CPUReadHalfWordQuick(reg[15].I) | (CPUReadHalfWordQuick(reg[15].I) << 16);
+ case 13:
+ case 14:
+ case 15:
+ return 0;
+ }
+ if (cpuDmaHack)
+ return cpuDmaLast & 0xFF;
+ else
+ {
+ if (armState)
+ return CPUReadByteQuick(reg[15].I + (address & 3));
+ else
+ return CPUReadByteQuick(reg[15].I + (address & 1));
}
}
@@ -305,6 +309,7 @@
return;
if ((address & 0x18000) == 0x18000)
address &= 0x17fff;
+
WRITE32LE(&vram[address], value);
break;
case 0x07:
@@ -405,7 +410,6 @@
if (b == 0x80)
stopState = true;
holdState = true;
- holdType = -1;
cpuNextEvent = cpuTotalTicks;
break;
default: // every other register
@@ -415,7 +419,6 @@
else
CPUUpdateRegister(lowerBits, (READ16LE(&ioMem[lowerBits]) & 0xFF00) | b);
}
- break;
}
break;
case 5:
@@ -442,5 +445,3 @@
}
}
-#endif // GBAINLINE_H
-
--- a/src/in_gsf/vbam/gba/Globals.h
+++ b/src/in_gsf/vbam/gba/Globals.h
@@ -1,5 +1,4 @@
-#ifndef GLOBALS_H
-#define GLOBALS_H
+#pragma once
#include <cstdint>
#include "GBA.h"
@@ -105,5 +104,3 @@
extern uint16_t IF;
extern uint16_t IME;
-#endif // GLOBALS_H
-
--- a/src/in_gsf/vbam/gba/Sound.cpp
+++ b/src/in_gsf/vbam/gba/Sound.cpp
@@ -8,7 +8,6 @@
#include "../common/SoundDriver.h"
extern SoundDriver *systemSoundInit();
-bool soundDeclicking = true;
static const uint32_t NR52 = 0x84;
@@ -20,12 +19,12 @@
static long soundSampleRate = 44100;
bool soundInterpolation = true;
static bool soundPaused = true;
-static float soundFiltering = 0.5f; // 0.0 = none, 1.0 = max
+static float soundFiltering = 1.0f;
int SOUND_CLOCK_TICKS = SOUND_CLOCK_TICKS_;
int soundTicks = SOUND_CLOCK_TICKS_;
static float soundVolume = 1.0f;
-static int soundEnableFlag = 0x30f; // emulator channels enabled
+static int soundEnableFlag = 0x3ff; // emulator channels enabled
static float soundFiltering_ = -1;
static float soundVolume_ = -1;
@@ -85,11 +84,11 @@
void Gba_Pcm::apply_control(int idx)
{
- this->shift = (~ioMem[SGCNT0_H] >> (2 + idx)) & 1;
+ this->shift = ~ioMem[SGCNT0_H] >> (2 + idx) & 1;
int ch = 0;
- if (((soundEnableFlag >> idx) & 0x100) && (ioMem[NR52] & 0x80))
- ch = (ioMem[SGCNT0_H + 1] >> (idx * 4)) & 3;
+ if ((soundEnableFlag >> idx & 0x100) && (ioMem[NR52] & 0x80))
+ ch = ioMem[SGCNT0_H + 1] >> (idx * 4) & 3;
Blip_Buffer *out = nullptr;
switch (ch)
@@ -108,7 +107,7 @@
{
if (this->output)
{
- blip_time_t time = blip_time();
+ auto time = blip_time();
this->output->set_modified();
@@ -147,7 +146,7 @@
{
if (this->output)
{
- blip_time_t time = blip_time();
+ auto time = blip_time();
dac = static_cast<int8_t>(dac) >> this->shift;
int delta = dac - this->last_amp;
@@ -179,15 +178,19 @@
{
if (which_timer == this->timer && this->enabled)
{
- if (this->count <= 16)
+ /* Mother 3 fix, refined to not break Metroid Fusion */
+ if (this->count == 16 || !this->count)
{
// Need to fill FIFO
+ int saved_count = this->count;
CPUCheckDMA(3, this->which ? 4 : 2);
- if (this->count <= 16)
+ if (!saved_count && this->count == 16)
+ CPUCheckDMA(3, this->which ? 4 : 2);
+ if (!this->count)
{
// Not filled by DMA, so fill with 16 bytes of silence
int reg = this->which ? FIFOB_L : FIFOA_L;
- for (int n = 4; n--; )
+ for (int n = 8; n--; )
{
soundEvent(reg, static_cast<uint16_t>(0));
soundEvent(reg + 2, static_cast<uint16_t>(0));
@@ -412,7 +415,7 @@
if (gb_apu)
// APU
for (int i = 0; i < 4; ++i)
- if ((soundEnableFlag >> i) & 1)
+ if (soundEnableFlag >> i & 1)
gb_apu->set_output(stereo_buffer->center(), stereo_buffer->left(), stereo_buffer->right(), i);
else
gb_apu->set_output(nullptr, nullptr, nullptr, i);
@@ -420,7 +423,7 @@
static void reset_apu()
{
- gb_apu->reduce_clicks(soundDeclicking);
+ gb_apu->reduce_clicks(true);
gb_apu->reset(gb_apu->mode_agb, true);
if (stereo_buffer)
--- a/src/in_gsf/vbam/gba/Sound.h
+++ b/src/in_gsf/vbam/gba/Sound.h
@@ -1,5 +1,4 @@
-#ifndef SOUND_H
-#define SOUND_H
+#pragma once
// Sound emulation setup/options and GBA sound emulation
@@ -37,11 +36,14 @@
//// GBA sound emulation
// GBA sound registers
-const uint32_t SGCNT0_H = 0x82;
-const uint32_t FIFOA_L = 0xa0;
-const uint32_t FIFOA_H = 0xa2;
-const uint32_t FIFOB_L = 0xa4;
-const uint32_t FIFOB_H = 0xa6;
+enum
+{
+ SGCNT0_H = 0x82,
+ FIFOA_L = 0xa0,
+ FIFOA_H = 0xa2,
+ FIFOB_L = 0xa4,
+ FIFOB_H = 0xa6
+};
// Resets emulated sound hardware
void soundReset();
@@ -62,5 +64,3 @@
void flush_samples(Multi_Buffer *buffer);
-#endif // SOUND_H
-
--- a/src/in_gsf/vbam/gba/bios.cpp
+++ b/src/in_gsf/vbam/gba/bios.cpp
@@ -62,31 +62,25 @@
uint32_t res = 0;
if (!y)
res = (x >> 16) & 0x8000;
+ else if (!x)
+ res = ((y >> 16) & 0x8000) + 0x4000;
+ else if (std::abs(x) > std::abs(y) || (std::abs(x) == std::abs(y) && !(x < 0 && y < 0)))
+ {
+ reg[1].I = x;
+ reg[0].I = y << 14;
+ BIOS_Div();
+ BIOS_ArcTan();
+ if (x < 0)
+ res = 0x8000 + reg[0].I;
+ else
+ res = (((y >> 16) & 0x8000) << 1) + reg[0].I;
+ }
else
{
- if (!x)
- res = ((y >> 16) & 0x8000) + 0x4000;
- else
- {
- if (std::abs(x) > std::abs(y) || (std::abs(x) == std::abs(y) && !(x < 0 && y < 0)))
- {
- reg[1].I = x;
- reg[0].I = y << 14;
- BIOS_Div();
- BIOS_ArcTan();
- if (x < 0)
- res = 0x8000 + reg[0].I;
- else
- res = (((y >> 16) & 0x8000) << 1) + reg[0].I;
- }
- else
- {
- reg[0].I = x << 14;
- BIOS_Div();
- BIOS_ArcTan();
- res = (0x4000 + ((y >> 16) & 0x8000)) - reg[0].I;
- }
- }
+ reg[0].I = x << 14;
+ BIOS_Div();
+ BIOS_ArcTan();
+ res = (0x4000 + ((y >> 16) & 0x8000)) - reg[0].I;
}
reg[0].I = res;
}
@@ -118,8 +112,7 @@
if (len < 0)
break;
int mask = 0xff >> revbits;
- uint8_t b = CPUReadByte(source);
- ++source;
+ uint8_t b = CPUReadByte(source++);
int bitcount = 0;
while (1)
{
@@ -629,6 +622,7 @@
writeValue |= CPUReadByte(source++) << byteShift;
byteShift += 8;
++byteCount;
+
if (byteCount == 2)
{
CPUWriteHalfWord(dest, writeValue);
@@ -990,7 +984,7 @@
void BIOS_MidiKey2Freq()
{
int freq = CPUReadMemory(reg[0].I + 4);
- double tmp = (180 - reg[1].I) - (reg[2].I / 256.0);
+ double tmp = (180.0 - reg[1].I) - (reg[2].I / 256.0);
tmp = std::pow(2.0, tmp / 12.0);
reg[0].I = static_cast<int>(freq / tmp);
}
--- a/src/in_gsf/vbam/gba/bios.h
+++ b/src/in_gsf/vbam/gba/bios.h
@@ -1,29 +1,26 @@
-#ifndef BIOS_H
-#define BIOS_H
+#pragma once
-extern void BIOS_ArcTan();
-extern void BIOS_ArcTan2();
-extern void BIOS_BitUnPack();
-extern void BIOS_GetBiosChecksum();
-extern void BIOS_BgAffineSet();
-extern void BIOS_CpuSet();
-extern void BIOS_CpuFastSet();
-extern void BIOS_Diff8bitUnFilterWram();
-extern void BIOS_Diff8bitUnFilterVram();
-extern void BIOS_Diff16bitUnFilter();
-extern void BIOS_Div();
-extern void BIOS_HuffUnComp();
-extern void BIOS_LZ77UnCompVram();
-extern void BIOS_LZ77UnCompWram();
-extern void BIOS_ObjAffineSet();
-extern void BIOS_RegisterRamReset();
-extern void BIOS_RegisterRamReset(uint32_t);
-extern void BIOS_RLUnCompVram();
-extern void BIOS_RLUnCompWram();
-extern void BIOS_SoftReset();
-extern void BIOS_Sqrt();
-extern void BIOS_MidiKey2Freq();
-extern void BIOS_SndDriverJmpTableCopy();
+void BIOS_ArcTan();
+void BIOS_ArcTan2();
+void BIOS_BitUnPack();
+void BIOS_GetBiosChecksum();
+void BIOS_BgAffineSet();
+void BIOS_CpuSet();
+void BIOS_CpuFastSet();
+void BIOS_Diff8bitUnFilterWram();
+void BIOS_Diff8bitUnFilterVram();
+void BIOS_Diff16bitUnFilter();
+void BIOS_Div();
+void BIOS_HuffUnComp();
+void BIOS_LZ77UnCompVram();
+void BIOS_LZ77UnCompWram();
+void BIOS_ObjAffineSet();
+void BIOS_RegisterRamReset();
+void BIOS_RegisterRamReset(uint32_t);
+void BIOS_RLUnCompVram();
+void BIOS_RLUnCompWram();
+void BIOS_SoftReset();
+void BIOS_Sqrt();
+void BIOS_MidiKey2Freq();
+void BIOS_SndDriverJmpTableCopy();
-#endif // BIOS_H
-
--- a/src/in_gsf/vbam/revision.txt
+++ b/src/in_gsf/vbam/revision.txt
@@ -1,1 +1,1 @@
-1195
+1231