[GSF] Cleanup, a tiny bit of making sure it was like viogsf, also used the standard integer types and not VBA-M's typedefs.
--- a/src/in_gsf/in_gsf.vcxproj
+++ b/src/in_gsf/in_gsf.vcxproj
@@ -83,7 +83,6 @@
<ClCompile Include="vbam\apu\Blip_Buffer.cpp" />
<ClCompile Include="vbam\apu\Effects_Buffer.cpp" />
<ClCompile Include="vbam\apu\Gb_Apu.cpp" />
- <ClCompile Include="vbam\apu\Gb_Apu_State.cpp" />
<ClCompile Include="vbam\apu\Gb_Oscs.cpp" />
<ClCompile Include="vbam\apu\Multi_Buffer.cpp" />
<ClCompile Include="vbam\gba\bios.cpp" />
@@ -106,6 +105,7 @@
<ClInclude Include="vbam\apu\Multi_Buffer.h" />
<ClInclude Include="vbam\common\Port.h" />
<ClInclude Include="vbam\common\SoundDriver.h" />
+ <ClInclude Include="vbam\common\Types.h" />
<ClInclude Include="vbam\gba\bios.h" />
<ClInclude Include="vbam\gba\GBA.h" />
<ClInclude Include="vbam\gba\GBAcpu.h" />
--- a/src/in_gsf/in_gsf.vcxproj.filters
+++ b/src/in_gsf/in_gsf.vcxproj.filters
@@ -75,9 +75,6 @@
<ClCompile Include="XSFConfig_GSF.cpp">
<Filter>Source Files</Filter>
</ClCompile>
- <ClCompile Include="vbam\apu\Gb_Apu_State.cpp">
- <Filter>Source Files\vbam\apu</Filter>
- </ClCompile>
</ItemGroup>
<ItemGroup>
<ClInclude Include="vbam\apu\blargg_common.h">
@@ -128,5 +125,8 @@
<ClInclude Include="vbam\gba\Sound.h">
<Filter>Header Files\vbam\gba</Filter>
</ClInclude>
+ <ClInclude Include="vbam\common\Types.h">
+ <Filter>Header Files\vbam\common</Filter>
+ </ClInclude>
</ItemGroup>
</Project>
--- a/src/in_gsf/vbam/apu/Blip_Buffer.cpp
+++ b/src/in_gsf/vbam/apu/Blip_Buffer.cpp
@@ -29,7 +29,7 @@
Blip_Buffer::Blip_Buffer()
{
- factor_ = (blip_ulong)LONG_MAX;
+ factor_ = LONG_MAX;
buffer_ = 0;
buffer_size_ = 0;
sample_rate_ = 0;
--- a/src/in_gsf/vbam/apu/Gb_Apu.h
+++ b/src/in_gsf/vbam/apu/Gb_Apu.h
@@ -78,16 +78,6 @@
// tempo in a game music player.
void set_tempo( double );
-// Save states
-
- // Saves full emulation state to state_out. Data format is portable and
- // includes some extra space to avoid expansion in case more state needs
- // to be stored in the future.
- void save_state( gb_apu_state_t* state_out );
-
- // Loads state. You should call reset() BEFORE this.
- blargg_err_t load_state( gb_apu_state_t const& in );
-
public:
Gb_Apu();
@@ -131,8 +121,6 @@
void run_until( blip_time_t );
void silence_osc( Gb_Osc& );
void write_osc( int index, int reg, int old_data, int data );
- const char* save_load( gb_apu_state_t*, bool save );
- void save_load2( gb_apu_state_t*, bool save );
friend class Gb_Apu_Tester;
public:
--- a/src/in_gsf/vbam/apu/Gb_Apu_State.cpp
+++ /dev/null
@@ -1,120 +1,1 @@
-// Gb_Snd_Emu $vers. http://www.slack.net/~ant/
-#include "Gb_Apu.h"
-
-#include <string.h>
-
-/* Copyright (C) 2007 Shay Green. This module is free software; you
-can redistribute it and/or modify it under the terms of the GNU Lesser
-General Public License as published by the Free Software Foundation; either
-version 2.1 of the License, or (at your option) any later version. This
-module is distributed in the hope that it will be useful, but WITHOUT ANY
-WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-details. You should have received a copy of the GNU Lesser General Public
-License along with this module; if not, write to the Free Software Foundation,
-Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
-
-#include "blargg_source.h"
-
-#if GB_APU_CUSTOM_STATE
- #define REFLECT( x, y ) (save ? (io->y) = (x) : (x) = (io->y) )
-#else
- #define REFLECT( x, y ) (save ? set_val( io->y, x ) : (void) ((x) = get_val( io->y )))
-
- static blargg_ulong get_val( byte const* p )
- {
- return p [3] * 0x1000000 + p [2] * 0x10000 + p [1] * 0x100 + p [0];
- }
-
- static void set_val( byte* p, blargg_ulong n )
- {
- p [0] = (byte) (n );
- p [1] = (byte) (n >> 8);
- p [2] = (byte) (n >> 16);
- p [3] = (byte) (n >> 24);
- }
-#endif
-
-inline const char* Gb_Apu::save_load( gb_apu_state_t* io, bool save )
-{
- #if !GB_APU_CUSTOM_STATE
- assert( sizeof (gb_apu_state_t) == 256 );
- #endif
-
- int format = io->format0;
- REFLECT( format, format );
- if ( format != io->format0 )
- return "Unsupported sound save state format";
-
- int version = 0;
- REFLECT( version, version );
-
- // Registers and wave RAM
- assert( regs_size == sizeof io->regs );
- if ( save )
- memcpy( io->regs, regs, sizeof io->regs );
- else
- memcpy( regs, io->regs, sizeof regs );
-
- // Frame sequencer
- REFLECT( frame_time, frame_time );
- REFLECT( frame_phase, frame_phase );
-
- REFLECT( square1.sweep_freq, sweep_freq );
- REFLECT( square1.sweep_delay, sweep_delay );
- REFLECT( square1.sweep_enabled, sweep_enabled );
- REFLECT( square1.sweep_neg, sweep_neg );
-
- REFLECT( noise.divider, noise_divider );
- REFLECT( wave.sample_buf, wave_buf );
-
- return 0;
-}
-
-// second function to avoid inline limits of some compilers
-inline void Gb_Apu::save_load2( gb_apu_state_t* io, bool save )
-{
- for ( int i = osc_count; --i >= 0; )
- {
- Gb_Osc& osc = *oscs [i];
- REFLECT( osc.delay, delay [i] );
- REFLECT( osc.length_ctr, length_ctr [i] );
- REFLECT( osc.phase, phase [i] );
- REFLECT( osc.enabled, enabled [i] );
-
- if ( i != 2 )
- {
- int j = min( i, 2 );
- Gb_Env& env = STATIC_CAST(Gb_Env&,osc);
- REFLECT( env.env_delay, env_delay [j] );
- REFLECT( env.volume, env_volume [j] );
- REFLECT( env.env_enabled, env_enabled [j] );
- }
- }
-}
-
-void Gb_Apu::save_state( gb_apu_state_t* out )
-{
- (void) save_load( out, true );
- save_load2( out, true );
-
- #if !GB_APU_CUSTOM_STATE
- memset( out->unused, 0, sizeof out->unused );
- #endif
-}
-
-blargg_err_t Gb_Apu::load_state( gb_apu_state_t const& in )
-{
- RETURN_ERR( save_load( CONST_CAST(gb_apu_state_t*,&in), false ) );
- save_load2( CONST_CAST(gb_apu_state_t*,&in), false );
-
- apply_stereo();
- synth_volume( 0 ); // suppress output for the moment
- run_until_( last_time ); // get last_amp updated
- apply_volume(); // now use correct volume
-
- return 0;
-}
-
-
--- a/src/in_gsf/vbam/common/Port.h
+++ b/src/in_gsf/vbam/common/Port.h
@@ -4,13 +4,13 @@
#include "Types.h"
// swaps a 16-bit value
-static inline u16 swap16(u16 v)
+static inline uint16_t swap16(uint16_t v)
{
return (v<<8)|(v>>8);
}
// swaps a 32-bit value
-static inline u32 swap32(u32 v)
+static inline uint32_t swap32(uint32_t v)
{
return (v<<24)|((v<<8)&0xff0000)|((v>>8)&0xff00)|(v>>24);
}
@@ -36,23 +36,23 @@
#else
#define READ16LE(x) \
- swap16(*((u16 *)(x)))
+ swap16(*((uint16_t *)(x)))
#define READ32LE(x) \
- swap32(*((u32 *)(x)))
+ swap32(*((uint32_t *)(x)))
#define WRITE16LE(x,v) \
- *((u16 *)x) = swap16((v))
+ *((uint16_t *)x) = swap16((v))
#define WRITE32LE(x,v) \
- *((u32 *)x) = swap32((v))
+ *((uint32_t *)x) = swap32((v))
#endif
#else
#define READ16LE(x) \
- *((u16 *)x)
+ *((uint16_t *)x)
#define READ32LE(x) \
- *((u32 *)x)
+ *((uint32_t *)x)
#define WRITE16LE(x,v) \
- *((u16 *)x) = (v)
+ *((uint16_t *)x) = (v)
#define WRITE32LE(x,v) \
- *((u32 *)x) = (v)
+ *((uint32_t *)x) = (v)
#endif
#endif // PORT_H
--- a/src/in_gsf/vbam/common/SoundDriver.h
+++ b/src/in_gsf/vbam/common/SoundDriver.h
@@ -57,7 +57,7 @@
/**
* Write length bytes of data from the finalWave buffer to the driver output buffer.
*/
- virtual void write(u16 * finalWave, int length) = 0;
+ virtual void write(uint16_t * finalWave, int length) = 0;
virtual void setThrottle(unsigned short throttle) { };
};
--- a/src/in_gsf/vbam/common/Types.h
+++ b/src/in_gsf/vbam/common/Types.h
@@ -20,7 +20,7 @@
#include <stdint.h>
-typedef uint8_t u8;
+/*typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
typedef uint64_t u64;
@@ -28,7 +28,7 @@
typedef int8_t s8;
typedef int16_t s16;
typedef int32_t s32;
-typedef int64_t s64;
+typedef int64_t s64;*/
#endif // __VBA_TYPES_H__
--- a/src/in_gsf/vbam/gba/GBA-arm.cpp
+++ b/src/in_gsf/vbam/gba/GBA-arm.cpp
@@ -35,7 +35,7 @@
static int clockTicks;
-static INSN_REGPARM void armUnknownInsn(u32 opcode)
+static INSN_REGPARM void armUnknownInsn(uint32_t opcode)
{
#ifdef GBA_LOGGING
if (systemVerbose & VERBOSE_UNDEFINED) {
@@ -47,7 +47,7 @@
}
#ifdef BKPT_SUPPORT
-static INSN_REGPARM void armBreakpoint(u32 opcode)
+static INSN_REGPARM void armBreakpoint(uint32_t opcode)
{
reg[15].I -= 4;
armNextPC -= 4;
@@ -60,7 +60,7 @@
// Subroutine to count instructions (for debugging/optimizing)
//#define INSN_COUNTER // comment out if you don't want it
#ifdef INSN_COUNTER
-static void count(u32 opcode, int cond_res)
+static void count(uint32_t opcode, int cond_res)
{
static int insncount = 0; // number of insns seen
static int executed = 0; // number of insns executed
@@ -716,11 +716,11 @@
// C core
#define C_SETCOND_LOGICAL \
- N_FLAG = ((s32)res < 0) ? true : false; \
+ N_FLAG = ((int32_t)res < 0) ? true : false; \
Z_FLAG = (res == 0) ? true : false; \
C_FLAG = C_OUT;
#define C_SETCOND_ADD \
- N_FLAG = ((s32)res < 0) ? true : false; \
+ N_FLAG = ((int32_t)res < 0) ? true : false; \
Z_FLAG = (res == 0) ? true : false; \
V_FLAG = ((NEG(lhs) & NEG(rhs) & POS(res)) | \
(POS(lhs) & POS(rhs) & NEG(res))) ? true : false;\
@@ -728,7 +728,7 @@
(NEG(lhs) & POS(res)) | \
(NEG(rhs) & POS(res))) ? true : false;
#define C_SETCOND_SUB \
- N_FLAG = ((s32)res < 0) ? true : false; \
+ N_FLAG = ((int32_t)res < 0) ? true : false; \
Z_FLAG = (res == 0) ? true : false; \
V_FLAG = ((NEG(lhs) & POS(rhs) & POS(res)) | \
(POS(lhs) & NEG(rhs) & NEG(res))) ? true : false;\
@@ -740,7 +740,7 @@
#define ALU_INIT_C \
int dest = (opcode>>12) & 15; \
bool C_OUT = C_FLAG; \
- u32 value;
+ uint32_t value;
#endif
// OP Rd,Rb,Rm LSL #
#ifndef VALUE_LSL_IMM_C
@@ -749,7 +749,7 @@
if (LIKELY(!shift)) { /* LSL #0 most common? */ \
value = reg[opcode & 0x0F].I; \
} else { \
- u32 v = reg[opcode & 0x0F].I; \
+ uint32_t v = reg[opcode & 0x0F].I; \
C_OUT = (v >> (32 - shift)) & 1 ? true : false; \
value = v << shift; \
}
@@ -757,8 +757,8 @@
// OP Rd,Rb,Rm LSL Rs
#ifndef VALUE_LSL_REG_C
#define VALUE_LSL_REG_C \
- u32 shift = reg[(opcode >> 8)&15].B.B0; \
- u32 rm = reg[opcode & 0x0F].I; \
+ uint32_t shift = reg[(opcode >> 8)&15].B.B0; \
+ uint32_t rm = reg[opcode & 0x0F].I; \
if((opcode & 0x0F) == 15) { \
rm += 4; \
} \
@@ -767,7 +767,7 @@
value = 0; \
C_OUT = (rm & 1 ? true : false); \
} else if (LIKELY(shift < 32)) { \
- u32 v = rm; \
+ uint32_t v = rm; \
C_OUT = (v >> (32 - shift)) & 1 ? true : false;\
value = v << shift; \
} else { \
@@ -781,9 +781,9 @@
// OP Rd,Rb,Rm LSR #
#ifndef VALUE_LSR_IMM_C
#define VALUE_LSR_IMM_C \
- u32 shift = (opcode >> 7) & 0x1F; \
+ uint32_t shift = (opcode >> 7) & 0x1F; \
if (LIKELY(shift)) { \
- u32 v = reg[opcode & 0x0F].I; \
+ uint32_t v = reg[opcode & 0x0F].I; \
C_OUT = (v >> (shift - 1)) & 1 ? true : false; \
value = v >> shift; \
} else { \
@@ -795,7 +795,7 @@
#ifndef VALUE_LSR_REG_C
#define VALUE_LSR_REG_C \
unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
- u32 rm = reg[opcode & 0x0F].I; \
+ uint32_t rm = reg[opcode & 0x0F].I; \
if((opcode & 0x0F) == 15) { \
rm += 4; \
} \
@@ -804,7 +804,7 @@
value = 0; \
C_OUT = (rm & 0x80000000 ? true : false);\
} else if (LIKELY(shift < 32)) { \
- u32 v = rm; \
+ uint32_t v = rm; \
C_OUT = (v >> (shift - 1)) & 1 ? true : false;\
value = v >> shift; \
} else { \
@@ -821,7 +821,7 @@
unsigned int shift = (opcode >> 7) & 0x1F; \
if (LIKELY(shift)) { \
/* VC++ BUG: u32 v; (s32)v>>n is optimized to shr! */ \
- s32 v = reg[opcode & 0x0F].I; \
+ int32_t v = reg[opcode & 0x0F].I; \
C_OUT = (v >> (int)(shift - 1)) & 1 ? true : false;\
value = v >> (int)shift; \
} else { \
@@ -838,13 +838,13 @@
#ifndef VALUE_ASR_REG_C
#define VALUE_ASR_REG_C \
unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
- u32 rm = reg[opcode & 0x0F].I; \
+ uint32_t rm = reg[opcode & 0x0F].I; \
if((opcode & 0x0F) == 15) { \
rm += 4; \
} \
if (LIKELY(shift < 32)) { \
if (LIKELY(shift)) { \
- s32 v = rm; \
+ int32_t v = rm; \
C_OUT = (v >> (int)(shift - 1)) & 1 ? true : false;\
value = v >> (int)shift; \
} else { \
@@ -865,12 +865,12 @@
#define VALUE_ROR_IMM_C \
unsigned int shift = (opcode >> 7) & 0x1F; \
if (LIKELY(shift)) { \
- u32 v = reg[opcode & 0x0F].I; \
+ uint32_t v = reg[opcode & 0x0F].I; \
C_OUT = (v >> (shift - 1)) & 1 ? true : false; \
value = ((v << (32 - shift)) | \
(v >> shift)); \
} else { \
- u32 v = reg[opcode & 0x0F].I; \
+ uint32_t v = reg[opcode & 0x0F].I; \
C_OUT = (v & 1) ? true : false; \
value = ((v >> 1) | \
(C_FLAG << 31)); \
@@ -880,12 +880,12 @@
#ifndef VALUE_ROR_REG_C
#define VALUE_ROR_REG_C \
unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
- u32 rm = reg[opcode & 0x0F].I; \
+ uint32_t rm = reg[opcode & 0x0F].I; \
if((opcode & 0x0F) == 15) { \
rm += 4; \
} \
if (LIKELY(shift & 0x1F)) { \
- u32 v = rm; \
+ uint32_t v = rm; \
C_OUT = (v >> (shift - 1)) & 1 ? true : false; \
value = ((v << (32 - shift)) | \
(v >> shift)); \
@@ -900,7 +900,7 @@
#define VALUE_IMM_C \
int shift = (opcode & 0xF00) >> 7; \
if (UNLIKELY(shift)) { \
- u32 v = opcode & 0xFF; \
+ uint32_t v = opcode & 0xFF; \
C_OUT = (v >> (shift - 1)) & 1 ? true : false; \
value = ((v << (32 - shift)) | \
(v >> shift)); \
@@ -945,7 +945,7 @@
#define C_CHECK_PC(SETCOND) if (LIKELY(dest != 15)) { SETCOND }
#ifndef OP_AND
#define OP_AND \
- u32 res = reg[(opcode>>16)&15].I & value; \
+ uint32_t res = reg[(opcode>>16)&15].I & value; \
reg[dest].I = res;
#endif
#ifndef OP_ANDS
@@ -953,7 +953,7 @@
#endif
#ifndef OP_EOR
#define OP_EOR \
- u32 res = reg[(opcode>>16)&15].I ^ value; \
+ uint32_t res = reg[(opcode>>16)&15].I ^ value; \
reg[dest].I = res;
#endif
#ifndef OP_EORS
@@ -961,9 +961,9 @@
#endif
#ifndef OP_SUB
#define OP_SUB \
- u32 lhs = reg[(opcode>>16)&15].I; \
- u32 rhs = value; \
- u32 res = lhs - rhs; \
+ uint32_t lhs = reg[(opcode>>16)&15].I; \
+ uint32_t rhs = value; \
+ uint32_t res = lhs - rhs; \
reg[dest].I = res;
#endif
#ifndef OP_SUBS
@@ -971,9 +971,9 @@
#endif
#ifndef OP_RSB
#define OP_RSB \
- u32 lhs = value; \
- u32 rhs = reg[(opcode>>16)&15].I; \
- u32 res = lhs - rhs; \
+ uint32_t lhs = value; \
+ uint32_t rhs = reg[(opcode>>16)&15].I; \
+ uint32_t res = lhs - rhs; \
reg[dest].I = res;
#endif
#ifndef OP_RSBS
@@ -981,9 +981,9 @@
#endif
#ifndef OP_ADD
#define OP_ADD \
- u32 lhs = reg[(opcode>>16)&15].I; \
- u32 rhs = value; \
- u32 res = lhs + rhs; \
+ uint32_t lhs = reg[(opcode>>16)&15].I; \
+ uint32_t rhs = value; \
+ uint32_t res = lhs + rhs; \
reg[dest].I = res;
#endif
#ifndef OP_ADDS
@@ -991,9 +991,9 @@
#endif
#ifndef OP_ADC
#define OP_ADC \
- u32 lhs = reg[(opcode>>16)&15].I; \
- u32 rhs = value; \
- u32 res = lhs + rhs + (u32)C_FLAG; \
+ uint32_t lhs = reg[(opcode>>16)&15].I; \
+ uint32_t rhs = value; \
+ uint32_t res = lhs + rhs + (uint32_t)C_FLAG; \
reg[dest].I = res;
#endif
#ifndef OP_ADCS
@@ -1001,9 +1001,9 @@
#endif
#ifndef OP_SBC
#define OP_SBC \
- u32 lhs = reg[(opcode>>16)&15].I; \
- u32 rhs = value; \
- u32 res = lhs - rhs - !((u32)C_FLAG); \
+ uint32_t lhs = reg[(opcode>>16)&15].I; \
+ uint32_t rhs = value; \
+ uint32_t res = lhs - rhs - !((uint32_t)C_FLAG); \
reg[dest].I = res;
#endif
#ifndef OP_SBCS
@@ -1011,9 +1011,9 @@
#endif
#ifndef OP_RSC
#define OP_RSC \
- u32 lhs = value; \
- u32 rhs = reg[(opcode>>16)&15].I; \
- u32 res = lhs - rhs - !((u32)C_FLAG); \
+ uint32_t lhs = value; \
+ uint32_t rhs = reg[(opcode>>16)&15].I; \
+ uint32_t res = lhs - rhs - !((uint32_t)C_FLAG); \
reg[dest].I = res;
#endif
#ifndef OP_RSCS
@@ -1021,31 +1021,31 @@
#endif
#ifndef OP_TST
#define OP_TST \
- u32 res = reg[(opcode >> 16) & 0x0F].I & value; \
+ uint32_t res = reg[(opcode >> 16) & 0x0F].I & value; \
C_SETCOND_LOGICAL;
#endif
#ifndef OP_TEQ
#define OP_TEQ \
- u32 res = reg[(opcode >> 16) & 0x0F].I ^ value; \
+ uint32_t res = reg[(opcode >> 16) & 0x0F].I ^ value; \
C_SETCOND_LOGICAL;
#endif
#ifndef OP_CMP
#define OP_CMP \
- u32 lhs = reg[(opcode>>16)&15].I; \
- u32 rhs = value; \
- u32 res = lhs - rhs; \
+ uint32_t lhs = reg[(opcode>>16)&15].I; \
+ uint32_t rhs = value; \
+ uint32_t res = lhs - rhs; \
C_SETCOND_SUB;
#endif
#ifndef OP_CMN
#define OP_CMN \
- u32 lhs = reg[(opcode>>16)&15].I; \
- u32 rhs = value; \
- u32 res = lhs + rhs; \
+ uint32_t lhs = reg[(opcode>>16)&15].I; \
+ uint32_t rhs = value; \
+ uint32_t res = lhs + rhs; \
C_SETCOND_ADD;
#endif
#ifndef OP_ORR
#define OP_ORR \
- u32 res = reg[(opcode >> 16) & 0x0F].I | value; \
+ uint32_t res = reg[(opcode >> 16) & 0x0F].I | value; \
reg[dest].I = res;
#endif
#ifndef OP_ORRS
@@ -1053,7 +1053,7 @@
#endif
#ifndef OP_MOV
#define OP_MOV \
- u32 res = value; \
+ uint32_t res = value; \
reg[dest].I = res;
#endif
#ifndef OP_MOVS
@@ -1061,7 +1061,7 @@
#endif
#ifndef OP_BIC
#define OP_BIC \
- u32 res = reg[(opcode >> 16) & 0x0F].I & (~value); \
+ uint32_t res = reg[(opcode >> 16) & 0x0F].I & (~value); \
reg[dest].I = res;
#endif
#ifndef OP_BICS
@@ -1069,7 +1069,7 @@
#endif
#ifndef OP_MVN
#define OP_MVN \
- u32 res = ~value; \
+ uint32_t res = ~value; \
reg[dest].I = res;
#endif
#ifndef OP_MVNS
@@ -1081,7 +1081,7 @@
#endif
#ifndef SETCOND_MUL
#define SETCOND_MUL \
- N_FLAG = ((s32)reg[dest].I < 0) ? true : false; \
+ N_FLAG = ((int32_t)reg[dest].I < 0) ? true : false; \
Z_FLAG = reg[dest].I ? false : true;
#endif
#ifndef SETCOND_MULL
@@ -1096,7 +1096,7 @@
#ifndef ROR_IMM_MSR
#define ROR_IMM_MSR \
- u32 v = opcode & 0xff; \
+ uint32_t v = opcode & 0xff; \
value = ((v << (32 - shift)) | (v >> shift));
#endif
#ifndef ROR_OFFSET
@@ -1144,25 +1144,25 @@
#define MODECHANGE_YES CPUSwitchMode(reg[17].I & 0x1f, false);
#define DEFINE_ALU_INSN_C(CODE1, CODE2, OP, MODECHANGE) \
- static INSN_REGPARM void arm##CODE1##0(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSL_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\
- static INSN_REGPARM void arm##CODE1##1(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSL_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\
- static INSN_REGPARM void arm##CODE1##2(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\
- static INSN_REGPARM void arm##CODE1##3(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\
- static INSN_REGPARM void arm##CODE1##4(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_ASR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\
- static INSN_REGPARM void arm##CODE1##5(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_ASR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\
- static INSN_REGPARM void arm##CODE1##6(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_ROR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\
- static INSN_REGPARM void arm##CODE1##7(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_ROR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\
- static INSN_REGPARM void arm##CODE2##0(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }
+ static INSN_REGPARM void arm##CODE1##0(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSL_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\
+ static INSN_REGPARM void arm##CODE1##1(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSL_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\
+ static INSN_REGPARM void arm##CODE1##2(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\
+ static INSN_REGPARM void arm##CODE1##3(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\
+ static INSN_REGPARM void arm##CODE1##4(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_ASR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\
+ static INSN_REGPARM void arm##CODE1##5(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_ASR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\
+ static INSN_REGPARM void arm##CODE1##6(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_ROR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\
+ static INSN_REGPARM void arm##CODE1##7(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_ROR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\
+ static INSN_REGPARM void arm##CODE2##0(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }
#define DEFINE_ALU_INSN_NC(CODE1, CODE2, OP, MODECHANGE) \
- static INSN_REGPARM void arm##CODE1##0(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSL_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\
- static INSN_REGPARM void arm##CODE1##1(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSL_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\
- static INSN_REGPARM void arm##CODE1##2(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\
- static INSN_REGPARM void arm##CODE1##3(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\
- static INSN_REGPARM void arm##CODE1##4(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ASR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\
- static INSN_REGPARM void arm##CODE1##5(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ASR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\
- static INSN_REGPARM void arm##CODE1##6(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ROR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\
- static INSN_REGPARM void arm##CODE1##7(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ROR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\
- static INSN_REGPARM void arm##CODE2##0(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }
+ static INSN_REGPARM void arm##CODE1##0(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSL_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\
+ static INSN_REGPARM void arm##CODE1##1(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSL_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\
+ static INSN_REGPARM void arm##CODE1##2(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\
+ static INSN_REGPARM void arm##CODE1##3(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\
+ static INSN_REGPARM void arm##CODE1##4(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ASR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\
+ static INSN_REGPARM void arm##CODE1##5(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ASR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\
+ static INSN_REGPARM void arm##CODE1##6(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ROR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\
+ static INSN_REGPARM void arm##CODE1##7(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ROR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\
+ static INSN_REGPARM void arm##CODE2##0(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }
// AND
DEFINE_ALU_INSN_NC(00, 20, AND, NO)
@@ -1243,12 +1243,12 @@
// CYCLES: base cycle count (1, 2, or 3)
#define MUL_INSN(OP, SETCOND, CYCLES) \
int mult = (opcode & 0x0F); \
- u32 rs = reg[(opcode >> 8) & 0x0F].I; \
+ uint32_t rs = reg[(opcode >> 8) & 0x0F].I; \
int acc = (opcode >> 12) & 0x0F; /* or destLo */ \
int dest = (opcode >> 16) & 0x0F; /* or destHi */ \
OP; \
SETCOND; \
- if ((s32)rs < 0) \
+ if ((int32_t)rs < 0) \
rs = ~rs; \
if ((rs & 0xFFFFFF00) == 0) \
clockTicks += 0; \
@@ -1267,58 +1267,58 @@
#define OP_MLA \
reg[dest].I = reg[mult].I * rs + reg[acc].I;
#define OP_MULL(SIGN) \
- SIGN##64 res = (SIGN##64)(SIGN##32)reg[mult].I \
- * (SIGN##64)(SIGN##32)rs; \
- reg[acc].I = (u32)res; \
- reg[dest].I = (u32)(res >> 32);
+ SIGN##64_t res = (SIGN##64_t)(SIGN##32_t)reg[mult].I \
+ * (SIGN##64_t)(SIGN##32_t)rs; \
+ reg[acc].I = (uint32_t)res; \
+ reg[dest].I = (uint32_t)(res >> 32);
#define OP_MLAL(SIGN) \
- SIGN##64 res = ((SIGN##64)reg[dest].I<<32 | reg[acc].I)\
- + ((SIGN##64)(SIGN##32)reg[mult].I \
- * (SIGN##64)(SIGN##32)rs); \
- reg[acc].I = (u32)res; \
- reg[dest].I = (u32)(res >> 32);
-#define OP_UMULL OP_MULL(u)
-#define OP_UMLAL OP_MLAL(u)
-#define OP_SMULL OP_MULL(s)
-#define OP_SMLAL OP_MLAL(s)
+ SIGN##64_t res = ((SIGN##64_t)reg[dest].I<<32 | reg[acc].I)\
+ + ((SIGN##64_t)(SIGN##32_t)reg[mult].I \
+ * (SIGN##64_t)(SIGN##32_t)rs); \
+ reg[acc].I = (uint32_t)res; \
+ reg[dest].I = (uint32_t)(res >> 32);
+#define OP_UMULL OP_MULL(uint)
+#define OP_UMLAL OP_MLAL(uint)
+#define OP_SMULL OP_MULL(int)
+#define OP_SMLAL OP_MLAL(int)
// MUL Rd, Rm, Rs
-static INSN_REGPARM void arm009(u32 opcode) { MUL_INSN(OP_MUL, SETCOND_NONE, 1); }
+static INSN_REGPARM void arm009(uint32_t opcode) { MUL_INSN(OP_MUL, SETCOND_NONE, 1); }
// MULS Rd, Rm, Rs
-static INSN_REGPARM void arm019(u32 opcode) { MUL_INSN(OP_MUL, SETCOND_MUL, 1); }
+static INSN_REGPARM void arm019(uint32_t opcode) { MUL_INSN(OP_MUL, SETCOND_MUL, 1); }
// MLA Rd, Rm, Rs, Rn
-static INSN_REGPARM void arm029(u32 opcode) { MUL_INSN(OP_MLA, SETCOND_NONE, 2); }
+static INSN_REGPARM void arm029(uint32_t opcode) { MUL_INSN(OP_MLA, SETCOND_NONE, 2); }
// MLAS Rd, Rm, Rs, Rn
-static INSN_REGPARM void arm039(u32 opcode) { MUL_INSN(OP_MLA, SETCOND_MUL, 2); }
+static INSN_REGPARM void arm039(uint32_t opcode) { MUL_INSN(OP_MLA, SETCOND_MUL, 2); }
// UMULL RdLo, RdHi, Rn, Rs
-static INSN_REGPARM void arm089(u32 opcode) { MUL_INSN(OP_UMULL, SETCOND_NONE, 2); }
+static INSN_REGPARM void arm089(uint32_t opcode) { MUL_INSN(OP_UMULL, SETCOND_NONE, 2); }
// UMULLS RdLo, RdHi, Rn, Rs
-static INSN_REGPARM void arm099(u32 opcode) { MUL_INSN(OP_UMULL, SETCOND_MULL, 2); }
+static INSN_REGPARM void arm099(uint32_t opcode) { MUL_INSN(OP_UMULL, SETCOND_MULL, 2); }
// UMLAL RdLo, RdHi, Rn, Rs
-static INSN_REGPARM void arm0A9(u32 opcode) { MUL_INSN(OP_UMLAL, SETCOND_NONE, 3); }
+static INSN_REGPARM void arm0A9(uint32_t opcode) { MUL_INSN(OP_UMLAL, SETCOND_NONE, 3); }
// UMLALS RdLo, RdHi, Rn, Rs
-static INSN_REGPARM void arm0B9(u32 opcode) { MUL_INSN(OP_UMLAL, SETCOND_MULL, 3); }
+static INSN_REGPARM void arm0B9(uint32_t opcode) { MUL_INSN(OP_UMLAL, SETCOND_MULL, 3); }
// SMULL RdLo, RdHi, Rm, Rs
-static INSN_REGPARM void arm0C9(u32 opcode) { MUL_INSN(OP_SMULL, SETCOND_NONE, 2); }
+static INSN_REGPARM void arm0C9(uint32_t opcode) { MUL_INSN(OP_SMULL, SETCOND_NONE, 2); }
// SMULLS RdLo, RdHi, Rm, Rs
-static INSN_REGPARM void arm0D9(u32 opcode) { MUL_INSN(OP_SMULL, SETCOND_MULL, 2); }
+static INSN_REGPARM void arm0D9(uint32_t opcode) { MUL_INSN(OP_SMULL, SETCOND_MULL, 2); }
// SMLAL RdLo, RdHi, Rm, Rs
-static INSN_REGPARM void arm0E9(u32 opcode) { MUL_INSN(OP_SMLAL, SETCOND_NONE, 3); }
+static INSN_REGPARM void arm0E9(uint32_t opcode) { MUL_INSN(OP_SMLAL, SETCOND_NONE, 3); }
// SMLALS RdLo, RdHi, Rm, Rs
-static INSN_REGPARM void arm0F9(u32 opcode) { MUL_INSN(OP_SMLAL, SETCOND_MULL, 3); }
+static INSN_REGPARM void arm0F9(uint32_t opcode) { MUL_INSN(OP_SMLAL, SETCOND_MULL, 3); }
// Misc instructions //////////////////////////////////////////////////////
// SWP Rd, Rm, [Rn]
-static INSN_REGPARM void arm109(u32 opcode)
-{
- u32 address = reg[(opcode >> 16) & 15].I;
- u32 temp = CPUReadMemory(address);
+static INSN_REGPARM void arm109(uint32_t opcode)
+{
+ uint32_t address = reg[(opcode >> 16) & 15].I;
+ uint32_t temp = CPUReadMemory(address);
CPUWriteMemory(address, reg[opcode&15].I);
reg[(opcode >> 12) & 15].I = temp;
clockTicks = 4 + dataTicksAccess32(address) + dataTicksAccess32(address)
@@ -1326,10 +1326,10 @@
}
// SWPB Rd, Rm, [Rn]
-static INSN_REGPARM void arm149(u32 opcode)
-{
- u32 address = reg[(opcode >> 16) & 15].I;
- u32 temp = CPUReadByte(address);
+static INSN_REGPARM void arm149(uint32_t opcode)
+{
+ uint32_t address = reg[(opcode >> 16) & 15].I;
+ uint32_t temp = CPUReadByte(address);
CPUWriteByte(address, reg[opcode&15].B.B0);
reg[(opcode>>12)&15].I = temp;
clockTicks = 4 + dataTicksAccess32(address) + dataTicksAccess32(address)
@@ -1337,7 +1337,7 @@
}
// MRS Rd, CPSR
-static INSN_REGPARM void arm100(u32 opcode)
+static INSN_REGPARM void arm100(uint32_t opcode)
{
if (LIKELY((opcode & 0x0FFF0FFF) == 0x010F0000)) {
CPUUpdateCPSR();
@@ -1348,7 +1348,7 @@
}
// MRS Rd, SPSR
-static INSN_REGPARM void arm140(u32 opcode)
+static INSN_REGPARM void arm140(uint32_t opcode)
{
if (LIKELY((opcode & 0x0FFF0FFF) == 0x014F0000)) {
reg[(opcode >> 12) & 0x0F].I = reg[17].I;
@@ -1358,12 +1358,12 @@
}
// MSR CPSR_fields, Rm
-static INSN_REGPARM void arm120(u32 opcode)
+static INSN_REGPARM void arm120(uint32_t opcode)
{
if (LIKELY((opcode & 0x0FF0FFF0) == 0x0120F000)) {
CPUUpdateCPSR();
- u32 value = reg[opcode & 15].I;
- u32 newValue = reg[16].I;
+ uint32_t value = reg[opcode & 15].I;
+ uint32_t newValue = reg[16].I;
if (armMode > 0x10) {
if (opcode & 0x00010000)
newValue = (newValue & 0xFFFFFF00) | (value & 0x000000FF);
@@ -1388,10 +1388,10 @@
}
// MSR SPSR_fields, Rm
-static INSN_REGPARM void arm160(u32 opcode)
+static INSN_REGPARM void arm160(uint32_t opcode)
{
if (LIKELY((opcode & 0x0FF0FFF0) == 0x0160F000)) {
- u32 value = reg[opcode & 15].I;
+ uint32_t value = reg[opcode & 15].I;
if (armMode > 0x10 && armMode < 0x1F) {
if (opcode & 0x00010000)
reg[17].I = (reg[17].I & 0xFFFFFF00) | (value & 0x000000FF);
@@ -1408,16 +1408,16 @@
}
// MSR CPSR_fields, #
-static INSN_REGPARM void arm320(u32 opcode)
+static INSN_REGPARM void arm320(uint32_t opcode)
{
if (LIKELY((opcode & 0x0FF0F000) == 0x0320F000)) {
CPUUpdateCPSR();
- u32 value = opcode & 0xFF;
+ uint32_t value = opcode & 0xFF;
int shift = (opcode & 0xF00) >> 7;
if (shift) {
ROR_IMM_MSR;
}
- u32 newValue = reg[16].I;
+ uint32_t newValue = reg[16].I;
if (armMode > 0x10) {
if (opcode & 0x00010000)
newValue = (newValue & 0xFFFFFF00) | (value & 0x000000FF);
@@ -1444,11 +1444,11 @@
}
// MSR SPSR_fields, #
-static INSN_REGPARM void arm360(u32 opcode)
+static INSN_REGPARM void arm360(uint32_t opcode)
{
if (LIKELY((opcode & 0x0FF0F000) == 0x0360F000)) {
if (armMode > 0x10 && armMode < 0x1F) {
- u32 value = opcode & 0xFF;
+ uint32_t value = opcode & 0xFF;
int shift = (opcode & 0xF00) >> 7;
if (shift) {
ROR_IMM_MSR;
@@ -1468,7 +1468,7 @@
}
// BX Rm
-static INSN_REGPARM void arm121(u32 opcode)
+static INSN_REGPARM void arm121(uint32_t opcode)
{
if (LIKELY((opcode & 0x0FFFFFF0) == 0x012FFF10)) {
int base = opcode & 0x0F;
@@ -1513,14 +1513,14 @@
int shift = (opcode >> 7) & 31; \
int offset; \
if (shift) \
- offset = (int)((s32)reg[opcode & 15].I >> shift);\
+ offset = (int)((int32_t)reg[opcode & 15].I >> shift);\
else if (reg[opcode & 15].I & 0x80000000) \
offset = 0xFFFFFFFF; \
else \
offset = 0;
#define OFFSET_ROR \
int shift = (opcode >> 7) & 31; \
- u32 offset = reg[opcode & 15].I; \
+ uint32_t offset = reg[opcode & 15].I; \
if (shift) { \
ROR_OFFSET; \
} else { \
@@ -1537,8 +1537,8 @@
#define OP_LDR reg[dest].I = CPUReadMemory(address)
#define OP_LDRH reg[dest].I = CPUReadHalfWord(address)
#define OP_LDRB reg[dest].I = CPUReadByte(address)
-#define OP_LDRSH reg[dest].I = (u32)CPUReadHalfWordSigned(address)
-#define OP_LDRSB reg[dest].I = (s8)CPUReadByte(address)
+#define OP_LDRSH reg[dest].I = (uint32_t)CPUReadHalfWordSigned(address)
+#define OP_LDRSB reg[dest].I = (int8_t)CPUReadByte(address)
#define WRITEBACK_NONE /*nothing*/
#define WRITEBACK_PRE reg[base].I = address
@@ -1551,7 +1551,7 @@
int dest = (opcode >> 12) & 15; \
int base = (opcode >> 16) & 15; \
CALC_OFFSET; \
- u32 address = CALC_ADDRESS;
+ uint32_t address = CALC_ADDRESS;
#define STR(CALC_OFFSET, CALC_ADDRESS, STORE_DATA, WRITEBACK1, WRITEBACK2, SIZE) \
LDRSTR_INIT(CALC_OFFSET, CALC_ADDRESS); \
@@ -1604,347 +1604,347 @@
LDR(CALC_OFFSET, ADDRESS_PREINC, LOAD_DATA, WRITEBACK_PRE, SIZE)
// STRH Rd, [Rn], -Rm
-static INSN_REGPARM void arm00B(u32 opcode) { STR_POSTDEC(OFFSET_REG, OP_STRH, 16); }
+static INSN_REGPARM void arm00B(uint32_t opcode) { STR_POSTDEC(OFFSET_REG, OP_STRH, 16); }
// STRH Rd, [Rn], #-offset
-static INSN_REGPARM void arm04B(u32 opcode) { STR_POSTDEC(OFFSET_IMM8, OP_STRH, 16); }
+static INSN_REGPARM void arm04B(uint32_t opcode) { STR_POSTDEC(OFFSET_IMM8, OP_STRH, 16); }
// STRH Rd, [Rn], Rm
-static INSN_REGPARM void arm08B(u32 opcode) { STR_POSTINC(OFFSET_REG, OP_STRH, 16); }
+static INSN_REGPARM void arm08B(uint32_t opcode) { STR_POSTINC(OFFSET_REG, OP_STRH, 16); }
// STRH Rd, [Rn], #offset
-static INSN_REGPARM void arm0CB(u32 opcode) { STR_POSTINC(OFFSET_IMM8, OP_STRH, 16); }
+static INSN_REGPARM void arm0CB(uint32_t opcode) { STR_POSTINC(OFFSET_IMM8, OP_STRH, 16); }
// STRH Rd, [Rn, -Rm]
-static INSN_REGPARM void arm10B(u32 opcode) { STR_PREDEC(OFFSET_REG, OP_STRH, 16); }
+static INSN_REGPARM void arm10B(uint32_t opcode) { STR_PREDEC(OFFSET_REG, OP_STRH, 16); }
// STRH Rd, [Rn, -Rm]!
-static INSN_REGPARM void arm12B(u32 opcode) { STR_PREDEC_WB(OFFSET_REG, OP_STRH, 16); }
+static INSN_REGPARM void arm12B(uint32_t opcode) { STR_PREDEC_WB(OFFSET_REG, OP_STRH, 16); }
// STRH Rd, [Rn, -#offset]
-static INSN_REGPARM void arm14B(u32 opcode) { STR_PREDEC(OFFSET_IMM8, OP_STRH, 16); }
+static INSN_REGPARM void arm14B(uint32_t opcode) { STR_PREDEC(OFFSET_IMM8, OP_STRH, 16); }
// STRH Rd, [Rn, -#offset]!
-static INSN_REGPARM void arm16B(u32 opcode) { STR_PREDEC_WB(OFFSET_IMM8, OP_STRH, 16); }
+static INSN_REGPARM void arm16B(uint32_t opcode) { STR_PREDEC_WB(OFFSET_IMM8, OP_STRH, 16); }
// STRH Rd, [Rn, Rm]
-static INSN_REGPARM void arm18B(u32 opcode) { STR_PREINC(OFFSET_REG, OP_STRH, 16); }
+static INSN_REGPARM void arm18B(uint32_t opcode) { STR_PREINC(OFFSET_REG, OP_STRH, 16); }
// STRH Rd, [Rn, Rm]!
-static INSN_REGPARM void arm1AB(u32 opcode) { STR_PREINC_WB(OFFSET_REG, OP_STRH, 16); }
+static INSN_REGPARM void arm1AB(uint32_t opcode) { STR_PREINC_WB(OFFSET_REG, OP_STRH, 16); }
// STRH Rd, [Rn, #offset]
-static INSN_REGPARM void arm1CB(u32 opcode) { STR_PREINC(OFFSET_IMM8, OP_STRH, 16); }
+static INSN_REGPARM void arm1CB(uint32_t opcode) { STR_PREINC(OFFSET_IMM8, OP_STRH, 16); }
// STRH Rd, [Rn, #offset]!
-static INSN_REGPARM void arm1EB(u32 opcode) { STR_PREINC_WB(OFFSET_IMM8, OP_STRH, 16); }
+static INSN_REGPARM void arm1EB(uint32_t opcode) { STR_PREINC_WB(OFFSET_IMM8, OP_STRH, 16); }
// LDRH Rd, [Rn], -Rm
-static INSN_REGPARM void arm01B(u32 opcode) { LDR_POSTDEC(OFFSET_REG, OP_LDRH, 16); }
+static INSN_REGPARM void arm01B(uint32_t opcode) { LDR_POSTDEC(OFFSET_REG, OP_LDRH, 16); }
// LDRH Rd, [Rn], #-offset
-static INSN_REGPARM void arm05B(u32 opcode) { LDR_POSTDEC(OFFSET_IMM8, OP_LDRH, 16); }
+static INSN_REGPARM void arm05B(uint32_t opcode) { LDR_POSTDEC(OFFSET_IMM8, OP_LDRH, 16); }
// LDRH Rd, [Rn], Rm
-static INSN_REGPARM void arm09B(u32 opcode) { LDR_POSTINC(OFFSET_REG, OP_LDRH, 16); }
+static INSN_REGPARM void arm09B(uint32_t opcode) { LDR_POSTINC(OFFSET_REG, OP_LDRH, 16); }
// LDRH Rd, [Rn], #offset
-static INSN_REGPARM void arm0DB(u32 opcode) { LDR_POSTINC(OFFSET_IMM8, OP_LDRH, 16); }
+static INSN_REGPARM void arm0DB(uint32_t opcode) { LDR_POSTINC(OFFSET_IMM8, OP_LDRH, 16); }
// LDRH Rd, [Rn, -Rm]
-static INSN_REGPARM void arm11B(u32 opcode) { LDR_PREDEC(OFFSET_REG, OP_LDRH, 16); }
+static INSN_REGPARM void arm11B(uint32_t opcode) { LDR_PREDEC(OFFSET_REG, OP_LDRH, 16); }
// LDRH Rd, [Rn, -Rm]!
-static INSN_REGPARM void arm13B(u32 opcode) { LDR_PREDEC_WB(OFFSET_REG, OP_LDRH, 16); }
+static INSN_REGPARM void arm13B(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_REG, OP_LDRH, 16); }
// LDRH Rd, [Rn, -#offset]
-static INSN_REGPARM void arm15B(u32 opcode) { LDR_PREDEC(OFFSET_IMM8, OP_LDRH, 16); }
+static INSN_REGPARM void arm15B(uint32_t opcode) { LDR_PREDEC(OFFSET_IMM8, OP_LDRH, 16); }
// LDRH Rd, [Rn, -#offset]!
-static INSN_REGPARM void arm17B(u32 opcode) { LDR_PREDEC_WB(OFFSET_IMM8, OP_LDRH, 16); }
+static INSN_REGPARM void arm17B(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_IMM8, OP_LDRH, 16); }
// LDRH Rd, [Rn, Rm]
-static INSN_REGPARM void arm19B(u32 opcode) { LDR_PREINC(OFFSET_REG, OP_LDRH, 16); }
+static INSN_REGPARM void arm19B(uint32_t opcode) { LDR_PREINC(OFFSET_REG, OP_LDRH, 16); }
// LDRH Rd, [Rn, Rm]!
-static INSN_REGPARM void arm1BB(u32 opcode) { LDR_PREINC_WB(OFFSET_REG, OP_LDRH, 16); }
+static INSN_REGPARM void arm1BB(uint32_t opcode) { LDR_PREINC_WB(OFFSET_REG, OP_LDRH, 16); }
// LDRH Rd, [Rn, #offset]
-static INSN_REGPARM void arm1DB(u32 opcode) { LDR_PREINC(OFFSET_IMM8, OP_LDRH, 16); }
+static INSN_REGPARM void arm1DB(uint32_t opcode) { LDR_PREINC(OFFSET_IMM8, OP_LDRH, 16); }
// LDRH Rd, [Rn, #offset]!
-static INSN_REGPARM void arm1FB(u32 opcode) { LDR_PREINC_WB(OFFSET_IMM8, OP_LDRH, 16); }
+static INSN_REGPARM void arm1FB(uint32_t opcode) { LDR_PREINC_WB(OFFSET_IMM8, OP_LDRH, 16); }
// LDRSB Rd, [Rn], -Rm
-static INSN_REGPARM void arm01D(u32 opcode) { LDR_POSTDEC(OFFSET_REG, OP_LDRSB, 16); }
+static INSN_REGPARM void arm01D(uint32_t opcode) { LDR_POSTDEC(OFFSET_REG, OP_LDRSB, 16); }
// LDRSB Rd, [Rn], #-offset
-static INSN_REGPARM void arm05D(u32 opcode) { LDR_POSTDEC(OFFSET_IMM8, OP_LDRSB, 16); }
+static INSN_REGPARM void arm05D(uint32_t opcode) { LDR_POSTDEC(OFFSET_IMM8, OP_LDRSB, 16); }
// LDRSB Rd, [Rn], Rm
-static INSN_REGPARM void arm09D(u32 opcode) { LDR_POSTINC(OFFSET_REG, OP_LDRSB, 16); }
+static INSN_REGPARM void arm09D(uint32_t opcode) { LDR_POSTINC(OFFSET_REG, OP_LDRSB, 16); }
// LDRSB Rd, [Rn], #offset
-static INSN_REGPARM void arm0DD(u32 opcode) { LDR_POSTINC(OFFSET_IMM8, OP_LDRSB, 16); }
+static INSN_REGPARM void arm0DD(uint32_t opcode) { LDR_POSTINC(OFFSET_IMM8, OP_LDRSB, 16); }
// LDRSB Rd, [Rn, -Rm]
-static INSN_REGPARM void arm11D(u32 opcode) { LDR_PREDEC(OFFSET_REG, OP_LDRSB, 16); }
+static INSN_REGPARM void arm11D(uint32_t opcode) { LDR_PREDEC(OFFSET_REG, OP_LDRSB, 16); }
// LDRSB Rd, [Rn, -Rm]!
-static INSN_REGPARM void arm13D(u32 opcode) { LDR_PREDEC_WB(OFFSET_REG, OP_LDRSB, 16); }
+static INSN_REGPARM void arm13D(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_REG, OP_LDRSB, 16); }
// LDRSB Rd, [Rn, -#offset]
-static INSN_REGPARM void arm15D(u32 opcode) { LDR_PREDEC(OFFSET_IMM8, OP_LDRSB, 16); }
+static INSN_REGPARM void arm15D(uint32_t opcode) { LDR_PREDEC(OFFSET_IMM8, OP_LDRSB, 16); }
// LDRSB Rd, [Rn, -#offset]!
-static INSN_REGPARM void arm17D(u32 opcode) { LDR_PREDEC_WB(OFFSET_IMM8, OP_LDRSB, 16); }
+static INSN_REGPARM void arm17D(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_IMM8, OP_LDRSB, 16); }
// LDRSB Rd, [Rn, Rm]
-static INSN_REGPARM void arm19D(u32 opcode) { LDR_PREINC(OFFSET_REG, OP_LDRSB, 16); }
+static INSN_REGPARM void arm19D(uint32_t opcode) { LDR_PREINC(OFFSET_REG, OP_LDRSB, 16); }
// LDRSB Rd, [Rn, Rm]!
-static INSN_REGPARM void arm1BD(u32 opcode) { LDR_PREINC_WB(OFFSET_REG, OP_LDRSB, 16); }
+static INSN_REGPARM void arm1BD(uint32_t opcode) { LDR_PREINC_WB(OFFSET_REG, OP_LDRSB, 16); }
// LDRSB Rd, [Rn, #offset]
-static INSN_REGPARM void arm1DD(u32 opcode) { LDR_PREINC(OFFSET_IMM8, OP_LDRSB, 16); }
+static INSN_REGPARM void arm1DD(uint32_t opcode) { LDR_PREINC(OFFSET_IMM8, OP_LDRSB, 16); }
// LDRSB Rd, [Rn, #offset]!
-static INSN_REGPARM void arm1FD(u32 opcode) { LDR_PREINC_WB(OFFSET_IMM8, OP_LDRSB, 16); }
+static INSN_REGPARM void arm1FD(uint32_t opcode) { LDR_PREINC_WB(OFFSET_IMM8, OP_LDRSB, 16); }
// LDRSH Rd, [Rn], -Rm
-static INSN_REGPARM void arm01F(u32 opcode) { LDR_POSTDEC(OFFSET_REG, OP_LDRSH, 16); }
+static INSN_REGPARM void arm01F(uint32_t opcode) { LDR_POSTDEC(OFFSET_REG, OP_LDRSH, 16); }
// LDRSH Rd, [Rn], #-offset
-static INSN_REGPARM void arm05F(u32 opcode) { LDR_POSTDEC(OFFSET_IMM8, OP_LDRSH, 16); }
+static INSN_REGPARM void arm05F(uint32_t opcode) { LDR_POSTDEC(OFFSET_IMM8, OP_LDRSH, 16); }
// LDRSH Rd, [Rn], Rm
-static INSN_REGPARM void arm09F(u32 opcode) { LDR_POSTINC(OFFSET_REG, OP_LDRSH, 16); }
+static INSN_REGPARM void arm09F(uint32_t opcode) { LDR_POSTINC(OFFSET_REG, OP_LDRSH, 16); }
// LDRSH Rd, [Rn], #offset
-static INSN_REGPARM void arm0DF(u32 opcode) { LDR_POSTINC(OFFSET_IMM8, OP_LDRSH, 16); }
+static INSN_REGPARM void arm0DF(uint32_t opcode) { LDR_POSTINC(OFFSET_IMM8, OP_LDRSH, 16); }
// LDRSH Rd, [Rn, -Rm]
-static INSN_REGPARM void arm11F(u32 opcode) { LDR_PREDEC(OFFSET_REG, OP_LDRSH, 16); }
+static INSN_REGPARM void arm11F(uint32_t opcode) { LDR_PREDEC(OFFSET_REG, OP_LDRSH, 16); }
// LDRSH Rd, [Rn, -Rm]!
-static INSN_REGPARM void arm13F(u32 opcode) { LDR_PREDEC_WB(OFFSET_REG, OP_LDRSH, 16); }
+static INSN_REGPARM void arm13F(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_REG, OP_LDRSH, 16); }
// LDRSH Rd, [Rn, -#offset]
-static INSN_REGPARM void arm15F(u32 opcode) { LDR_PREDEC(OFFSET_IMM8, OP_LDRSH, 16); }
+static INSN_REGPARM void arm15F(uint32_t opcode) { LDR_PREDEC(OFFSET_IMM8, OP_LDRSH, 16); }
// LDRSH Rd, [Rn, -#offset]!
-static INSN_REGPARM void arm17F(u32 opcode) { LDR_PREDEC_WB(OFFSET_IMM8, OP_LDRSH, 16); }
+static INSN_REGPARM void arm17F(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_IMM8, OP_LDRSH, 16); }
// LDRSH Rd, [Rn, Rm]
-static INSN_REGPARM void arm19F(u32 opcode) { LDR_PREINC(OFFSET_REG, OP_LDRSH, 16); }
+static INSN_REGPARM void arm19F(uint32_t opcode) { LDR_PREINC(OFFSET_REG, OP_LDRSH, 16); }
// LDRSH Rd, [Rn, Rm]!
-static INSN_REGPARM void arm1BF(u32 opcode) { LDR_PREINC_WB(OFFSET_REG, OP_LDRSH, 16); }
+static INSN_REGPARM void arm1BF(uint32_t opcode) { LDR_PREINC_WB(OFFSET_REG, OP_LDRSH, 16); }
// LDRSH Rd, [Rn, #offset]
-static INSN_REGPARM void arm1DF(u32 opcode) { LDR_PREINC(OFFSET_IMM8, OP_LDRSH, 16); }
+static INSN_REGPARM void arm1DF(uint32_t opcode) { LDR_PREINC(OFFSET_IMM8, OP_LDRSH, 16); }
// LDRSH Rd, [Rn, #offset]!
-static INSN_REGPARM void arm1FF(u32 opcode) { LDR_PREINC_WB(OFFSET_IMM8, OP_LDRSH, 16); }
+static INSN_REGPARM void arm1FF(uint32_t opcode) { LDR_PREINC_WB(OFFSET_IMM8, OP_LDRSH, 16); }
// STR[T] Rd, [Rn], -#
// Note: STR and STRT do the same thing on the GBA (likewise for LDR/LDRT etc)
-static INSN_REGPARM void arm400(u32 opcode) { STR_POSTDEC(OFFSET_IMM, OP_STR, 32); }
+static INSN_REGPARM void arm400(uint32_t opcode) { STR_POSTDEC(OFFSET_IMM, OP_STR, 32); }
// LDR[T] Rd, [Rn], -#
-static INSN_REGPARM void arm410(u32 opcode) { LDR_POSTDEC(OFFSET_IMM, OP_LDR, 32); }
+static INSN_REGPARM void arm410(uint32_t opcode) { LDR_POSTDEC(OFFSET_IMM, OP_LDR, 32); }
// STRB[T] Rd, [Rn], -#
-static INSN_REGPARM void arm440(u32 opcode) { STR_POSTDEC(OFFSET_IMM, OP_STRB, 16); }
+static INSN_REGPARM void arm440(uint32_t opcode) { STR_POSTDEC(OFFSET_IMM, OP_STRB, 16); }
// LDRB[T] Rd, [Rn], -#
-static INSN_REGPARM void arm450(u32 opcode) { LDR_POSTDEC(OFFSET_IMM, OP_LDRB, 16); }
+static INSN_REGPARM void arm450(uint32_t opcode) { LDR_POSTDEC(OFFSET_IMM, OP_LDRB, 16); }
// STR[T] Rd, [Rn], #
-static INSN_REGPARM void arm480(u32 opcode) { STR_POSTINC(OFFSET_IMM, OP_STR, 32); }
+static INSN_REGPARM void arm480(uint32_t opcode) { STR_POSTINC(OFFSET_IMM, OP_STR, 32); }
// LDR Rd, [Rn], #
-static INSN_REGPARM void arm490(u32 opcode) { LDR_POSTINC(OFFSET_IMM, OP_LDR, 32); }
+static INSN_REGPARM void arm490(uint32_t opcode) { LDR_POSTINC(OFFSET_IMM, OP_LDR, 32); }
// STRB[T] Rd, [Rn], #
-static INSN_REGPARM void arm4C0(u32 opcode) { STR_POSTINC(OFFSET_IMM, OP_STRB, 16); }
+static INSN_REGPARM void arm4C0(uint32_t opcode) { STR_POSTINC(OFFSET_IMM, OP_STRB, 16); }
// LDRB[T] Rd, [Rn], #
-static INSN_REGPARM void arm4D0(u32 opcode) { LDR_POSTINC(OFFSET_IMM, OP_LDRB, 16); }
+static INSN_REGPARM void arm4D0(uint32_t opcode) { LDR_POSTINC(OFFSET_IMM, OP_LDRB, 16); }
// STR Rd, [Rn, -#]
-static INSN_REGPARM void arm500(u32 opcode) { STR_PREDEC(OFFSET_IMM, OP_STR, 32); }
+static INSN_REGPARM void arm500(uint32_t opcode) { STR_PREDEC(OFFSET_IMM, OP_STR, 32); }
// LDR Rd, [Rn, -#]
-static INSN_REGPARM void arm510(u32 opcode) { LDR_PREDEC(OFFSET_IMM, OP_LDR, 32); }
+static INSN_REGPARM void arm510(uint32_t opcode) { LDR_PREDEC(OFFSET_IMM, OP_LDR, 32); }
// STR Rd, [Rn, -#]!
-static INSN_REGPARM void arm520(u32 opcode) { STR_PREDEC_WB(OFFSET_IMM, OP_STR, 32); }
+static INSN_REGPARM void arm520(uint32_t opcode) { STR_PREDEC_WB(OFFSET_IMM, OP_STR, 32); }
// LDR Rd, [Rn, -#]!
-static INSN_REGPARM void arm530(u32 opcode) { LDR_PREDEC_WB(OFFSET_IMM, OP_LDR, 32); }
+static INSN_REGPARM void arm530(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_IMM, OP_LDR, 32); }
// STRB Rd, [Rn, -#]
-static INSN_REGPARM void arm540(u32 opcode) { STR_PREDEC(OFFSET_IMM, OP_STRB, 16); }
+static INSN_REGPARM void arm540(uint32_t opcode) { STR_PREDEC(OFFSET_IMM, OP_STRB, 16); }
// LDRB Rd, [Rn, -#]
-static INSN_REGPARM void arm550(u32 opcode) { LDR_PREDEC(OFFSET_IMM, OP_LDRB, 16); }
+static INSN_REGPARM void arm550(uint32_t opcode) { LDR_PREDEC(OFFSET_IMM, OP_LDRB, 16); }
// STRB Rd, [Rn, -#]!
-static INSN_REGPARM void arm560(u32 opcode) { STR_PREDEC_WB(OFFSET_IMM, OP_STRB, 16); }
+static INSN_REGPARM void arm560(uint32_t opcode) { STR_PREDEC_WB(OFFSET_IMM, OP_STRB, 16); }
// LDRB Rd, [Rn, -#]!
-static INSN_REGPARM void arm570(u32 opcode) { LDR_PREDEC_WB(OFFSET_IMM, OP_LDRB, 16); }
+static INSN_REGPARM void arm570(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_IMM, OP_LDRB, 16); }
// STR Rd, [Rn, #]
-static INSN_REGPARM void arm580(u32 opcode) { STR_PREINC(OFFSET_IMM, OP_STR, 32); }
+static INSN_REGPARM void arm580(uint32_t opcode) { STR_PREINC(OFFSET_IMM, OP_STR, 32); }
// LDR Rd, [Rn, #]
-static INSN_REGPARM void arm590(u32 opcode) { LDR_PREINC(OFFSET_IMM, OP_LDR, 32); }
+static INSN_REGPARM void arm590(uint32_t opcode) { LDR_PREINC(OFFSET_IMM, OP_LDR, 32); }
// STR Rd, [Rn, #]!
-static INSN_REGPARM void arm5A0(u32 opcode) { STR_PREINC_WB(OFFSET_IMM, OP_STR, 32); }
+static INSN_REGPARM void arm5A0(uint32_t opcode) { STR_PREINC_WB(OFFSET_IMM, OP_STR, 32); }
// LDR Rd, [Rn, #]!
-static INSN_REGPARM void arm5B0(u32 opcode) { LDR_PREINC_WB(OFFSET_IMM, OP_LDR, 32); }
+static INSN_REGPARM void arm5B0(uint32_t opcode) { LDR_PREINC_WB(OFFSET_IMM, OP_LDR, 32); }
// STRB Rd, [Rn, #]
-static INSN_REGPARM void arm5C0(u32 opcode) { STR_PREINC(OFFSET_IMM, OP_STRB, 16); }
+static INSN_REGPARM void arm5C0(uint32_t opcode) { STR_PREINC(OFFSET_IMM, OP_STRB, 16); }
// LDRB Rd, [Rn, #]
-static INSN_REGPARM void arm5D0(u32 opcode) { LDR_PREINC(OFFSET_IMM, OP_LDRB, 16); }
+static INSN_REGPARM void arm5D0(uint32_t opcode) { LDR_PREINC(OFFSET_IMM, OP_LDRB, 16); }
// STRB Rd, [Rn, #]!
-static INSN_REGPARM void arm5E0(u32 opcode) { STR_PREINC_WB(OFFSET_IMM, OP_STRB, 16); }
+static INSN_REGPARM void arm5E0(uint32_t opcode) { STR_PREINC_WB(OFFSET_IMM, OP_STRB, 16); }
// LDRB Rd, [Rn, #]!
-static INSN_REGPARM void arm5F0(u32 opcode) { LDR_PREINC_WB(OFFSET_IMM, OP_LDRB, 16); }
+static INSN_REGPARM void arm5F0(uint32_t opcode) { LDR_PREINC_WB(OFFSET_IMM, OP_LDRB, 16); }
// STR[T] Rd, [Rn], -Rm, LSL #
-static INSN_REGPARM void arm600(u32 opcode) { STR_POSTDEC(OFFSET_LSL, OP_STR, 32); }
+static INSN_REGPARM void arm600(uint32_t opcode) { STR_POSTDEC(OFFSET_LSL, OP_STR, 32); }
// STR[T] Rd, [Rn], -Rm, LSR #
-static INSN_REGPARM void arm602(u32 opcode) { STR_POSTDEC(OFFSET_LSR, OP_STR, 32); }
+static INSN_REGPARM void arm602(uint32_t opcode) { STR_POSTDEC(OFFSET_LSR, OP_STR, 32); }
// STR[T] Rd, [Rn], -Rm, ASR #
-static INSN_REGPARM void arm604(u32 opcode) { STR_POSTDEC(OFFSET_ASR, OP_STR, 32); }
+static INSN_REGPARM void arm604(uint32_t opcode) { STR_POSTDEC(OFFSET_ASR, OP_STR, 32); }
// STR[T] Rd, [Rn], -Rm, ROR #
-static INSN_REGPARM void arm606(u32 opcode) { STR_POSTDEC(OFFSET_ROR, OP_STR, 32); }
+static INSN_REGPARM void arm606(uint32_t opcode) { STR_POSTDEC(OFFSET_ROR, OP_STR, 32); }
// LDR[T] Rd, [Rn], -Rm, LSL #
-static INSN_REGPARM void arm610(u32 opcode) { LDR_POSTDEC(OFFSET_LSL, OP_LDR, 32); }
+static INSN_REGPARM void arm610(uint32_t opcode) { LDR_POSTDEC(OFFSET_LSL, OP_LDR, 32); }
// LDR[T] Rd, [Rn], -Rm, LSR #
-static INSN_REGPARM void arm612(u32 opcode) { LDR_POSTDEC(OFFSET_LSR, OP_LDR, 32); }
+static INSN_REGPARM void arm612(uint32_t opcode) { LDR_POSTDEC(OFFSET_LSR, OP_LDR, 32); }
// LDR[T] Rd, [Rn], -Rm, ASR #
-static INSN_REGPARM void arm614(u32 opcode) { LDR_POSTDEC(OFFSET_ASR, OP_LDR, 32); }
+static INSN_REGPARM void arm614(uint32_t opcode) { LDR_POSTDEC(OFFSET_ASR, OP_LDR, 32); }
// LDR[T] Rd, [Rn], -Rm, ROR #
-static INSN_REGPARM void arm616(u32 opcode) { LDR_POSTDEC(OFFSET_ROR, OP_LDR, 32); }
+static INSN_REGPARM void arm616(uint32_t opcode) { LDR_POSTDEC(OFFSET_ROR, OP_LDR, 32); }
// STRB[T] Rd, [Rn], -Rm, LSL #
-static INSN_REGPARM void arm640(u32 opcode) { STR_POSTDEC(OFFSET_LSL, OP_STRB, 16); }
+static INSN_REGPARM void arm640(uint32_t opcode) { STR_POSTDEC(OFFSET_LSL, OP_STRB, 16); }
// STRB[T] Rd, [Rn], -Rm, LSR #
-static INSN_REGPARM void arm642(u32 opcode) { STR_POSTDEC(OFFSET_LSR, OP_STRB, 16); }
+static INSN_REGPARM void arm642(uint32_t opcode) { STR_POSTDEC(OFFSET_LSR, OP_STRB, 16); }
// STRB[T] Rd, [Rn], -Rm, ASR #
-static INSN_REGPARM void arm644(u32 opcode) { STR_POSTDEC(OFFSET_ASR, OP_STRB, 16); }
+static INSN_REGPARM void arm644(uint32_t opcode) { STR_POSTDEC(OFFSET_ASR, OP_STRB, 16); }
// STRB[T] Rd, [Rn], -Rm, ROR #
-static INSN_REGPARM void arm646(u32 opcode) { STR_POSTDEC(OFFSET_ROR, OP_STRB, 16); }
+static INSN_REGPARM void arm646(uint32_t opcode) { STR_POSTDEC(OFFSET_ROR, OP_STRB, 16); }
// LDRB[T] Rd, [Rn], -Rm, LSL #
-static INSN_REGPARM void arm650(u32 opcode) { LDR_POSTDEC(OFFSET_LSL, OP_LDRB, 16); }
+static INSN_REGPARM void arm650(uint32_t opcode) { LDR_POSTDEC(OFFSET_LSL, OP_LDRB, 16); }
// LDRB[T] Rd, [Rn], -Rm, LSR #
-static INSN_REGPARM void arm652(u32 opcode) { LDR_POSTDEC(OFFSET_LSR, OP_LDRB, 16); }
+static INSN_REGPARM void arm652(uint32_t opcode) { LDR_POSTDEC(OFFSET_LSR, OP_LDRB, 16); }
// LDRB[T] Rd, [Rn], -Rm, ASR #
-static INSN_REGPARM void arm654(u32 opcode) { LDR_POSTDEC(OFFSET_ASR, OP_LDRB, 16); }
+static INSN_REGPARM void arm654(uint32_t opcode) { LDR_POSTDEC(OFFSET_ASR, OP_LDRB, 16); }
// LDRB Rd, [Rn], -Rm, ROR #
-static INSN_REGPARM void arm656(u32 opcode) { LDR_POSTDEC(OFFSET_ROR, OP_LDRB, 16); }
+static INSN_REGPARM void arm656(uint32_t opcode) { LDR_POSTDEC(OFFSET_ROR, OP_LDRB, 16); }
// STR[T] Rd, [Rn], Rm, LSL #
-static INSN_REGPARM void arm680(u32 opcode) { STR_POSTINC(OFFSET_LSL, OP_STR, 32); }
+static INSN_REGPARM void arm680(uint32_t opcode) { STR_POSTINC(OFFSET_LSL, OP_STR, 32); }
// STR[T] Rd, [Rn], Rm, LSR #
-static INSN_REGPARM void arm682(u32 opcode) { STR_POSTINC(OFFSET_LSR, OP_STR, 32); }
+static INSN_REGPARM void arm682(uint32_t opcode) { STR_POSTINC(OFFSET_LSR, OP_STR, 32); }
// STR[T] Rd, [Rn], Rm, ASR #
-static INSN_REGPARM void arm684(u32 opcode) { STR_POSTINC(OFFSET_ASR, OP_STR, 32); }
+static INSN_REGPARM void arm684(uint32_t opcode) { STR_POSTINC(OFFSET_ASR, OP_STR, 32); }
// STR[T] Rd, [Rn], Rm, ROR #
-static INSN_REGPARM void arm686(u32 opcode) { STR_POSTINC(OFFSET_ROR, OP_STR, 32); }
+static INSN_REGPARM void arm686(uint32_t opcode) { STR_POSTINC(OFFSET_ROR, OP_STR, 32); }
// LDR[T] Rd, [Rn], Rm, LSL #
-static INSN_REGPARM void arm690(u32 opcode) { LDR_POSTINC(OFFSET_LSL, OP_LDR, 32); }
+static INSN_REGPARM void arm690(uint32_t opcode) { LDR_POSTINC(OFFSET_LSL, OP_LDR, 32); }
// LDR[T] Rd, [Rn], Rm, LSR #
-static INSN_REGPARM void arm692(u32 opcode) { LDR_POSTINC(OFFSET_LSR, OP_LDR, 32); }
+static INSN_REGPARM void arm692(uint32_t opcode) { LDR_POSTINC(OFFSET_LSR, OP_LDR, 32); }
// LDR[T] Rd, [Rn], Rm, ASR #
-static INSN_REGPARM void arm694(u32 opcode) { LDR_POSTINC(OFFSET_ASR, OP_LDR, 32); }
+static INSN_REGPARM void arm694(uint32_t opcode) { LDR_POSTINC(OFFSET_ASR, OP_LDR, 32); }
// LDR[T] Rd, [Rn], Rm, ROR #
-static INSN_REGPARM void arm696(u32 opcode) { LDR_POSTINC(OFFSET_ROR, OP_LDR, 32); }
+static INSN_REGPARM void arm696(uint32_t opcode) { LDR_POSTINC(OFFSET_ROR, OP_LDR, 32); }
// STRB[T] Rd, [Rn], Rm, LSL #
-static INSN_REGPARM void arm6C0(u32 opcode) { STR_POSTINC(OFFSET_LSL, OP_STRB, 16); }
+static INSN_REGPARM void arm6C0(uint32_t opcode) { STR_POSTINC(OFFSET_LSL, OP_STRB, 16); }
// STRB[T] Rd, [Rn], Rm, LSR #
-static INSN_REGPARM void arm6C2(u32 opcode) { STR_POSTINC(OFFSET_LSR, OP_STRB, 16); }
+static INSN_REGPARM void arm6C2(uint32_t opcode) { STR_POSTINC(OFFSET_LSR, OP_STRB, 16); }
// STRB[T] Rd, [Rn], Rm, ASR #
-static INSN_REGPARM void arm6C4(u32 opcode) { STR_POSTINC(OFFSET_ASR, OP_STRB, 16); }
+static INSN_REGPARM void arm6C4(uint32_t opcode) { STR_POSTINC(OFFSET_ASR, OP_STRB, 16); }
// STRB[T] Rd, [Rn], Rm, ROR #
-static INSN_REGPARM void arm6C6(u32 opcode) { STR_POSTINC(OFFSET_ROR, OP_STRB, 16); }
+static INSN_REGPARM void arm6C6(uint32_t opcode) { STR_POSTINC(OFFSET_ROR, OP_STRB, 16); }
// LDRB[T] Rd, [Rn], Rm, LSL #
-static INSN_REGPARM void arm6D0(u32 opcode) { LDR_POSTINC(OFFSET_LSL, OP_LDRB, 16); }
+static INSN_REGPARM void arm6D0(uint32_t opcode) { LDR_POSTINC(OFFSET_LSL, OP_LDRB, 16); }
// LDRB[T] Rd, [Rn], Rm, LSR #
-static INSN_REGPARM void arm6D2(u32 opcode) { LDR_POSTINC(OFFSET_LSR, OP_LDRB, 16); }
+static INSN_REGPARM void arm6D2(uint32_t opcode) { LDR_POSTINC(OFFSET_LSR, OP_LDRB, 16); }
// LDRB[T] Rd, [Rn], Rm, ASR #
-static INSN_REGPARM void arm6D4(u32 opcode) { LDR_POSTINC(OFFSET_ASR, OP_LDRB, 16); }
+static INSN_REGPARM void arm6D4(uint32_t opcode) { LDR_POSTINC(OFFSET_ASR, OP_LDRB, 16); }
// LDRB[T] Rd, [Rn], Rm, ROR #
-static INSN_REGPARM void arm6D6(u32 opcode) { LDR_POSTINC(OFFSET_ROR, OP_LDRB, 16); }
+static INSN_REGPARM void arm6D6(uint32_t opcode) { LDR_POSTINC(OFFSET_ROR, OP_LDRB, 16); }
// STR Rd, [Rn, -Rm, LSL #]
-static INSN_REGPARM void arm700(u32 opcode) { STR_PREDEC(OFFSET_LSL, OP_STR, 32); }
+static INSN_REGPARM void arm700(uint32_t opcode) { STR_PREDEC(OFFSET_LSL, OP_STR, 32); }
// STR Rd, [Rn, -Rm, LSR #]
-static INSN_REGPARM void arm702(u32 opcode) { STR_PREDEC(OFFSET_LSR, OP_STR, 32); }
+static INSN_REGPARM void arm702(uint32_t opcode) { STR_PREDEC(OFFSET_LSR, OP_STR, 32); }
// STR Rd, [Rn, -Rm, ASR #]
-static INSN_REGPARM void arm704(u32 opcode) { STR_PREDEC(OFFSET_ASR, OP_STR, 32); }
+static INSN_REGPARM void arm704(uint32_t opcode) { STR_PREDEC(OFFSET_ASR, OP_STR, 32); }
// STR Rd, [Rn, -Rm, ROR #]
-static INSN_REGPARM void arm706(u32 opcode) { STR_PREDEC(OFFSET_ROR, OP_STR, 32); }
+static INSN_REGPARM void arm706(uint32_t opcode) { STR_PREDEC(OFFSET_ROR, OP_STR, 32); }
// LDR Rd, [Rn, -Rm, LSL #]
-static INSN_REGPARM void arm710(u32 opcode) { LDR_PREDEC(OFFSET_LSL, OP_LDR, 32); }
+static INSN_REGPARM void arm710(uint32_t opcode) { LDR_PREDEC(OFFSET_LSL, OP_LDR, 32); }
// LDR Rd, [Rn, -Rm, LSR #]
-static INSN_REGPARM void arm712(u32 opcode) { LDR_PREDEC(OFFSET_LSR, OP_LDR, 32); }
+static INSN_REGPARM void arm712(uint32_t opcode) { LDR_PREDEC(OFFSET_LSR, OP_LDR, 32); }
// LDR Rd, [Rn, -Rm, ASR #]
-static INSN_REGPARM void arm714(u32 opcode) { LDR_PREDEC(OFFSET_ASR, OP_LDR, 32); }
+static INSN_REGPARM void arm714(uint32_t opcode) { LDR_PREDEC(OFFSET_ASR, OP_LDR, 32); }
// LDR Rd, [Rn, -Rm, ROR #]
-static INSN_REGPARM void arm716(u32 opcode) { LDR_PREDEC(OFFSET_ROR, OP_LDR, 32); }
+static INSN_REGPARM void arm716(uint32_t opcode) { LDR_PREDEC(OFFSET_ROR, OP_LDR, 32); }
// STR Rd, [Rn, -Rm, LSL #]!
-static INSN_REGPARM void arm720(u32 opcode) { STR_PREDEC_WB(OFFSET_LSL, OP_STR, 32); }
+static INSN_REGPARM void arm720(uint32_t opcode) { STR_PREDEC_WB(OFFSET_LSL, OP_STR, 32); }
// STR Rd, [Rn, -Rm, LSR #]!
-static INSN_REGPARM void arm722(u32 opcode) { STR_PREDEC_WB(OFFSET_LSR, OP_STR, 32); }
+static INSN_REGPARM void arm722(uint32_t opcode) { STR_PREDEC_WB(OFFSET_LSR, OP_STR, 32); }
// STR Rd, [Rn, -Rm, ASR #]!
-static INSN_REGPARM void arm724(u32 opcode) { STR_PREDEC_WB(OFFSET_ASR, OP_STR, 32); }
+static INSN_REGPARM void arm724(uint32_t opcode) { STR_PREDEC_WB(OFFSET_ASR, OP_STR, 32); }
// STR Rd, [Rn, -Rm, ROR #]!
-static INSN_REGPARM void arm726(u32 opcode) { STR_PREDEC_WB(OFFSET_ROR, OP_STR, 32); }
+static INSN_REGPARM void arm726(uint32_t opcode) { STR_PREDEC_WB(OFFSET_ROR, OP_STR, 32); }
// LDR Rd, [Rn, -Rm, LSL #]!
-static INSN_REGPARM void arm730(u32 opcode) { LDR_PREDEC_WB(OFFSET_LSL, OP_LDR, 32); }
+static INSN_REGPARM void arm730(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_LSL, OP_LDR, 32); }
// LDR Rd, [Rn, -Rm, LSR #]!
-static INSN_REGPARM void arm732(u32 opcode) { LDR_PREDEC_WB(OFFSET_LSR, OP_LDR, 32); }
+static INSN_REGPARM void arm732(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_LSR, OP_LDR, 32); }
// LDR Rd, [Rn, -Rm, ASR #]!
-static INSN_REGPARM void arm734(u32 opcode) { LDR_PREDEC_WB(OFFSET_ASR, OP_LDR, 32); }
+static INSN_REGPARM void arm734(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_ASR, OP_LDR, 32); }
// LDR Rd, [Rn, -Rm, ROR #]!
-static INSN_REGPARM void arm736(u32 opcode) { LDR_PREDEC_WB(OFFSET_ROR, OP_LDR, 32); }
+static INSN_REGPARM void arm736(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_ROR, OP_LDR, 32); }
// STRB Rd, [Rn, -Rm, LSL #]
-static INSN_REGPARM void arm740(u32 opcode) { STR_PREDEC(OFFSET_LSL, OP_STRB, 16); }
+static INSN_REGPARM void arm740(uint32_t opcode) { STR_PREDEC(OFFSET_LSL, OP_STRB, 16); }
// STRB Rd, [Rn, -Rm, LSR #]
-static INSN_REGPARM void arm742(u32 opcode) { STR_PREDEC(OFFSET_LSR, OP_STRB, 16); }
+static INSN_REGPARM void arm742(uint32_t opcode) { STR_PREDEC(OFFSET_LSR, OP_STRB, 16); }
// STRB Rd, [Rn, -Rm, ASR #]
-static INSN_REGPARM void arm744(u32 opcode) { STR_PREDEC(OFFSET_ASR, OP_STRB, 16); }
+static INSN_REGPARM void arm744(uint32_t opcode) { STR_PREDEC(OFFSET_ASR, OP_STRB, 16); }
// STRB Rd, [Rn, -Rm, ROR #]
-static INSN_REGPARM void arm746(u32 opcode) { STR_PREDEC(OFFSET_ROR, OP_STRB, 16); }
+static INSN_REGPARM void arm746(uint32_t opcode) { STR_PREDEC(OFFSET_ROR, OP_STRB, 16); }
// LDRB Rd, [Rn, -Rm, LSL #]
-static INSN_REGPARM void arm750(u32 opcode) { LDR_PREDEC(OFFSET_LSL, OP_LDRB, 16); }
+static INSN_REGPARM void arm750(uint32_t opcode) { LDR_PREDEC(OFFSET_LSL, OP_LDRB, 16); }
// LDRB Rd, [Rn, -Rm, LSR #]
-static INSN_REGPARM void arm752(u32 opcode) { LDR_PREDEC(OFFSET_LSR, OP_LDRB, 16); }
+static INSN_REGPARM void arm752(uint32_t opcode) { LDR_PREDEC(OFFSET_LSR, OP_LDRB, 16); }
// LDRB Rd, [Rn, -Rm, ASR #]
-static INSN_REGPARM void arm754(u32 opcode) { LDR_PREDEC(OFFSET_ASR, OP_LDRB, 16); }
+static INSN_REGPARM void arm754(uint32_t opcode) { LDR_PREDEC(OFFSET_ASR, OP_LDRB, 16); }
// LDRB Rd, [Rn, -Rm, ROR #]
-static INSN_REGPARM void arm756(u32 opcode) { LDR_PREDEC(OFFSET_ROR, OP_LDRB, 16); }
+static INSN_REGPARM void arm756(uint32_t opcode) { LDR_PREDEC(OFFSET_ROR, OP_LDRB, 16); }
// STRB Rd, [Rn, -Rm, LSL #]!
-static INSN_REGPARM void arm760(u32 opcode) { STR_PREDEC_WB(OFFSET_LSL, OP_STRB, 16); }
+static INSN_REGPARM void arm760(uint32_t opcode) { STR_PREDEC_WB(OFFSET_LSL, OP_STRB, 16); }
// STRB Rd, [Rn, -Rm, LSR #]!
-static INSN_REGPARM void arm762(u32 opcode) { STR_PREDEC_WB(OFFSET_LSR, OP_STRB, 16); }
+static INSN_REGPARM void arm762(uint32_t opcode) { STR_PREDEC_WB(OFFSET_LSR, OP_STRB, 16); }
// STRB Rd, [Rn, -Rm, ASR #]!
-static INSN_REGPARM void arm764(u32 opcode) { STR_PREDEC_WB(OFFSET_ASR, OP_STRB, 16); }
+static INSN_REGPARM void arm764(uint32_t opcode) { STR_PREDEC_WB(OFFSET_ASR, OP_STRB, 16); }
// STRB Rd, [Rn, -Rm, ROR #]!
-static INSN_REGPARM void arm766(u32 opcode) { STR_PREDEC_WB(OFFSET_ROR, OP_STRB, 16); }
+static INSN_REGPARM void arm766(uint32_t opcode) { STR_PREDEC_WB(OFFSET_ROR, OP_STRB, 16); }
// LDRB Rd, [Rn, -Rm, LSL #]!
-static INSN_REGPARM void arm770(u32 opcode) { LDR_PREDEC_WB(OFFSET_LSL, OP_LDRB, 16); }
+static INSN_REGPARM void arm770(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_LSL, OP_LDRB, 16); }
// LDRB Rd, [Rn, -Rm, LSR #]!
-static INSN_REGPARM void arm772(u32 opcode) { LDR_PREDEC_WB(OFFSET_LSR, OP_LDRB, 16); }
+static INSN_REGPARM void arm772(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_LSR, OP_LDRB, 16); }
// LDRB Rd, [Rn, -Rm, ASR #]!
-static INSN_REGPARM void arm774(u32 opcode) { LDR_PREDEC_WB(OFFSET_ASR, OP_LDRB, 16); }
+static INSN_REGPARM void arm774(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_ASR, OP_LDRB, 16); }
// LDRB Rd, [Rn, -Rm, ROR #]!
-static INSN_REGPARM void arm776(u32 opcode) { LDR_PREDEC_WB(OFFSET_ROR, OP_LDRB, 16); }
+static INSN_REGPARM void arm776(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_ROR, OP_LDRB, 16); }
// STR Rd, [Rn, Rm, LSL #]
-static INSN_REGPARM void arm780(u32 opcode) { STR_PREINC(OFFSET_LSL, OP_STR, 32); }
+static INSN_REGPARM void arm780(uint32_t opcode) { STR_PREINC(OFFSET_LSL, OP_STR, 32); }
// STR Rd, [Rn, Rm, LSR #]
-static INSN_REGPARM void arm782(u32 opcode) { STR_PREINC(OFFSET_LSR, OP_STR, 32); }
+static INSN_REGPARM void arm782(uint32_t opcode) { STR_PREINC(OFFSET_LSR, OP_STR, 32); }
// STR Rd, [Rn, Rm, ASR #]
-static INSN_REGPARM void arm784(u32 opcode) { STR_PREINC(OFFSET_ASR, OP_STR, 32); }
+static INSN_REGPARM void arm784(uint32_t opcode) { STR_PREINC(OFFSET_ASR, OP_STR, 32); }
// STR Rd, [Rn, Rm, ROR #]
-static INSN_REGPARM void arm786(u32 opcode) { STR_PREINC(OFFSET_ROR, OP_STR, 32); }
+static INSN_REGPARM void arm786(uint32_t opcode) { STR_PREINC(OFFSET_ROR, OP_STR, 32); }
// LDR Rd, [Rn, Rm, LSL #]
-static INSN_REGPARM void arm790(u32 opcode) { LDR_PREINC(OFFSET_LSL, OP_LDR, 32); }
+static INSN_REGPARM void arm790(uint32_t opcode) { LDR_PREINC(OFFSET_LSL, OP_LDR, 32); }
// LDR Rd, [Rn, Rm, LSR #]
-static INSN_REGPARM void arm792(u32 opcode) { LDR_PREINC(OFFSET_LSR, OP_LDR, 32); }
+static INSN_REGPARM void arm792(uint32_t opcode) { LDR_PREINC(OFFSET_LSR, OP_LDR, 32); }
// LDR Rd, [Rn, Rm, ASR #]
-static INSN_REGPARM void arm794(u32 opcode) { LDR_PREINC(OFFSET_ASR, OP_LDR, 32); }
+static INSN_REGPARM void arm794(uint32_t opcode) { LDR_PREINC(OFFSET_ASR, OP_LDR, 32); }
// LDR Rd, [Rn, Rm, ROR #]
-static INSN_REGPARM void arm796(u32 opcode) { LDR_PREINC(OFFSET_ROR, OP_LDR, 32); }
+static INSN_REGPARM void arm796(uint32_t opcode) { LDR_PREINC(OFFSET_ROR, OP_LDR, 32); }
// STR Rd, [Rn, Rm, LSL #]!
-static INSN_REGPARM void arm7A0(u32 opcode) { STR_PREINC_WB(OFFSET_LSL, OP_STR, 32); }
+static INSN_REGPARM void arm7A0(uint32_t opcode) { STR_PREINC_WB(OFFSET_LSL, OP_STR, 32); }
// STR Rd, [Rn, Rm, LSR #]!
-static INSN_REGPARM void arm7A2(u32 opcode) { STR_PREINC_WB(OFFSET_LSR, OP_STR, 32); }
+static INSN_REGPARM void arm7A2(uint32_t opcode) { STR_PREINC_WB(OFFSET_LSR, OP_STR, 32); }
// STR Rd, [Rn, Rm, ASR #]!
-static INSN_REGPARM void arm7A4(u32 opcode) { STR_PREINC_WB(OFFSET_ASR, OP_STR, 32); }
+static INSN_REGPARM void arm7A4(uint32_t opcode) { STR_PREINC_WB(OFFSET_ASR, OP_STR, 32); }
// STR Rd, [Rn, Rm, ROR #]!
-static INSN_REGPARM void arm7A6(u32 opcode) { STR_PREINC_WB(OFFSET_ROR, OP_STR, 32); }
+static INSN_REGPARM void arm7A6(uint32_t opcode) { STR_PREINC_WB(OFFSET_ROR, OP_STR, 32); }
// LDR Rd, [Rn, Rm, LSL #]!
-static INSN_REGPARM void arm7B0(u32 opcode) { LDR_PREINC_WB(OFFSET_LSL, OP_LDR, 32); }
+static INSN_REGPARM void arm7B0(uint32_t opcode) { LDR_PREINC_WB(OFFSET_LSL, OP_LDR, 32); }
// LDR Rd, [Rn, Rm, LSR #]!
-static INSN_REGPARM void arm7B2(u32 opcode) { LDR_PREINC_WB(OFFSET_LSR, OP_LDR, 32); }
+static INSN_REGPARM void arm7B2(uint32_t opcode) { LDR_PREINC_WB(OFFSET_LSR, OP_LDR, 32); }
// LDR Rd, [Rn, Rm, ASR #]!
-static INSN_REGPARM void arm7B4(u32 opcode) { LDR_PREINC_WB(OFFSET_ASR, OP_LDR, 32); }
+static INSN_REGPARM void arm7B4(uint32_t opcode) { LDR_PREINC_WB(OFFSET_ASR, OP_LDR, 32); }
// LDR Rd, [Rn, Rm, ROR #]!
-static INSN_REGPARM void arm7B6(u32 opcode) { LDR_PREINC_WB(OFFSET_ROR, OP_LDR, 32); }
+static INSN_REGPARM void arm7B6(uint32_t opcode) { LDR_PREINC_WB(OFFSET_ROR, OP_LDR, 32); }
// STRB Rd, [Rn, Rm, LSL #]
-static INSN_REGPARM void arm7C0(u32 opcode) { STR_PREINC(OFFSET_LSL, OP_STRB, 16); }
+static INSN_REGPARM void arm7C0(uint32_t opcode) { STR_PREINC(OFFSET_LSL, OP_STRB, 16); }
// STRB Rd, [Rn, Rm, LSR #]
-static INSN_REGPARM void arm7C2(u32 opcode) { STR_PREINC(OFFSET_LSR, OP_STRB, 16); }
+static INSN_REGPARM void arm7C2(uint32_t opcode) { STR_PREINC(OFFSET_LSR, OP_STRB, 16); }
// STRB Rd, [Rn, Rm, ASR #]
-static INSN_REGPARM void arm7C4(u32 opcode) { STR_PREINC(OFFSET_ASR, OP_STRB, 16); }
+static INSN_REGPARM void arm7C4(uint32_t opcode) { STR_PREINC(OFFSET_ASR, OP_STRB, 16); }
// STRB Rd, [Rn, Rm, ROR #]
-static INSN_REGPARM void arm7C6(u32 opcode) { STR_PREINC(OFFSET_ROR, OP_STRB, 16); }
+static INSN_REGPARM void arm7C6(uint32_t opcode) { STR_PREINC(OFFSET_ROR, OP_STRB, 16); }
// LDRB Rd, [Rn, Rm, LSL #]
-static INSN_REGPARM void arm7D0(u32 opcode) { LDR_PREINC(OFFSET_LSL, OP_LDRB, 16); }
+static INSN_REGPARM void arm7D0(uint32_t opcode) { LDR_PREINC(OFFSET_LSL, OP_LDRB, 16); }
// LDRB Rd, [Rn, Rm, LSR #]
-static INSN_REGPARM void arm7D2(u32 opcode) { LDR_PREINC(OFFSET_LSR, OP_LDRB, 16); }
+static INSN_REGPARM void arm7D2(uint32_t opcode) { LDR_PREINC(OFFSET_LSR, OP_LDRB, 16); }
// LDRB Rd, [Rn, Rm, ASR #]
-static INSN_REGPARM void arm7D4(u32 opcode) { LDR_PREINC(OFFSET_ASR, OP_LDRB, 16); }
+static INSN_REGPARM void arm7D4(uint32_t opcode) { LDR_PREINC(OFFSET_ASR, OP_LDRB, 16); }
// LDRB Rd, [Rn, Rm, ROR #]
-static INSN_REGPARM void arm7D6(u32 opcode) { LDR_PREINC(OFFSET_ROR, OP_LDRB, 16); }
+static INSN_REGPARM void arm7D6(uint32_t opcode) { LDR_PREINC(OFFSET_ROR, OP_LDRB, 16); }
// STRB Rd, [Rn, Rm, LSL #]!
-static INSN_REGPARM void arm7E0(u32 opcode) { STR_PREINC_WB(OFFSET_LSL, OP_STRB, 16); }
+static INSN_REGPARM void arm7E0(uint32_t opcode) { STR_PREINC_WB(OFFSET_LSL, OP_STRB, 16); }
// STRB Rd, [Rn, Rm, LSR #]!
-static INSN_REGPARM void arm7E2(u32 opcode) { STR_PREINC_WB(OFFSET_LSR, OP_STRB, 16); }
+static INSN_REGPARM void arm7E2(uint32_t opcode) { STR_PREINC_WB(OFFSET_LSR, OP_STRB, 16); }
// STRB Rd, [Rn, Rm, ASR #]!
-static INSN_REGPARM void arm7E4(u32 opcode) { STR_PREINC_WB(OFFSET_ASR, OP_STRB, 16); }
+static INSN_REGPARM void arm7E4(uint32_t opcode) { STR_PREINC_WB(OFFSET_ASR, OP_STRB, 16); }
// STRB Rd, [Rn, Rm, ROR #]!
-static INSN_REGPARM void arm7E6(u32 opcode) { STR_PREINC_WB(OFFSET_ROR, OP_STRB, 16); }
+static INSN_REGPARM void arm7E6(uint32_t opcode) { STR_PREINC_WB(OFFSET_ROR, OP_STRB, 16); }
// LDRB Rd, [Rn, Rm, LSL #]!
-static INSN_REGPARM void arm7F0(u32 opcode) { LDR_PREINC_WB(OFFSET_LSL, OP_LDRB, 16); }
+static INSN_REGPARM void arm7F0(uint32_t opcode) { LDR_PREINC_WB(OFFSET_LSL, OP_LDRB, 16); }
// LDRB Rd, [Rn, Rm, LSR #]!
-static INSN_REGPARM void arm7F2(u32 opcode) { LDR_PREINC_WB(OFFSET_LSR, OP_LDRB, 16); }
+static INSN_REGPARM void arm7F2(uint32_t opcode) { LDR_PREINC_WB(OFFSET_LSR, OP_LDRB, 16); }
// LDRB Rd, [Rn, Rm, ASR #]!
-static INSN_REGPARM void arm7F4(u32 opcode) { LDR_PREINC_WB(OFFSET_ASR, OP_LDRB, 16); }
+static INSN_REGPARM void arm7F4(uint32_t opcode) { LDR_PREINC_WB(OFFSET_ASR, OP_LDRB, 16); }
// LDRB Rd, [Rn, Rm, ROR #]!
-static INSN_REGPARM void arm7F6(u32 opcode) { LDR_PREINC_WB(OFFSET_ROR, OP_LDRB, 16); }
+static INSN_REGPARM void arm7F6(uint32_t opcode) { LDR_PREINC_WB(OFFSET_ROR, OP_LDRB, 16); }
// STM/LDM ////////////////////////////////////////////////////////////////
@@ -2144,56 +2144,56 @@
// STMDA Rn, {Rlist}
-static INSN_REGPARM void arm800(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 temp = reg[base].I -
+static INSN_REGPARM void arm800(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t temp = reg[base].I -
4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]);
- u32 address = (temp + 4) & 0xFFFFFFFC;
+ uint32_t address = (temp + 4) & 0xFFFFFFFC;
int count = 0;
STM_ALL;
clockTicks += 1 + codeTicksAccess32(armNextPC);
}
// LDMDA Rn, {Rlist}
-static INSN_REGPARM void arm810(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 temp = reg[base].I -
+static INSN_REGPARM void arm810(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t temp = reg[base].I -
4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]);
- u32 address = (temp + 4) & 0xFFFFFFFC;
+ uint32_t address = (temp + 4) & 0xFFFFFFFC;
int count = 0;
LDM_ALL;
clockTicks += 2 + codeTicksAccess32(armNextPC);
}
// STMDA Rn!, {Rlist}
-static INSN_REGPARM void arm820(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 temp = reg[base].I -
+static INSN_REGPARM void arm820(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t temp = reg[base].I -
4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]);
- u32 address = (temp+4) & 0xFFFFFFFC;
+ uint32_t address = (temp+4) & 0xFFFFFFFC;
int count = 0;
STMW_ALL;
clockTicks += 1 + codeTicksAccess32(armNextPC);
}
// LDMDA Rn!, {Rlist}
-static INSN_REGPARM void arm830(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 temp = reg[base].I -
+static INSN_REGPARM void arm830(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t temp = reg[base].I -
4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]);
- u32 address = (temp + 4) & 0xFFFFFFFC;
+ uint32_t address = (temp + 4) & 0xFFFFFFFC;
int count = 0;
LDM_ALL;
clockTicks += 2 + codeTicksAccess32(armNextPC);
@@ -2202,28 +2202,28 @@
}
// STMDA Rn, {Rlist}^
-static INSN_REGPARM void arm840(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 temp = reg[base].I -
+static INSN_REGPARM void arm840(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t temp = reg[base].I -
4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]);
- u32 address = (temp+4) & 0xFFFFFFFC;
+ uint32_t address = (temp+4) & 0xFFFFFFFC;
int count = 0;
STM_ALL_2;
clockTicks += 1 + codeTicksAccess32(armNextPC);
}
// LDMDA Rn, {Rlist}^
-static INSN_REGPARM void arm850(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 temp = reg[base].I -
+static INSN_REGPARM void arm850(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t temp = reg[base].I -
4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]);
- u32 address = (temp + 4) & 0xFFFFFFFC;
+ uint32_t address = (temp + 4) & 0xFFFFFFFC;
int count = 0;
LDM_ALL_2;
LDM_ALL_2B;
@@ -2231,28 +2231,28 @@
}
// STMDA Rn!, {Rlist}^
-static INSN_REGPARM void arm860(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 temp = reg[base].I -
+static INSN_REGPARM void arm860(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t temp = reg[base].I -
4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]);
- u32 address = (temp+4) & 0xFFFFFFFC;
+ uint32_t address = (temp+4) & 0xFFFFFFFC;
int count = 0;
STMW_ALL_2;
clockTicks += 1 + codeTicksAccess32(armNextPC);
}
// LDMDA Rn!, {Rlist}^
-static INSN_REGPARM void arm870(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 temp = reg[base].I -
+static INSN_REGPARM void arm870(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t temp = reg[base].I -
4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]);
- u32 address = (temp + 4) & 0xFFFFFFFC;
+ uint32_t address = (temp + 4) & 0xFFFFFFFC;
int count = 0;
LDM_ALL_2;
if (!(opcode & (1U << base)))
@@ -2262,52 +2262,52 @@
}
// STMIA Rn, {Rlist}
-static INSN_REGPARM void arm880(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 address = reg[base].I & 0xFFFFFFFC;
+static INSN_REGPARM void arm880(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t address = reg[base].I & 0xFFFFFFFC;
int count = 0;
STM_ALL;
clockTicks += 1 + codeTicksAccess32(armNextPC);
}
// LDMIA Rn, {Rlist}
-static INSN_REGPARM void arm890(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 address = reg[base].I & 0xFFFFFFFC;
+static INSN_REGPARM void arm890(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t address = reg[base].I & 0xFFFFFFFC;
int count = 0;
LDM_ALL;
clockTicks += 2 + codeTicksAccess32(armNextPC);
}
// STMIA Rn!, {Rlist}
-static INSN_REGPARM void arm8A0(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 address = reg[base].I & 0xFFFFFFFC;
- int count = 0;
- u32 temp = reg[base].I +
+static INSN_REGPARM void arm8A0(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t address = reg[base].I & 0xFFFFFFFC;
+ int count = 0;
+ uint32_t temp = reg[base].I +
4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]);
STMW_ALL;
clockTicks += 1 + codeTicksAccess32(armNextPC);
}
// LDMIA Rn!, {Rlist}
-static INSN_REGPARM void arm8B0(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 temp = reg[base].I +
+static INSN_REGPARM void arm8B0(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t temp = reg[base].I +
4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]);
- u32 address = reg[base].I & 0xFFFFFFFC;
+ uint32_t address = reg[base].I & 0xFFFFFFFC;
int count = 0;
LDM_ALL;
clockTicks += 2 + codeTicksAccess32(armNextPC);
@@ -2316,24 +2316,24 @@
}
// STMIA Rn, {Rlist}^
-static INSN_REGPARM void arm8C0(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 address = reg[base].I & 0xFFFFFFFC;
+static INSN_REGPARM void arm8C0(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t address = reg[base].I & 0xFFFFFFFC;
int count = 0;
STM_ALL_2;
clockTicks += 1 + codeTicksAccess32(armNextPC);
}
// LDMIA Rn, {Rlist}^
-static INSN_REGPARM void arm8D0(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 address = reg[base].I & 0xFFFFFFFC;
+static INSN_REGPARM void arm8D0(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t address = reg[base].I & 0xFFFFFFFC;
int count = 0;
LDM_ALL_2;
LDM_ALL_2B;
@@ -2341,28 +2341,28 @@
}
// STMIA Rn!, {Rlist}^
-static INSN_REGPARM void arm8E0(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 address = reg[base].I & 0xFFFFFFFC;
- int count = 0;
- u32 temp = reg[base].I +
+static INSN_REGPARM void arm8E0(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t address = reg[base].I & 0xFFFFFFFC;
+ int count = 0;
+ uint32_t temp = reg[base].I +
4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]);
STMW_ALL_2;
clockTicks += 1 + codeTicksAccess32(armNextPC);
}
// LDMIA Rn!, {Rlist}^
-static INSN_REGPARM void arm8F0(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 temp = reg[base].I +
+static INSN_REGPARM void arm8F0(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t temp = reg[base].I +
4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]);
- u32 address = reg[base].I & 0xFFFFFFFC;
+ uint32_t address = reg[base].I & 0xFFFFFFFC;
int count = 0;
LDM_ALL_2;
if (!(opcode & (1U << base)))
@@ -2372,56 +2372,56 @@
}
// STMDB Rn, {Rlist}
-static INSN_REGPARM void arm900(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 temp = reg[base].I -
+static INSN_REGPARM void arm900(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t temp = reg[base].I -
4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]);
- u32 address = temp & 0xFFFFFFFC;
+ uint32_t address = temp & 0xFFFFFFFC;
int count = 0;
STM_ALL;
clockTicks += 1 + codeTicksAccess32(armNextPC);
}
// LDMDB Rn, {Rlist}
-static INSN_REGPARM void arm910(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 temp = reg[base].I -
+static INSN_REGPARM void arm910(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t temp = reg[base].I -
4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]);
- u32 address = temp & 0xFFFFFFFC;
+ uint32_t address = temp & 0xFFFFFFFC;
int count = 0;
LDM_ALL;
clockTicks += 2 + codeTicksAccess32(armNextPC);
}
// STMDB Rn!, {Rlist}
-static INSN_REGPARM void arm920(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 temp = reg[base].I -
+static INSN_REGPARM void arm920(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t temp = reg[base].I -
4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]);
- u32 address = temp & 0xFFFFFFFC;
+ uint32_t address = temp & 0xFFFFFFFC;
int count = 0;
STMW_ALL;
clockTicks += 1 + codeTicksAccess32(armNextPC);
}
// LDMDB Rn!, {Rlist}
-static INSN_REGPARM void arm930(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 temp = reg[base].I -
+static INSN_REGPARM void arm930(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t temp = reg[base].I -
4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]);
- u32 address = temp & 0xFFFFFFFC;
+ uint32_t address = temp & 0xFFFFFFFC;
int count = 0;
LDM_ALL;
clockTicks += 2 + codeTicksAccess32(armNextPC);
@@ -2430,28 +2430,28 @@
}
// STMDB Rn, {Rlist}^
-static INSN_REGPARM void arm940(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 temp = reg[base].I -
+static INSN_REGPARM void arm940(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t temp = reg[base].I -
4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]);
- u32 address = temp & 0xFFFFFFFC;
+ uint32_t address = temp & 0xFFFFFFFC;
int count = 0;
STM_ALL_2;
clockTicks += 1 + codeTicksAccess32(armNextPC);
}
// LDMDB Rn, {Rlist}^
-static INSN_REGPARM void arm950(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 temp = reg[base].I -
+static INSN_REGPARM void arm950(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t temp = reg[base].I -
4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]);
- u32 address = temp & 0xFFFFFFFC;
+ uint32_t address = temp & 0xFFFFFFFC;
int count = 0;
LDM_ALL_2;
LDM_ALL_2B;
@@ -2459,28 +2459,28 @@
}
// STMDB Rn!, {Rlist}^
-static INSN_REGPARM void arm960(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 temp = reg[base].I -
+static INSN_REGPARM void arm960(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t temp = reg[base].I -
4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]);
- u32 address = temp & 0xFFFFFFFC;
+ uint32_t address = temp & 0xFFFFFFFC;
int count = 0;
STMW_ALL_2;
clockTicks += 1 + codeTicksAccess32(armNextPC);
}
// LDMDB Rn!, {Rlist}^
-static INSN_REGPARM void arm970(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 temp = reg[base].I -
+static INSN_REGPARM void arm970(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t temp = reg[base].I -
4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]);
- u32 address = temp & 0xFFFFFFFC;
+ uint32_t address = temp & 0xFFFFFFFC;
int count = 0;
LDM_ALL_2;
if (!(opcode & (1U << base)))
@@ -2490,52 +2490,52 @@
}
// STMIB Rn, {Rlist}
-static INSN_REGPARM void arm980(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 address = (reg[base].I+4) & 0xFFFFFFFC;
+static INSN_REGPARM void arm980(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t address = (reg[base].I+4) & 0xFFFFFFFC;
int count = 0;
STM_ALL;
clockTicks += 1 + codeTicksAccess32(armNextPC);
}
// LDMIB Rn, {Rlist}
-static INSN_REGPARM void arm990(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 address = (reg[base].I+4) & 0xFFFFFFFC;
+static INSN_REGPARM void arm990(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t address = (reg[base].I+4) & 0xFFFFFFFC;
int count = 0;
LDM_ALL;
clockTicks += 2 + codeTicksAccess32(armNextPC);
}
// STMIB Rn!, {Rlist}
-static INSN_REGPARM void arm9A0(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 address = (reg[base].I+4) & 0xFFFFFFFC;
- int count = 0;
- u32 temp = reg[base].I +
+static INSN_REGPARM void arm9A0(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t address = (reg[base].I+4) & 0xFFFFFFFC;
+ int count = 0;
+ uint32_t temp = reg[base].I +
4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]);
STMW_ALL;
clockTicks += 1 + codeTicksAccess32(armNextPC);
}
// LDMIB Rn!, {Rlist}
-static INSN_REGPARM void arm9B0(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 temp = reg[base].I +
+static INSN_REGPARM void arm9B0(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t temp = reg[base].I +
4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]);
- u32 address = (reg[base].I+4) & 0xFFFFFFFC;
+ uint32_t address = (reg[base].I+4) & 0xFFFFFFFC;
int count = 0;
LDM_ALL;
clockTicks += 2 + codeTicksAccess32(armNextPC);
@@ -2544,24 +2544,24 @@
}
// STMIB Rn, {Rlist}^
-static INSN_REGPARM void arm9C0(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 address = (reg[base].I+4) & 0xFFFFFFFC;
+static INSN_REGPARM void arm9C0(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t address = (reg[base].I+4) & 0xFFFFFFFC;
int count = 0;
STM_ALL_2;
clockTicks += 1 + codeTicksAccess32(armNextPC);
}
// LDMIB Rn, {Rlist}^
-static INSN_REGPARM void arm9D0(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 address = (reg[base].I+4) & 0xFFFFFFFC;
+static INSN_REGPARM void arm9D0(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t address = (reg[base].I+4) & 0xFFFFFFFC;
int count = 0;
LDM_ALL_2;
LDM_ALL_2B;
@@ -2569,28 +2569,28 @@
}
// STMIB Rn!, {Rlist}^
-static INSN_REGPARM void arm9E0(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 address = (reg[base].I+4) & 0xFFFFFFFC;
- int count = 0;
- u32 temp = reg[base].I +
+static INSN_REGPARM void arm9E0(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t address = (reg[base].I+4) & 0xFFFFFFFC;
+ int count = 0;
+ uint32_t temp = reg[base].I +
4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]);
STMW_ALL_2;
clockTicks += 1 + codeTicksAccess32(armNextPC);
}
// LDMIB Rn!, {Rlist}^
-static INSN_REGPARM void arm9F0(u32 opcode)
-{
- if (busPrefetchCount == 0)
- busPrefetch = busPrefetchEnable;
- int base = (opcode & 0x000F0000) >> 16;
- u32 temp = reg[base].I +
+static INSN_REGPARM void arm9F0(uint32_t opcode)
+{
+ if (busPrefetchCount == 0)
+ busPrefetch = busPrefetchEnable;
+ int base = (opcode & 0x000F0000) >> 16;
+ uint32_t temp = reg[base].I +
4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]);
- u32 address = (reg[base].I+4) & 0xFFFFFFFC;
+ uint32_t address = (reg[base].I+4) & 0xFFFFFFFC;
int count = 0;
LDM_ALL_2;
if (!(opcode & (1U << base)))
@@ -2602,7 +2602,7 @@
// B/BL/SWI and (unimplemented) coproc support ////////////////////////////
// B <offset>
-static INSN_REGPARM void armA00(u32 opcode)
+static INSN_REGPARM void armA00(uint32_t opcode)
{
int offset = opcode & 0x00FFFFFF;
if (offset & 0x00800000)
@@ -2617,7 +2617,7 @@
}
// BL <offset>
-static INSN_REGPARM void armB00(u32 opcode)
+static INSN_REGPARM void armB00(uint32_t opcode)
{
int offset = opcode & 0x00FFFFFF;
if (offset & 0x00800000)
@@ -2636,7 +2636,7 @@
#ifdef GP_SUPPORT
// MRC
-static INSN_REGPARM void armE01(u32 opcode)
+static INSN_REGPARM void armE01(uint32_t opcode)
{
}
#else
@@ -2645,7 +2645,7 @@
// SWI <comment>
-static INSN_REGPARM void armF00(u32 opcode)
+static INSN_REGPARM void armF00(uint32_t opcode)
{
clockTicks = codeTicksAccessSeq32(armNextPC) + 1;
clockTicks = (clockTicks * 2) + codeTicksAccess32(armNextPC) + 1;
@@ -2655,7 +2655,7 @@
// Instruction table //////////////////////////////////////////////////////
-typedef INSN_REGPARM void (*insnfunc_t)(u32 opcode);
+typedef INSN_REGPARM void (*insnfunc_t)(uint32_t opcode);
#define REP16(insn) \
insn,insn,insn,insn,insn,insn,insn,insn,\
insn,insn,insn,insn,insn,insn,insn,insn
@@ -2874,7 +2874,7 @@
if ((armNextPC & 0x0803FFFF) == 0x08020000)
busPrefetchCount = 0x100;
- u32 opcode = cpuPrefetch[0];
+ uint32_t opcode = cpuPrefetch[0];
cpuPrefetch[0] = cpuPrefetch[1];
busPrefetch = false;
--- a/src/in_gsf/vbam/gba/GBA-thumb.cpp
+++ b/src/in_gsf/vbam/gba/GBA-thumb.cpp
@@ -31,7 +31,7 @@
static int clockTicks;
-static INSN_REGPARM void thumbUnknownInsn(u32 opcode)
+static INSN_REGPARM void thumbUnknownInsn(uint32_t opcode)
{
#ifdef GBA_LOGGING
if(systemVerbose & VERBOSE_UNDEFINED)
@@ -41,7 +41,7 @@
}
#ifdef BKPT_SUPPORT
-static INSN_REGPARM void thumbBreakpoint(u32 opcode)
+static INSN_REGPARM void thumbBreakpoint(uint32_t opcode)
{
reg[15].I -= 2;
armNextPC -= 2;
@@ -745,9 +745,9 @@
#ifndef ADD_RD_RS_RN
#define ADD_RD_RS_RN(N) \
{\
- u32 lhs = reg[source].I;\
- u32 rhs = reg[N].I;\
- u32 res = lhs + rhs;\
+ uint32_t lhs = reg[source].I;\
+ uint32_t rhs = reg[N].I;\
+ uint32_t res = lhs + rhs;\
reg[dest].I = res;\
Z_FLAG = (res == 0) ? true : false;\
N_FLAG = NEG(res) ? true : false;\
@@ -758,9 +758,9 @@
#ifndef ADD_RD_RS_O3
#define ADD_RD_RS_O3(N) \
{\
- u32 lhs = reg[source].I;\
- u32 rhs = N;\
- u32 res = lhs + rhs;\
+ uint32_t lhs = reg[source].I;\
+ uint32_t rhs = N;\
+ uint32_t res = lhs + rhs;\
reg[dest].I = res;\
Z_FLAG = (res == 0) ? true : false;\
N_FLAG = NEG(res) ? true : false;\
@@ -774,9 +774,9 @@
#ifndef ADD_RN_O8
#define ADD_RN_O8(d) \
{\
- u32 lhs = reg[(d)].I;\
- u32 rhs = (opcode & 255);\
- u32 res = lhs + rhs;\
+ uint32_t lhs = reg[(d)].I;\
+ uint32_t rhs = (opcode & 255);\
+ uint32_t res = lhs + rhs;\
reg[(d)].I = res;\
Z_FLAG = (res == 0) ? true : false;\
N_FLAG = NEG(res) ? true : false;\
@@ -787,9 +787,9 @@
#ifndef CMN_RD_RS
#define CMN_RD_RS \
{\
- u32 lhs = reg[dest].I;\
- u32 rhs = value;\
- u32 res = lhs + rhs;\
+ uint32_t lhs = reg[dest].I;\
+ uint32_t rhs = value;\
+ uint32_t res = lhs + rhs;\
Z_FLAG = (res == 0) ? true : false;\
N_FLAG = NEG(res) ? true : false;\
ADDCARRY(lhs, rhs, res);\
@@ -799,9 +799,9 @@
#ifndef ADC_RD_RS
#define ADC_RD_RS \
{\
- u32 lhs = reg[dest].I;\
- u32 rhs = value;\
- u32 res = lhs + rhs + (u32)C_FLAG;\
+ uint32_t lhs = reg[dest].I;\
+ uint32_t rhs = value;\
+ uint32_t res = lhs + rhs + (uint32_t)C_FLAG;\
reg[dest].I = res;\
Z_FLAG = (res == 0) ? true : false;\
N_FLAG = NEG(res) ? true : false;\
@@ -812,9 +812,9 @@
#ifndef SUB_RD_RS_RN
#define SUB_RD_RS_RN(N) \
{\
- u32 lhs = reg[source].I;\
- u32 rhs = reg[N].I;\
- u32 res = lhs - rhs;\
+ uint32_t lhs = reg[source].I;\
+ uint32_t rhs = reg[N].I;\
+ uint32_t res = lhs - rhs;\
reg[dest].I = res;\
Z_FLAG = (res == 0) ? true : false;\
N_FLAG = NEG(res) ? true : false;\
@@ -825,9 +825,9 @@
#ifndef SUB_RD_RS_O3
#define SUB_RD_RS_O3(N) \
{\
- u32 lhs = reg[source].I;\
- u32 rhs = N;\
- u32 res = lhs - rhs;\
+ uint32_t lhs = reg[source].I;\
+ uint32_t rhs = N;\
+ uint32_t res = lhs - rhs;\
reg[dest].I = res;\
Z_FLAG = (res == 0) ? true : false;\
N_FLAG = NEG(res) ? true : false;\
@@ -841,9 +841,9 @@
#ifndef SUB_RN_O8
#define SUB_RN_O8(d) \
{\
- u32 lhs = reg[(d)].I;\
- u32 rhs = (opcode & 255);\
- u32 res = lhs - rhs;\
+ uint32_t lhs = reg[(d)].I;\
+ uint32_t rhs = (opcode & 255);\
+ uint32_t res = lhs - rhs;\
reg[(d)].I = res;\
Z_FLAG = (res == 0) ? true : false;\
N_FLAG = NEG(res) ? true : false;\
@@ -862,9 +862,9 @@
#ifndef CMP_RN_O8
#define CMP_RN_O8(d) \
{\
- u32 lhs = reg[(d)].I;\
- u32 rhs = (opcode & 255);\
- u32 res = lhs - rhs;\
+ uint32_t lhs = reg[(d)].I;\
+ uint32_t rhs = (opcode & 255);\
+ uint32_t res = lhs - rhs;\
Z_FLAG = (res == 0) ? true : false;\
N_FLAG = NEG(res) ? true : false;\
SUBCARRY(lhs, rhs, res);\
@@ -874,9 +874,9 @@
#ifndef SBC_RD_RS
#define SBC_RD_RS \
{\
- u32 lhs = reg[dest].I;\
- u32 rhs = value;\
- u32 res = lhs - rhs - !((u32)C_FLAG);\
+ uint32_t lhs = reg[dest].I;\
+ uint32_t rhs = value;\
+ uint32_t res = lhs - rhs - !((uint32_t)C_FLAG);\
reg[dest].I = res;\
Z_FLAG = (res == 0) ? true : false;\
N_FLAG = NEG(res) ? true : false;\
@@ -915,15 +915,15 @@
#ifndef ASR_RD_RM_I5
#define ASR_RD_RM_I5 \
{\
- C_FLAG = ((s32)reg[source].I >> (int)(shift - 1)) & 1 ? true : false;\
- value = (s32)reg[source].I >> (int)shift;\
+ C_FLAG = ((int32_t)reg[source].I >> (int)(shift - 1)) & 1 ? true : false;\
+ value = (int32_t)reg[source].I >> (int)shift;\
}
#endif
#ifndef ASR_RD_RS
#define ASR_RD_RS \
{\
- C_FLAG = ((s32)reg[dest].I >> (int)(value - 1)) & 1 ? true : false;\
- value = (s32)reg[dest].I >> (int)value;\
+ C_FLAG = ((int32_t)reg[dest].I >> (int)(value - 1)) & 1 ? true : false;\
+ value = (int32_t)reg[dest].I >> (int)value;\
}
#endif
#ifndef ROR_RD_RS
@@ -937,9 +937,9 @@
#ifndef NEG_RD_RS
#define NEG_RD_RS \
{\
- u32 lhs = reg[source].I;\
- u32 rhs = 0;\
- u32 res = rhs - lhs;\
+ uint32_t lhs = reg[source].I;\
+ uint32_t rhs = 0;\
+ uint32_t res = rhs - lhs;\
reg[dest].I = res;\
Z_FLAG = (res == 0) ? true : false;\
N_FLAG = NEG(res) ? true : false;\
@@ -950,9 +950,9 @@
#ifndef CMP_RD_RS
#define CMP_RD_RS \
{\
- u32 lhs = reg[dest].I;\
- u32 rhs = value;\
- u32 res = lhs - rhs;\
+ uint32_t lhs = reg[dest].I;\
+ uint32_t rhs = value;\
+ uint32_t res = lhs - rhs;\
Z_FLAG = (res == 0) ? true : false;\
N_FLAG = NEG(res) ? true : false;\
SUBCARRY(lhs, rhs, res);\
@@ -963,7 +963,7 @@
#define IMM5_INSN(OP,N) \
int dest = opcode & 0x07;\
int source = (opcode >> 3) & 0x07;\
- u32 value;\
+ uint32_t value;\
OP(N);\
reg[dest].I = value;\
N_FLAG = (value & 0x80000000 ? true : false);\
@@ -971,7 +971,7 @@
#define IMM5_INSN_0(OP) \
int dest = opcode & 0x07;\
int source = (opcode >> 3) & 0x07;\
- u32 value;\
+ uint32_t value;\
OP;\
reg[dest].I = value;\
N_FLAG = (value & 0x80000000 ? true : false);\
@@ -1009,38 +1009,38 @@
// Shift instructions /////////////////////////////////////////////////////
#define DEFINE_IMM5_INSN(OP,BASE) \
- static INSN_REGPARM void thumb##BASE##_00(u32 opcode) { IMM5_INSN_0(OP##_0); } \
- static INSN_REGPARM void thumb##BASE##_01(u32 opcode) { IMM5_INSN(OP, 1); } \
- static INSN_REGPARM void thumb##BASE##_02(u32 opcode) { IMM5_INSN(OP, 2); } \
- static INSN_REGPARM void thumb##BASE##_03(u32 opcode) { IMM5_INSN(OP, 3); } \
- static INSN_REGPARM void thumb##BASE##_04(u32 opcode) { IMM5_INSN(OP, 4); } \
- static INSN_REGPARM void thumb##BASE##_05(u32 opcode) { IMM5_INSN(OP, 5); } \
- static INSN_REGPARM void thumb##BASE##_06(u32 opcode) { IMM5_INSN(OP, 6); } \
- static INSN_REGPARM void thumb##BASE##_07(u32 opcode) { IMM5_INSN(OP, 7); } \
- static INSN_REGPARM void thumb##BASE##_08(u32 opcode) { IMM5_INSN(OP, 8); } \
- static INSN_REGPARM void thumb##BASE##_09(u32 opcode) { IMM5_INSN(OP, 9); } \
- static INSN_REGPARM void thumb##BASE##_0A(u32 opcode) { IMM5_INSN(OP,10); } \
- static INSN_REGPARM void thumb##BASE##_0B(u32 opcode) { IMM5_INSN(OP,11); } \
- static INSN_REGPARM void thumb##BASE##_0C(u32 opcode) { IMM5_INSN(OP,12); } \
- static INSN_REGPARM void thumb##BASE##_0D(u32 opcode) { IMM5_INSN(OP,13); } \
- static INSN_REGPARM void thumb##BASE##_0E(u32 opcode) { IMM5_INSN(OP,14); } \
- static INSN_REGPARM void thumb##BASE##_0F(u32 opcode) { IMM5_INSN(OP,15); } \
- static INSN_REGPARM void thumb##BASE##_10(u32 opcode) { IMM5_INSN(OP,16); } \
- static INSN_REGPARM void thumb##BASE##_11(u32 opcode) { IMM5_INSN(OP,17); } \
- static INSN_REGPARM void thumb##BASE##_12(u32 opcode) { IMM5_INSN(OP,18); } \
- static INSN_REGPARM void thumb##BASE##_13(u32 opcode) { IMM5_INSN(OP,19); } \
- static INSN_REGPARM void thumb##BASE##_14(u32 opcode) { IMM5_INSN(OP,20); } \
- static INSN_REGPARM void thumb##BASE##_15(u32 opcode) { IMM5_INSN(OP,21); } \
- static INSN_REGPARM void thumb##BASE##_16(u32 opcode) { IMM5_INSN(OP,22); } \
- static INSN_REGPARM void thumb##BASE##_17(u32 opcode) { IMM5_INSN(OP,23); } \
- static INSN_REGPARM void thumb##BASE##_18(u32 opcode) { IMM5_INSN(OP,24); } \
- static INSN_REGPARM void thumb##BASE##_19(u32 opcode) { IMM5_INSN(OP,25); } \
- static INSN_REGPARM void thumb##BASE##_1A(u32 opcode) { IMM5_INSN(OP,26); } \
- static INSN_REGPARM void thumb##BASE##_1B(u32 opcode) { IMM5_INSN(OP,27); } \
- static INSN_REGPARM void thumb##BASE##_1C(u32 opcode) { IMM5_INSN(OP,28); } \
- static INSN_REGPARM void thumb##BASE##_1D(u32 opcode) { IMM5_INSN(OP,29); } \
- static INSN_REGPARM void thumb##BASE##_1E(u32 opcode) { IMM5_INSN(OP,30); } \
- static INSN_REGPARM void thumb##BASE##_1F(u32 opcode) { IMM5_INSN(OP,31); }
+ static INSN_REGPARM void thumb##BASE##_00(uint32_t opcode) { IMM5_INSN_0(OP##_0); } \
+ static INSN_REGPARM void thumb##BASE##_01(uint32_t opcode) { IMM5_INSN(OP, 1); } \
+ static INSN_REGPARM void thumb##BASE##_02(uint32_t opcode) { IMM5_INSN(OP, 2); } \
+ static INSN_REGPARM void thumb##BASE##_03(uint32_t opcode) { IMM5_INSN(OP, 3); } \
+ static INSN_REGPARM void thumb##BASE##_04(uint32_t opcode) { IMM5_INSN(OP, 4); } \
+ static INSN_REGPARM void thumb##BASE##_05(uint32_t opcode) { IMM5_INSN(OP, 5); } \
+ static INSN_REGPARM void thumb##BASE##_06(uint32_t opcode) { IMM5_INSN(OP, 6); } \
+ static INSN_REGPARM void thumb##BASE##_07(uint32_t opcode) { IMM5_INSN(OP, 7); } \
+ static INSN_REGPARM void thumb##BASE##_08(uint32_t opcode) { IMM5_INSN(OP, 8); } \
+ static INSN_REGPARM void thumb##BASE##_09(uint32_t opcode) { IMM5_INSN(OP, 9); } \
+ static INSN_REGPARM void thumb##BASE##_0A(uint32_t opcode) { IMM5_INSN(OP,10); } \
+ static INSN_REGPARM void thumb##BASE##_0B(uint32_t opcode) { IMM5_INSN(OP,11); } \
+ static INSN_REGPARM void thumb##BASE##_0C(uint32_t opcode) { IMM5_INSN(OP,12); } \
+ static INSN_REGPARM void thumb##BASE##_0D(uint32_t opcode) { IMM5_INSN(OP,13); } \
+ static INSN_REGPARM void thumb##BASE##_0E(uint32_t opcode) { IMM5_INSN(OP,14); } \
+ static INSN_REGPARM void thumb##BASE##_0F(uint32_t opcode) { IMM5_INSN(OP,15); } \
+ static INSN_REGPARM void thumb##BASE##_10(uint32_t opcode) { IMM5_INSN(OP,16); } \
+ static INSN_REGPARM void thumb##BASE##_11(uint32_t opcode) { IMM5_INSN(OP,17); } \
+ static INSN_REGPARM void thumb##BASE##_12(uint32_t opcode) { IMM5_INSN(OP,18); } \
+ static INSN_REGPARM void thumb##BASE##_13(uint32_t opcode) { IMM5_INSN(OP,19); } \
+ static INSN_REGPARM void thumb##BASE##_14(uint32_t opcode) { IMM5_INSN(OP,20); } \
+ static INSN_REGPARM void thumb##BASE##_15(uint32_t opcode) { IMM5_INSN(OP,21); } \
+ static INSN_REGPARM void thumb##BASE##_16(uint32_t opcode) { IMM5_INSN(OP,22); } \
+ static INSN_REGPARM void thumb##BASE##_17(uint32_t opcode) { IMM5_INSN(OP,23); } \
+ static INSN_REGPARM void thumb##BASE##_18(uint32_t opcode) { IMM5_INSN(OP,24); } \
+ static INSN_REGPARM void thumb##BASE##_19(uint32_t opcode) { IMM5_INSN(OP,25); } \
+ static INSN_REGPARM void thumb##BASE##_1A(uint32_t opcode) { IMM5_INSN(OP,26); } \
+ static INSN_REGPARM void thumb##BASE##_1B(uint32_t opcode) { IMM5_INSN(OP,27); } \
+ static INSN_REGPARM void thumb##BASE##_1C(uint32_t opcode) { IMM5_INSN(OP,28); } \
+ static INSN_REGPARM void thumb##BASE##_1D(uint32_t opcode) { IMM5_INSN(OP,29); } \
+ static INSN_REGPARM void thumb##BASE##_1E(uint32_t opcode) { IMM5_INSN(OP,30); } \
+ static INSN_REGPARM void thumb##BASE##_1F(uint32_t opcode) { IMM5_INSN(OP,31); }
// LSL Rd, Rm, #Imm 5
DEFINE_IMM5_INSN(IMM5_LSL,00)
@@ -1052,24 +1052,24 @@
// 3-argument ADD/SUB /////////////////////////////////////////////////////
#define DEFINE_REG3_INSN(OP,BASE) \
- static INSN_REGPARM void thumb##BASE##_0(u32 opcode) { THREEARG_INSN(OP,0); } \
- static INSN_REGPARM void thumb##BASE##_1(u32 opcode) { THREEARG_INSN(OP,1); } \
- static INSN_REGPARM void thumb##BASE##_2(u32 opcode) { THREEARG_INSN(OP,2); } \
- static INSN_REGPARM void thumb##BASE##_3(u32 opcode) { THREEARG_INSN(OP,3); } \
- static INSN_REGPARM void thumb##BASE##_4(u32 opcode) { THREEARG_INSN(OP,4); } \
- static INSN_REGPARM void thumb##BASE##_5(u32 opcode) { THREEARG_INSN(OP,5); } \
- static INSN_REGPARM void thumb##BASE##_6(u32 opcode) { THREEARG_INSN(OP,6); } \
- static INSN_REGPARM void thumb##BASE##_7(u32 opcode) { THREEARG_INSN(OP,7); }
+ static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP,0); } \
+ static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP,1); } \
+ static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP,2); } \
+ static INSN_REGPARM void thumb##BASE##_3(uint32_t opcode) { THREEARG_INSN(OP,3); } \
+ static INSN_REGPARM void thumb##BASE##_4(uint32_t opcode) { THREEARG_INSN(OP,4); } \
+ static INSN_REGPARM void thumb##BASE##_5(uint32_t opcode) { THREEARG_INSN(OP,5); } \
+ static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP,6); } \
+ static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP,7); }
#define DEFINE_IMM3_INSN(OP,BASE) \
- static INSN_REGPARM void thumb##BASE##_0(u32 opcode) { THREEARG_INSN(OP##_0,0); } \
- static INSN_REGPARM void thumb##BASE##_1(u32 opcode) { THREEARG_INSN(OP,1); } \
- static INSN_REGPARM void thumb##BASE##_2(u32 opcode) { THREEARG_INSN(OP,2); } \
- static INSN_REGPARM void thumb##BASE##_3(u32 opcode) { THREEARG_INSN(OP,3); } \
- static INSN_REGPARM void thumb##BASE##_4(u32 opcode) { THREEARG_INSN(OP,4); } \
- static INSN_REGPARM void thumb##BASE##_5(u32 opcode) { THREEARG_INSN(OP,5); } \
- static INSN_REGPARM void thumb##BASE##_6(u32 opcode) { THREEARG_INSN(OP,6); } \
- static INSN_REGPARM void thumb##BASE##_7(u32 opcode) { THREEARG_INSN(OP,7); }
+ static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP##_0,0); } \
+ static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP,1); } \
+ static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP,2); } \
+ static INSN_REGPARM void thumb##BASE##_3(uint32_t opcode) { THREEARG_INSN(OP,3); } \
+ static INSN_REGPARM void thumb##BASE##_4(uint32_t opcode) { THREEARG_INSN(OP,4); } \
+ static INSN_REGPARM void thumb##BASE##_5(uint32_t opcode) { THREEARG_INSN(OP,5); } \
+ static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP,6); } \
+ static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP,7); }
// ADD Rd, Rs, Rn
DEFINE_REG3_INSN(ADD_RD_RS_RN,18)
@@ -1083,77 +1083,77 @@
// MOV/CMP/ADD/SUB immediate //////////////////////////////////////////////
// MOV R0, #Offset8
-static INSN_REGPARM void thumb20(u32 opcode) { MOV_RN_O8(0); }
+static INSN_REGPARM void thumb20(uint32_t opcode) { MOV_RN_O8(0); }
// MOV R1, #Offset8
-static INSN_REGPARM void thumb21(u32 opcode) { MOV_RN_O8(1); }
+static INSN_REGPARM void thumb21(uint32_t opcode) { MOV_RN_O8(1); }
// MOV R2, #Offset8
-static INSN_REGPARM void thumb22(u32 opcode) { MOV_RN_O8(2); }
+static INSN_REGPARM void thumb22(uint32_t opcode) { MOV_RN_O8(2); }
// MOV R3, #Offset8
-static INSN_REGPARM void thumb23(u32 opcode) { MOV_RN_O8(3); }
+static INSN_REGPARM void thumb23(uint32_t opcode) { MOV_RN_O8(3); }
// MOV R4, #Offset8
-static INSN_REGPARM void thumb24(u32 opcode) { MOV_RN_O8(4); }
+static INSN_REGPARM void thumb24(uint32_t opcode) { MOV_RN_O8(4); }
// MOV R5, #Offset8
-static INSN_REGPARM void thumb25(u32 opcode) { MOV_RN_O8(5); }
+static INSN_REGPARM void thumb25(uint32_t opcode) { MOV_RN_O8(5); }
// MOV R6, #Offset8
-static INSN_REGPARM void thumb26(u32 opcode) { MOV_RN_O8(6); }
+static INSN_REGPARM void thumb26(uint32_t opcode) { MOV_RN_O8(6); }
// MOV R7, #Offset8
-static INSN_REGPARM void thumb27(u32 opcode) { MOV_RN_O8(7); }
+static INSN_REGPARM void thumb27(uint32_t opcode) { MOV_RN_O8(7); }
// CMP R0, #Offset8
-static INSN_REGPARM void thumb28(u32 opcode) { CMP_RN_O8(0); }
+static INSN_REGPARM void thumb28(uint32_t opcode) { CMP_RN_O8(0); }
// CMP R1, #Offset8
-static INSN_REGPARM void thumb29(u32 opcode) { CMP_RN_O8(1); }
+static INSN_REGPARM void thumb29(uint32_t opcode) { CMP_RN_O8(1); }
// CMP R2, #Offset8
-static INSN_REGPARM void thumb2A(u32 opcode) { CMP_RN_O8(2); }
+static INSN_REGPARM void thumb2A(uint32_t opcode) { CMP_RN_O8(2); }
// CMP R3, #Offset8
-static INSN_REGPARM void thumb2B(u32 opcode) { CMP_RN_O8(3); }
+static INSN_REGPARM void thumb2B(uint32_t opcode) { CMP_RN_O8(3); }
// CMP R4, #Offset8
-static INSN_REGPARM void thumb2C(u32 opcode) { CMP_RN_O8(4); }
+static INSN_REGPARM void thumb2C(uint32_t opcode) { CMP_RN_O8(4); }
// CMP R5, #Offset8
-static INSN_REGPARM void thumb2D(u32 opcode) { CMP_RN_O8(5); }
+static INSN_REGPARM void thumb2D(uint32_t opcode) { CMP_RN_O8(5); }
// CMP R6, #Offset8
-static INSN_REGPARM void thumb2E(u32 opcode) { CMP_RN_O8(6); }
+static INSN_REGPARM void thumb2E(uint32_t opcode) { CMP_RN_O8(6); }
// CMP R7, #Offset8
-static INSN_REGPARM void thumb2F(u32 opcode) { CMP_RN_O8(7); }
+static INSN_REGPARM void thumb2F(uint32_t opcode) { CMP_RN_O8(7); }
// ADD R0,#Offset8
-static INSN_REGPARM void thumb30(u32 opcode) { ADD_RN_O8(0); }
+static INSN_REGPARM void thumb30(uint32_t opcode) { ADD_RN_O8(0); }
// ADD R1,#Offset8
-static INSN_REGPARM void thumb31(u32 opcode) { ADD_RN_O8(1); }
+static INSN_REGPARM void thumb31(uint32_t opcode) { ADD_RN_O8(1); }
// ADD R2,#Offset8
-static INSN_REGPARM void thumb32(u32 opcode) { ADD_RN_O8(2); }
+static INSN_REGPARM void thumb32(uint32_t opcode) { ADD_RN_O8(2); }
// ADD R3,#Offset8
-static INSN_REGPARM void thumb33(u32 opcode) { ADD_RN_O8(3); }
+static INSN_REGPARM void thumb33(uint32_t opcode) { ADD_RN_O8(3); }
// ADD R4,#Offset8
-static INSN_REGPARM void thumb34(u32 opcode) { ADD_RN_O8(4); }
+static INSN_REGPARM void thumb34(uint32_t opcode) { ADD_RN_O8(4); }
// ADD R5,#Offset8
-static INSN_REGPARM void thumb35(u32 opcode) { ADD_RN_O8(5); }
+static INSN_REGPARM void thumb35(uint32_t opcode) { ADD_RN_O8(5); }
// ADD R6,#Offset8
-static INSN_REGPARM void thumb36(u32 opcode) { ADD_RN_O8(6); }
+static INSN_REGPARM void thumb36(uint32_t opcode) { ADD_RN_O8(6); }
// ADD R7,#Offset8
-static INSN_REGPARM void thumb37(u32 opcode) { ADD_RN_O8(7); }
+static INSN_REGPARM void thumb37(uint32_t opcode) { ADD_RN_O8(7); }
// SUB R0,#Offset8
-static INSN_REGPARM void thumb38(u32 opcode) { SUB_RN_O8(0); }
+static INSN_REGPARM void thumb38(uint32_t opcode) { SUB_RN_O8(0); }
// SUB R1,#Offset8
-static INSN_REGPARM void thumb39(u32 opcode) { SUB_RN_O8(1); }
+static INSN_REGPARM void thumb39(uint32_t opcode) { SUB_RN_O8(1); }
// SUB R2,#Offset8
-static INSN_REGPARM void thumb3A(u32 opcode) { SUB_RN_O8(2); }
+static INSN_REGPARM void thumb3A(uint32_t opcode) { SUB_RN_O8(2); }
// SUB R3,#Offset8
-static INSN_REGPARM void thumb3B(u32 opcode) { SUB_RN_O8(3); }
+static INSN_REGPARM void thumb3B(uint32_t opcode) { SUB_RN_O8(3); }
// SUB R4,#Offset8
-static INSN_REGPARM void thumb3C(u32 opcode) { SUB_RN_O8(4); }
+static INSN_REGPARM void thumb3C(uint32_t opcode) { SUB_RN_O8(4); }
// SUB R5,#Offset8
-static INSN_REGPARM void thumb3D(u32 opcode) { SUB_RN_O8(5); }
+static INSN_REGPARM void thumb3D(uint32_t opcode) { SUB_RN_O8(5); }
// SUB R6,#Offset8
-static INSN_REGPARM void thumb3E(u32 opcode) { SUB_RN_O8(6); }
+static INSN_REGPARM void thumb3E(uint32_t opcode) { SUB_RN_O8(6); }
// SUB R7,#Offset8
-static INSN_REGPARM void thumb3F(u32 opcode) { SUB_RN_O8(7); }
+static INSN_REGPARM void thumb3F(uint32_t opcode) { SUB_RN_O8(7); }
// ALU operations /////////////////////////////////////////////////////////
// AND Rd, Rs
-static INSN_REGPARM void thumb40_0(u32 opcode)
+static INSN_REGPARM void thumb40_0(uint32_t opcode)
{
int dest = opcode & 7;
reg[dest].I &= reg[(opcode >> 3)&7].I;
@@ -1163,7 +1163,7 @@
}
// EOR Rd, Rs
-static INSN_REGPARM void thumb40_1(u32 opcode)
+static INSN_REGPARM void thumb40_1(uint32_t opcode)
{
int dest = opcode & 7;
reg[dest].I ^= reg[(opcode >> 3)&7].I;
@@ -1172,10 +1172,10 @@
}
// LSL Rd, Rs
-static INSN_REGPARM void thumb40_2(u32 opcode)
+static INSN_REGPARM void thumb40_2(uint32_t opcode)
{
int dest = opcode & 7;
- u32 value = reg[(opcode >> 3)&7].B.B0;
+ uint32_t value = reg[(opcode >> 3)&7].B.B0;
if(value) {
if(value == 32) {
value = 0;
@@ -1194,10 +1194,10 @@
}
// LSR Rd, Rs
-static INSN_REGPARM void thumb40_3(u32 opcode)
+static INSN_REGPARM void thumb40_3(uint32_t opcode)
{
int dest = opcode & 7;
- u32 value = reg[(opcode >> 3)&7].B.B0;
+ uint32_t value = reg[(opcode >> 3)&7].B.B0;
if(value) {
if(value == 32) {
value = 0;
@@ -1216,10 +1216,10 @@
}
// ASR Rd, Rs
-static INSN_REGPARM void thumb41_0(u32 opcode)
+static INSN_REGPARM void thumb41_0(uint32_t opcode)
{
int dest = opcode & 7;
- u32 value = reg[(opcode >> 3)&7].B.B0;
+ uint32_t value = reg[(opcode >> 3)&7].B.B0;
if(value) {
if(value < 32) {
ASR_RD_RS;
@@ -1240,26 +1240,26 @@
}
// ADC Rd, Rs
-static INSN_REGPARM void thumb41_1(u32 opcode)
+static INSN_REGPARM void thumb41_1(uint32_t opcode)
{
int dest = opcode & 0x07;
- u32 value = reg[(opcode >> 3)&7].I;
+ uint32_t value = reg[(opcode >> 3)&7].I;
ADC_RD_RS;
}
// SBC Rd, Rs
-static INSN_REGPARM void thumb41_2(u32 opcode)
+static INSN_REGPARM void thumb41_2(uint32_t opcode)
{
int dest = opcode & 0x07;
- u32 value = reg[(opcode >> 3)&7].I;
+ uint32_t value = reg[(opcode >> 3)&7].I;
SBC_RD_RS;
}
// ROR Rd, Rs
-static INSN_REGPARM void thumb41_3(u32 opcode)
+static INSN_REGPARM void thumb41_3(uint32_t opcode)
{
int dest = opcode & 7;
- u32 value = reg[(opcode >> 3)&7].B.B0;
+ uint32_t value = reg[(opcode >> 3)&7].B.B0;
if(value) {
value = value & 0x1f;
@@ -1276,15 +1276,15 @@
}
// TST Rd, Rs
-static INSN_REGPARM void thumb42_0(u32 opcode)
-{
- u32 value = reg[opcode & 7].I & reg[(opcode >> 3) & 7].I;
+static INSN_REGPARM void thumb42_0(uint32_t opcode)
+{
+ uint32_t value = reg[opcode & 7].I & reg[(opcode >> 3) & 7].I;
N_FLAG = value & 0x80000000 ? true : false;
Z_FLAG = value ? false : true;
}
// NEG Rd, Rs
-static INSN_REGPARM void thumb42_1(u32 opcode)
+static INSN_REGPARM void thumb42_1(uint32_t opcode)
{
int dest = opcode & 7;
int source = (opcode >> 3) & 7;
@@ -1292,23 +1292,23 @@
}
// CMP Rd, Rs
-static INSN_REGPARM void thumb42_2(u32 opcode)
+static INSN_REGPARM void thumb42_2(uint32_t opcode)
{
int dest = opcode & 7;
- u32 value = reg[(opcode >> 3)&7].I;
+ uint32_t value = reg[(opcode >> 3)&7].I;
CMP_RD_RS;
}
// CMN Rd, Rs
-static INSN_REGPARM void thumb42_3(u32 opcode)
+static INSN_REGPARM void thumb42_3(uint32_t opcode)
{
int dest = opcode & 7;
- u32 value = reg[(opcode >> 3)&7].I;
+ uint32_t value = reg[(opcode >> 3)&7].I;
CMN_RD_RS;
}
// ORR Rd, Rs
-static INSN_REGPARM void thumb43_0(u32 opcode)
+static INSN_REGPARM void thumb43_0(uint32_t opcode)
{
int dest = opcode & 7;
reg[dest].I |= reg[(opcode >> 3) & 7].I;
@@ -1317,13 +1317,13 @@
}
// MUL Rd, Rs
-static INSN_REGPARM void thumb43_1(u32 opcode)
+static INSN_REGPARM void thumb43_1(uint32_t opcode)
{
clockTicks = 1;
int dest = opcode & 7;
- u32 rm = reg[dest].I;
+ uint32_t rm = reg[dest].I;
reg[dest].I = reg[(opcode >> 3) & 7].I * rm;
- if (((s32)rm) < 0)
+ if (((int32_t)rm) < 0)
rm = ~rm;
if ((rm & 0xFFFFFF00) == 0)
clockTicks += 0;
@@ -1340,7 +1340,7 @@
}
// BIC Rd, Rs
-static INSN_REGPARM void thumb43_2(u32 opcode)
+static INSN_REGPARM void thumb43_2(uint32_t opcode)
{
int dest = opcode & 7;
reg[dest].I &= (~reg[(opcode >> 3) & 7].I);
@@ -1349,7 +1349,7 @@
}
// MVN Rd, Rs
-static INSN_REGPARM void thumb43_3(u32 opcode)
+static INSN_REGPARM void thumb43_3(uint32_t opcode)
{
int dest = opcode & 7;
reg[dest].I = ~reg[(opcode >> 3) & 7].I;
@@ -1360,13 +1360,13 @@
// High-register instructions and BX //////////////////////////////////////
// ADD Rd, Hs
-static INSN_REGPARM void thumb44_1(u32 opcode)
+static INSN_REGPARM void thumb44_1(uint32_t opcode)
{
reg[opcode&7].I += reg[((opcode>>3)&7)+8].I;
}
// ADD Hd, Rs
-static INSN_REGPARM void thumb44_2(u32 opcode)
+static INSN_REGPARM void thumb44_2(uint32_t opcode)
{
reg[(opcode&7)+8].I += reg[(opcode>>3)&7].I;
if((opcode&7) == 7) {
@@ -1380,7 +1380,7 @@
}
// ADD Hd, Hs
-static INSN_REGPARM void thumb44_3(u32 opcode)
+static INSN_REGPARM void thumb44_3(uint32_t opcode)
{
reg[(opcode&7)+8].I += reg[((opcode>>3)&7)+8].I;
if((opcode&7) == 7) {
@@ -1394,45 +1394,45 @@
}
// CMP Rd, Hs
-static INSN_REGPARM void thumb45_1(u32 opcode)
+static INSN_REGPARM void thumb45_1(uint32_t opcode)
{
int dest = opcode & 7;
- u32 value = reg[((opcode>>3)&7)+8].I;
+ uint32_t value = reg[((opcode>>3)&7)+8].I;
CMP_RD_RS;
}
// CMP Hd, Rs
-static INSN_REGPARM void thumb45_2(u32 opcode)
+static INSN_REGPARM void thumb45_2(uint32_t opcode)
{
int dest = (opcode & 7) + 8;
- u32 value = reg[(opcode>>3)&7].I;
+ uint32_t value = reg[(opcode>>3)&7].I;
CMP_RD_RS;
}
// CMP Hd, Hs
-static INSN_REGPARM void thumb45_3(u32 opcode)
+static INSN_REGPARM void thumb45_3(uint32_t opcode)
{
int dest = (opcode & 7) + 8;
- u32 value = reg[((opcode>>3)&7)+8].I;
+ uint32_t value = reg[((opcode>>3)&7)+8].I;
CMP_RD_RS;
}
// MOV Rd, Rs
-static INSN_REGPARM void thumb46_0(u32 opcode)
+static INSN_REGPARM void thumb46_0(uint32_t opcode)
{
reg[opcode&7].I = reg[((opcode>>3)&7)].I;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
}
// MOV Rd, Hs
-static INSN_REGPARM void thumb46_1(u32 opcode)
+static INSN_REGPARM void thumb46_1(uint32_t opcode)
{
reg[opcode&7].I = reg[((opcode>>3)&7)+8].I;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
}
// MOV Hd, Rs
-static INSN_REGPARM void thumb46_2(u32 opcode)
+static INSN_REGPARM void thumb46_2(uint32_t opcode)
{
reg[(opcode&7)+8].I = reg[(opcode>>3)&7].I;
if((opcode&7) == 7) {
@@ -1447,7 +1447,7 @@
}
// MOV Hd, Hs
-static INSN_REGPARM void thumb46_3(u32 opcode)
+static INSN_REGPARM void thumb46_3(uint32_t opcode)
{
reg[(opcode&7)+8].I = reg[((opcode>>3)&7)+8].I;
if((opcode&7) == 7) {
@@ -1463,7 +1463,7 @@
// BX Rs
-static INSN_REGPARM void thumb47(u32 opcode)
+static INSN_REGPARM void thumb47(uint32_t opcode)
{
int base = (opcode >> 3) & 15;
busPrefetchCount=0;
@@ -1489,175 +1489,175 @@
// Load/store instructions ////////////////////////////////////////////////
// LDR R0~R7,[PC, #Imm]
-static INSN_REGPARM void thumb48(u32 opcode)
-{
- u8 regist = (opcode >> 8) & 7;
+static INSN_REGPARM void thumb48(uint32_t opcode)
+{
+ uint8_t regist = (opcode >> 8) & 7;
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
- u32 address = (reg[15].I & 0xFFFFFFFC) + ((opcode & 0xFF) << 2);
+ uint32_t address = (reg[15].I & 0xFFFFFFFC) + ((opcode & 0xFF) << 2);
reg[regist].I = CPUReadMemoryQuick(address);
busPrefetchCount=0;
clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
}
// STR Rd, [Rs, Rn]
-static INSN_REGPARM void thumb50(u32 opcode)
+static INSN_REGPARM void thumb50(uint32_t opcode)
{
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
- u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
+ uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
CPUWriteMemory(address, reg[opcode & 7].I);
clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2;
}
// STRH Rd, [Rs, Rn]
-static INSN_REGPARM void thumb52(u32 opcode)
+static INSN_REGPARM void thumb52(uint32_t opcode)
{
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
- u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
+ uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
CPUWriteHalfWord(address, reg[opcode&7].W.W0);
clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2;
}
// STRB Rd, [Rs, Rn]
-static INSN_REGPARM void thumb54(u32 opcode)
+static INSN_REGPARM void thumb54(uint32_t opcode)
{
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
- u32 address = reg[(opcode>>3)&7].I + reg[(opcode >>6)&7].I;
+ uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode >>6)&7].I;
CPUWriteByte(address, reg[opcode & 7].B.B0);
clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2;
}
// LDSB Rd, [Rs, Rn]
-static INSN_REGPARM void thumb56(u32 opcode)
+static INSN_REGPARM void thumb56(uint32_t opcode)
{
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
- u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
- reg[opcode&7].I = (s8)CPUReadByte(address);
+ uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
+ reg[opcode&7].I = (int8_t)CPUReadByte(address);
clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
}
// LDR Rd, [Rs, Rn]
-static INSN_REGPARM void thumb58(u32 opcode)
+static INSN_REGPARM void thumb58(uint32_t opcode)
{
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
- u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
+ uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
reg[opcode&7].I = CPUReadMemory(address);
clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
}
// LDRH Rd, [Rs, Rn]
-static INSN_REGPARM void thumb5A(u32 opcode)
+static INSN_REGPARM void thumb5A(uint32_t opcode)
{
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
- u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
+ uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
reg[opcode&7].I = CPUReadHalfWord(address);
clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
}
// LDRB Rd, [Rs, Rn]
-static INSN_REGPARM void thumb5C(u32 opcode)
+static INSN_REGPARM void thumb5C(uint32_t opcode)
{
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
- u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
+ uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
reg[opcode&7].I = CPUReadByte(address);
clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
}
// LDSH Rd, [Rs, Rn]
-static INSN_REGPARM void thumb5E(u32 opcode)
+static INSN_REGPARM void thumb5E(uint32_t opcode)
{
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
- u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
- reg[opcode&7].I = (u32)CPUReadHalfWordSigned(address);
+ uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
+ reg[opcode&7].I = (uint32_t)CPUReadHalfWordSigned(address);
clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
}
// STR Rd, [Rs, #Imm]
-static INSN_REGPARM void thumb60(u32 opcode)
+static INSN_REGPARM void thumb60(uint32_t opcode)
{
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
- u32 address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<2);
+ uint32_t address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<2);
CPUWriteMemory(address, reg[opcode&7].I);
clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2;
}
// LDR Rd, [Rs, #Imm]
-static INSN_REGPARM void thumb68(u32 opcode)
+static INSN_REGPARM void thumb68(uint32_t opcode)
{
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
- u32 address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<2);
+ uint32_t address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<2);
reg[opcode&7].I = CPUReadMemory(address);
clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
}
// STRB Rd, [Rs, #Imm]
-static INSN_REGPARM void thumb70(u32 opcode)
+static INSN_REGPARM void thumb70(uint32_t opcode)
{
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
- u32 address = reg[(opcode>>3)&7].I + (((opcode>>6)&31));
+ uint32_t address = reg[(opcode>>3)&7].I + (((opcode>>6)&31));
CPUWriteByte(address, reg[opcode&7].B.B0);
clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2;
}
// LDRB Rd, [Rs, #Imm]
-static INSN_REGPARM void thumb78(u32 opcode)
+static INSN_REGPARM void thumb78(uint32_t opcode)
{
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
- u32 address = reg[(opcode>>3)&7].I + (((opcode>>6)&31));
+ uint32_t address = reg[(opcode>>3)&7].I + (((opcode>>6)&31));
reg[opcode&7].I = CPUReadByte(address);
clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
}
// STRH Rd, [Rs, #Imm]
-static INSN_REGPARM void thumb80(u32 opcode)
+static INSN_REGPARM void thumb80(uint32_t opcode)
{
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
- u32 address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<1);
+ uint32_t address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<1);
CPUWriteHalfWord(address, reg[opcode&7].W.W0);
clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2;
}
// LDRH Rd, [Rs, #Imm]
-static INSN_REGPARM void thumb88(u32 opcode)
+static INSN_REGPARM void thumb88(uint32_t opcode)
{
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
- u32 address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<1);
+ uint32_t address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<1);
reg[opcode&7].I = CPUReadHalfWord(address);
clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
}
// STR R0~R7, [SP, #Imm]
-static INSN_REGPARM void thumb90(u32 opcode)
-{
- u8 regist = (opcode >> 8) & 7;
+static INSN_REGPARM void thumb90(uint32_t opcode)
+{
+ uint8_t regist = (opcode >> 8) & 7;
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
- u32 address = reg[13].I + ((opcode&255)<<2);
+ uint32_t address = reg[13].I + ((opcode&255)<<2);
CPUWriteMemory(address, reg[regist].I);
clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2;
}
// LDR R0~R7, [SP, #Imm]
-static INSN_REGPARM void thumb98(u32 opcode)
-{
- u8 regist = (opcode >> 8) & 7;
+static INSN_REGPARM void thumb98(uint32_t opcode)
+{
+ uint8_t regist = (opcode >> 8) & 7;
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
- u32 address = reg[13].I + ((opcode&255)<<2);
+ uint32_t address = reg[13].I + ((opcode&255)<<2);
reg[regist].I = CPUReadMemoryQuick(address);
clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
}
@@ -1665,23 +1665,23 @@
// PC/stack-related ///////////////////////////////////////////////////////
// ADD R0~R7, PC, Imm
-static INSN_REGPARM void thumbA0(u32 opcode)
-{
- u8 regist = (opcode >> 8) & 7;
+static INSN_REGPARM void thumbA0(uint32_t opcode)
+{
+ uint8_t regist = (opcode >> 8) & 7;
reg[regist].I = (reg[15].I & 0xFFFFFFFC) + ((opcode&255)<<2);
clockTicks = 1 + codeTicksAccess16(armNextPC);
}
// ADD R0~R7, SP, Imm
-static INSN_REGPARM void thumbA8(u32 opcode)
-{
- u8 regist = (opcode >> 8) & 7;
+static INSN_REGPARM void thumbA8(uint32_t opcode)
+{
+ uint8_t regist = (opcode >> 8) & 7;
reg[regist].I = reg[13].I + ((opcode&255)<<2);
clockTicks = 1 + codeTicksAccess16(armNextPC);
}
// ADD SP, Imm
-static INSN_REGPARM void thumbB0(u32 opcode)
+static INSN_REGPARM void thumbB0(uint32_t opcode)
{
int offset = (opcode & 127) << 2;
if(opcode & 0x80)
@@ -1717,13 +1717,13 @@
}
// PUSH {Rlist}
-static INSN_REGPARM void thumbB4(u32 opcode)
+static INSN_REGPARM void thumbB4(uint32_t opcode)
{
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
int count = 0;
- u32 temp = reg[13].I - 4 * cpuBitsSet[opcode & 0xff];
- u32 address = temp & 0xFFFFFFFC;
+ uint32_t temp = reg[13].I - 4 * cpuBitsSet[opcode & 0xff];
+ uint32_t address = temp & 0xFFFFFFFC;
PUSH_REG(1, 0);
PUSH_REG(2, 1);
PUSH_REG(4, 2);
@@ -1737,13 +1737,13 @@
}
// PUSH {Rlist, LR}
-static INSN_REGPARM void thumbB5(u32 opcode)
+static INSN_REGPARM void thumbB5(uint32_t opcode)
{
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
int count = 0;
- u32 temp = reg[13].I - 4 - 4 * cpuBitsSet[opcode & 0xff];
- u32 address = temp & 0xFFFFFFFC;
+ uint32_t temp = reg[13].I - 4 - 4 * cpuBitsSet[opcode & 0xff];
+ uint32_t address = temp & 0xFFFFFFFC;
PUSH_REG(1, 0);
PUSH_REG(2, 1);
PUSH_REG(4, 2);
@@ -1758,13 +1758,13 @@
}
// POP {Rlist}
-static INSN_REGPARM void thumbBC(u32 opcode)
+static INSN_REGPARM void thumbBC(uint32_t opcode)
{
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
int count = 0;
- u32 address = reg[13].I & 0xFFFFFFFC;
- u32 temp = reg[13].I + 4*cpuBitsSet[opcode & 0xFF];
+ uint32_t address = reg[13].I & 0xFFFFFFFC;
+ uint32_t temp = reg[13].I + 4*cpuBitsSet[opcode & 0xFF];
POP_REG(1, 0);
POP_REG(2, 1);
POP_REG(4, 2);
@@ -1778,13 +1778,13 @@
}
// POP {Rlist, PC}
-static INSN_REGPARM void thumbBD(u32 opcode)
+static INSN_REGPARM void thumbBD(uint32_t opcode)
{
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
int count = 0;
- u32 address = reg[13].I & 0xFFFFFFFC;
- u32 temp = reg[13].I + 4 + 4*cpuBitsSet[opcode & 0xFF];
+ uint32_t address = reg[13].I & 0xFFFFFFFC;
+ uint32_t temp = reg[13].I + 4 + 4*cpuBitsSet[opcode & 0xFF];
POP_REG(1, 0);
POP_REG(2, 1);
POP_REG(4, 2);
@@ -1836,13 +1836,13 @@
}
// STM R0~7!, {Rlist}
-static INSN_REGPARM void thumbC0(u32 opcode)
-{
- u8 regist = (opcode >> 8) & 7;
+static INSN_REGPARM void thumbC0(uint32_t opcode)
+{
+ uint8_t regist = (opcode >> 8) & 7;
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
- u32 address = reg[regist].I & 0xFFFFFFFC;
- u32 temp = reg[regist].I + 4*cpuBitsSet[opcode & 0xff];
+ uint32_t address = reg[regist].I & 0xFFFFFFFC;
+ uint32_t temp = reg[regist].I + 4*cpuBitsSet[opcode & 0xff];
int count = 0;
// store
THUMB_STM_REG(1, 0, regist);
@@ -1857,13 +1857,13 @@
}
// LDM R0~R7!, {Rlist}
-static INSN_REGPARM void thumbC8(u32 opcode)
-{
- u8 regist = (opcode >> 8) & 7;
+static INSN_REGPARM void thumbC8(uint32_t opcode)
+{
+ uint8_t regist = (opcode >> 8) & 7;
if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable;
- u32 address = reg[regist].I & 0xFFFFFFFC;
- u32 temp = reg[regist].I + 4*cpuBitsSet[opcode & 0xFF];
+ uint32_t address = reg[regist].I & 0xFFFFFFFC;
+ uint32_t temp = reg[regist].I + 4*cpuBitsSet[opcode & 0xFF];
int count = 0;
// load
THUMB_LDM_REG(1, 0);
@@ -1882,12 +1882,12 @@
// Conditional branches ///////////////////////////////////////////////////
// BEQ offset
-static INSN_REGPARM void thumbD0(u32 opcode)
+static INSN_REGPARM void thumbD0(uint32_t opcode)
{
UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(Z_FLAG) {
- reg[15].I += ((s8)(opcode & 0xFF)) << 1;
+ reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I;
reg[15].I += 2;
THUMB_PREFETCH;
@@ -1897,12 +1897,12 @@
}
// BNE offset
-static INSN_REGPARM void thumbD1(u32 opcode)
+static INSN_REGPARM void thumbD1(uint32_t opcode)
{
UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(!Z_FLAG) {
- reg[15].I += ((s8)(opcode & 0xFF)) << 1;
+ reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I;
reg[15].I += 2;
THUMB_PREFETCH;
@@ -1912,12 +1912,12 @@
}
// BCS offset
-static INSN_REGPARM void thumbD2(u32 opcode)
+static INSN_REGPARM void thumbD2(uint32_t opcode)
{
UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(C_FLAG) {
- reg[15].I += ((s8)(opcode & 0xFF)) << 1;
+ reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I;
reg[15].I += 2;
THUMB_PREFETCH;
@@ -1927,12 +1927,12 @@
}
// BCC offset
-static INSN_REGPARM void thumbD3(u32 opcode)
+static INSN_REGPARM void thumbD3(uint32_t opcode)
{
UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(!C_FLAG) {
- reg[15].I += ((s8)(opcode & 0xFF)) << 1;
+ reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I;
reg[15].I += 2;
THUMB_PREFETCH;
@@ -1942,12 +1942,12 @@
}
// BMI offset
-static INSN_REGPARM void thumbD4(u32 opcode)
+static INSN_REGPARM void thumbD4(uint32_t opcode)
{
UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(N_FLAG) {
- reg[15].I += ((s8)(opcode & 0xFF)) << 1;
+ reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I;
reg[15].I += 2;
THUMB_PREFETCH;
@@ -1957,12 +1957,12 @@
}
// BPL offset
-static INSN_REGPARM void thumbD5(u32 opcode)
+static INSN_REGPARM void thumbD5(uint32_t opcode)
{
UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(!N_FLAG) {
- reg[15].I += ((s8)(opcode & 0xFF)) << 1;
+ reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I;
reg[15].I += 2;
THUMB_PREFETCH;
@@ -1972,12 +1972,12 @@
}
// BVS offset
-static INSN_REGPARM void thumbD6(u32 opcode)
+static INSN_REGPARM void thumbD6(uint32_t opcode)
{
UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(V_FLAG) {
- reg[15].I += ((s8)(opcode & 0xFF)) << 1;
+ reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I;
reg[15].I += 2;
THUMB_PREFETCH;
@@ -1987,12 +1987,12 @@
}
// BVC offset
-static INSN_REGPARM void thumbD7(u32 opcode)
+static INSN_REGPARM void thumbD7(uint32_t opcode)
{
UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(!V_FLAG) {
- reg[15].I += ((s8)(opcode & 0xFF)) << 1;
+ reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I;
reg[15].I += 2;
THUMB_PREFETCH;
@@ -2002,12 +2002,12 @@
}
// BHI offset
-static INSN_REGPARM void thumbD8(u32 opcode)
+static INSN_REGPARM void thumbD8(uint32_t opcode)
{
UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(C_FLAG && !Z_FLAG) {
- reg[15].I += ((s8)(opcode & 0xFF)) << 1;
+ reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I;
reg[15].I += 2;
THUMB_PREFETCH;
@@ -2017,12 +2017,12 @@
}
// BLS offset
-static INSN_REGPARM void thumbD9(u32 opcode)
+static INSN_REGPARM void thumbD9(uint32_t opcode)
{
UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(!C_FLAG || Z_FLAG) {
- reg[15].I += ((s8)(opcode & 0xFF)) << 1;
+ reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I;
reg[15].I += 2;
THUMB_PREFETCH;
@@ -2032,12 +2032,12 @@
}
// BGE offset
-static INSN_REGPARM void thumbDA(u32 opcode)
+static INSN_REGPARM void thumbDA(uint32_t opcode)
{
UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(N_FLAG == V_FLAG) {
- reg[15].I += ((s8)(opcode & 0xFF)) << 1;
+ reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I;
reg[15].I += 2;
THUMB_PREFETCH;
@@ -2047,12 +2047,12 @@
}
// BLT offset
-static INSN_REGPARM void thumbDB(u32 opcode)
+static INSN_REGPARM void thumbDB(uint32_t opcode)
{
UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(N_FLAG != V_FLAG) {
- reg[15].I += ((s8)(opcode & 0xFF)) << 1;
+ reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I;
reg[15].I += 2;
THUMB_PREFETCH;
@@ -2062,12 +2062,12 @@
}
// BGT offset
-static INSN_REGPARM void thumbDC(u32 opcode)
+static INSN_REGPARM void thumbDC(uint32_t opcode)
{
UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(!Z_FLAG && (N_FLAG == V_FLAG)) {
- reg[15].I += ((s8)(opcode & 0xFF)) << 1;
+ reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I;
reg[15].I += 2;
THUMB_PREFETCH;
@@ -2077,12 +2077,12 @@
}
// BLE offset
-static INSN_REGPARM void thumbDD(u32 opcode)
+static INSN_REGPARM void thumbDD(uint32_t opcode)
{
UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC);
if(Z_FLAG || (N_FLAG != V_FLAG)) {
- reg[15].I += ((s8)(opcode & 0xFF)) << 1;
+ reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I;
reg[15].I += 2;
THUMB_PREFETCH;
@@ -2094,9 +2094,9 @@
// SWI, B, BL /////////////////////////////////////////////////////////////
// SWI #comment
-static INSN_REGPARM void thumbDF(u32 opcode)
-{
- u32 address = 0;
+static INSN_REGPARM void thumbDF(uint32_t opcode)
+{
+ uint32_t address = 0;
//clockTicks = codeTicksAccessSeq16(address)*2 + codeTicksAccess16(address)+3;
clockTicks = 3;
busPrefetchCount=0;
@@ -2104,7 +2104,7 @@
}
// B offset
-static INSN_REGPARM void thumbE0(u32 opcode)
+static INSN_REGPARM void thumbE0(uint32_t opcode)
{
int offset = (opcode & 0x3FF) << 1;
if(opcode & 0x0400)
@@ -2118,7 +2118,7 @@
}
// BLL #offset (forward)
-static INSN_REGPARM void thumbF0(u32 opcode)
+static INSN_REGPARM void thumbF0(uint32_t opcode)
{
int offset = (opcode & 0x7FF);
reg[14].I = reg[15].I + (offset << 12);
@@ -2126,7 +2126,7 @@
}
// BLL #offset (backward)
-static INSN_REGPARM void thumbF4(u32 opcode)
+static INSN_REGPARM void thumbF4(uint32_t opcode)
{
int offset = (opcode & 0x7FF);
reg[14].I = reg[15].I + ((offset << 12) | 0xFF800000);
@@ -2134,10 +2134,10 @@
}
// BLH #offset
-static INSN_REGPARM void thumbF8(u32 opcode)
+static INSN_REGPARM void thumbF8(uint32_t opcode)
{
int offset = (opcode & 0x7FF);
- u32 temp = reg[15].I-2;
+ uint32_t temp = reg[15].I-2;
reg[15].I = (reg[14].I + (offset<<1))&0xFFFFFFFE;
armNextPC = reg[15].I;
reg[15].I += 2;
@@ -2149,7 +2149,7 @@
// Instruction table //////////////////////////////////////////////////////
-typedef INSN_REGPARM void (*insnfunc_t)(u32 opcode);
+typedef INSN_REGPARM void (*insnfunc_t)(uint32_t opcode);
#define thumbUI thumbUnknownInsn
#ifdef BKPT_SUPPORT
#define thumbBP thumbBreakpoint
@@ -2299,14 +2299,14 @@
//if ((armNextPC & 0x0803FFFF) == 0x08020000)
// busPrefetchCount=0x100;
- u32 opcode = cpuPrefetch[0];
+ uint32_t opcode = cpuPrefetch[0];
cpuPrefetch[0] = cpuPrefetch[1];
busPrefetch = false;
if (busPrefetchCount & 0xFFFFFF00)
busPrefetchCount = 0x100 | (busPrefetchCount & 0xFF);
clockTicks = 0;
- u32 oldArmNextPC = armNextPC;
+ uint32_t oldArmNextPC = armNextPC;
#ifndef FINAL_VERSION
if(armNextPC == stop) {
armNextPC++;
--- a/src/in_gsf/vbam/gba/GBA.cpp
+++ b/src/in_gsf/vbam/gba/GBA.cpp
@@ -22,7 +22,7 @@
//#include "agbprint.h"
//#include "GBALink.h"
-extern int mapgsf(u8* a, int l, int &s);
+extern int mapgsf(uint8_t* a, int l, int &s);
#ifdef PROFILING
#include "prof/prof.h"
@@ -37,14 +37,14 @@
int SWITicks = 0;
int IRQTicks = 0;
-u32 mastercode = 0;
+uint32_t mastercode = 0;
int layerEnableDelay = 0;
bool busPrefetch = false;
bool busPrefetchEnable = false;
-u32 busPrefetchCount = 0;
+uint32_t busPrefetchCount = 0;
int cpuDmaTicksToUpdate = 0;
int cpuDmaCount = 0;
-u32 cpuDmaLast = 0;
+uint32_t cpuDmaLast = 0;
int dummyAddress = 0;
bool cpuBreakLoop = false;
@@ -60,7 +60,7 @@
bool cpuEEPROMEnabled = true;
bool cpuEEPROMSensorEnabled = false;
-u32 cpuPrefetch[2];
+uint32_t cpuPrefetch[2];
int cpuTotalTicks = 0;
#ifdef PROFILING
@@ -70,51 +70,51 @@
#endif
#ifdef BKPT_SUPPORT
-u8 freezeWorkRAM[0x40000];
-u8 freezeInternalRAM[0x8000];
-u8 freezeVRAM[0x18000];
-u8 freezePRAM[0x400];
-u8 freezeOAM[0x400];
+uint8_t freezeWorkRAM[0x40000];
+uint8_t freezeInternalRAM[0x8000];
+uint8_t freezeVRAM[0x18000];
+uint8_t freezePRAM[0x400];
+uint8_t freezeOAM[0x400];
bool debugger_last;
#endif
int lcdTicks = (useBios && !skipBios) ? 1008 : 208;
-u8 timerOnOffDelay = 0;
-u16 timer0Value = 0;
+uint8_t timerOnOffDelay = 0;
+uint16_t timer0Value = 0;
bool timer0On = false;
int timer0Ticks = 0;
int timer0Reload = 0;
int timer0ClockReload = 0;
-u16 timer1Value = 0;
+uint16_t timer1Value = 0;
bool timer1On = false;
int timer1Ticks = 0;
int timer1Reload = 0;
int timer1ClockReload = 0;
-u16 timer2Value = 0;
+uint16_t timer2Value = 0;
bool timer2On = false;
int timer2Ticks = 0;
int timer2Reload = 0;
int timer2ClockReload = 0;
-u16 timer3Value = 0;
+uint16_t timer3Value = 0;
bool timer3On = false;
int timer3Ticks = 0;
int timer3Reload = 0;
int timer3ClockReload = 0;
-u32 dma0Source = 0;
-u32 dma0Dest = 0;
-u32 dma1Source = 0;
-u32 dma1Dest = 0;
-u32 dma2Source = 0;
-u32 dma2Dest = 0;
-u32 dma3Source = 0;
-u32 dma3Dest = 0;
+uint32_t dma0Source = 0;
+uint32_t dma0Dest = 0;
+uint32_t dma1Source = 0;
+uint32_t dma1Dest = 0;
+uint32_t dma2Source = 0;
+uint32_t dma2Dest = 0;
+uint32_t dma3Source = 0;
+uint32_t dma3Dest = 0;
//void (*cpuSaveGameFunc)(u32,u8) = /*flashSaveDecide*/0;
//void (*renderLine)() = /*mode0RenderLine*/0;
bool fxOn = false;
bool windowOn = false;
int frameCount = 0;
char buffer[1024];
-u32 lastTime = 0;
+uint32_t lastTime = 0;
int count = 0;
int capture = 0;
@@ -128,23 +128,23 @@
10
};
-const u32 objTilesAddress [3] = {0x010000, 0x014000, 0x014000};
-const u8 gamepakRamWaitState[4] = { 4, 3, 2, 8 };
-const u8 gamepakWaitState[4] = { 4, 3, 2, 8 };
-const u8 gamepakWaitState0[2] = { 2, 1 };
-const u8 gamepakWaitState1[2] = { 4, 1 };
-const u8 gamepakWaitState2[2] = { 8, 1 };
+const uint32_t objTilesAddress [3] = {0x010000, 0x014000, 0x014000};
+const uint8_t gamepakRamWaitState[4] = { 4, 3, 2, 8 };
+const uint8_t gamepakWaitState[4] = { 4, 3, 2, 8 };
+const uint8_t gamepakWaitState0[2] = { 2, 1 };
+const uint8_t gamepakWaitState1[2] = { 4, 1 };
+const uint8_t gamepakWaitState2[2] = { 8, 1 };
const bool isInRom [16]=
{ false, false, false, false, false, false, false, false,
true, true, true, true, true, true, false, false };
-u8 memoryWait[16] =
+uint8_t memoryWait[16] =
{ 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4, 0 };
-u8 memoryWait32[16] =
+uint8_t memoryWait32[16] =
{ 0, 0, 5, 0, 0, 1, 1, 0, 7, 7, 9, 9, 13, 13, 4, 0 };
-u8 memoryWaitSeq[16] =
+uint8_t memoryWaitSeq[16] =
{ 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4, 0 };
-u8 memoryWaitSeq32[16] =
+uint8_t memoryWaitSeq32[16] =
{ 0, 0, 5, 0, 0, 1, 1, 0, 5, 5, 9, 9, 17, 17, 4, 0 };
// The videoMemoryWait constants are used to add some waitstates
@@ -155,13 +155,13 @@
// {0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0};
-u8 biosProtected[4];
+uint8_t biosProtected[4];
#ifdef WORDS_BIGENDIAN
bool cpuBiosSwapped = false;
#endif
-u32 myROM[] = {
+uint32_t myROM[] = {
0xEA000006,
0xEA000093,
0xEA000006,
@@ -546,10 +546,10 @@
}
}*/
-extern u32 line0[240];
-extern u32 line1[240];
-extern u32 line2[240];
-extern u32 line3[240];
+/*extern uint32_t line0[240];
+extern uint32_t line1[240];
+extern uint32_t line2[240];
+extern uint32_t line3[240];
#define CLEAR_ARRAY(a) \
{\
@@ -557,7 +557,7 @@
for(int i = 0; i < 240; i++) {\
*array++ = 0x80000000;\
}\
- }\
+ }\*/
/*void CPUUpdateRenderBuffers(bool force)
{
@@ -1339,13 +1339,13 @@
//systemSaveUpdateCounter = SYSTEM_SAVE_NOT_UPDATED;
- rom = (u8 *)malloc(0x2000000);
+ rom = (uint8_t *)malloc(0x2000000);
if(rom == NULL) {
/*systemMessage(MSG_OUT_OF_MEMORY, N_("Failed to allocate memory for %s"),
"ROM");*/
return 0;
}
- workRAM = (u8 *)calloc(1, 0x40000);
+ workRAM = (uint8_t *)calloc(1, 0x40000);
if(workRAM == NULL) {
/*systemMessage(MSG_OUT_OF_MEMORY, N_("Failed to allocate memory for %s"),
"WRAM");*/
@@ -1395,56 +1395,56 @@
else
mapgsf(rom, 0x2000000,romSize);
- u16 *temp = (u16 *)(rom+((romSize+1)&~1));
+ uint16_t *temp = (uint16_t *)(rom+((romSize+1)&~1));
int i;
for(i = (romSize+1)&~1; i < 0x2000000; i+=2) {
WRITE16LE(temp, (i >> 1) & 0xFFFF);
temp++;
}
- bios = (u8 *)calloc(1,0x4000);
+ bios = (uint8_t *)calloc(1,0x4000);
if(bios == NULL) {
/*systemMessage(MSG_OUT_OF_MEMORY, N_("Failed to allocate memory for %s"),
"BIOS");*/
CPUCleanUp();
return 0;
}
- internalRAM = (u8 *)calloc(1,0x8000);
+ internalRAM = (uint8_t *)calloc(1,0x8000);
if(internalRAM == NULL) {
/*systemMessage(MSG_OUT_OF_MEMORY, N_("Failed to allocate memory for %s"),
"IRAM");*/
CPUCleanUp();
return 0;
}
- paletteRAM = (u8 *)calloc(1,0x400);
+ paletteRAM = (uint8_t *)calloc(1,0x400);
if(paletteRAM == NULL) {
/*systemMessage(MSG_OUT_OF_MEMORY, N_("Failed to allocate memory for %s"),
"PRAM");*/
CPUCleanUp();
return 0;
}
- vram = (u8 *)calloc(1, 0x20000);
+ vram = (uint8_t *)calloc(1, 0x20000);
if(vram == NULL) {
/*systemMessage(MSG_OUT_OF_MEMORY, N_("Failed to allocate memory for %s"),
"VRAM");*/
CPUCleanUp();
return 0;
}
- oam = (u8 *)calloc(1, 0x400);
+ oam = (uint8_t *)calloc(1, 0x400);
if(oam == NULL) {
/*systemMessage(MSG_OUT_OF_MEMORY, N_("Failed to allocate memory for %s"),
"OAM");*/
CPUCleanUp();
return 0;
}
- pix = (u8 *)calloc(1, 4 * 241 * 162);
+ pix = (uint8_t *)calloc(1, 4 * 241 * 162);
if(pix == NULL) {
/*systemMessage(MSG_OUT_OF_MEMORY, N_("Failed to allocate memory for %s"),
"PIX");*/
CPUCleanUp();
return 0;
}
- ioMem = (u8 *)calloc(1, 0x400);
+ ioMem = (uint8_t *)calloc(1, 0x400);
if(ioMem == NULL) {
/*systemMessage(MSG_OUT_OF_MEMORY, N_("Failed to allocate memory for %s"),
"IO");*/
@@ -1462,8 +1462,8 @@
void doMirroring (bool b)
{
- u32 mirroredRomSize = (((romSize)>>20) & 0x3F)<<20;
- u32 mirroredRomAddress = romSize;
+ uint32_t mirroredRomSize = (((romSize)>>20) & 0x3F)<<20;
+ uint32_t mirroredRomAddress = romSize;
if ((mirroredRomSize <=0x800000) && (b))
{
mirroredRomAddress = mirroredRomSize;
@@ -1471,7 +1471,7 @@
mirroredRomSize=0x100000;
while (mirroredRomAddress<0x01000000)
{
- memcpy ((u16 *)(rom+mirroredRomAddress), (u16 *)(rom), mirroredRomSize);
+ memcpy ((uint16_t *)(rom+mirroredRomAddress), (uint16_t *)(rom), mirroredRomSize);
mirroredRomAddress+=mirroredRomSize;
}
}
@@ -1540,7 +1540,7 @@
void CPUUpdateCPSR()
{
- u32 CPSR = reg[16].I & 0x40;
+ uint32_t CPSR = reg[16].I & 0x40;
if(N_FLAG)
CPSR |= 0x80000000;
if(Z_FLAG)
@@ -1559,7 +1559,7 @@
void CPUUpdateFlags(bool breakLoop)
{
- u32 CPSR = reg[16].I;
+ uint32_t CPSR = reg[16].I;
N_FLAG = (CPSR & 0x80000000) ? true: false;
Z_FLAG = (CPSR & 0x40000000) ? true: false;
@@ -1579,16 +1579,16 @@
}
#ifdef WORDS_BIGENDIAN
-static void CPUSwap(volatile u32 *a, volatile u32 *b)
-{
- volatile u32 c = *b;
+static void CPUSwap(volatile uint32_t *a, volatile uint32_t *b)
+{
+ volatile uint32_t c = *b;
*b = *a;
*a = c;
}
#else
-static void CPUSwap(u32 *a, u32 *b)
-{
- u32 c = *b;
+static void CPUSwap(uint32_t *a, uint32_t *b)
+{
+ uint32_t c = *b;
*b = *a;
*a = c;
}
@@ -1640,8 +1640,8 @@
break;
}
- u32 CPSR = reg[16].I;
- u32 SPSR = reg[17].I;
+ uint32_t CPSR = reg[16].I;
+ uint32_t SPSR = reg[17].I;
switch(mode) {
case 0x10:
@@ -1715,7 +1715,7 @@
void CPUUndefinedException()
{
- u32 PC = reg[15].I;
+ uint32_t PC = reg[15].I;
bool savedArmState = armState;
CPUSwitchMode(0x1b, true, false);
reg[14].I = PC - (savedArmState ? 4 : 2);
@@ -1729,7 +1729,7 @@
void CPUSoftwareInterrupt()
{
- u32 PC = reg[15].I;
+ uint32_t PC = reg[15].I;
bool savedArmState = armState;
CPUSwitchMode(0x13, true, false);
reg[14].I = PC - (savedArmState ? 4 : 2);
@@ -1930,7 +1930,7 @@
break;
case 0x11:
{
- u32 len = CPUReadMemory(reg[0].I) >> 8;
+ uint32_t len = CPUReadMemory(reg[0].I) >> 8;
if(!(((reg[0].I & 0xe000000) == 0) ||
((reg[0].I + (len & 0x1fffff)) & 0xe000000) == 0))
SWITicks = (9 + memoryWait[(reg[1].I>>24) & 0xF]) * len;
@@ -1939,7 +1939,7 @@
break;
case 0x12:
{
- u32 len = CPUReadMemory(reg[0].I) >> 8;
+ uint32_t len = CPUReadMemory(reg[0].I) >> 8;
if(!(((reg[0].I & 0xe000000) == 0) ||
((reg[0].I + (len & 0x1fffff)) & 0xe000000) == 0))
SWITicks = (19 + memoryWait[(reg[1].I>>24) & 0xF]) * len;
@@ -1948,7 +1948,7 @@
break;
case 0x13:
{
- u32 len = CPUReadMemory(reg[0].I) >> 8;
+ uint32_t len = CPUReadMemory(reg[0].I) >> 8;
if(!(((reg[0].I & 0xe000000) == 0) ||
((reg[0].I + (len & 0x1fffff)) & 0xe000000) == 0))
SWITicks = (29 + (memoryWait[(reg[0].I>>24) & 0xF]<<1)) * len;
@@ -1957,7 +1957,7 @@
break;
case 0x14:
{
- u32 len = CPUReadMemory(reg[0].I) >> 8;
+ uint32_t len = CPUReadMemory(reg[0].I) >> 8;
if(!(((reg[0].I & 0xe000000) == 0) ||
((reg[0].I + (len & 0x1fffff)) & 0xe000000) == 0))
SWITicks = (11 + memoryWait[(reg[0].I>>24) & 0xF] +
@@ -1967,7 +1967,7 @@
break;
case 0x15:
{
- u32 len = CPUReadMemory(reg[0].I) >> 9;
+ uint32_t len = CPUReadMemory(reg[0].I) >> 9;
if(!(((reg[0].I & 0xe000000) == 0) ||
((reg[0].I + (len & 0x1fffff)) & 0xe000000) == 0))
SWITicks = (34 + (memoryWait[(reg[0].I>>24) & 0xF] << 1) +
@@ -1977,7 +1977,7 @@
break;
case 0x16:
{
- u32 len = CPUReadMemory(reg[0].I) >> 8;
+ uint32_t len = CPUReadMemory(reg[0].I) >> 8;
if(!(((reg[0].I & 0xe000000) == 0) ||
((reg[0].I + (len & 0x1fffff)) & 0xe000000) == 0))
SWITicks = (13 + memoryWait[(reg[0].I>>24) & 0xF] +
@@ -1987,7 +1987,7 @@
break;
case 0x17:
{
- u32 len = CPUReadMemory(reg[0].I) >> 9;
+ uint32_t len = CPUReadMemory(reg[0].I) >> 9;
if(!(((reg[0].I & 0xe000000) == 0) ||
((reg[0].I + (len & 0x1fffff)) & 0xe000000) == 0))
SWITicks = (39 + (memoryWait[(reg[0].I>>24) & 0xF]<<1) +
@@ -1997,7 +1997,7 @@
break;
case 0x18:
{
- u32 len = CPUReadMemory(reg[0].I) >> 9;
+ uint32_t len = CPUReadMemory(reg[0].I) >> 9;
if(!(((reg[0].I & 0xe000000) == 0) ||
((reg[0].I + (len & 0x1fffff)) & 0xe000000) == 0))
SWITicks = (13 + memoryWait[(reg[0].I>>24) & 0xF] +
@@ -2070,7 +2070,7 @@
}
-void doDMA(u32 &s, u32 &d, u32 si, u32 di, u32 c, int transfer32)
+void doDMA(uint32_t &s, uint32_t &d, uint32_t si, uint32_t di, uint32_t c, int transfer32)
{
int sm = s >> 24;
int dm = d >> 24;
@@ -2154,13 +2154,13 @@
// DMA 0
if((DM0CNT_H & 0x8000) && (dmamask & 1)) {
if(((DM0CNT_H >> 12) & 3) == reason) {
- u32 sourceIncrement = 4;
- u32 destIncrement = 4;
+ uint32_t sourceIncrement = 4;
+ uint32_t destIncrement = 4;
switch((DM0CNT_H >> 7) & 3) {
case 0:
break;
case 1:
- sourceIncrement = (u32)-4;
+ sourceIncrement = (uint32_t)-4;
break;
case 2:
sourceIncrement = 0;
@@ -2170,7 +2170,7 @@
case 0:
break;
case 1:
- destIncrement = (u32)-4;
+ destIncrement = (uint32_t)-4;
break;
case 2:
destIncrement = 0;
@@ -2210,13 +2210,13 @@
// DMA 1
if((DM1CNT_H & 0x8000) && (dmamask & 2)) {
if(((DM1CNT_H >> 12) & 3) == reason) {
- u32 sourceIncrement = 4;
- u32 destIncrement = 4;
+ uint32_t sourceIncrement = 4;
+ uint32_t destIncrement = 4;
switch((DM1CNT_H >> 7) & 3) {
case 0:
break;
case 1:
- sourceIncrement = (u32)-4;
+ sourceIncrement = (uint32_t)-4;
break;
case 2:
sourceIncrement = 0;
@@ -2226,7 +2226,7 @@
case 0:
break;
case 1:
- destIncrement = (u32)-4;
+ destIncrement = (uint32_t)-4;
break;
case 2:
destIncrement = 0;
@@ -2278,13 +2278,13 @@
// DMA 2
if((DM2CNT_H & 0x8000) && (dmamask & 4)) {
if(((DM2CNT_H >> 12) & 3) == reason) {
- u32 sourceIncrement = 4;
- u32 destIncrement = 4;
+ uint32_t sourceIncrement = 4;
+ uint32_t destIncrement = 4;
switch((DM2CNT_H >> 7) & 3) {
case 0:
break;
case 1:
- sourceIncrement = (u32)-4;
+ sourceIncrement = (uint32_t)-4;
break;
case 2:
sourceIncrement = 0;
@@ -2294,7 +2294,7 @@
case 0:
break;
case 1:
- destIncrement = (u32)-4;
+ destIncrement = (uint32_t)-4;
break;
case 2:
destIncrement = 0;
@@ -2347,13 +2347,13 @@
// DMA 3
if((DM3CNT_H & 0x8000) && (dmamask & 8)) {
if(((DM3CNT_H >> 12) & 3) == reason) {
- u32 sourceIncrement = 4;
- u32 destIncrement = 4;
+ uint32_t sourceIncrement = 4;
+ uint32_t destIncrement = 4;
switch((DM3CNT_H >> 7) & 3) {
case 0:
break;
case 1:
- sourceIncrement = (u32)-4;
+ sourceIncrement = (uint32_t)-4;
break;
case 2:
sourceIncrement = 0;
@@ -2363,7 +2363,7 @@
case 0:
break;
case 1:
- destIncrement = (u32)-4;
+ destIncrement = (uint32_t)-4;
break;
case 2:
destIncrement = 0;
@@ -2400,7 +2400,7 @@
}
}
-void CPUUpdateRegister(u32 address, u16 value)
+void CPUUpdateRegister(uint32_t address, uint16_t value)
{
switch(address)
{
@@ -2412,7 +2412,7 @@
}
bool change = (0 != ((DISPCNT ^ value) & 0x80));
bool changeBG = (0 != ((DISPCNT ^ value) & 0x0F00));
- u16 changeBGon = ((~DISPCNT) & value) & 0x0F00; // these layers are being activated
+ uint16_t changeBGon = ((~DISPCNT) & value) & 0x0F00; // these layers are being activated
DISPCNT = (value & 0xFFF7); // bit 3 can only be accessed by the BIOS to enable GBC mode
UPDATE_REG(0x00, DISPCNT);
@@ -2627,8 +2627,8 @@
case 0x7c:
case 0x80:
case 0x84:
- soundEvent(address&0xFF, (u8)(value & 0xFF));
- soundEvent((address&0xFF)+1, (u8)(value>>8));
+ soundEvent(address&0xFF, (uint8_t)(value & 0xFF));
+ soundEvent((address&0xFF)+1, (uint8_t)(value>>8));
break;
case 0x82:
case 0x88:
@@ -3013,8 +3013,8 @@
timerOnOffDelay = 0;
}
-u8 cpuBitsSet[256];
-u8 cpuLowestBitSet[256];
+uint8_t cpuBitsSet[256];
+uint8_t cpuLowestBitSet[256];
void CPUInit(const char *biosFileName, bool useBiosFile)
{
@@ -3105,8 +3105,8 @@
ioReadable[i] = false;
if(romSize < 0x1fe2000) {
- *((u16 *)&rom[0x1fe209c]) = 0xdffa; // SWI 0xFA
- *((u16 *)&rom[0x1fe209e]) = 0x4770; // BX LR
+ *((uint16_t *)&rom[0x1fe209c]) = 0xdffa; // SWI 0xFA
+ *((uint16_t *)&rom[0x1fe209e]) = 0x4770; // BX LR
} else {
//agbPrintEnable(false);
}
@@ -3306,7 +3306,7 @@
//CPUUpdateRenderBuffers(true);
for(int i = 0; i < 256; i++) {
- map[i].address = (u8 *)&dummyAddress;
+ map[i].address = (uint8_t *)&dummyAddress;
map[i].mask = 0;
}
@@ -3415,7 +3415,7 @@
void CPUInterrupt()
{
- u32 PC = reg[15].I;
+ uint32_t PC = reg[15].I;
bool savedState = armState;
CPUSwitchMode(0x12, true, false);
reg[14].I = PC;
@@ -3547,9 +3547,9 @@
CPUCompareVCOUNT();
}
} else {
- int framesToSkip = /*systemFrameSkip*/0;
+ /*int framesToSkip = *//*systemFrameSkip*//*0;
if(speedup)
- framesToSkip = 9; // try 6 FPS during speedup
+ framesToSkip = 9;*/ // try 6 FPS during speedup
if(DISPSTAT & 2) {
// if in H-Blank, leave it and move to drawing mode
@@ -3562,28 +3562,28 @@
count++;
//systemFrame();
- if((count % 10) == 0) {
+ /*if((count % 10) == 0) {
//system10Frames(60);
- }
+ }*/
if(count == 60) {
- u32 time = /*systemGetClock()*/0;
+ /*u32 time = *//*systemGetClock()*//*0;
if(time != lastTime) {
//u32 t = 100000/(time - lastTime);
//systemShowSpeed(t);
} else
//systemShowSpeed(0);
- lastTime = time;
+ lastTime = time;*/
count = 0;
}
- u32 joy = 0;
+ //u32 joy = 0;
// update joystick information
/*if(systemReadJoypads())
// read default joystick
joy = systemReadJoypad(-1);*/
- P1 = 0x03FF ^ (joy & 0x3FF);
+ //P1 = 0x03FF ^ (joy & 0x3FF);
/*if(cpuEEPROMSensorEnabled)
systemUpdateMotionSensor();*/
- UPDATE_REG(0x130, P1);
+ /*UPDATE_REG(0x130, P1);
u16 P1CNT = READ16LE(((u16 *)&ioMem[0x132]));
// this seems wrong, but there are cases where the game
// can enter the stop state without requesting an IRQ from
@@ -3603,18 +3603,18 @@
}
}
- u32 ext = (joy >> 10);
+ u32 ext = (joy >> 10);*/
// If no (m) code is enabled, apply the cheats at each LCDline
/*if((cheatsEnabled) && (mastercode==0))
remainingTicks += cheatsCheckKeys(P1^0x3FF, ext);*/
- speedup = (ext & 1) ? true : false;
+ /*speedup = (ext & 1) ? true : false;
capture = (ext & 2) ? true : false;
if(capture && !capturePrevious) {
captureNumber++;
//systemScreenCapture(captureNumber);
}
- capturePrevious = capture;
+ capturePrevious = capture;*/
DISPSTAT |= 1;
DISPSTAT &= 0xFFFD;
@@ -3624,10 +3624,10 @@
UPDATE_REG(0x202, IF);
}
CPUCheckDMA(1, 0x0f);
- if(frameCount >= framesToSkip) {
+ /*if(frameCount >= framesToSkip) {
//systemDrawScreen();
frameCount = 0;
- } else
+ } else*/
frameCount++;
/*if(systemPauseOnFrame())
ticks = 0;*/
@@ -3637,8 +3637,8 @@
CPUCompareVCOUNT();
} else {
- if(frameCount >= framesToSkip)
- {
+ /*if(frameCount >= framesToSkip)
+ {*/
/*(*renderLine)();
switch(systemColorDepth) {
case 16:
@@ -3738,7 +3738,7 @@
}
break;
}*/
- }
+ /*}*/
// entering H-Blank
DISPSTAT |= 2;
UPDATE_REG(0x04, DISPSTAT);
@@ -3876,7 +3876,7 @@
if(profilSegment) {
profile_segment *seg = profilSegment;
do {
- u16 *b = (u16 *)seg->sbuf;
+ uint16_t *b = (uint16_t *)seg->sbuf;
int pc = ((reg[15].I - seg->s_lowpc) * seg->s_scale)/0x10000;
if(pc >= 0 && pc < seg->ssiz) {
b[pc]++;
--- a/src/in_gsf/vbam/gba/GBA.h
+++ b/src/in_gsf/vbam/gba/GBA.h
@@ -4,7 +4,7 @@
//#include "../System.h"
#include "../common/Types.h"
-#define SAVE_GAME_VERSION_1 1
+/*#define SAVE_GAME_VERSION_1 1
#define SAVE_GAME_VERSION_2 2
#define SAVE_GAME_VERSION_3 3
#define SAVE_GAME_VERSION_4 4
@@ -14,40 +14,40 @@
#define SAVE_GAME_VERSION_8 8
#define SAVE_GAME_VERSION_9 9
#define SAVE_GAME_VERSION_10 10
-#define SAVE_GAME_VERSION SAVE_GAME_VERSION_10
+#define SAVE_GAME_VERSION SAVE_GAME_VERSION_10*/
typedef struct {
- u8 *address;
- u32 mask;
+ uint8_t *address;
+ uint32_t mask;
} memoryMap;
typedef union {
struct {
#ifdef WORDS_BIGENDIAN
- u8 B3;
- u8 B2;
- u8 B1;
- u8 B0;
+ uint8_t B3;
+ uint8_t B2;
+ uint8_t B1;
+ uint8_t B0;
#else
- u8 B0;
- u8 B1;
- u8 B2;
- u8 B3;
+ uint8_t B0;
+ uint8_t B1;
+ uint8_t B2;
+ uint8_t B3;
#endif
} B;
struct {
#ifdef WORDS_BIGENDIAN
- u16 W1;
- u16 W0;
+ uint16_t W1;
+ uint16_t W0;
#else
- u16 W0;
- u16 W1;
+ uint16_t W0;
+ uint16_t W1;
#endif
} W;
#ifdef WORDS_BIGENDIAN
- volatile u32 I;
+ volatile uint32_t I;
#else
- u32 I;
+ uint32_t I;
#endif
} reg_pair;
@@ -56,7 +56,7 @@
#endif
extern reg_pair reg[45];
-extern u8 biosProtected[4];
+extern uint8_t biosProtected[4];
extern bool N_FLAG;
extern bool Z_FLAG;
@@ -68,11 +68,11 @@
//extern void (*cpuSaveGameFunc)(u32,u8);
#ifdef BKPT_SUPPORT
-extern u8 freezeWorkRAM[0x40000];
-extern u8 freezeInternalRAM[0x8000];
-extern u8 freezeVRAM[0x18000];
-extern u8 freezeOAM[0x400];
-extern u8 freezePRAM[0x400];
+extern uint8_t freezeWorkRAM[0x40000];
+extern uint8_t freezeInternalRAM[0x8000];
+extern uint8_t freezeVRAM[0x18000];
+extern uint8_t freezeOAM[0x400];
+extern uint8_t freezePRAM[0x400];
extern bool debugger_last;
extern int oldreg[18];
extern char oldbuffer[10];
@@ -96,7 +96,7 @@
extern bool CPUWriteState(const char *);
extern int CPULoadRom(const char *);
extern void doMirroring(bool);
-extern void CPUUpdateRegister(u32, u16);
+extern void CPUUpdateRegister(uint32_t, uint16_t);
extern void applyTimer ();
extern void CPUInit(const char *,bool);
extern void CPUReset();
--- a/src/in_gsf/vbam/gba/GBAcpu.h
+++ b/src/in_gsf/vbam/gba/GBAcpu.h
@@ -20,7 +20,7 @@
#define UPDATE_REG(address, value)\
{\
- WRITE16LE(((u16 *)&ioMem[address]),value);\
+ WRITE16LE(((uint16_t *)&ioMem[address]),value);\
}\
#define ARM_PREFETCH \
@@ -43,20 +43,20 @@
extern int SWITicks;
-extern u32 mastercode;
+extern uint32_t mastercode;
extern bool busPrefetch;
extern bool busPrefetchEnable;
-extern u32 busPrefetchCount;
+extern uint32_t busPrefetchCount;
extern int cpuNextEvent;
extern bool holdState;
-extern u32 cpuPrefetch[2];
+extern uint32_t cpuPrefetch[2];
extern int cpuTotalTicks;
-extern u8 memoryWait[16];
-extern u8 memoryWait32[16];
-extern u8 memoryWaitSeq[16];
-extern u8 memoryWaitSeq32[16];
-extern u8 cpuBitsSet[256];
-extern u8 cpuLowestBitSet[256];
+extern uint8_t memoryWait[16];
+extern uint8_t memoryWait32[16];
+extern uint8_t memoryWaitSeq[16];
+extern uint8_t memoryWaitSeq32[16];
+extern uint8_t cpuBitsSet[256];
+extern uint8_t cpuLowestBitSet[256];
extern void CPUSwitchMode(int mode, bool saveState, bool breakLoop);
extern void CPUSwitchMode(int mode, bool saveState);
extern void CPUUpdateCPSR();
@@ -68,7 +68,7 @@
// Waitstates when accessing data
-inline int dataTicksAccess16(u32 address) // DATA 8/16bits NON SEQ
+inline int dataTicksAccess16(uint32_t address) // DATA 8/16bits NON SEQ
{
int addr = (address>>24)&15;
int value = memoryWait[addr];
@@ -89,7 +89,7 @@
return value;
}
-inline int dataTicksAccess32(u32 address) // DATA 32bits NON SEQ
+inline int dataTicksAccess32(uint32_t address) // DATA 32bits NON SEQ
{
int addr = (address>>24)&15;
int value = memoryWait32[addr];
@@ -110,7 +110,7 @@
return value;
}
-inline int dataTicksAccessSeq16(u32 address)// DATA 8/16bits SEQ
+inline int dataTicksAccessSeq16(uint32_t address)// DATA 8/16bits SEQ
{
int addr = (address>>24)&15;
int value = memoryWaitSeq[addr];
@@ -131,7 +131,7 @@
return value;
}
-inline int dataTicksAccessSeq32(u32 address)// DATA 32bits SEQ
+inline int dataTicksAccessSeq32(uint32_t address)// DATA 32bits SEQ
{
int addr = (address>>24)&15;
int value = memoryWaitSeq32[addr];
@@ -154,7 +154,7 @@
// Waitstates when executing opcode
-inline int codeTicksAccess16(u32 address) // THUMB NON SEQ
+inline int codeTicksAccess16(uint32_t address) // THUMB NON SEQ
{
int addr = (address>>24)&15;
@@ -183,7 +183,7 @@
}
}
-inline int codeTicksAccess32(u32 address) // ARM NON SEQ
+inline int codeTicksAccess32(uint32_t address) // ARM NON SEQ
{
int addr = (address>>24)&15;
@@ -212,7 +212,7 @@
}
}
-inline int codeTicksAccessSeq16(u32 address) // THUMB SEQ
+inline int codeTicksAccessSeq16(uint32_t address) // THUMB SEQ
{
int addr = (address>>24)&15;
@@ -239,7 +239,7 @@
}
}
-inline int codeTicksAccessSeq32(u32 address) // ARM SEQ
+inline int codeTicksAccessSeq32(uint32_t address) // ARM SEQ
{
int addr = (address>>24)&15;
--- a/src/in_gsf/vbam/gba/GBAinline.h
+++ b/src/in_gsf/vbam/gba/GBAinline.h
@@ -9,7 +9,7 @@
#include "GBAcpu.h"
//#include "GBALink.h"
-extern const u32 objTilesAddress[3];
+extern const uint32_t objTilesAddress[3];
extern bool stopState;
extern bool holdState;
@@ -19,7 +19,7 @@
extern bool cpuFlashEnabled;
extern bool cpuEEPROMEnabled;
extern bool cpuEEPROMSensorEnabled;
-extern u32 cpuDmaLast;
+extern uint32_t cpuDmaLast;
extern bool timer0On;
extern int timer0Ticks;
extern int timer0ClockReload;
@@ -38,15 +38,15 @@
map[(addr)>>24].address[(addr) & map[(addr)>>24].mask]
#define CPUReadHalfWordQuick(addr) \
- READ16LE(((u16*)&map[(addr)>>24].address[(addr) & map[(addr)>>24].mask]))
+ READ16LE(((uint16_t*)&map[(addr)>>24].address[(addr) & map[(addr)>>24].mask]))
#define CPUReadMemoryQuick(addr) \
- READ32LE(((u32*)&map[(addr)>>24].address[(addr) & map[(addr)>>24].mask]))
-
-static inline u32 CPUReadMemory(u32 address)
+ READ32LE(((uint32_t*)&map[(addr)>>24].address[(addr) & map[(addr)>>24].mask]))
+
+static inline uint32_t CPUReadMemory(uint32_t address)
{
- u32 value;
- u32 oldAddress = address;
+ uint32_t value;
+ uint32_t oldAddress = address;
if(address & 3) {
address &= ~0x03;
@@ -63,33 +63,33 @@
}
#endif
- value = READ32LE(((u32 *)&biosProtected));
+ value = READ32LE(((uint32_t *)&biosProtected));
}
else goto unreadable;
} else
- value = READ32LE(((u32 *)&bios[address & 0x3FFC]));
+ value = READ32LE(((uint32_t *)&bios[address & 0x3FFC]));
break;
case 2:
- value = READ32LE(((u32 *)&workRAM[address & 0x3FFFC]));
+ value = READ32LE(((uint32_t *)&workRAM[address & 0x3FFFC]));
break;
case 3:
- value = READ32LE(((u32 *)&internalRAM[address & 0x7ffC]));
+ value = READ32LE(((uint32_t *)&internalRAM[address & 0x7ffC]));
break;
case 4:
if((address < 0x4000400) && ioReadable[address & 0x3fc]) {
if(ioReadable[(address & 0x3fc) + 2]) {
- value = READ32LE(((u32 *)&ioMem[address & 0x3fC]));
+ value = READ32LE(((uint32_t *)&ioMem[address & 0x3fC]));
/*if ((address & 0x3fc) == COMM_JOY_RECV_L)
UPDATE_REG(COMM_JOYSTAT, READ16LE(&ioMem[COMM_JOYSTAT]) & ~JOYSTAT_RECV);*/
} else {
- value = READ16LE(((u16 *)&ioMem[address & 0x3fc]));
+ value = READ16LE(((uint16_t *)&ioMem[address & 0x3fc]));
}
}
else
goto unreadable;
break;
case 5:
- value = READ32LE(((u32 *)&paletteRAM[address & 0x3fC]));
+ value = READ32LE(((uint32_t *)&paletteRAM[address & 0x3fC]));
break;
case 6:
address = (address & 0x1fffc);
@@ -100,17 +100,17 @@
}
if ((address & 0x18000) == 0x18000)
address &= 0x17fff;
- value = READ32LE(((u32 *)&vram[address]));
+ value = READ32LE(((uint32_t *)&vram[address]));
break;
case 7:
- value = READ32LE(((u32 *)&oam[address & 0x3FC]));
+ value = READ32LE(((uint32_t *)&oam[address & 0x3FC]));
break;
case 8:
case 9:
case 10:
case 11:
case 12:
- value = READ32LE(((u32 *)&rom[address&0x1FFFFFC]));
+ value = READ32LE(((uint32_t *)&rom[address&0x1FFFFFC]));
break;
case 13:
if(cpuEEPROMEnabled)
@@ -172,12 +172,12 @@
return value;
}
-extern u32 myROM[];
-
-static inline u32 CPUReadHalfWord(u32 address)
+extern uint32_t myROM[];
+
+static inline uint32_t CPUReadHalfWord(uint32_t address)
{
- u32 value;
- u32 oldAddress = address;
+ uint32_t value;
+ uint32_t oldAddress = address;
if(address & 1) {
address &= ~0x01;
@@ -193,21 +193,21 @@
armNextPC - 4 : armNextPC - 2);
}
#endif
- value = READ16LE(((u16 *)&biosProtected[address&2]));
+ value = READ16LE(((uint16_t *)&biosProtected[address&2]));
} else goto unreadable;
} else
- value = READ16LE(((u16 *)&bios[address & 0x3FFE]));
+ value = READ16LE(((uint16_t *)&bios[address & 0x3FFE]));
break;
case 2:
- value = READ16LE(((u16 *)&workRAM[address & 0x3FFFE]));
+ value = READ16LE(((uint16_t *)&workRAM[address & 0x3FFFE]));
break;
case 3:
- value = READ16LE(((u16 *)&internalRAM[address & 0x7ffe]));
+ value = READ16LE(((uint16_t *)&internalRAM[address & 0x7ffe]));
break;
case 4:
if((address < 0x4000400) && ioReadable[address & 0x3fe])
{
- value = READ16LE(((u16 *)&ioMem[address & 0x3fe]));
+ value = READ16LE(((uint16_t *)&ioMem[address & 0x3fe]));
if (((address & 0x3fe)>0xFF) && ((address & 0x3fe)<0x10E))
{
if (((address & 0x3fe) == 0x100) && timer0On)
@@ -226,7 +226,7 @@
else goto unreadable;
break;
case 5:
- value = READ16LE(((u16 *)&paletteRAM[address & 0x3fe]));
+ value = READ16LE(((uint16_t *)&paletteRAM[address & 0x3fe]));
break;
case 6:
address = (address & 0x1fffe);
@@ -237,10 +237,10 @@
}
if ((address & 0x18000) == 0x18000)
address &= 0x17fff;
- value = READ16LE(((u16 *)&vram[address]));
+ value = READ16LE(((uint16_t *)&vram[address]));
break;
case 7:
- value = READ16LE(((u16 *)&oam[address & 0x3fe]));
+ value = READ16LE(((uint16_t *)&oam[address & 0x3fe]));
break;
case 8:
case 9:
@@ -250,7 +250,7 @@
if(address == 0x80000c4 || address == 0x80000c6 || address == 0x80000c8)
value = /*rtcRead(address)*/0;
else
- value = READ16LE(((u16 *)&rom[address & 0x1FFFFFE]));
+ value = READ16LE(((uint16_t *)&rom[address & 0x1FFFFFE]));
break;
case 13:
if(cpuEEPROMEnabled)
@@ -291,16 +291,16 @@
return value;
}
-static inline s16 CPUReadHalfWordSigned(u32 address)
+static inline int16_t CPUReadHalfWordSigned(uint32_t address)
{
- u32 oldAddress = address;
+ uint32_t oldAddress = address;
if(address & 1) {
address &= ~0x01;
}
- s16 value = (s16)CPUReadHalfWord(address);
+ int16_t value = (int16_t)CPUReadHalfWord(address);
if((oldAddress & 1))
{
- value = (s8)value;
+ value = (int8_t)value;
#ifdef GBA_LOGGING
if(systemVerbose & VERBOSE_UNALIGNED_MEMORY) {
log("Unaligned signed halfword read from: %08x at %08x (%08x)\n", oldAddress, armMode ?
@@ -311,7 +311,7 @@
return value;
}
-static inline u8 CPUReadByte(u32 address)
+static inline uint8_t CPUReadByte(uint32_t address)
{
switch(address >> 24) {
case 0:
@@ -389,7 +389,7 @@
}
}
-static inline void CPUWriteMemory(u32 address, u32 value)
+static inline void CPUWriteMemory(uint32_t address, uint32_t value)
{
#ifdef GBA_LOGGING
@@ -408,21 +408,21 @@
switch(address >> 24) {
case 0x02:
#ifdef BKPT_SUPPORT
- if(*((u32 *)&freezeWorkRAM[address & 0x3FFFC]))
+ if(*((uint32_t *)&freezeWorkRAM[address & 0x3FFFC]))
cheatsWriteMemory(address & 0x203FFFC,
value);
else
#endif
- WRITE32LE(((u32 *)&workRAM[address & 0x3FFFC]), value);
+ WRITE32LE(((uint32_t *)&workRAM[address & 0x3FFFC]), value);
break;
case 0x03:
#ifdef BKPT_SUPPORT
- if(*((u32 *)&freezeInternalRAM[address & 0x7ffc]))
+ if(*((uint32_t *)&freezeInternalRAM[address & 0x7ffc]))
cheatsWriteMemory(address & 0x3007FFC,
value);
else
#endif
- WRITE32LE(((u32 *)&internalRAM[address & 0x7ffC]), value);
+ WRITE32LE(((uint32_t *)&internalRAM[address & 0x7ffC]), value);
break;
case 0x04:
if(address < 0x4000400) {
@@ -432,12 +432,12 @@
break;
case 0x05:
#ifdef BKPT_SUPPORT
- if(*((u32 *)&freezePRAM[address & 0x3fc]))
+ if(*((uint32_t *)&freezePRAM[address & 0x3fc]))
cheatsWriteMemory(address & 0x70003FC,
value);
else
#endif
- WRITE32LE(((u32 *)&paletteRAM[address & 0x3FC]), value);
+ WRITE32LE(((uint32_t *)&paletteRAM[address & 0x3FC]), value);
break;
case 0x06:
address = (address & 0x1fffc);
@@ -447,21 +447,21 @@
address &= 0x17fff;
#ifdef BKPT_SUPPORT
- if(*((u32 *)&freezeVRAM[address]))
+ if(*((uint32_t *)&freezeVRAM[address]))
cheatsWriteMemory(address + 0x06000000, value);
else
#endif
- WRITE32LE(((u32 *)&vram[address]), value);
+ WRITE32LE(((uint32_t *)&vram[address]), value);
break;
case 0x07:
#ifdef BKPT_SUPPORT
- if(*((u32 *)&freezeOAM[address & 0x3fc]))
+ if(*((uint32_t *)&freezeOAM[address & 0x3fc]))
cheatsWriteMemory(address & 0x70003FC,
value);
else
#endif
- WRITE32LE(((u32 *)&oam[address & 0x3fc]), value);
+ WRITE32LE(((uint32_t *)&oam[address & 0x3fc]), value);
break;
case 0x0D:
if(cpuEEPROMEnabled) {
@@ -469,11 +469,11 @@
break;
}
goto unwritable;
- case 0x0E:
- if(/*(!eepromInUse) | */cpuSramEnabled | cpuFlashEnabled) {
+ /*case 0x0E:
+ if(*//*(!eepromInUse) | *//*cpuSramEnabled | cpuFlashEnabled) {
//(*cpuSaveGameFunc)(address, (u8)value);
break;
- }
+ }*/
// default
default:
unwritable:
@@ -489,7 +489,7 @@
}
}
-static inline void CPUWriteHalfWord(u32 address, u16 value)
+static inline void CPUWriteHalfWord(uint32_t address, uint16_t value)
{
#ifdef GBA_LOGGING
if(address & 1) {
@@ -507,21 +507,21 @@
switch(address >> 24) {
case 2:
#ifdef BKPT_SUPPORT
- if(*((u16 *)&freezeWorkRAM[address & 0x3FFFE]))
+ if(*((uint16_t *)&freezeWorkRAM[address & 0x3FFFE]))
cheatsWriteHalfWord(address & 0x203FFFE,
value);
else
#endif
- WRITE16LE(((u16 *)&workRAM[address & 0x3FFFE]),value);
+ WRITE16LE(((uint16_t *)&workRAM[address & 0x3FFFE]),value);
break;
case 3:
#ifdef BKPT_SUPPORT
- if(*((u16 *)&freezeInternalRAM[address & 0x7ffe]))
+ if(*((uint16_t *)&freezeInternalRAM[address & 0x7ffe]))
cheatsWriteHalfWord(address & 0x3007ffe,
value);
else
#endif
- WRITE16LE(((u16 *)&internalRAM[address & 0x7ffe]), value);
+ WRITE16LE(((uint16_t *)&internalRAM[address & 0x7ffe]), value);
break;
case 4:
if(address < 0x4000400)
@@ -530,12 +530,12 @@
break;
case 5:
#ifdef BKPT_SUPPORT
- if(*((u16 *)&freezePRAM[address & 0x03fe]))
+ if(*((uint16_t *)&freezePRAM[address & 0x03fe]))
cheatsWriteHalfWord(address & 0x70003fe,
value);
else
#endif
- WRITE16LE(((u16 *)&paletteRAM[address & 0x3fe]), value);
+ WRITE16LE(((uint16_t *)&paletteRAM[address & 0x3fe]), value);
break;
case 6:
address = (address & 0x1fffe);
@@ -544,21 +544,21 @@
if ((address & 0x18000) == 0x18000)
address &= 0x17fff;
#ifdef BKPT_SUPPORT
- if(*((u16 *)&freezeVRAM[address]))
+ if(*((uint16_t *)&freezeVRAM[address]))
cheatsWriteHalfWord(address + 0x06000000,
value);
else
#endif
- WRITE16LE(((u16 *)&vram[address]), value);
+ WRITE16LE(((uint16_t *)&vram[address]), value);
break;
case 7:
#ifdef BKPT_SUPPORT
- if(*((u16 *)&freezeOAM[address & 0x03fe]))
+ if(*((uint16_t *)&freezeOAM[address & 0x03fe]))
cheatsWriteHalfWord(address & 0x70003fe,
value);
else
#endif
- WRITE16LE(((u16 *)&oam[address & 0x3fe]), value);
+ WRITE16LE(((uint16_t *)&oam[address & 0x3fe]), value);
break;
case 8:
case 9:
@@ -573,12 +573,12 @@
break;
}
goto unwritable;
- case 14:
- if(/*(!eepromInUse) | */cpuSramEnabled | cpuFlashEnabled) {
+ /*case 14:
+ if(*//*(!eepromInUse) | *//*cpuSramEnabled | cpuFlashEnabled) {
//(*cpuSaveGameFunc)(address, (u8)value);
break;
}
- goto unwritable;
+ goto unwritable;*/
default:
unwritable:
#ifdef GBA_LOGGING
@@ -593,7 +593,7 @@
}
}
-static inline void CPUWriteByte(u32 address, u8 b)
+static inline void CPUWriteByte(uint32_t address, uint8_t b)
{
switch(address >> 24) {
case 2:
@@ -665,7 +665,7 @@
cpuNextEvent = cpuTotalTicks;
break;
default: // every other register
- u32 lowerBits = address & 0x3fe;
+ uint32_t lowerBits = address & 0x3fe;
if(address & 1) {
CPUUpdateRegister(lowerBits, (READ16LE(&ioMem[lowerBits]) & 0x00FF) | (b << 8));
} else {
@@ -677,7 +677,7 @@
break;
case 5:
// no need to switch
- *((u16 *)&paletteRAM[address & 0x3FE]) = (b << 8) | b;
+ *((uint16_t *)&paletteRAM[address & 0x3FE]) = (b << 8) | b;
break;
case 6:
address = (address & 0x1fffe);
@@ -695,13 +695,13 @@
cheatsWriteByte(address + 0x06000000, b);
else
#endif
- *((u16 *)&vram[address]) = (b << 8) | b;
+ *((uint16_t *)&vram[address]) = (b << 8) | b;
}
break;
case 7:
// no need to switch
// byte writes to OAM are ignored
- // *((u16 *)&oam[address & 0x3FE]) = (b << 8) | b;
+ // *((uint16_t *)&oam[address & 0x3FE]) = (b << 8) | b;
break;
case 13:
if(cpuEEPROMEnabled) {
@@ -709,14 +709,14 @@
break;
}
goto unwritable;
- case 14:
- if ((saveType != 5) && (/*(!eepromInUse) | */cpuSramEnabled | cpuFlashEnabled)) {
+ /*case 14:
+ if ((saveType != 5) && (*//*(!eepromInUse) | *//*cpuSramEnabled | cpuFlashEnabled)) {
//if(!cpuEEPROMEnabled && (cpuSramEnabled | cpuFlashEnabled)) {
//(*cpuSaveGameFunc)(address, b);
break;
- }
+ }*/
// default
default:
unwritable:
--- a/src/in_gsf/vbam/gba/Globals.cpp
+++ b/src/in_gsf/vbam/gba/Globals.cpp
@@ -14,9 +14,9 @@
bool V_FLAG = 0;
bool armState = true;
bool armIrqEnable = true;
-u32 armNextPC = 0x00000000;
+uint32_t armNextPC = 0x00000000;
int armMode = 0x1f;
-u32 stop = 0x08000568;
+uint32_t stop = 0x08000568;
int saveType = 0;
bool useBios = false;
bool skipBios = false;
@@ -40,91 +40,91 @@
// 0x0000 to 0x7FFF: set custom 15 bit color
int customBackdropColor = -1;
-u8 *bios = 0;
-u8 *rom = 0;
-u8 *internalRAM = 0;
-u8 *workRAM = 0;
-u8 *paletteRAM = 0;
-u8 *vram = 0;
-u8 *pix = 0;
-u8 *oam = 0;
-u8 *ioMem = 0;
+uint8_t *bios = 0;
+uint8_t *rom = 0;
+uint8_t *internalRAM = 0;
+uint8_t *workRAM = 0;
+uint8_t *paletteRAM = 0;
+uint8_t *vram = 0;
+uint8_t *pix = 0;
+uint8_t *oam = 0;
+uint8_t *ioMem = 0;
-u16 DISPCNT = 0x0080;
-u16 DISPSTAT = 0x0000;
-u16 VCOUNT = 0x0000;
-u16 BG0CNT = 0x0000;
-u16 BG1CNT = 0x0000;
-u16 BG2CNT = 0x0000;
-u16 BG3CNT = 0x0000;
-u16 BG0HOFS = 0x0000;
-u16 BG0VOFS = 0x0000;
-u16 BG1HOFS = 0x0000;
-u16 BG1VOFS = 0x0000;
-u16 BG2HOFS = 0x0000;
-u16 BG2VOFS = 0x0000;
-u16 BG3HOFS = 0x0000;
-u16 BG3VOFS = 0x0000;
-u16 BG2PA = 0x0100;
-u16 BG2PB = 0x0000;
-u16 BG2PC = 0x0000;
-u16 BG2PD = 0x0100;
-u16 BG2X_L = 0x0000;
-u16 BG2X_H = 0x0000;
-u16 BG2Y_L = 0x0000;
-u16 BG2Y_H = 0x0000;
-u16 BG3PA = 0x0100;
-u16 BG3PB = 0x0000;
-u16 BG3PC = 0x0000;
-u16 BG3PD = 0x0100;
-u16 BG3X_L = 0x0000;
-u16 BG3X_H = 0x0000;
-u16 BG3Y_L = 0x0000;
-u16 BG3Y_H = 0x0000;
-u16 WIN0H = 0x0000;
-u16 WIN1H = 0x0000;
-u16 WIN0V = 0x0000;
-u16 WIN1V = 0x0000;
-u16 WININ = 0x0000;
-u16 WINOUT = 0x0000;
-u16 MOSAIC = 0x0000;
-u16 BLDMOD = 0x0000;
-u16 COLEV = 0x0000;
-u16 COLY = 0x0000;
-u16 DM0SAD_L = 0x0000;
-u16 DM0SAD_H = 0x0000;
-u16 DM0DAD_L = 0x0000;
-u16 DM0DAD_H = 0x0000;
-u16 DM0CNT_L = 0x0000;
-u16 DM0CNT_H = 0x0000;
-u16 DM1SAD_L = 0x0000;
-u16 DM1SAD_H = 0x0000;
-u16 DM1DAD_L = 0x0000;
-u16 DM1DAD_H = 0x0000;
-u16 DM1CNT_L = 0x0000;
-u16 DM1CNT_H = 0x0000;
-u16 DM2SAD_L = 0x0000;
-u16 DM2SAD_H = 0x0000;
-u16 DM2DAD_L = 0x0000;
-u16 DM2DAD_H = 0x0000;
-u16 DM2CNT_L = 0x0000;
-u16 DM2CNT_H = 0x0000;
-u16 DM3SAD_L = 0x0000;
-u16 DM3SAD_H = 0x0000;
-u16 DM3DAD_L = 0x0000;
-u16 DM3DAD_H = 0x0000;
-u16 DM3CNT_L = 0x0000;
-u16 DM3CNT_H = 0x0000;
-u16 TM0D = 0x0000;
-u16 TM0CNT = 0x0000;
-u16 TM1D = 0x0000;
-u16 TM1CNT = 0x0000;
-u16 TM2D = 0x0000;
-u16 TM2CNT = 0x0000;
-u16 TM3D = 0x0000;
-u16 TM3CNT = 0x0000;
-u16 P1 = 0xFFFF;
-u16 IE = 0x0000;
-u16 IF = 0x0000;
-u16 IME = 0x0000;
+uint16_t DISPCNT = 0x0080;
+uint16_t DISPSTAT = 0x0000;
+uint16_t VCOUNT = 0x0000;
+uint16_t BG0CNT = 0x0000;
+uint16_t BG1CNT = 0x0000;
+uint16_t BG2CNT = 0x0000;
+uint16_t BG3CNT = 0x0000;
+uint16_t BG0HOFS = 0x0000;
+uint16_t BG0VOFS = 0x0000;
+uint16_t BG1HOFS = 0x0000;
+uint16_t BG1VOFS = 0x0000;
+uint16_t BG2HOFS = 0x0000;
+uint16_t BG2VOFS = 0x0000;
+uint16_t BG3HOFS = 0x0000;
+uint16_t BG3VOFS = 0x0000;
+uint16_t BG2PA = 0x0100;
+uint16_t BG2PB = 0x0000;
+uint16_t BG2PC = 0x0000;
+uint16_t BG2PD = 0x0100;
+uint16_t BG2X_L = 0x0000;
+uint16_t BG2X_H = 0x0000;
+uint16_t BG2Y_L = 0x0000;
+uint16_t BG2Y_H = 0x0000;
+uint16_t BG3PA = 0x0100;
+uint16_t BG3PB = 0x0000;
+uint16_t BG3PC = 0x0000;
+uint16_t BG3PD = 0x0100;
+uint16_t BG3X_L = 0x0000;
+uint16_t BG3X_H = 0x0000;
+uint16_t BG3Y_L = 0x0000;
+uint16_t BG3Y_H = 0x0000;
+uint16_t WIN0H = 0x0000;
+uint16_t WIN1H = 0x0000;
+uint16_t WIN0V = 0x0000;
+uint16_t WIN1V = 0x0000;
+uint16_t WININ = 0x0000;
+uint16_t WINOUT = 0x0000;
+uint16_t MOSAIC = 0x0000;
+uint16_t BLDMOD = 0x0000;
+uint16_t COLEV = 0x0000;
+uint16_t COLY = 0x0000;
+uint16_t DM0SAD_L = 0x0000;
+uint16_t DM0SAD_H = 0x0000;
+uint16_t DM0DAD_L = 0x0000;
+uint16_t DM0DAD_H = 0x0000;
+uint16_t DM0CNT_L = 0x0000;
+uint16_t DM0CNT_H = 0x0000;
+uint16_t DM1SAD_L = 0x0000;
+uint16_t DM1SAD_H = 0x0000;
+uint16_t DM1DAD_L = 0x0000;
+uint16_t DM1DAD_H = 0x0000;
+uint16_t DM1CNT_L = 0x0000;
+uint16_t DM1CNT_H = 0x0000;
+uint16_t DM2SAD_L = 0x0000;
+uint16_t DM2SAD_H = 0x0000;
+uint16_t DM2DAD_L = 0x0000;
+uint16_t DM2DAD_H = 0x0000;
+uint16_t DM2CNT_L = 0x0000;
+uint16_t DM2CNT_H = 0x0000;
+uint16_t DM3SAD_L = 0x0000;
+uint16_t DM3SAD_H = 0x0000;
+uint16_t DM3DAD_L = 0x0000;
+uint16_t DM3DAD_H = 0x0000;
+uint16_t DM3CNT_L = 0x0000;
+uint16_t DM3CNT_H = 0x0000;
+uint16_t TM0D = 0x0000;
+uint16_t TM0CNT = 0x0000;
+uint16_t TM1D = 0x0000;
+uint16_t TM1CNT = 0x0000;
+uint16_t TM2D = 0x0000;
+uint16_t TM2CNT = 0x0000;
+uint16_t TM3D = 0x0000;
+uint16_t TM3CNT = 0x0000;
+uint16_t P1 = 0xFFFF;
+uint16_t IE = 0x0000;
+uint16_t IF = 0x0000;
+uint16_t IME = 0x0000;
--- a/src/in_gsf/vbam/gba/Globals.h
+++ b/src/in_gsf/vbam/gba/Globals.h
@@ -24,9 +24,9 @@
extern bool V_FLAG;
extern bool armState;
extern bool armIrqEnable;
-extern u32 armNextPC;
+extern uint32_t armNextPC;
extern int armMode;
-extern u32 stop;
+extern uint32_t stop;
extern int saveType;
extern bool useBios;
extern bool skipBios;
@@ -46,93 +46,93 @@
extern bool skipSaveGameCheats; // skip cheat list data when reading save states
extern int customBackdropColor;
-extern u8 *bios;
-extern u8 *rom;
-extern u8 *internalRAM;
-extern u8 *workRAM;
-extern u8 *paletteRAM;
-extern u8 *vram;
-extern u8 *pix;
-extern u8 *oam;
-extern u8 *ioMem;
+extern uint8_t *bios;
+extern uint8_t *rom;
+extern uint8_t *internalRAM;
+extern uint8_t *workRAM;
+extern uint8_t *paletteRAM;
+extern uint8_t *vram;
+extern uint8_t *pix;
+extern uint8_t *oam;
+extern uint8_t *ioMem;
-extern u16 DISPCNT;
-extern u16 DISPSTAT;
-extern u16 VCOUNT;
-extern u16 BG0CNT;
-extern u16 BG1CNT;
-extern u16 BG2CNT;
-extern u16 BG3CNT;
-extern u16 BG0HOFS;
-extern u16 BG0VOFS;
-extern u16 BG1HOFS;
-extern u16 BG1VOFS;
-extern u16 BG2HOFS;
-extern u16 BG2VOFS;
-extern u16 BG3HOFS;
-extern u16 BG3VOFS;
-extern u16 BG2PA;
-extern u16 BG2PB;
-extern u16 BG2PC;
-extern u16 BG2PD;
-extern u16 BG2X_L;
-extern u16 BG2X_H;
-extern u16 BG2Y_L;
-extern u16 BG2Y_H;
-extern u16 BG3PA;
-extern u16 BG3PB;
-extern u16 BG3PC;
-extern u16 BG3PD;
-extern u16 BG3X_L;
-extern u16 BG3X_H;
-extern u16 BG3Y_L;
-extern u16 BG3Y_H;
-extern u16 WIN0H;
-extern u16 WIN1H;
-extern u16 WIN0V;
-extern u16 WIN1V;
-extern u16 WININ;
-extern u16 WINOUT;
-extern u16 MOSAIC;
-extern u16 BLDMOD;
-extern u16 COLEV;
-extern u16 COLY;
-extern u16 DM0SAD_L;
-extern u16 DM0SAD_H;
-extern u16 DM0DAD_L;
-extern u16 DM0DAD_H;
-extern u16 DM0CNT_L;
-extern u16 DM0CNT_H;
-extern u16 DM1SAD_L;
-extern u16 DM1SAD_H;
-extern u16 DM1DAD_L;
-extern u16 DM1DAD_H;
-extern u16 DM1CNT_L;
-extern u16 DM1CNT_H;
-extern u16 DM2SAD_L;
-extern u16 DM2SAD_H;
-extern u16 DM2DAD_L;
-extern u16 DM2DAD_H;
-extern u16 DM2CNT_L;
-extern u16 DM2CNT_H;
-extern u16 DM3SAD_L;
-extern u16 DM3SAD_H;
-extern u16 DM3DAD_L;
-extern u16 DM3DAD_H;
-extern u16 DM3CNT_L;
-extern u16 DM3CNT_H;
-extern u16 TM0D;
-extern u16 TM0CNT;
-extern u16 TM1D;
-extern u16 TM1CNT;
-extern u16 TM2D;
-extern u16 TM2CNT;
-extern u16 TM3D;
-extern u16 TM3CNT;
-extern u16 P1;
-extern u16 IE;
-extern u16 IF;
-extern u16 IME;
+extern uint16_t DISPCNT;
+extern uint16_t DISPSTAT;
+extern uint16_t VCOUNT;
+extern uint16_t BG0CNT;
+extern uint16_t BG1CNT;
+extern uint16_t BG2CNT;
+extern uint16_t BG3CNT;
+extern uint16_t BG0HOFS;
+extern uint16_t BG0VOFS;
+extern uint16_t BG1HOFS;
+extern uint16_t BG1VOFS;
+extern uint16_t BG2HOFS;
+extern uint16_t BG2VOFS;
+extern uint16_t BG3HOFS;
+extern uint16_t BG3VOFS;
+extern uint16_t BG2PA;
+extern uint16_t BG2PB;
+extern uint16_t BG2PC;
+extern uint16_t BG2PD;
+extern uint16_t BG2X_L;
+extern uint16_t BG2X_H;
+extern uint16_t BG2Y_L;
+extern uint16_t BG2Y_H;
+extern uint16_t BG3PA;
+extern uint16_t BG3PB;
+extern uint16_t BG3PC;
+extern uint16_t BG3PD;
+extern uint16_t BG3X_L;
+extern uint16_t BG3X_H;
+extern uint16_t BG3Y_L;
+extern uint16_t BG3Y_H;
+extern uint16_t WIN0H;
+extern uint16_t WIN1H;
+extern uint16_t WIN0V;
+extern uint16_t WIN1V;
+extern uint16_t WININ;
+extern uint16_t WINOUT;
+extern uint16_t MOSAIC;
+extern uint16_t BLDMOD;
+extern uint16_t COLEV;
+extern uint16_t COLY;
+extern uint16_t DM0SAD_L;
+extern uint16_t DM0SAD_H;
+extern uint16_t DM0DAD_L;
+extern uint16_t DM0DAD_H;
+extern uint16_t DM0CNT_L;
+extern uint16_t DM0CNT_H;
+extern uint16_t DM1SAD_L;
+extern uint16_t DM1SAD_H;
+extern uint16_t DM1DAD_L;
+extern uint16_t DM1DAD_H;
+extern uint16_t DM1CNT_L;
+extern uint16_t DM1CNT_H;
+extern uint16_t DM2SAD_L;
+extern uint16_t DM2SAD_H;
+extern uint16_t DM2DAD_L;
+extern uint16_t DM2DAD_H;
+extern uint16_t DM2CNT_L;
+extern uint16_t DM2CNT_H;
+extern uint16_t DM3SAD_L;
+extern uint16_t DM3SAD_H;
+extern uint16_t DM3DAD_L;
+extern uint16_t DM3DAD_H;
+extern uint16_t DM3CNT_L;
+extern uint16_t DM3CNT_H;
+extern uint16_t TM0D;
+extern uint16_t TM0CNT;
+extern uint16_t TM1D;
+extern uint16_t TM1CNT;
+extern uint16_t TM2D;
+extern uint16_t TM2CNT;
+extern uint16_t TM3D;
+extern uint16_t TM3CNT;
+extern uint16_t P1;
+extern uint16_t IE;
+extern uint16_t IF;
+extern uint16_t IME;
#endif // GLOBALS_H
--- a/src/in_gsf/vbam/gba/Sound.cpp
+++ b/src/in_gsf/vbam/gba/Sound.cpp
@@ -13,6 +13,7 @@
#include "../common/SoundDriver.h"
extern SoundDriver *systemSoundInit();
+bool soundDeclicking = true;
#define NR10 0x60
#define NR11 0x62
@@ -42,7 +43,7 @@
int const SOUND_CLOCK_TICKS_ = 167772; // 1/100 second
-static u16 soundFinalWave [6400];
+static uint16_t soundFinalWave [6400];
long soundSampleRate = 44100;
bool soundInterpolation = true;
bool soundPaused = true;
@@ -84,7 +85,7 @@
int readIndex;
int count;
int writeIndex;
- u8 fifo [32];
+ uint8_t fifo [32];
int dac;
private:
@@ -155,7 +156,7 @@
{
blip_time_t time = blip_time();
- dac = (s8) dac >> shift;
+ dac = (int8_t) dac >> shift;
int delta = dac - last_amp;
if ( delta )
{
@@ -195,8 +196,8 @@
int reg = which ? FIFOB_L : FIFOA_L;
for ( int n = 4; n--; )
{
- soundEvent(reg , (u16)0);
- soundEvent(reg+2, (u16)0);
+ soundEvent(reg , (uint16_t)0);
+ soundEvent(reg+2, (uint16_t)0);
}
}
}
@@ -260,7 +261,7 @@
return 0;
}
-void soundEvent(u32 address, u8 data)
+void soundEvent(uint32_t address, uint8_t data)
{
int gb_addr = gba_to_gb_sound( address );
if ( gb_addr )
@@ -303,7 +304,7 @@
apply_volume( true );
}
-void soundEvent(u32 address, u16 data)
+void soundEvent(uint32_t address, uint16_t data)
{
switch ( address )
{
@@ -329,8 +330,8 @@
break;
default:
- soundEvent( address & ~1, (u8) (data ) ); // even
- soundEvent( address | 1, (u8) (data >> 8) ); // odd
+ soundEvent( address & ~1, (uint8_t) (data ) ); // even
+ soundEvent( address | 1, (uint8_t) (data >> 8) ); // odd
break;
}
}
@@ -435,6 +436,7 @@
static void reset_apu()
{
+ gb_apu->reduce_clicks(soundDeclicking);
gb_apu->reset( gb_apu->mode_agb, true );
if ( stereo_buffer )
@@ -485,6 +487,20 @@
soundDriver = 0;
}
+ // APU
+ if ( gb_apu )
+ {
+ delete gb_apu;
+ gb_apu = 0;
+ }
+
+ // Stereo_Buffer
+ if (stereo_buffer)
+ {
+ delete stereo_buffer;
+ stereo_buffer = 0;
+ }
+
//systemOnSoundShutdown();
}
@@ -534,7 +550,7 @@
SOUND_CLOCK_TICKS = SOUND_CLOCK_TICKS_;
soundTicks = SOUND_CLOCK_TICKS_;
- soundEvent( NR52, (u8) 0x80 );
+ soundEvent( NR52, (uint8_t) 0x80 );
}
bool soundInit()
--- a/src/in_gsf/vbam/gba/Sound.h
+++ b/src/in_gsf/vbam/gba/Sound.h
@@ -5,6 +5,8 @@
//#include "../System.h"
#include "../common/Types.h"
+
+extern bool soundDeclicking;
//// Setup/options (these affect GBA and GB sound)
@@ -60,8 +62,8 @@
void soundReset();
// Emulates write to sound hardware
-void soundEvent( u32 addr, u8 data );
-void soundEvent( u32 addr, u16 data ); // TODO: error-prone to overload like this
+void soundEvent( uint32_t addr, uint8_t data );
+void soundEvent( uint32_t addr, uint16_t data ); // TODO: error-prone to overload like this
// Notifies emulator that a timer has overflowed
void soundTimerOverflow( int which );
--- a/src/in_gsf/vbam/gba/bios.cpp
+++ b/src/in_gsf/vbam/gba/bios.cpp
@@ -7,39 +7,39 @@
#include "GBAinline.h"
#include "Globals.h"
-s16 sineTable[256] = {
- (s16)0x0000, (s16)0x0192, (s16)0x0323, (s16)0x04B5, (s16)0x0645, (s16)0x07D5, (s16)0x0964, (s16)0x0AF1,
- (s16)0x0C7C, (s16)0x0E05, (s16)0x0F8C, (s16)0x1111, (s16)0x1294, (s16)0x1413, (s16)0x158F, (s16)0x1708,
- (s16)0x187D, (s16)0x19EF, (s16)0x1B5D, (s16)0x1CC6, (s16)0x1E2B, (s16)0x1F8B, (s16)0x20E7, (s16)0x223D,
- (s16)0x238E, (s16)0x24DA, (s16)0x261F, (s16)0x275F, (s16)0x2899, (s16)0x29CD, (s16)0x2AFA, (s16)0x2C21,
- (s16)0x2D41, (s16)0x2E5A, (s16)0x2F6B, (s16)0x3076, (s16)0x3179, (s16)0x3274, (s16)0x3367, (s16)0x3453,
- (s16)0x3536, (s16)0x3612, (s16)0x36E5, (s16)0x37AF, (s16)0x3871, (s16)0x392A, (s16)0x39DA, (s16)0x3A82,
- (s16)0x3B20, (s16)0x3BB6, (s16)0x3C42, (s16)0x3CC5, (s16)0x3D3E, (s16)0x3DAE, (s16)0x3E14, (s16)0x3E71,
- (s16)0x3EC5, (s16)0x3F0E, (s16)0x3F4E, (s16)0x3F84, (s16)0x3FB1, (s16)0x3FD3, (s16)0x3FEC, (s16)0x3FFB,
- (s16)0x4000, (s16)0x3FFB, (s16)0x3FEC, (s16)0x3FD3, (s16)0x3FB1, (s16)0x3F84, (s16)0x3F4E, (s16)0x3F0E,
- (s16)0x3EC5, (s16)0x3E71, (s16)0x3E14, (s16)0x3DAE, (s16)0x3D3E, (s16)0x3CC5, (s16)0x3C42, (s16)0x3BB6,
- (s16)0x3B20, (s16)0x3A82, (s16)0x39DA, (s16)0x392A, (s16)0x3871, (s16)0x37AF, (s16)0x36E5, (s16)0x3612,
- (s16)0x3536, (s16)0x3453, (s16)0x3367, (s16)0x3274, (s16)0x3179, (s16)0x3076, (s16)0x2F6B, (s16)0x2E5A,
- (s16)0x2D41, (s16)0x2C21, (s16)0x2AFA, (s16)0x29CD, (s16)0x2899, (s16)0x275F, (s16)0x261F, (s16)0x24DA,
- (s16)0x238E, (s16)0x223D, (s16)0x20E7, (s16)0x1F8B, (s16)0x1E2B, (s16)0x1CC6, (s16)0x1B5D, (s16)0x19EF,
- (s16)0x187D, (s16)0x1708, (s16)0x158F, (s16)0x1413, (s16)0x1294, (s16)0x1111, (s16)0x0F8C, (s16)0x0E05,
- (s16)0x0C7C, (s16)0x0AF1, (s16)0x0964, (s16)0x07D5, (s16)0x0645, (s16)0x04B5, (s16)0x0323, (s16)0x0192,
- (s16)0x0000, (s16)0xFE6E, (s16)0xFCDD, (s16)0xFB4B, (s16)0xF9BB, (s16)0xF82B, (s16)0xF69C, (s16)0xF50F,
- (s16)0xF384, (s16)0xF1FB, (s16)0xF074, (s16)0xEEEF, (s16)0xED6C, (s16)0xEBED, (s16)0xEA71, (s16)0xE8F8,
- (s16)0xE783, (s16)0xE611, (s16)0xE4A3, (s16)0xE33A, (s16)0xE1D5, (s16)0xE075, (s16)0xDF19, (s16)0xDDC3,
- (s16)0xDC72, (s16)0xDB26, (s16)0xD9E1, (s16)0xD8A1, (s16)0xD767, (s16)0xD633, (s16)0xD506, (s16)0xD3DF,
- (s16)0xD2BF, (s16)0xD1A6, (s16)0xD095, (s16)0xCF8A, (s16)0xCE87, (s16)0xCD8C, (s16)0xCC99, (s16)0xCBAD,
- (s16)0xCACA, (s16)0xC9EE, (s16)0xC91B, (s16)0xC851, (s16)0xC78F, (s16)0xC6D6, (s16)0xC626, (s16)0xC57E,
- (s16)0xC4E0, (s16)0xC44A, (s16)0xC3BE, (s16)0xC33B, (s16)0xC2C2, (s16)0xC252, (s16)0xC1EC, (s16)0xC18F,
- (s16)0xC13B, (s16)0xC0F2, (s16)0xC0B2, (s16)0xC07C, (s16)0xC04F, (s16)0xC02D, (s16)0xC014, (s16)0xC005,
- (s16)0xC000, (s16)0xC005, (s16)0xC014, (s16)0xC02D, (s16)0xC04F, (s16)0xC07C, (s16)0xC0B2, (s16)0xC0F2,
- (s16)0xC13B, (s16)0xC18F, (s16)0xC1EC, (s16)0xC252, (s16)0xC2C2, (s16)0xC33B, (s16)0xC3BE, (s16)0xC44A,
- (s16)0xC4E0, (s16)0xC57E, (s16)0xC626, (s16)0xC6D6, (s16)0xC78F, (s16)0xC851, (s16)0xC91B, (s16)0xC9EE,
- (s16)0xCACA, (s16)0xCBAD, (s16)0xCC99, (s16)0xCD8C, (s16)0xCE87, (s16)0xCF8A, (s16)0xD095, (s16)0xD1A6,
- (s16)0xD2BF, (s16)0xD3DF, (s16)0xD506, (s16)0xD633, (s16)0xD767, (s16)0xD8A1, (s16)0xD9E1, (s16)0xDB26,
- (s16)0xDC72, (s16)0xDDC3, (s16)0xDF19, (s16)0xE075, (s16)0xE1D5, (s16)0xE33A, (s16)0xE4A3, (s16)0xE611,
- (s16)0xE783, (s16)0xE8F8, (s16)0xEA71, (s16)0xEBED, (s16)0xED6C, (s16)0xEEEF, (s16)0xF074, (s16)0xF1FB,
- (s16)0xF384, (s16)0xF50F, (s16)0xF69C, (s16)0xF82B, (s16)0xF9BB, (s16)0xFB4B, (s16)0xFCDD, (s16)0xFE6E
+int16_t sineTable[256] = {
+ (int16_t)0x0000, (int16_t)0x0192, (int16_t)0x0323, (int16_t)0x04B5, (int16_t)0x0645, (int16_t)0x07D5, (int16_t)0x0964, (int16_t)0x0AF1,
+ (int16_t)0x0C7C, (int16_t)0x0E05, (int16_t)0x0F8C, (int16_t)0x1111, (int16_t)0x1294, (int16_t)0x1413, (int16_t)0x158F, (int16_t)0x1708,
+ (int16_t)0x187D, (int16_t)0x19EF, (int16_t)0x1B5D, (int16_t)0x1CC6, (int16_t)0x1E2B, (int16_t)0x1F8B, (int16_t)0x20E7, (int16_t)0x223D,
+ (int16_t)0x238E, (int16_t)0x24DA, (int16_t)0x261F, (int16_t)0x275F, (int16_t)0x2899, (int16_t)0x29CD, (int16_t)0x2AFA, (int16_t)0x2C21,
+ (int16_t)0x2D41, (int16_t)0x2E5A, (int16_t)0x2F6B, (int16_t)0x3076, (int16_t)0x3179, (int16_t)0x3274, (int16_t)0x3367, (int16_t)0x3453,
+ (int16_t)0x3536, (int16_t)0x3612, (int16_t)0x36E5, (int16_t)0x37AF, (int16_t)0x3871, (int16_t)0x392A, (int16_t)0x39DA, (int16_t)0x3A82,
+ (int16_t)0x3B20, (int16_t)0x3BB6, (int16_t)0x3C42, (int16_t)0x3CC5, (int16_t)0x3D3E, (int16_t)0x3DAE, (int16_t)0x3E14, (int16_t)0x3E71,
+ (int16_t)0x3EC5, (int16_t)0x3F0E, (int16_t)0x3F4E, (int16_t)0x3F84, (int16_t)0x3FB1, (int16_t)0x3FD3, (int16_t)0x3FEC, (int16_t)0x3FFB,
+ (int16_t)0x4000, (int16_t)0x3FFB, (int16_t)0x3FEC, (int16_t)0x3FD3, (int16_t)0x3FB1, (int16_t)0x3F84, (int16_t)0x3F4E, (int16_t)0x3F0E,
+ (int16_t)0x3EC5, (int16_t)0x3E71, (int16_t)0x3E14, (int16_t)0x3DAE, (int16_t)0x3D3E, (int16_t)0x3CC5, (int16_t)0x3C42, (int16_t)0x3BB6,
+ (int16_t)0x3B20, (int16_t)0x3A82, (int16_t)0x39DA, (int16_t)0x392A, (int16_t)0x3871, (int16_t)0x37AF, (int16_t)0x36E5, (int16_t)0x3612,
+ (int16_t)0x3536, (int16_t)0x3453, (int16_t)0x3367, (int16_t)0x3274, (int16_t)0x3179, (int16_t)0x3076, (int16_t)0x2F6B, (int16_t)0x2E5A,
+ (int16_t)0x2D41, (int16_t)0x2C21, (int16_t)0x2AFA, (int16_t)0x29CD, (int16_t)0x2899, (int16_t)0x275F, (int16_t)0x261F, (int16_t)0x24DA,
+ (int16_t)0x238E, (int16_t)0x223D, (int16_t)0x20E7, (int16_t)0x1F8B, (int16_t)0x1E2B, (int16_t)0x1CC6, (int16_t)0x1B5D, (int16_t)0x19EF,
+ (int16_t)0x187D, (int16_t)0x1708, (int16_t)0x158F, (int16_t)0x1413, (int16_t)0x1294, (int16_t)0x1111, (int16_t)0x0F8C, (int16_t)0x0E05,
+ (int16_t)0x0C7C, (int16_t)0x0AF1, (int16_t)0x0964, (int16_t)0x07D5, (int16_t)0x0645, (int16_t)0x04B5, (int16_t)0x0323, (int16_t)0x0192,
+ (int16_t)0x0000, (int16_t)0xFE6E, (int16_t)0xFCDD, (int16_t)0xFB4B, (int16_t)0xF9BB, (int16_t)0xF82B, (int16_t)0xF69C, (int16_t)0xF50F,
+ (int16_t)0xF384, (int16_t)0xF1FB, (int16_t)0xF074, (int16_t)0xEEEF, (int16_t)0xED6C, (int16_t)0xEBED, (int16_t)0xEA71, (int16_t)0xE8F8,
+ (int16_t)0xE783, (int16_t)0xE611, (int16_t)0xE4A3, (int16_t)0xE33A, (int16_t)0xE1D5, (int16_t)0xE075, (int16_t)0xDF19, (int16_t)0xDDC3,
+ (int16_t)0xDC72, (int16_t)0xDB26, (int16_t)0xD9E1, (int16_t)0xD8A1, (int16_t)0xD767, (int16_t)0xD633, (int16_t)0xD506, (int16_t)0xD3DF,
+ (int16_t)0xD2BF, (int16_t)0xD1A6, (int16_t)0xD095, (int16_t)0xCF8A, (int16_t)0xCE87, (int16_t)0xCD8C, (int16_t)0xCC99, (int16_t)0xCBAD,
+ (int16_t)0xCACA, (int16_t)0xC9EE, (int16_t)0xC91B, (int16_t)0xC851, (int16_t)0xC78F, (int16_t)0xC6D6, (int16_t)0xC626, (int16_t)0xC57E,
+ (int16_t)0xC4E0, (int16_t)0xC44A, (int16_t)0xC3BE, (int16_t)0xC33B, (int16_t)0xC2C2, (int16_t)0xC252, (int16_t)0xC1EC, (int16_t)0xC18F,
+ (int16_t)0xC13B, (int16_t)0xC0F2, (int16_t)0xC0B2, (int16_t)0xC07C, (int16_t)0xC04F, (int16_t)0xC02D, (int16_t)0xC014, (int16_t)0xC005,
+ (int16_t)0xC000, (int16_t)0xC005, (int16_t)0xC014, (int16_t)0xC02D, (int16_t)0xC04F, (int16_t)0xC07C, (int16_t)0xC0B2, (int16_t)0xC0F2,
+ (int16_t)0xC13B, (int16_t)0xC18F, (int16_t)0xC1EC, (int16_t)0xC252, (int16_t)0xC2C2, (int16_t)0xC33B, (int16_t)0xC3BE, (int16_t)0xC44A,
+ (int16_t)0xC4E0, (int16_t)0xC57E, (int16_t)0xC626, (int16_t)0xC6D6, (int16_t)0xC78F, (int16_t)0xC851, (int16_t)0xC91B, (int16_t)0xC9EE,
+ (int16_t)0xCACA, (int16_t)0xCBAD, (int16_t)0xCC99, (int16_t)0xCD8C, (int16_t)0xCE87, (int16_t)0xCF8A, (int16_t)0xD095, (int16_t)0xD1A6,
+ (int16_t)0xD2BF, (int16_t)0xD3DF, (int16_t)0xD506, (int16_t)0xD633, (int16_t)0xD767, (int16_t)0xD8A1, (int16_t)0xD9E1, (int16_t)0xDB26,
+ (int16_t)0xDC72, (int16_t)0xDDC3, (int16_t)0xDF19, (int16_t)0xE075, (int16_t)0xE1D5, (int16_t)0xE33A, (int16_t)0xE4A3, (int16_t)0xE611,
+ (int16_t)0xE783, (int16_t)0xE8F8, (int16_t)0xEA71, (int16_t)0xEBED, (int16_t)0xED6C, (int16_t)0xEEEF, (int16_t)0xF074, (int16_t)0xF1FB,
+ (int16_t)0xF384, (int16_t)0xF50F, (int16_t)0xF69C, (int16_t)0xF82B, (int16_t)0xF9BB, (int16_t)0xFB4B, (int16_t)0xFCDD, (int16_t)0xFE6E
};
void BIOS_ArcTan()
@@ -52,15 +52,15 @@
}
#endif
- s32 a = -(((s32)(reg[0].I*reg[0].I)) >> 14);
- s32 b = ((0xA9 * a) >> 14) + 0x390;
+ int32_t a = -(((int32_t)(reg[0].I*reg[0].I)) >> 14);
+ int32_t b = ((0xA9 * a) >> 14) + 0x390;
b = ((b * a) >> 14) + 0x91C;
b = ((b * a) >> 14) + 0xFB6;
b = ((b * a) >> 14) + 0x16AA;
b = ((b * a) >> 14) + 0x2081;
b = ((b * a) >> 14) + 0x3651;
b = ((b * a) >> 14) + 0xA2F9;
- a = ((s32)reg[0].I * b) >> 16;
+ a = ((int32_t)reg[0].I * b) >> 16;
reg[0].I = a;
#ifdef GBA_LOGGING
@@ -82,9 +82,9 @@
}
#endif
- s32 x = reg[0].I;
- s32 y = reg[1].I;
- u32 res = 0;
+ int32_t x = reg[0].I;
+ int32_t y = reg[1].I;
+ uint32_t res = 0;
if (y == 0) {
res = ((x>>16) & 0x8000);
} else {
@@ -130,9 +130,9 @@
}
#endif
- u32 source = reg[0].I;
- u32 dest = reg[1].I;
- u32 header = reg[2].I;
+ uint32_t source = reg[0].I;
+ uint32_t dest = reg[1].I;
+ uint32_t header = reg[2].I;
int len = CPUReadHalfWord(header);
// check address
@@ -143,7 +143,7 @@
int bits = CPUReadByte(header+2);
int revbits = 8 - bits;
// u32 value = 0;
- u32 base = CPUReadMemory(header+4);
+ uint32_t base = CPUReadMemory(header+4);
bool addBase = (base & 0x80000000) ? true : false;
base &= 0x7fffffff;
int dataSize = CPUReadByte(header+3);
@@ -155,14 +155,14 @@
if(len < 0)
break;
int mask = 0xff >> revbits;
- u8 b = CPUReadByte(source);
+ uint8_t b = CPUReadByte(source);
source++;
int bitcount = 0;
while(1) {
if(bitcount >= 8)
break;
- u32 d = b & mask;
- u32 temp = d >> bitcount;
+ uint32_t d = b & mask;
+ uint32_t temp = d >> bitcount;
if(d || addBase) {
temp += base;
}
@@ -197,32 +197,32 @@
}
#endif
- u32 src = reg[0].I;
- u32 dest = reg[1].I;
+ uint32_t src = reg[0].I;
+ uint32_t dest = reg[1].I;
int num = reg[2].I;
for(int i = 0; i < num; i++) {
- s32 cx = CPUReadMemory(src);
+ int32_t cx = CPUReadMemory(src);
src+=4;
- s32 cy = CPUReadMemory(src);
+ int32_t cy = CPUReadMemory(src);
src+=4;
- s16 dispx = CPUReadHalfWord(src);
+ int16_t dispx = CPUReadHalfWord(src);
src+=2;
- s16 dispy = CPUReadHalfWord(src);
+ int16_t dispy = CPUReadHalfWord(src);
src+=2;
- s16 rx = CPUReadHalfWord(src);
+ int16_t rx = CPUReadHalfWord(src);
src+=2;
- s16 ry = CPUReadHalfWord(src);
+ int16_t ry = CPUReadHalfWord(src);
src+=2;
- u16 theta = CPUReadHalfWord(src)>>8;
+ uint16_t theta = CPUReadHalfWord(src)>>8;
src+=4; // keep structure alignment
- s32 a = sineTable[(theta+0x40)&255];
- s32 b = sineTable[theta];
-
- s16 dx = (rx * a)>>14;
- s16 dmx = (rx * b)>>14;
- s16 dy = (ry * b)>>14;
- s16 dmy = (ry * a)>>14;
+ int32_t a = sineTable[(theta+0x40)&255];
+ int32_t b = sineTable[theta];
+
+ int16_t dx = (rx * a)>>14;
+ int16_t dmx = (rx * b)>>14;
+ int16_t dy = (ry * b)>>14;
+ int16_t dmy = (ry * a)>>14;
CPUWriteHalfWord(dest, dx);
dest += 2;
@@ -233,8 +233,8 @@
CPUWriteHalfWord(dest, dmy);
dest += 2;
- s32 startx = cx - dx * dispx + dmx * dispy;
- s32 starty = cy - dy * dispx - dmy * dispy;
+ int32_t startx = cx - dx * dispx + dmx * dispy;
+ int32_t starty = cy - dy * dispx - dmy * dispy;
CPUWriteMemory(dest, startx);
dest += 4;
@@ -252,9 +252,9 @@
}
#endif
- u32 source = reg[0].I;
- u32 dest = reg[1].I;
- u32 cnt = reg[2].I;
+ uint32_t source = reg[0].I;
+ uint32_t dest = reg[1].I;
+ uint32_t cnt = reg[2].I;
if(((source & 0xe000000) == 0) ||
((source + (((cnt << 11)>>9) & 0x1fffff)) & 0xe000000) == 0)
@@ -269,7 +269,7 @@
dest &= 0xFFFFFFFC;
// fill ?
if((cnt >> 24) & 1) {
- u32 value = (source>0x0EFFFFFF ? 0x1CAD1CAD : CPUReadMemory(source));
+ uint32_t value = (source>0x0EFFFFFF ? 0x1CAD1CAD : CPUReadMemory(source));
while(count) {
CPUWriteMemory(dest, value);
dest += 4;
@@ -287,7 +287,7 @@
} else {
// 16-bit fill?
if((cnt >> 24) & 1) {
- u16 value = (source>0x0EFFFFFF ? 0x1CAD : CPUReadHalfWord(source));
+ uint16_t value = (source>0x0EFFFFFF ? 0x1CAD : CPUReadHalfWord(source));
while(count) {
CPUWriteHalfWord(dest, value);
dest += 2;
@@ -314,9 +314,9 @@
}
#endif
- u32 source = reg[0].I;
- u32 dest = reg[1].I;
- u32 cnt = reg[2].I;
+ uint32_t source = reg[0].I;
+ uint32_t dest = reg[1].I;
+ uint32_t cnt = reg[2].I;
if(((source & 0xe000000) == 0) ||
((source + (((cnt << 11)>>9) & 0x1fffff)) & 0xe000000) == 0)
@@ -332,7 +332,7 @@
if((cnt >> 24) & 1) {
while(count > 0) {
// BIOS always transfers 32 bytes at a time
- u32 value = (source>0x0EFFFFFF ? 0xBAFFFFFB : CPUReadMemory(source));
+ uint32_t value = (source>0x0EFFFFFF ? 0xBAFFFFFB : CPUReadMemory(source));
for(int i = 0; i < 8; i++) {
CPUWriteMemory(dest, value);
dest += 4;
@@ -362,10 +362,10 @@
}
#endif
- u32 source = reg[0].I;
- u32 dest = reg[1].I;
-
- u32 header = CPUReadMemory(source);
+ uint32_t source = reg[0].I;
+ uint32_t dest = reg[1].I;
+
+ uint32_t header = CPUReadMemory(source);
source += 4;
if(((source & 0xe000000) == 0) ||
@@ -374,12 +374,12 @@
int len = header >> 8;
- u8 data = CPUReadByte(source++);
+ uint8_t data = CPUReadByte(source++);
CPUWriteByte(dest++, data);
len--;
while(len > 0) {
- u8 diff = CPUReadByte(source++);
+ uint8_t diff = CPUReadByte(source++);
data += diff;
CPUWriteByte(dest++, data);
len--;
@@ -395,10 +395,10 @@
}
#endif
- u32 source = reg[0].I;
- u32 dest = reg[1].I;
-
- u32 header = CPUReadMemory(source);
+ uint32_t source = reg[0].I;
+ uint32_t dest = reg[1].I;
+
+ uint32_t header = CPUReadMemory(source);
source += 4;
if(((source & 0xe000000) == 0) ||
@@ -407,13 +407,13 @@
int len = header >> 8;
- u8 data = CPUReadByte(source++);
- u16 writeData = data;
+ uint8_t data = CPUReadByte(source++);
+ uint16_t writeData = data;
int shift = 8;
int bytes = 1;
while(len >= 2) {
- u8 diff = CPUReadByte(source++);
+ uint8_t diff = CPUReadByte(source++);
data += diff;
writeData |= (data << shift);
bytes++;
@@ -438,10 +438,10 @@
}
#endif
- u32 source = reg[0].I;
- u32 dest = reg[1].I;
-
- u32 header = CPUReadMemory(source);
+ uint32_t source = reg[0].I;
+ uint32_t dest = reg[1].I;
+
+ uint32_t header = CPUReadMemory(source);
source += 4;
if(((source & 0xe000000) == 0) ||
@@ -450,14 +450,14 @@
int len = header >> 8;
- u16 data = CPUReadHalfWord(source);
+ uint16_t data = CPUReadHalfWord(source);
source += 2;
CPUWriteHalfWord(dest, data);
dest += 2;
len -= 2;
while(len >= 2) {
- u16 diff = CPUReadHalfWord(source);
+ uint16_t diff = CPUReadHalfWord(source);
source += 2;
data += diff;
CPUWriteHalfWord(dest, data);
@@ -483,8 +483,8 @@
if(denom != 0) {
reg[0].I = number / denom;
reg[1].I = number % denom;
- s32 temp = (s32)reg[0].I;
- reg[3].I = temp < 0 ? (u32)-temp : (u32)temp;
+ int32_t temp = (int32_t)reg[0].I;
+ reg[3].I = temp < 0 ? (uint32_t)-temp : (uint32_t)temp;
}
#ifdef GBA_LOGGING
if(systemVerbose & VERBOSE_SWI) {
@@ -506,7 +506,7 @@
}
#endif
- u32 temp = reg[0].I;
+ uint32_t temp = reg[0].I;
reg[0].I = reg[1].I;
reg[1].I = temp;
BIOS_Div();
@@ -523,35 +523,35 @@
}
#endif
- u32 source = reg[0].I;
- u32 dest = reg[1].I;
-
- u32 header = CPUReadMemory(source);
+ uint32_t source = reg[0].I;
+ uint32_t dest = reg[1].I;
+
+ uint32_t header = CPUReadMemory(source);
source += 4;
if(((source & 0xe000000) == 0) ||
((source + ((header >> 8) & 0x1fffff)) & 0xe000000) == 0)
return;
- u8 treeSize = CPUReadByte(source++);
-
- u32 treeStart = source;
+ uint8_t treeSize = CPUReadByte(source++);
+
+ uint32_t treeStart = source;
source += ((treeSize+1)<<1)-1; // minus because we already skipped one byte
int len = header >> 8;
- u32 mask = 0x80000000;
- u32 data = CPUReadMemory(source);
+ uint32_t mask = 0x80000000;
+ uint32_t data = CPUReadMemory(source);
source += 4;
int pos = 0;
- u8 rootNode = CPUReadByte(treeStart);
- u8 currentNode = rootNode;
+ uint8_t rootNode = CPUReadByte(treeStart);
+ uint8_t currentNode = rootNode;
bool writeData = false;
int byteShift = 0;
int byteCount = 0;
- u32 writeValue = 0;
+ uint32_t writeValue = 0;
if((header & 0x0F) == 8) {
while(len > 0) {
@@ -669,10 +669,10 @@
}
#endif
- u32 source = reg[0].I;
- u32 dest = reg[1].I;
-
- u32 header = CPUReadMemory(source);
+ uint32_t source = reg[0].I;
+ uint32_t dest = reg[1].I;
+
+ uint32_t header = CPUReadMemory(source);
source += 4;
if(((source & 0xe000000) == 0) ||
@@ -681,21 +681,21 @@
int byteCount = 0;
int byteShift = 0;
- u32 writeValue = 0;
+ uint32_t writeValue = 0;
int len = header >> 8;
while(len > 0) {
- u8 d = CPUReadByte(source++);
+ uint8_t d = CPUReadByte(source++);
if(d) {
for(int i = 0; i < 8; i++) {
if(d & 0x80) {
- u16 data = CPUReadByte(source++) << 8;
+ uint16_t data = CPUReadByte(source++) << 8;
data |= CPUReadByte(source++);
int length = (data >> 12) + 3;
int offset = (data & 0x0FFF);
- u32 windowOffset = dest + byteCount - offset - 1;
+ uint32_t windowOffset = dest + byteCount - offset - 1;
for(int i2 = 0; i2 < length; i2++) {
writeValue |= (CPUReadByte(windowOffset++) << byteShift);
byteShift += 8;
@@ -758,10 +758,10 @@
}
#endif
- u32 source = reg[0].I;
- u32 dest = reg[1].I;
-
- u32 header = CPUReadMemory(source);
+ uint32_t source = reg[0].I;
+ uint32_t dest = reg[1].I;
+
+ uint32_t header = CPUReadMemory(source);
source += 4;
if(((source & 0xe000000) == 0) ||
@@ -771,16 +771,16 @@
int len = header >> 8;
while(len > 0) {
- u8 d = CPUReadByte(source++);
+ uint8_t d = CPUReadByte(source++);
if(d) {
for(int i = 0; i < 8; i++) {
if(d & 0x80) {
- u16 data = CPUReadByte(source++) << 8;
+ uint16_t data = CPUReadByte(source++) << 8;
data |= CPUReadByte(source++);
int length = (data >> 12) + 3;
int offset = (data & 0x0FFF);
- u32 windowOffset = dest - offset - 1;
+ uint32_t windowOffset = dest - offset - 1;
for(int i2 = 0; i2 < length; i2++) {
CPUWriteByte(dest++, CPUReadByte(windowOffset++));
len--;
@@ -819,26 +819,26 @@
}
#endif
- u32 src = reg[0].I;
- u32 dest = reg[1].I;
+ uint32_t src = reg[0].I;
+ uint32_t dest = reg[1].I;
int num = reg[2].I;
int offset = reg[3].I;
for(int i = 0; i < num; i++) {
- s16 rx = CPUReadHalfWord(src);
+ int16_t rx = CPUReadHalfWord(src);
src+=2;
- s16 ry = CPUReadHalfWord(src);
+ int16_t ry = CPUReadHalfWord(src);
src+=2;
- u16 theta = CPUReadHalfWord(src)>>8;
+ uint16_t theta = CPUReadHalfWord(src)>>8;
src+=4; // keep structure alignment
- s32 a = (s32)sineTable[(theta+0x40)&255];
- s32 b = (s32)sineTable[theta];
-
- s16 dx = ((s32)rx * a)>>14;
- s16 dmx = ((s32)rx * b)>>14;
- s16 dy = ((s32)ry * b)>>14;
- s16 dmy = ((s32)ry * a)>>14;
+ int32_t a = (int32_t)sineTable[(theta+0x40)&255];
+ int32_t b = (int32_t)sineTable[theta];
+
+ int16_t dx = ((int32_t)rx * a)>>14;
+ int16_t dmx = ((int32_t)rx * b)>>14;
+ int16_t dy = ((int32_t)ry * b)>>14;
+ int16_t dmy = ((int32_t)ry * a)>>14;
CPUWriteHalfWord(dest, dx);
dest += offset;
@@ -851,7 +851,7 @@
}
}
-void BIOS_RegisterRamReset(u32 flags)
+void BIOS_RegisterRamReset(uint32_t flags)
{
// no need to trace here. this is only called directly from GBA.cpp
// to emulate bios initialization
@@ -951,10 +951,10 @@
}
#endif
- u32 source = reg[0].I;
- u32 dest = reg[1].I;
-
- u32 header = CPUReadMemory(source & 0xFFFFFFFC);
+ uint32_t source = reg[0].I;
+ uint32_t dest = reg[1].I;
+
+ uint32_t header = CPUReadMemory(source & 0xFFFFFFFC);
source += 4;
if(((source & 0xe000000) == 0) ||
@@ -964,13 +964,13 @@
int len = header >> 8;
int byteCount = 0;
int byteShift = 0;
- u32 writeValue = 0;
+ uint32_t writeValue = 0;
while(len > 0) {
- u8 d = CPUReadByte(source++);
+ uint8_t d = CPUReadByte(source++);
int l = d & 0x7F;
if(d & 0x80) {
- u8 data = CPUReadByte(source++);
+ uint8_t data = CPUReadByte(source++);
l += 3;
for(int i = 0;i < l; i++) {
writeValue |= (data << byteShift);
@@ -1020,10 +1020,10 @@
}
#endif
- u32 source = reg[0].I;
- u32 dest = reg[1].I;
-
- u32 header = CPUReadMemory(source & 0xFFFFFFFC);
+ uint32_t source = reg[0].I;
+ uint32_t dest = reg[1].I;
+
+ uint32_t header = CPUReadMemory(source & 0xFFFFFFFC);
source += 4;
if(((source & 0xe000000) == 0) ||
@@ -1033,10 +1033,10 @@
int len = header >> 8;
while(len > 0) {
- u8 d = CPUReadByte(source++);
+ uint8_t d = CPUReadByte(source++);
int l = d & 0x7F;
if(d & 0x80) {
- u8 data = CPUReadByte(source++);
+ uint8_t data = CPUReadByte(source++);
l += 3;
for(int i = 0;i < l; i++) {
CPUWriteByte(dest++, data);
@@ -1077,7 +1077,7 @@
reg[R13_SVC].I = 0x03007FE0;
reg[R14_SVC].I = 0x00000000;
reg[SPSR_SVC].I = 0x00000000;
- u8 b = internalRAM[0x7ffa];
+ uint8_t b = internalRAM[0x7ffa];
memset(&internalRAM[0x7e00], 0, 0x200);
@@ -1099,7 +1099,7 @@
VCOUNT);
}
#endif
- reg[0].I = (u32)sqrt((double)reg[0].I);
+ reg[0].I = (uint32_t)sqrt((double)reg[0].I);
#ifdef GBA_LOGGING
if(systemVerbose & VERBOSE_SWI) {
log("Sqrt: return=%08x\n",
--- a/src/in_gsf/vbam/gba/bios.h
+++ b/src/in_gsf/vbam/gba/bios.h
@@ -18,7 +18,7 @@
extern void BIOS_LZ77UnCompWram();
extern void BIOS_ObjAffineSet();
extern void BIOS_RegisterRamReset();
-extern void BIOS_RegisterRamReset(u32);
+extern void BIOS_RegisterRamReset(uint32_t);
extern void BIOS_RLUnCompVram();
extern void BIOS_RLUnCompWram();
extern void BIOS_SoftReset();