@@ -322,7 +322,7 @@ struct MMU_struct

 		// an extra 128KB for blank memory, directly after arm9_lcd, so that

 		// we can easily map things to the end of arm9_lcd to represent

 		// an unmapped state

-		uint8_t blank_memory[0x20000];

+		uint8_t blank_memory[0x100000 - 0xA4000];

 	};

 #include "PACKED_END.h"

@@ -82,6 +82,8 @@ enum EDMADestinationUpdate

 class TRegister_32

 {

 public:

+	virtual ~TRegister_32() { }

+

 	virtual uint32_t read32() = 0;

 	virtual void write32(uint32_t val) = 0;

 	void write(int size, uint32_t adr, uint32_t val)

@@ -131,6 +133,7 @@ struct TGXSTAT : public TRegister_32

 		this->fifo_empty = true;

 		this->fifo_low = false;

 	}

+	virtual ~TGXSTAT() { }

 	uint8_t tb; // test busy

 	uint8_t tr; // test result

 	uint8_t se; // stack error

@@ -238,6 +241,7 @@ public:

 		DmaController *controller;

 		uint32_t *const ptr;

 		AddressRegister(uint32_t *_ptr) : ptr(_ptr) { }

+		virtual ~AddressRegister() { }

 		virtual uint32_t read32()

 		{

 			return *this->ptr;

@@ -254,6 +258,7 @@ public:

 		// we pass in a pointer to the controller here so we can alert it if anything changes

 		DmaController *controller;

 		ControlRegister() { }

+		virtual ~ControlRegister() { }

 		virtual uint32_t read32()

 		{

 			return this->controller->read32();

@@ -17,8 +17,7 @@

 	along with the this software.  If not, see <http://www.gnu.org/licenses/>.

 */

-#ifndef MMU_H

-#define MMU_H

+#pragma once

 #include "FIFO.h"

 #include "mem.h"

@@ -812,5 +811,3 @@ template<int PROCNUM, MMU_ACCESS_TYPE AT> inline uint32_t _MMU_read32(uint32_t a

 template<int PROCNUM, MMU_ACCESS_TYPE AT> inline void _MMU_write08(uint32_t addr, uint8_t val) { _MMU_write08(PROCNUM, AT, addr, val); }

 template<int PROCNUM, MMU_ACCESS_TYPE AT> inline void _MMU_write16(uint32_t addr, uint16_t val) { _MMU_write16(PROCNUM, AT, addr, val); }

 template<int PROCNUM, MMU_ACCESS_TYPE AT> inline void _MMU_write32(uint32_t addr, uint32_t val) { _MMU_write32(PROCNUM, AT, addr, val); }

-

-#endif

@@ -26,15 +26,18 @@

 #include "mc.h"

 #include "bits.h"

 #include "readwrite.h"

-//#include "debug.h"

 #ifdef HAVE_LUA

 #include "lua-engine.h"

 #endif

+#ifdef HAVE_JIT

+#include "arm_jit.h"

+#endif

+

 #define ARMCPU_ARM7 1

 #define ARMCPU_ARM9 0

-#define ARMPROC (PROCNUM ? NDS_ARM7:NDS_ARM9)

+#define ARMPROC (PROCNUM ? NDS_ARM7 : NDS_ARM9)

 typedef const uint8_t TWaitState;

@@ -74,61 +77,71 @@ enum EDMADestinationUpdate

 	EDMADestinationUpdate_IncrementReload = 3

 };

-//TODO

-//n.b. this may be a bad idea, for complex registers like the dma control register.

-//we need to know exactly what part was written to, instead of assuming all 32bits were written.

+// TODO

+// n.b. this may be a bad idea, for complex registers like the dma control register.

+// we need to know exactly what part was written to, instead of assuming all 32bits were written.

 class TRegister_32

 {

 public:

 	virtual uint32_t read32() = 0;

-	virtual void write32(const uint32_t val) = 0;

-	void write(const int size, const uint32_t adr, const uint32_t val) {

-		if(size==32) write32(val);

-		else {

-			const uint32_t offset = adr&3;

-			if(size==8) {

+	virtual void write32(uint32_t val) = 0;

+	void write(int size, uint32_t adr, uint32_t val)

+	{

+		if (size == 32)

+			this->write32(val);

+		else

+		{

+			uint32_t offset = adr & 3;

+			if (size == 8)

+			{

 				printf("WARNING! 8BIT DMA ACCESS\n");

-				uint32_t mask = 0xFF<<(offset<<3);

-				write32((read32()&~mask)|(val<<(offset<<3)));

+				uint32_t mask = 0xFF << (offset << 3);

+				this->write32((this->read32() & ~mask) | (val << (offset << 3)));

 			}

-			else if(size==16) {

-				uint32_t mask = 0xFFFF<<(offset<<3);

-				write32((read32()&~mask)|(val<<(offset<<3)));

+			else if (size == 16)

+			{

+				uint32_t mask = 0xFFFF << (offset << 3);

+				this->write32((this->read32() & ~mask) | (val << (offset << 3)));

 			}

 		}

 	}

-	uint32_t read(const int size, const uint32_t adr)

+	uint32_t read(int size, uint32_t adr)

 	{

-		if(size==32) return read32();

-		else {

-			const uint32_t offset = adr&3;

-			if(size==8) { printf("WARNING! 8BIT DMA ACCESS\n"); return (read32()>>(offset<<3))&0xFF; }

-			else return (read32()>>(offset<<3))&0xFFFF;

+		if (size == 32)

+			return this->read32();

+		else

+		{

+			uint32_t offset = adr & 3;

+			if (size == 8)

+			{

+				printf("WARNING! 8BIT DMA ACCESS\n");

+				return (this->read32() >> (offset << 3)) & 0xFF;

+			}

+			else

+				return (this->read32() >> (offset << 3)) & 0xFFFF;

 		}

 	}

 };

 struct TGXSTAT : public TRegister_32

 {

-	TGXSTAT() {

-		gxfifo_irq = se = tr = tb = sb = 0;

-		fifo_empty = true;

-		fifo_low = false;

+	TGXSTAT()

+	{

+		this->gxfifo_irq = this->se = this->tr = this->tb = this->sb = 0;

+		this->fifo_empty = true;

+		this->fifo_low = false;

 	}

-	uint8_t tb; //test busy

-	uint8_t tr; //test result

-	uint8_t se; //stack error

-	uint8_t sb; //stack busy

-	uint8_t gxfifo_irq; //irq configuration

+	uint8_t tb; // test busy

+	uint8_t tr; // test result

+	uint8_t se; // stack error

+	uint8_t sb; // stack busy

+	uint8_t gxfifo_irq; // irq configuration

 	bool fifo_empty, fifo_low;

 	virtual uint32_t read32();

-	virtual void write32(const uint32_t val);

-

-	//void savestate(EMUFILE *f);

-	bool loadstate(EMUFILE *f);

+	virtual void write32(uint32_t val);

 };

 void triggerDma(EDMAMode mode);

@@ -136,54 +149,25 @@ void triggerDma(EDMAMode mode);

 class DivController

 {

 public:

-	DivController()

-		: mode(0), busy(0)

-	{}

+	DivController() : mode(0), busy(0) { }

 	void exec();

 	uint8_t mode, busy, div0;

-	uint16_t read16() { return mode|(busy<<15)|(div0<<14); }

-	void write16(uint16_t val) {

-		mode = val&3;

-		//todo - do we clear the div0 flag here or is that strictly done by the divider unit?

-	}

-	/*void savestate(EMUFILE* os)

+	uint16_t read16() { return this->mode | (this->busy << 15) | (this->div0 << 14); }

+	void write16(uint16_t val)

 	{

-		write8le(&mode,os);

-		write8le(&busy,os);

-		write8le(&div0,os);

-	}*/

-	bool loadstate(EMUFILE* is, int)

-	{

-		int ret = 1;

-		ret &= read8le(&mode,is);

-		ret &= read8le(&busy,is);

-		ret &= read8le(&div0,is);

-		return ret==1;

+		this->mode = val & 3;

+		// todo - do we clear the div0 flag here or is that strictly done by the divider unit?

 	}

 };

 class SqrtController

 {

 public:

-	SqrtController()

-		: mode(0), busy(0)

-	{}

+	SqrtController() : mode(0), busy(0) { }

 	void exec();

 	uint8_t mode, busy;

-	uint16_t read16() { return mode|(busy<<15); }

-	void write16(uint16_t val) { mode = val&1; }

-	/*void savestate(EMUFILE* os)

-	{

-		write8le(&mode,os);

-		write8le(&busy,os);

-	}*/

-	bool loadstate(EMUFILE* is, int)

-	{

-		int ret=1;

-		ret &= read8le(&mode,is);

-		ret &= read8le(&busy,is);

-		return ret==1;

-	}

+	uint16_t read16() { return this->mode | (this->busy << 15); }

+	void write16(uint16_t val) { this->mode = val & 1; }

 };

 class DmaController

@@ -199,26 +183,23 @@ public:

 	uint32_t saddr, daddr;

 	uint32_t saddr_user, daddr_user;

-	//indicates whether the dma needs to be checked for triggering

+	// indicates whether the dma needs to be checked for triggering

 	bool dmaCheck;

-	//indicates whether the dma right now is logically running

-	//(though for now we copy all the data when it triggers)

+	// indicates whether the dma right now is logically running

+	// (though for now we copy all the data when it triggers)

 	bool running;

 	bool paused;

-	//this flag will sometimes be set when a start condition is triggered

-	//other conditions may be automatically triggered based on scanning conditions

+	// this flag will sometimes be set when a start condition is triggered

+	// other conditions may be automatically triggered based on scanning conditions

 	bool triggered;

 	uint64_t nextEvent;

 	int procnum, chan;

-	//void savestate(EMUFILE *f);

-	bool loadstate(EMUFILE *f);

-

 	void exec();

 	template<int PROCNUM> void doCopy();

 	void doPause();

@@ -231,8 +212,8 @@ public:

 		wordcount(0), startmode(EDMAMode_Immediate),

 		bitWidth(EDMABitWidth_16),

 		sar(EDMASourceUpdate_Increment), dar(EDMADestinationUpdate_Increment),

-		//if saddr isnt cleared then rings of fate will trigger copy protection

-		//by inspecting dma3 saddr when it boots

+		// if saddr isnt cleared then rings of fate will trigger copy protection

+		// by inspecting dma3 saddr when it boots

 		saddr(0), daddr(0),

 		saddr_user(0), daddr_user(0),

 		dmaCheck(false),

@@ -243,50 +224,53 @@ public:

 		sad(&saddr_user),

 		dad(&daddr_user)

 	{

-		sad.controller = this;

-		dad.controller = this;

-		ctrl.controller = this;

-		regs[0] = &sad;

-		regs[1] = &dad;

-		regs[2] = &ctrl;

+		this->sad.controller = this;

+		this->dad.controller = this;

+		this->ctrl.controller = this;

+		this->regs[0] = &this->sad;

+		this->regs[1] = &this->dad;

+		this->regs[2] = &this->ctrl;

 	}

-	class AddressRegister : public TRegister_32 {

+	class AddressRegister : public TRegister_32

+	{

 	public:

-		//we pass in a pointer to the controller here so we can alert it if anything changes

-		DmaController* controller;

-		uint32_t * const ptr;

-		AddressRegister(uint32_t* _ptr)

-			: ptr(_ptr)

-		{}

-		virtual uint32_t read32() {

-			return *ptr;

+		// we pass in a pointer to the controller here so we can alert it if anything changes

+		DmaController *controller;

+		uint32_t *const ptr;

+		AddressRegister(uint32_t *_ptr) : ptr(_ptr) { }

+		virtual uint32_t read32()

+		{

+			return *this->ptr;

 		}

-		virtual void write32(const uint32_t val) {

-			*ptr = val;

+		virtual void write32(uint32_t val)

+		{

+			*this->ptr = val;

 		}

 	};

-	class ControlRegister : public TRegister_32 {

+	class ControlRegister : public TRegister_32

+	{

 	public:

-		//we pass in a pointer to the controller here so we can alert it if anything changes

-		DmaController* controller;

-		ControlRegister() {}

-		virtual uint32_t read32() {

-			return controller->read32();

+		// we pass in a pointer to the controller here so we can alert it if anything changes

+		DmaController *controller;

+		ControlRegister() { }

+		virtual uint32_t read32()

+		{

+			return this->controller->read32();

 		}

-		virtual void write32(const uint32_t val) {

-			return controller->write32(val);

+		virtual void write32(uint32_t val)

+		{

+			return this->controller->write32(val);

 		}

 	};

 	AddressRegister sad, dad;

 	ControlRegister ctrl;

-	TRegister_32* regs[3];

+	TRegister_32 *regs[3];

-	void write32(const uint32_t val);

+	void write32(uint32_t val);

 	uint32_t read32();

-

 };

 enum ECardMode

@@ -296,9 +280,8 @@ enum ECardMode

 	CardMode_KEY2

 };

-typedef struct

+struct nds_dscard

 {

-

 	uint8_t command[8];

 	uint32_t address;

@@ -308,68 +291,74 @@ typedef struct

 	// NJSD stuff

 	int blocklen;

+};

-} nds_dscard;

+#define DUP2(x)  x, x

+#define DUP4(x)  x, x, x, x

+#define DUP8(x)  x, x, x, x,  x, x, x, x

+#define DUP16(x) x, x, x, x,  x, x, x, x,  x, x, x, x,  x, x, x, x

 struct MMU_struct

 {

 	//ARM9 mem

 	uint8_t ARM9_ITCM[0x8000];

-    uint8_t ARM9_DTCM[0x4000];

+	uint8_t ARM9_DTCM[0x4000];

-	//u8 MAIN_MEM[4*1024*1024]; //expanded from 4MB to 8MB to support debug consoles

-	//u8 MAIN_MEM[8*1024*1024]; //expanded from 8MB to 16MB to support dsi

-	uint8_t MAIN_MEM[16*1024*1024]; //expanded from 8MB to 16MB to support dsi

-    uint8_t ARM9_REG[0x1000000];

-    uint8_t ARM9_BIOS[0x8000];

-    uint8_t ARM9_VMEM[0x800];

+	//u8 MAIN_MEM[4*1024*1024]; // expanded from 4MB to 8MB to support debug consoles

+	//u8 MAIN_MEM[8*1024*1024]; // expanded from 8MB to 16MB to support dsi

+	uint8_t MAIN_MEM[16*1024*1024]; // expanded from 8MB to 16MB to support dsi

+	uint8_t ARM9_REG[0x1000000];

+	uint8_t ARM9_BIOS[0x8000];

+	uint8_t ARM9_VMEM[0x800];

-	#include "PACKED.h"

-	struct {

+#include "PACKED.h"

+	struct

+	{

 		uint8_t ARM9_LCD[0xA4000];

-		//an extra 128KB for blank memory, directly after arm9_lcd, so that

-		//we can easily map things to the end of arm9_lcd to represent

-		//an unmapped state

+		// an extra 128KB for blank memory, directly after arm9_lcd, so that

+		// we can easily map things to the end of arm9_lcd to represent

+		// an unmapped state

 		uint8_t blank_memory[0x20000];

 	};

-	#include "PACKED_END.h"

+#include "PACKED_END.h"

-    uint8_t ARM9_OAM[0x800];

+	uint8_t ARM9_OAM[0x800];

-	uint8_t* ExtPal[2][4];

-	uint8_t* ObjExtPal[2][2];

+	uint8_t *ExtPal[2][4];

+	uint8_t *ObjExtPal[2][2];

-	struct TextureInfo {

-		uint8_t* texPalSlot[6];

-		uint8_t* textureSlotAddr[4];

+	struct TextureInfo

+	{

+		uint8_t *texPalSlot[6];

+		uint8_t *textureSlotAddr[4];

 	} texInfo;

-	//ARM7 mem

+	// ARM7 mem

 	uint8_t ARM7_BIOS[0x4000];

-	uint8_t ARM7_ERAM[0x10000];

+	uint8_t ARM7_ERAM[0x10000]; // 64KB of exclusive WRAM

 	uint8_t ARM7_REG[0x10000];

-	uint8_t ARM7_WIRAM[0x10000];

+	uint8_t ARM7_WIRAM[0x10000]; // WIFI ram

 	// VRAM mapping

 	uint8_t VRAM_MAP[4][32];

 	uint32_t LCD_VRAM_ADDR[10];

 	uint8_t LCDCenable[10];

-	//Shared ram

+	// 32KB of shared WRAM - can be switched between ARM7 & ARM9 in two blocks

 	uint8_t SWIRAM[0x8000];

-	//Card rom & ram

+	// Card rom & ram

 	uint8_t * CART_ROM;

-	//Unused ram

+	// Unused ram

 	uint8_t UNUSED_RAM[4];

-	//this is here so that we can trap glitchy emulator code

-	//which is accessing offsets 5,6,7 of unused ram due to unaligned accesses

-	//(also since the emulator doesn't prevent unaligned accesses)

+	// this is here so that we can trap glitchy emulator code

+	// which is accessing offsets 5,6,7 of unused ram due to unaligned accesses

+	// (also since the emulator doesn't prevent unaligned accesses)

 	uint8_t MORE_UNUSED_RAM[4];

-	static uint8_t * MMU_MEM[2][256];

+	static uint8_t *MMU_MEM[2][256];

 	static uint32_t MMU_MASK[2][256];

 	uint8_t ARM9_RW_MODE;

@@ -386,13 +375,11 @@ struct MMU_struct

 	uint32_t reg_IME[2];

 	uint32_t reg_IE[2];

-	//these are the user-controlled IF bits. some IF bits are generated as necessary from hardware conditions

+	// these are the user-controlled IF bits. some IF bits are generated as necessary from hardware conditions

 	uint32_t reg_IF_bits[2];

-	//these flags are set occasionally to indicate that an irq should have entered the pipeline, and processing will be deferred a tiny bit to help emulate things

+	// these flags are set occasionally to indicate that an irq should have entered the pipeline, and processing will be deferred a tiny bit to help emulate things

 	uint32_t reg_IF_pending[2];

-	//uint32_t reg_DISP3DCNT_bits;

-

 	template<int PROCNUM> uint32_t gen_IF();

 	bool divRunning;

@@ -409,7 +396,7 @@ struct MMU_struct

 	uint16_t AUX_SPI_CNT;

 	uint16_t AUX_SPI_CMD;

-	//uint64_t gfx3dCycles;

+	uint8_t WRAMCNT;

 	uint8_t powerMan_CntReg;

 	bool powerMan_CntRegWritten;

@@ -420,16 +407,13 @@ struct MMU_struct

 	nds_dscard dscard[2];

 };

-//everything in here is derived from libnds behaviours. no hardware tests yet

+// everything in here is derived from libnds behaviours. no hardware tests yet

 class DSI_TSC

 {

 public:

 	DSI_TSC();

 	void reset_command();

 	uint16_t write16(uint16_t val);

-	//bool save_state(EMUFILE* os);

-	//bool load_state(EMUFILE* is);

-

 private:

 	uint16_t read16();

 	uint8_t reg_selection;

@@ -437,17 +421,17 @@ private:

 	int32_t state;

 	int32_t readcount;

-	//registers[0] contains the current page.

-	//we are going to go ahead and save these out in case we want to change the way this is emulated in the future..

-	//we may want to poke registers in here at more convenient times and have the TSC dumbly pluck them out,

-	//rather than generate the values on the fly

+	// registers[0] contains the current page.

+	// we are going to go ahead and save these out in case we want to change the way this is emulated in the future..

+	// we may want to poke registers in here at more convenient times and have the TSC dumbly pluck them out,

+	// rather than generate the values on the fly

 	uint8_t registers[0x80];

 };

-//this contains things which can't be memzeroed because they are smarter classes

+// this contains things which can't be memzeroed because they are smarter classes

 struct MMU_struct_new

 {

-	MMU_struct_new() ;

+	MMU_struct_new();

 	BackupDevice backupDevice;

 	DmaController dma[2][4];

 	TGXSTAT gxstat;

@@ -455,65 +439,22 @@ struct MMU_struct_new

 	DivController div;

 	DSI_TSC dsi_tsc;

-	void write_dma(const int proc, const int size, const uint32_t adr, const uint32_t val);

-	uint32_t read_dma(const int proc, const int size, const uint32_t adr);

-	bool is_dma(const uint32_t adr) { return adr >= _REG_DMA_CONTROL_MIN && adr <= _REG_DMA_CONTROL_MAX; }

+	void write_dma(int proc, int size, uint32_t adr, uint32_t val);

+	uint32_t read_dma(int proc, int size, uint32_t adr);

+	bool is_dma(uint32_t adr) { return adr >= _REG_DMA_CONTROL_MIN && adr <= _REG_DMA_CONTROL_MAX; }

 };

 extern MMU_struct MMU;

 extern MMU_struct_new MMU_new;

-

-/*struct armcpu_memory_iface {*/

-  /** the 32 bit instruction prefetch */

-  //uint32_t FASTCALL (*prefetch32)( void *data, uint32_t adr);

-

-  /** the 16 bit instruction prefetch */

-  //uint16_t FASTCALL (*prefetch16)( void *data, uint32_t adr);

-

-  /** read 8 bit data value */

-  //uint8_t FASTCALL (*read8)( void *data, uint32_t adr);

-  /** read 16 bit data value */

-  //uint16_t FASTCALL (*read16)( void *data, uint32_t adr);

-  /** read 32 bit data value */

-  //uint32_t FASTCALL (*read32)( void *data, uint32_t adr);

-

-  /** write 8 bit data value */

-  //void FASTCALL (*write8)( void *data, uint32_t adr, uint8_t val);

-  /** write 16 bit data value */

-  //void FASTCALL (*write16)( void *data, uint32_t adr, uint16_t val);

-  /** write 32 bit data value */

-  /*void FASTCALL (*write32)( void *data, uint32_t adr, uint32_t val);

-

-  void *data;

-};*/

-

-

 void MMU_Init();

 void MMU_DeInit();

 void MMU_Reset();

-void MMU_setRom(uint8_t * rom, uint32_t mask);

+void MMU_setRom(uint8_t *rom, uint32_t mask);

 void MMU_unsetRom();

-//void print_memory_profiling();

-

-// Memory reading/writing (old)

-//uint8_t FASTCALL MMU_read8(uint32_t proc, uint32_t adr);

-//uint16_t FASTCALL MMU_read16(uint32_t proc, uint32_t adr);

-//uint32_t FASTCALL MMU_read32(uint32_t proc, uint32_t adr);

-//void FASTCALL MMU_write8(uint32_t proc, uint32_t adr, uint8_t val);

-//void FASTCALL MMU_write16(uint32_t proc, uint32_t adr, uint16_t val);

-//void FASTCALL MMU_write32(uint32_t proc, uint32_t adr, uint32_t val);

-

-//template<int PROCNUM> void FASTCALL MMU_doDMA(uint32_t num);

-

-//The base ARM memory interfaces

-//extern struct armcpu_memory_iface arm9_base_memory_iface;

-//extern struct armcpu_memory_iface arm7_base_memory_iface;

-//extern struct armcpu_memory_iface arm9_direct_memory_iface;

-

 #define VRAM_BANKS 9

 #define VRAM_BANK_A 0

 #define VRAM_BANK_B 1

@@ -530,54 +471,46 @@ void MMU_unsetRom();

 #define VRAM_PAGE_AOBJ 256

 #define VRAM_PAGE_BOBJ 384

-

-struct VramConfiguration {

-

-	enum Purpose {

-		OFF, INVALID, ABG, BBG, AOBJ, BOBJ, LCDC, ARM7, TEX, TEXPAL, ABGEXTPAL, BBGEXTPAL, AOBJEXTPAL, BOBJEXTPAL

+struct VramConfiguration

+{

+	enum Purpose

+	{

+		OFF,

+		INVALID,

+		ABG,

+		BBG,

+		AOBJ,

+		BOBJ,

+		LCDC,

+		ARM7,

+		TEX,

+		TEXPAL,

+		ABGEXTPAL,

+		BBGEXTPAL,

+		AOBJEXTPAL,

+		BOBJEXTPAL

 	};

-	struct BankInfo {

+	struct BankInfo

+	{

 		Purpose purpose;

 		int ofs;

 	} banks[VRAM_BANKS];

-	inline void clear() {

-		for(int i=0;i<VRAM_BANKS;i++) {

+	void clear()

+	{

+		for (int i = 0; i < VRAM_BANKS; ++i)

+		{

 			banks[i].ofs = 0;

 			banks[i].purpose = OFF;

 		}

 	}

-

-	//std::string describePurpose(Purpose p);

-	//std::string describe();

 };

 extern VramConfiguration vramConfiguration;

-#define VRAM_ARM9_PAGES 512

+const int VRAM_ARM9_PAGES = 512;

 extern uint8_t vram_arm9_map[VRAM_ARM9_PAGES];

-/*inline void* MMU_gpu_map(uint32_t vram_addr)

-{

-	//this is supposed to map a single gpu vram address to emulator host memory

-	//but it returns a pointer to some zero memory in case of accesses to unmapped memory.

-	//this correctly handles the case with tile accesses to unmapped memory.

-	//it could also potentially go through a different LUT than vram_arm9_map in case we discover

-	//that it needs to be set up with different or no mirroring

-	//(I think it is a reasonable possibility that only the cpu has the nutty mirroring rules)

-	//

-	//if this system isn't used, Fantasy Aquarium displays garbage in the first ingame screen

-	//due to it storing 0x0F0F or somesuch in screen memory which points to a ridiculously big tile

-	//which should contain all 0 pixels

-

-	uint32_t vram_page = (vram_addr>>14)&(VRAM_ARM9_PAGES-1);

-	uint32_t ofs = vram_addr & 0x3FFF;

-	vram_page = vram_arm9_map[vram_page];

-	//blank pages are handled by the extra 16KB of blank memory at the end of ARM9_LCD

-	//and the fact that blank pages are mapped to appear at that location

-	return MMU.ARM9_LCD + (vram_page<<14) + ofs;

-}*/

-

 template<int PROCNUM, MMU_ACCESS_TYPE AT> uint8_t _MMU_read08(uint32_t addr);

 template<int PROCNUM, MMU_ACCESS_TYPE AT> uint16_t _MMU_read16(uint32_t addr);

@@ -612,191 +545,161 @@ extern uint32_t partie;

 extern uint32_t _MMU_MAIN_MEM_MASK;

 extern uint32_t _MMU_MAIN_MEM_MASK16;

 extern uint32_t _MMU_MAIN_MEM_MASK32;

-/*inline void SetupMMU(bool debugConsole) {

-	if(debugConsole) _MMU_MAIN_MEM_MASK = 0x7FFFFF;

-	else _MMU_MAIN_MEM_MASK = 0x3FFFFF;

-	_MMU_MAIN_MEM_MASK16 = _MMU_MAIN_MEM_MASK & ~1;

-	_MMU_MAIN_MEM_MASK32 = _MMU_MAIN_MEM_MASK & ~3;

-}*/

 void SetupMMU(bool debugConsole, bool dsi);

-/*inline void CheckMemoryDebugEvent(EDEBUG_EVENT event, const MMU_ACCESS_TYPE type, const uint32_t procnum, const uint32_t addr, const uint32_t size, const uint32_t val)

-{

-	//TODO - ugh work out a better prefetch event system

-	if(type == MMU_AT_CODE && event == DEBUG_EVENT_READ)

-		event = DEBUG_EVENT_EXECUTE;

-	if(CheckDebugEvent(event))

-	{

-		DebugEventData.memAccessType = type;

-		DebugEventData.procnum = procnum;

-		DebugEventData.addr = addr;

-		DebugEventData.size = size;

-		DebugEventData.val = val;

-		HandleDebugEvent(event);

-	}

-}*/

-

-

-//ALERT!!!!!!!!!!!!!!

-//the following inline functions dont do the 0x0FFFFFFF mask.

-//this may result in some unexpected behavior

+// ALERT!!!!!!!!!!!!!!

+// the following inline functions dont do the 0x0FFFFFFF mask.

+// this may result in some unexpected behavior

-inline uint8_t _MMU_read08(const int PROCNUM, const MMU_ACCESS_TYPE AT, const uint32_t addr)

+inline uint8_t _MMU_read08(int PROCNUM, MMU_ACCESS_TYPE AT, uint32_t addr)

 {

-	//CheckMemoryDebugEvent(DEBUG_EVENT_READ,AT,PROCNUM,addr,8,0);

-

-	//special handling for DMA: read 0 from TCM

-	if(PROCNUM==ARMCPU_ARM9 && AT == MMU_AT_DMA)

+	// special handling for DMA: read 0 from TCM

+	if (PROCNUM == ARMCPU_ARM9 && AT == MMU_AT_DMA)

 	{

-		if(addr<0x02000000) return 0; //itcm

-		if((addr&(~0x3FFF)) == MMU.DTCMRegion) return 0; //dtcm

+		if (addr < 0x02000000)

+			return 0; // itcm

+		if ((addr & ~0x3FFF) == MMU.DTCMRegion)

+			return 0; // dtcm

 	}

 #ifdef HAVE_LUA

 	CallRegisteredLuaMemHook(addr, 1, /*FIXME*/ 0, LUAMEMHOOK_READ);

 #endif

-	if(PROCNUM==ARMCPU_ARM9)

-		if((addr&(~0x3FFF)) == MMU.DTCMRegion)

-		{

-			//Returns data from DTCM (ARM9 only)

-			return T1ReadByte(MMU.ARM9_DTCM, addr & 0x3FFF);

-		}

+	if (PROCNUM == ARMCPU_ARM9 && (addr & ~0x3FFF) == MMU.DTCMRegion)

+		// Returns data from DTCM (ARM9 only)

+		return T1ReadByte(MMU.ARM9_DTCM, addr & 0x3FFF);

-	if ( (addr & 0x0F000000) == 0x02000000)

-		return T1ReadByte( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK);

+	if ((addr & 0x0F000000) == 0x02000000)

+		return T1ReadByte(MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK);

-	if(PROCNUM==ARMCPU_ARM9) return _MMU_ARM9_read08(addr);

-	else return _MMU_ARM7_read08(addr);

+	if (PROCNUM == ARMCPU_ARM9)

+		return _MMU_ARM9_read08(addr);

+	else

+		return _MMU_ARM7_read08(addr);

 }

-inline uint16_t _MMU_read16(const int PROCNUM, const MMU_ACCESS_TYPE AT, const uint32_t addr)

+inline uint16_t _MMU_read16(int PROCNUM, MMU_ACCESS_TYPE AT, uint32_t addr)

 {

-	//CheckMemoryDebugEvent(DEBUG_EVENT_READ,AT,PROCNUM,addr,16,0);

-

-	//special handling for DMA: read 0 from TCM

-	if(PROCNUM==ARMCPU_ARM9 && AT == MMU_AT_DMA)

+	// special handling for DMA: read 0 from TCM

+	if (PROCNUM == ARMCPU_ARM9 && AT == MMU_AT_DMA)

 	{

-		if(addr<0x02000000) return 0; //itcm

-		if((addr&(~0x3FFF)) == MMU.DTCMRegion) return 0; //dtcm

+		if (addr < 0x02000000)

+			return 0; // itcm

+		if ((addr & ~0x3FFF) == MMU.DTCMRegion)

+			return 0; // dtcm

 	}

 #ifdef HAVE_LUA

 	CallRegisteredLuaMemHook(addr, 2, /*FIXME*/ 0, LUAMEMHOOK_READ);

 #endif

-	//special handling for execution from arm9, since we spend so much time in there

-	if(PROCNUM==ARMCPU_ARM9 && AT == MMU_AT_CODE)

+	// special handling for execution from arm9, since we spend so much time in there

+	if (PROCNUM == ARMCPU_ARM9 && AT == MMU_AT_CODE)

 	{

 		if ((addr & 0x0F000000) == 0x02000000)

-			return T1ReadWord_guaranteedAligned( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK16);

+			return T1ReadWord_guaranteedAligned(MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK16);

-		if(addr<0x02000000)

+		if (addr < 0x02000000)

 			return T1ReadWord_guaranteedAligned(MMU.ARM9_ITCM, addr&0x7FFE);

 		goto dunno;

 	}

-	if(PROCNUM==ARMCPU_ARM9)

-		if((addr&(~0x3FFF)) == MMU.DTCMRegion)

-		{

-			//Returns data from DTCM (ARM9 only)

-			return T1ReadWord_guaranteedAligned(MMU.ARM9_DTCM, addr & 0x3FFE);

-		}

+	if (PROCNUM == ARMCPU_ARM9 && (addr & ~0x3FFF) == MMU.DTCMRegion)

+		// Returns data from DTCM (ARM9 only)

+		return T1ReadWord_guaranteedAligned(MMU.ARM9_DTCM, addr & 0x3FFE);

-	if ( (addr & 0x0F000000) == 0x02000000)

-		return T1ReadWord_guaranteedAligned( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK16);

+	if ((addr & 0x0F000000) == 0x02000000)

+		return T1ReadWord_guaranteedAligned(MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK16);

 dunno:

-	if(PROCNUM==ARMCPU_ARM9) return _MMU_ARM9_read16(addr);

-	else return _MMU_ARM7_read16(addr);

+	if (PROCNUM == ARMCPU_ARM9)

+		return _MMU_ARM9_read16(addr);

+	else

+		return _MMU_ARM7_read16(addr);

 }

-inline uint32_t _MMU_read32(const int PROCNUM, const MMU_ACCESS_TYPE AT, const uint32_t addr)

+inline uint32_t _MMU_read32(int PROCNUM, MMU_ACCESS_TYPE AT, uint32_t addr)

 {

-	//CheckMemoryDebugEvent(DEBUG_EVENT_READ,AT,PROCNUM,addr,32,0);

-

-	//special handling for DMA: read 0 from TCM

-	if(PROCNUM==ARMCPU_ARM9 && AT == MMU_AT_DMA)

+	// special handling for DMA: read 0 from TCM

+	if (PROCNUM == ARMCPU_ARM9 && AT == MMU_AT_DMA)

 	{

-		if(addr<0x02000000) return 0; //itcm

-		if((addr&(~0x3FFF)) == MMU.DTCMRegion) return 0; //dtcm

+		if (addr < 0x02000000)

+			return 0; // itcm

+		if ((addr & ~0x3FFF) == MMU.DTCMRegion)

+			return 0; // dtcm

 	}

 #ifdef HAVE_LUA

 	CallRegisteredLuaMemHook(addr, 4, /*FIXME*/ 0, LUAMEMHOOK_READ);

 #endif

-	//special handling for execution from arm9, since we spend so much time in there

-	if(PROCNUM==ARMCPU_ARM9 && AT == MMU_AT_CODE)

+	//s pecial handling for execution from arm9, since we spend so much time in there

+	if (PROCNUM == ARMCPU_ARM9 && AT == MMU_AT_CODE)

 	{

-		if ( (addr & 0x0F000000) == 0x02000000)

-			return T1ReadLong_guaranteedAligned( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK32);

+		if ((addr & 0x0F000000) == 0x02000000)

+			return T1ReadLong_guaranteedAligned(MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK32);

-		if(addr<0x02000000)