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* Fixes for gcc and clang (while they can compile the code, the DLLs made aren't functional, but oh well).

* [2SF] Used more up-to-date asmjit, despite the ugly looking code.

Naram Qashat authored on 2014/09/17 19:51:45
Showing 1 changed files
src/in_snsf/snes9x/ppu.h
History View file @ 9315374
... ... 
@@ -281,13 +281,13 @@ struct SnesModel
281 281 
 extern SnesModel *Model;
282 282 
 extern SnesModel M1SNES;
283 283
284 
-inline void REGISTER_2104(uint8_t Byte)
284 
+inline void REGISTER_2104(uint8_t Byt)
285 285 
 {
286 286 
 	if (PPU.OAMAddr & 0x100)
287 287 
 	{
288 288 
 		int addr = ((PPU.OAMAddr & 0x10f) << 1) + (PPU.OAMFlip & 1);
289 
-		if (Byte != PPU.OAMData[addr])
290 
-			PPU.OAMData[addr] = Byte;
289 
+		if (Byt != PPU.OAMData[addr])
290 
+			PPU.OAMData[addr] = Byt;
291 291
292 292 
 		PPU.OAMFlip ^= 1;
293 293 
 		if (!(PPU.OAMFlip & 1))
... ... 
@@ -301,15 +301,15 @@ inline void REGISTER_2104(uint8_t Byte)
301 301 
 	else if (!(PPU.OAMFlip & 1))
302 302 
 	{
303 303 
 		PPU.OAMWriteRegister &= 0xff00;
304 
-		PPU.OAMWriteRegister |= Byte;
304 
+		PPU.OAMWriteRegister |= Byt;
305 305 
 		PPU.OAMFlip |= 1;
306 306 
 	}
307 307 
 	else
308 308 
 	{
309 309 
 		PPU.OAMWriteRegister &= 0x00ff;
310 310 
 		uint8_t lowbyte = static_cast<uint8_t>(PPU.OAMWriteRegister);
311 
-		uint8_t highbyte = Byte;
312 
-		PPU.OAMWriteRegister |= Byte << 8;
311 
+		uint8_t highbyte = Byt;
312 
+		PPU.OAMWriteRegister |= Byt << 8;
313 313
314 314 
 		int addr = PPU.OAMAddr << 1;
315 315 
 		if (lowbyte != PPU.OAMData[addr] || highbyte != PPU.OAMData[addr + 1])
... ... 
@@ -328,7 +328,7 @@ inline void REGISTER_2104(uint8_t Byte)
328 328 
 // This code is correct, however due to Snes9x's inaccurate timings, some games might be broken by this chage. :(
329 329 
 inline bool CHECK_INBLANK() { return Settings.BlockInvalidVRAMAccess && !PPU.ForcedBlanking && CPU.V_Counter < PPU.ScreenHeight + FIRST_VISIBLE_LINE; }
330 330
331 
-inline void REGISTER_2118(uint8_t Byte)
331 
+inline void REGISTER_2118(uint8_t Byt)
332 332 
 {
333 333 
 	if (CHECK_INBLANK())
334 334 
 		return;
... ... 
@@ -339,16 +339,16 @@ inline void REGISTER_2118(uint8_t Byte)
339 339 
 	{
340 340 
 		uint32_t rem = PPU.VMA.Address & PPU.VMA.Mask1;
341 341 
 		address = (((PPU.VMA.Address & ~PPU.VMA.Mask1) + (rem >> PPU.VMA.Shift) + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) & 0xffff;
342 
-		Memory.VRAM[address] = Byte;
342 
+		Memory.VRAM[address] = Byt;
343 343 
 	}
344 344 
 	else
345 
-		Memory.VRAM[address = (PPU.VMA.Address << 1) & 0xffff] = Byte;
345 
+		Memory.VRAM[address = (PPU.VMA.Address << 1) & 0xffff] = Byt;
346 346
347 347 
 	if (!PPU.VMA.High)
348 348 
 		PPU.VMA.Address += PPU.VMA.Increment;
349 349 
 }
350 350
351 
-inline void REGISTER_2119(uint8_t Byte)
351 
+inline void REGISTER_2119(uint8_t Byt)
352 352 
 {
353 353 
 	if (CHECK_INBLANK())
354 354 
 		return;
... ... 
@@ -359,16 +359,16 @@ inline void REGISTER_2119(uint8_t Byte)
359 359 
 	{
360 360 
 		uint32_t rem = PPU.VMA.Address & PPU.VMA.Mask1;
361 361 
 		address = ((((PPU.VMA.Address & ~PPU.VMA.Mask1) + (rem >> PPU.VMA.Shift) + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) + 1) & 0xffff;
362 
-		Memory.VRAM[address] = Byte;
362 
+		Memory.VRAM[address] = Byt;
363 363 
 	}
364 364 
 	else
365 
-		Memory.VRAM[address = ((PPU.VMA.Address << 1) + 1) & 0xffff] = Byte;
365 
+		Memory.VRAM[address = ((PPU.VMA.Address << 1) + 1) & 0xffff] = Byt;
366 366
367 367 
 	if (PPU.VMA.High)
368 368 
 		PPU.VMA.Address += PPU.VMA.Increment;
369 369 
 }
370 370
371 
-inline void REGISTER_2118_tile(uint8_t Byte)
371 
+inline void REGISTER_2118_tile(uint8_t Byt)
372 372 
 {
373 373 
 	if (CHECK_INBLANK())
374 374 
 		return;
... ... 
@@ -376,13 +376,13 @@ inline void REGISTER_2118_tile(uint8_t Byte)
376 376 
 	uint32_t rem = PPU.VMA.Address & PPU.VMA.Mask1;
377 377 
 	uint32_t address = (((PPU.VMA.Address & ~PPU.VMA.Mask1) + (rem >> PPU.VMA.Shift) + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) & 0xffff;
378 378
379 
-	Memory.VRAM[address] = Byte;
379 
+	Memory.VRAM[address] = Byt;
380 380
381 381 
 	if (!PPU.VMA.High)
382 382 
 		PPU.VMA.Address += PPU.VMA.Increment;
383 383 
 }
384 384
385 
-inline void REGISTER_2119_tile(uint8_t Byte)
385 
+inline void REGISTER_2119_tile(uint8_t Byt)
386 386 
 {
387 387 
 	if (CHECK_INBLANK())
388 388 
 		return;
... ... 
@@ -390,41 +390,41 @@ inline void REGISTER_2119_tile(uint8_t Byte)
390 390 
 	uint32_t rem = PPU.VMA.Address & PPU.VMA.Mask1;
391 391 
 	uint32_t address = ((((PPU.VMA.Address & ~PPU.VMA.Mask1) + (rem >> PPU.VMA.Shift) + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) + 1) & 0xffff;
392 392
393 
-	Memory.VRAM[address] = Byte;
393 
+	Memory.VRAM[address] = Byt;
394 394
395 395 
 	if (PPU.VMA.High)
396 396 
 		PPU.VMA.Address += PPU.VMA.Increment;
397 397 
 }
398 398
399 
-inline void REGISTER_2118_linear(uint8_t Byte)
399 
+inline void REGISTER_2118_linear(uint8_t Byt)
400 400 
 {
401 401 
 	if (CHECK_INBLANK())
402 402 
 		return;
403 403
404 404 
 	uint32_t address;
405 405
406 
-	Memory.VRAM[address = (PPU.VMA.Address << 1) & 0xffff] = Byte;
406 
+	Memory.VRAM[address = (PPU.VMA.Address << 1) & 0xffff] = Byt;
407 407
408 408 
 	if (!PPU.VMA.High)
409 409 
 		PPU.VMA.Address += PPU.VMA.Increment;
410 410 
 }
411 411
412 
-inline void REGISTER_2119_linear(uint8_t Byte)
412 
+inline void REGISTER_2119_linear(uint8_t Byt)
413 413 
 {
414 414 
 	if (CHECK_INBLANK())
415 415 
 		return;
416 416
417 417 
 	uint32_t address;
418 418
419 
-	Memory.VRAM[address = ((PPU.VMA.Address << 1) + 1) & 0xffff] = Byte;
419 
+	Memory.VRAM[address = ((PPU.VMA.Address << 1) + 1) & 0xffff] = Byt;
420 420
421 421 
 	if (PPU.VMA.High)
422 422 
 		PPU.VMA.Address += PPU.VMA.Increment;
423 423 
 }
424 424
425 
-inline void REGISTER_2180(uint8_t Byte)
425 
+inline void REGISTER_2180(uint8_t Byt)
426 426 
 {
427 
-	Memory.RAM[PPU.WRAM++] = Byte;
427 
+	Memory.RAM[PPU.WRAM++] = Byt;
428 428 
 	PPU.WRAM &= 0x1ffff;
429 429 
 }
430 430
Browse code

Use #pragma once instead of include guards.

Naram Qashat authored on 2014/09/08 14:47:36
Showing 1 changed files
src/in_snsf/snes9x/ppu.h
History View file @ b6add6e
... ... 
@@ -175,8 +175,7 @@
175 175 
   Nintendo Co., Limited and its subsidiary companies.
176 176 
  ***********************************************************************************/
177 177
178 
-#ifndef _PPU_H_
179 
-#define _PPU_H_
178 
+#pragma once
180 179
181 180 
 const int32_t FIRST_VISIBLE_LINE = 1;
182 181
... ... 
@@ -442,5 +441,3 @@ inline uint8_t REGISTER_4212()
442 441
443 442 
 	return byte;
444 443 
 }
445 
-
446 
-#endif
Browse code

[SNSF] Massive code cleanup, as well as removing as much unused code/variables as possible.

Naram Qashat authored on 2013/05/23 06:02:16
Showing 1 changed files
src/in_snsf/snes9x/ppu.h
History View file @ 5035fcf
... ... 
@@ -175,257 +175,120 @@
175 175 
   Nintendo Co., Limited and its subsidiary companies.
176 176 
  ***********************************************************************************/
177 177
178 
-
179 178 
 #ifndef _PPU_H_
180 179 
 #define _PPU_H_
181 180
182 
-#define FIRST_VISIBLE_LINE	1
183 
-
184 
-#define TILE_2BIT			0
185 
-#define TILE_4BIT			1
186 
-#define TILE_8BIT			2
187 
-#define TILE_2BIT_EVEN		3
188 
-#define TILE_2BIT_ODD		4
189 
-#define TILE_4BIT_EVEN		5
190 
-#define TILE_4BIT_ODD		6
191 
-
192 
-#define MAX_2BIT_TILES		4096
193 
-#define MAX_4BIT_TILES		2048
194 
-#define MAX_8BIT_TILES		1024
195 
-
196 
-#define CLIP_OR				0
197 
-#define CLIP_AND			1
198 
-#define CLIP_XOR			2
199 
-#define CLIP_XNOR			3
181 
+const int32_t FIRST_VISIBLE_LINE = 1;
200 182
201 
-struct ClipData
183 
+enum
202 184 
 {
203 
-	uint8_t	Count;
204 
-	uint8_t	DrawMode[6];
205 
-	uint16_t	Left[6];
206 
-	uint16_t	Right[6];
185 
+	TILE_2BIT,
186 
+	TILE_4BIT,
187 
+	TILE_8BIT,
188 
+	TILE_2BIT_EVEN,
189 
+	TILE_2BIT_ODD,
190 
+	TILE_4BIT_EVEN,
191 
+	TILE_4BIT_ODD
207 192 
 };
208 193
209 
-struct InternalPPU
210 
-{
211 
-	struct ClipData Clip[2][6];
212 
-	bool	ColorsChanged;
213 
-	bool	OBJChanged;
214 
-	bool	DirectColourMapsNeedRebuild;
215 
-	uint8_t	*TileCache[7];
216 
-	uint8_t	*TileCached[7];
217 
-	uint16_t	VRAMReadBuffer;
218 
-	bool	Interlace;
219 
-	bool	InterlaceOBJ;
220 
-	bool	PseudoHires;
221 
-	bool	DoubleWidthPixels;
222 
-	bool	DoubleHeightPixels;
223 
-	int		CurrentLine;
224 
-	int		PreviousLine;
225 
-	uint8_t	*XB;
226 
-	uint32_t	Red[256];
227 
-	uint32_t	Green[256];
228 
-	uint32_t	Blue[256];
229 
-	uint16_t	ScreenColors[256];
230 
-	uint8_t	MaxBrightness;
231 
-	bool	RenderThisFrame;
232 
-	int		RenderedScreenWidth;
233 
-	int		RenderedScreenHeight;
234 
-	uint32_t	FrameCount;
235 
-	uint32_t	RenderedFramesCount;
236 
-	uint32_t	DisplayedRenderedFrameCount;
237 
-	uint32_t	TotalEmulatedFrames;
238 
-	uint32_t	SkippedFrames;
239 
-	uint32_t	FrameSkip;
240 
-};
194 
+const size_t MAX_2BIT_TILES = 4096;
195 
+const size_t MAX_4BIT_TILES = 2048;
196 
+const size_t MAX_8BIT_TILES = 1024;
241 197
242 
-struct SOBJ
198 
+struct InternalPPU
243 199 
 {
244 
-	int16_t	HPos;
245 
-	uint16_t	VPos;
246 
-	uint8_t	HFlip;
247 
-	uint8_t	VFlip;
248 
-	uint16_t	Name;
249 
-	uint8_t	Priority;
250 
-	uint8_t	Palette;
251 
-	uint8_t	Size;
200 
+	uint16_t VRAMReadBuffer;
201 
+	bool Interlace;
202 
+	uint32_t Red[256];
203 
+	uint32_t Green[256];
204 
+	uint32_t Blue[256];
252 205 
 };
253 206
254 207 
 struct SPPU
255 208 
 {
256 209 
 	struct
257 210 
 	{
258 
-		bool	High;
259 
-		uint8_t	Increment;
260 
-		uint16_t	Address;
261 
-		uint16_t	Mask1;
262 
-		uint16_t	FullGraphicCount;
263 
-		uint16_t	Shift;
264 
-	}	VMA;
211 
+		bool High;
212 
+		uint8_t Increment;
213 
+		uint16_t Address;
214 
+		uint16_t Mask1;
215 
+		uint16_t FullGraphicCount;
216 
+		uint16_t Shift;
217 
+	} VMA;
265 218
266 
-	uint32_t	WRAM;
219 
+	uint32_t WRAM;
267 220
268 
-	struct
269 
-	{
270 
-		uint16_t	SCBase;
271 
-		uint16_t	HOffset;
272 
-		uint16_t	VOffset;
273 
-		uint8_t	BGSize;
274 
-		uint16_t	NameBase;
275 
-		uint16_t	SCSize;
276 
-	}	BG[4];
277 
-
278 
-	uint8_t	BGMode;
279 
-	uint8_t	BG3Priority;
280 
-
281 
-	bool	CGFLIP;
282 
-	uint8_t	CGFLIPRead;
283 
-	uint8_t	CGADD;
284 
-	uint16_t	CGDATA[256];
285 
-
286 
-	struct SOBJ OBJ[128];
287 
-	bool	OBJThroughMain;
288 
-	bool	OBJThroughSub;
289 
-	bool	OBJAddition;
290 
-	uint16_t	OBJNameBase;
291 
-	uint16_t	OBJNameSelect;
292 
-	uint8_t	OBJSizeSelect;
293 
-
294 
-	uint16_t	OAMAddr;
295 
-	uint16_t	SavedOAMAddr;
296 
-	uint8_t	OAMPriorityRotation;
297 
-	uint8_t	OAMFlip;
298 
-	uint8_t	OAMReadFlip;
299 
-	uint16_t	OAMTileAddress;
300 
-	uint16_t	OAMWriteRegister;
301 
-	uint8_t	OAMData[512 + 32];
302 
-
303 
-	uint8_t	FirstSprite;
304 
-	uint8_t	LastSprite;
305 
-	uint8_t	RangeTimeOver;
306 
-
307 
-	bool	HTimerEnabled;
308 
-	bool	VTimerEnabled;
309 
-	short	HTimerPosition;
310 
-	short	VTimerPosition;
311 
-	uint16_t	IRQHBeamPos;
312 
-	uint16_t	IRQVBeamPos;
313 
-
314 
-	uint8_t	HBeamFlip;
315 
-	uint8_t	VBeamFlip;
316 
-	uint16_t	HBeamPosLatched;
317 
-	uint16_t	VBeamPosLatched;
318 
-	uint16_t	GunHLatch;
319 
-	uint16_t	GunVLatch;
320 
-	uint8_t	HVBeamCounterLatched;
321 
-
322 
-	bool	Mode7HFlip;
323 
-	bool	Mode7VFlip;
324 
-	uint8_t	Mode7Repeat;
325 
-	short	MatrixA;
326 
-	short	MatrixB;
327 
-	short	MatrixC;
328 
-	short	MatrixD;
329 
-	short	CentreX;
330 
-	short	CentreY;
331 
-	short	M7HOFS;
332 
-	short	M7VOFS;
333 
-
334 
-	uint8_t	Mosaic;
335 
-	uint8_t	MosaicStart;
336 
-	bool	BGMosaic[4];
337 
-
338 
-	uint8_t	Window1Left;
339 
-	uint8_t	Window1Right;
340 
-	uint8_t	Window2Left;
341 
-	uint8_t	Window2Right;
342 
-	bool	RecomputeClipWindows;
343 
-	uint8_t	ClipCounts[6];
344 
-	uint8_t	ClipWindowOverlapLogic[6];
345 
-	uint8_t	ClipWindow1Enable[6];
346 
-	uint8_t	ClipWindow2Enable[6];
347 
-	bool	ClipWindow1Inside[6];
348 
-	bool	ClipWindow2Inside[6];
349 
-
350 
-	bool	ForcedBlanking;
351 
-
352 
-	uint8_t	FixedColourRed;
353 
-	uint8_t	FixedColourGreen;
354 
-	uint8_t	FixedColourBlue;
355 
-	uint8_t	Brightness;
356 
-	uint16_t	ScreenHeight;
357 
-
358 
-	bool	Need16x8Mulitply;
359 
-	uint8_t	BGnxOFSbyte;
360 
-	uint8_t	M7byte;
361 
-
362 
-	uint8_t	HDMA;
363 
-	uint8_t	HDMAEnded;
364 
-
365 
-	uint8_t	OpenBus1;
366 
-	uint8_t	OpenBus2;
221 
+	bool CGFLIPRead;
222 
+	uint8_t CGADD;
223 
+	uint16_t CGDATA[256];
224 
+
225 
+	uint16_t OAMAddr;
226 
+	uint16_t SavedOAMAddr;
227 
+	bool OAMPriorityRotation;
228 
+	uint8_t OAMFlip;
229 
+	uint16_t OAMWriteRegister;
230 
+	uint8_t OAMData[512 + 32];
231 
+
232 
+	uint8_t FirstSprite;
233 
+
234 
+	bool HTimerEnabled;
235 
+	bool VTimerEnabled;
236 
+	short HTimerPosition;
237 
+	short VTimerPosition;
238 
+	uint16_t IRQHBeamPos;
239 
+	uint16_t IRQVBeamPos;
240 
+
241 
+	bool HBeamFlip;
242 
+	bool VBeamFlip;
243 
+
244 
+	short MatrixA;
245 
+	short MatrixB;
246 
+
247 
+	bool ForcedBlanking;
248 
+
249 
+	uint16_t ScreenHeight;
250 
+
251 
+	bool Need16x8Mulitply;
252 
+	uint8_t M7byte;
253 
+
254 
+	uint8_t HDMA;
255 
+	uint8_t HDMAEnded;
256 
+
257 
+	uint8_t OpenBus1;
258 
+	uint8_t OpenBus2;
367 259 
 };
368 260
369 
-extern uint16_t				SignExtend[2];
370 
-extern struct SPPU			PPU;
371 
-extern struct InternalPPU	IPPU;
261 
+extern uint16_t SignExtend[2];
262 
+extern SPPU PPU;
263 
+extern InternalPPU IPPU;
372 264
373 265 
 void S9xResetPPU();
374 266 
 void S9xSoftResetPPU();
375 
-void S9xSetPPU (uint8_t, uint16_t);
376 
-uint8_t S9xGetPPU (uint16_t);
377 
-void S9xSetCPU (uint8_t, uint16_t);
378 
-uint8_t S9xGetCPU (uint16_t);
267 
+void S9xSetPPU(uint8_t, uint16_t);
268 
+uint8_t S9xGetPPU(uint16_t);
269 
+void S9xSetCPU(uint8_t, uint16_t);
270 
+uint8_t S9xGetCPU(uint16_t);
379 271 
 void S9xUpdateHVTimerPosition();
380 
-//void S9xFixColourBrightness();
381 
-//void S9xDoAutoJoypad();
382 272
383 
-//#include "gfx.h"
384 273 
 #include "memmap.h"
385 274
386 
-typedef struct
275 
+struct SnesModel
387 276 
 {
388 
-	uint8_t	_5C77;
389 
-	uint8_t	_5C78;
390 
-	uint8_t	_5A22;
391 
-}	SnesModel;
392 
-
393 
-extern SnesModel	*Model;
394 
-extern SnesModel	M1SNES;
395 
-//extern SnesModel	M2SNES;
396 
-
397 
-#define MAX_5C77_VERSION	0x01
398 
-#define MAX_5C78_VERSION	0x03
399 
-#define MAX_5A22_VERSION	0x02
277 
+	uint8_t _5C77;
278 
+	uint8_t _5C78;
279 
+	uint8_t _5A22;
280 
+};
400 281
401 
-/*static inline void FLUSH_REDRAW()
402 
-{
403 
-	if (IPPU.PreviousLine != IPPU.CurrentLine)
404 
-		S9xUpdateScreen();
405 
-}*/
282 
+extern SnesModel *Model;
283 
+extern SnesModel M1SNES;
406 284
407 
-static inline void REGISTER_2104 (uint8_t Byte)
285 
+inline void REGISTER_2104(uint8_t Byte)
408 286 
 {
409 287 
 	if (PPU.OAMAddr & 0x100)
410 288 
 	{
411 289 
 		int addr = ((PPU.OAMAddr & 0x10f) << 1) + (PPU.OAMFlip & 1);
412 290 
 		if (Byte != PPU.OAMData[addr])
413 
-		{
414 
-			//FLUSH_REDRAW();
415 291 
 			PPU.OAMData[addr] = Byte;
416 
-			IPPU.OBJChanged = true;
417 
-
418 
-			// X position high bit, and sprite size (x4)
419 
-			struct SOBJ *pObj = &PPU.OBJ[(addr & 0x1f) * 4];
420 
-			pObj->HPos = (pObj->HPos & 0xFF) | SignExtend[(Byte >> 0) & 1];
421 
-			pObj++->Size = Byte & 2;
422 
-			pObj->HPos = (pObj->HPos & 0xFF) | SignExtend[(Byte >> 2) & 1];
423 
-			pObj++->Size = Byte & 8;
424 
-			pObj->HPos = (pObj->HPos & 0xFF) | SignExtend[(Byte >> 4) & 1];
425 
-			pObj++->Size = Byte & 32;
426 
-			pObj->HPos = (pObj->HPos & 0xFF) | SignExtend[(Byte >> 6) & 1];
427 
-			pObj->Size = Byte & 128;
428 
-		}
429 292
430 293 
 		PPU.OAMFlip ^= 1;
431 294 
 		if (!(PPU.OAMFlip & 1))
... ... 
@@ -433,90 +296,45 @@ static inline void REGISTER_2104 (uint8_t Byte)
433 296 
 			++PPU.OAMAddr;
434 297 
 			PPU.OAMAddr &= 0x1ff;
435 298 
 			if (PPU.OAMPriorityRotation && PPU.FirstSprite != (PPU.OAMAddr >> 1))
436 
-			{
437 299 
 				PPU.FirstSprite = (PPU.OAMAddr & 0xfe) >> 1;
438 
-				IPPU.OBJChanged = true;
439 
-			}
440 
-		}
441 
-		else
442 
-		{
443 
-			if (PPU.OAMPriorityRotation && (PPU.OAMAddr & 1))
444 
-				IPPU.OBJChanged = true;
445 300 
 		}
446 301 
 	}
447 
-	else
448 
-	if (!(PPU.OAMFlip & 1))
302 
+	else if (!(PPU.OAMFlip & 1))
449 303 
 	{
450 304 
 		PPU.OAMWriteRegister &= 0xff00;
451 305 
 		PPU.OAMWriteRegister |= Byte;
452 306 
 		PPU.OAMFlip |= 1;
453 
-		if (PPU.OAMPriorityRotation && (PPU.OAMAddr & 1))
454 
-			IPPU.OBJChanged = true;
455 307 
 	}
456 308 
 	else
457 309 
 	{
458 310 
 		PPU.OAMWriteRegister &= 0x00ff;
459 
-		uint8_t lowbyte = (uint8_t) (PPU.OAMWriteRegister);
311 
+		uint8_t lowbyte = static_cast<uint8_t>(PPU.OAMWriteRegister);
460 312 
 		uint8_t highbyte = Byte;
461 313 
 		PPU.OAMWriteRegister |= Byte << 8;
462 314
463 
-		int addr = (PPU.OAMAddr << 1);
315 
+		int addr = PPU.OAMAddr << 1;
464 316 
 		if (lowbyte != PPU.OAMData[addr] || highbyte != PPU.OAMData[addr + 1])
465 317 
 		{
466 
-			//FLUSH_REDRAW();
467 318 
 			PPU.OAMData[addr] = lowbyte;
468 319 
 			PPU.OAMData[addr + 1] = highbyte;
469 
-			IPPU.OBJChanged = true;
470 
-			if (addr & 2)
471 
-			{
472 
-				// Tile
473 
-				PPU.OBJ[addr = PPU.OAMAddr >> 1].Name = PPU.OAMWriteRegister & 0x1ff;
474 
-				// priority, h and v flip.
475 
-				PPU.OBJ[addr].Palette  = (highbyte >> 1) & 7;
476 
-				PPU.OBJ[addr].Priority = (highbyte >> 4) & 3;
477 
-				PPU.OBJ[addr].HFlip    = (highbyte >> 6) & 1;
478 
-				PPU.OBJ[addr].VFlip    = (highbyte >> 7) & 1;
479 
-			}
480 
-			else
481 
-			{
482 
-				// X position (low)
483 
-				PPU.OBJ[addr = PPU.OAMAddr >> 1].HPos &= 0xff00;
484 
-				PPU.OBJ[addr].HPos |= lowbyte;
485 
-				// Sprite Y position
486 
-				PPU.OBJ[addr].VPos = highbyte;
487 
-			}
488 320 
 		}
489 321
490 322 
 		PPU.OAMFlip &= ~1;
491 323 
 		++PPU.OAMAddr;
492 324 
 		if (PPU.OAMPriorityRotation && PPU.FirstSprite != (PPU.OAMAddr >> 1))
493 
-		{
494 325 
 			PPU.FirstSprite = (PPU.OAMAddr & 0xfe) >> 1;
495 
-			IPPU.OBJChanged = true;
496 
-		}
497 326 
 	}
498 327 
 }
499 328
500 329 
 // This code is correct, however due to Snes9x's inaccurate timings, some games might be broken by this chage. :(
501 
-#ifdef DEBUGGER
502 
-#define CHECK_INBLANK() \
503 
-	if (!PPU.ForcedBlanking && CPU.V_Counter < PPU.ScreenHeight + FIRST_VISIBLE_LINE) \
504 
-	{ \
505 
-		printf("Invalid VRAM acess at (%04d, %04d) blank:%d\n", CPU.Cycles, CPU.V_Counter, PPU.ForcedBlanking); \
506 
-		if (Settings.BlockInvalidVRAMAccess) \
507 
-			return; \
508 
-	}
509 
-#else
510 
-#define CHECK_INBLANK() \
511 
-	if (Settings.BlockInvalidVRAMAccess && !PPU.ForcedBlanking && CPU.V_Counter < PPU.ScreenHeight + FIRST_VISIBLE_LINE) \
512 
-		return;
513 
-#endif
330 
+inline bool CHECK_INBLANK() { return Settings.BlockInvalidVRAMAccess && !PPU.ForcedBlanking && CPU.V_Counter < PPU.ScreenHeight + FIRST_VISIBLE_LINE; }
514 331
515 
-static inline void REGISTER_2118 (uint8_t Byte)
332 
+inline void REGISTER_2118(uint8_t Byte)
516 333 
 {
517 
-	CHECK_INBLANK();
334 
+	if (CHECK_INBLANK())
335 
+		return;
518 336
519 
-	uint32_t	address;
337 
+	uint32_t address;
520 338
521 339 
 	if (PPU.VMA.FullGraphicCount)
522 340 
 	{
... ... 
@@ -527,33 +345,16 @@ static inline void REGISTER_2118 (uint8_t Byte)
527 345 
 	else
528 346 
 		Memory.VRAM[address = (PPU.VMA.Address << 1) & 0xffff] = Byte;
529 347
530 
-	IPPU.TileCached[TILE_2BIT][address >> 4] = false;
531 
-	IPPU.TileCached[TILE_4BIT][address >> 5] = false;
532 
-	IPPU.TileCached[TILE_8BIT][address >> 6] = false;
533 
-	IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = false;
534 
-	IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
535 
-	IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = false;
536 
-	IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
537 
-	IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = false;
538 
-	IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
539 
-	IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = false;
540 
-	IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
541 
-
542 348 
 	if (!PPU.VMA.High)
543 
-	{
544 
-	#ifdef DEBUGGER
545 
-		if (Settings.TraceVRAM && !CPU.InDMAorHDMA)
546 
-			printf("VRAM write byte: $%04X (%d, %d)\n", PPU.VMA.Address, Memory.FillRAM[0x2115] & 3, (Memory.FillRAM[0x2115] & 0x0c) >> 2);
547 
-	#endif
548 349 
 		PPU.VMA.Address += PPU.VMA.Increment;
549 
-	}
550 350 
 }
551 351
552 
-static inline void REGISTER_2119 (uint8_t Byte)
352 
+inline void REGISTER_2119(uint8_t Byte)
553 353 
 {
554 
-	CHECK_INBLANK();
354 
+	if (CHECK_INBLANK())
355 
+		return;
555 356
556 
-	uint32_t	address;
357 
+	uint32_t address;
557 358
558 359 
 	if (PPU.VMA.FullGraphicCount)
559 360 
 	{
... ... 
@@ -564,178 +365,82 @@ static inline void REGISTER_2119 (uint8_t Byte)
564 365 
 	else
565 366 
 		Memory.VRAM[address = ((PPU.VMA.Address << 1) + 1) & 0xffff] = Byte;
566 367
567 
-	IPPU.TileCached[TILE_2BIT][address >> 4] = false;
568 
-	IPPU.TileCached[TILE_4BIT][address >> 5] = false;
569 
-	IPPU.TileCached[TILE_8BIT][address >> 6] = false;
570 
-	IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = false;
571 
-	IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
572 
-	IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = false;
573 
-	IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
574 
-	IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = false;
575 
-	IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
576 
-	IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = false;
577 
-	IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
578 
-
579 368 
 	if (PPU.VMA.High)
580 
-	{
581 
-	#ifdef DEBUGGER
582 
-		if (Settings.TraceVRAM && !CPU.InDMAorHDMA)
583 
-			printf("VRAM write word: $%04X (%d, %d)\n", PPU.VMA.Address, Memory.FillRAM[0x2115] & 3, (Memory.FillRAM[0x2115] & 0x0c) >> 2);
584 
-	#endif
585 369 
 		PPU.VMA.Address += PPU.VMA.Increment;
586 
-	}
587 370 
 }
588 371
589 
-static inline void REGISTER_2118_tile (uint8_t Byte)
372 
+inline void REGISTER_2118_tile(uint8_t Byte)
590 373 
 {
591 
-	CHECK_INBLANK();
374 
+	if (CHECK_INBLANK())
375 
+		return;
592 376
593 377 
 	uint32_t rem = PPU.VMA.Address & PPU.VMA.Mask1;
594 378 
 	uint32_t address = (((PPU.VMA.Address & ~PPU.VMA.Mask1) + (rem >> PPU.VMA.Shift) + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) & 0xffff;
595 379
596 380 
 	Memory.VRAM[address] = Byte;
597 381
598 
-	IPPU.TileCached[TILE_2BIT][address >> 4] = false;
599 
-	IPPU.TileCached[TILE_4BIT][address >> 5] = false;
600 
-	IPPU.TileCached[TILE_8BIT][address >> 6] = false;
601 
-	IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = false;
602 
-	IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
603 
-	IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = false;
604 
-	IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
605 
-	IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = false;
606 
-	IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
607 
-	IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = false;
608 
-	IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
609 
-
610 382 
 	if (!PPU.VMA.High)
611 383 
 		PPU.VMA.Address += PPU.VMA.Increment;
612 384 
 }
613 385
614 
-static inline void REGISTER_2119_tile (uint8_t Byte)
386 
+inline void REGISTER_2119_tile(uint8_t Byte)
615 387 
 {
616 
-	CHECK_INBLANK();
388 
+	if (CHECK_INBLANK())
389 
+		return;
617 390
618 391 
 	uint32_t rem = PPU.VMA.Address & PPU.VMA.Mask1;
619 392 
 	uint32_t address = ((((PPU.VMA.Address & ~PPU.VMA.Mask1) + (rem >> PPU.VMA.Shift) + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) + 1) & 0xffff;
620 393
621 394 
 	Memory.VRAM[address] = Byte;
622 395
623 
-	IPPU.TileCached[TILE_2BIT][address >> 4] = false;
624 
-	IPPU.TileCached[TILE_4BIT][address >> 5] = false;
625 
-	IPPU.TileCached[TILE_8BIT][address >> 6] = false;
626 
-	IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = false;
627 
-	IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
628 
-	IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = false;
629 
-	IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
630 
-	IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = false;
631 
-	IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
632 
-	IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = false;
633 
-	IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
634 
-
635 396 
 	if (PPU.VMA.High)
636 397 
 		PPU.VMA.Address += PPU.VMA.Increment;
637 398 
 }
638 399
639 
-static inline void REGISTER_2118_linear (uint8_t Byte)
400 
+inline void REGISTER_2118_linear(uint8_t Byte)
640 401 
 {
641 
-	CHECK_INBLANK();
402 
+	if (CHECK_INBLANK())
403 
+		return;
642 404
643 
-	uint32_t	address;
405 
+	uint32_t address;
644 406
645 407 
 	Memory.VRAM[address = (PPU.VMA.Address << 1) & 0xffff] = Byte;
646 408
647 
-	IPPU.TileCached[TILE_2BIT][address >> 4] = false;
648 
-	IPPU.TileCached[TILE_4BIT][address >> 5] = false;
649 
-	IPPU.TileCached[TILE_8BIT][address >> 6] = false;
650 
-	IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = false;
651 
-	IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
652 
-	IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = false;
653 
-	IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
654 
-	IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = false;
655 
-	IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
656 
-	IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = false;
657 
-	IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
658 
-
659 409 
 	if (!PPU.VMA.High)
660 410 
 		PPU.VMA.Address += PPU.VMA.Increment;
661 411 
 }
662 412
663 
-static inline void REGISTER_2119_linear (uint8_t Byte)
413 
+inline void REGISTER_2119_linear(uint8_t Byte)
664 414 
 {
665 
-	CHECK_INBLANK();
415 
+	if (CHECK_INBLANK())
416 
+		return;
666 417
667 
-	uint32_t	address;
418 
+	uint32_t address;
668 419
669 420 
 	Memory.VRAM[address = ((PPU.VMA.Address << 1) + 1) & 0xffff] = Byte;
670 421
671 
-	IPPU.TileCached[TILE_2BIT][address >> 4] = false;
672 
-	IPPU.TileCached[TILE_4BIT][address >> 5] = false;
673 
-	IPPU.TileCached[TILE_8BIT][address >> 6] = false;
674 
-	IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = false;
675 
-	IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
676 
-	IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = false;
677 
-	IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
678 
-	IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = false;
679 
-	IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
680 
-	IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = false;
681 
-	IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
682 
-
683 422 
 	if (PPU.VMA.High)
684 423 
 		PPU.VMA.Address += PPU.VMA.Increment;
685 424 
 }
686 425
687 
-/*static inline void REGISTER_2122 (uint8_t Byte)
688 
-{
689 
-	if (PPU.CGFLIP)
690 
-	{
691 
-		if ((Byte & 0x7f) != (PPU.CGDATA[PPU.CGADD] >> 8))
692 
-		{
693 
-			FLUSH_REDRAW();
694 
-			PPU.CGDATA[PPU.CGADD] &= 0x00ff;
695 
-			PPU.CGDATA[PPU.CGADD] |= (Byte & 0x7f) << 8;
696 
-			IPPU.ColorsChanged = true;
697 
-			IPPU.Blue[PPU.CGADD] = IPPU.XB[(Byte >> 2) & 0x1f];
698 
-			IPPU.Green[PPU.CGADD] = IPPU.XB[(PPU.CGDATA[PPU.CGADD] >> 5) & 0x1f];
699 
-			IPPU.ScreenColors[PPU.CGADD] = (uint16_t) BUILD_PIXEL(IPPU.Red[PPU.CGADD], IPPU.Green[PPU.CGADD], IPPU.Blue[PPU.CGADD]);
700 
-		}
701 
-
702 
-		PPU.CGADD++;
703 
-	}
704 
-	else
705 
-	{
706 
-		if (Byte != (uint8_t) (PPU.CGDATA[PPU.CGADD] & 0xff))
707 
-		{
708 
-			FLUSH_REDRAW();
709 
-			PPU.CGDATA[PPU.CGADD] &= 0x7f00;
710 
-			PPU.CGDATA[PPU.CGADD] |= Byte;
711 
-			IPPU.ColorsChanged = true;
712 
-			IPPU.Red[PPU.CGADD] = IPPU.XB[Byte & 0x1f];
713 
-			IPPU.Green[PPU.CGADD] = IPPU.XB[(PPU.CGDATA[PPU.CGADD] >> 5) & 0x1f];
714 
-			IPPU.ScreenColors[PPU.CGADD] = (uint16_t) BUILD_PIXEL(IPPU.Red[PPU.CGADD], IPPU.Green[PPU.CGADD], IPPU.Blue[PPU.CGADD]);
715 
-		}
716 
-	}
717 
-
718 
-	PPU.CGFLIP ^= 1;
719 
-}*/
720 
-
721 
-static inline void REGISTER_2180 (uint8_t Byte)
426 
+inline void REGISTER_2180(uint8_t Byte)
722 427 
 {
723 428 
 	Memory.RAM[PPU.WRAM++] = Byte;
724 429 
 	PPU.WRAM &= 0x1ffff;
725 430 
 }
726 431
727 
-static inline uint8_t REGISTER_4212()
432 
+inline uint8_t REGISTER_4212()
728 433 
 {
729 
-	uint8_t	byte = 0;
434 
+	uint8_t byte = 0;
730 435
731 
-    if ((CPU.V_Counter >= PPU.ScreenHeight + FIRST_VISIBLE_LINE) && (CPU.V_Counter < PPU.ScreenHeight + FIRST_VISIBLE_LINE + 3))
436 
+	if (CPU.V_Counter >= PPU.ScreenHeight + FIRST_VISIBLE_LINE && CPU.V_Counter < PPU.ScreenHeight + FIRST_VISIBLE_LINE + 3)
732 437 
 		byte = 1;
733 
-	if ((CPU.Cycles < Timings.HBlankEnd) || (CPU.Cycles >= Timings.HBlankStart))
438 
+	if (CPU.Cycles < Timings.HBlankEnd || CPU.Cycles >= Timings.HBlankStart)
734 439 
 		byte |= 0x40;
735 
-    if (CPU.V_Counter >= PPU.ScreenHeight + FIRST_VISIBLE_LINE)
440 
+	if (CPU.V_Counter >= PPU.ScreenHeight + FIRST_VISIBLE_LINE)
736 441 
 		byte |= 0x80;
737 442
738 
-    return byte;
443 
+	return byte;
739 444 
 }
740 445
741 446 
 #endif
Browse code

Import actual code.

Naram Qashat authored on 2013/03/26 02:41:19
Showing 1 changed files
src/in_snsf/snes9x/ppu.h
History View file @ bc076aa
1 1 
new file mode 100644
... ... 
@@ -0,0 +1,741 @@
1 
+/***********************************************************************************
2 
+  Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
3 
+
4 
+  (c) Copyright 1996 - 2002  Gary Henderson (gary.henderson@ntlworld.com),
5 
+                             Jerremy Koot (jkoot@snes9x.com)
6 
+
7 
+  (c) Copyright 2002 - 2004  Matthew Kendora
8 
+
9 
+  (c) Copyright 2002 - 2005  Peter Bortas (peter@bortas.org)
10 
+
11 
+  (c) Copyright 2004 - 2005  Joel Yliluoma (http://iki.fi/bisqwit/)
12 
+
13 
+  (c) Copyright 2001 - 2006  John Weidman (jweidman@slip.net)
14 
+
15 
+  (c) Copyright 2002 - 2006  funkyass (funkyass@spam.shaw.ca),
16 
+                             Kris Bleakley (codeviolation@hotmail.com)
17 
+
18 
+  (c) Copyright 2002 - 2010  Brad Jorsch (anomie@users.sourceforge.net),
19 
+                             Nach (n-a-c-h@users.sourceforge.net),
20 
+
21 
+  (c) Copyright 2002 - 2011  zones (kasumitokoduck@yahoo.com)
22 
+
23 
+  (c) Copyright 2006 - 2007  nitsuja
24 
+
25 
+  (c) Copyright 2009 - 2011  BearOso,
26 
+                             OV2
27 
+
28 
+
29 
+  BS-X C emulator code
30 
+  (c) Copyright 2005 - 2006  Dreamer Nom,
31 
+                             zones
32 
+
33 
+  C4 x86 assembler and some C emulation code
34 
+  (c) Copyright 2000 - 2003  _Demo_ (_demo_@zsnes.com),
35 
+                             Nach,
36 
+                             zsKnight (zsknight@zsnes.com)
37 
+
38 
+  C4 C++ code
39 
+  (c) Copyright 2003 - 2006  Brad Jorsch,
40 
+                             Nach
41 
+
42 
+  DSP-1 emulator code
43 
+  (c) Copyright 1998 - 2006  _Demo_,
44 
+                             Andreas Naive (andreasnaive@gmail.com),
45 
+                             Gary Henderson,
46 
+                             Ivar (ivar@snes9x.com),
47 
+                             John Weidman,
48 
+                             Kris Bleakley,
49 
+                             Matthew Kendora,
50 
+                             Nach,
51 
+                             neviksti (neviksti@hotmail.com)
52 
+
53 
+  DSP-2 emulator code
54 
+  (c) Copyright 2003         John Weidman,
55 
+                             Kris Bleakley,
56 
+                             Lord Nightmare (lord_nightmare@users.sourceforge.net),
57 
+                             Matthew Kendora,
58 
+                             neviksti
59 
+
60 
+  DSP-3 emulator code
61 
+  (c) Copyright 2003 - 2006  John Weidman,
62 
+                             Kris Bleakley,
63 
+                             Lancer,
64 
+                             z80 gaiden
65 
+
66 
+  DSP-4 emulator code
67 
+  (c) Copyright 2004 - 2006  Dreamer Nom,
68 
+                             John Weidman,
69 
+                             Kris Bleakley,
70 
+                             Nach,
71 
+                             z80 gaiden
72 
+
73 
+  OBC1 emulator code
74 
+  (c) Copyright 2001 - 2004  zsKnight,
75 
+                             pagefault (pagefault@zsnes.com),
76 
+                             Kris Bleakley
77 
+                             Ported from x86 assembler to C by sanmaiwashi
78 
+
79 
+  SPC7110 and RTC C++ emulator code used in 1.39-1.51
80 
+  (c) Copyright 2002         Matthew Kendora with research by
81 
+                             zsKnight,
82 
+                             John Weidman,
83 
+                             Dark Force
84 
+
85 
+  SPC7110 and RTC C++ emulator code used in 1.52+
86 
+  (c) Copyright 2009         byuu,
87 
+                             neviksti
88 
+
89 
+  S-DD1 C emulator code
90 
+  (c) Copyright 2003         Brad Jorsch with research by
91 
+                             Andreas Naive,
92 
+                             John Weidman
93 
+
94 
+  S-RTC C emulator code
95 
+  (c) Copyright 2001 - 2006  byuu,
96 
+                             John Weidman
97 
+
98 
+  ST010 C++ emulator code
99 
+  (c) Copyright 2003         Feather,
100 
+                             John Weidman,
101 
+                             Kris Bleakley,
102 
+                             Matthew Kendora
103 
+
104 
+  Super FX x86 assembler emulator code
105 
+  (c) Copyright 1998 - 2003  _Demo_,
106 
+                             pagefault,
107 
+                             zsKnight
108 
+
109 
+  Super FX C emulator code
110 
+  (c) Copyright 1997 - 1999  Ivar,
111 
+                             Gary Henderson,
112 
+                             John Weidman
113 
+
114 
+  Sound emulator code used in 1.5-1.51
115 
+  (c) Copyright 1998 - 2003  Brad Martin
116 
+  (c) Copyright 1998 - 2006  Charles Bilyue'
117 
+
118 
+  Sound emulator code used in 1.52+
119 
+  (c) Copyright 2004 - 2007  Shay Green (gblargg@gmail.com)
120 
+
121 
+  SH assembler code partly based on x86 assembler code
122 
+  (c) Copyright 2002 - 2004  Marcus Comstedt (marcus@mc.pp.se)
123 
+
124 
+  2xSaI filter
125 
+  (c) Copyright 1999 - 2001  Derek Liauw Kie Fa
126 
+
127 
+  HQ2x, HQ3x, HQ4x filters
128 
+  (c) Copyright 2003         Maxim Stepin (maxim@hiend3d.com)
129 
+
130 
+  NTSC filter
131 
+  (c) Copyright 2006 - 2007  Shay Green
132 
+
133 
+  GTK+ GUI code
134 
+  (c) Copyright 2004 - 2011  BearOso
135 
+
136 
+  Win32 GUI code
137 
+  (c) Copyright 2003 - 2006  blip,
138 
+                             funkyass,
139 
+                             Matthew Kendora,
140 
+                             Nach,
141 
+                             nitsuja
142 
+  (c) Copyright 2009 - 2011  OV2
143 
+
144 
+  Mac OS GUI code
145 
+  (c) Copyright 1998 - 2001  John Stiles
146 
+  (c) Copyright 2001 - 2011  zones
147 
+
148 
+
149 
+  Specific ports contains the works of other authors. See headers in
150 
+  individual files.
151 
+
152 
+
153 
+  Snes9x homepage: http://www.snes9x.com/
154 
+
155 
+  Permission to use, copy, modify and/or distribute Snes9x in both binary
156 
+  and source form, for non-commercial purposes, is hereby granted without
157 
+  fee, providing that this license information and copyright notice appear
158 
+  with all copies and any derived work.
159 
+
160 
+  This software is provided 'as-is', without any express or implied
161 
+  warranty. In no event shall the authors be held liable for any damages
162 
+  arising from the use of this software or it's derivatives.
163 
+
164 
+  Snes9x is freeware for PERSONAL USE only. Commercial users should
165 
+  seek permission of the copyright holders first. Commercial use includes,
166 
+  but is not limited to, charging money for Snes9x or software derived from
167 
+  Snes9x, including Snes9x or derivatives in commercial game bundles, and/or
168 
+  using Snes9x as a promotion for your commercial product.
169 
+
170 
+  The copyright holders request that bug fixes and improvements to the code
171 
+  should be forwarded to them so everyone can benefit from the modifications
172 
+  in future versions.
173 
+
174 
+  Super NES and Super Nintendo Entertainment System are trademarks of
175 
+  Nintendo Co., Limited and its subsidiary companies.
176 
+ ***********************************************************************************/
177 
+
178 
+
179 
+#ifndef _PPU_H_
180 
+#define _PPU_H_
181 
+
182 
+#define FIRST_VISIBLE_LINE	1
183 
+
184 
+#define TILE_2BIT			0
185 
+#define TILE_4BIT			1
186 
+#define TILE_8BIT			2
187 
+#define TILE_2BIT_EVEN		3
188 
+#define TILE_2BIT_ODD		4
189 
+#define TILE_4BIT_EVEN		5
190 
+#define TILE_4BIT_ODD		6
191 
+
192 
+#define MAX_2BIT_TILES		4096
193 
+#define MAX_4BIT_TILES		2048
194 
+#define MAX_8BIT_TILES		1024
195 
+
196 
+#define CLIP_OR				0
197 
+#define CLIP_AND			1
198 
+#define CLIP_XOR			2
199 
+#define CLIP_XNOR			3
200 
+
201 
+struct ClipData
202 
+{
203 
+	uint8_t	Count;
204 
+	uint8_t	DrawMode[6];
205 
+	uint16_t	Left[6];
206 
+	uint16_t	Right[6];
207 
+};
208 
+
209 
+struct InternalPPU
210 
+{
211 
+	struct ClipData Clip[2][6];
212 
+	bool	ColorsChanged;
213 
+	bool	OBJChanged;
214 
+	bool	DirectColourMapsNeedRebuild;
215 
+	uint8_t	*TileCache[7];
216 
+	uint8_t	*TileCached[7];
217 
+	uint16_t	VRAMReadBuffer;
218 
+	bool	Interlace;
219 
+	bool	InterlaceOBJ;
220 
+	bool	PseudoHires;
221 
+	bool	DoubleWidthPixels;
222 
+	bool	DoubleHeightPixels;
223 
+	int		CurrentLine;
224 
+	int		PreviousLine;
225 
+	uint8_t	*XB;
226 
+	uint32_t	Red[256];
227 
+	uint32_t	Green[256];
228 
+	uint32_t	Blue[256];
229 
+	uint16_t	ScreenColors[256];
230 
+	uint8_t	MaxBrightness;
231 
+	bool	RenderThisFrame;
232 
+	int		RenderedScreenWidth;
233 
+	int		RenderedScreenHeight;
234 
+	uint32_t	FrameCount;
235 
+	uint32_t	RenderedFramesCount;
236 
+	uint32_t	DisplayedRenderedFrameCount;
237 
+	uint32_t	TotalEmulatedFrames;
238 
+	uint32_t	SkippedFrames;
239 
+	uint32_t	FrameSkip;
240 
+};
241 
+
242 
+struct SOBJ
243 
+{
244 
+	int16_t	HPos;
245 
+	uint16_t	VPos;
246 
+	uint8_t	HFlip;
247 
+	uint8_t	VFlip;
248 
+	uint16_t	Name;
249 
+	uint8_t	Priority;
250 
+	uint8_t	Palette;
251 
+	uint8_t	Size;
252 
+};
253 
+
254 
+struct SPPU
255 
+{
256 
+	struct
257 
+	{
258 
+		bool	High;
259 
+		uint8_t	Increment;
260 
+		uint16_t	Address;
261 
+		uint16_t	Mask1;
262 
+		uint16_t	FullGraphicCount;
263 
+		uint16_t	Shift;
264 
+	}	VMA;
265 
+
266 
+	uint32_t	WRAM;
267 
+
268 
+	struct
269 
+	{
270 
+		uint16_t	SCBase;
271 
+		uint16_t	HOffset;
272 
+		uint16_t	VOffset;
273 
+		uint8_t	BGSize;
274 
+		uint16_t	NameBase;
275 
+		uint16_t	SCSize;
276 
+	}	BG[4];
277 
+
278 
+	uint8_t	BGMode;
279 
+	uint8_t	BG3Priority;
280 
+
281 
+	bool	CGFLIP;
282 
+	uint8_t	CGFLIPRead;
283 
+	uint8_t	CGADD;
284 
+	uint16_t	CGDATA[256];
285 
+
286 
+	struct SOBJ OBJ[128];
287 
+	bool	OBJThroughMain;
288 
+	bool	OBJThroughSub;
289 
+	bool	OBJAddition;
290 
+	uint16_t	OBJNameBase;
291 
+	uint16_t	OBJNameSelect;
292 
+	uint8_t	OBJSizeSelect;
293 
+
294 
+	uint16_t	OAMAddr;
295 
+	uint16_t	SavedOAMAddr;
296 
+	uint8_t	OAMPriorityRotation;
297 
+	uint8_t	OAMFlip;
298 
+	uint8_t	OAMReadFlip;
299 
+	uint16_t	OAMTileAddress;
300 
+	uint16_t	OAMWriteRegister;
301 
+	uint8_t	OAMData[512 + 32];
302 
+
303 
+	uint8_t	FirstSprite;
304 
+	uint8_t	LastSprite;
305 
+	uint8_t	RangeTimeOver;
306 
+
307 
+	bool	HTimerEnabled;
308 
+	bool	VTimerEnabled;
309 
+	short	HTimerPosition;
310 
+	short	VTimerPosition;
311 
+	uint16_t	IRQHBeamPos;
312 
+	uint16_t	IRQVBeamPos;
313 
+
314 
+	uint8_t	HBeamFlip;
315 
+	uint8_t	VBeamFlip;
316 
+	uint16_t	HBeamPosLatched;
317 
+	uint16_t	VBeamPosLatched;
318 
+	uint16_t	GunHLatch;
319 
+	uint16_t	GunVLatch;
320 
+	uint8_t	HVBeamCounterLatched;
321 
+
322 
+	bool	Mode7HFlip;
323 
+	bool	Mode7VFlip;
324 
+	uint8_t	Mode7Repeat;
325 
+	short	MatrixA;
326 
+	short	MatrixB;
327 
+	short	MatrixC;
328 
+	short	MatrixD;
329 
+	short	CentreX;
330 
+	short	CentreY;
331 
+	short	M7HOFS;
332 
+	short	M7VOFS;
333 
+
334 
+	uint8_t	Mosaic;
335 
+	uint8_t	MosaicStart;
336 
+	bool	BGMosaic[4];
337 
+
338 
+	uint8_t	Window1Left;
339 
+	uint8_t	Window1Right;
340 
+	uint8_t	Window2Left;
341 
+	uint8_t	Window2Right;
342 
+	bool	RecomputeClipWindows;
343 
+	uint8_t	ClipCounts[6];
344 
+	uint8_t	ClipWindowOverlapLogic[6];
345 
+	uint8_t	ClipWindow1Enable[6];
346 
+	uint8_t	ClipWindow2Enable[6];
347 
+	bool	ClipWindow1Inside[6];
348 
+	bool	ClipWindow2Inside[6];
349 
+
350 
+	bool	ForcedBlanking;
351 
+
352 
+	uint8_t	FixedColourRed;
353 
+	uint8_t	FixedColourGreen;
354 
+	uint8_t	FixedColourBlue;
355 
+	uint8_t	Brightness;
356 
+	uint16_t	ScreenHeight;
357 
+
358 
+	bool	Need16x8Mulitply;
359 
+	uint8_t	BGnxOFSbyte;
360 
+	uint8_t	M7byte;
361 
+
362 
+	uint8_t	HDMA;
363 
+	uint8_t	HDMAEnded;
364 
+
365 
+	uint8_t	OpenBus1;
366 
+	uint8_t	OpenBus2;
367 
+};
368 
+
369 
+extern uint16_t				SignExtend[2];
370 
+extern struct SPPU			PPU;
371 
+extern struct InternalPPU	IPPU;
372 
+
373 
+void S9xResetPPU();
374 
+void S9xSoftResetPPU();
375 
+void S9xSetPPU (uint8_t, uint16_t);
376 
+uint8_t S9xGetPPU (uint16_t);
377 
+void S9xSetCPU (uint8_t, uint16_t);
378 
+uint8_t S9xGetCPU (uint16_t);
379 
+void S9xUpdateHVTimerPosition();
380 
+//void S9xFixColourBrightness();
381 
+//void S9xDoAutoJoypad();
382 
+
383 
+//#include "gfx.h"
384 
+#include "memmap.h"
385 
+
386 
+typedef struct
387 
+{
388 
+	uint8_t	_5C77;
389 
+	uint8_t	_5C78;
390 
+	uint8_t	_5A22;
391 
+}	SnesModel;
392 
+
393 
+extern SnesModel	*Model;
394 
+extern SnesModel	M1SNES;
395 
+//extern SnesModel	M2SNES;
396 
+
397 
+#define MAX_5C77_VERSION	0x01
398 
+#define MAX_5C78_VERSION	0x03
399 
+#define MAX_5A22_VERSION	0x02
400 
+
401 
+/*static inline void FLUSH_REDRAW()
402 
+{
403 
+	if (IPPU.PreviousLine != IPPU.CurrentLine)
404 
+		S9xUpdateScreen();
405 
+}*/
406 
+
407 
+static inline void REGISTER_2104 (uint8_t Byte)
408 
+{
409 
+	if (PPU.OAMAddr & 0x100)
410 
+	{
411 
+		int addr = ((PPU.OAMAddr & 0x10f) << 1) + (PPU.OAMFlip & 1);
412 
+		if (Byte != PPU.OAMData[addr])
413 
+		{
414 
+			//FLUSH_REDRAW();
415 
+			PPU.OAMData[addr] = Byte;
416 
+			IPPU.OBJChanged = true;
417 
+
418 
+			// X position high bit, and sprite size (x4)
419 
+			struct SOBJ *pObj = &PPU.OBJ[(addr & 0x1f) * 4];
420 
+			pObj->HPos = (pObj->HPos & 0xFF) | SignExtend[(Byte >> 0) & 1];
421 
+			pObj++->Size = Byte & 2;
422 
+			pObj->HPos = (pObj->HPos & 0xFF) | SignExtend[(Byte >> 2) & 1];
423 
+			pObj++->Size = Byte & 8;
424 
+			pObj->HPos = (pObj->HPos & 0xFF) | SignExtend[(Byte >> 4) & 1];
425 
+			pObj++->Size = Byte & 32;
426 
+			pObj->HPos = (pObj->HPos & 0xFF) | SignExtend[(Byte >> 6) & 1];
427 
+			pObj->Size = Byte & 128;
428 
+		}
429 
+
430 
+		PPU.OAMFlip ^= 1;
431 
+		if (!(PPU.OAMFlip & 1))
432 
+		{
433 
+			++PPU.OAMAddr;
434 
+			PPU.OAMAddr &= 0x1ff;
435 
+			if (PPU.OAMPriorityRotation && PPU.FirstSprite != (PPU.OAMAddr >> 1))
436 
+			{
437 
+				PPU.FirstSprite = (PPU.OAMAddr & 0xfe) >> 1;
438 
+				IPPU.OBJChanged = true;
439 
+			}
440 
+		}
441 
+		else
442 
+		{
443 
+			if (PPU.OAMPriorityRotation && (PPU.OAMAddr & 1))
444 
+				IPPU.OBJChanged = true;
445 
+		}
446 
+	}
447 
+	else
448 
+	if (!(PPU.OAMFlip & 1))
449 
+	{
450 
+		PPU.OAMWriteRegister &= 0xff00;
451 
+		PPU.OAMWriteRegister |= Byte;
452 
+		PPU.OAMFlip |= 1;
453 
+		if (PPU.OAMPriorityRotation && (PPU.OAMAddr & 1))
454 
+			IPPU.OBJChanged = true;
455 
+	}
456 
+	else
457 
+	{
458 
+		PPU.OAMWriteRegister &= 0x00ff;
459 
+		uint8_t lowbyte = (uint8_t) (PPU.OAMWriteRegister);
460 
+		uint8_t highbyte = Byte;
461 
+		PPU.OAMWriteRegister |= Byte << 8;
462 
+
463 
+		int addr = (PPU.OAMAddr << 1);
464 
+		if (lowbyte != PPU.OAMData[addr] || highbyte != PPU.OAMData[addr + 1])
465 
+		{
466 
+			//FLUSH_REDRAW();
467 
+			PPU.OAMData[addr] = lowbyte;
468 
+			PPU.OAMData[addr + 1] = highbyte;
469 
+			IPPU.OBJChanged = true;
470 
+			if (addr & 2)
471 
+			{
472 
+				// Tile
473 
+				PPU.OBJ[addr = PPU.OAMAddr >> 1].Name = PPU.OAMWriteRegister & 0x1ff;
474 
+				// priority, h and v flip.
475 
+				PPU.OBJ[addr].Palette  = (highbyte >> 1) & 7;
476 
+				PPU.OBJ[addr].Priority = (highbyte >> 4) & 3;
477 
+				PPU.OBJ[addr].HFlip    = (highbyte >> 6) & 1;
478 
+				PPU.OBJ[addr].VFlip    = (highbyte >> 7) & 1;
479 
+			}
480 
+			else
481 
+			{
482 
+				// X position (low)
483 
+				PPU.OBJ[addr = PPU.OAMAddr >> 1].HPos &= 0xff00;
484 
+				PPU.OBJ[addr].HPos |= lowbyte;
485 
+				// Sprite Y position
486 
+				PPU.OBJ[addr].VPos = highbyte;
487 
+			}
488 
+		}
489 
+
490 
+		PPU.OAMFlip &= ~1;
491 
+		++PPU.OAMAddr;
492 
+		if (PPU.OAMPriorityRotation && PPU.FirstSprite != (PPU.OAMAddr >> 1))
493 
+		{
494 
+			PPU.FirstSprite = (PPU.OAMAddr & 0xfe) >> 1;
495 
+			IPPU.OBJChanged = true;
496 
+		}
497 
+	}
498 
+}
499 
+
500 
+// This code is correct, however due to Snes9x's inaccurate timings, some games might be broken by this chage. :(
501 
+#ifdef DEBUGGER
502 
+#define CHECK_INBLANK() \
503 
+	if (!PPU.ForcedBlanking && CPU.V_Counter < PPU.ScreenHeight + FIRST_VISIBLE_LINE) \
504 
+	{ \
505 
+		printf("Invalid VRAM acess at (%04d, %04d) blank:%d\n", CPU.Cycles, CPU.V_Counter, PPU.ForcedBlanking); \
506 
+		if (Settings.BlockInvalidVRAMAccess) \
507 
+			return; \
508 
+	}
509 
+#else
510 
+#define CHECK_INBLANK() \
511 
+	if (Settings.BlockInvalidVRAMAccess && !PPU.ForcedBlanking && CPU.V_Counter < PPU.ScreenHeight + FIRST_VISIBLE_LINE) \
512 
+		return;
513 
+#endif
514 
+
515 
+static inline void REGISTER_2118 (uint8_t Byte)
516 
+{
517 
+	CHECK_INBLANK();
518 
+
519 
+	uint32_t	address;
520 
+
521 
+	if (PPU.VMA.FullGraphicCount)
522 
+	{
523 
+		uint32_t rem = PPU.VMA.Address & PPU.VMA.Mask1;
524 
+		address = (((PPU.VMA.Address & ~PPU.VMA.Mask1) + (rem >> PPU.VMA.Shift) + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) & 0xffff;
525 
+		Memory.VRAM[address] = Byte;
526 
+	}
527 
+	else
528 
+		Memory.VRAM[address = (PPU.VMA.Address << 1) & 0xffff] = Byte;
529 
+
530 
+	IPPU.TileCached[TILE_2BIT][address >> 4] = false;
531 
+	IPPU.TileCached[TILE_4BIT][address >> 5] = false;
532 
+	IPPU.TileCached[TILE_8BIT][address >> 6] = false;
533 
+	IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = false;
534 
+	IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
535 
+	IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = false;
536 
+	IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
537 
+	IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = false;
538 
+	IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
539 
+	IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = false;
540 
+	IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
541 
+
542 
+	if (!PPU.VMA.High)
543 
+	{
544 
+	#ifdef DEBUGGER
545 
+		if (Settings.TraceVRAM && !CPU.InDMAorHDMA)
546 
+			printf("VRAM write byte: $%04X (%d, %d)\n", PPU.VMA.Address, Memory.FillRAM[0x2115] & 3, (Memory.FillRAM[0x2115] & 0x0c) >> 2);
547 
+	#endif
548 
+		PPU.VMA.Address += PPU.VMA.Increment;
549 
+	}
550 
+}
551 
+
552 
+static inline void REGISTER_2119 (uint8_t Byte)
553 
+{
554 
+	CHECK_INBLANK();
555 
+
556 
+	uint32_t	address;
557 
+
558 
+	if (PPU.VMA.FullGraphicCount)
559 
+	{
560 
+		uint32_t rem = PPU.VMA.Address & PPU.VMA.Mask1;
561 
+		address = ((((PPU.VMA.Address & ~PPU.VMA.Mask1) + (rem >> PPU.VMA.Shift) + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) + 1) & 0xffff;
562 
+		Memory.VRAM[address] = Byte;
563 
+	}
564 
+	else
565 
+		Memory.VRAM[address = ((PPU.VMA.Address << 1) + 1) & 0xffff] = Byte;
566 
+
567 
+	IPPU.TileCached[TILE_2BIT][address >> 4] = false;
568 
+	IPPU.TileCached[TILE_4BIT][address >> 5] = false;
569 
+	IPPU.TileCached[TILE_8BIT][address >> 6] = false;
570 
+	IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = false;
571 
+	IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
572 
+	IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = false;
573 
+	IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
574 
+	IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = false;
575 
+	IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
576 
+	IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = false;
577 
+	IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
578 
+
579 
+	if (PPU.VMA.High)
580 
+	{
581 
+	#ifdef DEBUGGER
582 
+		if (Settings.TraceVRAM && !CPU.InDMAorHDMA)
583 
+			printf("VRAM write word: $%04X (%d, %d)\n", PPU.VMA.Address, Memory.FillRAM[0x2115] & 3, (Memory.FillRAM[0x2115] & 0x0c) >> 2);
584 
+	#endif
585 
+		PPU.VMA.Address += PPU.VMA.Increment;
586 
+	}
587 
+}
588 
+
589 
+static inline void REGISTER_2118_tile (uint8_t Byte)
590 
+{
591 
+	CHECK_INBLANK();
592 
+
593 
+	uint32_t rem = PPU.VMA.Address & PPU.VMA.Mask1;
594 
+	uint32_t address = (((PPU.VMA.Address & ~PPU.VMA.Mask1) + (rem >> PPU.VMA.Shift) + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) & 0xffff;
595 
+
596 
+	Memory.VRAM[address] = Byte;
597 
+
598 
+	IPPU.TileCached[TILE_2BIT][address >> 4] = false;
599 
+	IPPU.TileCached[TILE_4BIT][address >> 5] = false;
600 
+	IPPU.TileCached[TILE_8BIT][address >> 6] = false;
601 
+	IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = false;
602 
+	IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
603 
+	IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = false;
604 
+	IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
605 
+	IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = false;
606 
+	IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
607 
+	IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = false;
608 
+	IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
609 
+
610 
+	if (!PPU.VMA.High)
611 
+		PPU.VMA.Address += PPU.VMA.Increment;
612 
+}
613 
+
614 
+static inline void REGISTER_2119_tile (uint8_t Byte)
615 
+{
616 
+	CHECK_INBLANK();
617 
+
618 
+	uint32_t rem = PPU.VMA.Address & PPU.VMA.Mask1;
619 
+	uint32_t address = ((((PPU.VMA.Address & ~PPU.VMA.Mask1) + (rem >> PPU.VMA.Shift) + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) + 1) & 0xffff;
620 
+
621 
+	Memory.VRAM[address] = Byte;
622 
+
623 
+	IPPU.TileCached[TILE_2BIT][address >> 4] = false;
624 
+	IPPU.TileCached[TILE_4BIT][address >> 5] = false;
625 
+	IPPU.TileCached[TILE_8BIT][address >> 6] = false;
626 
+	IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = false;
627 
+	IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
628 
+	IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = false;
629 
+	IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
630 
+	IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = false;
631 
+	IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
632 
+	IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = false;
633 
+	IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
634 
+
635 
+	if (PPU.VMA.High)
636 
+		PPU.VMA.Address += PPU.VMA.Increment;
637 
+}
638 
+
639 
+static inline void REGISTER_2118_linear (uint8_t Byte)
640 
+{
641 
+	CHECK_INBLANK();
642 
+
643 
+	uint32_t	address;
644 
+
645 
+	Memory.VRAM[address = (PPU.VMA.Address << 1) & 0xffff] = Byte;
646 
+
647 
+	IPPU.TileCached[TILE_2BIT][address >> 4] = false;
648 
+	IPPU.TileCached[TILE_4BIT][address >> 5] = false;
649 
+	IPPU.TileCached[TILE_8BIT][address >> 6] = false;
650 
+	IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = false;
651 
+	IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
652 
+	IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = false;
653 
+	IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
654 
+	IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = false;
655 
+	IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
656 
+	IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = false;
657 
+	IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
658 
+
659 
+	if (!PPU.VMA.High)
660 
+		PPU.VMA.Address += PPU.VMA.Increment;
661 
+}
662 
+
663 
+static inline void REGISTER_2119_linear (uint8_t Byte)
664 
+{
665 
+	CHECK_INBLANK();
666 
+
667 
+	uint32_t	address;
668 
+
669 
+	Memory.VRAM[address = ((PPU.VMA.Address << 1) + 1) & 0xffff] = Byte;
670 
+
671 
+	IPPU.TileCached[TILE_2BIT][address >> 4] = false;
672 
+	IPPU.TileCached[TILE_4BIT][address >> 5] = false;
673 
+	IPPU.TileCached[TILE_8BIT][address >> 6] = false;
674 
+	IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = false;
675 
+	IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
676 
+	IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = false;
677 
+	IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = false;
678 
+	IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = false;
679 
+	IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
680 
+	IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = false;
681 
+	IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = false;
682 
+
683 
+	if (PPU.VMA.High)
684 
+		PPU.VMA.Address += PPU.VMA.Increment;
685 
+}
686 
+
687 
+/*static inline void REGISTER_2122 (uint8_t Byte)
688 
+{
689 
+	if (PPU.CGFLIP)
690 
+	{
691 
+		if ((Byte & 0x7f) != (PPU.CGDATA[PPU.CGADD] >> 8))
692 
+		{
693 
+			FLUSH_REDRAW();
694 
+			PPU.CGDATA[PPU.CGADD] &= 0x00ff;
695 
+			PPU.CGDATA[PPU.CGADD] |= (Byte & 0x7f) << 8;
696 
+			IPPU.ColorsChanged = true;
697 
+			IPPU.Blue[PPU.CGADD] = IPPU.XB[(Byte >> 2) & 0x1f];
698 
+			IPPU.Green[PPU.CGADD] = IPPU.XB[(PPU.CGDATA[PPU.CGADD] >> 5) & 0x1f];
699 
+			IPPU.ScreenColors[PPU.CGADD] = (uint16_t) BUILD_PIXEL(IPPU.Red[PPU.CGADD], IPPU.Green[PPU.CGADD], IPPU.Blue[PPU.CGADD]);
700 
+		}
701 
+
702 
+		PPU.CGADD++;
703 
+	}
704 
+	else
705 
+	{
706 
+		if (Byte != (uint8_t) (PPU.CGDATA[PPU.CGADD] & 0xff))
707 
+		{
708 
+			FLUSH_REDRAW();
709 
+			PPU.CGDATA[PPU.CGADD] &= 0x7f00;
710 
+			PPU.CGDATA[PPU.CGADD] |= Byte;
711 
+			IPPU.ColorsChanged = true;
712 
+			IPPU.Red[PPU.CGADD] = IPPU.XB[Byte & 0x1f];
713 
+			IPPU.Green[PPU.CGADD] = IPPU.XB[(PPU.CGDATA[PPU.CGADD] >> 5) & 0x1f];
714 
+			IPPU.ScreenColors[PPU.CGADD] = (uint16_t) BUILD_PIXEL(IPPU.Red[PPU.CGADD], IPPU.Green[PPU.CGADD], IPPU.Blue[PPU.CGADD]);
715 
+		}
716 
+	}
717 
+
718 
+	PPU.CGFLIP ^= 1;
719 
+}*/
720 
+
721 
+static inline void REGISTER_2180 (uint8_t Byte)
722 
+{
723 
+	Memory.RAM[PPU.WRAM++] = Byte;
724 
+	PPU.WRAM &= 0x1ffff;
725 
+}
726 
+
727 
+static inline uint8_t REGISTER_4212()
728 
+{
729 
+	uint8_t	byte = 0;
730 
+
731 
+    if ((CPU.V_Counter >= PPU.ScreenHeight + FIRST_VISIBLE_LINE) && (CPU.V_Counter < PPU.ScreenHeight + FIRST_VISIBLE_LINE + 3))
732 
+		byte = 1;
733 
+	if ((CPU.Cycles < Timings.HBlankEnd) || (CPU.Cycles >= Timings.HBlankStart))
734 
+		byte |= 0x40;
735 
+    if (CPU.V_Counter >= PPU.ScreenHeight + FIRST_VISIBLE_LINE)
736 
+		byte |= 0x80;
737 
+
738 
+    return byte;
739 
+}
740 
+
741 
+#endif