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* Fixes for gcc and clang (while they can compile the code, the DLLs made aren't functional, but oh well).

* [2SF] Used more up-to-date asmjit, despite the ugly looking code.

Naram Qashat authored on 2014/09/17 19:51:45
Showing 1 changed files
src/in_gsf/vbam/gba/GBA-thumb.cpp
History View file @ 9315374
... ... 
@@ -9,7 +9,7 @@
9 9
10 10 
 static int clockTicks;
11 11
12 
-static INSN_REGPARM void thumbUnknownInsn(uint32_t opcode)
12 
+static INSN_REGPARM void thumbUnknownInsn(uint32_t)
13 13 
 {
14 14 
 	CPUUndefinedException();
15 15 
 }
... ... 
@@ -1364,7 +1364,7 @@ static INSN_REGPARM void thumbDD(uint32_t opcode)
1364 1364 
 // SWI #comment
1365 1365 
 static INSN_REGPARM void thumbDF(uint32_t opcode)
1366 1366 
 {
1367 
-	uint32_t address = 0;
1367 
+	//uint32_t address = 0;
1368 1368 
 	//clockTicks = codeTicksAccessSeq16(address) * 2 + codeTicksAccess16(address) + 3;
1369 1369 
 	clockTicks = 3;
1370 1370 
 	busPrefetchCount = 0;
Browse code

Updating the VBA-M code to revision 1231.

Naram Qashat authored on 2014/09/08 12:20:28
Showing 1 changed files
src/in_gsf/vbam/gba/GBA-thumb.cpp
History View file @ bee3026
... ... 
@@ -19,671 +19,27 @@ static INSN_REGPARM void thumbUnknownInsn(uint32_t opcode)
19 19 
 template<typename T> static inline T NEG(const T &i) { return i >> 31; }
20 20 
 template<typename T> static inline T POS(const T &i) { return ~i >> 31; }
21 21
22 
-#ifndef C_CORE
23 
-# ifdef __GNUC__
24 
-#  ifdef __POWERPC__
25 
-#   define ADD_RD_RS_RN(N) \
26 
-{ \
27 
-	register int Flags; \
28 
-	register int Result; \
29 
-	asm volatile("addco. %0, %2, %3\n" \
30 
-		"mcrxr cr1\n" \
31 
-		"mfcr %1\n" \
32 
-		: "=r" (Result), \
33 
-		"=r" (Flags) \
34 
-		: "r" (reg[source].I), \
35 
-		"r" (reg[N].I) \
36 
-		); \
37 
-	reg[dest].I = Result; \
38 
-	Z_FLAG = (Flags >> 29) & 1; \
39 
-	N_FLAG = (Flags >> 31) & 1; \
40 
-	C_FLAG = (Flags >> 25) & 1; \
41 
-	V_FLAG = (Flags >> 26) & 1; \
42 
-}
43 
-#   define ADD_RD_RS_O3(N) \
44 
-{ \
45 
-	register int Flags; \
46 
-	register int Result; \
47 
-	asm volatile("addco. %0, %2, %3\n" \
48 
-		"mcrxr cr1\n" \
49 
-		"mfcr %1\n" \
50 
-		: "=r" (Result), \
51 
-		"=r" (Flags) \
52 
-		: "r" (reg[source].I), \
53 
-		"r" (N) \
54 
-		); \
55 
-	reg[dest].I = Result; \
56 
-	Z_FLAG = (Flags >> 29) & 1; \
57 
-	N_FLAG = (Flags >> 31) & 1; \
58 
-	C_FLAG = (Flags >> 25) & 1; \
59 
-	V_FLAG = (Flags >> 26) & 1; \
60 
-}
61 
-#   define ADD_RD_RS_O3_0 ADD_RD_RS_O3
62 
-#   define ADD_RN_O8(d) \
63 
-{ \
64 
-	register int Flags; \
65 
-	register int Result; \
66 
-	asm volatile("addco. %0, %2, %3\n" \
67 
-		"mcrxr cr1\n" \
68 
-		"mfcr %1\n" \
69 
-		: "=r" (Result), \
70 
-		"=r" (Flags) \
71 
-		: "r" (reg[(d)].I), \
72 
-		"r" (opcode & 255) \
73 
-		); \
74 
-	reg[(d)].I = Result; \
75 
-	Z_FLAG = (Flags >> 29) & 1; \
76 
-	N_FLAG = (Flags >> 31) & 1; \
77 
-	C_FLAG = (Flags >> 25) & 1; \
78 
-	V_FLAG = (Flags >> 26) & 1; \
79 
-}
80 
-#   define CMN_RD_RS \
81 
-{ \
82 
-	register int Flags; \
83 
-	register int Result; \
84 
-	asm volatile("addco. %0, %2, %3\n" \
85 
-		"mcrxr cr1\n" \
86 
-		"mfcr %1\n" \
87 
-		: "=r" (Result), \
88 
-		"=r" (Flags) \
89 
-		: "r" (reg[dest].I), \
90 
-		"r" (value) \
91 
-		); \
92 
-	Z_FLAG = (Flags >> 29) & 1; \
93 
-	N_FLAG = (Flags >> 31) & 1; \
94 
-	C_FLAG = (Flags >> 25) & 1; \
95 
-	V_FLAG = (Flags >> 26) & 1; \
96 
-}
97 
-#   define ADC_RD_RS \
98 
-{ \
99 
-	register int Flags; \
100 
-	register int Result; \
101 
-	asm volatile("mtspr 1, %4\n" \ /* reg 1 is xer */
102 
-		"addeo. %0, %2, %3\n" \
103 
-		"mcrxr cr1\n" \
104 
-		"mfcr %1\n" \
105 
-		: "=r" (Result), \
106 
-		"=r" (Flags) \
107 
-		: "r" (reg[dest].I), \
108 
-		"r" (value), \
109 
-		"r" (C_FLAG << 29) \
110 
-		); \
111 
-	reg[dest].I = Result; \
112 
-	Z_FLAG = (Flags >> 29) & 1; \
113 
-	N_FLAG = (Flags >> 31) & 1; \
114 
-	C_FLAG = (Flags >> 25) & 1; \
115 
-	V_FLAG = (Flags >> 26) & 1; \
116 
-}
117 
-#   define SUB_RD_RS_RN(N) \
118 
-{ \
119 
-	register int Flags; \
120 
-	register int Result; \
121 
-	asm volatile("subco. %0, %2, %3\n" \
122 
-		"mcrxr cr1\n" \
123 
-		"mfcr %1\n" \
124 
-		: "=r" (Result), \
125 
-		"=r" (Flags) \
126 
-		: "r" (reg[source].I), \
127 
-		"r" (reg[N].I) \
128 
-		); \
129 
-	reg[dest].I = Result; \
130 
-	Z_FLAG = (Flags >> 29) & 1; \
131 
-	N_FLAG = (Flags >> 31) & 1; \
132 
-	C_FLAG = (Flags >> 25) & 1; \
133 
-	V_FLAG = (Flags >> 26) & 1; \
134 
-}
135 
-#   define SUB_RD_RS_O3(N) \
136 
-{ \
137 
-	register int Flags; \
138 
-	register int Result; \
139 
-	asm volatile("subco. %0, %2, %3\n" \
140 
-		"mcrxr cr1\n" \
141 
-		"mfcr %1\n" \
142 
-		: "=r" (Result), \
143 
-		"=r" (Flags) \
144 
-		: "r" (reg[source].I), \
145 
-		"r" (N) \
146 
-		); \
147 
-	reg[dest].I = Result; \
148 
-	Z_FLAG = (Flags >> 29) & 1; \
149 
-	N_FLAG = (Flags >> 31) & 1; \
150 
-	C_FLAG = (Flags >> 25) & 1; \
151 
-	V_FLAG = (Flags >> 26) & 1; \
152 
-}
153 
-#   define SUB_RD_RS_O3_0 SUB_RD_RS_O3
154 
-#   define SUB_RN_O8(d) \
155 
-{ \
156 
-	register int Flags; \
157 
-	register int Result; \
158 
-	asm volatile("subco. %0, %2, %3\n" \
159 
-		"mcrxr cr1\n" \
160 
-		"mfcr %1\n" \
161 
-		: "=r" (Result), \
162 
-		"=r" (Flags) \
163 
-		: "r" (reg[(d)].I), \
164 
-		"r" (opcode & 255) \
165 
-		); \
166 
-	reg[(d)].I = Result; \
167 
-	Z_FLAG = (Flags >> 29) & 1; \
168 
-	N_FLAG = (Flags >> 31) & 1; \
169 
-	C_FLAG = (Flags >> 25) & 1; \
170 
-	V_FLAG = (Flags >> 26) & 1; \
171 
-}
172 
-#   define CMP_RN_O8(d) \
173 
-{ \
174 
-	register int Flags; \
175 
-	register int Result; \
176 
-	asm volatile("subco. %0, %2, %3\n" \
177 
-		"mcrxr cr1\n" \
178 
-		"mfcr %1\n" \
179 
-		: "=r" (Result), \
180 
-		"=r" (Flags) \
181 
-		: "r" (reg[(d)].I), \
182 
-		"r" (opcode & 255) \
183 
-		); \
184 
-	Z_FLAG = (Flags >> 29) & 1; \
185 
-	N_FLAG = (Flags >> 31) & 1; \
186 
-	C_FLAG = (Flags >> 25) & 1; \
187 
-	V_FLAG = (Flags >> 26) & 1; \
188 
-}
189 
-#   define SBC_RD_RS \
190 
-{ \
191 
-	register int Flags; \
192 
-	register int Result; \
193 
-	asm volatile("mtspr 1, %4\n" \ /* reg 1 is xer */
194 
-		"subfeo. %0, %3, %2\n" \
195 
-		"mcrxr cr1\n" \
196 
-		"mfcr %1\n" \
197 
-		: "=r" (Result), \
198 
-		"=r" (Flags) \
199 
-		: "r" (reg[dest].I), \
200 
-		"r" (value), \
201 
-		"r" (C_FLAG << 29) \
202 
-		); \
203 
-	reg[dest].I = Result; \
204 
-	Z_FLAG = (Flags >> 29) & 1; \
205 
-	N_FLAG = (Flags >> 31) & 1; \
206 
-	C_FLAG = (Flags >> 25) & 1; \
207 
-	V_FLAG = (Flags >> 26) & 1; \
208 
-}
209 
-#   define NEG_RD_RS \
210 
-{ \
211 
-	register int Flags; \
212 
-	register int Result; \
213 
-	asm volatile("subfco. %0, %2, %3\n" \
214 
-		"mcrxr cr1\n" \
215 
-		"mfcr %1\n" \
216 
-		: "=r" (Result), \
217 
-		"=r" (Flags) \
218 
-		: "r" (reg[source].I), \
219 
-		"r" (0) \
220 
-		); \
221 
-	reg[dest].I = Result; \
222 
-	Z_FLAG = (Flags >> 29) & 1; \
223 
-	N_FLAG = (Flags >> 31) & 1; \
224 
-	C_FLAG = (Flags >> 25) & 1; \
225 
-	V_FLAG = (Flags >> 26) & 1; \
226 
-}
227 
-#   define CMP_RD_RS \
228 
-{ \
229 
-	register int Flags; \
230 
-	register int Result; \
231 
-	asm volatile("subco. %0, %2, %3\n" \
232 
-		"mcrxr cr1\n" \
233 
-		"mfcr %1\n" \
234 
-		: "=r" (Result), \
235 
-		"=r" (Flags) \
236 
-		: "r" (reg[dest].I), \
237 
-		"r" (value) \
238 
-		); \
239 
-	Z_FLAG = (Flags >> 29) & 1; \
240 
-	N_FLAG = (Flags >> 31) & 1; \
241 
-	C_FLAG = (Flags >> 25) & 1; \
242 
-	V_FLAG = (Flags >> 26) & 1; \
243 
-}
244 
-#  else
245 
-#   define EMIT1(op, arg) #op " " arg "; "
246 
-#   define EMIT2(op, src, dest) #op " " src ", " dest "; "
247 
-#   define KONST(val) "$" #val
248 
-#   define ASMVAR(cvar) ASMVAR2(__USER_LABEL_PREFIX__, cvar)
249 
-#   define ASMVAR2(prefix, cvar) STRING(prefix) cvar
250 
-#   define STRING(x) #x
251 
-#   define VAR(var) ASMVAR(#var)
252 
-#   define REGREF1(index) ASMVAR("reg(" index ")")
253 
-#   define REGREF2(index, scale) ASMVAR("reg(," index "," #scale ")")
254 
-#   define eax "%%eax"
255 
-#   define ecx "%%ecx"
256 
-#   define edx "%%edx"
257 
-#   define ADD_RN_O8(d) \
258 
-	asm("andl $0xFF, %%eax;" \
259 
-		"addl %%eax, %0;" \
260 
-		EMIT1(setsb, VAR(N_FLAG)) \
261 
-		EMIT1(setzb, VAR(Z_FLAG)) \
262 
-		EMIT1(setcb, VAR(C_FLAG)) \
263 
-		EMIT1(setob, VAR(V_FLAG)) \
264 
-		: "=m" (reg[(d)].I));
265 
-#   define CMN_RD_RS \
266 
-	asm("add %0, %1;" \
267 
-		EMIT1(setsb, VAR(N_FLAG)) \
268 
-		EMIT1(setzb, VAR(Z_FLAG)) \
269 
-		EMIT1(setcb, VAR(C_FLAG)) \
270 
-		EMIT1(setob, VAR(V_FLAG)) \
271 
-		: \
272 
-		: "r" (value), "r" (reg[dest].I) : "1");
273 
-#   define ADC_RD_RS \
274 
-	asm(EMIT2(bt, KONST(0), VAR(C_FLAG)) \
275 
-		"adc %1, %%ebx;" \
276 
-		EMIT1(setsb, VAR(N_FLAG)) \
277 
-		EMIT1(setzb, VAR(Z_FLAG)) \
278 
-		EMIT1(setcb, VAR(C_FLAG)) \
279 
-		EMIT1(setob, VAR(V_FLAG)) \
280 
-		: "=b" (reg[dest].I) \
281 
-		: "r" (value), "b" (reg[dest].I));
282 
-#   define SUB_RN_O8(d) \
283 
-	asm("andl $0xFF, %%eax;" \
284 
-		"subl %%eax, %0;" \
285 
-		EMIT1(setsb, VAR(N_FLAG)) \
286 
-		EMIT1(setzb, VAR(Z_FLAG)) \
287 
-		EMIT1(setncb, VAR(C_FLAG)) \
288 
-		EMIT1(setob, VAR(V_FLAG)) \
289 
-		: "=m" (reg[(d)].I));
290 
-#   define MOV_RN_O8(d) \
291 
-	asm("andl $0xFF, %%eax;" \
292 
-		EMIT2(movb, KONST(0), VAR(N_FLAG)) \
293 
-		"movl %%eax, %0;" \
294 
-		EMIT1(setzb, VAR(Z_FLAG)) \
295 
-		: "=m" (reg[(d)].I));
296 
-#   define CMP_RN_O8(d) \
297 
-	asm("andl $0xFF, %%eax;" \
298 
-		"cmpl %%eax, %0;" \
299 
-		EMIT1(setsb, VAR(N_FLAG)) \
300 
-		EMIT1(setzb, VAR(Z_FLAG)) \
301 
-		EMIT1(setncb, VAR(C_FLAG)) \
302 
-		EMIT1(setob, VAR(V_FLAG)) \
303 
-		: \
304 
-		: "m" (reg[(d)].I));
305 
-#   define SBC_RD_RS \
306 
-	asm volatile(EMIT2(bt, KONST(0), VAR(C_FLAG)) \
307 
-		"cmc;" \
308 
-		"sbb %1, %%ebx;" \
309 
-		EMIT1(setsb, VAR(N_FLAG)) \
310 
-		EMIT1(setzb, VAR(Z_FLAG)) \
311 
-		EMIT1(setncb, VAR(C_FLAG)) \
312 
-		EMIT1(setob, VAR(V_FLAG)) \
313 
-		: "=b" (reg[dest].I) \
314 
-		: "r" (value), "b" (reg[dest].I) : "cc", "memory");
315 
-#   define LSL_RD_RS \
316 
-	asm("shl %%cl, %%eax;" \
317 
-		EMIT1(setcb, VAR(C_FLAG)) \
318 
-		: "=a" (value) \
319 
-		: "a" (reg[dest].I), "c" (value));
320 
-#   define LSR_RD_RS \
321 
-	asm("shr %%cl, %%eax;" \
322 
-		EMIT1(setcb, VAR(C_FLAG)) \
323 
-		: "=a" (value) \
324 
-		: "a" (reg[dest].I), "c" (value));
325 
-#   define ASR_RD_RS \
326 
-	asm("sar %%cl, %%eax;" \
327 
-		EMIT1(setcb, VAR(C_FLAG)) \
328 
-		: "=a" (value) \
329 
-		: "a" (reg[dest].I), "c" (value));
330 
-#   define ROR_RD_RS \
331 
-	asm("ror %%cl, %%eax;" \
332 
-		EMIT1(setcb, VAR(C_FLAG)) \
333 
-		: "=a" (value) \
334 
-		: "a" (reg[dest].I), "c" (value));
335 
-#   define NEG_RD_RS \
336 
-	asm("neg %%ebx;" \
337 
-		EMIT1(setsb, VAR(N_FLAG)) \
338 
-		EMIT1(setzb, VAR(Z_FLAG)) \
339 
-		EMIT1(setncb, VAR(C_FLAG)) \
340 
-		EMIT1(setob, VAR(V_FLAG)) \
341 
-		: "=b" (reg[dest].I) \
342 
-		: "b" (reg[source].I));
343 
-#   define CMP_RD_RS \
344 
-	asm("sub %0, %1;" \
345 
-		EMIT1(setsb, VAR(N_FLAG)) \
346 
-		EMIT1(setzb, VAR(Z_FLAG)) \
347 
-		EMIT1(setncb, VAR(C_FLAG)) \
348 
-		EMIT1(setob, VAR(V_FLAG)) \
349 
-		: \
350 
-		: "r" (value), "r" (reg[dest].I) : "1");
351 
-#   define IMM5_INSN(OP, N) \
352 
-	asm("movl %%eax,%%ecx;" \
353 
-		"shrl $1,%%eax;" \
354 
-		"andl $7,%%ecx;" \
355 
-		"andl $0x1C,%%eax;" \
356 
-		EMIT2(movl, REGREF1(eax), edx) \
357 
-		OP \
358 
-		EMIT1(setsb, VAR(N_FLAG)) \
359 
-		EMIT1(setzb, VAR(Z_FLAG)) \
360 
-		EMIT2(movl, edx, REGREF2(ecx, 4)) \
361 
-		: : "i" (N))
362 
-#   define IMM5_INSN_0(OP) \
363 
-	asm("movl %%eax,%%ecx;" \
364 
-		"shrl $1,%%eax;" \
365 
-		"andl $7,%%ecx;" \
366 
-		"andl $0x1C,%%eax;" \
367 
-		EMIT2(movl, REGREF1(eax), edx) \
368 
-		OP \
369 
-		EMIT1(setsb, VAR(N_FLAG)) \
370 
-		EMIT1(setzb, VAR(Z_FLAG)) \
371 
-		EMIT2(movl, edx, REGREF2(ecx, 4)) \
372 
-		: : )
373 
-#   define IMM5_LSL \
374 
-	"shll %0,%%edx;" \
375 
-	EMIT1(setcb, VAR(C_FLAG))
376 
-#   define IMM5_LSL_0 \
377 
-	"testl %%edx,%%edx;"
378 
-#   define IMM5_LSR \
379 
-	"shrl %0,%%edx;" \
380 
-	EMIT1(setcb, VAR(C_FLAG))
381 
-#   define IMM5_LSR_0 \
382 
-	"testl %%edx,%%edx;" \
383 
-	EMIT1(setsb, VAR(C_FLAG)) \
384 
-	"xorl %%edx,%%edx;"
385 
-#   define IMM5_ASR \
386 
-	"sarl %0,%%edx;" \
387 
-	EMIT1(setcb, VAR(C_FLAG))
388 
-#   define IMM5_ASR_0 \
389 
-	"sarl $31,%%edx;" \
390 
-	EMIT1(setsb, VAR(C_FLAG))
391 
-#   define THREEARG_INSN(OP, N) \
392 
-	asm("movl %%eax,%%edx;" \
393 
-		"shrl $1,%%edx;" \
394 
-		"andl $0x1C,%%edx;" \
395 
-		"andl $7,%%eax;" \
396 
-		EMIT2(movl, REGREF1(edx), ecx) \
397 
-		OP(N) \
398 
-		EMIT1(setsb, VAR(N_FLAG)) \
399 
-		EMIT1(setzb, VAR(Z_FLAG)) \
400 
-		EMIT2(movl, ecx, REGREF2(eax, 4)) \
401 
-		: : )
402 
-#   define ADD_RD_RS_RN(N) \
403 
-	EMIT2(add, VAR(reg) "+" #N "*4", ecx) \
404 
-	EMIT1(setcb, VAR(C_FLAG)) \
405 
-	EMIT1(setob, VAR(V_FLAG))
406 
-#   define ADD_RD_RS_O3(N) \
407 
-	"add $" #N ",%%ecx;" \
408 
-	EMIT1(setcb, VAR(C_FLAG)) \
409 
-	EMIT1(setob, VAR(V_FLAG))
410 
-#   define ADD_RD_RS_O3_0(N) \
411 
-	EMIT2(movb, KONST(0), VAR(C_FLAG)) \
412 
-	"add $0,%%ecx;" \
413 
-	EMIT2(movb, KONST(0), VAR(V_FLAG))
414 
-#   define SUB_RD_RS_RN(N) \
415 
-	EMIT2(sub, VAR(reg) "+" #N "*4", ecx) \
416 
-	EMIT1(setncb, VAR(C_FLAG)) \
417 
-	EMIT1(setob, VAR(V_FLAG))
418 
-#   define SUB_RD_RS_O3(N) \
419 
-	"sub $" #N ",%%ecx;" \
420 
-	EMIT1(setncb, VAR(C_FLAG)) \
421 
-	EMIT1(setob, VAR(V_FLAG))
422 
-#   define SUB_RD_RS_O3_0(N) \
423 
-	EMIT2(movb, KONST(1), VAR(C_FLAG)) \
424 
-	"sub $0,%%ecx;" \
425 
-	EMIT2(movb, KONST(0), VAR(V_FLAG))
426 
-#  endif
427 
-# else // !__GNUC__
428 
-#  define ADD_RD_RS_RN(N) \
429 
-{ \
430 
-	__asm mov eax, source \
431 
-	__asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
432 
-	__asm add ebx, dword ptr [OFFSET reg + 4 * N] \
433 
-	__asm mov eax, dest \
434 
-	__asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
435 
-	__asm sets byte ptr N_FLAG \
436 
-	__asm setz byte ptr Z_FLAG \
437 
-	__asm setc byte ptr C_FLAG \
438 
-	__asm seto byte ptr V_FLAG \
439 
-}
440 
-#  define ADD_RD_RS_O3(N) \
441 
-{ \
442 
-	__asm mov eax, source \
443 
-	__asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
444 
-	__asm add ebx, N \
445 
-	__asm mov eax, dest \
446 
-	__asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
447 
-	__asm sets byte ptr N_FLAG \
448 
-	__asm setz byte ptr Z_FLAG \
449 
-	__asm setc byte ptr C_FLAG \
450 
-	__asm seto byte ptr V_FLAG \
451 
-}
452 
-#  define ADD_RD_RS_O3_0 \
453 
-{ \
454 
-	__asm mov eax, source \
455 
-	__asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
456 
-	__asm add ebx, 0 \
457 
-	__asm mov eax, dest \
458 
-	__asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
459 
-	__asm sets byte ptr N_FLAG \
460 
-	__asm setz byte ptr Z_FLAG \
461 
-	__asm mov byte ptr C_FLAG, 0 \
462 
-	__asm mov byte ptr V_FLAG, 0 \
463 
-}
464 
-#  define ADD_RN_O8(d) \
465 
-{ \
466 
-	__asm mov ebx, opcode \
467 
-	__asm and ebx, 255 \
468 
-	__asm add dword ptr [OFFSET reg + 4 * (d)], ebx \
469 
-	__asm sets byte ptr N_FLAG \
470 
-	__asm setz byte ptr Z_FLAG \
471 
-	__asm setc byte ptr C_FLAG \
472 
-	__asm seto byte ptr V_FLAG \
473 
-}
474 
-#  define CMN_RD_RS \
475 
-{ \
476 
-	__asm mov eax, dest \
477 
-	__asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
478 
-	__asm add ebx, value \
479 
-	__asm sets byte ptr N_FLAG \
480 
-	__asm setz byte ptr Z_FLAG \
481 
-	__asm setc byte ptr C_FLAG \
482 
-	__asm seto byte ptr V_FLAG \
483 
-}
484 
-#  define ADC_RD_RS \
485 
-{ \
486 
-	__asm mov ebx, dest \
487 
-	__asm mov ebx, dword ptr [OFFSET reg + 4 * ebx] \
488 
-	__asm bt word ptr C_FLAG, 0 \
489 
-	__asm adc ebx, value \
490 
-	__asm mov eax, dest \
491 
-	__asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
492 
-	__asm sets byte ptr N_FLAG \
493 
-	__asm setz byte ptr Z_FLAG \
494 
-	__asm setc byte ptr C_FLAG \
495 
-	__asm seto byte ptr V_FLAG \
496 
-}
497 
-#  define SUB_RD_RS_RN(N) \
498 
-{ \
499 
-	__asm mov eax, source \
500 
-	__asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
501 
-	__asm sub ebx, dword ptr [OFFSET reg + 4 * N] \
502 
-	__asm mov eax, dest \
503 
-	__asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
504 
-	__asm sets byte ptr N_FLAG \
505 
-	__asm setz byte ptr Z_FLAG \
506 
-	__asm setnc byte ptr C_FLAG \
507 
-	__asm seto byte ptr V_FLAG \
508 
-}
509 
-#  define SUB_RD_RS_O3(N) \
510 
-{ \
511 
-	__asm mov eax, source \
512 
-	__asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
513 
-	__asm sub ebx, N \
514 
-	__asm mov eax, dest \
515 
-	__asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
516 
-	__asm sets byte ptr N_FLAG \
517 
-	__asm setz byte ptr Z_FLAG \
518 
-	__asm setnc byte ptr C_FLAG \
519 
-	__asm seto byte ptr V_FLAG \
520 
-}
521 
-#  define SUB_RD_RS_O3_0 \
522 
-{ \
523 
-	__asm mov eax, source \
524 
-	__asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
525 
-	__asm sub ebx, 0 \
526 
-	__asm mov eax, dest \
527 
-	__asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
528 
-	__asm sets byte ptr N_FLAG \
529 
-	__asm setz byte ptr Z_FLAG \
530 
-	__asm mov byte ptr C_FLAG, 1 \
531 
-	__asm mov byte ptr V_FLAG, 0 \
532 
-}
533 
-#  define SUB_RN_O8(d) \
534 
-{ \
535 
-	__asm mov ebx, opcode \
536 
-	__asm and ebx, 255 \
537 
-	__asm sub dword ptr [OFFSET reg + 4 * (d)], ebx \
538 
-	__asm sets byte ptr N_FLAG \
539 
-	__asm setz byte ptr Z_FLAG \
540 
-	__asm setnc byte ptr C_FLAG \
541 
-	__asm seto byte ptr V_FLAG \
542 
-}
543 
-#  define MOV_RN_O8(d) \
544 
-{ \
545 
-	__asm mov eax, opcode \
546 
-	__asm and eax, 255 \
547 
-	__asm mov dword ptr [OFFSET reg + 4 * (d)], eax \
548 
-	__asm sets byte ptr N_FLAG \
549 
-	__asm setz byte ptr Z_FLAG \
550 
-}
551 
-#  define CMP_RN_O8(d) \
552 
-{ \
553 
-	__asm mov eax, dword ptr [OFFSET reg + 4 * (d)] \
554 
-	__asm mov ebx, opcode \
555 
-	__asm and ebx, 255 \
556 
-	__asm sub eax, ebx \
557 
-	__asm sets byte ptr N_FLAG \
558 
-	__asm setz byte ptr Z_FLAG \
559 
-	__asm setnc byte ptr C_FLAG \
560 
-	__asm seto byte ptr V_FLAG \
561 
-}
562 
-#  define SBC_RD_RS \
563 
-{ \
564 
-	__asm mov ebx, dest \
565 
-	__asm mov ebx, dword ptr [OFFSET reg + 4 * ebx] \
566 
-	__asm mov eax, value \
567 
-	__asm bt word ptr C_FLAG, 0 \
568 
-	__asm cmc \
569 
-	__asm sbb ebx, eax \
570 
-	__asm mov eax, dest \
571 
-	__asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
572 
-	__asm sets byte ptr N_FLAG \
573 
-	__asm setz byte ptr Z_FLAG \
574 
-	__asm setnc byte ptr C_FLAG \
575 
-	__asm seto byte ptr V_FLAG \
576 
-}
577 
-#  define LSL_RD_RM_I5 \
578 
-{ \
579 
-	__asm mov eax, source \
580 
-	__asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
581 
-	__asm mov cl, byte ptr shift \
582 
-	__asm shl eax, cl \
583 
-	__asm mov value, eax \
584 
-	__asm setc byte ptr C_FLAG \
585 
-}
586 
-#  define LSL_RD_RS \
587 
-{ \
588 
-	__asm mov eax, dest \
589 
-	__asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
590 
-	__asm mov cl, byte ptr value \
591 
-	__asm shl eax, cl \
592 
-	__asm mov value, eax \
593 
-	__asm setc byte ptr C_FLAG \
594 
-}
595 
-#  define LSR_RD_RM_I5 \
596 
-{ \
597 
-	__asm mov eax, source \
598 
-	__asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
599 
-	__asm mov cl, byte ptr shift \
600 
-	__asm shr eax, cl \
601 
-	__asm mov value, eax \
602 
-	__asm setc byte ptr C_FLAG \
603 
-}
604 
-#  define LSR_RD_RS \
605 
-{ \
606 
-	__asm mov eax, dest \
607 
-	__asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
608 
-	__asm mov cl, byte ptr value \
609 
-	__asm shr eax, cl \
610 
-	__asm mov value, eax \
611 
-	__asm setc byte ptr C_FLAG \
612 
-}
613 
-#  define ASR_RD_RM_I5 \
614 
-{ \
615 
-	__asm mov eax, source \
616 
-	__asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
617 
-	__asm mov cl, byte ptr shift \
618 
-	__asm sar eax, cl \
619 
-	__asm mov value, eax \
620 
-	__asm setc byte ptr C_FLAG \
621 
-}
622 
-#  define ASR_RD_RS \
623 
-{ \
624 
-	__asm mov eax, dest \
625 
-	__asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
626 
-	__asm mov cl, byte ptr value \
627 
-	__asm sar eax, cl \
628 
-	__asm mov value, eax \
629 
-	__asm setc byte ptr C_FLAG \
630 
-}
631 
-#  define ROR_RD_RS \
632 
-{ \
633 
-	__asm mov eax, dest \
634 
-	__asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
635 
-	__asm mov cl, byte ptr value \
636 
-	__asm ror eax, cl \
637 
-	__asm mov value, eax \
638 
-	__asm setc byte ptr C_FLAG \
639 
-}
640 
-#  define NEG_RD_RS \
641 
-{ \
642 
-	__asm mov ebx, source \
643 
-	__asm mov ebx, dword ptr [OFFSET reg + 4 * ebx] \
644 
-	__asm neg ebx \
645 
-	__asm mov eax, dest \
646 
-	__asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
647 
-	__asm sets byte ptr N_FLAG \
648 
-	__asm setz byte ptr Z_FLAG \
649 
-	__asm setnc byte ptr C_FLAG \
650 
-	__asm seto byte ptr V_FLAG \
651 
-}
652 
-#  define CMP_RD_RS \
653 
-{ \
654 
-	__asm mov eax, dest \
655 
-	__asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
656 
-	__asm sub ebx, value \
657 
-	__asm sets byte ptr N_FLAG \
658 
-	__asm setz byte ptr Z_FLAG \
659 
-	__asm setnc byte ptr C_FLAG \
660 
-	__asm seto byte ptr V_FLAG \
661 
-}
662 
-# endif
663 
-#endif
664 
-
665 22 
 // C core
666 
-static inline void ADDCARRY(uint32_t a, uint32_t b, uint32_t c)
23 
+auto ADDCARRY = [](uint32_t a, uint32_t b, uint32_t c)
667 24 
 {
668 25 
 	C_FLAG = !!((NEG(a) & NEG(b)) | (NEG(a) & POS(c)) | (NEG(b) & POS(c)));
669 
-}
670 
-static inline void ADDOVERFLOW(uint32_t a, uint32_t b, uint32_t c)
26 
+};
27 
+auto ADDOVERFLOW = [](uint32_t a, uint32_t b, uint32_t c)
671 28 
 {
672 29 
 	V_FLAG = !!((NEG(a) & NEG(b) & POS(c)) | (POS(a) & POS(b) & NEG(c)));
673 
-}
674 
-static inline void SUBCARRY(uint32_t a, uint32_t b, uint32_t c)
30 
+};
31 
+auto SUBCARRY = [](uint32_t a, uint32_t b, uint32_t c)
675 32 
 {
676 33 
 	C_FLAG = !!((NEG(a) & POS(b)) | (NEG(a) & POS(c)) | (POS(b) & POS(c)));
677 
-}
678 
-static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c)
34 
+};
35 
+auto SUBOVERFLOW = [](uint32_t a, uint32_t b, uint32_t c)
679 36 
 {
680 37 
 	V_FLAG = !!((NEG(a) & POS(b) & POS(c)) | (POS(a) & NEG(b) & NEG(c)));
681 
-}
682 
-#ifndef ADD_RD_RS_RN
683 
-# define ADD_RD_RS_RN(N) \
38 
+};
39 
+#define ADD_RD_RS_RN(N) \
684 40 
 { \
685 41 
 	uint32_t lhs = reg[source].I; \
686 
-	uint32_t rhs = reg[N].I; \
42 
+	uint32_t rhs = reg[(N)].I; \
687 43 
 	uint32_t res = lhs + rhs; \
688 44 
 	reg[dest].I = res; \
689 45 
 	Z_FLAG = !res; \
... ... 
@@ -691,12 +47,10 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c)
691 47 
 	ADDCARRY(lhs, rhs, res); \
692 48 
 	ADDOVERFLOW(lhs, rhs, res); \
693 49 
 }
694 
-#endif
695 
-#ifndef ADD_RD_RS_O3
696 
-# define ADD_RD_RS_O3(N) \
50 
+#define ADD_RD_RS_O3(N) \
697 51 
 { \
698 52 
 	uint32_t lhs = reg[source].I; \
699 
-	uint32_t rhs = N; \
53 
+	uint32_t rhs = (N); \
700 54 
 	uint32_t res = lhs + rhs; \
701 55 
 	reg[dest].I = res; \
702 56 
 	Z_FLAG = !res; \
... ... 
@@ -704,12 +58,8 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c)
704 58 
 	ADDCARRY(lhs, rhs, res); \
705 59 
 	ADDOVERFLOW(lhs, rhs, res); \
706 60 
 }
707 
-#endif
708 
-#ifndef ADD_RD_RS_O3_0
709 
-# define ADD_RD_RS_O3_0 ADD_RD_RS_O3
710 
-#endif
711 
-#ifndef ADD_RN_O8
712 
-# define ADD_RN_O8(d) \
61 
+#define ADD_RD_RS_O3_0 ADD_RD_RS_O3
62 
+#define ADD_RN_O8(d) \
713 63 
 { \
714 64 
 	uint32_t lhs = reg[(d)].I; \
715 65 
 	uint32_t rhs = opcode & 255; \
... ... 
@@ -720,9 +70,7 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c)
720 70 
 	ADDCARRY(lhs, rhs, res); \
721 71 
 	ADDOVERFLOW(lhs, rhs, res); \
722 72 
 }
723 
-#endif
724 
-#ifndef CMN_RD_RS
725 
-# define CMN_RD_RS \
73 
+#define CMN_RD_RS \
726 74 
 { \
727 75 
 	uint32_t lhs = reg[dest].I; \
728 76 
 	uint32_t rhs = value; \
... ... 
@@ -732,9 +80,7 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c)
732 80 
 	ADDCARRY(lhs, rhs, res); \
733 81 
 	ADDOVERFLOW(lhs, rhs, res); \
734 82 
 }
735 
-#endif
736 
-#ifndef ADC_RD_RS
737 
-# define ADC_RD_RS \
83 
+#define ADC_RD_RS \
738 84 
 { \
739 85 
 	uint32_t lhs = reg[dest].I; \
740 86 
 	uint32_t rhs = value; \
... ... 
@@ -745,12 +91,10 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c)
745 91 
 	ADDCARRY(lhs, rhs, res); \
746 92 
 	ADDOVERFLOW(lhs, rhs, res); \
747 93 
 }
748 
-#endif
749 
-#ifndef SUB_RD_RS_RN
750 
-# define SUB_RD_RS_RN(N) \
94 
+#define SUB_RD_RS_RN(N) \
751 95 
 { \
752 96 
 	uint32_t lhs = reg[source].I; \
753 
-	uint32_t rhs = reg[N].I; \
97 
+	uint32_t rhs = reg[(N)].I; \
754 98 
 	uint32_t res = lhs - rhs; \
755 99 
 	reg[dest].I = res; \
756 100 
 	Z_FLAG = !res; \
... ... 
@@ -758,25 +102,19 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c)
758 102 
 	SUBCARRY(lhs, rhs, res); \
759 103 
 	SUBOVERFLOW(lhs, rhs, res); \
760 104 
 }
761 
-#endif
762 
-#ifndef SUB_RD_RS_O3
763 
-# define SUB_RD_RS_O3(N) \
105 
+#define SUB_RD_RS_O3(N) \
764 106 
 { \
765 107 
 	uint32_t lhs = reg[source].I; \
766 
-	uint32_t rhs = N; \
108 
+	uint32_t rhs = (N); \
767 109 
 	uint32_t res = lhs - rhs; \
768 
-	reg[dest].I = res; \
110 
+	reg[dest].I = res;\
769 111 
 	Z_FLAG = !res; \
770 112 
 	N_FLAG = !!NEG(res); \
771 113 
 	SUBCARRY(lhs, rhs, res); \
772 114 
 	SUBOVERFLOW(lhs, rhs, res); \
773 115 
 }
774 
-#endif
775 
-#ifndef SUB_RD_RS_O3_0
776 
-# define SUB_RD_RS_O3_0 SUB_RD_RS_O3
777 
-#endif
778 
-#ifndef SUB_RN_O8
779 
-# define SUB_RN_O8(d) \
116 
+#define SUB_RD_RS_O3_0 SUB_RD_RS_O3
117 
+#define SUB_RN_O8(d) \
780 118 
 { \
781 119 
 	uint32_t lhs = reg[(d)].I; \
782 120 
 	uint32_t rhs = opcode & 255; \
... ... 
@@ -787,17 +125,13 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c)
787 125 
 	SUBCARRY(lhs, rhs, res); \
788 126 
 	SUBOVERFLOW(lhs, rhs, res); \
789 127 
 }
790 
-#endif
791 
-#ifndef MOV_RN_O8
792 
-# define MOV_RN_O8(d) \
128 
+#define MOV_RN_O8(d) \
793 129 
 { \
794 
-	reg[d].I = opcode & 255; \
130 
+	reg[(d)].I = opcode & 255; \
795 131 
 	N_FLAG = false; \
796 132 
 	Z_FLAG = !reg[d].I; \
797 133 
 }
798 
-#endif
799 
-#ifndef CMP_RN_O8
800 
-# define CMP_RN_O8(d) \
134 
+#define CMP_RN_O8(d) \
801 135 
 { \
802 136 
 	uint32_t lhs = reg[(d)].I; \
803 137 
 	uint32_t rhs = opcode & 255; \
... ... 
@@ -807,9 +141,7 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c)
807 141 
 	SUBCARRY(lhs, rhs, res); \
808 142 
 	SUBOVERFLOW(lhs, rhs, res); \
809 143 
 }
810 
-#endif
811 
-#ifndef SBC_RD_RS
812 
-# define SBC_RD_RS \
144 
+#define SBC_RD_RS \
813 145 
 { \
814 146 
 	uint32_t lhs = reg[dest].I; \
815 147 
 	uint32_t rhs = value; \
... ... 
@@ -820,58 +152,42 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c)
820 152 
 	SUBCARRY(lhs, rhs, res); \
821 153 
 	SUBOVERFLOW(lhs, rhs, res); \
822 154 
 }
823 
-#endif
824 
-#ifndef LSL_RD_RM_I5
825 
-# define LSL_RD_RM_I5 \
155 
+#define LSL_RD_RM_I5 \
826 156 
 { \
827 157 
 	C_FLAG = !!((reg[source].I >> (32 - shift)) & 1); \
828 158 
 	value = reg[source].I << shift; \
829 159 
 }
830 
-#endif
831 
-#ifndef LSL_RD_RS
832 
-# define LSL_RD_RS \
160 
+#define LSL_RD_RS \
833 161 
 { \
834 162 
 	C_FLAG = !!((reg[dest].I >> (32 - value)) & 1); \
835 163 
 	value = reg[dest].I << value; \
836 164 
 }
837 
-#endif
838 
-#ifndef LSR_RD_RM_I5
839 
-# define LSR_RD_RM_I5 \
165 
+#define LSR_RD_RM_I5 \
840 166 
 { \
841 167 
 	C_FLAG = !!((reg[source].I >> (shift - 1)) & 1); \
842 168 
 	value = reg[source].I >> shift; \
843 169 
 }
844 
-#endif
845 
-#ifndef LSR_RD_RS
846 
-# define LSR_RD_RS \
170 
+#define LSR_RD_RS \
847 171 
 { \
848 172 
 	C_FLAG = !!((reg[dest].I >> (value - 1)) & 1); \
849 173 
 	value = reg[dest].I >> value; \
850 174 
 }
851 
-#endif
852 
-#ifndef ASR_RD_RM_I5
853 
-# define ASR_RD_RM_I5 \
175 
+#define ASR_RD_RM_I5 \
854 176 
 { \
855 177 
 	C_FLAG = !!((static_cast<int32_t>(reg[source].I) >> static_cast<int>(shift - 1)) & 1); \
856 178 
 	value = static_cast<int32_t>(reg[source].I) >> static_cast<int>(shift); \
857 179 
 }
858 
-#endif
859 
-#ifndef ASR_RD_RS
860 
-# define ASR_RD_RS \
180 
+#define ASR_RD_RS \
861 181 
 { \
862 182 
 	C_FLAG = !!((static_cast<int32_t>(reg[dest].I) >> static_cast<int>(value - 1)) & 1); \
863 183 
 	value = static_cast<int32_t>(reg[dest].I) >> static_cast<int>(value); \
864 184 
 }
865 
-#endif
866 
-#ifndef ROR_RD_RS
867 
-# define ROR_RD_RS \
185 
+#define ROR_RD_RS \
868 186 
 { \
869 187 
 	C_FLAG = !!((reg[dest].I >> (value - 1)) & 1); \
870 188 
 	value = (reg[dest].I << (32 - value)) | (reg[dest].I >> value); \
871 
-}
872 
-#endif
873 
-#ifndef NEG_RD_RS
874 
-# define NEG_RD_RS \
189 
+ }
190 
+#define NEG_RD_RS \
875 191 
 { \
876 192 
 	uint32_t lhs = reg[source].I; \
877 193 
 	uint32_t rhs = 0; \
... ... 
@@ -882,9 +198,7 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c)
882 198 
 	SUBCARRY(rhs, lhs, res); \
883 199 
 	SUBOVERFLOW(rhs, lhs, res); \
884 200 
 }
885 
-#endif
886 
-#ifndef CMP_RD_RS
887 
-# define CMP_RD_RS \
201 
+#define CMP_RD_RS \
888 202 
 { \
889 203 
 	uint32_t lhs = reg[dest].I; \
890 204 
 	uint32_t rhs = value; \
... ... 
@@ -894,17 +208,15 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c)
894 208 
 	SUBCARRY(lhs, rhs, res); \
895 209 
 	SUBOVERFLOW(lhs, rhs, res); \
896 210 
 }
897 
-#endif
898 
-#ifndef IMM5_INSN
899 
-# define IMM5_INSN(OP, N) \
211 
+#define IMM5_INSN(OP, N) \
900 212 
 	int dest = opcode & 0x07; \
901 213 
 	int source = (opcode >> 3) & 0x07; \
902 214 
 	uint32_t value; \
903 
-	OP(N); \
215 
+	OP((N)); \
904 216 
 	reg[dest].I = value; \
905 217 
 	N_FLAG = !!(value & 0x80000000); \
906 218 
 	Z_FLAG = !value;
907 
-# define IMM5_INSN_0(OP) \
219 
+#define IMM5_INSN_0(OP) \
908 220 
 	int dest = opcode & 0x07; \
909 221 
 	int source = (opcode >> 3) & 0x07; \
910 222 
 	uint32_t value; \
... ... 
@@ -912,21 +224,21 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c)
912 224 
 	reg[dest].I = value; \
913 225 
 	N_FLAG = !!(value & 0x80000000); \
914 226 
 	Z_FLAG = !value;
915 
-# define IMM5_LSL(N) \
916 
-	int shift = N; \
227 
+#define IMM5_LSL(N) \
228 
+	int shift = (N); \
917 229 
 	LSL_RD_RM_I5;
918 
-# define IMM5_LSL_0 \
230 
+#define IMM5_LSL_0 \
919 231 
 	value = reg[source].I;
920 
-# define IMM5_LSR(N) \
921 
-	int shift = N; \
232 
+#define IMM5_LSR(N) \
233 
+	int shift = (N); \
922 234 
 	LSR_RD_RM_I5;
923 
-# define IMM5_LSR_0 \
235 
+#define IMM5_LSR_0 \
924 236 
 	C_FLAG = !!(reg[source].I & 0x80000000); \
925 237 
 	value = 0;
926 
-# define IMM5_ASR(N) \
927 
-	int shift = N; \
238 
+#define IMM5_ASR(N) \
239 
+	int shift = (N); \
928 240 
 	ASR_RD_RM_I5;
929 
-# define IMM5_ASR_0 \
241 
+#define IMM5_ASR_0 \
930 242 
 	if (reg[source].I & 0x80000000) \
931 243 
 	{ \
932 244 
 		value = 0xFFFFFFFF; \
... ... 
@@ -937,13 +249,10 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c)
937 249 
 		value = 0; \
938 250 
 		C_FLAG = false; \
939 251 
 	}
940 
-#endif
941 
-#ifndef THREEARG_INSN
942 
-# define THREEARG_INSN(OP, N) \
252 
+#define THREEARG_INSN(OP, N) \
943 253 
 	int dest = opcode & 0x07; \
944 254 
 	int source = (opcode >> 3) & 0x07; \
945 
-	OP(N);
946 
-#endif
255 
+	OP((N));
947 256
948 257 
 // Shift instructions /////////////////////////////////////////////////////
949 258
... ... 
@@ -958,28 +267,28 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c)
958 267 
 	static INSN_REGPARM void thumb##BASE##_07(uint32_t opcode) { IMM5_INSN(OP, 7); } \
959 268 
 	static INSN_REGPARM void thumb##BASE##_08(uint32_t opcode) { IMM5_INSN(OP, 8); } \
960 269 
 	static INSN_REGPARM void thumb##BASE##_09(uint32_t opcode) { IMM5_INSN(OP, 9); } \
961 
-	static INSN_REGPARM void thumb##BASE##_0A(uint32_t opcode) { IMM5_INSN(OP, 10); } \
962 
-	static INSN_REGPARM void thumb##BASE##_0B(uint32_t opcode) { IMM5_INSN(OP, 11); } \
963 
-	static INSN_REGPARM void thumb##BASE##_0C(uint32_t opcode) { IMM5_INSN(OP, 12); } \
964 
-	static INSN_REGPARM void thumb##BASE##_0D(uint32_t opcode) { IMM5_INSN(OP, 13); } \
965 
-	static INSN_REGPARM void thumb##BASE##_0E(uint32_t opcode) { IMM5_INSN(OP, 14); } \
966 
-	static INSN_REGPARM void thumb##BASE##_0F(uint32_t opcode) { IMM5_INSN(OP, 15); } \
967 
-	static INSN_REGPARM void thumb##BASE##_10(uint32_t opcode) { IMM5_INSN(OP, 16); } \
968 
-	static INSN_REGPARM void thumb##BASE##_11(uint32_t opcode) { IMM5_INSN(OP, 17); } \
969 
-	static INSN_REGPARM void thumb##BASE##_12(uint32_t opcode) { IMM5_INSN(OP, 18); } \
970 
-	static INSN_REGPARM void thumb##BASE##_13(uint32_t opcode) { IMM5_INSN(OP, 19); } \
971 
-	static INSN_REGPARM void thumb##BASE##_14(uint32_t opcode) { IMM5_INSN(OP, 20); } \
972 
-	static INSN_REGPARM void thumb##BASE##_15(uint32_t opcode) { IMM5_INSN(OP, 21); } \
973 
-	static INSN_REGPARM void thumb##BASE##_16(uint32_t opcode) { IMM5_INSN(OP, 22); } \
974 
-	static INSN_REGPARM void thumb##BASE##_17(uint32_t opcode) { IMM5_INSN(OP, 23); } \
975 
-	static INSN_REGPARM void thumb##BASE##_18(uint32_t opcode) { IMM5_INSN(OP, 24); } \
976 
-	static INSN_REGPARM void thumb##BASE##_19(uint32_t opcode) { IMM5_INSN(OP, 25); } \
977 
-	static INSN_REGPARM void thumb##BASE##_1A(uint32_t opcode) { IMM5_INSN(OP, 26); } \
978 
-	static INSN_REGPARM void thumb##BASE##_1B(uint32_t opcode) { IMM5_INSN(OP, 27); } \
979 
-	static INSN_REGPARM void thumb##BASE##_1C(uint32_t opcode) { IMM5_INSN(OP, 28); } \
980 
-	static INSN_REGPARM void thumb##BASE##_1D(uint32_t opcode) { IMM5_INSN(OP, 29); } \
981 
-	static INSN_REGPARM void thumb##BASE##_1E(uint32_t opcode) { IMM5_INSN(OP, 30); } \
982 
-	static INSN_REGPARM void thumb##BASE##_1F(uint32_t opcode) { IMM5_INSN(OP, 31); }
270 
+	static INSN_REGPARM void thumb##BASE##_0A(uint32_t opcode) { IMM5_INSN(OP,10); } \
271 
+	static INSN_REGPARM void thumb##BASE##_0B(uint32_t opcode) { IMM5_INSN(OP,11); } \
272 
+	static INSN_REGPARM void thumb##BASE##_0C(uint32_t opcode) { IMM5_INSN(OP,12); } \
273 
+	static INSN_REGPARM void thumb##BASE##_0D(uint32_t opcode) { IMM5_INSN(OP,13); } \
274 
+	static INSN_REGPARM void thumb##BASE##_0E(uint32_t opcode) { IMM5_INSN(OP,14); } \
275 
+	static INSN_REGPARM void thumb##BASE##_0F(uint32_t opcode) { IMM5_INSN(OP,15); } \
276 
+	static INSN_REGPARM void thumb##BASE##_10(uint32_t opcode) { IMM5_INSN(OP,16); } \
277 
+	static INSN_REGPARM void thumb##BASE##_11(uint32_t opcode) { IMM5_INSN(OP,17); } \
278 
+	static INSN_REGPARM void thumb##BASE##_12(uint32_t opcode) { IMM5_INSN(OP,18); } \
279 
+	static INSN_REGPARM void thumb##BASE##_13(uint32_t opcode) { IMM5_INSN(OP,19); } \
280 
+	static INSN_REGPARM void thumb##BASE##_14(uint32_t opcode) { IMM5_INSN(OP,20); } \
281 
+	static INSN_REGPARM void thumb##BASE##_15(uint32_t opcode) { IMM5_INSN(OP,21); } \
282 
+	static INSN_REGPARM void thumb##BASE##_16(uint32_t opcode) { IMM5_INSN(OP,22); } \
283 
+	static INSN_REGPARM void thumb##BASE##_17(uint32_t opcode) { IMM5_INSN(OP,23); } \
284 
+	static INSN_REGPARM void thumb##BASE##_18(uint32_t opcode) { IMM5_INSN(OP,24); } \
285 
+	static INSN_REGPARM void thumb##BASE##_19(uint32_t opcode) { IMM5_INSN(OP,25); } \
286 
+	static INSN_REGPARM void thumb##BASE##_1A(uint32_t opcode) { IMM5_INSN(OP,26); } \
287 
+	static INSN_REGPARM void thumb##BASE##_1B(uint32_t opcode) { IMM5_INSN(OP,27); } \
288 
+	static INSN_REGPARM void thumb##BASE##_1C(uint32_t opcode) { IMM5_INSN(OP,28); } \
289 
+	static INSN_REGPARM void thumb##BASE##_1D(uint32_t opcode) { IMM5_INSN(OP,29); } \
290 
+	static INSN_REGPARM void thumb##BASE##_1E(uint32_t opcode) { IMM5_INSN(OP,30); } \
291 
+	static INSN_REGPARM void thumb##BASE##_1F(uint32_t opcode) { IMM5_INSN(OP,31); }
983 292
984 293 
 // LSL Rd, Rm, #Imm 5
985 294 
 DEFINE_IMM5_INSN(IMM5_LSL, 00)
... ... 
@@ -991,24 +300,24 @@ DEFINE_IMM5_INSN(IMM5_ASR, 10)
991 300 
 // 3-argument ADD/SUB /////////////////////////////////////////////////////
992 301
993 302 
 #define DEFINE_REG3_INSN(OP, BASE) \
994 
-	static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP, 0); } \
995 
-	static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP, 1); } \
996 
-	static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP, 2); } \
997 
-	static INSN_REGPARM void thumb##BASE##_3(uint32_t opcode) { THREEARG_INSN(OP, 3); } \
998 
-	static INSN_REGPARM void thumb##BASE##_4(uint32_t opcode) { THREEARG_INSN(OP, 4); } \
999 
-	static INSN_REGPARM void thumb##BASE##_5(uint32_t opcode) { THREEARG_INSN(OP, 5); } \
1000 
-	static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP, 6); } \
1001 
-	static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP, 7); }
303 
+	static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP,0); } \
304 
+	static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP,1); } \
305 
+	static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP,2); } \
306 
+	static INSN_REGPARM void thumb##BASE##_3(uint32_t opcode) { THREEARG_INSN(OP,3); } \
307 
+	static INSN_REGPARM void thumb##BASE##_4(uint32_t opcode) { THREEARG_INSN(OP,4); } \
308 
+	static INSN_REGPARM void thumb##BASE##_5(uint32_t opcode) { THREEARG_INSN(OP,5); } \
309 
+	static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP,6); } \
310 
+	static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP,7); }
1002 311
1003 312 
 #define DEFINE_IMM3_INSN(OP, BASE) \
1004 
-	static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP##_0, 0); } \
1005 
-	static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP, 1); } \
1006 
-	static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP, 2); } \
1007 
-	static INSN_REGPARM void thumb##BASE##_3(uint32_t opcode) { THREEARG_INSN(OP, 3); } \
1008 
-	static INSN_REGPARM void thumb##BASE##_4(uint32_t opcode) { THREEARG_INSN(OP, 4); } \
1009 
-	static INSN_REGPARM void thumb##BASE##_5(uint32_t opcode) { THREEARG_INSN(OP, 5); } \
1010 
-	static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP, 6); } \
1011 
-	static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP, 7); }
313 
+	static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP##_0,0); } \
314 
+	static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP,1); } \
315 
+	static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP,2); } \
316 
+	static INSN_REGPARM void thumb##BASE##_3(uint32_t opcode) { THREEARG_INSN(OP,3); } \
317 
+	static INSN_REGPARM void thumb##BASE##_4(uint32_t opcode) { THREEARG_INSN(OP,4); } \
318 
+	static INSN_REGPARM void thumb##BASE##_5(uint32_t opcode) { THREEARG_INSN(OP,5); } \
319 
+	static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP,6); } \
320 
+	static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP,7); }
1012 321
1013 322 
 // ADD Rd, Rs, Rn
1014 323 
 DEFINE_REG3_INSN(ADD_RD_RS_RN, 18)
... ... 
@@ -1122,9 +431,7 @@ static INSN_REGPARM void thumb40_2(uint32_t opcode)
1122 431 
 			C_FLAG = !!(reg[dest].I & 1);
1123 432 
 		}
1124 433 
 		else if (value < 32)
1125 
-		{
1126 
-			LSL_RD_RS;
1127 
-		}
434 
+			LSL_RD_RS
1128 435 
 		else
1129 436 
 		{
1130 437 
 			value = 0;
... ... 
@@ -1150,9 +457,7 @@ static INSN_REGPARM void thumb40_3(uint32_t opcode)
1150 457 
 			C_FLAG = !!(reg[dest].I & 0x80000000);
1151 458 
 		}
1152 459 
 		else if (value < 32)
1153 
-		{
1154 
-			LSR_RD_RS;
1155 
-		}
460 
+			LSR_RD_RS
1156 461 
 		else
1157 462 
 		{
1158 463 
 			value = 0;
... ... 
@@ -1220,7 +525,7 @@ static INSN_REGPARM void thumb41_3(uint32_t opcode)
1220 525
1221 526 
 	if (value)
1222 527 
 	{
1223 
-		value = value & 0x1f;
528 
+		value &= 0x1f;
1224 529 
 		if (!value)
1225 530 
 			C_FLAG = !!(reg[dest].I & 0x80000000);
1226 531 
 		else
... ... 
@@ -1229,9 +534,9 @@ static INSN_REGPARM void thumb41_3(uint32_t opcode)
1229 534 
 			reg[dest].I = value;
1230 535 
 		}
1231 536 
 	}
537 
+	clockTicks = codeTicksAccess16(armNextPC) + 2;
1232 538 
 	N_FLAG = !!(reg[dest].I & 0x80000000);
1233 539 
 	Z_FLAG = !reg[dest].I;
1234 
-	clockTicks = codeTicksAccess16(armNextPC) + 2;
1235 540 
 }
1236 541
1237 542 
 // TST Rd, Rs
... ... 
@@ -1271,8 +576,8 @@ static INSN_REGPARM void thumb43_0(uint32_t opcode)
1271 576 
 {
1272 577 
 	int dest = opcode & 7;
1273 578 
 	reg[dest].I |= reg[(opcode >> 3) & 7].I;
1274 
-	N_FLAG = !!(reg[dest].I & 0x80000000);
1275 579 
 	Z_FLAG = !reg[dest].I;
580 
+	N_FLAG = !!(reg[dest].I & 0x80000000);
1276 581 
 }
1277 582
1278 583 
 // MUL Rd, Rs
... ... 
@@ -1293,9 +598,9 @@ static INSN_REGPARM void thumb43_1(uint32_t opcode)
1293 598 
 	else
1294 599 
 		clockTicks += 3;
1295 600 
 	busPrefetchCount = (busPrefetchCount << clockTicks) | (0xFF >> (8 - clockTicks));
1296 
-	N_FLAG = !!(reg[dest].I & 0x80000000);
1297 
-	Z_FLAG = !reg[dest].I;
1298 601 
 	clockTicks += codeTicksAccess16(armNextPC) + 1;
602 
+	Z_FLAG = !reg[dest].I;
603 
+	N_FLAG = !!(reg[dest].I & 0x80000000);
1299 604 
 }
1300 605
1301 606 
 // BIC Rd, Rs
... ... 
@@ -1303,8 +608,8 @@ static INSN_REGPARM void thumb43_2(uint32_t opcode)
1303 608 
 {
1304 609 
 	int dest = opcode & 7;
1305 610 
 	reg[dest].I &= ~reg[(opcode >> 3) & 7].I;
1306 
-	N_FLAG = !!(reg[dest].I & 0x80000000);
1307 611 
 	Z_FLAG = !reg[dest].I;
612 
+	N_FLAG = !!(reg[dest].I & 0x80000000);
1308 613 
 }
1309 614
1310 615 
 // MVN Rd, Rs
... ... 
@@ -1312,8 +617,8 @@ static INSN_REGPARM void thumb43_3(uint32_t opcode)
1312 617 
 {
1313 618 
 	int dest = opcode & 7;
1314 619 
 	reg[dest].I = ~reg[(opcode >> 3) & 7].I;
1315 
-	N_FLAG = !!(reg[dest].I & 0x80000000);
1316 620 
 	Z_FLAG = !reg[dest].I;
621 
+	N_FLAG = !!(reg[dest].I & 0x80000000);
1317 622 
 }
1318 623
1319 624 
 // High-register instructions and BX //////////////////////////////////////
... ... 
@@ -1321,7 +626,7 @@ static INSN_REGPARM void thumb43_3(uint32_t opcode)
1321 626 
 // ADD Rd, Hs
1322 627 
 static INSN_REGPARM void thumb44_1(uint32_t opcode)
1323 628 
 {
1324 
-	reg[opcode & 7].I += reg[((opcode >> 3) & 7) + 8].I;
629 
+	reg[opcode&7].I += reg[((opcode >> 3) & 7) + 8].I;
1325 630 
 }
1326 631
1327 632 
 // ADD Hd, Rs
... ... 
@@ -1379,7 +684,7 @@ static INSN_REGPARM void thumb45_3(uint32_t opcode)
1379 684 
 // MOV Rd, Rs
1380 685 
 static INSN_REGPARM void thumb46_0(uint32_t opcode)
1381 686 
 {
1382 
-	reg[opcode & 7].I = reg[(opcode >> 3) & 7].I;
687 
+	reg[opcode & 7].I = reg[((opcode >> 3) & 7)].I;
1383 688 
 	clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1384 689 
 }
1385 690
... ... 
@@ -1650,29 +955,33 @@ static INSN_REGPARM void thumbB0(uint32_t opcode)
1650 955
1651 956 
 // Push and pop ///////////////////////////////////////////////////////////
1652 957
1653 
-#define PUSH_REG(val, r) \
1654 
-	if (opcode & (val)) \
1655 
-	{ \
1656 
-		CPUWriteMemory(address, reg[(r)].I); \
1657 
-		if (!count) \
1658 
-			clockTicks += 1 + dataTicksAccess32(address); \
1659 
-		else \
1660 
-			clockTicks += 1 + dataTicksAccessSeq32(address); \
1661 
-		++count; \
1662 
-		address += 4; \
958 
+auto PUSH_REG = [](uint32_t opcode, uint32_t &address, int &count, uint32_t val, uint32_t r)
959 
+{
960 
+	if (opcode & val)
961 
+	{
962 
+		CPUWriteMemory(address, reg[r].I);
963 
+		if (!count)
964 
+			clockTicks += 1 + dataTicksAccess32(address);
965 
+		else
966 
+			clockTicks += 1 + dataTicksAccessSeq32(address);
967 
+		++count;
968 
+		address += 4;
1663 969 
 	}
970 
+};
1664 971
1665 
-#define POP_REG(val, r) \
1666 
-	if (opcode & (val)) \
1667 
-	{ \
1668 
-		reg[(r)].I = CPUReadMemory(address); \
1669 
-		if (!count) \
1670 
-			clockTicks += 1 + dataTicksAccess32(address); \
1671 
-		else \
1672 
-			clockTicks += 1 + dataTicksAccessSeq32(address); \
1673 
-		++count; \
1674 
-		address += 4; \
972 
+auto POP_REG = [](uint32_t opcode, uint32_t &address, int &count, uint32_t val, uint32_t r)
973 
+{
974 
+	if (opcode & val)
975 
+	{
976 
+		reg[r].I = CPUReadMemory(address);
977 
+		if (!count)
978 
+			clockTicks += 1 + dataTicksAccess32(address);
979 
+		else
980 
+			clockTicks += 1 + dataTicksAccessSeq32(address);
981 
+		++count;
982 
+		address += 4;
1675 983 
 	}
984 
+};
1676 985
1677 986 
 // PUSH {Rlist}
1678 987 
 static INSN_REGPARM void thumbB4(uint32_t opcode)
... ... 
@@ -1682,14 +991,14 @@ static INSN_REGPARM void thumbB4(uint32_t opcode)
1682 991 
 	int count = 0;
1683 992 
 	uint32_t temp = reg[13].I - 4 * cpuBitsSet[opcode & 0xff];
1684 993 
 	uint32_t address = temp & 0xFFFFFFFC;
1685 
-	PUSH_REG(1, 0);
1686 
-	PUSH_REG(2, 1);
1687 
-	PUSH_REG(4, 2);
1688 
-	PUSH_REG(8, 3);
1689 
-	PUSH_REG(16, 4);
1690 
-	PUSH_REG(32, 5);
1691 
-	PUSH_REG(64, 6);
1692 
-	PUSH_REG(128, 7);
994 
+	PUSH_REG(opcode, address, count, 1, 0);
995 
+	PUSH_REG(opcode, address, count, 2, 1);
996 
+	PUSH_REG(opcode, address, count, 4, 2);
997 
+	PUSH_REG(opcode, address, count, 8, 3);
998 
+	PUSH_REG(opcode, address, count, 16, 4);
999 
+	PUSH_REG(opcode, address, count, 32, 5);
1000 
+	PUSH_REG(opcode, address, count, 64, 6);
1001 
+	PUSH_REG(opcode, address, count, 128, 7);
1693 1002 
 	clockTicks += 1 + codeTicksAccess16(armNextPC);
1694 1003 
 	reg[13].I = temp;
1695 1004 
 }
... ... 
@@ -1702,15 +1011,15 @@ static INSN_REGPARM void thumbB5(uint32_t opcode)
1702 1011 
 	int count = 0;
1703 1012 
 	uint32_t temp = reg[13].I - 4 - 4 * cpuBitsSet[opcode & 0xff];
1704 1013 
 	uint32_t address = temp & 0xFFFFFFFC;
1705 
-	PUSH_REG(1, 0);
1706 
-	PUSH_REG(2, 1);
1707 
-	PUSH_REG(4, 2);
1708 
-	PUSH_REG(8, 3);
1709 
-	PUSH_REG(16, 4);
1710 
-	PUSH_REG(32, 5);
1711 
-	PUSH_REG(64, 6);
1712 
-	PUSH_REG(128, 7);
1713 
-	PUSH_REG(256, 14);
1014 
+	PUSH_REG(opcode, address, count, 1, 0);
1015 
+	PUSH_REG(opcode, address, count, 2, 1);
1016 
+	PUSH_REG(opcode, address, count, 4, 2);
1017 
+	PUSH_REG(opcode, address, count, 8, 3);
1018 
+	PUSH_REG(opcode, address, count, 16, 4);
1019 
+	PUSH_REG(opcode, address, count, 32, 5);
1020 
+	PUSH_REG(opcode, address, count, 64, 6);
1021 
+	PUSH_REG(opcode, address, count, 128, 7);
1022 
+	PUSH_REG(opcode, address, count, 256, 14);
1714 1023 
 	clockTicks += 1 + codeTicksAccess16(armNextPC);
1715 1024 
 	reg[13].I = temp;
1716 1025 
 }
... ... 
@@ -1723,14 +1032,14 @@ static INSN_REGPARM void thumbBC(uint32_t opcode)
1723 1032 
 	int count = 0;
1724 1033 
 	uint32_t address = reg[13].I & 0xFFFFFFFC;
1725 1034 
 	uint32_t temp = reg[13].I + 4 * cpuBitsSet[opcode & 0xFF];
1726 
-	POP_REG(1, 0);
1727 
-	POP_REG(2, 1);
1728 
-	POP_REG(4, 2);
1729 
-	POP_REG(8, 3);
1730 
-	POP_REG(16, 4);
1731 
-	POP_REG(32, 5);
1732 
-	POP_REG(64, 6);
1733 
-	POP_REG(128, 7);
1035 
+	POP_REG(opcode, address, count, 1, 0);
1036 
+	POP_REG(opcode, address, count, 2, 1);
1037 
+	POP_REG(opcode, address, count, 4, 2);
1038 
+	POP_REG(opcode, address, count, 8, 3);
1039 
+	POP_REG(opcode, address, count, 16, 4);
1040 
+	POP_REG(opcode, address, count, 32, 5);
1041 
+	POP_REG(opcode, address, count, 64, 6);
1042 
+	POP_REG(opcode, address, count, 128, 7);
1734 1043 
 	reg[13].I = temp;
1735 1044 
 	clockTicks = 2 + codeTicksAccess16(armNextPC);
1736 1045 
 }
... ... 
@@ -1743,14 +1052,14 @@ static INSN_REGPARM void thumbBD(uint32_t opcode)
1743 1052 
 	int count = 0;
1744 1053 
 	uint32_t address = reg[13].I & 0xFFFFFFFC;
1745 1054 
 	uint32_t temp = reg[13].I + 4 + 4 * cpuBitsSet[opcode & 0xFF];
1746 
-	POP_REG(1, 0);
1747 
-	POP_REG(2, 1);
1748 
-	POP_REG(4, 2);
1749 
-	POP_REG(8, 3);
1750 
-	POP_REG(16, 4);
1751 
-	POP_REG(32, 5);
1752 
-	POP_REG(64, 6);
1753 
-	POP_REG(128, 7);
1055 
+	POP_REG(opcode, address, count, 1, 0);
1056 
+	POP_REG(opcode, address, count, 2, 1);
1057 
+	POP_REG(opcode, address, count, 4, 2);
1058 
+	POP_REG(opcode, address, count, 8, 3);
1059 
+	POP_REG(opcode, address, count, 16, 4);
1060 
+	POP_REG(opcode, address, count, 32, 5);
1061 
+	POP_REG(opcode, address, count, 64, 6);
1062 
+	POP_REG(opcode, address, count, 128, 7);
1754 1063 
 	reg[15].I = CPUReadMemory(address) & 0xFFFFFFFE;
1755 1064 
 	if (!count)
1756 1065 
 		clockTicks += 1 + dataTicksAccess32(address);
... ... 
@@ -1777,7 +1086,7 @@ static INSN_REGPARM void thumbC0(uint32_t opcode)
1777 1086 
 	uint32_t temp = reg[regist].I + 4 * cpuBitsSet[opcode & 0xff];
1778 1087 
 	int count = 0;
1779 1088 
 	// store
1780 
-	auto THUMB_STM_REG = [&](int val, int r, uint8_t b)
1089 
+	auto THUMB_STM_REG = [&](uint32_t val, uint32_t r, uint8_t b)
1781 1090 
 	{
1782 1091 
 		if (opcode & val)
1783 1092 
 		{
... ... 
@@ -1812,7 +1121,7 @@ static INSN_REGPARM void thumbC8(uint32_t opcode)
1812 1121 
 	uint32_t temp = reg[regist].I + 4 * cpuBitsSet[opcode & 0xFF];
1813 1122 
 	int count = 0;
1814 1123 
 	// load
1815 
-	auto THUMB_LDM_REG = [&](int val, int r)
1124 
+	auto THUMB_LDM_REG = [&](uint32_t val, uint32_t r)
1816 1125 
 	{
1817 1126 
 		if (opcode & val)
1818 1127 
 		{
... ... 
@@ -2055,6 +1364,8 @@ static INSN_REGPARM void thumbDD(uint32_t opcode)
2055 1364 
 // SWI #comment
2056 1365 
 static INSN_REGPARM void thumbDF(uint32_t opcode)
2057 1366 
 {
1367 
+	uint32_t address = 0;
1368 
+	//clockTicks = codeTicksAccessSeq16(address) * 2 + codeTicksAccess16(address) + 3;
2058 1369 
 	clockTicks = 3;
2059 1370 
 	busPrefetchCount = 0;
2060 1371 
 	CPUSoftwareInterrupt(opcode & 0xFF);
... ... 
@@ -2238,7 +1549,7 @@ static insnfunc_t thumbInsnTable[] =
2238 1549 
 	thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,  // F8
2239 1550 
 	thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,
2240 1551 
 	thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,
2241 
-	thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,
1552 
+	thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8
2242 1553 
 };
2243 1554
2244 1555 
 // Wrapper routine (execution loop) ///////////////////////////////////////
... ... 
@@ -2247,6 +1558,9 @@ int thumbExecute()
2247 1558 
 {
2248 1559 
 	do
2249 1560 
 	{
1561 
+		//if ((armNextPC & 0x0803FFFF) == 0x08020000)
1562 
+		//    busPrefetchCount = 0x100;
1563 
+
2250 1564 
 		uint32_t opcode = cpuPrefetch[0];
2251 1565 
 		cpuPrefetch[0] = cpuPrefetch[1];
2252 1566
Browse code

[GSF] Minor changes.

Naram Qashat authored on 2013/05/16 19:35:37
Showing 1 changed files
src/in_gsf/vbam/gba/GBA-thumb.cpp
History View file @ 201fd2e
... ... 
@@ -663,22 +663,22 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }
663 663 
 #endif
664 664
665 665 
 // C core
666 
-#ifndef ADDCARRY
667 
-# define ADDCARRY(a, b, c) \
666 
+static inline void ADDCARRY(uint32_t a, uint32_t b, uint32_t c)
667 
+{
668 668 
 	C_FLAG = !!((NEG(a) & NEG(b)) | (NEG(a) & POS(c)) | (NEG(b) & POS(c)));
669 
-#endif
670 
-#ifndef ADDOVERFLOW
671 
-# define ADDOVERFLOW(a, b, c) \
669 
+}
670 
+static inline void ADDOVERFLOW(uint32_t a, uint32_t b, uint32_t c)
671 
+{
672 672 
 	V_FLAG = !!((NEG(a) & NEG(b) & POS(c)) | (POS(a) & POS(b) & NEG(c)));
673 
-#endif
674 
-#ifndef SUBCARRY
675 
-# define SUBCARRY(a, b, c) \
673 
+}
674 
+static inline void SUBCARRY(uint32_t a, uint32_t b, uint32_t c)
675 
+{
676 676 
 	C_FLAG = !!((NEG(a) & POS(b)) | (NEG(a) & POS(c)) | (POS(b) & POS(c)));
677 
-#endif
678 
-#ifndef SUBOVERFLOW
679 
-# define SUBOVERFLOW(a, b, c) \
677 
+}
678 
+static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c)
679 
+{
680 680 
 	V_FLAG = !!((NEG(a) & POS(b) & POS(c)) | (POS(a) & NEG(b) & NEG(c)));
681 
-#endif
681 
+}
682 682 
 #ifndef ADD_RD_RS_RN
683 683 
 # define ADD_RD_RS_RN(N) \
684 684 
 { \
... ... 
@@ -1767,31 +1767,6 @@ static INSN_REGPARM void thumbBD(uint32_t opcode)
1767 1767
1768 1768 
 // Load/store multiple ////////////////////////////////////////////////////
1769 1769
1770 
-#define THUMB_STM_REG(val, r, b) \
1771 
-	if (opcode & (val)) \
1772 
-	{ \
1773 
-		CPUWriteMemory(address, reg[(r)].I); \
1774 
-		reg[(b)].I = temp; \
1775 
-		if (!count) \
1776 
-			clockTicks += 1 + dataTicksAccess32(address); \
1777 
-		else \
1778 
-			clockTicks += 1 + dataTicksAccessSeq32(address); \
1779 
-		++count; \
1780 
-		address += 4; \
1781 
-	}
1782 
-
1783 
-#define THUMB_LDM_REG(val, r) \
1784 
-	if (opcode & (val)) \
1785 
-	{ \
1786 
-		reg[(r)].I = CPUReadMemory(address); \
1787 
-		if (!count) \
1788 
-			clockTicks += 1 + dataTicksAccess32(address); \
1789 
-		else \
1790 
-			clockTicks += 1 + dataTicksAccessSeq32(address); \
1791 
-		++count; \
1792 
-		address += 4; \
1793 
-	}
1794 
-
1795 1770 
 // STM R0~7!, {Rlist}
1796 1771 
 static INSN_REGPARM void thumbC0(uint32_t opcode)
1797 1772 
 {
... ... 
@@ -1802,6 +1777,20 @@ static INSN_REGPARM void thumbC0(uint32_t opcode)
1802 1777 
 	uint32_t temp = reg[regist].I + 4 * cpuBitsSet[opcode & 0xff];
1803 1778 
 	int count = 0;
1804 1779 
 	// store
1780 
+	auto THUMB_STM_REG = [&](int val, int r, uint8_t b)
1781 
+	{
1782 
+		if (opcode & val)
1783 
+		{
1784 
+			CPUWriteMemory(address, reg[r].I);
1785 
+			reg[b].I = temp;
1786 
+			if (!count)
1787 
+				clockTicks += 1 + dataTicksAccess32(address);
1788 
+			else
1789 
+				clockTicks += 1 + dataTicksAccessSeq32(address);
1790 
+			++count;
1791 
+			address += 4;
1792 
+		}
1793 
+	};
1805 1794 
 	THUMB_STM_REG(1, 0, regist);
1806 1795 
 	THUMB_STM_REG(2, 1, regist);
1807 1796 
 	THUMB_STM_REG(4, 2, regist);
... ... 
@@ -1823,6 +1812,19 @@ static INSN_REGPARM void thumbC8(uint32_t opcode)
1823 1812 
 	uint32_t temp = reg[regist].I + 4 * cpuBitsSet[opcode & 0xFF];
1824 1813 
 	int count = 0;
1825 1814 
 	// load
1815 
+	auto THUMB_LDM_REG = [&](int val, int r)
1816 
+	{
1817 
+		if (opcode & val)
1818 
+		{
1819 
+			reg[r].I = CPUReadMemory(address);
1820 
+			if (!count)
1821 
+				clockTicks += 1 + dataTicksAccess32(address);
1822 
+			else
1823 
+				clockTicks += 1 + dataTicksAccessSeq32(address);
1824 
+			++count;
1825 
+			address += 4;
1826 
+		}
1827 
+	};
1826 1828 
 	THUMB_LDM_REG(1, 0);
1827 1829 
 	THUMB_LDM_REG(2, 1);
1828 1830 
 	THUMB_LDM_REG(4, 2);
Browse code

[GSF] Some more code cleanup, also removed a few files that were unneeded.

Naram Qashat authored on 2013/05/16 01:25:34
Showing 1 changed files
src/in_gsf/vbam/gba/GBA-thumb.cpp
History View file @ 91cc309
... ... 
@@ -5,10 +5,6 @@
5 5 
 #include "Sound.h"
6 6 
 #include "bios.h"
7 7
8 
-#ifdef _MSC_VER
9 
-# define snprintf _snprintf
10 
-#endif
11 
-
12 8 
 ///////////////////////////////////////////////////////////////////////////
13 9
14 10 
 static int clockTicks;
... ... 
@@ -20,8 +16,8 @@ static INSN_REGPARM void thumbUnknownInsn(uint32_t opcode)
20 16
21 17 
 // Common macros //////////////////////////////////////////////////////////
22 18
23 
-static inline uint32_t NEG(uint32_t i) { return i >> 31; }
24 
-static inline uint32_t POS(uint32_t i) { return ~i >> 31; }
19 
+template<typename T> static inline T NEG(const T &i) { return i >> 31; }
20 
+template<typename T> static inline T POS(const T &i) { return ~i >> 31; }
25 21
26 22 
 #ifndef C_CORE
27 23 
 # ifdef __GNUC__
... ... 
@@ -82,7 +78,7 @@ static inline uint32_t POS(uint32_t i) { return ~i >> 31; }
82 78 
 	V_FLAG = (Flags >> 26) & 1; \
83 79 
 }
84 80 
 #   define CMN_RD_RS \
85 
-{\
81 
+{ \
86 82 
 	register int Flags; \
87 83 
 	register int Result; \
88 84 
 	asm volatile("addco. %0, %2, %3\n" \
... ... 
@@ -105,7 +101,7 @@ static inline uint32_t POS(uint32_t i) { return ~i >> 31; }
105 101 
 	asm volatile("mtspr 1, %4\n" \ /* reg 1 is xer */
106 102 
 		"addeo. %0, %2, %3\n" \
107 103 
 		"mcrxr cr1\n" \
108 
-		"mfcr	%1\n" \
104 
+		"mfcr %1\n" \
109 105 
 		: "=r" (Result), \
110 106 
 		"=r" (Flags) \
111 107 
 		: "r" (reg[dest].I), \
... ... 
@@ -221,7 +217,7 @@ static inline uint32_t POS(uint32_t i) { return ~i >> 31; }
221 217 
 		"=r" (Flags) \
222 218 
 		: "r" (reg[source].I), \
223 219 
 		"r" (0) \
224 
-	); \
220 
+		); \
225 221 
 	reg[dest].I = Result; \
226 222 
 	Z_FLAG = (Flags >> 29) & 1; \
227 223 
 	N_FLAG = (Flags >> 31) & 1; \
... ... 
@@ -259,7 +255,7 @@ static inline uint32_t POS(uint32_t i) { return ~i >> 31; }
259 255 
 #   define ecx "%%ecx"
260 256 
 #   define edx "%%edx"
261 257 
 #   define ADD_RN_O8(d) \
262 
-	asm("andl $0xFF, %%eax;"\
258 
+	asm("andl $0xFF, %%eax;" \
263 259 
 		"addl %%eax, %0;" \
264 260 
 		EMIT1(setsb, VAR(N_FLAG)) \
265 261 
 		EMIT1(setzb, VAR(Z_FLAG)) \
... ... 
@@ -352,7 +348,7 @@ static inline uint32_t POS(uint32_t i) { return ~i >> 31; }
352 348 
 		EMIT1(setob, VAR(V_FLAG)) \
353 349 
 		: \
354 350 
 		: "r" (value), "r" (reg[dest].I) : "1");
355 
-#   define IMM5_INSN(OP,N) \
351 
+#   define IMM5_INSN(OP, N) \
356 352 
 	asm("movl %%eax,%%ecx;" \
357 353 
 		"shrl $1,%%eax;" \
358 354 
 		"andl $7,%%ecx;" \
... ... 
@@ -361,7 +357,7 @@ static inline uint32_t POS(uint32_t i) { return ~i >> 31; }
361 357 
 		OP \
362 358 
 		EMIT1(setsb, VAR(N_FLAG)) \
363 359 
 		EMIT1(setzb, VAR(Z_FLAG)) \
364 
-		EMIT2(movl, edx, REGREF2(ecx,4)) \
360 
+		EMIT2(movl, edx, REGREF2(ecx, 4)) \
365 361 
 		: : "i" (N))
366 362 
 #   define IMM5_INSN_0(OP) \
367 363 
 	asm("movl %%eax,%%ecx;" \
... ... 
@@ -372,25 +368,25 @@ static inline uint32_t POS(uint32_t i) { return ~i >> 31; }
372 368 
 		OP \
373 369 
 		EMIT1(setsb, VAR(N_FLAG)) \
374 370 
 		EMIT1(setzb, VAR(Z_FLAG)) \
375 
-		EMIT2(movl, edx, REGREF2(ecx,4)) \
371 
+		EMIT2(movl, edx, REGREF2(ecx, 4)) \
376 372 
 		: : )
377 373 
 #   define IMM5_LSL \
378 
-	"shll %0,%%edx;"\
374 
+	"shll %0,%%edx;" \
379 375 
 	EMIT1(setcb, VAR(C_FLAG))
380 376 
 #   define IMM5_LSL_0 \
381 377 
 	"testl %%edx,%%edx;"
382 378 
 #   define IMM5_LSR \
383 
-	"shrl %0,%%edx;"\
379 
+	"shrl %0,%%edx;" \
384 380 
 	EMIT1(setcb, VAR(C_FLAG))
385 381 
 #   define IMM5_LSR_0 \
386 
-	"testl %%edx,%%edx;"\
382 
+	"testl %%edx,%%edx;" \
387 383 
 	EMIT1(setsb, VAR(C_FLAG)) \
388 384 
 	"xorl %%edx,%%edx;"
389 385 
 #   define IMM5_ASR \
390 
-	"sarl %0,%%edx;"\
386 
+	"sarl %0,%%edx;" \
391 387 
 	EMIT1(setcb, VAR(C_FLAG))
392 
-#  define IMM5_ASR_0 \
393 
-	"sarl $31,%%edx;"\
388 
+#   define IMM5_ASR_0 \
389 
+	"sarl $31,%%edx;" \
394 390 
 	EMIT1(setsb, VAR(C_FLAG))
395 391 
 #   define THREEARG_INSN(OP, N) \
396 392 
 	asm("movl %%eax,%%edx;" \
... ... 
@@ -401,7 +397,7 @@ static inline uint32_t POS(uint32_t i) { return ~i >> 31; }
401 397 
 		OP(N) \
402 398 
 		EMIT1(setsb, VAR(N_FLAG)) \
403 399 
 		EMIT1(setzb, VAR(Z_FLAG)) \
404 
-		EMIT2(movl, ecx, REGREF2(eax,4)) \
400 
+		EMIT2(movl, ecx, REGREF2(eax, 4)) \
405 401 
 		: : )
406 402 
 #   define ADD_RD_RS_RN(N) \
407 403 
 	EMIT2(add, VAR(reg) "+" #N "*4", ecx) \
... ... 
@@ -420,7 +416,7 @@ static inline uint32_t POS(uint32_t i) { return ~i >> 31; }
420 416 
 	EMIT1(setncb, VAR(C_FLAG)) \
421 417 
 	EMIT1(setob, VAR(V_FLAG))
422 418 
 #   define SUB_RD_RS_O3(N) \
423 
-	"sub $"#N",%%ecx;" \
419 
+	"sub $" #N ",%%ecx;" \
424 420 
 	EMIT1(setncb, VAR(C_FLAG)) \
425 421 
 	EMIT1(setob, VAR(V_FLAG))
426 422 
 #   define SUB_RD_RS_O3_0(N) \
... ... 
@@ -718,7 +714,7 @@ static inline uint32_t POS(uint32_t i) { return ~i >> 31; }
718 714 
 	uint32_t lhs = reg[(d)].I; \
719 715 
 	uint32_t rhs = opcode & 255; \
720 716 
 	uint32_t res = lhs + rhs; \
721 
-	reg[(d)].I = res;\
717 
+	reg[(d)].I = res; \
722 718 
 	Z_FLAG = !res; \
723 719 
 	N_FLAG = !!NEG(res); \
724 720 
 	ADDCARRY(lhs, rhs, res); \
... ... 
@@ -863,7 +859,7 @@ static inline uint32_t POS(uint32_t i) { return ~i >> 31; }
863 859 
 #ifndef ASR_RD_RS
864 860 
 # define ASR_RD_RS \
865 861 
 { \
866 
-	C_FLAG = !!((static_cast<int32_t>(reg[dest].I >> static_cast<int>(value - 1)) & 1); \
862 
+	C_FLAG = !!((static_cast<int32_t>(reg[dest].I) >> static_cast<int>(value - 1)) & 1); \
867 863 
 	value = static_cast<int32_t>(reg[dest].I) >> static_cast<int>(value); \
868 864 
 }
869 865 
 #endif
... ... 
@@ -1224,7 +1220,7 @@ static INSN_REGPARM void thumb41_3(uint32_t opcode)
1224 1220
1225 1221 
 	if (value)
1226 1222 
 	{
1227 
-		value &= 0x1f;
1223 
+		value = value & 0x1f;
1228 1224 
 		if (!value)
1229 1225 
 			C_FLAG = !!(reg[dest].I & 0x80000000);
1230 1226 
 		else
... ... 
@@ -1233,9 +1229,9 @@ static INSN_REGPARM void thumb41_3(uint32_t opcode)
1233 1229 
 			reg[dest].I = value;
1234 1230 
 		}
1235 1231 
 	}
1236 
-	clockTicks = codeTicksAccess16(armNextPC) + 2;
1237 1232 
 	N_FLAG = !!(reg[dest].I & 0x80000000);
1238 1233 
 	Z_FLAG = !reg[dest].I;
1234 
+	clockTicks = codeTicksAccess16(armNextPC) + 2;
1239 1235 
 }
1240 1236
1241 1237 
 // TST Rd, Rs
... ... 
@@ -1275,8 +1271,8 @@ static INSN_REGPARM void thumb43_0(uint32_t opcode)
1275 1271 
 {
1276 1272 
 	int dest = opcode & 7;
1277 1273 
 	reg[dest].I |= reg[(opcode >> 3) & 7].I;
1278 
-	Z_FLAG = !reg[dest].I;
1279 1274 
 	N_FLAG = !!(reg[dest].I & 0x80000000);
1275 
+	Z_FLAG = !reg[dest].I;
1280 1276 
 }
1281 1277
1282 1278 
 // MUL Rd, Rs
... ... 
@@ -1289,7 +1285,7 @@ static INSN_REGPARM void thumb43_1(uint32_t opcode)
1289 1285 
 	if (static_cast<int32_t>(rm) < 0)
1290 1286 
 		rm = ~rm;
1291 1287 
 	if (!(rm & 0xFFFFFF00))
1292 
-		; // No-op
1288 
+		; /* No-op */
1293 1289 
 	else if (!(rm & 0xFFFF0000))
1294 1290 
 		++clockTicks;
1295 1291 
 	else if (!(rm & 0xFF000000))
... ... 
@@ -1297,9 +1293,9 @@ static INSN_REGPARM void thumb43_1(uint32_t opcode)
1297 1293 
 	else
1298 1294 
 		clockTicks += 3;
1299 1295 
 	busPrefetchCount = (busPrefetchCount << clockTicks) | (0xFF >> (8 - clockTicks));
1300 
-	clockTicks += codeTicksAccess16(armNextPC) + 1;
1301 
-	Z_FLAG = !reg[dest].I;
1302 1296 
 	N_FLAG = !!(reg[dest].I & 0x80000000);
1297 
+	Z_FLAG = !reg[dest].I;
1298 
+	clockTicks += codeTicksAccess16(armNextPC) + 1;
1303 1299 
 }
1304 1300
1305 1301 
 // BIC Rd, Rs
... ... 
@@ -1307,8 +1303,8 @@ static INSN_REGPARM void thumb43_2(uint32_t opcode)
1307 1303 
 {
1308 1304 
 	int dest = opcode & 7;
1309 1305 
 	reg[dest].I &= ~reg[(opcode >> 3) & 7].I;
1310 
-	Z_FLAG = !reg[dest].I;
1311 1306 
 	N_FLAG = !!(reg[dest].I & 0x80000000);
1307 
+	Z_FLAG = !reg[dest].I;
1312 1308 
 }
1313 1309
1314 1310 
 // MVN Rd, Rs
... ... 
@@ -1316,8 +1312,8 @@ static INSN_REGPARM void thumb43_3(uint32_t opcode)
1316 1312 
 {
1317 1313 
 	int dest = opcode & 7;
1318 1314 
 	reg[dest].I = ~reg[(opcode >> 3) & 7].I;
1319 
-	Z_FLAG = !reg[dest].I;
1320 1315 
 	N_FLAG = !!(reg[dest].I & 0x80000000);
1316 
+	Z_FLAG = !reg[dest].I;
1321 1317 
 }
1322 1318
1323 1319 
 // High-register instructions and BX //////////////////////////////////////
... ... 
@@ -1339,7 +1335,7 @@ static INSN_REGPARM void thumb44_2(uint32_t opcode)
1339 1335 
 		reg[15].I += 2;
1340 1336 
 		THUMB_PREFETCH();
1341 1337 
 		clockTicks = codeTicksAccessSeq16(armNextPC) * 2 + codeTicksAccess16(armNextPC) + 3;
1342 
-  }
1338 
+	}
1343 1339 
 }
1344 1340
1345 1341 
 // ADD Hd, Hs
... ... 
@@ -1538,7 +1534,7 @@ static INSN_REGPARM void thumb5E(uint32_t opcode)
1538 1534 
 	if (!busPrefetchCount)
1539 1535 
 		busPrefetch = busPrefetchEnable;
1540 1536 
 	uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I;
1541 
-	reg[opcode & 7].I = (uint32_t)CPUReadHalfWordSigned(address);
1537 
+	reg[opcode & 7].I = static_cast<uint32_t>(CPUReadHalfWordSigned(address));
1542 1538 
 	clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1543 1539 
 }
1544 1540
... ... 
@@ -1803,7 +1799,7 @@ static INSN_REGPARM void thumbC0(uint32_t opcode)
1803 1799 
 	if (!busPrefetchCount)
1804 1800 
 		busPrefetch = busPrefetchEnable;
1805 1801 
 	uint32_t address = reg[regist].I & 0xFFFFFFFC;
1806 
-	uint32_t temp = reg[regist].I + 4*cpuBitsSet[opcode & 0xff];
1802 
+	uint32_t temp = reg[regist].I + 4 * cpuBitsSet[opcode & 0xff];
1807 1803 
 	int count = 0;
1808 1804 
 	// store
1809 1805 
 	THUMB_STM_REG(1, 0, regist);
... ... 
@@ -1824,7 +1820,7 @@ static INSN_REGPARM void thumbC8(uint32_t opcode)
1824 1820 
 	if (!busPrefetchCount)
1825 1821 
 		busPrefetch = busPrefetchEnable;
1826 1822 
 	uint32_t address = reg[regist].I & 0xFFFFFFFC;
1827 
-	uint32_t temp = reg[regist].I + 4*cpuBitsSet[opcode & 0xFF];
1823 
+	uint32_t temp = reg[regist].I + 4 * cpuBitsSet[opcode & 0xFF];
1828 1824 
 	int count = 0;
1829 1825 
 	// load
1830 1826 
 	THUMB_LDM_REG(1, 0);
... ... 
@@ -2057,7 +2053,6 @@ static INSN_REGPARM void thumbDD(uint32_t opcode)
2057 2053 
 // SWI #comment
2058 2054 
 static INSN_REGPARM void thumbDF(uint32_t opcode)
2059 2055 
 {
2060 
-	uint32_t address = 0;
2061 2056 
 	clockTicks = 3;
2062 2057 
 	busPrefetchCount = 0;
2063 2058 
 	CPUSoftwareInterrupt(opcode & 0xFF);
Browse code

[GSF] Massive code cleanup.

(As an aside, blargg's code style makes me go blarg myself.)

Naram Qashat authored on 2013/05/14 01:07:18
Showing 1 changed files
src/in_gsf/vbam/gba/GBA-thumb.cpp
History View file @ 260239f
... ... 
@@ -1,30 +1,12 @@
1 
-#include <stdio.h>
2 
-#include <stdlib.h>
3 
-#include <memory.h>
4 
-#include <stdarg.h>
5 
-#include <string.h>
6 
-
7 1 
 #include "GBA.h"
8 2 
 #include "GBAcpu.h"
9 3 
 #include "GBAinline.h"
10 4 
 #include "Globals.h"
11 
-//#include "EEprom.h"
12 
-//#include "Flash.h"
13 5 
 #include "Sound.h"
14 
-//#include "Sram.h"
15 6 
 #include "bios.h"
16 
-//#include "Cheats.h"
17 
-//#include "../NLS.h"
18 
-//#include "elf.h"
19 
-//#include "../Util.h"
20 
-//#include "../System.h"
21 
-//#include "agbprint.h"
22 
-#ifdef PROFILING
23 
-#include "prof/prof.h"
24 
-#endif
25 7
26 8 
 #ifdef _MSC_VER
27 
-#define snprintf _snprintf
9 
+# define snprintf _snprintf
28 10 
 #endif
29 11
30 12 
 ///////////////////////////////////////////////////////////////////////////
... ... 
@@ -33,1052 +15,1013 @@ static int clockTicks;
33 15
34 16 
 static INSN_REGPARM void thumbUnknownInsn(uint32_t opcode)
35 17 
 {
36 
-#ifdef GBA_LOGGING
37 
-  if(systemVerbose & VERBOSE_UNDEFINED)
38 
-    log("Undefined THUMB instruction %04x at %08x\n", opcode, armNextPC-2);
39 
-#endif
40 
-  CPUUndefinedException();
18 
+	CPUUndefinedException();
41 19 
 }
42 20
43 
-#ifdef BKPT_SUPPORT
44 
-static INSN_REGPARM void thumbBreakpoint(uint32_t opcode)
45 
-{
46 
-  reg[15].I -= 2;
47 
-  armNextPC -= 2;
48 
-  dbgSignal(5, opcode & 255);
49 
-  clockTicks = -1;
50 
-}
51 
-#endif
52 
-
53 21 
 // Common macros //////////////////////////////////////////////////////////
54 22
55 
-#ifdef BKPT_SUPPORT
56 
-# define THUMB_CONSOLE_OUTPUT(a,b) do {                     \
57 
-    if ((opcode == 0x4000) && (reg[0].I == 0xC0DED00D)) {   \
58 
-      dbgOutput((a), (b));                                  \
59 
-    }                                                       \
60 
-} while (0)
61 
-# define UPDATE_OLDREG do {                                 \
62 
-    if (debugger_last) {                                    \
63 
-        snprintf(oldbuffer, sizeof(oldbuffer), "%08X",      \
64 
-                 armState ? reg[15].I - 4 : reg[15].I - 2); \
65 
-        int i;						    \
66 
-        for (i = 0; i < 18; i++) {                          \
67 
-            oldreg[i] = reg[i].I;                           \
68 
-        }                                                   \
69 
-    }                                                       \
70 
-} while (0)
71 
-#else
72 
-# define THUMB_CONSOLE_OUTPUT(a,b)
73 
-# define UPDATE_OLDREG
74 
-#endif
75 
-
76 
-#define NEG(i) ((i) >> 31)
77 
-#define POS(i) ((~(i)) >> 31)
23 
+static inline uint32_t NEG(uint32_t i) { return i >> 31; }
24 
+static inline uint32_t POS(uint32_t i) { return ~i >> 31; }
78 25
79 26 
 #ifndef C_CORE
80 
-#ifdef __GNUC__
81 
-#ifdef __POWERPC__
82 
-  #define ADD_RD_RS_RN(N) \
83 
-            {										\
84 
-                register int Flags;					\
85 
-                register int Result;				\
86 
-                asm volatile("addco. %0, %2, %3\n"	\
87 
-                            "mcrxr cr1\n"			\
88 
-                            "mfcr %1\n"				\
89 
-                            : "=r" (Result), 		\
90 
-                              "=r" (Flags)			\
91 
-                            : "r" (reg[source].I), 	\
92 
-                              "r" (reg[N].I)		\
93 
-                            );						\
94 
-                reg[dest].I = Result;				\
95 
-                Z_FLAG = (Flags >> 29) & 1;			\
96 
-                N_FLAG = (Flags >> 31) & 1;			\
97 
-                C_FLAG = (Flags >> 25) & 1;			\
98 
-                V_FLAG = (Flags >> 26) & 1;			\
99 
-            }
100 
-  #define ADD_RD_RS_O3(N) \
101 
-            {										\
102 
-                register int Flags;					\
103 
-                register int Result;				\
104 
-                asm volatile("addco. %0, %2, %3\n"	\
105 
-                            "mcrxr cr1\n"			\
106 
-                            "mfcr %1\n"				\
107 
-                            : "=r" (Result), 		\
108 
-                              "=r" (Flags)			\
109 
-                            : "r" (reg[source].I), 	\
110 
-                              "r" (N)				\
111 
-                            );						\
112 
-                reg[dest].I = Result;				\
113 
-                Z_FLAG = (Flags >> 29) & 1;			\
114 
-                N_FLAG = (Flags >> 31) & 1;			\
115 
-                C_FLAG = (Flags >> 25) & 1;			\
116 
-                V_FLAG = (Flags >> 26) & 1;			\
117 
-            }
118 
-  #define ADD_RD_RS_O3_0 ADD_RD_RS_O3
119 
-  #define ADD_RN_O8(d) \
120 
-            {\
121 
-                register int Flags;					\
122 
-                register int Result;				\
123 
-                asm volatile("addco. %0, %2, %3\n"	\
124 
-                            "mcrxr cr1\n"			\
125 
-                            "mfcr %1\n"				\
126 
-                            : "=r" (Result), 		\
127 
-                              "=r" (Flags)			\
128 
-                            : "r" (reg[(d)].I), 	\
129 
-                              "r" (opcode & 255)	\
130 
-                            );						\
131 
-                reg[(d)].I = Result;				\
132 
-                Z_FLAG = (Flags >> 29) & 1;			\
133 
-                N_FLAG = (Flags >> 31) & 1;			\
134 
-                C_FLAG = (Flags >> 25) & 1;			\
135 
-                V_FLAG = (Flags >> 26) & 1;			\
136 
-            }
137 
-  #define CMN_RD_RS \
138 
-            {\
139 
-                register int Flags;					\
140 
-                register int Result;				\
141 
-                asm volatile("addco. %0, %2, %3\n"	\
142 
-                            "mcrxr cr1\n"			\
143 
-                            "mfcr %1\n"				\
144 
-                            : "=r" (Result), 		\
145 
-                              "=r" (Flags)			\
146 
-                            : "r" (reg[dest].I), 	\
147 
-                              "r" (value)			\
148 
-                            );						\
149 
-                Z_FLAG = (Flags >> 29) & 1;			\
150 
-                N_FLAG = (Flags >> 31) & 1;			\
151 
-                C_FLAG = (Flags >> 25) & 1;			\
152 
-                V_FLAG = (Flags >> 26) & 1;			\
153 
-            }
154 
-  #define ADC_RD_RS \
155 
-            {\
156 
-                register int Flags;					\
157 
-                register int Result;				\
158 
-                asm volatile("mtspr 1, %4\n"		\ /* reg 1 is xer */
159 
-                             "addeo. %0, %2, %3\n"	\
160 
-                             "mcrxr cr1\n"			\
161 
-                             "mfcr	%1\n"			\
162 
-                             : "=r" (Result),		\
163 
-                               "=r" (Flags)			\
164 
-                             : "r" (reg[dest].I),	\
165 
-                               "r" (value),			\
166 
-                               "r" (C_FLAG << 29)	\
167 
-                             );						\
168 
-                reg[dest].I = Result;				\
169 
-                Z_FLAG = (Flags >> 29) & 1;			\
170 
-                N_FLAG = (Flags >> 31) & 1;			\
171 
-                C_FLAG = (Flags >> 25) & 1;			\
172 
-                V_FLAG = (Flags >> 26) & 1;			\
173 
-            }
174 
-  #define SUB_RD_RS_RN(N) \
175 
-            {\
176 
-                register int Flags;					\
177 
-                register int Result;				\
178 
-                asm volatile("subco. %0, %2, %3\n"	\
179 
-                            "mcrxr cr1\n"			\
180 
-                            "mfcr %1\n"				\
181 
-                            : "=r" (Result), 		\
182 
-                              "=r" (Flags)			\
183 
-                            : "r" (reg[source].I), 	\
184 
-                              "r" (reg[N].I)		\
185 
-                            );						\
186 
-                reg[dest].I = Result;				\
187 
-                Z_FLAG = (Flags >> 29) & 1;			\
188 
-                N_FLAG = (Flags >> 31) & 1;			\
189 
-                C_FLAG = (Flags >> 25) & 1;			\
190 
-                V_FLAG = (Flags >> 26) & 1;			\
191 
-            }
192 
-  #define SUB_RD_RS_O3(N) \
193 
-            {\
194 
-                register int Flags;					\
195 
-                register int Result;				\
196 
-                asm volatile("subco. %0, %2, %3\n"	\
197 
-                            "mcrxr cr1\n"			\
198 
-                            "mfcr %1\n"				\
199 
-                            : "=r" (Result), 		\
200 
-                              "=r" (Flags)			\
201 
-                            : "r" (reg[source].I), 	\
202 
-                              "r" (N)				\
203 
-                            );						\
204 
-                reg[dest].I = Result;				\
205 
-                Z_FLAG = (Flags >> 29) & 1;			\
206 
-                N_FLAG = (Flags >> 31) & 1;			\
207 
-                C_FLAG = (Flags >> 25) & 1;			\
208 
-                V_FLAG = (Flags >> 26) & 1;			\
209 
-            }
210 
-  #define SUB_RD_RS_O3_0 SUB_RD_RS_O3
211 
-  #define SUB_RN_O8(d) \
212 
-            {\
213 
-                register int Flags;					\
214 
-                register int Result;				\
215 
-                asm volatile("subco. %0, %2, %3\n"	\
216 
-                            "mcrxr cr1\n"			\
217 
-                            "mfcr %1\n"				\
218 
-                            : "=r" (Result), 		\
219 
-                              "=r" (Flags)			\
220 
-                            : "r" (reg[(d)].I), 	\
221 
-                              "r" (opcode & 255)	\
222 
-                            );						\
223 
-                reg[(d)].I = Result;				\
224 
-                Z_FLAG = (Flags >> 29) & 1;			\
225 
-                N_FLAG = (Flags >> 31) & 1;			\
226 
-                C_FLAG = (Flags >> 25) & 1;			\
227 
-                V_FLAG = (Flags >> 26) & 1;			\
228 
-            }
229 
-  #define CMP_RN_O8(d) \
230 
-            {\
231 
-                register int Flags;					\
232 
-                register int Result;				\
233 
-                asm volatile("subco. %0, %2, %3\n"	\
234 
-                            "mcrxr cr1\n"			\
235 
-                            "mfcr %1\n"				\
236 
-                            : "=r" (Result), 		\
237 
-                              "=r" (Flags)			\
238 
-                            : "r" (reg[(d)].I), 	\
239 
-                              "r" (opcode & 255)	\
240 
-                            );						\
241 
-                Z_FLAG = (Flags >> 29) & 1;			\
242 
-                N_FLAG = (Flags >> 31) & 1;			\
243 
-                C_FLAG = (Flags >> 25) & 1;			\
244 
-                V_FLAG = (Flags >> 26) & 1;			\
245 
-            }
246 
-  #define SBC_RD_RS \
247 
-            {\
248 
-                register int Flags;					\
249 
-                register int Result;				\
250 
-                asm volatile("mtspr 1, %4\n"		\ /* reg 1 is xer */
251 
-                             "subfeo. %0, %3, %2\n"	\
252 
-                             "mcrxr cr1\n"			\
253 
-                             "mfcr	%1\n"			\
254 
-                             : "=r" (Result),		\
255 
-                               "=r" (Flags)			\
256 
-                             : "r" (reg[dest].I),	\
257 
-                               "r" (value),			\
258 
-                               "r" (C_FLAG << 29) 	\
259 
-                             );						\
260 
-                reg[dest].I = Result;				\
261 
-                Z_FLAG = (Flags >> 29) & 1;			\
262 
-                N_FLAG = (Flags >> 31) & 1;			\
263 
-                C_FLAG = (Flags >> 25) & 1;			\
264 
-                V_FLAG = (Flags >> 26) & 1;			\
265 
-            }
266 
-  #define NEG_RD_RS \
267 
-            {\
268 
-                register int Flags;					\
269 
-                register int Result;				\
270 
-                asm volatile("subfco. %0, %2, %3\n"	\
271 
-                            "mcrxr cr1\n"			\
272 
-                            "mfcr %1\n"				\
273 
-                            : "=r" (Result), 		\
274 
-                              "=r" (Flags)			\
275 
-                            : "r" (reg[source].I), 	\
276 
-                              "r" (0)				\
277 
-                            );						\
278 
-                reg[dest].I = Result;				\
279 
-                Z_FLAG = (Flags >> 29) & 1;			\
280 
-                N_FLAG = (Flags >> 31) & 1;			\
281 
-                C_FLAG = (Flags >> 25) & 1;			\
282 
-                V_FLAG = (Flags >> 26) & 1;			\
283 
-            }
284 
-  #define CMP_RD_RS \
285 
-            {\
286 
-                register int Flags;					\
287 
-                register int Result;				\
288 
-                asm volatile("subco. %0, %2, %3\n"	\
289 
-                            "mcrxr cr1\n"			\
290 
-                            "mfcr %1\n"				\
291 
-                            : "=r" (Result), 		\
292 
-                              "=r" (Flags)			\
293 
-                            : "r" (reg[dest].I), 	\
294 
-                              "r" (value)			\
295 
-                            );						\
296 
-                Z_FLAG = (Flags >> 29) & 1;			\
297 
-                N_FLAG = (Flags >> 31) & 1;			\
298 
-                C_FLAG = (Flags >> 25) & 1;			\
299 
-                V_FLAG = (Flags >> 26) & 1;			\
300 
-            }
301 
-#else
302 
-  #define EMIT1(op,arg)        #op" "arg"; "
303 
-  #define EMIT2(op,src,dest)   #op" "src", "dest"; "
304 
-  #define KONST(val)           "$"#val
305 
-  #define ASMVAR(cvar)         ASMVAR2 (__USER_LABEL_PREFIX__, cvar)
306 
-  #define ASMVAR2(prefix,cvar) STRING (prefix) cvar
307 
-  #define STRING(x)            #x
308 
-  #define VAR(var)             ASMVAR(#var)
309 
-  #define REGREF1(index)       ASMVAR("reg("index")")
310 
-  #define REGREF2(index,scale) ASMVAR("reg(,"index","#scale")")
311 
-  #define eax "%%eax"
312 
-  #define ecx "%%ecx"
313 
-  #define edx "%%edx"
314 
-  #define ADD_RN_O8(d) \
315 
-     asm ("andl $0xFF, %%eax;"\
316 
-          "addl %%eax, %0;"\
317 
-          EMIT1(setsb, VAR(N_FLAG)) \
318 
-          EMIT1(setzb, VAR(Z_FLAG)) \
319 
-          EMIT1(setcb, VAR(C_FLAG)) \
320 
-          EMIT1(setob, VAR(V_FLAG)) \
321 
-          : "=m" (reg[(d)].I));
322 
-  #define CMN_RD_RS \
323 
-     asm ("add %0, %1;"\
324 
-          EMIT1(setsb, VAR(N_FLAG)) \
325 
-          EMIT1(setzb, VAR(Z_FLAG)) \
326 
-          EMIT1(setcb, VAR(C_FLAG)) \
327 
-          EMIT1(setob, VAR(V_FLAG)) \
328 
-          : \
329 
-          : "r" (value), "r" (reg[dest].I):"1");
330 
-  #define ADC_RD_RS \
331 
-     asm (EMIT2(bt,KONST(0),VAR(C_FLAG)) \
332 
-          "adc %1, %%ebx;"\
333 
-          EMIT1(setsb, VAR(N_FLAG)) \
334 
-          EMIT1(setzb, VAR(Z_FLAG)) \
335 
-          EMIT1(setcb, VAR(C_FLAG)) \
336 
-          EMIT1(setob, VAR(V_FLAG)) \
337 
-          : "=b" (reg[dest].I)\
338 
-          : "r" (value), "b" (reg[dest].I));
339 
-  #define SUB_RN_O8(d) \
340 
-     asm ("andl $0xFF, %%eax;"\
341 
-          "subl %%eax, %0;"\
342 
-          EMIT1(setsb, VAR(N_FLAG)) \
343 
-          EMIT1(setzb, VAR(Z_FLAG)) \
344 
-          EMIT1(setncb, VAR(C_FLAG)) \
345 
-          EMIT1(setob, VAR(V_FLAG)) \
346 
-          : "=m" (reg[(d)].I));
347 
-  #define MOV_RN_O8(d) \
348 
-     asm ("andl $0xFF, %%eax;"\
349 
-          EMIT2(movb,KONST(0),VAR(N_FLAG)) \
350 
-          "movl %%eax, %0;"\
351 
-          EMIT1(setzb, VAR(Z_FLAG)) \
352 
-          : "=m" (reg[(d)].I));
353 
-  #define CMP_RN_O8(d) \
354 
-     asm ("andl $0xFF, %%eax;"\
355 
-          "cmpl %%eax, %0;"\
356 
-          EMIT1(setsb, VAR(N_FLAG)) \
357 
-          EMIT1(setzb, VAR(Z_FLAG)) \
358 
-          EMIT1(setncb, VAR(C_FLAG)) \
359 
-          EMIT1(setob, VAR(V_FLAG)) \
360 
-          : \
361 
-          : "m" (reg[(d)].I));
362 
-  #define SBC_RD_RS \
363 
-     asm volatile (EMIT2(bt,KONST(0),VAR(C_FLAG)) \
364 
-                   "cmc;"\
365 
-                   "sbb %1, %%ebx;"\
366 
-                   EMIT1(setsb, VAR(N_FLAG)) \
367 
-                   EMIT1(setzb, VAR(Z_FLAG)) \
368 
-                   EMIT1(setncb, VAR(C_FLAG)) \
369 
-                   EMIT1(setob, VAR(V_FLAG)) \
370 
-                   : "=b" (reg[dest].I)\
371 
-                   : "r" (value), "b" (reg[dest].I) : "cc", "memory");
372 
-  #define LSL_RD_RS \
373 
-         asm ("shl %%cl, %%eax;"\
374 
-              EMIT1(setcb, VAR(C_FLAG)) \
375 
-              : "=a" (value)\
376 
-              : "a" (reg[dest].I), "c" (value));
377 
-  #define LSR_RD_RS \
378 
-         asm ("shr %%cl, %%eax;"\
379 
-              EMIT1(setcb, VAR(C_FLAG)) \
380 
-              : "=a" (value)\
381 
-              : "a" (reg[dest].I), "c" (value));
382 
-  #define ASR_RD_RS \
383 
-         asm ("sar %%cl, %%eax;"\
384 
-              EMIT1(setcb, VAR(C_FLAG)) \
385 
-              : "=a" (value)\
386 
-              : "a" (reg[dest].I), "c" (value));
387 
-  #define ROR_RD_RS \
388 
-         asm ("ror %%cl, %%eax;"\
389 
-              EMIT1(setcb, VAR(C_FLAG)) \
390 
-              : "=a" (value)\
391 
-              : "a" (reg[dest].I), "c" (value));
392 
-  #define NEG_RD_RS \
393 
-     asm ("neg %%ebx;"\
394 
-          EMIT1(setsb, VAR(N_FLAG)) \
395 
-          EMIT1(setzb, VAR(Z_FLAG)) \
396 
-          EMIT1(setncb, VAR(C_FLAG)) \
397 
-          EMIT1(setob, VAR(V_FLAG)) \
398 
-          : "=b" (reg[dest].I)\
399 
-          : "b" (reg[source].I));
400 
-  #define CMP_RD_RS \
401 
-     asm ("sub %0, %1;"\
402 
-          EMIT1(setsb, VAR(N_FLAG)) \
403 
-          EMIT1(setzb, VAR(Z_FLAG)) \
404 
-          EMIT1(setncb, VAR(C_FLAG)) \
405 
-          EMIT1(setob, VAR(V_FLAG)) \
406 
-          : \
407 
-          : "r" (value), "r" (reg[dest].I):"1");
408 
-  #define IMM5_INSN(OP,N) \
409 
-     asm("movl %%eax,%%ecx;"         \
410 
-         "shrl $1,%%eax;"            \
411 
-         "andl $7,%%ecx;"            \
412 
-         "andl $0x1C,%%eax;"         \
413 
-         EMIT2(movl, REGREF1(eax), edx) \
414 
-         OP                          \
415 
-         EMIT1(setsb, VAR(N_FLAG)) \
416 
-         EMIT1(setzb, VAR(Z_FLAG)) \
417 
-         EMIT2(movl, edx, REGREF2(ecx,4)) \
418 
-         : : "i" (N))
419 
-  #define IMM5_INSN_0(OP)            \
420 
-     asm("movl %%eax,%%ecx;"         \
421 
-         "shrl $1,%%eax;"            \
422 
-         "andl $7,%%ecx;"            \
423 
-         "andl $0x1C,%%eax;"         \
424 
-         EMIT2(movl, REGREF1(eax), edx) \
425 
-         OP                          \
426 
-         EMIT1(setsb, VAR(N_FLAG)) \
427 
-         EMIT1(setzb, VAR(Z_FLAG)) \
428 
-         EMIT2(movl, edx, REGREF2(ecx,4)) \
429 
-         : : )
430 
-  #define IMM5_LSL \
431 
-         "shll %0,%%edx;"\
432 
-         EMIT1(setcb, VAR(C_FLAG))
433 
-  #define IMM5_LSL_0 \
434 
-         "testl %%edx,%%edx;"
435 
-  #define IMM5_LSR \
436 
-         "shrl %0,%%edx;"\
437 
-         EMIT1(setcb, VAR(C_FLAG))
438 
-  #define IMM5_LSR_0 \
439 
-         "testl %%edx,%%edx;"\
440 
-         EMIT1(setsb, VAR(C_FLAG)) \
441 
-         "xorl %%edx,%%edx;"
442 
-  #define IMM5_ASR \
443 
-         "sarl %0,%%edx;"\
444 
-         EMIT1(setcb, VAR(C_FLAG))
445 
-  #define IMM5_ASR_0 \
446 
-         "sarl $31,%%edx;"\
447 
-         EMIT1(setsb, VAR(C_FLAG))
448 
-  #define THREEARG_INSN(OP,N) \
449 
-     asm("movl %%eax,%%edx;"       \
450 
-         "shrl $1,%%edx;"          \
451 
-         "andl $0x1C,%%edx;"       \
452 
-         "andl $7,%%eax;"          \
453 
-         EMIT2(movl, REGREF1(edx), ecx) \
454 
-         OP(N)                     \
455 
-         EMIT1(setsb, VAR(N_FLAG)) \
456 
-         EMIT1(setzb, VAR(Z_FLAG)) \
457 
-         EMIT2(movl, ecx, REGREF2(eax,4)) \
458 
-         : : )
459 
-  #define ADD_RD_RS_RN(N)          \
460 
-         EMIT2(add,VAR(reg)"+"#N"*4",ecx) \
461 
-         EMIT1(setcb, VAR(C_FLAG)) \
462 
-         EMIT1(setob, VAR(V_FLAG))
463 
-  #define ADD_RD_RS_O3(N)          \
464 
-         "add $"#N",%%ecx;"        \
465 
-         EMIT1(setcb, VAR(C_FLAG)) \
466 
-         EMIT1(setob, VAR(V_FLAG))
467 
-  #define ADD_RD_RS_O3_0(N)        \
468 
-         EMIT2(movb,KONST(0),VAR(C_FLAG)) \
469 
-         "add $0,%%ecx;"           \
470 
-         EMIT2(movb,KONST(0),VAR(V_FLAG))
471 
-  #define SUB_RD_RS_RN(N) \
472 
-         EMIT2(sub,VAR(reg)"+"#N"*4",ecx) \
473 
-         EMIT1(setncb, VAR(C_FLAG)) \
474 
-         EMIT1(setob, VAR(V_FLAG))
475 
-  #define SUB_RD_RS_O3(N) \
476 
-         "sub $"#N",%%ecx;"        \
477 
-         EMIT1(setncb, VAR(C_FLAG)) \
478 
-         EMIT1(setob, VAR(V_FLAG))
479 
-  #define SUB_RD_RS_O3_0(N)        \
480 
-         EMIT2(movb,KONST(1),VAR(C_FLAG)) \
481 
-         "sub $0,%%ecx;"           \
482 
-         EMIT2(movb,KONST(0),VAR(V_FLAG))
483 
-#endif
484 
-#else // !__GNUC__
485 
-  #define ADD_RD_RS_RN(N) \
486 
-   {\
487 
-     __asm mov eax, source\
488 
-     __asm mov ebx, dword ptr [OFFSET reg+4*eax]\
489 
-     __asm add ebx, dword ptr [OFFSET reg+4*N]\
490 
-     __asm mov eax, dest\
491 
-     __asm mov dword ptr [OFFSET reg+4*eax], ebx\
492 
-     __asm sets byte ptr N_FLAG\
493 
-     __asm setz byte ptr Z_FLAG\
494 
-     __asm setc byte ptr C_FLAG\
495 
-     __asm seto byte ptr V_FLAG\
496 
-   }
497 
-  #define ADD_RD_RS_O3(N) \
498 
-   {\
499 
-     __asm mov eax, source\
500 
-     __asm mov ebx, dword ptr [OFFSET reg+4*eax]\
501 
-     __asm add ebx, N\
502 
-     __asm mov eax, dest\
503 
-     __asm mov dword ptr [OFFSET reg+4*eax], ebx\
504 
-     __asm sets byte ptr N_FLAG\
505 
-     __asm setz byte ptr Z_FLAG\
506 
-     __asm setc byte ptr C_FLAG\
507 
-     __asm seto byte ptr V_FLAG\
508 
-   }
509 
-  #define ADD_RD_RS_O3_0 \
510 
-   {\
511 
-     __asm mov eax, source\
512 
-     __asm mov ebx, dword ptr [OFFSET reg+4*eax]\
513 
-     __asm add ebx, 0\
514 
-     __asm mov eax, dest\
515 
-     __asm mov dword ptr [OFFSET reg+4*eax], ebx\
516 
-     __asm sets byte ptr N_FLAG\
517 
-     __asm setz byte ptr Z_FLAG\
518 
-     __asm mov byte ptr C_FLAG, 0\
519 
-     __asm mov byte ptr V_FLAG, 0\
520 
-   }
521 
-  #define ADD_RN_O8(d) \
522 
-   {\
523 
-     __asm mov ebx, opcode\
524 
-     __asm and ebx, 255\
525 
-     __asm add dword ptr [OFFSET reg+4*(d)], ebx\
526 
-     __asm sets byte ptr N_FLAG\
527 
-     __asm setz byte ptr Z_FLAG\
528 
-     __asm setc byte ptr C_FLAG\
529 
-     __asm seto byte ptr V_FLAG\
530 
-   }
531 
-  #define CMN_RD_RS \
532 
-     {\
533 
-       __asm mov eax, dest\
534 
-       __asm mov ebx, dword ptr [OFFSET reg+4*eax]\
535 
-       __asm add ebx, value\
536 
-       __asm sets byte ptr N_FLAG\
537 
-       __asm setz byte ptr Z_FLAG\
538 
-       __asm setc byte ptr C_FLAG\
539 
-       __asm seto byte ptr V_FLAG\
540 
-     }
541 
-  #define ADC_RD_RS \
542 
-     {\
543 
-       __asm mov ebx, dest\
544 
-       __asm mov ebx, dword ptr [OFFSET reg+4*ebx]\
545 
-       __asm bt word ptr C_FLAG, 0\
546 
-       __asm adc ebx, value\
547 
-       __asm mov eax, dest\
548 
-       __asm mov dword ptr [OFFSET reg+4*eax], ebx\
549 
-       __asm sets byte ptr N_FLAG\
550 
-       __asm setz byte ptr Z_FLAG\
551 
-       __asm setc byte ptr C_FLAG\
552 
-       __asm seto byte ptr V_FLAG\
553 
-     }
554 
-  #define SUB_RD_RS_RN(N) \
555 
-   {\
556 
-     __asm mov eax, source\
557 
-     __asm mov ebx, dword ptr [OFFSET reg+4*eax]\
558 
-     __asm sub ebx, dword ptr [OFFSET reg+4*N]\
559 
-     __asm mov eax, dest\
560 
-     __asm mov dword ptr [OFFSET reg+4*eax], ebx\
561 
-     __asm sets byte ptr N_FLAG\
562 
-     __asm setz byte ptr Z_FLAG\
563 
-     __asm setnc byte ptr C_FLAG\
564 
-     __asm seto byte ptr V_FLAG\
565 
-   }
566 
-  #define SUB_RD_RS_O3(N) \
567 
-   {\
568 
-     __asm mov eax, source\
569 
-     __asm mov ebx, dword ptr [OFFSET reg+4*eax]\
570 
-     __asm sub ebx, N\
571 
-     __asm mov eax, dest\
572 
-     __asm mov dword ptr [OFFSET reg+4*eax], ebx\
573 
-     __asm sets byte ptr N_FLAG\
574 
-     __asm setz byte ptr Z_FLAG\
575 
-     __asm setnc byte ptr C_FLAG\
576 
-     __asm seto byte ptr V_FLAG\
577 
-   }
578 
-  #define SUB_RD_RS_O3_0 \
579 
-   {\
580 
-     __asm mov eax, source\
581 
-     __asm mov ebx, dword ptr [OFFSET reg+4*eax]\
582 
-     __asm sub ebx, 0\
583 
-     __asm mov eax, dest\
584 
-     __asm mov dword ptr [OFFSET reg+4*eax], ebx\
585 
-     __asm sets byte ptr N_FLAG\
586 
-     __asm setz byte ptr Z_FLAG\
587 
-     __asm mov byte ptr C_FLAG, 1\
588 
-     __asm mov byte ptr V_FLAG, 0\
589 
-   }
590 
-  #define SUB_RN_O8(d) \
591 
-   {\
592 
-     __asm mov ebx, opcode\
593 
-     __asm and ebx, 255\
594 
-     __asm sub dword ptr [OFFSET reg + 4*(d)], ebx\
595 
-     __asm sets byte ptr N_FLAG\
596 
-     __asm setz byte ptr Z_FLAG\
597 
-     __asm setnc byte ptr C_FLAG\
598 
-     __asm seto byte ptr V_FLAG\
599 
-   }
600 
-  #define MOV_RN_O8(d) \
601 
-   {\
602 
-     __asm mov eax, opcode\
603 
-     __asm and eax, 255\
604 
-     __asm mov dword ptr [OFFSET reg+4*(d)], eax\
605 
-     __asm sets byte ptr N_FLAG\
606 
-     __asm setz byte ptr Z_FLAG\
607 
-   }
608 
-  #define CMP_RN_O8(d) \
609 
-   {\
610 
-     __asm mov eax, dword ptr [OFFSET reg+4*(d)]\
611 
-     __asm mov ebx, opcode\
612 
-     __asm and ebx, 255\
613 
-     __asm sub eax, ebx\
614 
-     __asm sets byte ptr N_FLAG\
615 
-     __asm setz byte ptr Z_FLAG\
616 
-     __asm setnc byte ptr C_FLAG\
617 
-     __asm seto byte ptr V_FLAG\
618 
-   }
619 
-  #define SBC_RD_RS \
620 
-     {\
621 
-       __asm mov ebx, dest\
622 
-       __asm mov ebx, dword ptr [OFFSET reg + 4*ebx]\
623 
-       __asm mov eax, value\
624 
-       __asm bt word ptr C_FLAG, 0\
625 
-       __asm cmc\
626 
-       __asm sbb ebx, eax\
627 
-       __asm mov eax, dest\
628 
-       __asm mov dword ptr [OFFSET reg + 4*eax], ebx\
629 
-       __asm sets byte ptr N_FLAG\
630 
-       __asm setz byte ptr Z_FLAG\
631 
-       __asm setnc byte ptr C_FLAG\
632 
-       __asm seto byte ptr V_FLAG\
633 
-     }
634 
-  #define LSL_RD_RM_I5 \
635 
-     {\
636 
-       __asm mov eax, source\
637 
-       __asm mov eax, dword ptr [OFFSET reg + 4 * eax]\
638 
-       __asm mov cl, byte ptr shift\
639 
-       __asm shl eax, cl\
640 
-       __asm mov value, eax\
641 
-       __asm setc byte ptr C_FLAG\
642 
-     }
643 
-  #define LSL_RD_RS \
644 
-         {\
645 
-           __asm mov eax, dest\
646 
-           __asm mov eax, dword ptr [OFFSET reg + 4 * eax]\
647 
-           __asm mov cl, byte ptr value\
648 
-           __asm shl eax, cl\
649 
-           __asm mov value, eax\
650 
-           __asm setc byte ptr C_FLAG\
651 
-         }
652 
-  #define LSR_RD_RM_I5 \
653 
-     {\
654 
-       __asm mov eax, source\
655 
-       __asm mov eax, dword ptr [OFFSET reg + 4 * eax]\
656 
-       __asm mov cl, byte ptr shift\
657 
-       __asm shr eax, cl\
658 
-       __asm mov value, eax\
659 
-       __asm setc byte ptr C_FLAG\
660 
-     }
661 
-  #define LSR_RD_RS \
662 
-         {\
663 
-           __asm mov eax, dest\
664 
-           __asm mov eax, dword ptr [OFFSET reg + 4 * eax]\
665 
-           __asm mov cl, byte ptr value\
666 
-           __asm shr eax, cl\
667 
-           __asm mov value, eax\
668 
-           __asm setc byte ptr C_FLAG\
669 
-         }
670 
-  #define ASR_RD_RM_I5 \
671 
-     {\
672 
-       __asm mov eax, source\
673 
-       __asm mov eax, dword ptr [OFFSET reg + 4*eax]\
674 
-       __asm mov cl, byte ptr shift\
675 
-       __asm sar eax, cl\
676 
-       __asm mov value, eax\
677 
-       __asm setc byte ptr C_FLAG\
678 
-     }
679 
-  #define ASR_RD_RS \
680 
-         {\
681 
-           __asm mov eax, dest\
682 
-           __asm mov eax, dword ptr [OFFSET reg + 4*eax]\
683 
-           __asm mov cl, byte ptr value\
684 
-           __asm sar eax, cl\
685 
-           __asm mov value, eax\
686 
-           __asm setc byte ptr C_FLAG\
687 
-         }
688 
-  #define ROR_RD_RS \
689 
-         {\
690 
-           __asm mov eax, dest\
691 
-           __asm mov eax, dword ptr [OFFSET reg + 4*eax]\
692 
-           __asm mov cl, byte ptr value\
693 
-           __asm ror eax, cl\
694 
-           __asm mov value, eax\
695 
-           __asm setc byte ptr C_FLAG\
696 
-         }
697 
-  #define NEG_RD_RS \
698 
-     {\
699 
-       __asm mov ebx, source\
700 
-       __asm mov ebx, dword ptr [OFFSET reg+4*ebx]\
701 
-       __asm neg ebx\
702 
-       __asm mov eax, dest\
703 
-       __asm mov dword ptr [OFFSET reg+4*eax],ebx\
704 
-       __asm sets byte ptr N_FLAG\
705 
-       __asm setz byte ptr Z_FLAG\
706 
-       __asm setnc byte ptr C_FLAG\
707 
-       __asm seto byte ptr V_FLAG\
708 
-     }
709 
-  #define CMP_RD_RS \
710 
-     {\
711 
-       __asm mov eax, dest\
712 
-       __asm mov ebx, dword ptr [OFFSET reg+4*eax]\
713 
-       __asm sub ebx, value\
714 
-       __asm sets byte ptr N_FLAG\
715 
-       __asm setz byte ptr Z_FLAG\
716 
-       __asm setnc byte ptr C_FLAG\
717 
-       __asm seto byte ptr V_FLAG\
718 
-     }
719 
-#endif
27 
+# ifdef __GNUC__
28 
+#  ifdef __POWERPC__
29 
+#   define ADD_RD_RS_RN(N) \
30 
+{ \
31 
+	register int Flags; \
32 
+	register int Result; \
33 
+	asm volatile("addco. %0, %2, %3\n" \
34 
+		"mcrxr cr1\n" \
35 
+		"mfcr %1\n" \
36 
+		: "=r" (Result), \
37 
+		"=r" (Flags) \
38 
+		: "r" (reg[source].I), \
39 
+		"r" (reg[N].I) \
40 
+		); \
41 
+	reg[dest].I = Result; \
42 
+	Z_FLAG = (Flags >> 29) & 1; \
43 
+	N_FLAG = (Flags >> 31) & 1; \
44 
+	C_FLAG = (Flags >> 25) & 1; \
45 
+	V_FLAG = (Flags >> 26) & 1; \
46 
+}
47 
+#   define ADD_RD_RS_O3(N) \
48 
+{ \
49 
+	register int Flags; \
50 
+	register int Result; \
51 
+	asm volatile("addco. %0, %2, %3\n" \
52 
+		"mcrxr cr1\n" \
53 
+		"mfcr %1\n" \
54 
+		: "=r" (Result), \
55 
+		"=r" (Flags) \
56 
+		: "r" (reg[source].I), \
57 
+		"r" (N) \
58 
+		); \
59 
+	reg[dest].I = Result; \
60 
+	Z_FLAG = (Flags >> 29) & 1; \
61 
+	N_FLAG = (Flags >> 31) & 1; \
62 
+	C_FLAG = (Flags >> 25) & 1; \
63 
+	V_FLAG = (Flags >> 26) & 1; \
64 
+}
65 
+#   define ADD_RD_RS_O3_0 ADD_RD_RS_O3
66 
+#   define ADD_RN_O8(d) \
67 
+{ \
68 
+	register int Flags; \
69 
+	register int Result; \
70 
+	asm volatile("addco. %0, %2, %3\n" \
71 
+		"mcrxr cr1\n" \
72 
+		"mfcr %1\n" \
73 
+		: "=r" (Result), \
74 
+		"=r" (Flags) \
75 
+		: "r" (reg[(d)].I), \
76 
+		"r" (opcode & 255) \
77 
+		); \
78 
+	reg[(d)].I = Result; \
79 
+	Z_FLAG = (Flags >> 29) & 1; \
80 
+	N_FLAG = (Flags >> 31) & 1; \
81 
+	C_FLAG = (Flags >> 25) & 1; \
82 
+	V_FLAG = (Flags >> 26) & 1; \
83 
+}
84 
+#   define CMN_RD_RS \
85 
+{\
86 
+	register int Flags; \
87 
+	register int Result; \
88 
+	asm volatile("addco. %0, %2, %3\n" \
89 
+		"mcrxr cr1\n" \
90 
+		"mfcr %1\n" \
91 
+		: "=r" (Result), \
92 
+		"=r" (Flags) \
93 
+		: "r" (reg[dest].I), \
94 
+		"r" (value) \
95 
+		); \
96 
+	Z_FLAG = (Flags >> 29) & 1; \
97 
+	N_FLAG = (Flags >> 31) & 1; \
98 
+	C_FLAG = (Flags >> 25) & 1; \
99 
+	V_FLAG = (Flags >> 26) & 1; \
100 
+}
101 
+#   define ADC_RD_RS \
102 
+{ \
103 
+	register int Flags; \
104 
+	register int Result; \
105 
+	asm volatile("mtspr 1, %4\n" \ /* reg 1 is xer */
106 
+		"addeo. %0, %2, %3\n" \
107 
+		"mcrxr cr1\n" \
108 
+		"mfcr	%1\n" \
109 
+		: "=r" (Result), \
110 
+		"=r" (Flags) \
111 
+		: "r" (reg[dest].I), \
112 
+		"r" (value), \
113 
+		"r" (C_FLAG << 29) \
114 
+		); \
115 
+	reg[dest].I = Result; \
116 
+	Z_FLAG = (Flags >> 29) & 1; \
117 
+	N_FLAG = (Flags >> 31) & 1; \
118 
+	C_FLAG = (Flags >> 25) & 1; \
119 
+	V_FLAG = (Flags >> 26) & 1; \
120 
+}
121 
+#   define SUB_RD_RS_RN(N) \
122 
+{ \
123 
+	register int Flags; \
124 
+	register int Result; \
125 
+	asm volatile("subco. %0, %2, %3\n" \
126 
+		"mcrxr cr1\n" \
127 
+		"mfcr %1\n" \
128 
+		: "=r" (Result), \
129 
+		"=r" (Flags) \
130 
+		: "r" (reg[source].I), \
131 
+		"r" (reg[N].I) \
132 
+		); \
133 
+	reg[dest].I = Result; \
134 
+	Z_FLAG = (Flags >> 29) & 1; \
135 
+	N_FLAG = (Flags >> 31) & 1; \
136 
+	C_FLAG = (Flags >> 25) & 1; \
137 
+	V_FLAG = (Flags >> 26) & 1; \
138 
+}
139 
+#   define SUB_RD_RS_O3(N) \
140 
+{ \
141 
+	register int Flags; \
142 
+	register int Result; \
143 
+	asm volatile("subco. %0, %2, %3\n" \
144 
+		"mcrxr cr1\n" \
145 
+		"mfcr %1\n" \
146 
+		: "=r" (Result), \
147 
+		"=r" (Flags) \
148 
+		: "r" (reg[source].I), \
149 
+		"r" (N) \
150 
+		); \
151 
+	reg[dest].I = Result; \
152 
+	Z_FLAG = (Flags >> 29) & 1; \
153 
+	N_FLAG = (Flags >> 31) & 1; \
154 
+	C_FLAG = (Flags >> 25) & 1; \
155 
+	V_FLAG = (Flags >> 26) & 1; \
156 
+}
157 
+#   define SUB_RD_RS_O3_0 SUB_RD_RS_O3
158 
+#   define SUB_RN_O8(d) \
159 
+{ \
160 
+	register int Flags; \
161 
+	register int Result; \
162 
+	asm volatile("subco. %0, %2, %3\n" \
163 
+		"mcrxr cr1\n" \
164 
+		"mfcr %1\n" \
165 
+		: "=r" (Result), \
166 
+		"=r" (Flags) \
167 
+		: "r" (reg[(d)].I), \
168 
+		"r" (opcode & 255) \
169 
+		); \
170 
+	reg[(d)].I = Result; \
171 
+	Z_FLAG = (Flags >> 29) & 1; \
172 
+	N_FLAG = (Flags >> 31) & 1; \
173 
+	C_FLAG = (Flags >> 25) & 1; \
174 
+	V_FLAG = (Flags >> 26) & 1; \
175 
+}
176 
+#   define CMP_RN_O8(d) \
177 
+{ \
178 
+	register int Flags; \
179 
+	register int Result; \
180 
+	asm volatile("subco. %0, %2, %3\n" \
181 
+		"mcrxr cr1\n" \
182 
+		"mfcr %1\n" \
183 
+		: "=r" (Result), \
184 
+		"=r" (Flags) \
185 
+		: "r" (reg[(d)].I), \
186 
+		"r" (opcode & 255) \
187 
+		); \
188 
+	Z_FLAG = (Flags >> 29) & 1; \
189 
+	N_FLAG = (Flags >> 31) & 1; \
190 
+	C_FLAG = (Flags >> 25) & 1; \
191 
+	V_FLAG = (Flags >> 26) & 1; \
192 
+}
193 
+#   define SBC_RD_RS \
194 
+{ \
195 
+	register int Flags; \
196 
+	register int Result; \
197 
+	asm volatile("mtspr 1, %4\n" \ /* reg 1 is xer */
198 
+		"subfeo. %0, %3, %2\n" \
199 
+		"mcrxr cr1\n" \
200 
+		"mfcr %1\n" \
201 
+		: "=r" (Result), \
202 
+		"=r" (Flags) \
203 
+		: "r" (reg[dest].I), \
204 
+		"r" (value), \
205 
+		"r" (C_FLAG << 29) \
206 
+		); \
207 
+	reg[dest].I = Result; \
208 
+	Z_FLAG = (Flags >> 29) & 1; \
209 
+	N_FLAG = (Flags >> 31) & 1; \
210 
+	C_FLAG = (Flags >> 25) & 1; \
211 
+	V_FLAG = (Flags >> 26) & 1; \
212 
+}
213 
+#   define NEG_RD_RS \
214 
+{ \
215 
+	register int Flags; \
216 
+	register int Result; \
217 
+	asm volatile("subfco. %0, %2, %3\n" \
218 
+		"mcrxr cr1\n" \
219 
+		"mfcr %1\n" \
220 
+		: "=r" (Result), \
221 
+		"=r" (Flags) \
222 
+		: "r" (reg[source].I), \
223 
+		"r" (0) \
224 
+	); \
225 
+	reg[dest].I = Result; \
226 
+	Z_FLAG = (Flags >> 29) & 1; \
227 
+	N_FLAG = (Flags >> 31) & 1; \
228 
+	C_FLAG = (Flags >> 25) & 1; \
229 
+	V_FLAG = (Flags >> 26) & 1; \
230 
+}
231 
+#   define CMP_RD_RS \
232 
+{ \
233 
+	register int Flags; \
234 
+	register int Result; \
235 
+	asm volatile("subco. %0, %2, %3\n" \
236 
+		"mcrxr cr1\n" \
237 
+		"mfcr %1\n" \
238 
+		: "=r" (Result), \
239 
+		"=r" (Flags) \
240 
+		: "r" (reg[dest].I), \
241 
+		"r" (value) \
242 
+		); \
243 
+	Z_FLAG = (Flags >> 29) & 1; \
244 
+	N_FLAG = (Flags >> 31) & 1; \
245 
+	C_FLAG = (Flags >> 25) & 1; \
246 
+	V_FLAG = (Flags >> 26) & 1; \
247 
+}
248 
+#  else
249 
+#   define EMIT1(op, arg) #op " " arg "; "
250 
+#   define EMIT2(op, src, dest) #op " " src ", " dest "; "
251 
+#   define KONST(val) "$" #val
252 
+#   define ASMVAR(cvar) ASMVAR2(__USER_LABEL_PREFIX__, cvar)
253 
+#   define ASMVAR2(prefix, cvar) STRING(prefix) cvar
254 
+#   define STRING(x) #x
255 
+#   define VAR(var) ASMVAR(#var)
256 
+#   define REGREF1(index) ASMVAR("reg(" index ")")
257 
+#   define REGREF2(index, scale) ASMVAR("reg(," index "," #scale ")")
258 
+#   define eax "%%eax"
259 
+#   define ecx "%%ecx"
260 
+#   define edx "%%edx"
261 
+#   define ADD_RN_O8(d) \
262 
+	asm("andl $0xFF, %%eax;"\
263 
+		"addl %%eax, %0;" \
264 
+		EMIT1(setsb, VAR(N_FLAG)) \
265 
+		EMIT1(setzb, VAR(Z_FLAG)) \
266 
+		EMIT1(setcb, VAR(C_FLAG)) \
267 
+		EMIT1(setob, VAR(V_FLAG)) \
268 
+		: "=m" (reg[(d)].I));
269 
+#   define CMN_RD_RS \
270 
+	asm("add %0, %1;" \
271 
+		EMIT1(setsb, VAR(N_FLAG)) \
272 
+		EMIT1(setzb, VAR(Z_FLAG)) \
273 
+		EMIT1(setcb, VAR(C_FLAG)) \
274 
+		EMIT1(setob, VAR(V_FLAG)) \
275 
+		: \
276 
+		: "r" (value), "r" (reg[dest].I) : "1");
277 
+#   define ADC_RD_RS \
278 
+	asm(EMIT2(bt, KONST(0), VAR(C_FLAG)) \
279 
+		"adc %1, %%ebx;" \
280 
+		EMIT1(setsb, VAR(N_FLAG)) \
281 
+		EMIT1(setzb, VAR(Z_FLAG)) \
282 
+		EMIT1(setcb, VAR(C_FLAG)) \
283 
+		EMIT1(setob, VAR(V_FLAG)) \
284 
+		: "=b" (reg[dest].I) \
285 
+		: "r" (value), "b" (reg[dest].I));
286 
+#   define SUB_RN_O8(d) \
287 
+	asm("andl $0xFF, %%eax;" \
288 
+		"subl %%eax, %0;" \
289 
+		EMIT1(setsb, VAR(N_FLAG)) \
290 
+		EMIT1(setzb, VAR(Z_FLAG)) \
291 
+		EMIT1(setncb, VAR(C_FLAG)) \
292 
+		EMIT1(setob, VAR(V_FLAG)) \
293 
+		: "=m" (reg[(d)].I));
294 
+#   define MOV_RN_O8(d) \
295 
+	asm("andl $0xFF, %%eax;" \
296 
+		EMIT2(movb, KONST(0), VAR(N_FLAG)) \
297 
+		"movl %%eax, %0;" \
298 
+		EMIT1(setzb, VAR(Z_FLAG)) \
299 
+		: "=m" (reg[(d)].I));
300 
+#   define CMP_RN_O8(d) \
301 
+	asm("andl $0xFF, %%eax;" \
302 
+		"cmpl %%eax, %0;" \
303 
+		EMIT1(setsb, VAR(N_FLAG)) \
304 
+		EMIT1(setzb, VAR(Z_FLAG)) \
305 
+		EMIT1(setncb, VAR(C_FLAG)) \
306 
+		EMIT1(setob, VAR(V_FLAG)) \
307 
+		: \
308 
+		: "m" (reg[(d)].I));
309 
+#   define SBC_RD_RS \
310 
+	asm volatile(EMIT2(bt, KONST(0), VAR(C_FLAG)) \
311 
+		"cmc;" \
312 
+		"sbb %1, %%ebx;" \
313 
+		EMIT1(setsb, VAR(N_FLAG)) \
314 
+		EMIT1(setzb, VAR(Z_FLAG)) \
315 
+		EMIT1(setncb, VAR(C_FLAG)) \
316 
+		EMIT1(setob, VAR(V_FLAG)) \
317 
+		: "=b" (reg[dest].I) \
318 
+		: "r" (value), "b" (reg[dest].I) : "cc", "memory");
319 
+#   define LSL_RD_RS \
320 
+	asm("shl %%cl, %%eax;" \
321 
+		EMIT1(setcb, VAR(C_FLAG)) \
322 
+		: "=a" (value) \
323 
+		: "a" (reg[dest].I), "c" (value));
324 
+#   define LSR_RD_RS \
325 
+	asm("shr %%cl, %%eax;" \
326 
+		EMIT1(setcb, VAR(C_FLAG)) \
327 
+		: "=a" (value) \
328 
+		: "a" (reg[dest].I), "c" (value));
329 
+#   define ASR_RD_RS \
330 
+	asm("sar %%cl, %%eax;" \
331 
+		EMIT1(setcb, VAR(C_FLAG)) \
332 
+		: "=a" (value) \
333 
+		: "a" (reg[dest].I), "c" (value));
334 
+#   define ROR_RD_RS \
335 
+	asm("ror %%cl, %%eax;" \
336 
+		EMIT1(setcb, VAR(C_FLAG)) \
337 
+		: "=a" (value) \
338 
+		: "a" (reg[dest].I), "c" (value));
339 
+#   define NEG_RD_RS \
340 
+	asm("neg %%ebx;" \
341 
+		EMIT1(setsb, VAR(N_FLAG)) \
342 
+		EMIT1(setzb, VAR(Z_FLAG)) \
343 
+		EMIT1(setncb, VAR(C_FLAG)) \
344 
+		EMIT1(setob, VAR(V_FLAG)) \
345 
+		: "=b" (reg[dest].I) \
346 
+		: "b" (reg[source].I));
347 
+#   define CMP_RD_RS \
348 
+	asm("sub %0, %1;" \
349 
+		EMIT1(setsb, VAR(N_FLAG)) \
350 
+		EMIT1(setzb, VAR(Z_FLAG)) \
351 
+		EMIT1(setncb, VAR(C_FLAG)) \
352 
+		EMIT1(setob, VAR(V_FLAG)) \
353 
+		: \
354 
+		: "r" (value), "r" (reg[dest].I) : "1");
355 
+#   define IMM5_INSN(OP,N) \
356 
+	asm("movl %%eax,%%ecx;" \
357 
+		"shrl $1,%%eax;" \
358 
+		"andl $7,%%ecx;" \
359 
+		"andl $0x1C,%%eax;" \
360 
+		EMIT2(movl, REGREF1(eax), edx) \
361 
+		OP \
362 
+		EMIT1(setsb, VAR(N_FLAG)) \
363 
+		EMIT1(setzb, VAR(Z_FLAG)) \
364 
+		EMIT2(movl, edx, REGREF2(ecx,4)) \
365 
+		: : "i" (N))
366 
+#   define IMM5_INSN_0(OP) \
367 
+	asm("movl %%eax,%%ecx;" \
368 
+		"shrl $1,%%eax;" \
369 
+		"andl $7,%%ecx;" \
370 
+		"andl $0x1C,%%eax;" \
371 
+		EMIT2(movl, REGREF1(eax), edx) \
372 
+		OP \
373 
+		EMIT1(setsb, VAR(N_FLAG)) \
374 
+		EMIT1(setzb, VAR(Z_FLAG)) \
375 
+		EMIT2(movl, edx, REGREF2(ecx,4)) \
376 
+		: : )
377 
+#   define IMM5_LSL \
378 
+	"shll %0,%%edx;"\
379 
+	EMIT1(setcb, VAR(C_FLAG))
380 
+#   define IMM5_LSL_0 \
381 
+	"testl %%edx,%%edx;"
382 
+#   define IMM5_LSR \
383 
+	"shrl %0,%%edx;"\
384 
+	EMIT1(setcb, VAR(C_FLAG))
385 
+#   define IMM5_LSR_0 \
386 
+	"testl %%edx,%%edx;"\
387 
+	EMIT1(setsb, VAR(C_FLAG)) \
388 
+	"xorl %%edx,%%edx;"
389 
+#   define IMM5_ASR \
390 
+	"sarl %0,%%edx;"\
391 
+	EMIT1(setcb, VAR(C_FLAG))
392 
+#  define IMM5_ASR_0 \
393 
+	"sarl $31,%%edx;"\
394 
+	EMIT1(setsb, VAR(C_FLAG))
395 
+#   define THREEARG_INSN(OP, N) \
396 
+	asm("movl %%eax,%%edx;" \
397 
+		"shrl $1,%%edx;" \
398 
+		"andl $0x1C,%%edx;" \
399 
+		"andl $7,%%eax;" \
400 
+		EMIT2(movl, REGREF1(edx), ecx) \
401 
+		OP(N) \
402 
+		EMIT1(setsb, VAR(N_FLAG)) \
403 
+		EMIT1(setzb, VAR(Z_FLAG)) \
404 
+		EMIT2(movl, ecx, REGREF2(eax,4)) \
405 
+		: : )
406 
+#   define ADD_RD_RS_RN(N) \
407 
+	EMIT2(add, VAR(reg) "+" #N "*4", ecx) \
408 
+	EMIT1(setcb, VAR(C_FLAG)) \
409 
+	EMIT1(setob, VAR(V_FLAG))
410 
+#   define ADD_RD_RS_O3(N) \
411 
+	"add $" #N ",%%ecx;" \
412 
+	EMIT1(setcb, VAR(C_FLAG)) \
413 
+	EMIT1(setob, VAR(V_FLAG))
414 
+#   define ADD_RD_RS_O3_0(N) \
415 
+	EMIT2(movb, KONST(0), VAR(C_FLAG)) \
416 
+	"add $0,%%ecx;" \
417 
+	EMIT2(movb, KONST(0), VAR(V_FLAG))
418 
+#   define SUB_RD_RS_RN(N) \
419 
+	EMIT2(sub, VAR(reg) "+" #N "*4", ecx) \
420 
+	EMIT1(setncb, VAR(C_FLAG)) \
421 
+	EMIT1(setob, VAR(V_FLAG))
422 
+#   define SUB_RD_RS_O3(N) \
423 
+	"sub $"#N",%%ecx;" \
424 
+	EMIT1(setncb, VAR(C_FLAG)) \
425 
+	EMIT1(setob, VAR(V_FLAG))
426 
+#   define SUB_RD_RS_O3_0(N) \
427 
+	EMIT2(movb, KONST(1), VAR(C_FLAG)) \
428 
+	"sub $0,%%ecx;" \
429 
+	EMIT2(movb, KONST(0), VAR(V_FLAG))
430 
+#  endif
431 
+# else // !__GNUC__
432 
+#  define ADD_RD_RS_RN(N) \
433 
+{ \
434 
+	__asm mov eax, source \
435 
+	__asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
436 
+	__asm add ebx, dword ptr [OFFSET reg + 4 * N] \
437 
+	__asm mov eax, dest \
438 
+	__asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
439 
+	__asm sets byte ptr N_FLAG \
440 
+	__asm setz byte ptr Z_FLAG \
441 
+	__asm setc byte ptr C_FLAG \
442 
+	__asm seto byte ptr V_FLAG \
443 
+}
444 
+#  define ADD_RD_RS_O3(N) \
445 
+{ \
446 
+	__asm mov eax, source \
447 
+	__asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
448 
+	__asm add ebx, N \
449 
+	__asm mov eax, dest \
450 
+	__asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
451 
+	__asm sets byte ptr N_FLAG \
452 
+	__asm setz byte ptr Z_FLAG \
453 
+	__asm setc byte ptr C_FLAG \
454 
+	__asm seto byte ptr V_FLAG \
455 
+}
456 
+#  define ADD_RD_RS_O3_0 \
457 
+{ \
458 
+	__asm mov eax, source \
459 
+	__asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
460 
+	__asm add ebx, 0 \
461 
+	__asm mov eax, dest \
462 
+	__asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
463 
+	__asm sets byte ptr N_FLAG \
464 
+	__asm setz byte ptr Z_FLAG \
465 
+	__asm mov byte ptr C_FLAG, 0 \
466 
+	__asm mov byte ptr V_FLAG, 0 \
467 
+}
468 
+#  define ADD_RN_O8(d) \
469 
+{ \
470 
+	__asm mov ebx, opcode \
471 
+	__asm and ebx, 255 \
472 
+	__asm add dword ptr [OFFSET reg + 4 * (d)], ebx \
473 
+	__asm sets byte ptr N_FLAG \
474 
+	__asm setz byte ptr Z_FLAG \
475 
+	__asm setc byte ptr C_FLAG \
476 
+	__asm seto byte ptr V_FLAG \
477 
+}
478 
+#  define CMN_RD_RS \
479 
+{ \
480 
+	__asm mov eax, dest \
481 
+	__asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
482 
+	__asm add ebx, value \
483 
+	__asm sets byte ptr N_FLAG \
484 
+	__asm setz byte ptr Z_FLAG \
485 
+	__asm setc byte ptr C_FLAG \
486 
+	__asm seto byte ptr V_FLAG \
487 
+}
488 
+#  define ADC_RD_RS \
489 
+{ \
490 
+	__asm mov ebx, dest \
491 
+	__asm mov ebx, dword ptr [OFFSET reg + 4 * ebx] \
492 
+	__asm bt word ptr C_FLAG, 0 \
493 
+	__asm adc ebx, value \
494 
+	__asm mov eax, dest \
495 
+	__asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
496 
+	__asm sets byte ptr N_FLAG \
497 
+	__asm setz byte ptr Z_FLAG \
498 
+	__asm setc byte ptr C_FLAG \
499 
+	__asm seto byte ptr V_FLAG \
500 
+}
501 
+#  define SUB_RD_RS_RN(N) \
502 
+{ \
503 
+	__asm mov eax, source \
504 
+	__asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
505 
+	__asm sub ebx, dword ptr [OFFSET reg + 4 * N] \
506 
+	__asm mov eax, dest \
507 
+	__asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
508 
+	__asm sets byte ptr N_FLAG \
509 
+	__asm setz byte ptr Z_FLAG \
510 
+	__asm setnc byte ptr C_FLAG \
511 
+	__asm seto byte ptr V_FLAG \
512 
+}
513 
+#  define SUB_RD_RS_O3(N) \
514 
+{ \
515 
+	__asm mov eax, source \
516 
+	__asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
517 
+	__asm sub ebx, N \
518 
+	__asm mov eax, dest \
519 
+	__asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
520 
+	__asm sets byte ptr N_FLAG \
521 
+	__asm setz byte ptr Z_FLAG \
522 
+	__asm setnc byte ptr C_FLAG \
523 
+	__asm seto byte ptr V_FLAG \
524 
+}
525 
+#  define SUB_RD_RS_O3_0 \
526 
+{ \
527 
+	__asm mov eax, source \
528 
+	__asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
529 
+	__asm sub ebx, 0 \
530 
+	__asm mov eax, dest \
531 
+	__asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
532 
+	__asm sets byte ptr N_FLAG \
533 
+	__asm setz byte ptr Z_FLAG \
534 
+	__asm mov byte ptr C_FLAG, 1 \
535 
+	__asm mov byte ptr V_FLAG, 0 \
536 
+}
537 
+#  define SUB_RN_O8(d) \
538 
+{ \
539 
+	__asm mov ebx, opcode \
540 
+	__asm and ebx, 255 \
541 
+	__asm sub dword ptr [OFFSET reg + 4 * (d)], ebx \
542 
+	__asm sets byte ptr N_FLAG \
543 
+	__asm setz byte ptr Z_FLAG \
544 
+	__asm setnc byte ptr C_FLAG \
545 
+	__asm seto byte ptr V_FLAG \
546 
+}
547 
+#  define MOV_RN_O8(d) \
548 
+{ \
549 
+	__asm mov eax, opcode \
550 
+	__asm and eax, 255 \
551 
+	__asm mov dword ptr [OFFSET reg + 4 * (d)], eax \
552 
+	__asm sets byte ptr N_FLAG \
553 
+	__asm setz byte ptr Z_FLAG \
554 
+}
555 
+#  define CMP_RN_O8(d) \
556 
+{ \
557 
+	__asm mov eax, dword ptr [OFFSET reg + 4 * (d)] \
558 
+	__asm mov ebx, opcode \
559 
+	__asm and ebx, 255 \
560 
+	__asm sub eax, ebx \
561 
+	__asm sets byte ptr N_FLAG \
562 
+	__asm setz byte ptr Z_FLAG \
563 
+	__asm setnc byte ptr C_FLAG \
564 
+	__asm seto byte ptr V_FLAG \
565 
+}
566 
+#  define SBC_RD_RS \
567 
+{ \
568 
+	__asm mov ebx, dest \
569 
+	__asm mov ebx, dword ptr [OFFSET reg + 4 * ebx] \
570 
+	__asm mov eax, value \
571 
+	__asm bt word ptr C_FLAG, 0 \
572 
+	__asm cmc \
573 
+	__asm sbb ebx, eax \
574 
+	__asm mov eax, dest \
575 
+	__asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
576 
+	__asm sets byte ptr N_FLAG \
577 
+	__asm setz byte ptr Z_FLAG \
578 
+	__asm setnc byte ptr C_FLAG \
579 
+	__asm seto byte ptr V_FLAG \
580 
+}
581 
+#  define LSL_RD_RM_I5 \
582 
+{ \
583 
+	__asm mov eax, source \
584 
+	__asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
585 
+	__asm mov cl, byte ptr shift \
586 
+	__asm shl eax, cl \
587 
+	__asm mov value, eax \
588 
+	__asm setc byte ptr C_FLAG \
589 
+}
590 
+#  define LSL_RD_RS \
591 
+{ \
592 
+	__asm mov eax, dest \
593 
+	__asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
594 
+	__asm mov cl, byte ptr value \
595 
+	__asm shl eax, cl \
596 
+	__asm mov value, eax \
597 
+	__asm setc byte ptr C_FLAG \
598 
+}
599 
+#  define LSR_RD_RM_I5 \
600 
+{ \
601 
+	__asm mov eax, source \
602 
+	__asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
603 
+	__asm mov cl, byte ptr shift \
604 
+	__asm shr eax, cl \
605 
+	__asm mov value, eax \
606 
+	__asm setc byte ptr C_FLAG \
607 
+}
608 
+#  define LSR_RD_RS \
609 
+{ \
610 
+	__asm mov eax, dest \
611 
+	__asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
612 
+	__asm mov cl, byte ptr value \
613 
+	__asm shr eax, cl \
614 
+	__asm mov value, eax \
615 
+	__asm setc byte ptr C_FLAG \
616 
+}
617 
+#  define ASR_RD_RM_I5 \
618 
+{ \
619 
+	__asm mov eax, source \
620 
+	__asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
621 
+	__asm mov cl, byte ptr shift \
622 
+	__asm sar eax, cl \
623 
+	__asm mov value, eax \
624 
+	__asm setc byte ptr C_FLAG \
625 
+}
626 
+#  define ASR_RD_RS \
627 
+{ \
628 
+	__asm mov eax, dest \
629 
+	__asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
630 
+	__asm mov cl, byte ptr value \
631 
+	__asm sar eax, cl \
632 
+	__asm mov value, eax \
633 
+	__asm setc byte ptr C_FLAG \
634 
+}
635 
+#  define ROR_RD_RS \
636 
+{ \
637 
+	__asm mov eax, dest \
638 
+	__asm mov eax, dword ptr [OFFSET reg + 4 * eax] \
639 
+	__asm mov cl, byte ptr value \
640 
+	__asm ror eax, cl \
641 
+	__asm mov value, eax \
642 
+	__asm setc byte ptr C_FLAG \
643 
+}
644 
+#  define NEG_RD_RS \
645 
+{ \
646 
+	__asm mov ebx, source \
647 
+	__asm mov ebx, dword ptr [OFFSET reg + 4 * ebx] \
648 
+	__asm neg ebx \
649 
+	__asm mov eax, dest \
650 
+	__asm mov dword ptr [OFFSET reg + 4 * eax], ebx \
651 
+	__asm sets byte ptr N_FLAG \
652 
+	__asm setz byte ptr Z_FLAG \
653 
+	__asm setnc byte ptr C_FLAG \
654 
+	__asm seto byte ptr V_FLAG \
655 
+}
656 
+#  define CMP_RD_RS \
657 
+{ \
658 
+	__asm mov eax, dest \
659 
+	__asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \
660 
+	__asm sub ebx, value \
661 
+	__asm sets byte ptr N_FLAG \
662 
+	__asm setz byte ptr Z_FLAG \
663 
+	__asm setnc byte ptr C_FLAG \
664 
+	__asm seto byte ptr V_FLAG \
665 
+}
666 
+# endif
720 667 
 #endif
721 668
722 669 
 // C core
723 670 
 #ifndef ADDCARRY
724 
- #define ADDCARRY(a, b, c) \
725 
-  C_FLAG = ((NEG(a) & NEG(b)) |\
726 
-            (NEG(a) & POS(c)) |\
727 
-            (NEG(b) & POS(c))) ? true : false;
671 
+# define ADDCARRY(a, b, c) \
672 
+	C_FLAG = !!((NEG(a) & NEG(b)) | (NEG(a) & POS(c)) | (NEG(b) & POS(c)));
728 673 
 #endif
729 674 
 #ifndef ADDOVERFLOW
730 
- #define ADDOVERFLOW(a, b, c) \
731 
-  V_FLAG = ((NEG(a) & NEG(b) & POS(c)) |\
732 
-            (POS(a) & POS(b) & NEG(c))) ? true : false;
675 
+# define ADDOVERFLOW(a, b, c) \
676 
+	V_FLAG = !!((NEG(a) & NEG(b) & POS(c)) | (POS(a) & POS(b) & NEG(c)));
733 677 
 #endif
734 678 
 #ifndef SUBCARRY
735 
- #define SUBCARRY(a, b, c) \
736 
-  C_FLAG = ((NEG(a) & POS(b)) |\
737 
-            (NEG(a) & POS(c)) |\
738 
-            (POS(b) & POS(c))) ? true : false;
679 
+# define SUBCARRY(a, b, c) \
680 
+	C_FLAG = !!((NEG(a) & POS(b)) | (NEG(a) & POS(c)) | (POS(b) & POS(c)));
739 681 
 #endif
740 682 
 #ifndef SUBOVERFLOW
741 
- #define SUBOVERFLOW(a, b, c)\
742 
-  V_FLAG = ((NEG(a) & POS(b) & POS(c)) |\
743 
-            (POS(a) & NEG(b) & NEG(c))) ? true : false;
683 
+# define SUBOVERFLOW(a, b, c) \
684 
+	V_FLAG = !!((NEG(a) & POS(b) & POS(c)) | (POS(a) & NEG(b) & NEG(c)));
744 685 
 #endif
745 686 
 #ifndef ADD_RD_RS_RN
746 
- #define ADD_RD_RS_RN(N) \
747 
-   {\
748 
-     uint32_t lhs = reg[source].I;\
749 
-     uint32_t rhs = reg[N].I;\
750 
-     uint32_t res = lhs + rhs;\
751 
-     reg[dest].I = res;\
752 
-     Z_FLAG = (res == 0) ? true : false;\
753 
-     N_FLAG = NEG(res) ? true : false;\
754 
-     ADDCARRY(lhs, rhs, res);\
755 
-     ADDOVERFLOW(lhs, rhs, res);\
756 
-   }
687 
+# define ADD_RD_RS_RN(N) \
688 
+{ \
689 
+	uint32_t lhs = reg[source].I; \
690 
+	uint32_t rhs = reg[N].I; \
691 
+	uint32_t res = lhs + rhs; \
692 
+	reg[dest].I = res; \
693 
+	Z_FLAG = !res; \
694 
+	N_FLAG = !!NEG(res); \
695 
+	ADDCARRY(lhs, rhs, res); \
696 
+	ADDOVERFLOW(lhs, rhs, res); \
697 
+}
757 698 
 #endif
758 699 
 #ifndef ADD_RD_RS_O3
759 
- #define ADD_RD_RS_O3(N) \
760 
-   {\
761 
-     uint32_t lhs = reg[source].I;\
762 
-     uint32_t rhs = N;\
763 
-     uint32_t res = lhs + rhs;\
764 
-     reg[dest].I = res;\
765 
-     Z_FLAG = (res == 0) ? true : false;\
766 
-     N_FLAG = NEG(res) ? true : false;\
767 
-     ADDCARRY(lhs, rhs, res);\
768 
-     ADDOVERFLOW(lhs, rhs, res);\
769 
-   }
700 
+# define ADD_RD_RS_O3(N) \
701 
+{ \
702 
+	uint32_t lhs = reg[source].I; \
703 
+	uint32_t rhs = N; \
704 
+	uint32_t res = lhs + rhs; \
705 
+	reg[dest].I = res; \
706 
+	Z_FLAG = !res; \
707 
+	N_FLAG = !!NEG(res); \
708 
+	ADDCARRY(lhs, rhs, res); \
709 
+	ADDOVERFLOW(lhs, rhs, res); \
710 
+}
770 711 
 #endif
771 712 
 #ifndef ADD_RD_RS_O3_0
772 713 
 # define ADD_RD_RS_O3_0 ADD_RD_RS_O3
773 714 
 #endif
774 715 
 #ifndef ADD_RN_O8
775 
- #define ADD_RN_O8(d) \
776 
-   {\
777 
-     uint32_t lhs = reg[(d)].I;\
778 
-     uint32_t rhs = (opcode & 255);\
779 
-     uint32_t res = lhs + rhs;\
780 
-     reg[(d)].I = res;\
781 
-     Z_FLAG = (res == 0) ? true : false;\
782 
-     N_FLAG = NEG(res) ? true : false;\
783 
-     ADDCARRY(lhs, rhs, res);\
784 
-     ADDOVERFLOW(lhs, rhs, res);\
785 
-   }
716 
+# define ADD_RN_O8(d) \
717 
+{ \
718 
+	uint32_t lhs = reg[(d)].I; \
719 
+	uint32_t rhs = opcode & 255; \
720 
+	uint32_t res = lhs + rhs; \
721 
+	reg[(d)].I = res;\
722 
+	Z_FLAG = !res; \
723 
+	N_FLAG = !!NEG(res); \
724 
+	ADDCARRY(lhs, rhs, res); \
725 
+	ADDOVERFLOW(lhs, rhs, res); \
726 
+}
786 727 
 #endif
787 728 
 #ifndef CMN_RD_RS
788 
- #define CMN_RD_RS \
789 
-   {\
790 
-     uint32_t lhs = reg[dest].I;\
791 
-     uint32_t rhs = value;\
792 
-     uint32_t res = lhs + rhs;\
793 
-     Z_FLAG = (res == 0) ? true : false;\
794 
-     N_FLAG = NEG(res) ? true : false;\
795 
-     ADDCARRY(lhs, rhs, res);\
796 
-     ADDOVERFLOW(lhs, rhs, res);\
797 
-   }
729 
+# define CMN_RD_RS \
730 
+{ \
731 
+	uint32_t lhs = reg[dest].I; \
732 
+	uint32_t rhs = value; \
733 
+	uint32_t res = lhs + rhs; \
734 
+	Z_FLAG = !res; \
735 
+	N_FLAG = !!NEG(res); \
736 
+	ADDCARRY(lhs, rhs, res); \
737 
+	ADDOVERFLOW(lhs, rhs, res); \
738 
+}
798 739 
 #endif
799 740 
 #ifndef ADC_RD_RS
800 
- #define ADC_RD_RS \
801 
-   {\
802 
-     uint32_t lhs = reg[dest].I;\
803 
-     uint32_t rhs = value;\
804 
-     uint32_t res = lhs + rhs + (uint32_t)C_FLAG;\
805 
-     reg[dest].I = res;\
806 
-     Z_FLAG = (res == 0) ? true : false;\
807 
-     N_FLAG = NEG(res) ? true : false;\
808 
-     ADDCARRY(lhs, rhs, res);\
809 
-     ADDOVERFLOW(lhs, rhs, res);\
810 
-   }
741 
+# define ADC_RD_RS \
742 
+{ \
743 
+	uint32_t lhs = reg[dest].I; \
744 
+	uint32_t rhs = value; \
745 
+	uint32_t res = lhs + rhs + static_cast<uint32_t>(C_FLAG); \
746 
+	reg[dest].I = res; \
747 
+	Z_FLAG = !res; \
748 
+	N_FLAG = !!NEG(res); \
749 
+	ADDCARRY(lhs, rhs, res); \
750 
+	ADDOVERFLOW(lhs, rhs, res); \
751 
+}
811 752 
 #endif
812 753 
 #ifndef SUB_RD_RS_RN
813 
- #define SUB_RD_RS_RN(N) \
814 
-   {\
815 
-     uint32_t lhs = reg[source].I;\
816 
-     uint32_t rhs = reg[N].I;\
817 
-     uint32_t res = lhs - rhs;\
818 
-     reg[dest].I = res;\
819 
-     Z_FLAG = (res == 0) ? true : false;\
820 
-     N_FLAG = NEG(res) ? true : false;\
821 
-     SUBCARRY(lhs, rhs, res);\
822 
-     SUBOVERFLOW(lhs, rhs, res);\
823 
-   }
754 
+# define SUB_RD_RS_RN(N) \
755 
+{ \
756 
+	uint32_t lhs = reg[source].I; \
757 
+	uint32_t rhs = reg[N].I; \
758 
+	uint32_t res = lhs - rhs; \
759 
+	reg[dest].I = res; \
760 
+	Z_FLAG = !res; \
761 
+	N_FLAG = !!NEG(res); \
762 
+	SUBCARRY(lhs, rhs, res); \
763 
+	SUBOVERFLOW(lhs, rhs, res); \
764 
+}
824 765 
 #endif
825 766 
 #ifndef SUB_RD_RS_O3
826 
- #define SUB_RD_RS_O3(N) \
827 
-   {\
828 
-     uint32_t lhs = reg[source].I;\
829 
-     uint32_t rhs = N;\
830 
-     uint32_t res = lhs - rhs;\
831 
-     reg[dest].I = res;\
832 
-     Z_FLAG = (res == 0) ? true : false;\
833 
-     N_FLAG = NEG(res) ? true : false;\
834 
-     SUBCARRY(lhs, rhs, res);\
835 
-     SUBOVERFLOW(lhs, rhs, res);\
836 
-   }
767 
+# define SUB_RD_RS_O3(N) \
768 
+{ \
769 
+	uint32_t lhs = reg[source].I; \
770 
+	uint32_t rhs = N; \
771 
+	uint32_t res = lhs - rhs; \
772 
+	reg[dest].I = res; \
773 
+	Z_FLAG = !res; \
774 
+	N_FLAG = !!NEG(res); \
775 
+	SUBCARRY(lhs, rhs, res); \
776 
+	SUBOVERFLOW(lhs, rhs, res); \
777 
+}
837 778 
 #endif
838 779 
 #ifndef SUB_RD_RS_O3_0
839 780 
 # define SUB_RD_RS_O3_0 SUB_RD_RS_O3
840 781 
 #endif
841 782 
 #ifndef SUB_RN_O8
842 
- #define SUB_RN_O8(d) \
843 
-   {\
844 
-     uint32_t lhs = reg[(d)].I;\
845 
-     uint32_t rhs = (opcode & 255);\
846 
-     uint32_t res = lhs - rhs;\
847 
-     reg[(d)].I = res;\
848 
-     Z_FLAG = (res == 0) ? true : false;\
849 
-     N_FLAG = NEG(res) ? true : false;\
850 
-     SUBCARRY(lhs, rhs, res);\
851 
-     SUBOVERFLOW(lhs, rhs, res);\
852 
-   }
783 
+# define SUB_RN_O8(d) \
784 
+{ \
785 
+	uint32_t lhs = reg[(d)].I; \
786 
+	uint32_t rhs = opcode & 255; \
787 
+	uint32_t res = lhs - rhs; \
788 
+	reg[(d)].I = res; \
789 
+	Z_FLAG = !res; \
790 
+	N_FLAG = !!NEG(res); \
791 
+	SUBCARRY(lhs, rhs, res); \
792 
+	SUBOVERFLOW(lhs, rhs, res); \
793 
+}
853 794 
 #endif
854 795 
 #ifndef MOV_RN_O8
855 
- #define MOV_RN_O8(d) \
856 
-   {\
857 
-     reg[d].I = opcode & 255;\
858 
-     N_FLAG = false;\
859 
-     Z_FLAG = (reg[d].I ? false : true);\
860 
-   }
796 
+# define MOV_RN_O8(d) \
797 
+{ \
798 
+	reg[d].I = opcode & 255; \
799 
+	N_FLAG = false; \
800 
+	Z_FLAG = !reg[d].I; \
801 
+}
861 802 
 #endif
862 803 
 #ifndef CMP_RN_O8
863 
- #define CMP_RN_O8(d) \
864 
-   {\
865 
-     uint32_t lhs = reg[(d)].I;\
866 
-     uint32_t rhs = (opcode & 255);\
867 
-     uint32_t res = lhs - rhs;\
868 
-     Z_FLAG = (res == 0) ? true : false;\
869 
-     N_FLAG = NEG(res) ? true : false;\
870 
-     SUBCARRY(lhs, rhs, res);\
871 
-     SUBOVERFLOW(lhs, rhs, res);\
872 
-   }
804 
+# define CMP_RN_O8(d) \
805 
+{ \
806 
+	uint32_t lhs = reg[(d)].I; \
807 
+	uint32_t rhs = opcode & 255; \
808 
+	uint32_t res = lhs - rhs; \
809 
+	Z_FLAG = !res; \
810 
+	N_FLAG = !!NEG(res); \
811 
+	SUBCARRY(lhs, rhs, res); \
812 
+	SUBOVERFLOW(lhs, rhs, res); \
813 
+}
873 814 
 #endif
874 815 
 #ifndef SBC_RD_RS
875 
- #define SBC_RD_RS \
876 
-   {\
877 
-     uint32_t lhs = reg[dest].I;\
878 
-     uint32_t rhs = value;\
879 
-     uint32_t res = lhs - rhs - !((uint32_t)C_FLAG);\
880 
-     reg[dest].I = res;\
881 
-     Z_FLAG = (res == 0) ? true : false;\
882 
-     N_FLAG = NEG(res) ? true : false;\
883 
-     SUBCARRY(lhs, rhs, res);\
884 
-     SUBOVERFLOW(lhs, rhs, res);\
885 
-   }
816 
+# define SBC_RD_RS \
817 
+{ \
818 
+	uint32_t lhs = reg[dest].I; \
819 
+	uint32_t rhs = value; \
820 
+	uint32_t res = lhs - rhs - !static_cast<uint32_t>(C_FLAG); \
821 
+	reg[dest].I = res; \
822 
+	Z_FLAG = !res; \
823 
+	N_FLAG = !!NEG(res); \
824 
+	SUBCARRY(lhs, rhs, res); \
825 
+	SUBOVERFLOW(lhs, rhs, res); \
826 
+}
886 827 
 #endif
887 828 
 #ifndef LSL_RD_RM_I5
888 
- #define LSL_RD_RM_I5 \
889 
-   {\
890 
-     C_FLAG = (reg[source].I >> (32 - shift)) & 1 ? true : false;\
891 
-     value = reg[source].I << shift;\
892 
-   }
829 
+# define LSL_RD_RM_I5 \
830 
+{ \
831 
+	C_FLAG = !!((reg[source].I >> (32 - shift)) & 1); \
832 
+	value = reg[source].I << shift; \
833 
+}
893 834 
 #endif
894 835 
 #ifndef LSL_RD_RS
895 
- #define LSL_RD_RS \
896 
-   {\
897 
-     C_FLAG = (reg[dest].I >> (32 - value)) & 1 ? true : false;\
898 
-     value = reg[dest].I << value;\
899 
-   }
836 
+# define LSL_RD_RS \
837 
+{ \
838 
+	C_FLAG = !!((reg[dest].I >> (32 - value)) & 1); \
839 
+	value = reg[dest].I << value; \
840 
+}
900 841 
 #endif
901 842 
 #ifndef LSR_RD_RM_I5
902 
- #define LSR_RD_RM_I5 \
903 
-   {\
904 
-     C_FLAG = (reg[source].I >> (shift - 1)) & 1 ? true : false;\
905 
-     value = reg[source].I >> shift;\
906 
-   }
843 
+# define LSR_RD_RM_I5 \
844 
+{ \
845 
+	C_FLAG = !!((reg[source].I >> (shift - 1)) & 1); \
846 
+	value = reg[source].I >> shift; \
847 
+}
907 848 
 #endif
908 849 
 #ifndef LSR_RD_RS
909 
- #define LSR_RD_RS \
910 
-   {\
911 
-     C_FLAG = (reg[dest].I >> (value - 1)) & 1 ? true : false;\
912 
-     value = reg[dest].I >> value;\
913 
-   }
850 
+# define LSR_RD_RS \
851 
+{ \
852 
+	C_FLAG = !!((reg[dest].I >> (value - 1)) & 1); \
853 
+	value = reg[dest].I >> value; \
854 
+}
914 855 
 #endif
915 856 
 #ifndef ASR_RD_RM_I5
916 
- #define ASR_RD_RM_I5 \
917 
-   {\
918 
-     C_FLAG = ((int32_t)reg[source].I >> (int)(shift - 1)) & 1 ? true : false;\
919 
-     value = (int32_t)reg[source].I >> (int)shift;\
920 
-   }
857 
+# define ASR_RD_RM_I5 \
858 
+{ \
859 
+	C_FLAG = !!((static_cast<int32_t>(reg[source].I) >> static_cast<int>(shift - 1)) & 1); \
860 
+	value = static_cast<int32_t>(reg[source].I) >> static_cast<int>(shift); \
861 
+}
921 862 
 #endif
922 863 
 #ifndef ASR_RD_RS
923 
- #define ASR_RD_RS \
924 
-   {\
925 
-     C_FLAG = ((int32_t)reg[dest].I >> (int)(value - 1)) & 1 ? true : false;\
926 
-     value = (int32_t)reg[dest].I >> (int)value;\
927 
-   }
864 
+# define ASR_RD_RS \
865 
+{ \
866 
+	C_FLAG = !!((static_cast<int32_t>(reg[dest].I >> static_cast<int>(value - 1)) & 1); \
867 
+	value = static_cast<int32_t>(reg[dest].I) >> static_cast<int>(value); \
868 
+}
928 869 
 #endif
929 870 
 #ifndef ROR_RD_RS
930 
- #define ROR_RD_RS \
931 
-   {\
932 
-     C_FLAG = (reg[dest].I >> (value - 1)) & 1 ? true : false;\
933 
-     value = ((reg[dest].I << (32 - value)) |\
934 
-              (reg[dest].I >> value));\
935 
-   }
871 
+# define ROR_RD_RS \
872 
+{ \
873 
+	C_FLAG = !!((reg[dest].I >> (value - 1)) & 1); \
874 
+	value = (reg[dest].I << (32 - value)) | (reg[dest].I >> value); \
875 
+}
936 876 
 #endif
937 877 
 #ifndef NEG_RD_RS
938 
- #define NEG_RD_RS \
939 
-   {\
940 
-     uint32_t lhs = reg[source].I;\
941 
-     uint32_t rhs = 0;\
942 
-     uint32_t res = rhs - lhs;\
943 
-     reg[dest].I = res;\
944 
-     Z_FLAG = (res == 0) ? true : false;\
945 
-     N_FLAG = NEG(res) ? true : false;\
946 
-     SUBCARRY(rhs, lhs, res);\
947 
-     SUBOVERFLOW(rhs, lhs, res);\
948 
-   }
878 
+# define NEG_RD_RS \
879 
+{ \
880 
+	uint32_t lhs = reg[source].I; \
881 
+	uint32_t rhs = 0; \
882 
+	uint32_t res = rhs - lhs; \
883 
+	reg[dest].I = res; \
884 
+	Z_FLAG = !res; \
885 
+	N_FLAG = !!NEG(res); \
886 
+	SUBCARRY(rhs, lhs, res); \
887 
+	SUBOVERFLOW(rhs, lhs, res); \
888 
+}
949 889 
 #endif
950 890 
 #ifndef CMP_RD_RS
951 
- #define CMP_RD_RS \
952 
-   {\
953 
-     uint32_t lhs = reg[dest].I;\
954 
-     uint32_t rhs = value;\
955 
-     uint32_t res = lhs - rhs;\
956 
-     Z_FLAG = (res == 0) ? true : false;\
957 
-     N_FLAG = NEG(res) ? true : false;\
958 
-     SUBCARRY(lhs, rhs, res);\
959 
-     SUBOVERFLOW(lhs, rhs, res);\
960 
-   }
891 
+# define CMP_RD_RS \
892 
+{ \
893 
+	uint32_t lhs = reg[dest].I; \
894 
+	uint32_t rhs = value; \
895 
+	uint32_t res = lhs - rhs; \
896 
+	Z_FLAG = !res; \
897 
+	N_FLAG = !!NEG(res); \
898 
+	SUBCARRY(lhs, rhs, res); \
899 
+	SUBOVERFLOW(lhs, rhs, res); \
900 
+}
961 901 
 #endif
962 902 
 #ifndef IMM5_INSN
963 
- #define IMM5_INSN(OP,N) \
964 
-  int dest = opcode & 0x07;\
965 
-  int source = (opcode >> 3) & 0x07;\
966 
-  uint32_t value;\
967 
-  OP(N);\
968 
-  reg[dest].I = value;\
969 
-  N_FLAG = (value & 0x80000000 ? true : false);\
970 
-  Z_FLAG = (value ? false : true);
971 
- #define IMM5_INSN_0(OP) \
972 
-  int dest = opcode & 0x07;\
973 
-  int source = (opcode >> 3) & 0x07;\
974 
-  uint32_t value;\
975 
-  OP;\
976 
-  reg[dest].I = value;\
977 
-  N_FLAG = (value & 0x80000000 ? true : false);\
978 
-  Z_FLAG = (value ? false : true);
979 
- #define IMM5_LSL(N) \
980 
-  int shift = N;\
981 
-  LSL_RD_RM_I5;
982 
- #define IMM5_LSL_0 \
983 
-  value = reg[source].I;
984 
- #define IMM5_LSR(N) \
985 
-  int shift = N;\
986 
-  LSR_RD_RM_I5;
987 
- #define IMM5_LSR_0 \
988 
-  C_FLAG = reg[source].I & 0x80000000 ? true : false;\
989 
-  value = 0;
990 
- #define IMM5_ASR(N) \
991 
-  int shift = N;\
992 
-  ASR_RD_RM_I5;
993 
- #define IMM5_ASR_0 \
994 
-  if(reg[source].I & 0x80000000) {\
995 
-    value = 0xFFFFFFFF;\
996 
-    C_FLAG = true;\
997 
-  } else {\
998 
-    value = 0;\
999 
-    C_FLAG = false;\
1000 
-  }
903 
+# define IMM5_INSN(OP, N) \
904 
+	int dest = opcode & 0x07; \
905 
+	int source = (opcode >> 3) & 0x07; \
906 
+	uint32_t value; \
907 
+	OP(N); \
908 
+	reg[dest].I = value; \
909 
+	N_FLAG = !!(value & 0x80000000); \
910 
+	Z_FLAG = !value;
911 
+# define IMM5_INSN_0(OP) \
912 
+	int dest = opcode & 0x07; \
913 
+	int source = (opcode >> 3) & 0x07; \
914 
+	uint32_t value; \
915 
+	OP; \
916 
+	reg[dest].I = value; \
917 
+	N_FLAG = !!(value & 0x80000000); \
918 
+	Z_FLAG = !value;
919 
+# define IMM5_LSL(N) \
920 
+	int shift = N; \
921 
+	LSL_RD_RM_I5;
922 
+# define IMM5_LSL_0 \
923 
+	value = reg[source].I;
924 
+# define IMM5_LSR(N) \
925 
+	int shift = N; \
926 
+	LSR_RD_RM_I5;
927 
+# define IMM5_LSR_0 \
928 
+	C_FLAG = !!(reg[source].I & 0x80000000); \
929 
+	value = 0;
930 
+# define IMM5_ASR(N) \
931 
+	int shift = N; \
932 
+	ASR_RD_RM_I5;
933 
+# define IMM5_ASR_0 \
934 
+	if (reg[source].I & 0x80000000) \
935 
+	{ \
936 
+		value = 0xFFFFFFFF; \
937 
+		C_FLAG = true; \
938 
+	} \
939 
+	else \
940 
+	{ \
941 
+		value = 0; \
942 
+		C_FLAG = false; \
943 
+	}
1001 944 
 #endif
1002 945 
 #ifndef THREEARG_INSN
1003 
- #define THREEARG_INSN(OP,N) \
1004 
-  int dest = opcode & 0x07;          \
1005 
-  int source = (opcode >> 3) & 0x07; \
1006 
-  OP(N);
946 
+# define THREEARG_INSN(OP, N) \
947 
+	int dest = opcode & 0x07; \
948 
+	int source = (opcode >> 3) & 0x07; \
949 
+	OP(N);
1007 950 
 #endif
1008 951
1009 952 
 // Shift instructions /////////////////////////////////////////////////////
1010 953
1011 
-#define DEFINE_IMM5_INSN(OP,BASE) \
1012 
-  static INSN_REGPARM void thumb##BASE##_00(uint32_t opcode) { IMM5_INSN_0(OP##_0); } \
1013 
-  static INSN_REGPARM void thumb##BASE##_01(uint32_t opcode) { IMM5_INSN(OP, 1); } \
1014 
-  static INSN_REGPARM void thumb##BASE##_02(uint32_t opcode) { IMM5_INSN(OP, 2); } \
1015 
-  static INSN_REGPARM void thumb##BASE##_03(uint32_t opcode) { IMM5_INSN(OP, 3); } \
1016 
-  static INSN_REGPARM void thumb##BASE##_04(uint32_t opcode) { IMM5_INSN(OP, 4); } \
1017 
-  static INSN_REGPARM void thumb##BASE##_05(uint32_t opcode) { IMM5_INSN(OP, 5); } \
1018 
-  static INSN_REGPARM void thumb##BASE##_06(uint32_t opcode) { IMM5_INSN(OP, 6); } \
1019 
-  static INSN_REGPARM void thumb##BASE##_07(uint32_t opcode) { IMM5_INSN(OP, 7); } \
1020 
-  static INSN_REGPARM void thumb##BASE##_08(uint32_t opcode) { IMM5_INSN(OP, 8); } \
1021 
-  static INSN_REGPARM void thumb##BASE##_09(uint32_t opcode) { IMM5_INSN(OP, 9); } \
1022 
-  static INSN_REGPARM void thumb##BASE##_0A(uint32_t opcode) { IMM5_INSN(OP,10); } \
1023 
-  static INSN_REGPARM void thumb##BASE##_0B(uint32_t opcode) { IMM5_INSN(OP,11); } \
1024 
-  static INSN_REGPARM void thumb##BASE##_0C(uint32_t opcode) { IMM5_INSN(OP,12); } \
1025 
-  static INSN_REGPARM void thumb##BASE##_0D(uint32_t opcode) { IMM5_INSN(OP,13); } \
1026 
-  static INSN_REGPARM void thumb##BASE##_0E(uint32_t opcode) { IMM5_INSN(OP,14); } \
1027 
-  static INSN_REGPARM void thumb##BASE##_0F(uint32_t opcode) { IMM5_INSN(OP,15); } \
1028 
-  static INSN_REGPARM void thumb##BASE##_10(uint32_t opcode) { IMM5_INSN(OP,16); } \
1029 
-  static INSN_REGPARM void thumb##BASE##_11(uint32_t opcode) { IMM5_INSN(OP,17); } \
1030 
-  static INSN_REGPARM void thumb##BASE##_12(uint32_t opcode) { IMM5_INSN(OP,18); } \
1031 
-  static INSN_REGPARM void thumb##BASE##_13(uint32_t opcode) { IMM5_INSN(OP,19); } \
1032 
-  static INSN_REGPARM void thumb##BASE##_14(uint32_t opcode) { IMM5_INSN(OP,20); } \
1033 
-  static INSN_REGPARM void thumb##BASE##_15(uint32_t opcode) { IMM5_INSN(OP,21); } \
1034 
-  static INSN_REGPARM void thumb##BASE##_16(uint32_t opcode) { IMM5_INSN(OP,22); } \
1035 
-  static INSN_REGPARM void thumb##BASE##_17(uint32_t opcode) { IMM5_INSN(OP,23); } \
1036 
-  static INSN_REGPARM void thumb##BASE##_18(uint32_t opcode) { IMM5_INSN(OP,24); } \
1037 
-  static INSN_REGPARM void thumb##BASE##_19(uint32_t opcode) { IMM5_INSN(OP,25); } \
1038 
-  static INSN_REGPARM void thumb##BASE##_1A(uint32_t opcode) { IMM5_INSN(OP,26); } \
1039 
-  static INSN_REGPARM void thumb##BASE##_1B(uint32_t opcode) { IMM5_INSN(OP,27); } \
1040 
-  static INSN_REGPARM void thumb##BASE##_1C(uint32_t opcode) { IMM5_INSN(OP,28); } \
1041 
-  static INSN_REGPARM void thumb##BASE##_1D(uint32_t opcode) { IMM5_INSN(OP,29); } \
1042 
-  static INSN_REGPARM void thumb##BASE##_1E(uint32_t opcode) { IMM5_INSN(OP,30); } \
1043 
-  static INSN_REGPARM void thumb##BASE##_1F(uint32_t opcode) { IMM5_INSN(OP,31); }
954 
+#define DEFINE_IMM5_INSN(OP, BASE) \
955 
+	static INSN_REGPARM void thumb##BASE##_00(uint32_t opcode) { IMM5_INSN_0(OP##_0); } \
956 
+	static INSN_REGPARM void thumb##BASE##_01(uint32_t opcode) { IMM5_INSN(OP, 1); } \
957 
+	static INSN_REGPARM void thumb##BASE##_02(uint32_t opcode) { IMM5_INSN(OP, 2); } \
958 
+	static INSN_REGPARM void thumb##BASE##_03(uint32_t opcode) { IMM5_INSN(OP, 3); } \
959 
+	static INSN_REGPARM void thumb##BASE##_04(uint32_t opcode) { IMM5_INSN(OP, 4); } \
960 
+	static INSN_REGPARM void thumb##BASE##_05(uint32_t opcode) { IMM5_INSN(OP, 5); } \
961 
+	static INSN_REGPARM void thumb##BASE##_06(uint32_t opcode) { IMM5_INSN(OP, 6); } \
962 
+	static INSN_REGPARM void thumb##BASE##_07(uint32_t opcode) { IMM5_INSN(OP, 7); } \
963 
+	static INSN_REGPARM void thumb##BASE##_08(uint32_t opcode) { IMM5_INSN(OP, 8); } \
964 
+	static INSN_REGPARM void thumb##BASE##_09(uint32_t opcode) { IMM5_INSN(OP, 9); } \
965 
+	static INSN_REGPARM void thumb##BASE##_0A(uint32_t opcode) { IMM5_INSN(OP, 10); } \
966 
+	static INSN_REGPARM void thumb##BASE##_0B(uint32_t opcode) { IMM5_INSN(OP, 11); } \
967 
+	static INSN_REGPARM void thumb##BASE##_0C(uint32_t opcode) { IMM5_INSN(OP, 12); } \
968 
+	static INSN_REGPARM void thumb##BASE##_0D(uint32_t opcode) { IMM5_INSN(OP, 13); } \
969 
+	static INSN_REGPARM void thumb##BASE##_0E(uint32_t opcode) { IMM5_INSN(OP, 14); } \
970 
+	static INSN_REGPARM void thumb##BASE##_0F(uint32_t opcode) { IMM5_INSN(OP, 15); } \
971 
+	static INSN_REGPARM void thumb##BASE##_10(uint32_t opcode) { IMM5_INSN(OP, 16); } \
972 
+	static INSN_REGPARM void thumb##BASE##_11(uint32_t opcode) { IMM5_INSN(OP, 17); } \
973 
+	static INSN_REGPARM void thumb##BASE##_12(uint32_t opcode) { IMM5_INSN(OP, 18); } \
974 
+	static INSN_REGPARM void thumb##BASE##_13(uint32_t opcode) { IMM5_INSN(OP, 19); } \
975 
+	static INSN_REGPARM void thumb##BASE##_14(uint32_t opcode) { IMM5_INSN(OP, 20); } \
976 
+	static INSN_REGPARM void thumb##BASE##_15(uint32_t opcode) { IMM5_INSN(OP, 21); } \
977 
+	static INSN_REGPARM void thumb##BASE##_16(uint32_t opcode) { IMM5_INSN(OP, 22); } \
978 
+	static INSN_REGPARM void thumb##BASE##_17(uint32_t opcode) { IMM5_INSN(OP, 23); } \
979 
+	static INSN_REGPARM void thumb##BASE##_18(uint32_t opcode) { IMM5_INSN(OP, 24); } \
980 
+	static INSN_REGPARM void thumb##BASE##_19(uint32_t opcode) { IMM5_INSN(OP, 25); } \
981 
+	static INSN_REGPARM void thumb##BASE##_1A(uint32_t opcode) { IMM5_INSN(OP, 26); } \
982 
+	static INSN_REGPARM void thumb##BASE##_1B(uint32_t opcode) { IMM5_INSN(OP, 27); } \
983 
+	static INSN_REGPARM void thumb##BASE##_1C(uint32_t opcode) { IMM5_INSN(OP, 28); } \
984 
+	static INSN_REGPARM void thumb##BASE##_1D(uint32_t opcode) { IMM5_INSN(OP, 29); } \
985 
+	static INSN_REGPARM void thumb##BASE##_1E(uint32_t opcode) { IMM5_INSN(OP, 30); } \
986 
+	static INSN_REGPARM void thumb##BASE##_1F(uint32_t opcode) { IMM5_INSN(OP, 31); }
1044 987
1045 988 
 // LSL Rd, Rm, #Imm 5
1046 
-DEFINE_IMM5_INSN(IMM5_LSL,00)
989 
+DEFINE_IMM5_INSN(IMM5_LSL, 00)
1047 990 
 // LSR Rd, Rm, #Imm 5
1048 
-DEFINE_IMM5_INSN(IMM5_LSR,08)
991 
+DEFINE_IMM5_INSN(IMM5_LSR, 08)
1049 992 
 // ASR Rd, Rm, #Imm 5
1050 
-DEFINE_IMM5_INSN(IMM5_ASR,10)
993 
+DEFINE_IMM5_INSN(IMM5_ASR, 10)
1051 994
1052 995 
 // 3-argument ADD/SUB /////////////////////////////////////////////////////
1053 996
1054 
-#define DEFINE_REG3_INSN(OP,BASE) \
1055 
-  static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP,0); } \
1056 
-  static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP,1); } \
1057 
-  static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP,2); } \
1058 
-  static INSN_REGPARM void thumb##BASE##_3(uint32_t opcode) { THREEARG_INSN(OP,3); } \
1059 
-  static INSN_REGPARM void thumb##BASE##_4(uint32_t opcode) { THREEARG_INSN(OP,4); } \
1060 
-  static INSN_REGPARM void thumb##BASE##_5(uint32_t opcode) { THREEARG_INSN(OP,5); } \
1061 
-  static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP,6); } \
1062 
-  static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP,7); }
1063 
-
1064 
-#define DEFINE_IMM3_INSN(OP,BASE) \
1065 
-  static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP##_0,0); } \
1066 
-  static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP,1); } \
1067 
-  static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP,2); } \
1068 
-  static INSN_REGPARM void thumb##BASE##_3(uint32_t opcode) { THREEARG_INSN(OP,3); } \
1069 
-  static INSN_REGPARM void thumb##BASE##_4(uint32_t opcode) { THREEARG_INSN(OP,4); } \
1070 
-  static INSN_REGPARM void thumb##BASE##_5(uint32_t opcode) { THREEARG_INSN(OP,5); } \
1071 
-  static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP,6); } \
1072 
-  static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP,7); }
997 
+#define DEFINE_REG3_INSN(OP, BASE) \
998 
+	static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP, 0); } \
999 
+	static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP, 1); } \
1000 
+	static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP, 2); } \
1001 
+	static INSN_REGPARM void thumb##BASE##_3(uint32_t opcode) { THREEARG_INSN(OP, 3); } \
1002 
+	static INSN_REGPARM void thumb##BASE##_4(uint32_t opcode) { THREEARG_INSN(OP, 4); } \
1003 
+	static INSN_REGPARM void thumb##BASE##_5(uint32_t opcode) { THREEARG_INSN(OP, 5); } \
1004 
+	static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP, 6); } \
1005 
+	static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP, 7); }
1006 
+
1007 
+#define DEFINE_IMM3_INSN(OP, BASE) \
1008 
+	static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP##_0, 0); } \
1009 
+	static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP, 1); } \
1010 
+	static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP, 2); } \
1011 
+	static INSN_REGPARM void thumb##BASE##_3(uint32_t opcode) { THREEARG_INSN(OP, 3); } \
1012 
+	static INSN_REGPARM void thumb##BASE##_4(uint32_t opcode) { THREEARG_INSN(OP, 4); } \
1013 
+	static INSN_REGPARM void thumb##BASE##_5(uint32_t opcode) { THREEARG_INSN(OP, 5); } \
1014 
+	static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP, 6); } \
1015 
+	static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP, 7); }
1073 1016
1074 1017 
 // ADD Rd, Rs, Rn
1075 
-DEFINE_REG3_INSN(ADD_RD_RS_RN,18)
1018 
+DEFINE_REG3_INSN(ADD_RD_RS_RN, 18)
1076 1019 
 // SUB Rd, Rs, Rn
1077 
-DEFINE_REG3_INSN(SUB_RD_RS_RN,1A)
1020 
+DEFINE_REG3_INSN(SUB_RD_RS_RN, 1A)
1078 1021 
 // ADD Rd, Rs, #Offset3
1079 
-DEFINE_IMM3_INSN(ADD_RD_RS_O3,1C)
1022 
+DEFINE_IMM3_INSN(ADD_RD_RS_O3, 1C)
1080 1023 
 // SUB Rd, Rs, #Offset3
1081 
-DEFINE_IMM3_INSN(SUB_RD_RS_O3,1E)
1024 
+DEFINE_IMM3_INSN(SUB_RD_RS_O3, 1E)
1082 1025
1083 1026 
 // MOV/CMP/ADD/SUB immediate //////////////////////////////////////////////
1084 1027
... ... 
@@ -1155,206 +1098,226 @@ static INSN_REGPARM void thumb3F(uint32_t opcode) { SUB_RN_O8(7); }
1155 1098 
 // AND Rd, Rs
1156 1099 
 static INSN_REGPARM void thumb40_0(uint32_t opcode)
1157 1100 
 {
1158 
-  int dest = opcode & 7;
1159 
-  reg[dest].I &= reg[(opcode >> 3)&7].I;
1160 
-  N_FLAG = reg[dest].I & 0x80000000 ? true : false;
1161 
-  Z_FLAG = reg[dest].I ? false : true;
1162 
-  THUMB_CONSOLE_OUTPUT(NULL, reg[2].I);
1101 
+	int dest = opcode & 7;
1102 
+	reg[dest].I &= reg[(opcode >> 3) & 7].I;
1103 
+	N_FLAG = !!(reg[dest].I & 0x80000000);
1104 
+	Z_FLAG = !reg[dest].I;
1163 1105 
 }
1164 1106
1165 1107 
 // EOR Rd, Rs
1166 1108 
 static INSN_REGPARM void thumb40_1(uint32_t opcode)
1167 1109 
 {
1168 
-  int dest = opcode & 7;
1169 
-  reg[dest].I ^= reg[(opcode >> 3)&7].I;
1170 
-  N_FLAG = reg[dest].I & 0x80000000 ? true : false;
1171 
-  Z_FLAG = reg[dest].I ? false : true;
1110 
+	int dest = opcode & 7;
1111 
+	reg[dest].I ^= reg[(opcode >> 3) & 7].I;
1112 
+	N_FLAG = !!(reg[dest].I & 0x80000000);
1113 
+	Z_FLAG = !reg[dest].I;
1172 1114 
 }
1173 1115
1174 1116 
 // LSL Rd, Rs
1175 1117 
 static INSN_REGPARM void thumb40_2(uint32_t opcode)
1176 1118 
 {
1177 
-  int dest = opcode & 7;
1178 
-  uint32_t value = reg[(opcode >> 3)&7].B.B0;
1179 
-  if(value) {
1180 
-    if(value == 32) {
1181 
-      value = 0;
1182 
-      C_FLAG = (reg[dest].I & 1 ? true : false);
1183 
-    } else if(value < 32) {
1184 
-      LSL_RD_RS;
1185 
-    } else {
1186 
-      value = 0;
1187 
-      C_FLAG = false;
1188 
-    }
1189 
-    reg[dest].I = value;
1190 
-  }
1191 
-  N_FLAG = reg[dest].I & 0x80000000 ? true : false;
1192 
-  Z_FLAG = reg[dest].I ? false : true;
1193 
-  clockTicks = codeTicksAccess16(armNextPC)+2;
1119 
+	int dest = opcode & 7;
1120 
+	uint32_t value = reg[(opcode >> 3) & 7].B.B0;
1121 
+	if (value)
1122 
+	{
1123 
+		if (value == 32)
1124 
+		{
1125 
+			value = 0;
1126 
+			C_FLAG = !!(reg[dest].I & 1);
1127 
+		}
1128 
+		else if (value < 32)
1129 
+		{
1130 
+			LSL_RD_RS;
1131 
+		}
1132 
+		else
1133 
+		{
1134 
+			value = 0;
1135 
+			C_FLAG = false;
1136 
+		}
1137 
+		reg[dest].I = value;
1138 
+	}
1139 
+	N_FLAG = !!(reg[dest].I & 0x80000000);
1140 
+	Z_FLAG = !reg[dest].I;
1141 
+	clockTicks = codeTicksAccess16(armNextPC) + 2;
1194 1142 
 }
1195 1143
1196 1144 
 // LSR Rd, Rs
1197 1145 
 static INSN_REGPARM void thumb40_3(uint32_t opcode)
1198 1146 
 {
1199 
-  int dest = opcode & 7;
1200 
-  uint32_t value = reg[(opcode >> 3)&7].B.B0;
1201 
-  if(value) {
1202 
-    if(value == 32) {
1203 
-      value = 0;
1204 
-      C_FLAG = (reg[dest].I & 0x80000000 ? true : false);
1205 
-    } else if(value < 32) {
1206 
-      LSR_RD_RS;
1207 
-    } else {
1208 
-      value = 0;
1209 
-      C_FLAG = false;
1210 
-    }
1211 
-    reg[dest].I = value;
1212 
-  }
1213 
-  N_FLAG = reg[dest].I & 0x80000000 ? true : false;
1214 
-  Z_FLAG = reg[dest].I ? false : true;
1215 
-  clockTicks = codeTicksAccess16(armNextPC)+2;
1147 
+	int dest = opcode & 7;
1148 
+	uint32_t value = reg[(opcode >> 3) & 7].B.B0;
1149 
+	if (value)
1150 
+	{
1151 
+		if (value == 32)
1152 
+		{
1153 
+			value = 0;
1154 
+			C_FLAG = !!(reg[dest].I & 0x80000000);
1155 
+		}
1156 
+		else if (value < 32)
1157 
+		{
1158 
+			LSR_RD_RS;
1159 
+		}
1160 
+		else
1161 
+		{
1162 
+			value = 0;
1163 
+			C_FLAG = false;
1164 
+		}
1165 
+		reg[dest].I = value;
1166 
+	}
1167 
+	N_FLAG = !!(reg[dest].I & 0x80000000);
1168 
+	Z_FLAG = !reg[dest].I;
1169 
+	clockTicks = codeTicksAccess16(armNextPC) + 2;
1216 1170 
 }
1217 1171
1218 1172 
 // ASR Rd, Rs
1219 1173 
 static INSN_REGPARM void thumb41_0(uint32_t opcode)
1220 1174 
 {
1221 
-  int dest = opcode & 7;
1222 
-  uint32_t value = reg[(opcode >> 3)&7].B.B0;
1223 
-  if(value) {
1224 
-    if(value < 32) {
1225 
-      ASR_RD_RS;
1226 
-      reg[dest].I = value;
1227 
-    } else {
1228 
-      if(reg[dest].I & 0x80000000){
1229 
-        reg[dest].I = 0xFFFFFFFF;
1230 
-        C_FLAG = true;
1231 
-      } else {
1232 
-        reg[dest].I = 0x00000000;
1233 
-        C_FLAG = false;
1234 
-      }
1235 
-    }
1236 
-  }
1237 
-  N_FLAG = reg[dest].I & 0x80000000 ? true : false;
1238 
-  Z_FLAG = reg[dest].I ? false : true;
1239 
-  clockTicks = codeTicksAccess16(armNextPC)+2;
1175 
+	int dest = opcode & 7;
1176 
+	uint32_t value = reg[(opcode >> 3) & 7].B.B0;
1177 
+	if (value)
1178 
+	{
1179 
+		if (value < 32)
1180 
+		{
1181 
+			ASR_RD_RS;
1182 
+			reg[dest].I = value;
1183 
+		}
1184 
+		else
1185 
+		{
1186 
+			if (reg[dest].I & 0x80000000)
1187 
+			{
1188 
+				reg[dest].I = 0xFFFFFFFF;
1189 
+				C_FLAG = true;
1190 
+			}
1191 
+			else
1192 
+			{
1193 
+				reg[dest].I = 0x00000000;
1194 
+				C_FLAG = false;
1195 
+			}
1196 
+		}
1197 
+	}
1198 
+	N_FLAG = !!(reg[dest].I & 0x80000000);
1199 
+	Z_FLAG = !reg[dest].I;
1200 
+	clockTicks = codeTicksAccess16(armNextPC) + 2;
1240 1201 
 }
1241 1202
1242 1203 
 // ADC Rd, Rs
1243 1204 
 static INSN_REGPARM void thumb41_1(uint32_t opcode)
1244 1205 
 {
1245 
-  int dest = opcode & 0x07;
1246 
-  uint32_t value = reg[(opcode >> 3)&7].I;
1247 
-  ADC_RD_RS;
1206 
+	int dest = opcode & 0x07;
1207 
+	uint32_t value = reg[(opcode >> 3) & 7].I;
1208 
+	ADC_RD_RS;
1248 1209 
 }
1249 1210
1250 1211 
 // SBC Rd, Rs
1251 1212 
 static INSN_REGPARM void thumb41_2(uint32_t opcode)
1252 1213 
 {
1253 
-  int dest = opcode & 0x07;
1254 
-  uint32_t value = reg[(opcode >> 3)&7].I;
1255 
-  SBC_RD_RS;
1214 
+	int dest = opcode & 0x07;
1215 
+	uint32_t value = reg[(opcode >> 3) & 7].I;
1216 
+	SBC_RD_RS;
1256 1217 
 }
1257 1218
1258 1219 
 // ROR Rd, Rs
1259 1220 
 static INSN_REGPARM void thumb41_3(uint32_t opcode)
1260 1221 
 {
1261 
-  int dest = opcode & 7;
1262 
-  uint32_t value = reg[(opcode >> 3)&7].B.B0;
1263 
-
1264 
-  if(value) {
1265 
-    value = value & 0x1f;
1266 
-    if(value == 0) {
1267 
-      C_FLAG = (reg[dest].I & 0x80000000 ? true : false);
1268 
-    } else {
1269 
-      ROR_RD_RS;
1270 
-      reg[dest].I = value;
1271 
-    }
1272 
-  }
1273 
-  clockTicks = codeTicksAccess16(armNextPC)+2;
1274 
-  N_FLAG = reg[dest].I & 0x80000000 ? true : false;
1275 
-  Z_FLAG = reg[dest].I ? false : true;
1222 
+	int dest = opcode & 7;
1223 
+	uint32_t value = reg[(opcode >> 3) & 7].B.B0;
1224 
+
1225 
+	if (value)
1226 
+	{
1227 
+		value &= 0x1f;
1228 
+		if (!value)
1229 
+			C_FLAG = !!(reg[dest].I & 0x80000000);
1230 
+		else
1231 
+		{
1232 
+			ROR_RD_RS;
1233 
+			reg[dest].I = value;
1234 
+		}
1235 
+	}
1236 
+	clockTicks = codeTicksAccess16(armNextPC) + 2;
1237 
+	N_FLAG = !!(reg[dest].I & 0x80000000);
1238 
+	Z_FLAG = !reg[dest].I;
1276 1239 
 }
1277 1240
1278 1241 
 // TST Rd, Rs
1279 1242 
 static INSN_REGPARM void thumb42_0(uint32_t opcode)
1280 1243 
 {
1281 
-  uint32_t value = reg[opcode & 7].I & reg[(opcode >> 3) & 7].I;
1282 
-  N_FLAG = value & 0x80000000 ? true : false;
1283 
-  Z_FLAG = value ? false : true;
1244 
+	uint32_t value = reg[opcode & 7].I & reg[(opcode >> 3) & 7].I;
1245 
+	N_FLAG = !!(value & 0x80000000);
1246 
+	Z_FLAG = !value;
1284 1247 
 }
1285 1248
1286 1249 
 // NEG Rd, Rs
1287 1250 
 static INSN_REGPARM void thumb42_1(uint32_t opcode)
1288 1251 
 {
1289 
-  int dest = opcode & 7;
1290 
-  int source = (opcode >> 3) & 7;
1291 
-  NEG_RD_RS;
1252 
+	int dest = opcode & 7;
1253 
+	int source = (opcode >> 3) & 7;
1254 
+	NEG_RD_RS;
1292 1255 
 }
1293 1256
1294 1257 
 // CMP Rd, Rs
1295 1258 
 static INSN_REGPARM void thumb42_2(uint32_t opcode)
1296 1259 
 {
1297 
-  int dest = opcode & 7;
1298 
-  uint32_t value = reg[(opcode >> 3)&7].I;
1299 
-  CMP_RD_RS;
1260 
+	int dest = opcode & 7;
1261 
+	uint32_t value = reg[(opcode >> 3) & 7].I;
1262 
+	CMP_RD_RS;
1300 1263 
 }
1301 1264
1302 1265 
 // CMN Rd, Rs
1303 1266 
 static INSN_REGPARM void thumb42_3(uint32_t opcode)
1304 1267 
 {
1305 
-  int dest = opcode & 7;
1306 
-  uint32_t value = reg[(opcode >> 3)&7].I;
1307 
-  CMN_RD_RS;
1268 
+	int dest = opcode & 7;
1269 
+	uint32_t value = reg[(opcode >> 3) & 7].I;
1270 
+	CMN_RD_RS;
1308 1271 
 }
1309 1272
1310 1273 
 // ORR Rd, Rs
1311 1274 
 static INSN_REGPARM void thumb43_0(uint32_t opcode)
1312 1275 
 {
1313 
-  int dest = opcode & 7;
1314 
-  reg[dest].I |= reg[(opcode >> 3) & 7].I;
1315 
-  Z_FLAG = reg[dest].I ? false : true;
1316 
-  N_FLAG = reg[dest].I & 0x80000000 ? true : false;
1276 
+	int dest = opcode & 7;
1277 
+	reg[dest].I |= reg[(opcode >> 3) & 7].I;
1278 
+	Z_FLAG = !reg[dest].I;
1279 
+	N_FLAG = !!(reg[dest].I & 0x80000000);
1317 1280 
 }
1318 1281
1319 1282 
 // MUL Rd, Rs
1320 1283 
 static INSN_REGPARM void thumb43_1(uint32_t opcode)
1321 1284 
 {
1322 
-  clockTicks = 1;
1323 
-  int dest = opcode & 7;
1324 
-  uint32_t rm = reg[dest].I;
1325 
-  reg[dest].I = reg[(opcode >> 3) & 7].I * rm;
1326 
-  if (((int32_t)rm) < 0)
1327 
-    rm = ~rm;
1328 
-  if ((rm & 0xFFFFFF00) == 0)
1329 
-    clockTicks += 0;
1330 
-  else if ((rm & 0xFFFF0000) == 0)
1331 
-    clockTicks += 1;
1332 
-  else if ((rm & 0xFF000000) == 0)
1333 
-    clockTicks += 2;
1334 
-  else
1335 
-    clockTicks += 3;
1336 
-  busPrefetchCount = (busPrefetchCount<<clockTicks) | (0xFF>>(8-clockTicks));
1337 
-  clockTicks += codeTicksAccess16(armNextPC) + 1;
1338 
-  Z_FLAG = reg[dest].I ? false : true;
1339 
-  N_FLAG = reg[dest].I & 0x80000000 ? true : false;
1285 
+	clockTicks = 1;
1286 
+	int dest = opcode & 7;
1287 
+	uint32_t rm = reg[dest].I;
1288 
+	reg[dest].I = reg[(opcode >> 3) & 7].I * rm;
1289 
+	if (static_cast<int32_t>(rm) < 0)
1290 
+		rm = ~rm;
1291 
+	if (!(rm & 0xFFFFFF00))
1292 
+		; // No-op
1293 
+	else if (!(rm & 0xFFFF0000))
1294 
+		++clockTicks;
1295 
+	else if (!(rm & 0xFF000000))
1296 
+		clockTicks += 2;
1297 
+	else
1298 
+		clockTicks += 3;
1299 
+	busPrefetchCount = (busPrefetchCount << clockTicks) | (0xFF >> (8 - clockTicks));
1300 
+	clockTicks += codeTicksAccess16(armNextPC) + 1;
1301 
+	Z_FLAG = !reg[dest].I;
1302 
+	N_FLAG = !!(reg[dest].I & 0x80000000);
1340 1303 
 }
1341 1304
1342 1305 
 // BIC Rd, Rs
1343 1306 
 static INSN_REGPARM void thumb43_2(uint32_t opcode)
1344 1307 
 {
1345 
-  int dest = opcode & 7;
1346 
-  reg[dest].I &= (~reg[(opcode >> 3) & 7].I);
1347 
-  Z_FLAG = reg[dest].I ? false : true;
1348 
-  N_FLAG = reg[dest].I & 0x80000000 ? true : false;
1308 
+	int dest = opcode & 7;
1309 
+	reg[dest].I &= ~reg[(opcode >> 3) & 7].I;
1310 
+	Z_FLAG = !reg[dest].I;
1311 
+	N_FLAG = !!(reg[dest].I & 0x80000000);
1349 1312 
 }
1350 1313
1351 1314 
 // MVN Rd, Rs
1352 1315 
 static INSN_REGPARM void thumb43_3(uint32_t opcode)
1353 1316 
 {
1354 
-  int dest = opcode & 7;
1355 
-  reg[dest].I = ~reg[(opcode >> 3) & 7].I;
1356 
-  Z_FLAG = reg[dest].I ? false : true;
1357 
-  N_FLAG = reg[dest].I & 0x80000000 ? true : false;
1317 
+	int dest = opcode & 7;
1318 
+	reg[dest].I = ~reg[(opcode >> 3) & 7].I;
1319 
+	Z_FLAG = !reg[dest].I;
1320 
+	N_FLAG = !!(reg[dest].I & 0x80000000);
1358 1321 
 }
1359 1322
1360 1323 
 // High-register instructions and BX //////////////////////////////////////
... ... 
@@ -1362,128 +1325,127 @@ static INSN_REGPARM void thumb43_3(uint32_t opcode)
1362 1325 
 // ADD Rd, Hs
1363 1326 
 static INSN_REGPARM void thumb44_1(uint32_t opcode)
1364 1327 
 {
1365 
-  reg[opcode&7].I += reg[((opcode>>3)&7)+8].I;
1328 
+	reg[opcode & 7].I += reg[((opcode >> 3) & 7) + 8].I;
1366 1329 
 }
1367 1330
1368 1331 
 // ADD Hd, Rs
1369 1332 
 static INSN_REGPARM void thumb44_2(uint32_t opcode)
1370 1333 
 {
1371 
-  reg[(opcode&7)+8].I += reg[(opcode>>3)&7].I;
1372 
-  if((opcode&7) == 7) {
1373 
-    reg[15].I &= 0xFFFFFFFE;
1374 
-    armNextPC = reg[15].I;
1375 
-    reg[15].I += 2;
1376 
-    THUMB_PREFETCH;
1377 
-    clockTicks = codeTicksAccessSeq16(armNextPC)*2
1378 
-        + codeTicksAccess16(armNextPC) + 3;
1334 
+	reg[(opcode & 7) + 8].I += reg[(opcode >> 3) & 7].I;
1335 
+	if ((opcode & 7) == 7)
1336 
+	{
1337 
+		reg[15].I &= 0xFFFFFFFE;
1338 
+		armNextPC = reg[15].I;
1339 
+		reg[15].I += 2;
1340 
+		THUMB_PREFETCH();
1341 
+		clockTicks = codeTicksAccessSeq16(armNextPC) * 2 + codeTicksAccess16(armNextPC) + 3;
1379 1342 
   }
1380 1343 
 }
1381 1344
1382 1345 
 // ADD Hd, Hs
1383 1346 
 static INSN_REGPARM void thumb44_3(uint32_t opcode)
1384 1347 
 {
1385 
-  reg[(opcode&7)+8].I += reg[((opcode>>3)&7)+8].I;
1386 
-  if((opcode&7) == 7) {
1387 
-    reg[15].I &= 0xFFFFFFFE;
1388 
-    armNextPC = reg[15].I;
1389 
-    reg[15].I += 2;
1390 
-    THUMB_PREFETCH;
1391 
-    clockTicks = codeTicksAccessSeq16(armNextPC)*2
1392 
-        + codeTicksAccess16(armNextPC) + 3;
1393 
-  }
1348 
+	reg[(opcode & 7) + 8].I += reg[((opcode >> 3) & 7) + 8].I;
1349 
+	if ((opcode & 7) == 7)
1350 
+	{
1351 
+		reg[15].I &= 0xFFFFFFFE;
1352 
+		armNextPC = reg[15].I;
1353 
+		reg[15].I += 2;
1354 
+		THUMB_PREFETCH();
1355 
+		clockTicks = codeTicksAccessSeq16(armNextPC) * 2 + codeTicksAccess16(armNextPC) + 3;
1356 
+	}
1394 1357 
 }
1395 1358
1396 1359 
 // CMP Rd, Hs
1397 1360 
 static INSN_REGPARM void thumb45_1(uint32_t opcode)
1398 1361 
 {
1399 
-  int dest = opcode & 7;
1400 
-  uint32_t value = reg[((opcode>>3)&7)+8].I;
1401 
-  CMP_RD_RS;
1362 
+	int dest = opcode & 7;
1363 
+	uint32_t value = reg[((opcode >> 3) & 7) + 8].I;
1364 
+	CMP_RD_RS;
1402 1365 
 }
1403 1366
1404 1367 
 // CMP Hd, Rs
1405 1368 
 static INSN_REGPARM void thumb45_2(uint32_t opcode)
1406 1369 
 {
1407 
-  int dest = (opcode & 7) + 8;
1408 
-  uint32_t value = reg[(opcode>>3)&7].I;
1409 
-  CMP_RD_RS;
1370 
+	int dest = (opcode & 7) + 8;
1371 
+	uint32_t value = reg[(opcode >> 3) & 7].I;
1372 
+	CMP_RD_RS;
1410 1373 
 }
1411 1374
1412 1375 
 // CMP Hd, Hs
1413 1376 
 static INSN_REGPARM void thumb45_3(uint32_t opcode)
1414 1377 
 {
1415 
-  int dest = (opcode & 7) + 8;
1416 
-  uint32_t value = reg[((opcode>>3)&7)+8].I;
1417 
-  CMP_RD_RS;
1378 
+	int dest = (opcode & 7) + 8;
1379 
+	uint32_t value = reg[((opcode >> 3) & 7) + 8].I;
1380 
+	CMP_RD_RS;
1418 1381 
 }
1419 1382
1420 1383 
 // MOV Rd, Rs
1421 1384 
 static INSN_REGPARM void thumb46_0(uint32_t opcode)
1422 1385 
 {
1423 
-        reg[opcode&7].I = reg[((opcode>>3)&7)].I;
1424 
-        clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1386 
+	reg[opcode & 7].I = reg[(opcode >> 3) & 7].I;
1387 
+	clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1425 1388 
 }
1426 1389
1427 1390 
 // MOV Rd, Hs
1428 1391 
 static INSN_REGPARM void thumb46_1(uint32_t opcode)
1429 1392 
 {
1430 
-  reg[opcode&7].I = reg[((opcode>>3)&7)+8].I;
1431 
-  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1393 
+	reg[opcode & 7].I = reg[((opcode >> 3) & 7) + 8].I;
1394 
+	clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1432 1395 
 }
1433 1396
1434 1397 
 // MOV Hd, Rs
1435 1398 
 static INSN_REGPARM void thumb46_2(uint32_t opcode)
1436 1399 
 {
1437 
-  reg[(opcode&7)+8].I = reg[(opcode>>3)&7].I;
1438 
-  if((opcode&7) == 7) {
1439 
-    UPDATE_OLDREG;
1440 
-    reg[15].I &= 0xFFFFFFFE;
1441 
-    armNextPC = reg[15].I;
1442 
-    reg[15].I += 2;
1443 
-    THUMB_PREFETCH;
1444 
-    clockTicks = codeTicksAccessSeq16(armNextPC)*2
1445 
-        + codeTicksAccess16(armNextPC) + 3;
1446 
-  }
1400 
+	reg[(opcode & 7) + 8].I = reg[(opcode >> 3) & 7].I;
1401 
+	if ((opcode & 7) == 7)
1402 
+	{
1403 
+		reg[15].I &= 0xFFFFFFFE;
1404 
+		armNextPC = reg[15].I;
1405 
+		reg[15].I += 2;
1406 
+		THUMB_PREFETCH();
1407 
+		clockTicks = codeTicksAccessSeq16(armNextPC) * 2 + codeTicksAccess16(armNextPC) + 3;
1408 
+	}
1447 1409 
 }
1448 1410
1449 1411 
 // MOV Hd, Hs
1450 1412 
 static INSN_REGPARM void thumb46_3(uint32_t opcode)
1451 1413 
 {
1452 
-  reg[(opcode&7)+8].I = reg[((opcode>>3)&7)+8].I;
1453 
-  if((opcode&7) == 7) {
1454 
-    UPDATE_OLDREG;
1455 
-    reg[15].I &= 0xFFFFFFFE;
1456 
-    armNextPC = reg[15].I;
1457 
-    reg[15].I += 2;
1458 
-    THUMB_PREFETCH;
1459 
-    clockTicks = codeTicksAccessSeq16(armNextPC)*2
1460 
-        + codeTicksAccess16(armNextPC) + 3;
1461 
-  }
1414 
+	reg[(opcode & 7) + 8].I = reg[((opcode >> 3) & 7) + 8].I;
1415 
+	if ((opcode & 7) == 7)
1416 
+	{
1417 
+		reg[15].I &= 0xFFFFFFFE;
1418 
+		armNextPC = reg[15].I;
1419 
+		reg[15].I += 2;
1420 
+		THUMB_PREFETCH();
1421 
+		clockTicks = codeTicksAccessSeq16(armNextPC) * 2 + codeTicksAccess16(armNextPC) + 3;
1422 
+	}
1462 1423 
 }
1463 1424
1464 
-
1465 1425 
 // BX Rs
1466 1426 
 static INSN_REGPARM void thumb47(uint32_t opcode)
1467 1427 
 {
1468 
-  int base = (opcode >> 3) & 15;
1469 
-  busPrefetchCount=0;
1470 
-  UPDATE_OLDREG;
1471 
-  reg[15].I = reg[base].I;
1472 
-  if(reg[base].I & 1) {
1473 
-    armState = false;
1474 
-    reg[15].I &= 0xFFFFFFFE;
1475 
-    armNextPC = reg[15].I;
1476 
-    reg[15].I += 2;
1477 
-    THUMB_PREFETCH;
1478 
-    clockTicks = codeTicksAccessSeq16(armNextPC)*2 + codeTicksAccess16(armNextPC) + 3;
1479 
-  } else {
1480 
-    armState = true;
1481 
-    reg[15].I &= 0xFFFFFFFC;
1482 
-    armNextPC = reg[15].I;
1483 
-    reg[15].I += 4;
1484 
-    ARM_PREFETCH;
1485 
-    clockTicks = codeTicksAccessSeq32(armNextPC)*2 + codeTicksAccess32(armNextPC) + 3;
1486 
-  }
1428 
+	int base = (opcode >> 3) & 15;
1429 
+	busPrefetchCount = 0;
1430 
+	reg[15].I = reg[base].I;
1431 
+	if (reg[base].I & 1)
1432 
+	{
1433 
+		armState = false;
1434 
+		reg[15].I &= 0xFFFFFFFE;
1435 
+		armNextPC = reg[15].I;
1436 
+		reg[15].I += 2;
1437 
+		THUMB_PREFETCH();
1438 
+		clockTicks = codeTicksAccessSeq16(armNextPC) * 2 + codeTicksAccess16(armNextPC) + 3;
1439 
+	}
1440 
+	else
1441 
+	{
1442 
+		armState = true;
1443 
+		reg[15].I &= 0xFFFFFFFC;
1444 
+		armNextPC = reg[15].I;
1445 
+		reg[15].I += 4;
1446 
+		ARM_PREFETCH();
1447 
+		clockTicks = codeTicksAccessSeq32(armNextPC) * 2 + codeTicksAccess32(armNextPC) + 3;
1448 
+	}
1487 1449 
 }
1488 1450
1489 1451 
 // Load/store instructions ////////////////////////////////////////////////
... ... 
@@ -1491,175 +1453,175 @@ static INSN_REGPARM void thumb47(uint32_t opcode)
1491 1453 
 // LDR R0~R7,[PC, #Imm]
1492 1454 
 static INSN_REGPARM void thumb48(uint32_t opcode)
1493 1455 
 {
1494 
-  uint8_t regist = (opcode >> 8) & 7;
1495 
-  if (busPrefetchCount == 0)
1496 
-    busPrefetch = busPrefetchEnable;
1497 
-  uint32_t address = (reg[15].I & 0xFFFFFFFC) + ((opcode & 0xFF) << 2);
1498 
-  reg[regist].I = CPUReadMemoryQuick(address);
1499 
-  busPrefetchCount=0;
1500 
-  clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
1456 
+	uint8_t regist = (opcode >> 8) & 7;
1457 
+	if (!busPrefetchCount)
1458 
+		busPrefetch = busPrefetchEnable;
1459 
+	uint32_t address = (reg[15].I & 0xFFFFFFFC) + ((opcode & 0xFF) << 2);
1460 
+	reg[regist].I = CPUReadMemoryQuick(address);
1461 
+	busPrefetchCount = 0;
1462 
+	clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
1501 1463 
 }
1502 1464
1503 1465 
 // STR Rd, [Rs, Rn]
1504 1466 
 static INSN_REGPARM void thumb50(uint32_t opcode)
1505 1467 
 {
1506 
-  if (busPrefetchCount == 0)
1507 
-    busPrefetch = busPrefetchEnable;
1508 
-  uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1509 
-  CPUWriteMemory(address, reg[opcode & 7].I);
1510 
-  clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2;
1468 
+	if (!busPrefetchCount)
1469 
+		busPrefetch = busPrefetchEnable;
1470 
+	uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I;
1471 
+	CPUWriteMemory(address, reg[opcode & 7].I);
1472 
+	clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2;
1511 1473 
 }
1512 1474
1513 1475 
 // STRH Rd, [Rs, Rn]
1514 1476 
 static INSN_REGPARM void thumb52(uint32_t opcode)
1515 1477 
 {
1516 
-  if (busPrefetchCount == 0)
1517 
-    busPrefetch = busPrefetchEnable;
1518 
-  uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1519 
-  CPUWriteHalfWord(address, reg[opcode&7].W.W0);
1520 
-  clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2;
1478 
+	if (!busPrefetchCount)
1479 
+		busPrefetch = busPrefetchEnable;
1480 
+	uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I;
1481 
+	CPUWriteHalfWord(address, reg[opcode & 7].W.W0);
1482 
+	clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2;
1521 1483 
 }
1522 1484
1523 1485 
 // STRB Rd, [Rs, Rn]
1524 1486 
 static INSN_REGPARM void thumb54(uint32_t opcode)
1525 1487 
 {
1526 
-  if (busPrefetchCount == 0)
1527 
-    busPrefetch = busPrefetchEnable;
1528 
-  uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode >>6)&7].I;
1529 
-  CPUWriteByte(address, reg[opcode & 7].B.B0);
1530 
-  clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2;
1488 
+	if (!busPrefetchCount)
1489 
+		busPrefetch = busPrefetchEnable;
1490 
+	uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I;
1491 
+	CPUWriteByte(address, reg[opcode & 7].B.B0);
1492 
+	clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2;
1531 1493 
 }
1532 1494
1533 1495 
 // LDSB Rd, [Rs, Rn]
1534 1496 
 static INSN_REGPARM void thumb56(uint32_t opcode)
1535 1497 
 {
1536 
-  if (busPrefetchCount == 0)
1537 
-    busPrefetch = busPrefetchEnable;
1538 
-  uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1539 
-  reg[opcode&7].I = (int8_t)CPUReadByte(address);
1540 
-  clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1498 
+	if (!busPrefetchCount)
1499 
+		busPrefetch = busPrefetchEnable;
1500 
+	uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I;
1501 
+	reg[opcode & 7].I = static_cast<int8_t>(CPUReadByte(address));
1502 
+	clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1541 1503 
 }
1542 1504
1543 1505 
 // LDR Rd, [Rs, Rn]
1544 1506 
 static INSN_REGPARM void thumb58(uint32_t opcode)
1545 1507 
 {
1546 
-  if (busPrefetchCount == 0)
1547 
-    busPrefetch = busPrefetchEnable;
1548 
-  uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1549 
-  reg[opcode&7].I = CPUReadMemory(address);
1550 
-  clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
1508 
+	if (!busPrefetchCount)
1509 
+		busPrefetch = busPrefetchEnable;
1510 
+	uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I;
1511 
+	reg[opcode & 7].I = CPUReadMemory(address);
1512 
+	clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
1551 1513 
 }
1552 1514
1553 1515 
 // LDRH Rd, [Rs, Rn]
1554 1516 
 static INSN_REGPARM void thumb5A(uint32_t opcode)
1555 1517 
 {
1556 
-  if (busPrefetchCount == 0)
1557 
-    busPrefetch = busPrefetchEnable;
1558 
-  uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1559 
-  reg[opcode&7].I = CPUReadHalfWord(address);
1560 
-  clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
1518 
+	if (!busPrefetchCount)
1519 
+		busPrefetch = busPrefetchEnable;
1520 
+	uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I;
1521 
+	reg[opcode & 7].I = CPUReadHalfWord(address);
1522 
+	clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
1561 1523 
 }
1562 1524
1563 1525 
 // LDRB Rd, [Rs, Rn]
1564 1526 
 static INSN_REGPARM void thumb5C(uint32_t opcode)
1565 1527 
 {
1566 
-  if (busPrefetchCount == 0)
1567 
-    busPrefetch = busPrefetchEnable;
1568 
-  uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1569 
-  reg[opcode&7].I = CPUReadByte(address);
1570 
-  clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1528 
+	if (!busPrefetchCount)
1529 
+		busPrefetch = busPrefetchEnable;
1530 
+	uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I;
1531 
+	reg[opcode & 7].I = CPUReadByte(address);
1532 
+	clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1571 1533 
 }
1572 1534
1573 1535 
 // LDSH Rd, [Rs, Rn]
1574 1536 
 static INSN_REGPARM void thumb5E(uint32_t opcode)
1575 1537 
 {
1576 
-  if (busPrefetchCount == 0)
1577 
-    busPrefetch = busPrefetchEnable;
1578 
-  uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1579 
-  reg[opcode&7].I = (uint32_t)CPUReadHalfWordSigned(address);
1580 
-  clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1538 
+	if (!busPrefetchCount)
1539 
+		busPrefetch = busPrefetchEnable;
1540 
+	uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I;
1541 
+	reg[opcode & 7].I = (uint32_t)CPUReadHalfWordSigned(address);
1542 
+	clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1581 1543 
 }
1582 1544
1583 1545 
 // STR Rd, [Rs, #Imm]
1584 1546 
 static INSN_REGPARM void thumb60(uint32_t opcode)
1585 1547 
 {
1586 
-  if (busPrefetchCount == 0)
1587 
-    busPrefetch = busPrefetchEnable;
1588 
-  uint32_t address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<2);
1589 
-  CPUWriteMemory(address, reg[opcode&7].I);
1590 
-  clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2;
1548 
+	if (!busPrefetchCount)
1549 
+		busPrefetch = busPrefetchEnable;
1550 
+	uint32_t address = reg[(opcode >> 3) & 7].I + (((opcode >> 6) & 31) << 2);
1551 
+	CPUWriteMemory(address, reg[opcode & 7].I);
1552 
+	clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2;
1591 1553 
 }
1592 1554
1593 1555 
 // LDR Rd, [Rs, #Imm]
1594 1556 
 static INSN_REGPARM void thumb68(uint32_t opcode)
1595 1557 
 {
1596 
-  if (busPrefetchCount == 0)
1597 
-    busPrefetch = busPrefetchEnable;
1598 
-  uint32_t address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<2);
1599 
-  reg[opcode&7].I = CPUReadMemory(address);
1600 
-  clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
1558 
+	if (!busPrefetchCount)
1559 
+		busPrefetch = busPrefetchEnable;
1560 
+	uint32_t address = reg[(opcode >> 3) & 7].I + (((opcode >> 6) & 31) << 2);
1561 
+	reg[opcode & 7].I = CPUReadMemory(address);
1562 
+	clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
1601 1563 
 }
1602 1564
1603 1565 
 // STRB Rd, [Rs, #Imm]
1604 1566 
 static INSN_REGPARM void thumb70(uint32_t opcode)
1605 1567 
 {
1606 
-  if (busPrefetchCount == 0)
1607 
-    busPrefetch = busPrefetchEnable;
1608 
-  uint32_t address = reg[(opcode>>3)&7].I + (((opcode>>6)&31));
1609 
-  CPUWriteByte(address, reg[opcode&7].B.B0);
1610 
-  clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2;
1568 
+	if (!busPrefetchCount)
1569 
+		busPrefetch = busPrefetchEnable;
1570 
+	uint32_t address = reg[(opcode >> 3) & 7].I + ((opcode >> 6) & 31);
1571 
+	CPUWriteByte(address, reg[opcode & 7].B.B0);
1572 
+	clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2;
1611 1573 
 }
1612 1574
1613 1575 
 // LDRB Rd, [Rs, #Imm]
1614 1576 
 static INSN_REGPARM void thumb78(uint32_t opcode)
1615 1577 
 {
1616 
-  if (busPrefetchCount == 0)
1617 
-    busPrefetch = busPrefetchEnable;
1618 
-  uint32_t address = reg[(opcode>>3)&7].I + (((opcode>>6)&31));
1619 
-  reg[opcode&7].I = CPUReadByte(address);
1620 
-  clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1578 
+	if (!busPrefetchCount)
1579 
+		busPrefetch = busPrefetchEnable;
1580 
+	uint32_t address = reg[(opcode >> 3) & 7].I + ((opcode >> 6) & 31);
1581 
+	reg[opcode & 7].I = CPUReadByte(address);
1582 
+	clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1621 1583 
 }
1622 1584
1623 1585 
 // STRH Rd, [Rs, #Imm]
1624 1586 
 static INSN_REGPARM void thumb80(uint32_t opcode)
1625 1587 
 {
1626 
-  if (busPrefetchCount == 0)
1627 
-    busPrefetch = busPrefetchEnable;
1628 
-  uint32_t address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<1);
1629 
-  CPUWriteHalfWord(address, reg[opcode&7].W.W0);
1630 
-  clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2;
1588 
+	if (!busPrefetchCount)
1589 
+		busPrefetch = busPrefetchEnable;
1590 
+	uint32_t address = reg[(opcode >> 3) & 7].I + (((opcode >> 6) & 31) << 1);
1591 
+	CPUWriteHalfWord(address, reg[opcode & 7].W.W0);
1592 
+	clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2;
1631 1593 
 }
1632 1594
1633 1595 
 // LDRH Rd, [Rs, #Imm]
1634 1596 
 static INSN_REGPARM void thumb88(uint32_t opcode)
1635 1597 
 {
1636 
-  if (busPrefetchCount == 0)
1637 
-    busPrefetch = busPrefetchEnable;
1638 
-  uint32_t address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<1);
1639 
-  reg[opcode&7].I = CPUReadHalfWord(address);
1640 
-  clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1598 
+	if (!busPrefetchCount)
1599 
+		busPrefetch = busPrefetchEnable;
1600 
+	uint32_t address = reg[(opcode >> 3) & 7].I + (((opcode >> 6) & 31) << 1);
1601 
+	reg[opcode & 7].I = CPUReadHalfWord(address);
1602 
+	clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1641 1603 
 }
1642 1604
1643 1605 
 // STR R0~R7, [SP, #Imm]
1644 1606 
 static INSN_REGPARM void thumb90(uint32_t opcode)
1645 1607 
 {
1646 
-  uint8_t regist = (opcode >> 8) & 7;
1647 
-  if (busPrefetchCount == 0)
1648 
-    busPrefetch = busPrefetchEnable;
1649 
-  uint32_t address = reg[13].I + ((opcode&255)<<2);
1650 
-  CPUWriteMemory(address, reg[regist].I);
1651 
-  clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2;
1608 
+	uint8_t regist = (opcode >> 8) & 7;
1609 
+	if (!busPrefetchCount)
1610 
+		busPrefetch = busPrefetchEnable;
1611 
+	uint32_t address = reg[13].I + ((opcode & 255) << 2);
1612 
+	CPUWriteMemory(address, reg[regist].I);
1613 
+	clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2;
1652 1614 
 }
1653 1615
1654 1616 
 // LDR R0~R7, [SP, #Imm]
1655 1617 
 static INSN_REGPARM void thumb98(uint32_t opcode)
1656 1618 
 {
1657 
-  uint8_t regist = (opcode >> 8) & 7;
1658 
-  if (busPrefetchCount == 0)
1659 
-    busPrefetch = busPrefetchEnable;
1660 
-  uint32_t address = reg[13].I + ((opcode&255)<<2);
1661 
-  reg[regist].I = CPUReadMemoryQuick(address);
1662 
-  clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
1619 
+	uint8_t regist = (opcode >> 8) & 7;
1620 
+	if (!busPrefetchCount)
1621 
+		busPrefetch = busPrefetchEnable;
1622 
+	uint32_t address = reg[13].I + ((opcode & 255) << 2);
1623 
+	reg[regist].I = CPUReadMemoryQuick(address);
1624 
+	clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
1663 1625 
 }
1664 1626
1665 1627 
 // PC/stack-related ///////////////////////////////////////////////////////
... ... 
@@ -1667,216 +1629,215 @@ static INSN_REGPARM void thumb98(uint32_t opcode)
1667 1629 
 // ADD R0~R7, PC, Imm
1668 1630 
 static INSN_REGPARM void thumbA0(uint32_t opcode)
1669 1631 
 {
1670 
-  uint8_t regist = (opcode >> 8) & 7;
1671 
-  reg[regist].I = (reg[15].I & 0xFFFFFFFC) + ((opcode&255)<<2);
1672 
-  clockTicks = 1 + codeTicksAccess16(armNextPC);
1632 
+	uint8_t regist = (opcode >> 8) & 7;
1633 
+	reg[regist].I = (reg[15].I & 0xFFFFFFFC) + ((opcode & 255) << 2);
1634 
+	clockTicks = 1 + codeTicksAccess16(armNextPC);
1673 1635 
 }
1674 1636
1675 1637 
 // ADD R0~R7, SP, Imm
1676 1638 
 static INSN_REGPARM void thumbA8(uint32_t opcode)
1677 1639 
 {
1678 
-  uint8_t regist = (opcode >> 8) & 7;
1679 
-  reg[regist].I = reg[13].I + ((opcode&255)<<2);
1680 
-  clockTicks = 1 + codeTicksAccess16(armNextPC);
1640 
+	uint8_t regist = (opcode >> 8) & 7;
1641 
+	reg[regist].I = reg[13].I + ((opcode & 255) << 2);
1642 
+	clockTicks = 1 + codeTicksAccess16(armNextPC);
1681 1643 
 }
1682 1644
1683 1645 
 // ADD SP, Imm
1684 1646 
 static INSN_REGPARM void thumbB0(uint32_t opcode)
1685 1647 
 {
1686 
-  int offset = (opcode & 127) << 2;
1687 
-  if(opcode & 0x80)
1688 
-    offset = -offset;
1689 
-  reg[13].I += offset;
1690 
-  clockTicks = 1 + codeTicksAccess16(armNextPC);
1648 
+	int offset = (opcode & 127) << 2;
1649 
+	if (opcode & 0x80)
1650 
+		offset = -offset;
1651 
+	reg[13].I += offset;
1652 
+	clockTicks = 1 + codeTicksAccess16(armNextPC);
1691 1653 
 }
1692 1654
1693 1655 
 // Push and pop ///////////////////////////////////////////////////////////
1694 1656
1695 
-#define PUSH_REG(val, r)                                    \
1696 
-  if (opcode & (val)) {                                     \
1697 
-    CPUWriteMemory(address, reg[(r)].I);                    \
1698 
-    if (!count) {                                           \
1699 
-        clockTicks += 1 + dataTicksAccess32(address);       \
1700 
-    } else {                                                \
1701 
-        clockTicks += 1 + dataTicksAccessSeq32(address);    \
1702 
-    }                                                       \
1703 
-    count++;                                                \
1704 
-    address += 4;                                           \
1705 
-  }
1706 
-
1707 
-#define POP_REG(val, r)                                     \
1708 
-  if (opcode & (val)) {                                     \
1709 
-    reg[(r)].I = CPUReadMemory(address);                    \
1710 
-    if (!count) {                                           \
1711 
-        clockTicks += 1 + dataTicksAccess32(address);       \
1712 
-    } else {                                                \
1713 
-        clockTicks += 1 + dataTicksAccessSeq32(address);    \
1714 
-    }                                                       \
1715 
-    count++;                                                \
1716 
-    address += 4;                                           \
1717 
-  }
1657 
+#define PUSH_REG(val, r) \
1658 
+	if (opcode & (val)) \
1659 
+	{ \
1660 
+		CPUWriteMemory(address, reg[(r)].I); \
1661 
+		if (!count) \
1662 
+			clockTicks += 1 + dataTicksAccess32(address); \
1663 
+		else \
1664 
+			clockTicks += 1 + dataTicksAccessSeq32(address); \
1665 
+		++count; \
1666 
+		address += 4; \
1667 
+	}
1668 
+
1669 
+#define POP_REG(val, r) \
1670 
+	if (opcode & (val)) \
1671 
+	{ \
1672 
+		reg[(r)].I = CPUReadMemory(address); \
1673 
+		if (!count) \
1674 
+			clockTicks += 1 + dataTicksAccess32(address); \
1675 
+		else \
1676 
+			clockTicks += 1 + dataTicksAccessSeq32(address); \
1677 
+		++count; \
1678 
+		address += 4; \
1679 
+	}
1718 1680
1719 1681 
 // PUSH {Rlist}
1720 1682 
 static INSN_REGPARM void thumbB4(uint32_t opcode)
1721 1683 
 {
1722 
-  if (busPrefetchCount == 0)
1723 
-    busPrefetch = busPrefetchEnable;
1724 
-  int count = 0;
1725 
-  uint32_t temp = reg[13].I - 4 * cpuBitsSet[opcode & 0xff];
1726 
-  uint32_t address = temp & 0xFFFFFFFC;
1727 
-  PUSH_REG(1, 0);
1728 
-  PUSH_REG(2, 1);
1729 
-  PUSH_REG(4, 2);
1730 
-  PUSH_REG(8, 3);
1731 
-  PUSH_REG(16, 4);
1732 
-  PUSH_REG(32, 5);
1733 
-  PUSH_REG(64, 6);
1734 
-  PUSH_REG(128, 7);
1735 
-  clockTicks += 1 + codeTicksAccess16(armNextPC);
1736 
-  reg[13].I = temp;
1684 
+	if (!busPrefetchCount)
1685 
+		busPrefetch = busPrefetchEnable;
1686 
+	int count = 0;
1687 
+	uint32_t temp = reg[13].I - 4 * cpuBitsSet[opcode & 0xff];
1688 
+	uint32_t address = temp & 0xFFFFFFFC;
1689 
+	PUSH_REG(1, 0);
1690 
+	PUSH_REG(2, 1);
1691 
+	PUSH_REG(4, 2);
1692 
+	PUSH_REG(8, 3);
1693 
+	PUSH_REG(16, 4);
1694 
+	PUSH_REG(32, 5);
1695 
+	PUSH_REG(64, 6);
1696 
+	PUSH_REG(128, 7);
1697 
+	clockTicks += 1 + codeTicksAccess16(armNextPC);
1698 
+	reg[13].I = temp;
1737 1699 
 }
1738 1700
1739 1701 
 // PUSH {Rlist, LR}
1740 1702 
 static INSN_REGPARM void thumbB5(uint32_t opcode)
1741 1703 
 {
1742 
-  if (busPrefetchCount == 0)
1743 
-    busPrefetch = busPrefetchEnable;
1744 
-  int count = 0;
1745 
-  uint32_t temp = reg[13].I - 4 - 4 * cpuBitsSet[opcode & 0xff];
1746 
-  uint32_t address = temp & 0xFFFFFFFC;
1747 
-  PUSH_REG(1, 0);
1748 
-  PUSH_REG(2, 1);
1749 
-  PUSH_REG(4, 2);
1750 
-  PUSH_REG(8, 3);
1751 
-  PUSH_REG(16, 4);
1752 
-  PUSH_REG(32, 5);
1753 
-  PUSH_REG(64, 6);
1754 
-  PUSH_REG(128, 7);
1755 
-  PUSH_REG(256, 14);
1756 
-  clockTicks += 1 + codeTicksAccess16(armNextPC);
1757 
-  reg[13].I = temp;
1704 
+	if (!busPrefetchCount)
1705 
+		busPrefetch = busPrefetchEnable;
1706 
+	int count = 0;
1707 
+	uint32_t temp = reg[13].I - 4 - 4 * cpuBitsSet[opcode & 0xff];
1708 
+	uint32_t address = temp & 0xFFFFFFFC;
1709 
+	PUSH_REG(1, 0);
1710 
+	PUSH_REG(2, 1);
1711 
+	PUSH_REG(4, 2);
1712 
+	PUSH_REG(8, 3);
1713 
+	PUSH_REG(16, 4);
1714 
+	PUSH_REG(32, 5);
1715 
+	PUSH_REG(64, 6);
1716 
+	PUSH_REG(128, 7);
1717 
+	PUSH_REG(256, 14);
1718 
+	clockTicks += 1 + codeTicksAccess16(armNextPC);
1719 
+	reg[13].I = temp;
1758 1720 
 }
1759 1721
1760 1722 
 // POP {Rlist}
1761 1723 
 static INSN_REGPARM void thumbBC(uint32_t opcode)
1762 1724 
 {
1763 
-  if (busPrefetchCount == 0)
1764 
-    busPrefetch = busPrefetchEnable;
1765 
-  int count = 0;
1766 
-  uint32_t address = reg[13].I & 0xFFFFFFFC;
1767 
-  uint32_t temp = reg[13].I + 4*cpuBitsSet[opcode & 0xFF];
1768 
-  POP_REG(1, 0);
1769 
-  POP_REG(2, 1);
1770 
-  POP_REG(4, 2);
1771 
-  POP_REG(8, 3);
1772 
-  POP_REG(16, 4);
1773 
-  POP_REG(32, 5);
1774 
-  POP_REG(64, 6);
1775 
-  POP_REG(128, 7);
1776 
-  reg[13].I = temp;
1777 
-  clockTicks = 2 + codeTicksAccess16(armNextPC);
1725 
+	if (!busPrefetchCount)
1726 
+		busPrefetch = busPrefetchEnable;
1727 
+	int count = 0;
1728 
+	uint32_t address = reg[13].I & 0xFFFFFFFC;
1729 
+	uint32_t temp = reg[13].I + 4 * cpuBitsSet[opcode & 0xFF];
1730 
+	POP_REG(1, 0);
1731 
+	POP_REG(2, 1);
1732 
+	POP_REG(4, 2);
1733 
+	POP_REG(8, 3);
1734 
+	POP_REG(16, 4);
1735 
+	POP_REG(32, 5);
1736 
+	POP_REG(64, 6);
1737 
+	POP_REG(128, 7);
1738 
+	reg[13].I = temp;
1739 
+	clockTicks = 2 + codeTicksAccess16(armNextPC);
1778 1740 
 }
1779 1741
1780 1742 
 // POP {Rlist, PC}
1781 1743 
 static INSN_REGPARM void thumbBD(uint32_t opcode)
1782 1744 
 {
1783 
-  if (busPrefetchCount == 0)
1784 
-    busPrefetch = busPrefetchEnable;
1785 
-  int count = 0;
1786 
-  uint32_t address = reg[13].I & 0xFFFFFFFC;
1787 
-  uint32_t temp = reg[13].I + 4 + 4*cpuBitsSet[opcode & 0xFF];
1788 
-  POP_REG(1, 0);
1789 
-  POP_REG(2, 1);
1790 
-  POP_REG(4, 2);
1791 
-  POP_REG(8, 3);
1792 
-  POP_REG(16, 4);
1793 
-  POP_REG(32, 5);
1794 
-  POP_REG(64, 6);
1795 
-  POP_REG(128, 7);
1796 
-  reg[15].I = (CPUReadMemory(address) & 0xFFFFFFFE);
1797 
-  if (!count) {
1798 
-    clockTicks += 1 + dataTicksAccess32(address);
1799 
-  } else {
1800 
-    clockTicks += 1 + dataTicksAccessSeq32(address);
1801 
-  }
1802 
-  count++;
1803 
-  armNextPC = reg[15].I;
1804 
-  reg[15].I += 2;
1805 
-  reg[13].I = temp;
1806 
-  THUMB_PREFETCH;
1807 
-  busPrefetchCount = 0;
1808 
-  clockTicks += 3 + codeTicksAccess16(armNextPC) + codeTicksAccess16(armNextPC);
1745 
+	if (!busPrefetchCount)
1746 
+		busPrefetch = busPrefetchEnable;
1747 
+	int count = 0;
1748 
+	uint32_t address = reg[13].I & 0xFFFFFFFC;
1749 
+	uint32_t temp = reg[13].I + 4 + 4 * cpuBitsSet[opcode & 0xFF];
1750 
+	POP_REG(1, 0);
1751 
+	POP_REG(2, 1);
1752 
+	POP_REG(4, 2);
1753 
+	POP_REG(8, 3);
1754 
+	POP_REG(16, 4);
1755 
+	POP_REG(32, 5);
1756 
+	POP_REG(64, 6);
1757 
+	POP_REG(128, 7);
1758 
+	reg[15].I = CPUReadMemory(address) & 0xFFFFFFFE;
1759 
+	if (!count)
1760 
+		clockTicks += 1 + dataTicksAccess32(address);
1761 
+	else
1762 
+		clockTicks += 1 + dataTicksAccessSeq32(address);
1763 
+	++count;
1764 
+	armNextPC = reg[15].I;
1765 
+	reg[15].I += 2;
1766 
+	reg[13].I = temp;
1767 
+	THUMB_PREFETCH();
1768 
+	busPrefetchCount = 0;
1769 
+	clockTicks += 3 + codeTicksAccess16(armNextPC) + codeTicksAccess16(armNextPC);
1809 1770 
 }
1810 1771
1811 1772 
 // Load/store multiple ////////////////////////////////////////////////////
1812 1773
1813 
-#define THUMB_STM_REG(val,r,b)                              \
1814 
-  if(opcode & (val)) {                                      \
1815 
-    CPUWriteMemory(address, reg[(r)].I);                    \
1816 
-    reg[(b)].I = temp;                                      \
1817 
-    if (!count) {                                           \
1818 
-        clockTicks += 1 + dataTicksAccess32(address);       \
1819 
-    } else {                                                \
1820 
-        clockTicks += 1 + dataTicksAccessSeq32(address);    \
1821 
-    }                                                       \
1822 
-    count++;                                                \
1823 
-    address += 4;                                           \
1824 
-  }
1825 
-
1826 
-#define THUMB_LDM_REG(val,r)                                \
1827 
-  if(opcode & (val)) {                                      \
1828 
-    reg[(r)].I = CPUReadMemory(address);                    \
1829 
-    if (!count) {                                           \
1830 
-        clockTicks += 1 + dataTicksAccess32(address);       \
1831 
-    } else {                                                \
1832 
-        clockTicks += 1 + dataTicksAccessSeq32(address);    \
1833 
-    }                                                       \
1834 
-    count++;                                                \
1835 
-    address += 4;                                           \
1836 
-  }
1774 
+#define THUMB_STM_REG(val, r, b) \
1775 
+	if (opcode & (val)) \
1776 
+	{ \
1777 
+		CPUWriteMemory(address, reg[(r)].I); \
1778 
+		reg[(b)].I = temp; \
1779 
+		if (!count) \
1780 
+			clockTicks += 1 + dataTicksAccess32(address); \
1781 
+		else \
1782 
+			clockTicks += 1 + dataTicksAccessSeq32(address); \
1783 
+		++count; \
1784 
+		address += 4; \
1785 
+	}
1786 
+
1787 
+#define THUMB_LDM_REG(val, r) \
1788 
+	if (opcode & (val)) \
1789 
+	{ \
1790 
+		reg[(r)].I = CPUReadMemory(address); \
1791 
+		if (!count) \
1792 
+			clockTicks += 1 + dataTicksAccess32(address); \
1793 
+		else \
1794 
+			clockTicks += 1 + dataTicksAccessSeq32(address); \
1795 
+		++count; \
1796 
+		address += 4; \
1797 
+	}
1837 1798
1838 1799 
 // STM R0~7!, {Rlist}
1839 1800 
 static INSN_REGPARM void thumbC0(uint32_t opcode)
1840 1801 
 {
1841 
-  uint8_t regist = (opcode >> 8) & 7;
1842 
-  if (busPrefetchCount == 0)
1843 
-    busPrefetch = busPrefetchEnable;
1844 
-  uint32_t address = reg[regist].I & 0xFFFFFFFC;
1845 
-  uint32_t temp = reg[regist].I + 4*cpuBitsSet[opcode & 0xff];
1846 
-  int count = 0;
1847 
-  // store
1848 
-  THUMB_STM_REG(1, 0, regist);
1849 
-  THUMB_STM_REG(2, 1, regist);
1850 
-  THUMB_STM_REG(4, 2, regist);
1851 
-  THUMB_STM_REG(8, 3, regist);
1852 
-  THUMB_STM_REG(16, 4, regist);
1853 
-  THUMB_STM_REG(32, 5, regist);
1854 
-  THUMB_STM_REG(64, 6, regist);
1855 
-  THUMB_STM_REG(128, 7, regist);
1856 
-  clockTicks = 1 + codeTicksAccess16(armNextPC);
1802 
+	uint8_t regist = (opcode >> 8) & 7;
1803 
+	if (!busPrefetchCount)
1804 
+		busPrefetch = busPrefetchEnable;
1805 
+	uint32_t address = reg[regist].I & 0xFFFFFFFC;
1806 
+	uint32_t temp = reg[regist].I + 4*cpuBitsSet[opcode & 0xff];
1807 
+	int count = 0;
1808 
+	// store
1809 
+	THUMB_STM_REG(1, 0, regist);
1810 
+	THUMB_STM_REG(2, 1, regist);
1811 
+	THUMB_STM_REG(4, 2, regist);
1812 
+	THUMB_STM_REG(8, 3, regist);
1813 
+	THUMB_STM_REG(16, 4, regist);
1814 
+	THUMB_STM_REG(32, 5, regist);
1815 
+	THUMB_STM_REG(64, 6, regist);
1816 
+	THUMB_STM_REG(128, 7, regist);
1817 
+	clockTicks = 1 + codeTicksAccess16(armNextPC);
1857 1818 
 }
1858 1819
1859 1820 
 // LDM R0~R7!, {Rlist}
1860 1821 
 static INSN_REGPARM void thumbC8(uint32_t opcode)
1861 1822 
 {
1862 
-  uint8_t regist = (opcode >> 8) & 7;
1863 
-  if (busPrefetchCount == 0)
1864 
-    busPrefetch = busPrefetchEnable;
1865 
-  uint32_t address = reg[regist].I & 0xFFFFFFFC;
1866 
-  uint32_t temp = reg[regist].I + 4*cpuBitsSet[opcode & 0xFF];
1867 
-  int count = 0;
1868 
-  // load
1869 
-  THUMB_LDM_REG(1, 0);
1870 
-  THUMB_LDM_REG(2, 1);
1871 
-  THUMB_LDM_REG(4, 2);
1872 
-  THUMB_LDM_REG(8, 3);
1873 
-  THUMB_LDM_REG(16, 4);
1874 
-  THUMB_LDM_REG(32, 5);
1875 
-  THUMB_LDM_REG(64, 6);
1876 
-  THUMB_LDM_REG(128, 7);
1877 
-  clockTicks = 2 + codeTicksAccess16(armNextPC);
1878 
-  if(!(opcode & (1<<regist)))
1879 
-    reg[regist].I = temp;
1823 
+	uint8_t regist = (opcode >> 8) & 7;
1824 
+	if (!busPrefetchCount)
1825 
+		busPrefetch = busPrefetchEnable;
1826 
+	uint32_t address = reg[regist].I & 0xFFFFFFFC;
1827 
+	uint32_t temp = reg[regist].I + 4*cpuBitsSet[opcode & 0xFF];
1828 
+	int count = 0;
1829 
+	// load
1830 
+	THUMB_LDM_REG(1, 0);
1831 
+	THUMB_LDM_REG(2, 1);
1832 
+	THUMB_LDM_REG(4, 2);
1833 
+	THUMB_LDM_REG(8, 3);
1834 
+	THUMB_LDM_REG(16, 4);
1835 
+	THUMB_LDM_REG(32, 5);
1836 
+	THUMB_LDM_REG(64, 6);
1837 
+	THUMB_LDM_REG(128, 7);
1838 
+	clockTicks = 2 + codeTicksAccess16(armNextPC);
1839 
+	if (!(opcode & (1 << regist)))
1840 
+		reg[regist].I = temp;
1880 1841 
 }
1881 1842
1882 1843 
 // Conditional branches ///////////////////////////////////////////////////
... ... 
@@ -1884,211 +1845,211 @@ static INSN_REGPARM void thumbC8(uint32_t opcode)
1884 1845 
 // BEQ offset
1885 1846 
 static INSN_REGPARM void thumbD0(uint32_t opcode)
1886 1847 
 {
1887 
-  UPDATE_OLDREG;
1888 
-  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1889 
-  if(Z_FLAG) {
1890 
-    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
1891 
-    armNextPC = reg[15].I;
1892 
-    reg[15].I += 2;
1893 
-    THUMB_PREFETCH;
1894 
-    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1895 
-    busPrefetchCount=0;
1896 
-  }
1848 
+	clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1849 
+	if (Z_FLAG)
1850 
+	{
1851 
+		reg[15].I += static_cast<int8_t>(opcode & 0xFF) << 1;
1852 
+		armNextPC = reg[15].I;
1853 
+		reg[15].I += 2;
1854 
+		THUMB_PREFETCH();
1855 
+		clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1856 
+		busPrefetchCount = 0;
1857 
+	}
1897 1858 
 }
1898 1859
1899 1860 
 // BNE offset
1900 1861 
 static INSN_REGPARM void thumbD1(uint32_t opcode)
1901 1862 
 {
1902 
-  UPDATE_OLDREG;
1903 
-  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1904 
-  if(!Z_FLAG) {
1905 
-    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
1906 
-    armNextPC = reg[15].I;
1907 
-    reg[15].I += 2;
1908 
-    THUMB_PREFETCH;
1909 
-    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1910 
-    busPrefetchCount=0;
1911 
-  }
1863 
+	clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1864 
+	if (!Z_FLAG)
1865 
+	{
1866 
+		reg[15].I += static_cast<int8_t>(opcode & 0xFF) << 1;
1867 
+		armNextPC = reg[15].I;
1868 
+		reg[15].I += 2;
1869 
+		THUMB_PREFETCH();
1870 
+		clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1871 
+		busPrefetchCount = 0;
1872 
+	}
1912 1873 
 }
1913 1874
1914 1875 
 // BCS offset
1915 1876 
 static INSN_REGPARM void thumbD2(uint32_t opcode)
1916 1877 
 {
1917 
-  UPDATE_OLDREG;
1918 
-  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1919 
-  if(C_FLAG) {
1920 
-    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
1921 
-    armNextPC = reg[15].I;
1922 
-    reg[15].I += 2;
1923 
-    THUMB_PREFETCH;
1924 
-    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1925 
-    busPrefetchCount=0;
1926 
-  }
1878 
+	clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1879 
+	if (C_FLAG)
1880 
+	{
1881 
+		reg[15].I += static_cast<int8_t>(opcode & 0xFF) << 1;
1882 
+		armNextPC = reg[15].I;
1883 
+		reg[15].I += 2;
1884 
+		THUMB_PREFETCH();
1885 
+		clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1886 
+		busPrefetchCount = 0;
1887 
+	}
1927 1888 
 }
1928 1889
1929 1890 
 // BCC offset
1930 1891 
 static INSN_REGPARM void thumbD3(uint32_t opcode)
1931 1892 
 {
1932 
-  UPDATE_OLDREG;
1933 
-  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1934 
-  if(!C_FLAG) {
1935 
-    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
1936 
-    armNextPC = reg[15].I;
1937 
-    reg[15].I += 2;
1938 
-    THUMB_PREFETCH;
1939 
-    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1940 
-    busPrefetchCount=0;
1941 
-  }
1893 
+	clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1894 
+	if (!C_FLAG)
1895 
+	{
1896 
+		reg[15].I += static_cast<int8_t>(opcode & 0xFF) << 1;
1897 
+		armNextPC = reg[15].I;
1898 
+		reg[15].I += 2;
1899 
+		THUMB_PREFETCH();
1900 
+		clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1901 
+		busPrefetchCount = 0;
1902 
+	}
1942 1903 
 }
1943 1904
1944 1905 
 // BMI offset
1945 1906 
 static INSN_REGPARM void thumbD4(uint32_t opcode)
1946 1907 
 {
1947 
-  UPDATE_OLDREG;
1948 
-  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1949 
-  if(N_FLAG) {
1950 
-    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
1951 
-    armNextPC = reg[15].I;
1952 
-    reg[15].I += 2;
1953 
-    THUMB_PREFETCH;
1954 
-    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1955 
-    busPrefetchCount=0;
1956 
-  }
1908 
+	clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1909 
+	if (N_FLAG)
1910 
+	{
1911 
+		reg[15].I += static_cast<int8_t>(opcode & 0xFF) << 1;
1912 
+		armNextPC = reg[15].I;
1913 
+		reg[15].I += 2;
1914 
+		THUMB_PREFETCH();
1915 
+		clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1916 
+		busPrefetchCount = 0;
1917 
+	}
1957 1918 
 }
1958 1919
1959 1920 
 // BPL offset
1960 1921 
 static INSN_REGPARM void thumbD5(uint32_t opcode)
1961 1922 
 {
1962 
-  UPDATE_OLDREG;
1963 
-  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1964 
-  if(!N_FLAG) {
1965 
-    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
1966 
-    armNextPC = reg[15].I;
1967 
-    reg[15].I += 2;
1968 
-    THUMB_PREFETCH;
1969 
-    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1970 
-    busPrefetchCount=0;
1971 
-  }
1923 
+	clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1924 
+	if (!N_FLAG)
1925 
+	{
1926 
+		reg[15].I += static_cast<int8_t>(opcode & 0xFF) << 1;
1927 
+		armNextPC = reg[15].I;
1928 
+		reg[15].I += 2;
1929 
+		THUMB_PREFETCH();
1930 
+		clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1931 
+		busPrefetchCount = 0;
1932 
+	}
1972 1933 
 }
1973 1934
1974 1935 
 // BVS offset
1975 1936 
 static INSN_REGPARM void thumbD6(uint32_t opcode)
1976 1937 
 {
1977 
-  UPDATE_OLDREG;
1978 
-  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1979 
-  if(V_FLAG) {
1980 
-    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
1981 
-    armNextPC = reg[15].I;
1982 
-    reg[15].I += 2;
1983 
-    THUMB_PREFETCH;
1984 
-    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1985 
-    busPrefetchCount=0;
1986 
-  }
1938 
+	clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1939 
+	if (V_FLAG)
1940 
+	{
1941 
+		reg[15].I += static_cast<int8_t>(opcode & 0xFF) << 1;
1942 
+		armNextPC = reg[15].I;
1943 
+		reg[15].I += 2;
1944 
+		THUMB_PREFETCH();
1945 
+		clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1946 
+		busPrefetchCount = 0;
1947 
+	}
1987 1948 
 }
1988 1949
1989 1950 
 // BVC offset
1990 1951 
 static INSN_REGPARM void thumbD7(uint32_t opcode)
1991 1952 
 {
1992 
-  UPDATE_OLDREG;
1993 
-  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1994 
-  if(!V_FLAG) {
1995 
-    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
1996 
-    armNextPC = reg[15].I;
1997 
-    reg[15].I += 2;
1998 
-    THUMB_PREFETCH;
1999 
-    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
2000 
-    busPrefetchCount=0;
2001 
-  }
1953 
+	clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1954 
+	if (!V_FLAG)
1955 
+	{
1956 
+		reg[15].I += static_cast<int8_t>(opcode & 0xFF) << 1;
1957 
+		armNextPC = reg[15].I;
1958 
+		reg[15].I += 2;
1959 
+		THUMB_PREFETCH();
1960 
+		clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1961 
+		busPrefetchCount = 0;
1962 
+	}
2002 1963 
 }
2003 1964
2004 1965 
 // BHI offset
2005 1966 
 static INSN_REGPARM void thumbD8(uint32_t opcode)
2006 1967 
 {
2007 
-  UPDATE_OLDREG;
2008 
-  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2009 
-  if(C_FLAG && !Z_FLAG) {
2010 
-    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
2011 
-    armNextPC = reg[15].I;
2012 
-    reg[15].I += 2;
2013 
-    THUMB_PREFETCH;
2014 
-    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
2015 
-    busPrefetchCount=0;
2016 
-  }
1968 
+	clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1969 
+	if (C_FLAG && !Z_FLAG)
1970 
+	{
1971 
+		reg[15].I += static_cast<int8_t>(opcode & 0xFF) << 1;
1972 
+		armNextPC = reg[15].I;
1973 
+		reg[15].I += 2;
1974 
+		THUMB_PREFETCH();
1975 
+		clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1976 
+		busPrefetchCount = 0;
1977 
+	}
2017 1978 
 }
2018 1979
2019 1980 
 // BLS offset
2020 1981 
 static INSN_REGPARM void thumbD9(uint32_t opcode)
2021 1982 
 {
2022 
-  UPDATE_OLDREG;
2023 
-  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2024 
-  if(!C_FLAG || Z_FLAG) {
2025 
-    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
2026 
-    armNextPC = reg[15].I;
2027 
-    reg[15].I += 2;
2028 
-    THUMB_PREFETCH;
2029 
-    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
2030 
-    busPrefetchCount=0;
2031 
-  }
1983 
+	clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1984 
+	if (!C_FLAG || Z_FLAG)
1985 
+	{
1986 
+		reg[15].I += static_cast<int8_t>(opcode & 0xFF) << 1;
1987 
+		armNextPC = reg[15].I;
1988 
+		reg[15].I += 2;
1989 
+		THUMB_PREFETCH();
1990 
+		clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1991 
+		busPrefetchCount = 0;
1992 
+	}
2032 1993 
 }
2033 1994
2034 1995 
 // BGE offset
2035 1996 
 static INSN_REGPARM void thumbDA(uint32_t opcode)
2036 1997 
 {
2037 
-  UPDATE_OLDREG;
2038 
-  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2039 
-  if(N_FLAG == V_FLAG) {
2040 
-    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
2041 
-    armNextPC = reg[15].I;
2042 
-    reg[15].I += 2;
2043 
-    THUMB_PREFETCH;
2044 
-    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
2045 
-    busPrefetchCount=0;
2046 
-  }
1998 
+	clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1999 
+	if (N_FLAG == V_FLAG)
2000 
+	{
2001 
+		reg[15].I += static_cast<int8_t>(opcode & 0xFF) << 1;
2002 
+		armNextPC = reg[15].I;
2003 
+		reg[15].I += 2;
2004 
+		THUMB_PREFETCH();
2005 
+		clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
2006 
+		busPrefetchCount = 0;
2007 
+	}
2047 2008 
 }
2048 2009
2049 2010 
 // BLT offset
2050 2011 
 static INSN_REGPARM void thumbDB(uint32_t opcode)
2051 2012 
 {
2052 
-  UPDATE_OLDREG;
2053 
-  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2054 
-  if(N_FLAG != V_FLAG) {
2055 
-    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
2056 
-    armNextPC = reg[15].I;
2057 
-    reg[15].I += 2;
2058 
-    THUMB_PREFETCH;
2059 
-    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
2060 
-    busPrefetchCount=0;
2061 
-  }
2013 
+	clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2014 
+	if (N_FLAG != V_FLAG)
2015 
+	{
2016 
+		reg[15].I += static_cast<int8_t>(opcode & 0xFF) << 1;
2017 
+		armNextPC = reg[15].I;
2018 
+		reg[15].I += 2;
2019 
+		THUMB_PREFETCH();
2020 
+		clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
2021 
+		busPrefetchCount = 0;
2022 
+	}
2062 2023 
 }
2063 2024
2064 2025 
 // BGT offset
2065 2026 
 static INSN_REGPARM void thumbDC(uint32_t opcode)
2066 2027 
 {
2067 
-  UPDATE_OLDREG;
2068 
-  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2069 
-  if(!Z_FLAG && (N_FLAG == V_FLAG)) {
2070 
-    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
2071 
-    armNextPC = reg[15].I;
2072 
-    reg[15].I += 2;
2073 
-    THUMB_PREFETCH;
2074 
-    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
2075 
-    busPrefetchCount=0;
2076 
-  }
2028 
+	clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2029 
+	if (!Z_FLAG && N_FLAG == V_FLAG)
2030 
+	{
2031 
+		reg[15].I += static_cast<int8_t>(opcode & 0xFF) << 1;
2032 
+		armNextPC = reg[15].I;
2033 
+		reg[15].I += 2;
2034 
+		THUMB_PREFETCH();
2035 
+		clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
2036 
+		busPrefetchCount = 0;
2037 
+	}
2077 2038 
 }
2078 2039
2079 2040 
 // BLE offset
2080 2041 
 static INSN_REGPARM void thumbDD(uint32_t opcode)
2081 2042 
 {
2082 
-  UPDATE_OLDREG;
2083 
-  clockTicks = codeTicksAccessSeq16(armNextPC);
2084 
-  if(Z_FLAG || (N_FLAG != V_FLAG)) {
2085 
-    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
2086 
-    armNextPC = reg[15].I;
2087 
-    reg[15].I += 2;
2088 
-    THUMB_PREFETCH;
2089 
-    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
2090 
-    busPrefetchCount=0;
2091 
-  }
2043 
+	clockTicks = codeTicksAccessSeq16(armNextPC);
2044 
+	if (Z_FLAG || N_FLAG != V_FLAG)
2045 
+	{
2046 
+		reg[15].I += static_cast<int8_t>(opcode & 0xFF) << 1;
2047 
+		armNextPC = reg[15].I;
2048 
+		reg[15].I += 2;
2049 
+		THUMB_PREFETCH();
2050 
+		clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
2051 
+		busPrefetchCount = 0;
2052 
+	}
2092 2053 
 }
2093 2054
2094 2055 
 // SWI, B, BL /////////////////////////////////////////////////////////////
... ... 
@@ -2096,235 +2057,219 @@ static INSN_REGPARM void thumbDD(uint32_t opcode)
2096 2057 
 // SWI #comment
2097 2058 
 static INSN_REGPARM void thumbDF(uint32_t opcode)
2098 2059 
 {
2099 
-  uint32_t address = 0;
2100 
-  //clockTicks = codeTicksAccessSeq16(address)*2 + codeTicksAccess16(address)+3;
2101 
-  clockTicks = 3;
2102 
-  busPrefetchCount=0;
2103 
-  CPUSoftwareInterrupt(opcode & 0xFF);
2060 
+	uint32_t address = 0;
2061 
+	clockTicks = 3;
2062 
+	busPrefetchCount = 0;
2063 
+	CPUSoftwareInterrupt(opcode & 0xFF);
2104 2064 
 }
2105 2065
2106 2066 
 // B offset
2107 2067 
 static INSN_REGPARM void thumbE0(uint32_t opcode)
2108 2068 
 {
2109 
-  int offset = (opcode & 0x3FF) << 1;
2110 
-  if(opcode & 0x0400)
2111 
-    offset |= 0xFFFFF800;
2112 
-  reg[15].I += offset;
2113 
-  armNextPC = reg[15].I;
2114 
-  reg[15].I += 2;
2115 
-  THUMB_PREFETCH;
2116 
-  clockTicks = codeTicksAccessSeq16(armNextPC)*2 + codeTicksAccess16(armNextPC)+3;
2117 
-  busPrefetchCount=0;
2069 
+	int offset = (opcode & 0x3FF) << 1;
2070 
+	if (opcode & 0x0400)
2071 
+		offset |= 0xFFFFF800;
2072 
+	reg[15].I += offset;
2073 
+	armNextPC = reg[15].I;
2074 
+	reg[15].I += 2;
2075 
+	THUMB_PREFETCH();
2076 
+	clockTicks = codeTicksAccessSeq16(armNextPC) * 2 + codeTicksAccess16(armNextPC) + 3;
2077 
+	busPrefetchCount = 0;
2118 2078 
 }
2119 2079
2120 2080 
 // BLL #offset (forward)
2121 2081 
 static INSN_REGPARM void thumbF0(uint32_t opcode)
2122 2082 
 {
2123 
-  int offset = (opcode & 0x7FF);
2124 
-  reg[14].I = reg[15].I + (offset << 12);
2125 
-  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2083 
+	int offset = opcode & 0x7FF;
2084 
+	reg[14].I = reg[15].I + (offset << 12);
2085 
+	clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2126 2086 
 }
2127 2087
2128 2088 
 // BLL #offset (backward)
2129 2089 
 static INSN_REGPARM void thumbF4(uint32_t opcode)
2130 2090 
 {
2131 
-  int offset = (opcode & 0x7FF);
2132 
-  reg[14].I = reg[15].I + ((offset << 12) | 0xFF800000);
2133 
-  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2091 
+	int offset = opcode & 0x7FF;
2092 
+	reg[14].I = reg[15].I + ((offset << 12) | 0xFF800000);
2093 
+	clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2134 2094 
 }
2135 2095
2136 2096 
 // BLH #offset
2137 2097 
 static INSN_REGPARM void thumbF8(uint32_t opcode)
2138 2098 
 {
2139 
-  int offset = (opcode & 0x7FF);
2140 
-  uint32_t temp = reg[15].I-2;
2141 
-  reg[15].I = (reg[14].I + (offset<<1))&0xFFFFFFFE;
2142 
-  armNextPC = reg[15].I;
2143 
-  reg[15].I += 2;
2144 
-  reg[14].I = temp|1;
2145 
-  THUMB_PREFETCH;
2146 
-  clockTicks = codeTicksAccessSeq16(armNextPC)*2 + codeTicksAccess16(armNextPC) + 3;
2147 
-  busPrefetchCount = 0;
2099 
+	int offset = opcode & 0x7FF;
2100 
+	uint32_t temp = reg[15].I - 2;
2101 
+	reg[15].I = (reg[14].I + (offset << 1)) & 0xFFFFFFFE;
2102 
+	armNextPC = reg[15].I;
2103 
+	reg[15].I += 2;
2104 
+	reg[14].I = temp | 1;
2105 
+	THUMB_PREFETCH();
2106 
+	clockTicks = codeTicksAccessSeq16(armNextPC) * 2 + codeTicksAccess16(armNextPC) + 3;
2107 
+	busPrefetchCount = 0;
2148 2108 
 }
2149 2109
2150 2110 
 // Instruction table //////////////////////////////////////////////////////
2151 2111
2152 2112 
 typedef INSN_REGPARM void (*insnfunc_t)(uint32_t opcode);
2153 2113 
 #define thumbUI thumbUnknownInsn
2154 
-#ifdef BKPT_SUPPORT
2155 
- #define thumbBP thumbBreakpoint
2156 
-#else
2157 
- #define thumbBP thumbUnknownInsn
2158 
-#endif
2159 
-static insnfunc_t thumbInsnTable[1024] = {
2160 
-  thumb00_00,thumb00_01,thumb00_02,thumb00_03,thumb00_04,thumb00_05,thumb00_06,thumb00_07,  // 00
2161 
-  thumb00_08,thumb00_09,thumb00_0A,thumb00_0B,thumb00_0C,thumb00_0D,thumb00_0E,thumb00_0F,
2162 
-  thumb00_10,thumb00_11,thumb00_12,thumb00_13,thumb00_14,thumb00_15,thumb00_16,thumb00_17,
2163 
-  thumb00_18,thumb00_19,thumb00_1A,thumb00_1B,thumb00_1C,thumb00_1D,thumb00_1E,thumb00_1F,
2164 
-  thumb08_00,thumb08_01,thumb08_02,thumb08_03,thumb08_04,thumb08_05,thumb08_06,thumb08_07,  // 08
2165 
-  thumb08_08,thumb08_09,thumb08_0A,thumb08_0B,thumb08_0C,thumb08_0D,thumb08_0E,thumb08_0F,
2166 
-  thumb08_10,thumb08_11,thumb08_12,thumb08_13,thumb08_14,thumb08_15,thumb08_16,thumb08_17,
2167 
-  thumb08_18,thumb08_19,thumb08_1A,thumb08_1B,thumb08_1C,thumb08_1D,thumb08_1E,thumb08_1F,
2168 
-  thumb10_00,thumb10_01,thumb10_02,thumb10_03,thumb10_04,thumb10_05,thumb10_06,thumb10_07,  // 10
2169 
-  thumb10_08,thumb10_09,thumb10_0A,thumb10_0B,thumb10_0C,thumb10_0D,thumb10_0E,thumb10_0F,
2170 
-  thumb10_10,thumb10_11,thumb10_12,thumb10_13,thumb10_14,thumb10_15,thumb10_16,thumb10_17,
2171 
-  thumb10_18,thumb10_19,thumb10_1A,thumb10_1B,thumb10_1C,thumb10_1D,thumb10_1E,thumb10_1F,
2172 
-  thumb18_0,thumb18_1,thumb18_2,thumb18_3,thumb18_4,thumb18_5,thumb18_6,thumb18_7,          // 18
2173 
-  thumb1A_0,thumb1A_1,thumb1A_2,thumb1A_3,thumb1A_4,thumb1A_5,thumb1A_6,thumb1A_7,
2174 
-  thumb1C_0,thumb1C_1,thumb1C_2,thumb1C_3,thumb1C_4,thumb1C_5,thumb1C_6,thumb1C_7,
2175 
-  thumb1E_0,thumb1E_1,thumb1E_2,thumb1E_3,thumb1E_4,thumb1E_5,thumb1E_6,thumb1E_7,
2176 
-  thumb20,thumb20,thumb20,thumb20,thumb21,thumb21,thumb21,thumb21,  // 20
2177 
-  thumb22,thumb22,thumb22,thumb22,thumb23,thumb23,thumb23,thumb23,
2178 
-  thumb24,thumb24,thumb24,thumb24,thumb25,thumb25,thumb25,thumb25,
2179 
-  thumb26,thumb26,thumb26,thumb26,thumb27,thumb27,thumb27,thumb27,
2180 
-  thumb28,thumb28,thumb28,thumb28,thumb29,thumb29,thumb29,thumb29,  // 28
2181 
-  thumb2A,thumb2A,thumb2A,thumb2A,thumb2B,thumb2B,thumb2B,thumb2B,
2182 
-  thumb2C,thumb2C,thumb2C,thumb2C,thumb2D,thumb2D,thumb2D,thumb2D,
2183 
-  thumb2E,thumb2E,thumb2E,thumb2E,thumb2F,thumb2F,thumb2F,thumb2F,
2184 
-  thumb30,thumb30,thumb30,thumb30,thumb31,thumb31,thumb31,thumb31,  // 30
2185 
-  thumb32,thumb32,thumb32,thumb32,thumb33,thumb33,thumb33,thumb33,
2186 
-  thumb34,thumb34,thumb34,thumb34,thumb35,thumb35,thumb35,thumb35,
2187 
-  thumb36,thumb36,thumb36,thumb36,thumb37,thumb37,thumb37,thumb37,
2188 
-  thumb38,thumb38,thumb38,thumb38,thumb39,thumb39,thumb39,thumb39,  // 38
2189 
-  thumb3A,thumb3A,thumb3A,thumb3A,thumb3B,thumb3B,thumb3B,thumb3B,
2190 
-  thumb3C,thumb3C,thumb3C,thumb3C,thumb3D,thumb3D,thumb3D,thumb3D,
2191 
-  thumb3E,thumb3E,thumb3E,thumb3E,thumb3F,thumb3F,thumb3F,thumb3F,
2192 
-  thumb40_0,thumb40_1,thumb40_2,thumb40_3,thumb41_0,thumb41_1,thumb41_2,thumb41_3,  // 40
2193 
-  thumb42_0,thumb42_1,thumb42_2,thumb42_3,thumb43_0,thumb43_1,thumb43_2,thumb43_3,
2194 
-  thumbUI,thumb44_1,thumb44_2,thumb44_3,thumbUI,thumb45_1,thumb45_2,thumb45_3,
2195 
-  thumb46_0,thumb46_1,thumb46_2,thumb46_3,thumb47,thumb47,thumbUI,thumbUI,
2196 
-  thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,  // 48
2197 
-  thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,
2198 
-  thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,
2199 
-  thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,
2200 
-  thumb50,thumb50,thumb50,thumb50,thumb50,thumb50,thumb50,thumb50,  // 50
2201 
-  thumb52,thumb52,thumb52,thumb52,thumb52,thumb52,thumb52,thumb52,
2202 
-  thumb54,thumb54,thumb54,thumb54,thumb54,thumb54,thumb54,thumb54,
2203 
-  thumb56,thumb56,thumb56,thumb56,thumb56,thumb56,thumb56,thumb56,
2204 
-  thumb58,thumb58,thumb58,thumb58,thumb58,thumb58,thumb58,thumb58,  // 58
2205 
-  thumb5A,thumb5A,thumb5A,thumb5A,thumb5A,thumb5A,thumb5A,thumb5A,
2206 
-  thumb5C,thumb5C,thumb5C,thumb5C,thumb5C,thumb5C,thumb5C,thumb5C,
2207 
-  thumb5E,thumb5E,thumb5E,thumb5E,thumb5E,thumb5E,thumb5E,thumb5E,
2208 
-  thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,  // 60
2209 
-  thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,
2210 
-  thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,
2211 
-  thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,
2212 
-  thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,  // 68
2213 
-  thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,
2214 
-  thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,
2215 
-  thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,
2216 
-  thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,  // 70
2217 
-  thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,
2218 
-  thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,
2219 
-  thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,
2220 
-  thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,  // 78
2221 
-  thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,
2222 
-  thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,
2223 
-  thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,
2224 
-  thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,  // 80
2225 
-  thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,
2226 
-  thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,
2227 
-  thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,
2228 
-  thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,  // 88
2229 
-  thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,
2230 
-  thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,
2231 
-  thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,
2232 
-  thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,  // 90
2233 
-  thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,
2234 
-  thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,
2235 
-  thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,
2236 
-  thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,  // 98
2237 
-  thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,
2238 
-  thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,
2239 
-  thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,
2240 
-  thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,  // A0
2241 
-  thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,
2242 
-  thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,
2243 
-  thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,
2244 
-  thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,  // A8
2245 
-  thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,
2246 
-  thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,
2247 
-  thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,
2248 
-  thumbB0,thumbB0,thumbB0,thumbB0,thumbUI,thumbUI,thumbUI,thumbUI,  // B0
2249 
-  thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,
2250 
-  thumbB4,thumbB4,thumbB4,thumbB4,thumbB5,thumbB5,thumbB5,thumbB5,
2251 
-  thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,
2252 
-  thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,  // B8
2253 
-  thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,
2254 
-  thumbBC,thumbBC,thumbBC,thumbBC,thumbBD,thumbBD,thumbBD,thumbBD,
2255 
-  thumbBP,thumbBP,thumbBP,thumbBP,thumbUI,thumbUI,thumbUI,thumbUI,
2256 
-  thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,  // C0
2257 
-  thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,
2258 
-  thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,
2259 
-  thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,
2260 
-  thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,  // C8
2261 
-  thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,
2262 
-  thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,
2263 
-  thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,
2264 
-  thumbD0,thumbD0,thumbD0,thumbD0,thumbD1,thumbD1,thumbD1,thumbD1,  // D0
2265 
-  thumbD2,thumbD2,thumbD2,thumbD2,thumbD3,thumbD3,thumbD3,thumbD3,
2266 
-  thumbD4,thumbD4,thumbD4,thumbD4,thumbD5,thumbD5,thumbD5,thumbD5,
2267 
-  thumbD6,thumbD6,thumbD6,thumbD6,thumbD7,thumbD7,thumbD7,thumbD7,
2268 
-  thumbD8,thumbD8,thumbD8,thumbD8,thumbD9,thumbD9,thumbD9,thumbD9,  // D8
2269 
-  thumbDA,thumbDA,thumbDA,thumbDA,thumbDB,thumbDB,thumbDB,thumbDB,
2270 
-  thumbDC,thumbDC,thumbDC,thumbDC,thumbDD,thumbDD,thumbDD,thumbDD,
2271 
-  thumbUI,thumbUI,thumbUI,thumbUI,thumbDF,thumbDF,thumbDF,thumbDF,
2272 
-  thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,  // E0
2273 
-  thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,
2274 
-  thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,
2275 
-  thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,
2276 
-  thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,  // E8
2277 
-  thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,
2278 
-  thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,
2279 
-  thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,
2280 
-  thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,  // F0
2281 
-  thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,
2282 
-  thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,
2283 
-  thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,
2284 
-  thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,  // F8
2285 
-  thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,
2286 
-  thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,
2287 
-  thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,
2114 
+#define thumbBP thumbUnknownInsn
2115 
+static insnfunc_t thumbInsnTable[] =
2116 
+{
2117 
+	thumb00_00,thumb00_01,thumb00_02,thumb00_03,thumb00_04,thumb00_05,thumb00_06,thumb00_07,  // 00
2118 
+	thumb00_08,thumb00_09,thumb00_0A,thumb00_0B,thumb00_0C,thumb00_0D,thumb00_0E,thumb00_0F,
2119 
+	thumb00_10,thumb00_11,thumb00_12,thumb00_13,thumb00_14,thumb00_15,thumb00_16,thumb00_17,
2120 
+	thumb00_18,thumb00_19,thumb00_1A,thumb00_1B,thumb00_1C,thumb00_1D,thumb00_1E,thumb00_1F,
2121 
+	thumb08_00,thumb08_01,thumb08_02,thumb08_03,thumb08_04,thumb08_05,thumb08_06,thumb08_07,  // 08
2122 
+	thumb08_08,thumb08_09,thumb08_0A,thumb08_0B,thumb08_0C,thumb08_0D,thumb08_0E,thumb08_0F,
2123 
+	thumb08_10,thumb08_11,thumb08_12,thumb08_13,thumb08_14,thumb08_15,thumb08_16,thumb08_17,
2124 
+	thumb08_18,thumb08_19,thumb08_1A,thumb08_1B,thumb08_1C,thumb08_1D,thumb08_1E,thumb08_1F,
2125 
+	thumb10_00,thumb10_01,thumb10_02,thumb10_03,thumb10_04,thumb10_05,thumb10_06,thumb10_07,  // 10
2126 
+	thumb10_08,thumb10_09,thumb10_0A,thumb10_0B,thumb10_0C,thumb10_0D,thumb10_0E,thumb10_0F,
2127 
+	thumb10_10,thumb10_11,thumb10_12,thumb10_13,thumb10_14,thumb10_15,thumb10_16,thumb10_17,
2128 
+	thumb10_18,thumb10_19,thumb10_1A,thumb10_1B,thumb10_1C,thumb10_1D,thumb10_1E,thumb10_1F,
2129 
+	thumb18_0,thumb18_1,thumb18_2,thumb18_3,thumb18_4,thumb18_5,thumb18_6,thumb18_7,          // 18
2130 
+	thumb1A_0,thumb1A_1,thumb1A_2,thumb1A_3,thumb1A_4,thumb1A_5,thumb1A_6,thumb1A_7,
2131 
+	thumb1C_0,thumb1C_1,thumb1C_2,thumb1C_3,thumb1C_4,thumb1C_5,thumb1C_6,thumb1C_7,
2132 
+	thumb1E_0,thumb1E_1,thumb1E_2,thumb1E_3,thumb1E_4,thumb1E_5,thumb1E_6,thumb1E_7,
2133 
+	thumb20,thumb20,thumb20,thumb20,thumb21,thumb21,thumb21,thumb21,  // 20
2134 
+	thumb22,thumb22,thumb22,thumb22,thumb23,thumb23,thumb23,thumb23,
2135 
+	thumb24,thumb24,thumb24,thumb24,thumb25,thumb25,thumb25,thumb25,
2136 
+	thumb26,thumb26,thumb26,thumb26,thumb27,thumb27,thumb27,thumb27,
2137 
+	thumb28,thumb28,thumb28,thumb28,thumb29,thumb29,thumb29,thumb29,  // 28
2138 
+	thumb2A,thumb2A,thumb2A,thumb2A,thumb2B,thumb2B,thumb2B,thumb2B,
2139 
+	thumb2C,thumb2C,thumb2C,thumb2C,thumb2D,thumb2D,thumb2D,thumb2D,
2140 
+	thumb2E,thumb2E,thumb2E,thumb2E,thumb2F,thumb2F,thumb2F,thumb2F,
2141 
+	thumb30,thumb30,thumb30,thumb30,thumb31,thumb31,thumb31,thumb31,  // 30
2142 
+	thumb32,thumb32,thumb32,thumb32,thumb33,thumb33,thumb33,thumb33,
2143 
+	thumb34,thumb34,thumb34,thumb34,thumb35,thumb35,thumb35,thumb35,
2144 
+	thumb36,thumb36,thumb36,thumb36,thumb37,thumb37,thumb37,thumb37,
2145 
+	thumb38,thumb38,thumb38,thumb38,thumb39,thumb39,thumb39,thumb39,  // 38
2146 
+	thumb3A,thumb3A,thumb3A,thumb3A,thumb3B,thumb3B,thumb3B,thumb3B,
2147 
+	thumb3C,thumb3C,thumb3C,thumb3C,thumb3D,thumb3D,thumb3D,thumb3D,
2148 
+	thumb3E,thumb3E,thumb3E,thumb3E,thumb3F,thumb3F,thumb3F,thumb3F,
2149 
+	thumb40_0,thumb40_1,thumb40_2,thumb40_3,thumb41_0,thumb41_1,thumb41_2,thumb41_3,  // 40
2150 
+	thumb42_0,thumb42_1,thumb42_2,thumb42_3,thumb43_0,thumb43_1,thumb43_2,thumb43_3,
2151 
+	thumbUI,thumb44_1,thumb44_2,thumb44_3,thumbUI,thumb45_1,thumb45_2,thumb45_3,
2152 
+	thumb46_0,thumb46_1,thumb46_2,thumb46_3,thumb47,thumb47,thumbUI,thumbUI,
2153 
+	thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,  // 48
2154 
+	thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,
2155 
+	thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,
2156 
+	thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,
2157 
+	thumb50,thumb50,thumb50,thumb50,thumb50,thumb50,thumb50,thumb50,  // 50
2158 
+	thumb52,thumb52,thumb52,thumb52,thumb52,thumb52,thumb52,thumb52,
2159 
+	thumb54,thumb54,thumb54,thumb54,thumb54,thumb54,thumb54,thumb54,
2160 
+	thumb56,thumb56,thumb56,thumb56,thumb56,thumb56,thumb56,thumb56,
2161 
+	thumb58,thumb58,thumb58,thumb58,thumb58,thumb58,thumb58,thumb58,  // 58
2162 
+	thumb5A,thumb5A,thumb5A,thumb5A,thumb5A,thumb5A,thumb5A,thumb5A,
2163 
+	thumb5C,thumb5C,thumb5C,thumb5C,thumb5C,thumb5C,thumb5C,thumb5C,
2164 
+	thumb5E,thumb5E,thumb5E,thumb5E,thumb5E,thumb5E,thumb5E,thumb5E,
2165 
+	thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,  // 60
2166 
+	thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,
2167 
+	thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,
2168 
+	thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,
2169 
+	thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,  // 68
2170 
+	thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,
2171 
+	thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,
2172 
+	thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,
2173 
+	thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,  // 70
2174 
+	thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,
2175 
+	thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,
2176 
+	thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,
2177 
+	thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,  // 78
2178 
+	thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,
2179 
+	thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,
2180 
+	thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,
2181 
+	thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,  // 80
2182 
+	thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,
2183 
+	thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,
2184 
+	thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,
2185 
+	thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,  // 88
2186 
+	thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,
2187 
+	thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,
2188 
+	thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,
2189 
+	thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,  // 90
2190 
+	thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,
2191 
+	thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,
2192 
+	thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,
2193 
+	thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,  // 98
2194 
+	thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,
2195 
+	thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,
2196 
+	thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,
2197 
+	thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,  // A0
2198 
+	thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,
2199 
+	thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,
2200 
+	thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,
2201 
+	thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,  // A8
2202 
+	thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,
2203 
+	thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,
2204 
+	thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,
2205 
+	thumbB0,thumbB0,thumbB0,thumbB0,thumbUI,thumbUI,thumbUI,thumbUI,  // B0
2206 
+	thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,
2207 
+	thumbB4,thumbB4,thumbB4,thumbB4,thumbB5,thumbB5,thumbB5,thumbB5,
2208 
+	thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,
2209 
+	thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,  // B8
2210 
+	thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,
2211 
+	thumbBC,thumbBC,thumbBC,thumbBC,thumbBD,thumbBD,thumbBD,thumbBD,
2212 
+	thumbBP,thumbBP,thumbBP,thumbBP,thumbUI,thumbUI,thumbUI,thumbUI,
2213 
+	thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,  // C0
2214 
+	thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,
2215 
+	thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,
2216 
+	thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,
2217 
+	thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,  // C8
2218 
+	thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,
2219 
+	thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,
2220 
+	thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,
2221 
+	thumbD0,thumbD0,thumbD0,thumbD0,thumbD1,thumbD1,thumbD1,thumbD1,  // D0
2222 
+	thumbD2,thumbD2,thumbD2,thumbD2,thumbD3,thumbD3,thumbD3,thumbD3,
2223 
+	thumbD4,thumbD4,thumbD4,thumbD4,thumbD5,thumbD5,thumbD5,thumbD5,
2224 
+	thumbD6,thumbD6,thumbD6,thumbD6,thumbD7,thumbD7,thumbD7,thumbD7,
2225 
+	thumbD8,thumbD8,thumbD8,thumbD8,thumbD9,thumbD9,thumbD9,thumbD9,  // D8
2226 
+	thumbDA,thumbDA,thumbDA,thumbDA,thumbDB,thumbDB,thumbDB,thumbDB,
2227 
+	thumbDC,thumbDC,thumbDC,thumbDC,thumbDD,thumbDD,thumbDD,thumbDD,
2228 
+	thumbUI,thumbUI,thumbUI,thumbUI,thumbDF,thumbDF,thumbDF,thumbDF,
2229 
+	thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,  // E0
2230 
+	thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,
2231 
+	thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,
2232 
+	thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,
2233 
+	thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,  // E8
2234 
+	thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,
2235 
+	thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,
2236 
+	thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,
2237 
+	thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,  // F0
2238 
+	thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,
2239 
+	thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,
2240 
+	thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,
2241 
+	thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,  // F8
2242 
+	thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,
2243 
+	thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,
2244 
+	thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,
2288 2245 
 };
2289 2246
2290 2247 
 // Wrapper routine (execution loop) ///////////////////////////////////////
2291 2248
2292 2249 
 int thumbExecute()
2293 2250 
 {
2294 
-  do {
2295 
-	  /*if( cheatsEnabled ) {
2296 
-		  cpuMasterCodeCheck();
2297 
-	  }*/
2298 
-
2299 
-    //if ((armNextPC & 0x0803FFFF) == 0x08020000)
2300 
-    //    busPrefetchCount=0x100;
2301 
-
2302 
-    uint32_t opcode = cpuPrefetch[0];
2303 
-    cpuPrefetch[0] = cpuPrefetch[1];
2304 
-
2305 
-    busPrefetch = false;
2306 
-    if (busPrefetchCount & 0xFFFFFF00)
2307 
-      busPrefetchCount = 0x100 | (busPrefetchCount & 0xFF);
2308 
-    clockTicks = 0;
2309 
-    uint32_t oldArmNextPC = armNextPC;
2310 
-#ifndef FINAL_VERSION
2311 
-    if(armNextPC == stop) {
2312 
-      armNextPC++;
2313 
-    }
2314 
-#endif
2315 
-
2316 
-    armNextPC = reg[15].I;
2317 
-    reg[15].I += 2;
2318 
-    THUMB_PREFETCH_NEXT;
2319 
-
2320 
-    (*thumbInsnTable[opcode>>6])(opcode);
2321 
-
2322 
-    if (clockTicks < 0)
2323 
-      return 0;
2324 
-    if (clockTicks==0)
2325 
-      clockTicks = codeTicksAccessSeq16(oldArmNextPC) + 1;
2326 
-    cpuTotalTicks += clockTicks;
2327 
-
2328 
-  } while (cpuTotalTicks < cpuNextEvent && !armState && !holdState && !SWITicks);
2329 
-  return 1;
2251 
+	do
2252 
+	{
2253 
+		uint32_t opcode = cpuPrefetch[0];
2254 
+		cpuPrefetch[0] = cpuPrefetch[1];
2255 
+
2256 
+		busPrefetch = false;
2257 
+		if (busPrefetchCount & 0xFFFFFF00)
2258 
+			busPrefetchCount = 0x100 | (busPrefetchCount & 0xFF);
2259 
+		clockTicks = 0;
2260 
+		uint32_t oldArmNextPC = armNextPC;
2261 
+
2262 
+		armNextPC = reg[15].I;
2263 
+		reg[15].I += 2;
2264 
+		THUMB_PREFETCH_NEXT();
2265 
+
2266 
+		(*thumbInsnTable[opcode >> 6])(opcode);
2267 
+
2268 
+		if (clockTicks < 0)
2269 
+			return 0;
2270 
+		if (!clockTicks)
2271 
+			clockTicks = codeTicksAccessSeq16(oldArmNextPC) + 1;
2272 
+		cpuTotalTicks += clockTicks;
2273 
+	} while (cpuTotalTicks < cpuNextEvent && !armState && !holdState && !SWITicks);
2274 
+	return 1;
2330 2275 
 }
Browse code

[GSF] Cleanup, a tiny bit of making sure it was like viogsf, also used the standard integer types and not VBA-M's typedefs.

Naram Qashat authored on 2013/05/10 17:45:36
Showing 1 changed files
src/in_gsf/vbam/gba/GBA-thumb.cpp
History View file @ 58ead5d
... ... 
@@ -31,7 +31,7 @@
31 31
32 32 
 static int clockTicks;
33 33
34 
-static INSN_REGPARM void thumbUnknownInsn(u32 opcode)
34 
+static INSN_REGPARM void thumbUnknownInsn(uint32_t opcode)
35 35 
 {
36 36 
 #ifdef GBA_LOGGING
37 37 
   if(systemVerbose & VERBOSE_UNDEFINED)
... ... 
@@ -41,7 +41,7 @@ static INSN_REGPARM void thumbUnknownInsn(u32 opcode)
41 41 
 }
42 42
43 43 
 #ifdef BKPT_SUPPORT
44 
-static INSN_REGPARM void thumbBreakpoint(u32 opcode)
44 
+static INSN_REGPARM void thumbBreakpoint(uint32_t opcode)
45 45 
 {
46 46 
   reg[15].I -= 2;
47 47 
   armNextPC -= 2;
... ... 
@@ -745,9 +745,9 @@ static INSN_REGPARM void thumbBreakpoint(u32 opcode)
745 745 
 #ifndef ADD_RD_RS_RN
746 746 
  #define ADD_RD_RS_RN(N) \
747 747 
    {\
748 
-     u32 lhs = reg[source].I;\
749 
-     u32 rhs = reg[N].I;\
750 
-     u32 res = lhs + rhs;\
748 
+     uint32_t lhs = reg[source].I;\
749 
+     uint32_t rhs = reg[N].I;\
750 
+     uint32_t res = lhs + rhs;\
751 751 
      reg[dest].I = res;\
752 752 
      Z_FLAG = (res == 0) ? true : false;\
753 753 
      N_FLAG = NEG(res) ? true : false;\
... ... 
@@ -758,9 +758,9 @@ static INSN_REGPARM void thumbBreakpoint(u32 opcode)
758 758 
 #ifndef ADD_RD_RS_O3
759 759 
  #define ADD_RD_RS_O3(N) \
760 760 
    {\
761 
-     u32 lhs = reg[source].I;\
762 
-     u32 rhs = N;\
763 
-     u32 res = lhs + rhs;\
761 
+     uint32_t lhs = reg[source].I;\
762 
+     uint32_t rhs = N;\
763 
+     uint32_t res = lhs + rhs;\
764 764 
      reg[dest].I = res;\
765 765 
      Z_FLAG = (res == 0) ? true : false;\
766 766 
      N_FLAG = NEG(res) ? true : false;\
... ... 
@@ -774,9 +774,9 @@ static INSN_REGPARM void thumbBreakpoint(u32 opcode)
774 774 
 #ifndef ADD_RN_O8
775 775 
  #define ADD_RN_O8(d) \
776 776 
    {\
777 
-     u32 lhs = reg[(d)].I;\
778 
-     u32 rhs = (opcode & 255);\
779 
-     u32 res = lhs + rhs;\
777 
+     uint32_t lhs = reg[(d)].I;\
778 
+     uint32_t rhs = (opcode & 255);\
779 
+     uint32_t res = lhs + rhs;\
780 780 
      reg[(d)].I = res;\
781 781 
      Z_FLAG = (res == 0) ? true : false;\
782 782 
      N_FLAG = NEG(res) ? true : false;\
... ... 
@@ -787,9 +787,9 @@ static INSN_REGPARM void thumbBreakpoint(u32 opcode)
787 787 
 #ifndef CMN_RD_RS
788 788 
  #define CMN_RD_RS \
789 789 
    {\
790 
-     u32 lhs = reg[dest].I;\
791 
-     u32 rhs = value;\
792 
-     u32 res = lhs + rhs;\
790 
+     uint32_t lhs = reg[dest].I;\
791 
+     uint32_t rhs = value;\
792 
+     uint32_t res = lhs + rhs;\
793 793 
      Z_FLAG = (res == 0) ? true : false;\
794 794 
      N_FLAG = NEG(res) ? true : false;\
795 795 
      ADDCARRY(lhs, rhs, res);\
... ... 
@@ -799,9 +799,9 @@ static INSN_REGPARM void thumbBreakpoint(u32 opcode)
799 799 
 #ifndef ADC_RD_RS
800 800 
  #define ADC_RD_RS \
801 801 
    {\
802 
-     u32 lhs = reg[dest].I;\
803 
-     u32 rhs = value;\
804 
-     u32 res = lhs + rhs + (u32)C_FLAG;\
802 
+     uint32_t lhs = reg[dest].I;\
803 
+     uint32_t rhs = value;\
804 
+     uint32_t res = lhs + rhs + (uint32_t)C_FLAG;\
805 805 
      reg[dest].I = res;\
806 806 
      Z_FLAG = (res == 0) ? true : false;\
807 807 
      N_FLAG = NEG(res) ? true : false;\
... ... 
@@ -812,9 +812,9 @@ static INSN_REGPARM void thumbBreakpoint(u32 opcode)
812 812 
 #ifndef SUB_RD_RS_RN
813 813 
  #define SUB_RD_RS_RN(N) \
814 814 
    {\
815 
-     u32 lhs = reg[source].I;\
816 
-     u32 rhs = reg[N].I;\
817 
-     u32 res = lhs - rhs;\
815 
+     uint32_t lhs = reg[source].I;\
816 
+     uint32_t rhs = reg[N].I;\
817 
+     uint32_t res = lhs - rhs;\
818 818 
      reg[dest].I = res;\
819 819 
      Z_FLAG = (res == 0) ? true : false;\
820 820 
      N_FLAG = NEG(res) ? true : false;\
... ... 
@@ -825,9 +825,9 @@ static INSN_REGPARM void thumbBreakpoint(u32 opcode)
825 825 
 #ifndef SUB_RD_RS_O3
826 826 
  #define SUB_RD_RS_O3(N) \
827 827 
    {\
828 
-     u32 lhs = reg[source].I;\
829 
-     u32 rhs = N;\
830 
-     u32 res = lhs - rhs;\
828 
+     uint32_t lhs = reg[source].I;\
829 
+     uint32_t rhs = N;\
830 
+     uint32_t res = lhs - rhs;\
831 831 
      reg[dest].I = res;\
832 832 
      Z_FLAG = (res == 0) ? true : false;\
833 833 
      N_FLAG = NEG(res) ? true : false;\
... ... 
@@ -841,9 +841,9 @@ static INSN_REGPARM void thumbBreakpoint(u32 opcode)
841 841 
 #ifndef SUB_RN_O8
842 842 
  #define SUB_RN_O8(d) \
843 843 
    {\
844 
-     u32 lhs = reg[(d)].I;\
845 
-     u32 rhs = (opcode & 255);\
846 
-     u32 res = lhs - rhs;\
844 
+     uint32_t lhs = reg[(d)].I;\
845 
+     uint32_t rhs = (opcode & 255);\
846 
+     uint32_t res = lhs - rhs;\
847 847 
      reg[(d)].I = res;\
848 848 
      Z_FLAG = (res == 0) ? true : false;\
849 849 
      N_FLAG = NEG(res) ? true : false;\
... ... 
@@ -862,9 +862,9 @@ static INSN_REGPARM void thumbBreakpoint(u32 opcode)
862 862 
 #ifndef CMP_RN_O8
863 863 
  #define CMP_RN_O8(d) \
864 864 
    {\
865 
-     u32 lhs = reg[(d)].I;\
866 
-     u32 rhs = (opcode & 255);\
867 
-     u32 res = lhs - rhs;\
865 
+     uint32_t lhs = reg[(d)].I;\
866 
+     uint32_t rhs = (opcode & 255);\
867 
+     uint32_t res = lhs - rhs;\
868 868 
      Z_FLAG = (res == 0) ? true : false;\
869 869 
      N_FLAG = NEG(res) ? true : false;\
870 870 
      SUBCARRY(lhs, rhs, res);\
... ... 
@@ -874,9 +874,9 @@ static INSN_REGPARM void thumbBreakpoint(u32 opcode)
874 874 
 #ifndef SBC_RD_RS
875 875 
  #define SBC_RD_RS \
876 876 
    {\
877 
-     u32 lhs = reg[dest].I;\
878 
-     u32 rhs = value;\
879 
-     u32 res = lhs - rhs - !((u32)C_FLAG);\
877 
+     uint32_t lhs = reg[dest].I;\
878 
+     uint32_t rhs = value;\
879 
+     uint32_t res = lhs - rhs - !((uint32_t)C_FLAG);\
880 880 
      reg[dest].I = res;\
881 881 
      Z_FLAG = (res == 0) ? true : false;\
882 882 
      N_FLAG = NEG(res) ? true : false;\
... ... 
@@ -915,15 +915,15 @@ static INSN_REGPARM void thumbBreakpoint(u32 opcode)
915 915 
 #ifndef ASR_RD_RM_I5
916 916 
  #define ASR_RD_RM_I5 \
917 917 
    {\
918 
-     C_FLAG = ((s32)reg[source].I >> (int)(shift - 1)) & 1 ? true : false;\
919 
-     value = (s32)reg[source].I >> (int)shift;\
918 
+     C_FLAG = ((int32_t)reg[source].I >> (int)(shift - 1)) & 1 ? true : false;\
919 
+     value = (int32_t)reg[source].I >> (int)shift;\
920 920 
    }
921 921 
 #endif
922 922 
 #ifndef ASR_RD_RS
923 923 
  #define ASR_RD_RS \
924 924 
    {\
925 
-     C_FLAG = ((s32)reg[dest].I >> (int)(value - 1)) & 1 ? true : false;\
926 
-     value = (s32)reg[dest].I >> (int)value;\
925 
+     C_FLAG = ((int32_t)reg[dest].I >> (int)(value - 1)) & 1 ? true : false;\
926 
+     value = (int32_t)reg[dest].I >> (int)value;\
927 927 
    }
928 928 
 #endif
929 929 
 #ifndef ROR_RD_RS
... ... 
@@ -937,9 +937,9 @@ static INSN_REGPARM void thumbBreakpoint(u32 opcode)
937 937 
 #ifndef NEG_RD_RS
938 938 
  #define NEG_RD_RS \
939 939 
    {\
940 
-     u32 lhs = reg[source].I;\
941 
-     u32 rhs = 0;\
942 
-     u32 res = rhs - lhs;\
940 
+     uint32_t lhs = reg[source].I;\
941 
+     uint32_t rhs = 0;\
942 
+     uint32_t res = rhs - lhs;\
943 943 
      reg[dest].I = res;\
944 944 
      Z_FLAG = (res == 0) ? true : false;\
945 945 
      N_FLAG = NEG(res) ? true : false;\
... ... 
@@ -950,9 +950,9 @@ static INSN_REGPARM void thumbBreakpoint(u32 opcode)
950 950 
 #ifndef CMP_RD_RS
951 951 
  #define CMP_RD_RS \
952 952 
    {\
953 
-     u32 lhs = reg[dest].I;\
954 
-     u32 rhs = value;\
955 
-     u32 res = lhs - rhs;\
953 
+     uint32_t lhs = reg[dest].I;\
954 
+     uint32_t rhs = value;\
955 
+     uint32_t res = lhs - rhs;\
956 956 
      Z_FLAG = (res == 0) ? true : false;\
957 957 
      N_FLAG = NEG(res) ? true : false;\
958 958 
      SUBCARRY(lhs, rhs, res);\
... ... 
@@ -963,7 +963,7 @@ static INSN_REGPARM void thumbBreakpoint(u32 opcode)
963 963 
  #define IMM5_INSN(OP,N) \
964 964 
   int dest = opcode & 0x07;\
965 965 
   int source = (opcode >> 3) & 0x07;\
966 
-  u32 value;\
966 
+  uint32_t value;\
967 967 
   OP(N);\
968 968 
   reg[dest].I = value;\
969 969 
   N_FLAG = (value & 0x80000000 ? true : false);\
... ... 
@@ -971,7 +971,7 @@ static INSN_REGPARM void thumbBreakpoint(u32 opcode)
971 971 
  #define IMM5_INSN_0(OP) \
972 972 
   int dest = opcode & 0x07;\
973 973 
   int source = (opcode >> 3) & 0x07;\
974 
-  u32 value;\
974 
+  uint32_t value;\
975 975 
   OP;\
976 976 
   reg[dest].I = value;\
977 977 
   N_FLAG = (value & 0x80000000 ? true : false);\
... ... 
@@ -1009,38 +1009,38 @@ static INSN_REGPARM void thumbBreakpoint(u32 opcode)
1009 1009 
 // Shift instructions /////////////////////////////////////////////////////
1010 1010
1011 1011 
 #define DEFINE_IMM5_INSN(OP,BASE) \
1012 
-  static INSN_REGPARM void thumb##BASE##_00(u32 opcode) { IMM5_INSN_0(OP##_0); } \
1013 
-  static INSN_REGPARM void thumb##BASE##_01(u32 opcode) { IMM5_INSN(OP, 1); } \
1014 
-  static INSN_REGPARM void thumb##BASE##_02(u32 opcode) { IMM5_INSN(OP, 2); } \
1015 
-  static INSN_REGPARM void thumb##BASE##_03(u32 opcode) { IMM5_INSN(OP, 3); } \
1016 
-  static INSN_REGPARM void thumb##BASE##_04(u32 opcode) { IMM5_INSN(OP, 4); } \
1017 
-  static INSN_REGPARM void thumb##BASE##_05(u32 opcode) { IMM5_INSN(OP, 5); } \
1018 
-  static INSN_REGPARM void thumb##BASE##_06(u32 opcode) { IMM5_INSN(OP, 6); } \
1019 
-  static INSN_REGPARM void thumb##BASE##_07(u32 opcode) { IMM5_INSN(OP, 7); } \
1020 
-  static INSN_REGPARM void thumb##BASE##_08(u32 opcode) { IMM5_INSN(OP, 8); } \
1021 
-  static INSN_REGPARM void thumb##BASE##_09(u32 opcode) { IMM5_INSN(OP, 9); } \
1022 
-  static INSN_REGPARM void thumb##BASE##_0A(u32 opcode) { IMM5_INSN(OP,10); } \
1023 
-  static INSN_REGPARM void thumb##BASE##_0B(u32 opcode) { IMM5_INSN(OP,11); } \
1024 
-  static INSN_REGPARM void thumb##BASE##_0C(u32 opcode) { IMM5_INSN(OP,12); } \
1025 
-  static INSN_REGPARM void thumb##BASE##_0D(u32 opcode) { IMM5_INSN(OP,13); } \
1026 
-  static INSN_REGPARM void thumb##BASE##_0E(u32 opcode) { IMM5_INSN(OP,14); } \
1027 
-  static INSN_REGPARM void thumb##BASE##_0F(u32 opcode) { IMM5_INSN(OP,15); } \
1028 
-  static INSN_REGPARM void thumb##BASE##_10(u32 opcode) { IMM5_INSN(OP,16); } \
1029 
-  static INSN_REGPARM void thumb##BASE##_11(u32 opcode) { IMM5_INSN(OP,17); } \
1030 
-  static INSN_REGPARM void thumb##BASE##_12(u32 opcode) { IMM5_INSN(OP,18); } \
1031 
-  static INSN_REGPARM void thumb##BASE##_13(u32 opcode) { IMM5_INSN(OP,19); } \
1032 
-  static INSN_REGPARM void thumb##BASE##_14(u32 opcode) { IMM5_INSN(OP,20); } \
1033 
-  static INSN_REGPARM void thumb##BASE##_15(u32 opcode) { IMM5_INSN(OP,21); } \
1034 
-  static INSN_REGPARM void thumb##BASE##_16(u32 opcode) { IMM5_INSN(OP,22); } \
1035 
-  static INSN_REGPARM void thumb##BASE##_17(u32 opcode) { IMM5_INSN(OP,23); } \
1036 
-  static INSN_REGPARM void thumb##BASE##_18(u32 opcode) { IMM5_INSN(OP,24); } \
1037 
-  static INSN_REGPARM void thumb##BASE##_19(u32 opcode) { IMM5_INSN(OP,25); } \
1038 
-  static INSN_REGPARM void thumb##BASE##_1A(u32 opcode) { IMM5_INSN(OP,26); } \
1039 
-  static INSN_REGPARM void thumb##BASE##_1B(u32 opcode) { IMM5_INSN(OP,27); } \
1040 
-  static INSN_REGPARM void thumb##BASE##_1C(u32 opcode) { IMM5_INSN(OP,28); } \
1041 
-  static INSN_REGPARM void thumb##BASE##_1D(u32 opcode) { IMM5_INSN(OP,29); } \
1042 
-  static INSN_REGPARM void thumb##BASE##_1E(u32 opcode) { IMM5_INSN(OP,30); } \
1043 
-  static INSN_REGPARM void thumb##BASE##_1F(u32 opcode) { IMM5_INSN(OP,31); }
1012 
+  static INSN_REGPARM void thumb##BASE##_00(uint32_t opcode) { IMM5_INSN_0(OP##_0); } \
1013 
+  static INSN_REGPARM void thumb##BASE##_01(uint32_t opcode) { IMM5_INSN(OP, 1); } \
1014 
+  static INSN_REGPARM void thumb##BASE##_02(uint32_t opcode) { IMM5_INSN(OP, 2); } \
1015 
+  static INSN_REGPARM void thumb##BASE##_03(uint32_t opcode) { IMM5_INSN(OP, 3); } \
1016 
+  static INSN_REGPARM void thumb##BASE##_04(uint32_t opcode) { IMM5_INSN(OP, 4); } \
1017 
+  static INSN_REGPARM void thumb##BASE##_05(uint32_t opcode) { IMM5_INSN(OP, 5); } \
1018 
+  static INSN_REGPARM void thumb##BASE##_06(uint32_t opcode) { IMM5_INSN(OP, 6); } \
1019 
+  static INSN_REGPARM void thumb##BASE##_07(uint32_t opcode) { IMM5_INSN(OP, 7); } \
1020 
+  static INSN_REGPARM void thumb##BASE##_08(uint32_t opcode) { IMM5_INSN(OP, 8); } \
1021 
+  static INSN_REGPARM void thumb##BASE##_09(uint32_t opcode) { IMM5_INSN(OP, 9); } \
1022 
+  static INSN_REGPARM void thumb##BASE##_0A(uint32_t opcode) { IMM5_INSN(OP,10); } \
1023 
+  static INSN_REGPARM void thumb##BASE##_0B(uint32_t opcode) { IMM5_INSN(OP,11); } \
1024 
+  static INSN_REGPARM void thumb##BASE##_0C(uint32_t opcode) { IMM5_INSN(OP,12); } \
1025 
+  static INSN_REGPARM void thumb##BASE##_0D(uint32_t opcode) { IMM5_INSN(OP,13); } \
1026 
+  static INSN_REGPARM void thumb##BASE##_0E(uint32_t opcode) { IMM5_INSN(OP,14); } \
1027 
+  static INSN_REGPARM void thumb##BASE##_0F(uint32_t opcode) { IMM5_INSN(OP,15); } \
1028 
+  static INSN_REGPARM void thumb##BASE##_10(uint32_t opcode) { IMM5_INSN(OP,16); } \
1029 
+  static INSN_REGPARM void thumb##BASE##_11(uint32_t opcode) { IMM5_INSN(OP,17); } \
1030 
+  static INSN_REGPARM void thumb##BASE##_12(uint32_t opcode) { IMM5_INSN(OP,18); } \
1031 
+  static INSN_REGPARM void thumb##BASE##_13(uint32_t opcode) { IMM5_INSN(OP,19); } \
1032 
+  static INSN_REGPARM void thumb##BASE##_14(uint32_t opcode) { IMM5_INSN(OP,20); } \
1033 
+  static INSN_REGPARM void thumb##BASE##_15(uint32_t opcode) { IMM5_INSN(OP,21); } \
1034 
+  static INSN_REGPARM void thumb##BASE##_16(uint32_t opcode) { IMM5_INSN(OP,22); } \
1035 
+  static INSN_REGPARM void thumb##BASE##_17(uint32_t opcode) { IMM5_INSN(OP,23); } \
1036 
+  static INSN_REGPARM void thumb##BASE##_18(uint32_t opcode) { IMM5_INSN(OP,24); } \
1037 
+  static INSN_REGPARM void thumb##BASE##_19(uint32_t opcode) { IMM5_INSN(OP,25); } \
1038 
+  static INSN_REGPARM void thumb##BASE##_1A(uint32_t opcode) { IMM5_INSN(OP,26); } \
1039 
+  static INSN_REGPARM void thumb##BASE##_1B(uint32_t opcode) { IMM5_INSN(OP,27); } \
1040 
+  static INSN_REGPARM void thumb##BASE##_1C(uint32_t opcode) { IMM5_INSN(OP,28); } \
1041 
+  static INSN_REGPARM void thumb##BASE##_1D(uint32_t opcode) { IMM5_INSN(OP,29); } \
1042 
+  static INSN_REGPARM void thumb##BASE##_1E(uint32_t opcode) { IMM5_INSN(OP,30); } \
1043 
+  static INSN_REGPARM void thumb##BASE##_1F(uint32_t opcode) { IMM5_INSN(OP,31); }
1044 1044
1045 1045 
 // LSL Rd, Rm, #Imm 5
1046 1046 
 DEFINE_IMM5_INSN(IMM5_LSL,00)
... ... 
@@ -1052,24 +1052,24 @@ DEFINE_IMM5_INSN(IMM5_ASR,10)
1052 1052 
 // 3-argument ADD/SUB /////////////////////////////////////////////////////
1053 1053
1054 1054 
 #define DEFINE_REG3_INSN(OP,BASE) \
1055 
-  static INSN_REGPARM void thumb##BASE##_0(u32 opcode) { THREEARG_INSN(OP,0); } \
1056 
-  static INSN_REGPARM void thumb##BASE##_1(u32 opcode) { THREEARG_INSN(OP,1); } \
1057 
-  static INSN_REGPARM void thumb##BASE##_2(u32 opcode) { THREEARG_INSN(OP,2); } \
1058 
-  static INSN_REGPARM void thumb##BASE##_3(u32 opcode) { THREEARG_INSN(OP,3); } \
1059 
-  static INSN_REGPARM void thumb##BASE##_4(u32 opcode) { THREEARG_INSN(OP,4); } \
1060 
-  static INSN_REGPARM void thumb##BASE##_5(u32 opcode) { THREEARG_INSN(OP,5); } \
1061 
-  static INSN_REGPARM void thumb##BASE##_6(u32 opcode) { THREEARG_INSN(OP,6); } \
1062 
-  static INSN_REGPARM void thumb##BASE##_7(u32 opcode) { THREEARG_INSN(OP,7); }
1055 
+  static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP,0); } \
1056 
+  static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP,1); } \
1057 
+  static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP,2); } \
1058 
+  static INSN_REGPARM void thumb##BASE##_3(uint32_t opcode) { THREEARG_INSN(OP,3); } \
1059 
+  static INSN_REGPARM void thumb##BASE##_4(uint32_t opcode) { THREEARG_INSN(OP,4); } \
1060 
+  static INSN_REGPARM void thumb##BASE##_5(uint32_t opcode) { THREEARG_INSN(OP,5); } \
1061 
+  static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP,6); } \
1062 
+  static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP,7); }
1063 1063
1064 1064 
 #define DEFINE_IMM3_INSN(OP,BASE) \
1065 
-  static INSN_REGPARM void thumb##BASE##_0(u32 opcode) { THREEARG_INSN(OP##_0,0); } \
1066 
-  static INSN_REGPARM void thumb##BASE##_1(u32 opcode) { THREEARG_INSN(OP,1); } \
1067 
-  static INSN_REGPARM void thumb##BASE##_2(u32 opcode) { THREEARG_INSN(OP,2); } \
1068 
-  static INSN_REGPARM void thumb##BASE##_3(u32 opcode) { THREEARG_INSN(OP,3); } \
1069 
-  static INSN_REGPARM void thumb##BASE##_4(u32 opcode) { THREEARG_INSN(OP,4); } \
1070 
-  static INSN_REGPARM void thumb##BASE##_5(u32 opcode) { THREEARG_INSN(OP,5); } \
1071 
-  static INSN_REGPARM void thumb##BASE##_6(u32 opcode) { THREEARG_INSN(OP,6); } \
1072 
-  static INSN_REGPARM void thumb##BASE##_7(u32 opcode) { THREEARG_INSN(OP,7); }
1065 
+  static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP##_0,0); } \
1066 
+  static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP,1); } \
1067 
+  static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP,2); } \
1068 
+  static INSN_REGPARM void thumb##BASE##_3(uint32_t opcode) { THREEARG_INSN(OP,3); } \
1069 
+  static INSN_REGPARM void thumb##BASE##_4(uint32_t opcode) { THREEARG_INSN(OP,4); } \
1070 
+  static INSN_REGPARM void thumb##BASE##_5(uint32_t opcode) { THREEARG_INSN(OP,5); } \
1071 
+  static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP,6); } \
1072 
+  static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP,7); }
1073 1073
1074 1074 
 // ADD Rd, Rs, Rn
1075 1075 
 DEFINE_REG3_INSN(ADD_RD_RS_RN,18)
... ... 
@@ -1083,77 +1083,77 @@ DEFINE_IMM3_INSN(SUB_RD_RS_O3,1E)
1083 1083 
 // MOV/CMP/ADD/SUB immediate //////////////////////////////////////////////
1084 1084
1085 1085 
 // MOV R0, #Offset8
1086 
-static INSN_REGPARM void thumb20(u32 opcode) { MOV_RN_O8(0); }
1086 
+static INSN_REGPARM void thumb20(uint32_t opcode) { MOV_RN_O8(0); }
1087 1087 
 // MOV R1, #Offset8
1088 
-static INSN_REGPARM void thumb21(u32 opcode) { MOV_RN_O8(1); }
1088 
+static INSN_REGPARM void thumb21(uint32_t opcode) { MOV_RN_O8(1); }
1089 1089 
 // MOV R2, #Offset8
1090 
-static INSN_REGPARM void thumb22(u32 opcode) { MOV_RN_O8(2); }
1090 
+static INSN_REGPARM void thumb22(uint32_t opcode) { MOV_RN_O8(2); }
1091 1091 
 // MOV R3, #Offset8
1092 
-static INSN_REGPARM void thumb23(u32 opcode) { MOV_RN_O8(3); }
1092 
+static INSN_REGPARM void thumb23(uint32_t opcode) { MOV_RN_O8(3); }
1093 1093 
 // MOV R4, #Offset8
1094 
-static INSN_REGPARM void thumb24(u32 opcode) { MOV_RN_O8(4); }
1094 
+static INSN_REGPARM void thumb24(uint32_t opcode) { MOV_RN_O8(4); }
1095 1095 
 // MOV R5, #Offset8
1096 
-static INSN_REGPARM void thumb25(u32 opcode) { MOV_RN_O8(5); }
1096 
+static INSN_REGPARM void thumb25(uint32_t opcode) { MOV_RN_O8(5); }
1097 1097 
 // MOV R6, #Offset8
1098 
-static INSN_REGPARM void thumb26(u32 opcode) { MOV_RN_O8(6); }
1098 
+static INSN_REGPARM void thumb26(uint32_t opcode) { MOV_RN_O8(6); }
1099 1099 
 // MOV R7, #Offset8
1100 
-static INSN_REGPARM void thumb27(u32 opcode) { MOV_RN_O8(7); }
1100 
+static INSN_REGPARM void thumb27(uint32_t opcode) { MOV_RN_O8(7); }
1101 1101
1102 1102 
 // CMP R0, #Offset8
1103 
-static INSN_REGPARM void thumb28(u32 opcode) { CMP_RN_O8(0); }
1103 
+static INSN_REGPARM void thumb28(uint32_t opcode) { CMP_RN_O8(0); }
1104 1104 
 // CMP R1, #Offset8
1105 
-static INSN_REGPARM void thumb29(u32 opcode) { CMP_RN_O8(1); }
1105 
+static INSN_REGPARM void thumb29(uint32_t opcode) { CMP_RN_O8(1); }
1106 1106 
 // CMP R2, #Offset8
1107 
-static INSN_REGPARM void thumb2A(u32 opcode) { CMP_RN_O8(2); }
1107 
+static INSN_REGPARM void thumb2A(uint32_t opcode) { CMP_RN_O8(2); }
1108 1108 
 // CMP R3, #Offset8
1109 
-static INSN_REGPARM void thumb2B(u32 opcode) { CMP_RN_O8(3); }
1109 
+static INSN_REGPARM void thumb2B(uint32_t opcode) { CMP_RN_O8(3); }
1110 1110 
 // CMP R4, #Offset8
1111 
-static INSN_REGPARM void thumb2C(u32 opcode) { CMP_RN_O8(4); }
1111 
+static INSN_REGPARM void thumb2C(uint32_t opcode) { CMP_RN_O8(4); }
1112 1112 
 // CMP R5, #Offset8
1113 
-static INSN_REGPARM void thumb2D(u32 opcode) { CMP_RN_O8(5); }
1113 
+static INSN_REGPARM void thumb2D(uint32_t opcode) { CMP_RN_O8(5); }
1114 1114 
 // CMP R6, #Offset8
1115 
-static INSN_REGPARM void thumb2E(u32 opcode) { CMP_RN_O8(6); }
1115 
+static INSN_REGPARM void thumb2E(uint32_t opcode) { CMP_RN_O8(6); }
1116 1116 
 // CMP R7, #Offset8
1117 
-static INSN_REGPARM void thumb2F(u32 opcode) { CMP_RN_O8(7); }
1117 
+static INSN_REGPARM void thumb2F(uint32_t opcode) { CMP_RN_O8(7); }
1118 1118
1119 1119 
 // ADD R0,#Offset8
1120 
-static INSN_REGPARM void thumb30(u32 opcode) { ADD_RN_O8(0); }
1120 
+static INSN_REGPARM void thumb30(uint32_t opcode) { ADD_RN_O8(0); }
1121 1121 
 // ADD R1,#Offset8
1122 
-static INSN_REGPARM void thumb31(u32 opcode) { ADD_RN_O8(1); }
1122 
+static INSN_REGPARM void thumb31(uint32_t opcode) { ADD_RN_O8(1); }
1123 1123 
 // ADD R2,#Offset8
1124 
-static INSN_REGPARM void thumb32(u32 opcode) { ADD_RN_O8(2); }
1124 
+static INSN_REGPARM void thumb32(uint32_t opcode) { ADD_RN_O8(2); }
1125 1125 
 // ADD R3,#Offset8
1126 
-static INSN_REGPARM void thumb33(u32 opcode) { ADD_RN_O8(3); }
1126 
+static INSN_REGPARM void thumb33(uint32_t opcode) { ADD_RN_O8(3); }
1127 1127 
 // ADD R4,#Offset8
1128 
-static INSN_REGPARM void thumb34(u32 opcode) { ADD_RN_O8(4); }
1128 
+static INSN_REGPARM void thumb34(uint32_t opcode) { ADD_RN_O8(4); }
1129 1129 
 // ADD R5,#Offset8
1130 
-static INSN_REGPARM void thumb35(u32 opcode) { ADD_RN_O8(5); }
1130 
+static INSN_REGPARM void thumb35(uint32_t opcode) { ADD_RN_O8(5); }
1131 1131 
 // ADD R6,#Offset8
1132 
-static INSN_REGPARM void thumb36(u32 opcode) { ADD_RN_O8(6); }
1132 
+static INSN_REGPARM void thumb36(uint32_t opcode) { ADD_RN_O8(6); }
1133 1133 
 // ADD R7,#Offset8
1134 
-static INSN_REGPARM void thumb37(u32 opcode) { ADD_RN_O8(7); }
1134 
+static INSN_REGPARM void thumb37(uint32_t opcode) { ADD_RN_O8(7); }
1135 1135
1136 1136 
 // SUB R0,#Offset8
1137 
-static INSN_REGPARM void thumb38(u32 opcode) { SUB_RN_O8(0); }
1137 
+static INSN_REGPARM void thumb38(uint32_t opcode) { SUB_RN_O8(0); }
1138 1138 
 // SUB R1,#Offset8
1139 
-static INSN_REGPARM void thumb39(u32 opcode) { SUB_RN_O8(1); }
1139 
+static INSN_REGPARM void thumb39(uint32_t opcode) { SUB_RN_O8(1); }
1140 1140 
 // SUB R2,#Offset8
1141 
-static INSN_REGPARM void thumb3A(u32 opcode) { SUB_RN_O8(2); }
1141 
+static INSN_REGPARM void thumb3A(uint32_t opcode) { SUB_RN_O8(2); }
1142 1142 
 // SUB R3,#Offset8
1143 
-static INSN_REGPARM void thumb3B(u32 opcode) { SUB_RN_O8(3); }
1143 
+static INSN_REGPARM void thumb3B(uint32_t opcode) { SUB_RN_O8(3); }
1144 1144 
 // SUB R4,#Offset8
1145 
-static INSN_REGPARM void thumb3C(u32 opcode) { SUB_RN_O8(4); }
1145 
+static INSN_REGPARM void thumb3C(uint32_t opcode) { SUB_RN_O8(4); }
1146 1146 
 // SUB R5,#Offset8
1147 
-static INSN_REGPARM void thumb3D(u32 opcode) { SUB_RN_O8(5); }
1147 
+static INSN_REGPARM void thumb3D(uint32_t opcode) { SUB_RN_O8(5); }
1148 1148 
 // SUB R6,#Offset8
1149 
-static INSN_REGPARM void thumb3E(u32 opcode) { SUB_RN_O8(6); }
1149 
+static INSN_REGPARM void thumb3E(uint32_t opcode) { SUB_RN_O8(6); }
1150 1150 
 // SUB R7,#Offset8
1151 
-static INSN_REGPARM void thumb3F(u32 opcode) { SUB_RN_O8(7); }
1151 
+static INSN_REGPARM void thumb3F(uint32_t opcode) { SUB_RN_O8(7); }
1152 1152
1153 1153 
 // ALU operations /////////////////////////////////////////////////////////
1154 1154
1155 1155 
 // AND Rd, Rs
1156 
-static INSN_REGPARM void thumb40_0(u32 opcode)
1156 
+static INSN_REGPARM void thumb40_0(uint32_t opcode)
1157 1157 
 {
1158 1158 
   int dest = opcode & 7;
1159 1159 
   reg[dest].I &= reg[(opcode >> 3)&7].I;
... ... 
@@ -1163,7 +1163,7 @@ static INSN_REGPARM void thumb40_0(u32 opcode)
1163 1163 
 }
1164 1164
1165 1165 
 // EOR Rd, Rs
1166 
-static INSN_REGPARM void thumb40_1(u32 opcode)
1166 
+static INSN_REGPARM void thumb40_1(uint32_t opcode)
1167 1167 
 {
1168 1168 
   int dest = opcode & 7;
1169 1169 
   reg[dest].I ^= reg[(opcode >> 3)&7].I;
... ... 
@@ -1172,10 +1172,10 @@ static INSN_REGPARM void thumb40_1(u32 opcode)
1172 1172 
 }
1173 1173
1174 1174 
 // LSL Rd, Rs
1175 
-static INSN_REGPARM void thumb40_2(u32 opcode)
1175 
+static INSN_REGPARM void thumb40_2(uint32_t opcode)
1176 1176 
 {
1177 1177 
   int dest = opcode & 7;
1178 
-  u32 value = reg[(opcode >> 3)&7].B.B0;
1178 
+  uint32_t value = reg[(opcode >> 3)&7].B.B0;
1179 1179 
   if(value) {
1180 1180 
     if(value == 32) {
1181 1181 
       value = 0;
... ... 
@@ -1194,10 +1194,10 @@ static INSN_REGPARM void thumb40_2(u32 opcode)
1194 1194 
 }
1195 1195
1196 1196 
 // LSR Rd, Rs
1197 
-static INSN_REGPARM void thumb40_3(u32 opcode)
1197 
+static INSN_REGPARM void thumb40_3(uint32_t opcode)
1198 1198 
 {
1199 1199 
   int dest = opcode & 7;
1200 
-  u32 value = reg[(opcode >> 3)&7].B.B0;
1200 
+  uint32_t value = reg[(opcode >> 3)&7].B.B0;
1201 1201 
   if(value) {
1202 1202 
     if(value == 32) {
1203 1203 
       value = 0;
... ... 
@@ -1216,10 +1216,10 @@ static INSN_REGPARM void thumb40_3(u32 opcode)
1216 1216 
 }
1217 1217
1218 1218 
 // ASR Rd, Rs
1219 
-static INSN_REGPARM void thumb41_0(u32 opcode)
1219 
+static INSN_REGPARM void thumb41_0(uint32_t opcode)
1220 1220 
 {
1221 1221 
   int dest = opcode & 7;
1222 
-  u32 value = reg[(opcode >> 3)&7].B.B0;
1222 
+  uint32_t value = reg[(opcode >> 3)&7].B.B0;
1223 1223 
   if(value) {
1224 1224 
     if(value < 32) {
1225 1225 
       ASR_RD_RS;
... ... 
@@ -1240,26 +1240,26 @@ static INSN_REGPARM void thumb41_0(u32 opcode)
1240 1240 
 }
1241 1241
1242 1242 
 // ADC Rd, Rs
1243 
-static INSN_REGPARM void thumb41_1(u32 opcode)
1243 
+static INSN_REGPARM void thumb41_1(uint32_t opcode)
1244 1244 
 {
1245 1245 
   int dest = opcode & 0x07;
1246 
-  u32 value = reg[(opcode >> 3)&7].I;
1246 
+  uint32_t value = reg[(opcode >> 3)&7].I;
1247 1247 
   ADC_RD_RS;
1248 1248 
 }
1249 1249
1250 1250 
 // SBC Rd, Rs
1251 
-static INSN_REGPARM void thumb41_2(u32 opcode)
1251 
+static INSN_REGPARM void thumb41_2(uint32_t opcode)
1252 1252 
 {
1253 1253 
   int dest = opcode & 0x07;
1254 
-  u32 value = reg[(opcode >> 3)&7].I;
1254 
+  uint32_t value = reg[(opcode >> 3)&7].I;
1255 1255 
   SBC_RD_RS;
1256 1256 
 }
1257 1257
1258 1258 
 // ROR Rd, Rs
1259 
-static INSN_REGPARM void thumb41_3(u32 opcode)
1259 
+static INSN_REGPARM void thumb41_3(uint32_t opcode)
1260 1260 
 {
1261 1261 
   int dest = opcode & 7;
1262 
-  u32 value = reg[(opcode >> 3)&7].B.B0;
1262 
+  uint32_t value = reg[(opcode >> 3)&7].B.B0;
1263 1263
1264 1264 
   if(value) {
1265 1265 
     value = value & 0x1f;
... ... 
@@ -1276,15 +1276,15 @@ static INSN_REGPARM void thumb41_3(u32 opcode)
1276 1276 
 }
1277 1277
1278 1278 
 // TST Rd, Rs
1279 
-static INSN_REGPARM void thumb42_0(u32 opcode)
1279 
+static INSN_REGPARM void thumb42_0(uint32_t opcode)
1280 1280 
 {
1281 
-  u32 value = reg[opcode & 7].I & reg[(opcode >> 3) & 7].I;
1281 
+  uint32_t value = reg[opcode & 7].I & reg[(opcode >> 3) & 7].I;
1282 1282 
   N_FLAG = value & 0x80000000 ? true : false;
1283 1283 
   Z_FLAG = value ? false : true;
1284 1284 
 }
1285 1285
1286 1286 
 // NEG Rd, Rs
1287 
-static INSN_REGPARM void thumb42_1(u32 opcode)
1287 
+static INSN_REGPARM void thumb42_1(uint32_t opcode)
1288 1288 
 {
1289 1289 
   int dest = opcode & 7;
1290 1290 
   int source = (opcode >> 3) & 7;
... ... 
@@ -1292,23 +1292,23 @@ static INSN_REGPARM void thumb42_1(u32 opcode)
1292 1292 
 }
1293 1293
1294 1294 
 // CMP Rd, Rs
1295 
-static INSN_REGPARM void thumb42_2(u32 opcode)
1295 
+static INSN_REGPARM void thumb42_2(uint32_t opcode)
1296 1296 
 {
1297 1297 
   int dest = opcode & 7;
1298 
-  u32 value = reg[(opcode >> 3)&7].I;
1298 
+  uint32_t value = reg[(opcode >> 3)&7].I;
1299 1299 
   CMP_RD_RS;
1300 1300 
 }
1301 1301
1302 1302 
 // CMN Rd, Rs
1303 
-static INSN_REGPARM void thumb42_3(u32 opcode)
1303 
+static INSN_REGPARM void thumb42_3(uint32_t opcode)
1304 1304 
 {
1305 1305 
   int dest = opcode & 7;
1306 
-  u32 value = reg[(opcode >> 3)&7].I;
1306 
+  uint32_t value = reg[(opcode >> 3)&7].I;
1307 1307 
   CMN_RD_RS;
1308 1308 
 }
1309 1309
1310 1310 
 // ORR Rd, Rs
1311 
-static INSN_REGPARM void thumb43_0(u32 opcode)
1311 
+static INSN_REGPARM void thumb43_0(uint32_t opcode)
1312 1312 
 {
1313 1313 
   int dest = opcode & 7;
1314 1314 
   reg[dest].I |= reg[(opcode >> 3) & 7].I;
... ... 
@@ -1317,13 +1317,13 @@ static INSN_REGPARM void thumb43_0(u32 opcode)
1317 1317 
 }
1318 1318
1319 1319 
 // MUL Rd, Rs
1320 
-static INSN_REGPARM void thumb43_1(u32 opcode)
1320 
+static INSN_REGPARM void thumb43_1(uint32_t opcode)
1321 1321 
 {
1322 1322 
   clockTicks = 1;
1323 1323 
   int dest = opcode & 7;
1324 
-  u32 rm = reg[dest].I;
1324 
+  uint32_t rm = reg[dest].I;
1325 1325 
   reg[dest].I = reg[(opcode >> 3) & 7].I * rm;
1326 
-  if (((s32)rm) < 0)
1326 
+  if (((int32_t)rm) < 0)
1327 1327 
     rm = ~rm;
1328 1328 
   if ((rm & 0xFFFFFF00) == 0)
1329 1329 
     clockTicks += 0;
... ... 
@@ -1340,7 +1340,7 @@ static INSN_REGPARM void thumb43_1(u32 opcode)
1340 1340 
 }
1341 1341
1342 1342 
 // BIC Rd, Rs
1343 
-static INSN_REGPARM void thumb43_2(u32 opcode)
1343 
+static INSN_REGPARM void thumb43_2(uint32_t opcode)
1344 1344 
 {
1345 1345 
   int dest = opcode & 7;
1346 1346 
   reg[dest].I &= (~reg[(opcode >> 3) & 7].I);
... ... 
@@ -1349,7 +1349,7 @@ static INSN_REGPARM void thumb43_2(u32 opcode)
1349 1349 
 }
1350 1350
1351 1351 
 // MVN Rd, Rs
1352 
-static INSN_REGPARM void thumb43_3(u32 opcode)
1352 
+static INSN_REGPARM void thumb43_3(uint32_t opcode)
1353 1353 
 {
1354 1354 
   int dest = opcode & 7;
1355 1355 
   reg[dest].I = ~reg[(opcode >> 3) & 7].I;
... ... 
@@ -1360,13 +1360,13 @@ static INSN_REGPARM void thumb43_3(u32 opcode)
1360 1360 
 // High-register instructions and BX //////////////////////////////////////
1361 1361
1362 1362 
 // ADD Rd, Hs
1363 
-static INSN_REGPARM void thumb44_1(u32 opcode)
1363 
+static INSN_REGPARM void thumb44_1(uint32_t opcode)
1364 1364 
 {
1365 1365 
   reg[opcode&7].I += reg[((opcode>>3)&7)+8].I;
1366 1366 
 }
1367 1367
1368 1368 
 // ADD Hd, Rs
1369 
-static INSN_REGPARM void thumb44_2(u32 opcode)
1369 
+static INSN_REGPARM void thumb44_2(uint32_t opcode)
1370 1370 
 {
1371 1371 
   reg[(opcode&7)+8].I += reg[(opcode>>3)&7].I;
1372 1372 
   if((opcode&7) == 7) {
... ... 
@@ -1380,7 +1380,7 @@ static INSN_REGPARM void thumb44_2(u32 opcode)
1380 1380 
 }
1381 1381
1382 1382 
 // ADD Hd, Hs
1383 
-static INSN_REGPARM void thumb44_3(u32 opcode)
1383 
+static INSN_REGPARM void thumb44_3(uint32_t opcode)
1384 1384 
 {
1385 1385 
   reg[(opcode&7)+8].I += reg[((opcode>>3)&7)+8].I;
1386 1386 
   if((opcode&7) == 7) {
... ... 
@@ -1394,45 +1394,45 @@ static INSN_REGPARM void thumb44_3(u32 opcode)
1394 1394 
 }
1395 1395
1396 1396 
 // CMP Rd, Hs
1397 
-static INSN_REGPARM void thumb45_1(u32 opcode)
1397 
+static INSN_REGPARM void thumb45_1(uint32_t opcode)
1398 1398 
 {
1399 1399 
   int dest = opcode & 7;
1400 
-  u32 value = reg[((opcode>>3)&7)+8].I;
1400 
+  uint32_t value = reg[((opcode>>3)&7)+8].I;
1401 1401 
   CMP_RD_RS;
1402 1402 
 }
1403 1403
1404 1404 
 // CMP Hd, Rs
1405 
-static INSN_REGPARM void thumb45_2(u32 opcode)
1405 
+static INSN_REGPARM void thumb45_2(uint32_t opcode)
1406 1406 
 {
1407 1407 
   int dest = (opcode & 7) + 8;
1408 
-  u32 value = reg[(opcode>>3)&7].I;
1408 
+  uint32_t value = reg[(opcode>>3)&7].I;
1409 1409 
   CMP_RD_RS;
1410 1410 
 }
1411 1411
1412 1412 
 // CMP Hd, Hs
1413 
-static INSN_REGPARM void thumb45_3(u32 opcode)
1413 
+static INSN_REGPARM void thumb45_3(uint32_t opcode)
1414 1414 
 {
1415 1415 
   int dest = (opcode & 7) + 8;
1416 
-  u32 value = reg[((opcode>>3)&7)+8].I;
1416 
+  uint32_t value = reg[((opcode>>3)&7)+8].I;
1417 1417 
   CMP_RD_RS;
1418 1418 
 }
1419 1419
1420 1420 
 // MOV Rd, Rs
1421 
-static INSN_REGPARM void thumb46_0(u32 opcode)
1421 
+static INSN_REGPARM void thumb46_0(uint32_t opcode)
1422 1422 
 {
1423 1423 
         reg[opcode&7].I = reg[((opcode>>3)&7)].I;
1424 1424 
         clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1425 1425 
 }
1426 1426
1427 1427 
 // MOV Rd, Hs
1428 
-static INSN_REGPARM void thumb46_1(u32 opcode)
1428 
+static INSN_REGPARM void thumb46_1(uint32_t opcode)
1429 1429 
 {
1430 1430 
   reg[opcode&7].I = reg[((opcode>>3)&7)+8].I;
1431 1431 
   clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1432 1432 
 }
1433 1433
1434 1434 
 // MOV Hd, Rs
1435 
-static INSN_REGPARM void thumb46_2(u32 opcode)
1435 
+static INSN_REGPARM void thumb46_2(uint32_t opcode)
1436 1436 
 {
1437 1437 
   reg[(opcode&7)+8].I = reg[(opcode>>3)&7].I;
1438 1438 
   if((opcode&7) == 7) {
... ... 
@@ -1447,7 +1447,7 @@ static INSN_REGPARM void thumb46_2(u32 opcode)
1447 1447 
 }
1448 1448
1449 1449 
 // MOV Hd, Hs
1450 
-static INSN_REGPARM void thumb46_3(u32 opcode)
1450 
+static INSN_REGPARM void thumb46_3(uint32_t opcode)
1451 1451 
 {
1452 1452 
   reg[(opcode&7)+8].I = reg[((opcode>>3)&7)+8].I;
1453 1453 
   if((opcode&7) == 7) {
... ... 
@@ -1463,7 +1463,7 @@ static INSN_REGPARM void thumb46_3(u32 opcode)
1463 1463
1464 1464
1465 1465 
 // BX Rs
1466 
-static INSN_REGPARM void thumb47(u32 opcode)
1466 
+static INSN_REGPARM void thumb47(uint32_t opcode)
1467 1467 
 {
1468 1468 
   int base = (opcode >> 3) & 15;
1469 1469 
   busPrefetchCount=0;
... ... 
@@ -1489,175 +1489,175 @@ static INSN_REGPARM void thumb47(u32 opcode)
1489 1489 
 // Load/store instructions ////////////////////////////////////////////////
1490 1490
1491 1491 
 // LDR R0~R7,[PC, #Imm]
1492 
-static INSN_REGPARM void thumb48(u32 opcode)
1492 
+static INSN_REGPARM void thumb48(uint32_t opcode)
1493 1493 
 {
1494 
-  u8 regist = (opcode >> 8) & 7;
1494 
+  uint8_t regist = (opcode >> 8) & 7;
1495 1495 
   if (busPrefetchCount == 0)
1496 1496 
     busPrefetch = busPrefetchEnable;
1497 
-  u32 address = (reg[15].I & 0xFFFFFFFC) + ((opcode & 0xFF) << 2);
1497 
+  uint32_t address = (reg[15].I & 0xFFFFFFFC) + ((opcode & 0xFF) << 2);
1498 1498 
   reg[regist].I = CPUReadMemoryQuick(address);
1499 1499 
   busPrefetchCount=0;
1500 1500 
   clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
1501 1501 
 }
1502 1502
1503 1503 
 // STR Rd, [Rs, Rn]
1504 
-static INSN_REGPARM void thumb50(u32 opcode)
1504 
+static INSN_REGPARM void thumb50(uint32_t opcode)
1505 1505 
 {
1506 1506 
   if (busPrefetchCount == 0)
1507 1507 
     busPrefetch = busPrefetchEnable;
1508 
-  u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1508 
+  uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1509 1509 
   CPUWriteMemory(address, reg[opcode & 7].I);
1510 1510 
   clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2;
1511 1511 
 }
1512 1512
1513 1513 
 // STRH Rd, [Rs, Rn]
1514 
-static INSN_REGPARM void thumb52(u32 opcode)
1514 
+static INSN_REGPARM void thumb52(uint32_t opcode)
1515 1515 
 {
1516 1516 
   if (busPrefetchCount == 0)
1517 1517 
     busPrefetch = busPrefetchEnable;
1518 
-  u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1518 
+  uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1519 1519 
   CPUWriteHalfWord(address, reg[opcode&7].W.W0);
1520 1520 
   clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2;
1521 1521 
 }
1522 1522
1523 1523 
 // STRB Rd, [Rs, Rn]
1524 
-static INSN_REGPARM void thumb54(u32 opcode)
1524 
+static INSN_REGPARM void thumb54(uint32_t opcode)
1525 1525 
 {
1526 1526 
   if (busPrefetchCount == 0)
1527 1527 
     busPrefetch = busPrefetchEnable;
1528 
-  u32 address = reg[(opcode>>3)&7].I + reg[(opcode >>6)&7].I;
1528 
+  uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode >>6)&7].I;
1529 1529 
   CPUWriteByte(address, reg[opcode & 7].B.B0);
1530 1530 
   clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2;
1531 1531 
 }
1532 1532
1533 1533 
 // LDSB Rd, [Rs, Rn]
1534 
-static INSN_REGPARM void thumb56(u32 opcode)
1534 
+static INSN_REGPARM void thumb56(uint32_t opcode)
1535 1535 
 {
1536 1536 
   if (busPrefetchCount == 0)
1537 1537 
     busPrefetch = busPrefetchEnable;
1538 
-  u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1539 
-  reg[opcode&7].I = (s8)CPUReadByte(address);
1538 
+  uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1539 
+  reg[opcode&7].I = (int8_t)CPUReadByte(address);
1540 1540 
   clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1541 1541 
 }
1542 1542
1543 1543 
 // LDR Rd, [Rs, Rn]
1544 
-static INSN_REGPARM void thumb58(u32 opcode)
1544 
+static INSN_REGPARM void thumb58(uint32_t opcode)
1545 1545 
 {
1546 1546 
   if (busPrefetchCount == 0)
1547 1547 
     busPrefetch = busPrefetchEnable;
1548 
-  u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1548 
+  uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1549 1549 
   reg[opcode&7].I = CPUReadMemory(address);
1550 1550 
   clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
1551 1551 
 }
1552 1552
1553 1553 
 // LDRH Rd, [Rs, Rn]
1554 
-static INSN_REGPARM void thumb5A(u32 opcode)
1554 
+static INSN_REGPARM void thumb5A(uint32_t opcode)
1555 1555 
 {
1556 1556 
   if (busPrefetchCount == 0)
1557 1557 
     busPrefetch = busPrefetchEnable;
1558 
-  u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1558 
+  uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1559 1559 
   reg[opcode&7].I = CPUReadHalfWord(address);
1560 1560 
   clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
1561 1561 
 }
1562 1562
1563 1563 
 // LDRB Rd, [Rs, Rn]
1564 
-static INSN_REGPARM void thumb5C(u32 opcode)
1564 
+static INSN_REGPARM void thumb5C(uint32_t opcode)
1565 1565 
 {
1566 1566 
   if (busPrefetchCount == 0)
1567 1567 
     busPrefetch = busPrefetchEnable;
1568 
-  u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1568 
+  uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1569 1569 
   reg[opcode&7].I = CPUReadByte(address);
1570 1570 
   clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1571 1571 
 }
1572 1572
1573 1573 
 // LDSH Rd, [Rs, Rn]
1574 
-static INSN_REGPARM void thumb5E(u32 opcode)
1574 
+static INSN_REGPARM void thumb5E(uint32_t opcode)
1575 1575 
 {
1576 1576 
   if (busPrefetchCount == 0)
1577 1577 
     busPrefetch = busPrefetchEnable;
1578 
-  u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1579 
-  reg[opcode&7].I = (u32)CPUReadHalfWordSigned(address);
1578 
+  uint32_t address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1579 
+  reg[opcode&7].I = (uint32_t)CPUReadHalfWordSigned(address);
1580 1580 
   clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1581 1581 
 }
1582 1582
1583 1583 
 // STR Rd, [Rs, #Imm]
1584 
-static INSN_REGPARM void thumb60(u32 opcode)
1584 
+static INSN_REGPARM void thumb60(uint32_t opcode)
1585 1585 
 {
1586 1586 
   if (busPrefetchCount == 0)
1587 1587 
     busPrefetch = busPrefetchEnable;
1588 
-  u32 address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<2);
1588 
+  uint32_t address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<2);
1589 1589 
   CPUWriteMemory(address, reg[opcode&7].I);
1590 1590 
   clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2;
1591 1591 
 }
1592 1592
1593 1593 
 // LDR Rd, [Rs, #Imm]
1594 
-static INSN_REGPARM void thumb68(u32 opcode)
1594 
+static INSN_REGPARM void thumb68(uint32_t opcode)
1595 1595 
 {
1596 1596 
   if (busPrefetchCount == 0)
1597 1597 
     busPrefetch = busPrefetchEnable;
1598 
-  u32 address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<2);
1598 
+  uint32_t address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<2);
1599 1599 
   reg[opcode&7].I = CPUReadMemory(address);
1600 1600 
   clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
1601 1601 
 }
1602 1602
1603 1603 
 // STRB Rd, [Rs, #Imm]
1604 
-static INSN_REGPARM void thumb70(u32 opcode)
1604 
+static INSN_REGPARM void thumb70(uint32_t opcode)
1605 1605 
 {
1606 1606 
   if (busPrefetchCount == 0)
1607 1607 
     busPrefetch = busPrefetchEnable;
1608 
-  u32 address = reg[(opcode>>3)&7].I + (((opcode>>6)&31));
1608 
+  uint32_t address = reg[(opcode>>3)&7].I + (((opcode>>6)&31));
1609 1609 
   CPUWriteByte(address, reg[opcode&7].B.B0);
1610 1610 
   clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2;
1611 1611 
 }
1612 1612
1613 1613 
 // LDRB Rd, [Rs, #Imm]
1614 
-static INSN_REGPARM void thumb78(u32 opcode)
1614 
+static INSN_REGPARM void thumb78(uint32_t opcode)
1615 1615 
 {
1616 1616 
   if (busPrefetchCount == 0)
1617 1617 
     busPrefetch = busPrefetchEnable;
1618 
-  u32 address = reg[(opcode>>3)&7].I + (((opcode>>6)&31));
1618 
+  uint32_t address = reg[(opcode>>3)&7].I + (((opcode>>6)&31));
1619 1619 
   reg[opcode&7].I = CPUReadByte(address);
1620 1620 
   clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1621 1621 
 }
1622 1622
1623 1623 
 // STRH Rd, [Rs, #Imm]
1624 
-static INSN_REGPARM void thumb80(u32 opcode)
1624 
+static INSN_REGPARM void thumb80(uint32_t opcode)
1625 1625 
 {
1626 1626 
   if (busPrefetchCount == 0)
1627 1627 
     busPrefetch = busPrefetchEnable;
1628 
-  u32 address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<1);
1628 
+  uint32_t address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<1);
1629 1629 
   CPUWriteHalfWord(address, reg[opcode&7].W.W0);
1630 1630 
   clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2;
1631 1631 
 }
1632 1632
1633 1633 
 // LDRH Rd, [Rs, #Imm]
1634 
-static INSN_REGPARM void thumb88(u32 opcode)
1634 
+static INSN_REGPARM void thumb88(uint32_t opcode)
1635 1635 
 {
1636 1636 
   if (busPrefetchCount == 0)
1637 1637 
     busPrefetch = busPrefetchEnable;
1638 
-  u32 address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<1);
1638 
+  uint32_t address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<1);
1639 1639 
   reg[opcode&7].I = CPUReadHalfWord(address);
1640 1640 
   clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1641 1641 
 }
1642 1642
1643 1643 
 // STR R0~R7, [SP, #Imm]
1644 
-static INSN_REGPARM void thumb90(u32 opcode)
1644 
+static INSN_REGPARM void thumb90(uint32_t opcode)
1645 1645 
 {
1646 
-  u8 regist = (opcode >> 8) & 7;
1646 
+  uint8_t regist = (opcode >> 8) & 7;
1647 1647 
   if (busPrefetchCount == 0)
1648 1648 
     busPrefetch = busPrefetchEnable;
1649 
-  u32 address = reg[13].I + ((opcode&255)<<2);
1649 
+  uint32_t address = reg[13].I + ((opcode&255)<<2);
1650 1650 
   CPUWriteMemory(address, reg[regist].I);
1651 1651 
   clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2;
1652 1652 
 }
1653 1653
1654 1654 
 // LDR R0~R7, [SP, #Imm]
1655 
-static INSN_REGPARM void thumb98(u32 opcode)
1655 
+static INSN_REGPARM void thumb98(uint32_t opcode)
1656 1656 
 {
1657 
-  u8 regist = (opcode >> 8) & 7;
1657 
+  uint8_t regist = (opcode >> 8) & 7;
1658 1658 
   if (busPrefetchCount == 0)
1659 1659 
     busPrefetch = busPrefetchEnable;
1660 
-  u32 address = reg[13].I + ((opcode&255)<<2);
1660 
+  uint32_t address = reg[13].I + ((opcode&255)<<2);
1661 1661 
   reg[regist].I = CPUReadMemoryQuick(address);
1662 1662 
   clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
1663 1663 
 }
... ... 
@@ -1665,23 +1665,23 @@ static INSN_REGPARM void thumb98(u32 opcode)
1665 1665 
 // PC/stack-related ///////////////////////////////////////////////////////
1666 1666
1667 1667 
 // ADD R0~R7, PC, Imm
1668 
-static INSN_REGPARM void thumbA0(u32 opcode)
1668 
+static INSN_REGPARM void thumbA0(uint32_t opcode)
1669 1669 
 {
1670 
-  u8 regist = (opcode >> 8) & 7;
1670 
+  uint8_t regist = (opcode >> 8) & 7;
1671 1671 
   reg[regist].I = (reg[15].I & 0xFFFFFFFC) + ((opcode&255)<<2);
1672 1672 
   clockTicks = 1 + codeTicksAccess16(armNextPC);
1673 1673 
 }
1674 1674
1675 1675 
 // ADD R0~R7, SP, Imm
1676 
-static INSN_REGPARM void thumbA8(u32 opcode)
1676 
+static INSN_REGPARM void thumbA8(uint32_t opcode)
1677 1677 
 {
1678 
-  u8 regist = (opcode >> 8) & 7;
1678 
+  uint8_t regist = (opcode >> 8) & 7;
1679 1679 
   reg[regist].I = reg[13].I + ((opcode&255)<<2);
1680 1680 
   clockTicks = 1 + codeTicksAccess16(armNextPC);
1681 1681 
 }
1682 1682
1683 1683 
 // ADD SP, Imm
1684 
-static INSN_REGPARM void thumbB0(u32 opcode)
1684 
+static INSN_REGPARM void thumbB0(uint32_t opcode)
1685 1685 
 {
1686 1686 
   int offset = (opcode & 127) << 2;
1687 1687 
   if(opcode & 0x80)
... ... 
@@ -1717,13 +1717,13 @@ static INSN_REGPARM void thumbB0(u32 opcode)
1717 1717 
   }
1718 1718
1719 1719 
 // PUSH {Rlist}
1720 
-static INSN_REGPARM void thumbB4(u32 opcode)
1720 
+static INSN_REGPARM void thumbB4(uint32_t opcode)
1721 1721 
 {
1722 1722 
   if (busPrefetchCount == 0)
1723 1723 
     busPrefetch = busPrefetchEnable;
1724 1724 
   int count = 0;
1725 
-  u32 temp = reg[13].I - 4 * cpuBitsSet[opcode & 0xff];
1726 
-  u32 address = temp & 0xFFFFFFFC;
1725 
+  uint32_t temp = reg[13].I - 4 * cpuBitsSet[opcode & 0xff];
1726 
+  uint32_t address = temp & 0xFFFFFFFC;
1727 1727 
   PUSH_REG(1, 0);
1728 1728 
   PUSH_REG(2, 1);
1729 1729 
   PUSH_REG(4, 2);
... ... 
@@ -1737,13 +1737,13 @@ static INSN_REGPARM void thumbB4(u32 opcode)
1737 1737 
 }
1738 1738
1739 1739 
 // PUSH {Rlist, LR}
1740 
-static INSN_REGPARM void thumbB5(u32 opcode)
1740 
+static INSN_REGPARM void thumbB5(uint32_t opcode)
1741 1741 
 {
1742 1742 
   if (busPrefetchCount == 0)
1743 1743 
     busPrefetch = busPrefetchEnable;
1744 1744 
   int count = 0;
1745 
-  u32 temp = reg[13].I - 4 - 4 * cpuBitsSet[opcode & 0xff];
1746 
-  u32 address = temp & 0xFFFFFFFC;
1745 
+  uint32_t temp = reg[13].I - 4 - 4 * cpuBitsSet[opcode & 0xff];
1746 
+  uint32_t address = temp & 0xFFFFFFFC;
1747 1747 
   PUSH_REG(1, 0);
1748 1748 
   PUSH_REG(2, 1);
1749 1749 
   PUSH_REG(4, 2);
... ... 
@@ -1758,13 +1758,13 @@ static INSN_REGPARM void thumbB5(u32 opcode)
1758 1758 
 }
1759 1759
1760 1760 
 // POP {Rlist}
1761 
-static INSN_REGPARM void thumbBC(u32 opcode)
1761 
+static INSN_REGPARM void thumbBC(uint32_t opcode)
1762 1762 
 {
1763 1763 
   if (busPrefetchCount == 0)
1764 1764 
     busPrefetch = busPrefetchEnable;
1765 1765 
   int count = 0;
1766 
-  u32 address = reg[13].I & 0xFFFFFFFC;
1767 
-  u32 temp = reg[13].I + 4*cpuBitsSet[opcode & 0xFF];
1766 
+  uint32_t address = reg[13].I & 0xFFFFFFFC;
1767 
+  uint32_t temp = reg[13].I + 4*cpuBitsSet[opcode & 0xFF];
1768 1768 
   POP_REG(1, 0);
1769 1769 
   POP_REG(2, 1);
1770 1770 
   POP_REG(4, 2);
... ... 
@@ -1778,13 +1778,13 @@ static INSN_REGPARM void thumbBC(u32 opcode)
1778 1778 
 }
1779 1779
1780 1780 
 // POP {Rlist, PC}
1781 
-static INSN_REGPARM void thumbBD(u32 opcode)
1781 
+static INSN_REGPARM void thumbBD(uint32_t opcode)
1782 1782 
 {
1783 1783 
   if (busPrefetchCount == 0)
1784 1784 
     busPrefetch = busPrefetchEnable;
1785 1785 
   int count = 0;
1786 
-  u32 address = reg[13].I & 0xFFFFFFFC;
1787 
-  u32 temp = reg[13].I + 4 + 4*cpuBitsSet[opcode & 0xFF];
1786 
+  uint32_t address = reg[13].I & 0xFFFFFFFC;
1787 
+  uint32_t temp = reg[13].I + 4 + 4*cpuBitsSet[opcode & 0xFF];
1788 1788 
   POP_REG(1, 0);
1789 1789 
   POP_REG(2, 1);
1790 1790 
   POP_REG(4, 2);
... ... 
@@ -1836,13 +1836,13 @@ static INSN_REGPARM void thumbBD(u32 opcode)
1836 1836 
   }
1837 1837
1838 1838 
 // STM R0~7!, {Rlist}
1839 
-static INSN_REGPARM void thumbC0(u32 opcode)
1839 
+static INSN_REGPARM void thumbC0(uint32_t opcode)
1840 1840 
 {
1841 
-  u8 regist = (opcode >> 8) & 7;
1841 
+  uint8_t regist = (opcode >> 8) & 7;
1842 1842 
   if (busPrefetchCount == 0)
1843 1843 
     busPrefetch = busPrefetchEnable;
1844 
-  u32 address = reg[regist].I & 0xFFFFFFFC;
1845 
-  u32 temp = reg[regist].I + 4*cpuBitsSet[opcode & 0xff];
1844 
+  uint32_t address = reg[regist].I & 0xFFFFFFFC;
1845 
+  uint32_t temp = reg[regist].I + 4*cpuBitsSet[opcode & 0xff];
1846 1846 
   int count = 0;
1847 1847 
   // store
1848 1848 
   THUMB_STM_REG(1, 0, regist);
... ... 
@@ -1857,13 +1857,13 @@ static INSN_REGPARM void thumbC0(u32 opcode)
1857 1857 
 }
1858 1858
1859 1859 
 // LDM R0~R7!, {Rlist}
1860 
-static INSN_REGPARM void thumbC8(u32 opcode)
1860 
+static INSN_REGPARM void thumbC8(uint32_t opcode)
1861 1861 
 {
1862 
-  u8 regist = (opcode >> 8) & 7;
1862 
+  uint8_t regist = (opcode >> 8) & 7;
1863 1863 
   if (busPrefetchCount == 0)
1864 1864 
     busPrefetch = busPrefetchEnable;
1865 
-  u32 address = reg[regist].I & 0xFFFFFFFC;
1866 
-  u32 temp = reg[regist].I + 4*cpuBitsSet[opcode & 0xFF];
1865 
+  uint32_t address = reg[regist].I & 0xFFFFFFFC;
1866 
+  uint32_t temp = reg[regist].I + 4*cpuBitsSet[opcode & 0xFF];
1867 1867 
   int count = 0;
1868 1868 
   // load
1869 1869 
   THUMB_LDM_REG(1, 0);
... ... 
@@ -1882,12 +1882,12 @@ static INSN_REGPARM void thumbC8(u32 opcode)
1882 1882 
 // Conditional branches ///////////////////////////////////////////////////
1883 1883
1884 1884 
 // BEQ offset
1885 
-static INSN_REGPARM void thumbD0(u32 opcode)
1885 
+static INSN_REGPARM void thumbD0(uint32_t opcode)
1886 1886 
 {
1887 1887 
   UPDATE_OLDREG;
1888 1888 
   clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1889 1889 
   if(Z_FLAG) {
1890 
-    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1890 
+    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
1891 1891 
     armNextPC = reg[15].I;
1892 1892 
     reg[15].I += 2;
1893 1893 
     THUMB_PREFETCH;
... ... 
@@ -1897,12 +1897,12 @@ static INSN_REGPARM void thumbD0(u32 opcode)
1897 1897 
 }
1898 1898
1899 1899 
 // BNE offset
1900 
-static INSN_REGPARM void thumbD1(u32 opcode)
1900 
+static INSN_REGPARM void thumbD1(uint32_t opcode)
1901 1901 
 {
1902 1902 
   UPDATE_OLDREG;
1903 1903 
   clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1904 1904 
   if(!Z_FLAG) {
1905 
-    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1905 
+    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
1906 1906 
     armNextPC = reg[15].I;
1907 1907 
     reg[15].I += 2;
1908 1908 
     THUMB_PREFETCH;
... ... 
@@ -1912,12 +1912,12 @@ static INSN_REGPARM void thumbD1(u32 opcode)
1912 1912 
 }
1913 1913
1914 1914 
 // BCS offset
1915 
-static INSN_REGPARM void thumbD2(u32 opcode)
1915 
+static INSN_REGPARM void thumbD2(uint32_t opcode)
1916 1916 
 {
1917 1917 
   UPDATE_OLDREG;
1918 1918 
   clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1919 1919 
   if(C_FLAG) {
1920 
-    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1920 
+    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
1921 1921 
     armNextPC = reg[15].I;
1922 1922 
     reg[15].I += 2;
1923 1923 
     THUMB_PREFETCH;
... ... 
@@ -1927,12 +1927,12 @@ static INSN_REGPARM void thumbD2(u32 opcode)
1927 1927 
 }
1928 1928
1929 1929 
 // BCC offset
1930 
-static INSN_REGPARM void thumbD3(u32 opcode)
1930 
+static INSN_REGPARM void thumbD3(uint32_t opcode)
1931 1931 
 {
1932 1932 
   UPDATE_OLDREG;
1933 1933 
   clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1934 1934 
   if(!C_FLAG) {
1935 
-    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1935 
+    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
1936 1936 
     armNextPC = reg[15].I;
1937 1937 
     reg[15].I += 2;
1938 1938 
     THUMB_PREFETCH;
... ... 
@@ -1942,12 +1942,12 @@ static INSN_REGPARM void thumbD3(u32 opcode)
1942 1942 
 }
1943 1943
1944 1944 
 // BMI offset
1945 
-static INSN_REGPARM void thumbD4(u32 opcode)
1945 
+static INSN_REGPARM void thumbD4(uint32_t opcode)
1946 1946 
 {
1947 1947 
   UPDATE_OLDREG;
1948 1948 
   clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1949 1949 
   if(N_FLAG) {
1950 
-    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1950 
+    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
1951 1951 
     armNextPC = reg[15].I;
1952 1952 
     reg[15].I += 2;
1953 1953 
     THUMB_PREFETCH;
... ... 
@@ -1957,12 +1957,12 @@ static INSN_REGPARM void thumbD4(u32 opcode)
1957 1957 
 }
1958 1958
1959 1959 
 // BPL offset
1960 
-static INSN_REGPARM void thumbD5(u32 opcode)
1960 
+static INSN_REGPARM void thumbD5(uint32_t opcode)
1961 1961 
 {
1962 1962 
   UPDATE_OLDREG;
1963 1963 
   clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1964 1964 
   if(!N_FLAG) {
1965 
-    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1965 
+    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
1966 1966 
     armNextPC = reg[15].I;
1967 1967 
     reg[15].I += 2;
1968 1968 
     THUMB_PREFETCH;
... ... 
@@ -1972,12 +1972,12 @@ static INSN_REGPARM void thumbD5(u32 opcode)
1972 1972 
 }
1973 1973
1974 1974 
 // BVS offset
1975 
-static INSN_REGPARM void thumbD6(u32 opcode)
1975 
+static INSN_REGPARM void thumbD6(uint32_t opcode)
1976 1976 
 {
1977 1977 
   UPDATE_OLDREG;
1978 1978 
   clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1979 1979 
   if(V_FLAG) {
1980 
-    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1980 
+    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
1981 1981 
     armNextPC = reg[15].I;
1982 1982 
     reg[15].I += 2;
1983 1983 
     THUMB_PREFETCH;
... ... 
@@ -1987,12 +1987,12 @@ static INSN_REGPARM void thumbD6(u32 opcode)
1987 1987 
 }
1988 1988
1989 1989 
 // BVC offset
1990 
-static INSN_REGPARM void thumbD7(u32 opcode)
1990 
+static INSN_REGPARM void thumbD7(uint32_t opcode)
1991 1991 
 {
1992 1992 
   UPDATE_OLDREG;
1993 1993 
   clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1994 1994 
   if(!V_FLAG) {
1995 
-    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1995 
+    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
1996 1996 
     armNextPC = reg[15].I;
1997 1997 
     reg[15].I += 2;
1998 1998 
     THUMB_PREFETCH;
... ... 
@@ -2002,12 +2002,12 @@ static INSN_REGPARM void thumbD7(u32 opcode)
2002 2002 
 }
2003 2003
2004 2004 
 // BHI offset
2005 
-static INSN_REGPARM void thumbD8(u32 opcode)
2005 
+static INSN_REGPARM void thumbD8(uint32_t opcode)
2006 2006 
 {
2007 2007 
   UPDATE_OLDREG;
2008 2008 
   clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2009 2009 
   if(C_FLAG && !Z_FLAG) {
2010 
-    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
2010 
+    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
2011 2011 
     armNextPC = reg[15].I;
2012 2012 
     reg[15].I += 2;
2013 2013 
     THUMB_PREFETCH;
... ... 
@@ -2017,12 +2017,12 @@ static INSN_REGPARM void thumbD8(u32 opcode)
2017 2017 
 }
2018 2018
2019 2019 
 // BLS offset
2020 
-static INSN_REGPARM void thumbD9(u32 opcode)
2020 
+static INSN_REGPARM void thumbD9(uint32_t opcode)
2021 2021 
 {
2022 2022 
   UPDATE_OLDREG;
2023 2023 
   clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2024 2024 
   if(!C_FLAG || Z_FLAG) {
2025 
-    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
2025 
+    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
2026 2026 
     armNextPC = reg[15].I;
2027 2027 
     reg[15].I += 2;
2028 2028 
     THUMB_PREFETCH;
... ... 
@@ -2032,12 +2032,12 @@ static INSN_REGPARM void thumbD9(u32 opcode)
2032 2032 
 }
2033 2033
2034 2034 
 // BGE offset
2035 
-static INSN_REGPARM void thumbDA(u32 opcode)
2035 
+static INSN_REGPARM void thumbDA(uint32_t opcode)
2036 2036 
 {
2037 2037 
   UPDATE_OLDREG;
2038 2038 
   clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2039 2039 
   if(N_FLAG == V_FLAG) {
2040 
-    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
2040 
+    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
2041 2041 
     armNextPC = reg[15].I;
2042 2042 
     reg[15].I += 2;
2043 2043 
     THUMB_PREFETCH;
... ... 
@@ -2047,12 +2047,12 @@ static INSN_REGPARM void thumbDA(u32 opcode)
2047 2047 
 }
2048 2048
2049 2049 
 // BLT offset
2050 
-static INSN_REGPARM void thumbDB(u32 opcode)
2050 
+static INSN_REGPARM void thumbDB(uint32_t opcode)
2051 2051 
 {
2052 2052 
   UPDATE_OLDREG;
2053 2053 
   clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2054 2054 
   if(N_FLAG != V_FLAG) {
2055 
-    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
2055 
+    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
2056 2056 
     armNextPC = reg[15].I;
2057 2057 
     reg[15].I += 2;
2058 2058 
     THUMB_PREFETCH;
... ... 
@@ -2062,12 +2062,12 @@ static INSN_REGPARM void thumbDB(u32 opcode)
2062 2062 
 }
2063 2063
2064 2064 
 // BGT offset
2065 
-static INSN_REGPARM void thumbDC(u32 opcode)
2065 
+static INSN_REGPARM void thumbDC(uint32_t opcode)
2066 2066 
 {
2067 2067 
   UPDATE_OLDREG;
2068 2068 
   clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2069 2069 
   if(!Z_FLAG && (N_FLAG == V_FLAG)) {
2070 
-    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
2070 
+    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
2071 2071 
     armNextPC = reg[15].I;
2072 2072 
     reg[15].I += 2;
2073 2073 
     THUMB_PREFETCH;
... ... 
@@ -2077,12 +2077,12 @@ static INSN_REGPARM void thumbDC(u32 opcode)
2077 2077 
 }
2078 2078
2079 2079 
 // BLE offset
2080 
-static INSN_REGPARM void thumbDD(u32 opcode)
2080 
+static INSN_REGPARM void thumbDD(uint32_t opcode)
2081 2081 
 {
2082 2082 
   UPDATE_OLDREG;
2083 2083 
   clockTicks = codeTicksAccessSeq16(armNextPC);
2084 2084 
   if(Z_FLAG || (N_FLAG != V_FLAG)) {
2085 
-    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
2085 
+    reg[15].I += ((int8_t)(opcode & 0xFF)) << 1;
2086 2086 
     armNextPC = reg[15].I;
2087 2087 
     reg[15].I += 2;
2088 2088 
     THUMB_PREFETCH;
... ... 
@@ -2094,9 +2094,9 @@ static INSN_REGPARM void thumbDD(u32 opcode)
2094 2094 
 // SWI, B, BL /////////////////////////////////////////////////////////////
2095 2095
2096 2096 
 // SWI #comment
2097 
-static INSN_REGPARM void thumbDF(u32 opcode)
2097 
+static INSN_REGPARM void thumbDF(uint32_t opcode)
2098 2098 
 {
2099 
-  u32 address = 0;
2099 
+  uint32_t address = 0;
2100 2100 
   //clockTicks = codeTicksAccessSeq16(address)*2 + codeTicksAccess16(address)+3;
2101 2101 
   clockTicks = 3;
2102 2102 
   busPrefetchCount=0;
... ... 
@@ -2104,7 +2104,7 @@ static INSN_REGPARM void thumbDF(u32 opcode)
2104 2104 
 }
2105 2105
2106 2106 
 // B offset
2107 
-static INSN_REGPARM void thumbE0(u32 opcode)
2107 
+static INSN_REGPARM void thumbE0(uint32_t opcode)
2108 2108 
 {
2109 2109 
   int offset = (opcode & 0x3FF) << 1;
2110 2110 
   if(opcode & 0x0400)
... ... 
@@ -2118,7 +2118,7 @@ static INSN_REGPARM void thumbE0(u32 opcode)
2118 2118 
 }
2119 2119
2120 2120 
 // BLL #offset (forward)
2121 
-static INSN_REGPARM void thumbF0(u32 opcode)
2121 
+static INSN_REGPARM void thumbF0(uint32_t opcode)
2122 2122 
 {
2123 2123 
   int offset = (opcode & 0x7FF);
2124 2124 
   reg[14].I = reg[15].I + (offset << 12);
... ... 
@@ -2126,7 +2126,7 @@ static INSN_REGPARM void thumbF0(u32 opcode)
2126 2126 
 }
2127 2127
2128 2128 
 // BLL #offset (backward)
2129 
-static INSN_REGPARM void thumbF4(u32 opcode)
2129 
+static INSN_REGPARM void thumbF4(uint32_t opcode)
2130 2130 
 {
2131 2131 
   int offset = (opcode & 0x7FF);
2132 2132 
   reg[14].I = reg[15].I + ((offset << 12) | 0xFF800000);
... ... 
@@ -2134,10 +2134,10 @@ static INSN_REGPARM void thumbF4(u32 opcode)
2134 2134 
 }
2135 2135
2136 2136 
 // BLH #offset
2137 
-static INSN_REGPARM void thumbF8(u32 opcode)
2137 
+static INSN_REGPARM void thumbF8(uint32_t opcode)
2138 2138 
 {
2139 2139 
   int offset = (opcode & 0x7FF);
2140 
-  u32 temp = reg[15].I-2;
2140 
+  uint32_t temp = reg[15].I-2;
2141 2141 
   reg[15].I = (reg[14].I + (offset<<1))&0xFFFFFFFE;
2142 2142 
   armNextPC = reg[15].I;
2143 2143 
   reg[15].I += 2;
... ... 
@@ -2149,7 +2149,7 @@ static INSN_REGPARM void thumbF8(u32 opcode)
2149 2149
2150 2150 
 // Instruction table //////////////////////////////////////////////////////
2151 2151
2152 
-typedef INSN_REGPARM void (*insnfunc_t)(u32 opcode);
2152 
+typedef INSN_REGPARM void (*insnfunc_t)(uint32_t opcode);
2153 2153 
 #define thumbUI thumbUnknownInsn
2154 2154 
 #ifdef BKPT_SUPPORT
2155 2155 
  #define thumbBP thumbBreakpoint
... ... 
@@ -2299,14 +2299,14 @@ int thumbExecute()
2299 2299 
     //if ((armNextPC & 0x0803FFFF) == 0x08020000)
2300 2300 
     //    busPrefetchCount=0x100;
2301 2301
2302 
-    u32 opcode = cpuPrefetch[0];
2302 
+    uint32_t opcode = cpuPrefetch[0];
2303 2303 
     cpuPrefetch[0] = cpuPrefetch[1];
2304 2304
2305 2305 
     busPrefetch = false;
2306 2306 
     if (busPrefetchCount & 0xFFFFFF00)
2307 2307 
       busPrefetchCount = 0x100 | (busPrefetchCount & 0xFF);
2308 2308 
     clockTicks = 0;
2309 
-    u32 oldArmNextPC = armNextPC;
2309 
+    uint32_t oldArmNextPC = armNextPC;
2310 2310 
 #ifndef FINAL_VERSION
2311 2311 
     if(armNextPC == stop) {
2312 2312 
       armNextPC++;
Browse code

Removed the save state loading from the 2SF player and updated the VBA-M code to the latest revision.

Naram Qashat authored on 2013/04/12 20:27:27
Showing 1 changed files
src/in_gsf/vbam/gba/GBA-thumb.cpp
History View file @ 3e0122a
... ... 
@@ -1417,10 +1417,18 @@ static INSN_REGPARM void thumb45_3(u32 opcode)
1417 1417 
   CMP_RD_RS;
1418 1418 
 }
1419 1419
1420 
+// MOV Rd, Rs
1421 
+static INSN_REGPARM void thumb46_0(u32 opcode)
1422 
+{
1423 
+        reg[opcode&7].I = reg[((opcode>>3)&7)].I;
1424 
+        clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1425 
+}
1426 
+
1420 1427 
 // MOV Rd, Hs
1421 1428 
 static INSN_REGPARM void thumb46_1(u32 opcode)
1422 1429 
 {
1423 1430 
   reg[opcode&7].I = reg[((opcode>>3)&7)+8].I;
1431 
+  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1424 1432 
 }
1425 1433
1426 1434 
 // MOV Hd, Rs
... ... 
@@ -1467,16 +1475,14 @@ static INSN_REGPARM void thumb47(u32 opcode)
1467 1475 
     armNextPC = reg[15].I;
1468 1476 
     reg[15].I += 2;
1469 1477 
     THUMB_PREFETCH;
1470 
-    clockTicks = codeTicksAccessSeq16(armNextPC)
1471 
-        + codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 3;
1478 
+    clockTicks = codeTicksAccessSeq16(armNextPC)*2 + codeTicksAccess16(armNextPC) + 3;
1472 1479 
   } else {
1473 1480 
     armState = true;
1474 1481 
     reg[15].I &= 0xFFFFFFFC;
1475 1482 
     armNextPC = reg[15].I;
1476 1483 
     reg[15].I += 4;
1477 1484 
     ARM_PREFETCH;
1478 
-    clockTicks = codeTicksAccessSeq32(armNextPC)
1479 
-        + codeTicksAccessSeq32(armNextPC) + codeTicksAccess32(armNextPC) + 3;
1485 
+    clockTicks = codeTicksAccessSeq32(armNextPC)*2 + codeTicksAccess32(armNextPC) + 3;
1480 1486 
   }
1481 1487 
 }
1482 1488
... ... 
@@ -1570,7 +1576,7 @@ static INSN_REGPARM void thumb5E(u32 opcode)
1570 1576 
   if (busPrefetchCount == 0)
1571 1577 
     busPrefetch = busPrefetchEnable;
1572 1578 
   u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1573 
-  reg[opcode&7].I = (s16)CPUReadHalfWordSigned(address);
1579 
+  reg[opcode&7].I = (u32)CPUReadHalfWordSigned(address);
1574 1580 
   clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1575 1581 
 }
1576 1582
... ... 
@@ -1663,6 +1669,7 @@ static INSN_REGPARM void thumbA0(u32 opcode)
1663 1669 
 {
1664 1670 
   u8 regist = (opcode >> 8) & 7;
1665 1671 
   reg[regist].I = (reg[15].I & 0xFFFFFFFC) + ((opcode&255)<<2);
1672 
+  clockTicks = 1 + codeTicksAccess16(armNextPC);
1666 1673 
 }
1667 1674
1668 1675 
 // ADD R0~R7, SP, Imm
... ... 
@@ -1670,6 +1677,7 @@ static INSN_REGPARM void thumbA8(u32 opcode)
1670 1677 
 {
1671 1678 
   u8 regist = (opcode >> 8) & 7;
1672 1679 
   reg[regist].I = reg[13].I + ((opcode&255)<<2);
1680 
+  clockTicks = 1 + codeTicksAccess16(armNextPC);
1673 1681 
 }
1674 1682
1675 1683 
 // ADD SP, Imm
... ... 
@@ -1679,6 +1687,7 @@ static INSN_REGPARM void thumbB0(u32 opcode)
1679 1687 
   if(opcode & 0x80)
1680 1688 
     offset = -offset;
1681 1689 
   reg[13].I += offset;
1690 
+  clockTicks = 1 + codeTicksAccess16(armNextPC);
1682 1691 
 }
1683 1692
1684 1693 
 // Push and pop ///////////////////////////////////////////////////////////
... ... 
@@ -1876,13 +1885,13 @@ static INSN_REGPARM void thumbC8(u32 opcode)
1876 1885 
 static INSN_REGPARM void thumbD0(u32 opcode)
1877 1886 
 {
1878 1887 
   UPDATE_OLDREG;
1888 
+  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1879 1889 
   if(Z_FLAG) {
1880 1890 
     reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1881 1891 
     armNextPC = reg[15].I;
1882 1892 
     reg[15].I += 2;
1883 1893 
     THUMB_PREFETCH;
1884 
-    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
1885 
-        codeTicksAccess16(armNextPC)+3;
1894 
+    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1886 1895 
     busPrefetchCount=0;
1887 1896 
   }
1888 1897 
 }
... ... 
@@ -1891,13 +1900,13 @@ static INSN_REGPARM void thumbD0(u32 opcode)
1891 1900 
 static INSN_REGPARM void thumbD1(u32 opcode)
1892 1901 
 {
1893 1902 
   UPDATE_OLDREG;
1903 
+  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1894 1904 
   if(!Z_FLAG) {
1895 1905 
     reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1896 1906 
     armNextPC = reg[15].I;
1897 1907 
     reg[15].I += 2;
1898 1908 
     THUMB_PREFETCH;
1899 
-    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
1900 
-        codeTicksAccess16(armNextPC)+3;
1909 
+    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1901 1910 
     busPrefetchCount=0;
1902 1911 
   }
1903 1912 
 }
... ... 
@@ -1906,13 +1915,13 @@ static INSN_REGPARM void thumbD1(u32 opcode)
1906 1915 
 static INSN_REGPARM void thumbD2(u32 opcode)
1907 1916 
 {
1908 1917 
   UPDATE_OLDREG;
1918 
+  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1909 1919 
   if(C_FLAG) {
1910 1920 
     reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1911 1921 
     armNextPC = reg[15].I;
1912 1922 
     reg[15].I += 2;
1913 1923 
     THUMB_PREFETCH;
1914 
-    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
1915 
-        codeTicksAccess16(armNextPC)+3;
1924 
+    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1916 1925 
     busPrefetchCount=0;
1917 1926 
   }
1918 1927 
 }
... ... 
@@ -1921,13 +1930,13 @@ static INSN_REGPARM void thumbD2(u32 opcode)
1921 1930 
 static INSN_REGPARM void thumbD3(u32 opcode)
1922 1931 
 {
1923 1932 
   UPDATE_OLDREG;
1933 
+  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1924 1934 
   if(!C_FLAG) {
1925 1935 
     reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1926 1936 
     armNextPC = reg[15].I;
1927 1937 
     reg[15].I += 2;
1928 1938 
     THUMB_PREFETCH;
1929 
-    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
1930 
-        codeTicksAccess16(armNextPC)+3;
1939 
+    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1931 1940 
     busPrefetchCount=0;
1932 1941 
   }
1933 1942 
 }
... ... 
@@ -1936,13 +1945,13 @@ static INSN_REGPARM void thumbD3(u32 opcode)
1936 1945 
 static INSN_REGPARM void thumbD4(u32 opcode)
1937 1946 
 {
1938 1947 
   UPDATE_OLDREG;
1948 
+  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1939 1949 
   if(N_FLAG) {
1940 1950 
     reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1941 1951 
     armNextPC = reg[15].I;
1942 1952 
     reg[15].I += 2;
1943 1953 
     THUMB_PREFETCH;
1944 
-    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
1945 
-        codeTicksAccess16(armNextPC)+3;
1954 
+    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1946 1955 
     busPrefetchCount=0;
1947 1956 
   }
1948 1957 
 }
... ... 
@@ -1951,13 +1960,13 @@ static INSN_REGPARM void thumbD4(u32 opcode)
1951 1960 
 static INSN_REGPARM void thumbD5(u32 opcode)
1952 1961 
 {
1953 1962 
   UPDATE_OLDREG;
1963 
+  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1954 1964 
   if(!N_FLAG) {
1955 1965 
     reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1956 1966 
     armNextPC = reg[15].I;
1957 1967 
     reg[15].I += 2;
1958 1968 
     THUMB_PREFETCH;
1959 
-    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
1960 
-        codeTicksAccess16(armNextPC)+3;
1969 
+    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1961 1970 
     busPrefetchCount=0;
1962 1971 
   }
1963 1972 
 }
... ... 
@@ -1966,13 +1975,13 @@ static INSN_REGPARM void thumbD5(u32 opcode)
1966 1975 
 static INSN_REGPARM void thumbD6(u32 opcode)
1967 1976 
 {
1968 1977 
   UPDATE_OLDREG;
1978 
+  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1969 1979 
   if(V_FLAG) {
1970 1980 
     reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1971 1981 
     armNextPC = reg[15].I;
1972 1982 
     reg[15].I += 2;
1973 1983 
     THUMB_PREFETCH;
1974 
-    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
1975 
-        codeTicksAccess16(armNextPC)+3;
1984 
+    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1976 1985 
     busPrefetchCount=0;
1977 1986 
   }
1978 1987 
 }
... ... 
@@ -1981,13 +1990,13 @@ static INSN_REGPARM void thumbD6(u32 opcode)
1981 1990 
 static INSN_REGPARM void thumbD7(u32 opcode)
1982 1991 
 {
1983 1992 
   UPDATE_OLDREG;
1993 
+  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1984 1994 
   if(!V_FLAG) {
1985 1995 
     reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1986 1996 
     armNextPC = reg[15].I;
1987 1997 
     reg[15].I += 2;
1988 1998 
     THUMB_PREFETCH;
1989 
-    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
1990 
-        codeTicksAccess16(armNextPC)+3;
1999 
+    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
1991 2000 
     busPrefetchCount=0;
1992 2001 
   }
1993 2002 
 }
... ... 
@@ -1996,13 +2005,13 @@ static INSN_REGPARM void thumbD7(u32 opcode)
1996 2005 
 static INSN_REGPARM void thumbD8(u32 opcode)
1997 2006 
 {
1998 2007 
   UPDATE_OLDREG;
2008 
+  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
1999 2009 
   if(C_FLAG && !Z_FLAG) {
2000 2010 
     reg[15].I += ((s8)(opcode & 0xFF)) << 1;
2001 2011 
     armNextPC = reg[15].I;
2002 2012 
     reg[15].I += 2;
2003 2013 
     THUMB_PREFETCH;
2004 
-    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
2005 
-        codeTicksAccess16(armNextPC)+3;
2014 
+    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
2006 2015 
     busPrefetchCount=0;
2007 2016 
   }
2008 2017 
 }
... ... 
@@ -2011,13 +2020,13 @@ static INSN_REGPARM void thumbD8(u32 opcode)
2011 2020 
 static INSN_REGPARM void thumbD9(u32 opcode)
2012 2021 
 {
2013 2022 
   UPDATE_OLDREG;
2023 
+  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2014 2024 
   if(!C_FLAG || Z_FLAG) {
2015 2025 
     reg[15].I += ((s8)(opcode & 0xFF)) << 1;
2016 2026 
     armNextPC = reg[15].I;
2017 2027 
     reg[15].I += 2;
2018 2028 
     THUMB_PREFETCH;
2019 
-    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
2020 
-        codeTicksAccess16(armNextPC)+3;
2029 
+    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
2021 2030 
     busPrefetchCount=0;
2022 2031 
   }
2023 2032 
 }
... ... 
@@ -2026,13 +2035,13 @@ static INSN_REGPARM void thumbD9(u32 opcode)
2026 2035 
 static INSN_REGPARM void thumbDA(u32 opcode)
2027 2036 
 {
2028 2037 
   UPDATE_OLDREG;
2038 
+  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2029 2039 
   if(N_FLAG == V_FLAG) {
2030 2040 
     reg[15].I += ((s8)(opcode & 0xFF)) << 1;
2031 2041 
     armNextPC = reg[15].I;
2032 2042 
     reg[15].I += 2;
2033 2043 
     THUMB_PREFETCH;
2034 
-    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
2035 
-        codeTicksAccess16(armNextPC)+3;
2044 
+    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
2036 2045 
     busPrefetchCount=0;
2037 2046 
   }
2038 2047 
 }
... ... 
@@ -2041,13 +2050,13 @@ static INSN_REGPARM void thumbDA(u32 opcode)
2041 2050 
 static INSN_REGPARM void thumbDB(u32 opcode)
2042 2051 
 {
2043 2052 
   UPDATE_OLDREG;
2053 
+  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2044 2054 
   if(N_FLAG != V_FLAG) {
2045 2055 
     reg[15].I += ((s8)(opcode & 0xFF)) << 1;
2046 2056 
     armNextPC = reg[15].I;
2047 2057 
     reg[15].I += 2;
2048 2058 
     THUMB_PREFETCH;
2049 
-    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
2050 
-        codeTicksAccess16(armNextPC)+3;
2059 
+    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
2051 2060 
     busPrefetchCount=0;
2052 2061 
   }
2053 2062 
 }
... ... 
@@ -2056,13 +2065,13 @@ static INSN_REGPARM void thumbDB(u32 opcode)
2056 2065 
 static INSN_REGPARM void thumbDC(u32 opcode)
2057 2066 
 {
2058 2067 
   UPDATE_OLDREG;
2068 
+  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2059 2069 
   if(!Z_FLAG && (N_FLAG == V_FLAG)) {
2060 2070 
     reg[15].I += ((s8)(opcode & 0xFF)) << 1;
2061 2071 
     armNextPC = reg[15].I;
2062 2072 
     reg[15].I += 2;
2063 2073 
     THUMB_PREFETCH;
2064 
-    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
2065 
-        codeTicksAccess16(armNextPC)+3;
2074 
+    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
2066 2075 
     busPrefetchCount=0;
2067 2076 
   }
2068 2077 
 }
... ... 
@@ -2071,13 +2080,13 @@ static INSN_REGPARM void thumbDC(u32 opcode)
2071 2080 
 static INSN_REGPARM void thumbDD(u32 opcode)
2072 2081 
 {
2073 2082 
   UPDATE_OLDREG;
2083 
+  clockTicks = codeTicksAccessSeq16(armNextPC);
2074 2084 
   if(Z_FLAG || (N_FLAG != V_FLAG)) {
2075 2085 
     reg[15].I += ((s8)(opcode & 0xFF)) << 1;
2076 2086 
     armNextPC = reg[15].I;
2077 2087 
     reg[15].I += 2;
2078 2088 
     THUMB_PREFETCH;
2079 
-    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
2080 
-        codeTicksAccess16(armNextPC)+3;
2089 
+    clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
2081 2090 
     busPrefetchCount=0;
2082 2091 
   }
2083 2092 
 }
... ... 
@@ -2088,8 +2097,8 @@ static INSN_REGPARM void thumbDD(u32 opcode)
2088 2097 
 static INSN_REGPARM void thumbDF(u32 opcode)
2089 2098 
 {
2090 2099 
   u32 address = 0;
2091 
-  clockTicks = codeTicksAccessSeq16(address) + codeTicksAccessSeq16(address) +
2092 
-      codeTicksAccess16(address)+3;
2100 
+  //clockTicks = codeTicksAccessSeq16(address)*2 + codeTicksAccess16(address)+3;
2101 
+  clockTicks = 3;
2093 2102 
   busPrefetchCount=0;
2094 2103 
   CPUSoftwareInterrupt(opcode & 0xFF);
2095 2104 
 }
... ... 
@@ -2104,8 +2113,7 @@ static INSN_REGPARM void thumbE0(u32 opcode)
2104 2113 
   armNextPC = reg[15].I;
2105 2114 
   reg[15].I += 2;
2106 2115 
   THUMB_PREFETCH;
2107 
-  clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
2108 
-      codeTicksAccess16(armNextPC) + 3;
2116 
+  clockTicks = codeTicksAccessSeq16(armNextPC)*2 + codeTicksAccess16(armNextPC)+3;
2109 2117 
   busPrefetchCount=0;
2110 2118 
 }
2111 2119
... ... 
@@ -2135,8 +2143,7 @@ static INSN_REGPARM void thumbF8(u32 opcode)
2135 2143 
   reg[15].I += 2;
2136 2144 
   reg[14].I = temp|1;
2137 2145 
   THUMB_PREFETCH;
2138 
-  clockTicks = codeTicksAccessSeq16(armNextPC) +
2139 
-      codeTicksAccess16(armNextPC) + codeTicksAccessSeq16(armNextPC) + 3;
2146 
+  clockTicks = codeTicksAccessSeq16(armNextPC)*2 + codeTicksAccess16(armNextPC) + 3;
2140 2147 
   busPrefetchCount = 0;
2141 2148 
 }
2142 2149
... ... 
@@ -2185,7 +2192,7 @@ static insnfunc_t thumbInsnTable[1024] = {
2185 2192 
   thumb40_0,thumb40_1,thumb40_2,thumb40_3,thumb41_0,thumb41_1,thumb41_2,thumb41_3,  // 40
2186 2193 
   thumb42_0,thumb42_1,thumb42_2,thumb42_3,thumb43_0,thumb43_1,thumb43_2,thumb43_3,
2187 2194 
   thumbUI,thumb44_1,thumb44_2,thumb44_3,thumbUI,thumb45_1,thumb45_2,thumb45_3,
2188 
-  thumbUI,thumb46_1,thumb46_2,thumb46_3,thumb47,thumb47,thumbUI,thumbUI,
2195 
+  thumb46_0,thumb46_1,thumb46_2,thumb46_3,thumb47,thumb47,thumbUI,thumbUI,
2189 2196 
   thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,  // 48
2190 2197 
   thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,
2191 2198 
   thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,
Browse code

Import actual code.

Naram Qashat authored on 2013/03/26 02:41:19
Showing 1 changed files
src/in_gsf/vbam/gba/GBA-thumb.cpp
History View file @ bc076aa
1 1 
new file mode 100644
... ... 
@@ -0,0 +1,2323 @@
1 
+#include <stdio.h>
2 
+#include <stdlib.h>
3 
+#include <memory.h>
4 
+#include <stdarg.h>
5 
+#include <string.h>
6 
+
7 
+#include "GBA.h"
8 
+#include "GBAcpu.h"
9 
+#include "GBAinline.h"
10 
+#include "Globals.h"
11 
+//#include "EEprom.h"
12 
+//#include "Flash.h"
13 
+#include "Sound.h"
14 
+//#include "Sram.h"
15 
+#include "bios.h"
16 
+//#include "Cheats.h"
17 
+//#include "../NLS.h"
18 
+//#include "elf.h"
19 
+//#include "../Util.h"
20 
+//#include "../System.h"
21 
+//#include "agbprint.h"
22 
+#ifdef PROFILING
23 
+#include "prof/prof.h"
24 
+#endif
25 
+
26 
+#ifdef _MSC_VER
27 
+#define snprintf _snprintf
28 
+#endif
29 
+
30 
+///////////////////////////////////////////////////////////////////////////
31 
+
32 
+static int clockTicks;
33 
+
34 
+static INSN_REGPARM void thumbUnknownInsn(u32 opcode)
35 
+{
36 
+#ifdef GBA_LOGGING
37 
+  if(systemVerbose & VERBOSE_UNDEFINED)
38 
+    log("Undefined THUMB instruction %04x at %08x\n", opcode, armNextPC-2);
39 
+#endif
40 
+  CPUUndefinedException();
41 
+}
42 
+
43 
+#ifdef BKPT_SUPPORT
44 
+static INSN_REGPARM void thumbBreakpoint(u32 opcode)
45 
+{
46 
+  reg[15].I -= 2;
47 
+  armNextPC -= 2;
48 
+  dbgSignal(5, opcode & 255);
49 
+  clockTicks = -1;
50 
+}
51 
+#endif
52 
+
53 
+// Common macros //////////////////////////////////////////////////////////
54 
+
55 
+#ifdef BKPT_SUPPORT
56 
+# define THUMB_CONSOLE_OUTPUT(a,b) do {                     \
57 
+    if ((opcode == 0x4000) && (reg[0].I == 0xC0DED00D)) {   \
58 
+      dbgOutput((a), (b));                                  \
59 
+    }                                                       \
60 
+} while (0)
61 
+# define UPDATE_OLDREG do {                                 \
62 
+    if (debugger_last) {                                    \
63 
+        snprintf(oldbuffer, sizeof(oldbuffer), "%08X",      \
64 
+                 armState ? reg[15].I - 4 : reg[15].I - 2); \
65 
+        int i;						    \
66 
+        for (i = 0; i < 18; i++) {                          \
67 
+            oldreg[i] = reg[i].I;                           \
68 
+        }                                                   \
69 
+    }                                                       \
70 
+} while (0)
71 
+#else
72 
+# define THUMB_CONSOLE_OUTPUT(a,b)
73 
+# define UPDATE_OLDREG
74 
+#endif
75 
+
76 
+#define NEG(i) ((i) >> 31)
77 
+#define POS(i) ((~(i)) >> 31)
78 
+
79 
+#ifndef C_CORE
80 
+#ifdef __GNUC__
81 
+#ifdef __POWERPC__
82 
+  #define ADD_RD_RS_RN(N) \
83 
+            {										\
84 
+                register int Flags;					\
85 
+                register int Result;				\
86 
+                asm volatile("addco. %0, %2, %3\n"	\
87 
+                            "mcrxr cr1\n"			\
88 
+                            "mfcr %1\n"				\
89 
+                            : "=r" (Result), 		\
90 
+                              "=r" (Flags)			\
91 
+                            : "r" (reg[source].I), 	\
92 
+                              "r" (reg[N].I)		\
93 
+                            );						\
94 
+                reg[dest].I = Result;				\
95 
+                Z_FLAG = (Flags >> 29) & 1;			\
96 
+                N_FLAG = (Flags >> 31) & 1;			\
97 
+                C_FLAG = (Flags >> 25) & 1;			\
98 
+                V_FLAG = (Flags >> 26) & 1;			\
99 
+            }
100 
+  #define ADD_RD_RS_O3(N) \
101 
+            {										\
102 
+                register int Flags;					\
103 
+                register int Result;				\
104 
+                asm volatile("addco. %0, %2, %3\n"	\
105 
+                            "mcrxr cr1\n"			\
106 
+                            "mfcr %1\n"				\
107 
+                            : "=r" (Result), 		\
108 
+                              "=r" (Flags)			\
109 
+                            : "r" (reg[source].I), 	\
110 
+                              "r" (N)				\
111 
+                            );						\
112 
+                reg[dest].I = Result;				\
113 
+                Z_FLAG = (Flags >> 29) & 1;			\
114 
+                N_FLAG = (Flags >> 31) & 1;			\
115 
+                C_FLAG = (Flags >> 25) & 1;			\
116 
+                V_FLAG = (Flags >> 26) & 1;			\
117 
+            }
118 
+  #define ADD_RD_RS_O3_0 ADD_RD_RS_O3
119 
+  #define ADD_RN_O8(d) \
120 
+            {\
121 
+                register int Flags;					\
122 
+                register int Result;				\
123 
+                asm volatile("addco. %0, %2, %3\n"	\
124 
+                            "mcrxr cr1\n"			\
125 
+                            "mfcr %1\n"				\
126 
+                            : "=r" (Result), 		\
127 
+                              "=r" (Flags)			\
128 
+                            : "r" (reg[(d)].I), 	\
129 
+                              "r" (opcode & 255)	\
130 
+                            );						\
131 
+                reg[(d)].I = Result;				\
132 
+                Z_FLAG = (Flags >> 29) & 1;			\
133 
+                N_FLAG = (Flags >> 31) & 1;			\
134 
+                C_FLAG = (Flags >> 25) & 1;			\
135 
+                V_FLAG = (Flags >> 26) & 1;			\
136 
+            }
137 
+  #define CMN_RD_RS \
138 
+            {\
139 
+                register int Flags;					\
140 
+                register int Result;				\
141 
+                asm volatile("addco. %0, %2, %3\n"	\
142 
+                            "mcrxr cr1\n"			\
143 
+                            "mfcr %1\n"				\
144 
+                            : "=r" (Result), 		\
145 
+                              "=r" (Flags)			\
146 
+                            : "r" (reg[dest].I), 	\
147 
+                              "r" (value)			\
148 
+                            );						\
149 
+                Z_FLAG = (Flags >> 29) & 1;			\
150 
+                N_FLAG = (Flags >> 31) & 1;			\
151 
+                C_FLAG = (Flags >> 25) & 1;			\
152 
+                V_FLAG = (Flags >> 26) & 1;			\
153 
+            }
154 
+  #define ADC_RD_RS \
155 
+            {\
156 
+                register int Flags;					\
157 
+                register int Result;				\
158 
+                asm volatile("mtspr 1, %4\n"		\ /* reg 1 is xer */
159 
+                             "addeo. %0, %2, %3\n"	\
160 
+                             "mcrxr cr1\n"			\
161 
+                             "mfcr	%1\n"			\
162 
+                             : "=r" (Result),		\
163 
+                               "=r" (Flags)			\
164 
+                             : "r" (reg[dest].I),	\
165 
+                               "r" (value),			\
166 
+                               "r" (C_FLAG << 29)	\
167 
+                             );						\
168 
+                reg[dest].I = Result;				\
169 
+                Z_FLAG = (Flags >> 29) & 1;			\
170 
+                N_FLAG = (Flags >> 31) & 1;			\
171 
+                C_FLAG = (Flags >> 25) & 1;			\
172 
+                V_FLAG = (Flags >> 26) & 1;			\
173 
+            }
174 
+  #define SUB_RD_RS_RN(N) \
175 
+            {\
176 
+                register int Flags;					\
177 
+                register int Result;				\
178 
+                asm volatile("subco. %0, %2, %3\n"	\
179 
+                            "mcrxr cr1\n"			\
180 
+                            "mfcr %1\n"				\
181 
+                            : "=r" (Result), 		\
182 
+                              "=r" (Flags)			\
183 
+                            : "r" (reg[source].I), 	\
184 
+                              "r" (reg[N].I)		\
185 
+                            );						\
186 
+                reg[dest].I = Result;				\
187 
+                Z_FLAG = (Flags >> 29) & 1;			\
188 
+                N_FLAG = (Flags >> 31) & 1;			\
189 
+                C_FLAG = (Flags >> 25) & 1;			\
190 
+                V_FLAG = (Flags >> 26) & 1;			\
191 
+            }
192 
+  #define SUB_RD_RS_O3(N) \
193 
+            {\
194 
+                register int Flags;					\
195 
+                register int Result;				\
196 
+                asm volatile("subco. %0, %2, %3\n"	\
197 
+                            "mcrxr cr1\n"			\
198 
+                            "mfcr %1\n"				\
199 
+                            : "=r" (Result), 		\
200 
+                              "=r" (Flags)			\
201 
+                            : "r" (reg[source].I), 	\
202 
+                              "r" (N)				\
203 
+                            );						\
204 
+                reg[dest].I = Result;				\
205 
+                Z_FLAG = (Flags >> 29) & 1;			\
206 
+                N_FLAG = (Flags >> 31) & 1;			\
207 
+                C_FLAG = (Flags >> 25) & 1;			\
208 
+                V_FLAG = (Flags >> 26) & 1;			\
209 
+            }
210 
+  #define SUB_RD_RS_O3_0 SUB_RD_RS_O3
211 
+  #define SUB_RN_O8(d) \
212 
+            {\
213 
+                register int Flags;					\
214 
+                register int Result;				\
215 
+                asm volatile("subco. %0, %2, %3\n"	\
216 
+                            "mcrxr cr1\n"			\
217 
+                            "mfcr %1\n"				\
218 
+                            : "=r" (Result), 		\
219 
+                              "=r" (Flags)			\
220 
+                            : "r" (reg[(d)].I), 	\
221 
+                              "r" (opcode & 255)	\
222 
+                            );						\
223 
+                reg[(d)].I = Result;				\
224 
+                Z_FLAG = (Flags >> 29) & 1;			\
225 
+                N_FLAG = (Flags >> 31) & 1;			\
226 
+                C_FLAG = (Flags >> 25) & 1;			\
227 
+                V_FLAG = (Flags >> 26) & 1;			\
228 
+            }
229 
+  #define CMP_RN_O8(d) \
230 
+            {\
231 
+                register int Flags;					\
232 
+                register int Result;				\
233 
+                asm volatile("subco. %0, %2, %3\n"	\
234 
+                            "mcrxr cr1\n"			\
235 
+                            "mfcr %1\n"				\
236 
+                            : "=r" (Result), 		\
237 
+                              "=r" (Flags)			\
238 
+                            : "r" (reg[(d)].I), 	\
239 
+                              "r" (opcode & 255)	\
240 
+                            );						\
241 
+                Z_FLAG = (Flags >> 29) & 1;			\
242 
+                N_FLAG = (Flags >> 31) & 1;			\
243 
+                C_FLAG = (Flags >> 25) & 1;			\
244 
+                V_FLAG = (Flags >> 26) & 1;			\
245 
+            }
246 
+  #define SBC_RD_RS \
247 
+            {\
248 
+                register int Flags;					\
249 
+                register int Result;				\
250 
+                asm volatile("mtspr 1, %4\n"		\ /* reg 1 is xer */
251 
+                             "subfeo. %0, %3, %2\n"	\
252 
+                             "mcrxr cr1\n"			\
253 
+                             "mfcr	%1\n"			\
254 
+                             : "=r" (Result),		\
255 
+                               "=r" (Flags)			\
256 
+                             : "r" (reg[dest].I),	\
257 
+                               "r" (value),			\
258 
+                               "r" (C_FLAG << 29) 	\
259 
+                             );						\
260 
+                reg[dest].I = Result;				\
261 
+                Z_FLAG = (Flags >> 29) & 1;			\
262 
+                N_FLAG = (Flags >> 31) & 1;			\
263 
+                C_FLAG = (Flags >> 25) & 1;			\
264 
+                V_FLAG = (Flags >> 26) & 1;			\
265 
+            }
266 
+  #define NEG_RD_RS \
267 
+            {\
268 
+                register int Flags;					\
269 
+                register int Result;				\
270 
+                asm volatile("subfco. %0, %2, %3\n"	\
271 
+                            "mcrxr cr1\n"			\
272 
+                            "mfcr %1\n"				\
273 
+                            : "=r" (Result), 		\
274 
+                              "=r" (Flags)			\
275 
+                            : "r" (reg[source].I), 	\
276 
+                              "r" (0)				\
277 
+                            );						\
278 
+                reg[dest].I = Result;				\
279 
+                Z_FLAG = (Flags >> 29) & 1;			\
280 
+                N_FLAG = (Flags >> 31) & 1;			\
281 
+                C_FLAG = (Flags >> 25) & 1;			\
282 
+                V_FLAG = (Flags >> 26) & 1;			\
283 
+            }
284 
+  #define CMP_RD_RS \
285 
+            {\
286 
+                register int Flags;					\
287 
+                register int Result;				\
288 
+                asm volatile("subco. %0, %2, %3\n"	\
289 
+                            "mcrxr cr1\n"			\
290 
+                            "mfcr %1\n"				\
291 
+                            : "=r" (Result), 		\
292 
+                              "=r" (Flags)			\
293 
+                            : "r" (reg[dest].I), 	\
294 
+                              "r" (value)			\
295 
+                            );						\
296 
+                Z_FLAG = (Flags >> 29) & 1;			\
297 
+                N_FLAG = (Flags >> 31) & 1;			\
298 
+                C_FLAG = (Flags >> 25) & 1;			\
299 
+                V_FLAG = (Flags >> 26) & 1;			\
300 
+            }
301 
+#else
302 
+  #define EMIT1(op,arg)        #op" "arg"; "
303 
+  #define EMIT2(op,src,dest)   #op" "src", "dest"; "
304 
+  #define KONST(val)           "$"#val
305 
+  #define ASMVAR(cvar)         ASMVAR2 (__USER_LABEL_PREFIX__, cvar)
306 
+  #define ASMVAR2(prefix,cvar) STRING (prefix) cvar
307 
+  #define STRING(x)            #x
308 
+  #define VAR(var)             ASMVAR(#var)
309 
+  #define REGREF1(index)       ASMVAR("reg("index")")
310 
+  #define REGREF2(index,scale) ASMVAR("reg(,"index","#scale")")
311 
+  #define eax "%%eax"
312 
+  #define ecx "%%ecx"
313 
+  #define edx "%%edx"
314 
+  #define ADD_RN_O8(d) \
315 
+     asm ("andl $0xFF, %%eax;"\
316 
+          "addl %%eax, %0;"\
317 
+          EMIT1(setsb, VAR(N_FLAG)) \
318 
+          EMIT1(setzb, VAR(Z_FLAG)) \
319 
+          EMIT1(setcb, VAR(C_FLAG)) \
320 
+          EMIT1(setob, VAR(V_FLAG)) \
321 
+          : "=m" (reg[(d)].I));
322 
+  #define CMN_RD_RS \
323 
+     asm ("add %0, %1;"\
324 
+          EMIT1(setsb, VAR(N_FLAG)) \
325 
+          EMIT1(setzb, VAR(Z_FLAG)) \
326 
+          EMIT1(setcb, VAR(C_FLAG)) \
327 
+          EMIT1(setob, VAR(V_FLAG)) \
328 
+          : \
329 
+          : "r" (value), "r" (reg[dest].I):"1");
330 
+  #define ADC_RD_RS \
331 
+     asm (EMIT2(bt,KONST(0),VAR(C_FLAG)) \
332 
+          "adc %1, %%ebx;"\
333 
+          EMIT1(setsb, VAR(N_FLAG)) \
334 
+          EMIT1(setzb, VAR(Z_FLAG)) \
335 
+          EMIT1(setcb, VAR(C_FLAG)) \
336 
+          EMIT1(setob, VAR(V_FLAG)) \
337 
+          : "=b" (reg[dest].I)\
338 
+          : "r" (value), "b" (reg[dest].I));
339 
+  #define SUB_RN_O8(d) \
340 
+     asm ("andl $0xFF, %%eax;"\
341 
+          "subl %%eax, %0;"\
342 
+          EMIT1(setsb, VAR(N_FLAG)) \
343 
+          EMIT1(setzb, VAR(Z_FLAG)) \
344 
+          EMIT1(setncb, VAR(C_FLAG)) \
345 
+          EMIT1(setob, VAR(V_FLAG)) \
346 
+          : "=m" (reg[(d)].I));
347 
+  #define MOV_RN_O8(d) \
348 
+     asm ("andl $0xFF, %%eax;"\
349 
+          EMIT2(movb,KONST(0),VAR(N_FLAG)) \
350 
+          "movl %%eax, %0;"\
351 
+          EMIT1(setzb, VAR(Z_FLAG)) \
352 
+          : "=m" (reg[(d)].I));
353 
+  #define CMP_RN_O8(d) \
354 
+     asm ("andl $0xFF, %%eax;"\
355 
+          "cmpl %%eax, %0;"\
356 
+          EMIT1(setsb, VAR(N_FLAG)) \
357 
+          EMIT1(setzb, VAR(Z_FLAG)) \
358 
+          EMIT1(setncb, VAR(C_FLAG)) \
359 
+          EMIT1(setob, VAR(V_FLAG)) \
360 
+          : \
361 
+          : "m" (reg[(d)].I));
362 
+  #define SBC_RD_RS \
363 
+     asm volatile (EMIT2(bt,KONST(0),VAR(C_FLAG)) \
364 
+                   "cmc;"\
365 
+                   "sbb %1, %%ebx;"\
366 
+                   EMIT1(setsb, VAR(N_FLAG)) \
367 
+                   EMIT1(setzb, VAR(Z_FLAG)) \
368 
+                   EMIT1(setncb, VAR(C_FLAG)) \
369 
+                   EMIT1(setob, VAR(V_FLAG)) \
370 
+                   : "=b" (reg[dest].I)\
371 
+                   : "r" (value), "b" (reg[dest].I) : "cc", "memory");
372 
+  #define LSL_RD_RS \
373 
+         asm ("shl %%cl, %%eax;"\
374 
+              EMIT1(setcb, VAR(C_FLAG)) \
375 
+              : "=a" (value)\
376 
+              : "a" (reg[dest].I), "c" (value));
377 
+  #define LSR_RD_RS \
378 
+         asm ("shr %%cl, %%eax;"\
379 
+              EMIT1(setcb, VAR(C_FLAG)) \
380 
+              : "=a" (value)\
381 
+              : "a" (reg[dest].I), "c" (value));
382 
+  #define ASR_RD_RS \
383 
+         asm ("sar %%cl, %%eax;"\
384 
+              EMIT1(setcb, VAR(C_FLAG)) \
385 
+              : "=a" (value)\
386 
+              : "a" (reg[dest].I), "c" (value));
387 
+  #define ROR_RD_RS \
388 
+         asm ("ror %%cl, %%eax;"\
389 
+              EMIT1(setcb, VAR(C_FLAG)) \
390 
+              : "=a" (value)\
391 
+              : "a" (reg[dest].I), "c" (value));
392 
+  #define NEG_RD_RS \
393 
+     asm ("neg %%ebx;"\
394 
+          EMIT1(setsb, VAR(N_FLAG)) \
395 
+          EMIT1(setzb, VAR(Z_FLAG)) \
396 
+          EMIT1(setncb, VAR(C_FLAG)) \
397 
+          EMIT1(setob, VAR(V_FLAG)) \
398 
+          : "=b" (reg[dest].I)\
399 
+          : "b" (reg[source].I));
400 
+  #define CMP_RD_RS \
401 
+     asm ("sub %0, %1;"\
402 
+          EMIT1(setsb, VAR(N_FLAG)) \
403 
+          EMIT1(setzb, VAR(Z_FLAG)) \
404 
+          EMIT1(setncb, VAR(C_FLAG)) \
405 
+          EMIT1(setob, VAR(V_FLAG)) \
406 
+          : \
407 
+          : "r" (value), "r" (reg[dest].I):"1");
408 
+  #define IMM5_INSN(OP,N) \
409 
+     asm("movl %%eax,%%ecx;"         \
410 
+         "shrl $1,%%eax;"            \
411 
+         "andl $7,%%ecx;"            \
412 
+         "andl $0x1C,%%eax;"         \
413 
+         EMIT2(movl, REGREF1(eax), edx) \
414 
+         OP                          \
415 
+         EMIT1(setsb, VAR(N_FLAG)) \
416 
+         EMIT1(setzb, VAR(Z_FLAG)) \
417 
+         EMIT2(movl, edx, REGREF2(ecx,4)) \
418 
+         : : "i" (N))
419 
+  #define IMM5_INSN_0(OP)            \
420 
+     asm("movl %%eax,%%ecx;"         \
421 
+         "shrl $1,%%eax;"            \
422 
+         "andl $7,%%ecx;"            \
423 
+         "andl $0x1C,%%eax;"         \
424 
+         EMIT2(movl, REGREF1(eax), edx) \
425 
+         OP                          \
426 
+         EMIT1(setsb, VAR(N_FLAG)) \
427 
+         EMIT1(setzb, VAR(Z_FLAG)) \
428 
+         EMIT2(movl, edx, REGREF2(ecx,4)) \
429 
+         : : )
430 
+  #define IMM5_LSL \
431 
+         "shll %0,%%edx;"\
432 
+         EMIT1(setcb, VAR(C_FLAG))
433 
+  #define IMM5_LSL_0 \
434 
+         "testl %%edx,%%edx;"
435 
+  #define IMM5_LSR \
436 
+         "shrl %0,%%edx;"\
437 
+         EMIT1(setcb, VAR(C_FLAG))
438 
+  #define IMM5_LSR_0 \
439 
+         "testl %%edx,%%edx;"\
440 
+         EMIT1(setsb, VAR(C_FLAG)) \
441 
+         "xorl %%edx,%%edx;"
442 
+  #define IMM5_ASR \
443 
+         "sarl %0,%%edx;"\
444 
+         EMIT1(setcb, VAR(C_FLAG))
445 
+  #define IMM5_ASR_0 \
446 
+         "sarl $31,%%edx;"\
447 
+         EMIT1(setsb, VAR(C_FLAG))
448 
+  #define THREEARG_INSN(OP,N) \
449 
+     asm("movl %%eax,%%edx;"       \
450 
+         "shrl $1,%%edx;"          \
451 
+         "andl $0x1C,%%edx;"       \
452 
+         "andl $7,%%eax;"          \
453 
+         EMIT2(movl, REGREF1(edx), ecx) \
454 
+         OP(N)                     \
455 
+         EMIT1(setsb, VAR(N_FLAG)) \
456 
+         EMIT1(setzb, VAR(Z_FLAG)) \
457 
+         EMIT2(movl, ecx, REGREF2(eax,4)) \
458 
+         : : )
459 
+  #define ADD_RD_RS_RN(N)          \
460 
+         EMIT2(add,VAR(reg)"+"#N"*4",ecx) \
461 
+         EMIT1(setcb, VAR(C_FLAG)) \
462 
+         EMIT1(setob, VAR(V_FLAG))
463 
+  #define ADD_RD_RS_O3(N)          \
464 
+         "add $"#N",%%ecx;"        \
465 
+         EMIT1(setcb, VAR(C_FLAG)) \
466 
+         EMIT1(setob, VAR(V_FLAG))
467 
+  #define ADD_RD_RS_O3_0(N)        \
468 
+         EMIT2(movb,KONST(0),VAR(C_FLAG)) \
469 
+         "add $0,%%ecx;"           \
470 
+         EMIT2(movb,KONST(0),VAR(V_FLAG))
471 
+  #define SUB_RD_RS_RN(N) \
472 
+         EMIT2(sub,VAR(reg)"+"#N"*4",ecx) \
473 
+         EMIT1(setncb, VAR(C_FLAG)) \
474 
+         EMIT1(setob, VAR(V_FLAG))
475 
+  #define SUB_RD_RS_O3(N) \
476 
+         "sub $"#N",%%ecx;"        \
477 
+         EMIT1(setncb, VAR(C_FLAG)) \
478 
+         EMIT1(setob, VAR(V_FLAG))
479 
+  #define SUB_RD_RS_O3_0(N)        \
480 
+         EMIT2(movb,KONST(1),VAR(C_FLAG)) \
481 
+         "sub $0,%%ecx;"           \
482 
+         EMIT2(movb,KONST(0),VAR(V_FLAG))
483 
+#endif
484 
+#else // !__GNUC__
485 
+  #define ADD_RD_RS_RN(N) \
486 
+   {\
487 
+     __asm mov eax, source\
488 
+     __asm mov ebx, dword ptr [OFFSET reg+4*eax]\
489 
+     __asm add ebx, dword ptr [OFFSET reg+4*N]\
490 
+     __asm mov eax, dest\
491 
+     __asm mov dword ptr [OFFSET reg+4*eax], ebx\
492 
+     __asm sets byte ptr N_FLAG\
493 
+     __asm setz byte ptr Z_FLAG\
494 
+     __asm setc byte ptr C_FLAG\
495 
+     __asm seto byte ptr V_FLAG\
496 
+   }
497 
+  #define ADD_RD_RS_O3(N) \
498 
+   {\
499 
+     __asm mov eax, source\
500 
+     __asm mov ebx, dword ptr [OFFSET reg+4*eax]\
501 
+     __asm add ebx, N\
502 
+     __asm mov eax, dest\
503 
+     __asm mov dword ptr [OFFSET reg+4*eax], ebx\
504 
+     __asm sets byte ptr N_FLAG\
505 
+     __asm setz byte ptr Z_FLAG\
506 
+     __asm setc byte ptr C_FLAG\
507 
+     __asm seto byte ptr V_FLAG\
508 
+   }
509 
+  #define ADD_RD_RS_O3_0 \
510 
+   {\
511 
+     __asm mov eax, source\
512 
+     __asm mov ebx, dword ptr [OFFSET reg+4*eax]\
513 
+     __asm add ebx, 0\
514 
+     __asm mov eax, dest\
515 
+     __asm mov dword ptr [OFFSET reg+4*eax], ebx\
516 
+     __asm sets byte ptr N_FLAG\
517 
+     __asm setz byte ptr Z_FLAG\
518 
+     __asm mov byte ptr C_FLAG, 0\
519 
+     __asm mov byte ptr V_FLAG, 0\
520 
+   }
521 
+  #define ADD_RN_O8(d) \
522 
+   {\
523 
+     __asm mov ebx, opcode\
524 
+     __asm and ebx, 255\
525 
+     __asm add dword ptr [OFFSET reg+4*(d)], ebx\
526 
+     __asm sets byte ptr N_FLAG\
527 
+     __asm setz byte ptr Z_FLAG\
528 
+     __asm setc byte ptr C_FLAG\
529 
+     __asm seto byte ptr V_FLAG\
530 
+   }
531 
+  #define CMN_RD_RS \
532 
+     {\
533 
+       __asm mov eax, dest\
534 
+       __asm mov ebx, dword ptr [OFFSET reg+4*eax]\
535 
+       __asm add ebx, value\
536 
+       __asm sets byte ptr N_FLAG\
537 
+       __asm setz byte ptr Z_FLAG\
538 
+       __asm setc byte ptr C_FLAG\
539 
+       __asm seto byte ptr V_FLAG\
540 
+     }
541 
+  #define ADC_RD_RS \
542 
+     {\
543 
+       __asm mov ebx, dest\
544 
+       __asm mov ebx, dword ptr [OFFSET reg+4*ebx]\
545 
+       __asm bt word ptr C_FLAG, 0\
546 
+       __asm adc ebx, value\
547 
+       __asm mov eax, dest\
548 
+       __asm mov dword ptr [OFFSET reg+4*eax], ebx\
549 
+       __asm sets byte ptr N_FLAG\
550 
+       __asm setz byte ptr Z_FLAG\
551 
+       __asm setc byte ptr C_FLAG\
552 
+       __asm seto byte ptr V_FLAG\
553 
+     }
554 
+  #define SUB_RD_RS_RN(N) \
555 
+   {\
556 
+     __asm mov eax, source\
557 
+     __asm mov ebx, dword ptr [OFFSET reg+4*eax]\
558 
+     __asm sub ebx, dword ptr [OFFSET reg+4*N]\
559 
+     __asm mov eax, dest\
560 
+     __asm mov dword ptr [OFFSET reg+4*eax], ebx\
561 
+     __asm sets byte ptr N_FLAG\
562 
+     __asm setz byte ptr Z_FLAG\
563 
+     __asm setnc byte ptr C_FLAG\
564 
+     __asm seto byte ptr V_FLAG\
565 
+   }
566 
+  #define SUB_RD_RS_O3(N) \
567 
+   {\
568 
+     __asm mov eax, source\
569 
+     __asm mov ebx, dword ptr [OFFSET reg+4*eax]\
570 
+     __asm sub ebx, N\
571 
+     __asm mov eax, dest\
572 
+     __asm mov dword ptr [OFFSET reg+4*eax], ebx\
573 
+     __asm sets byte ptr N_FLAG\
574 
+     __asm setz byte ptr Z_FLAG\
575 
+     __asm setnc byte ptr C_FLAG\
576 
+     __asm seto byte ptr V_FLAG\
577 
+   }
578 
+  #define SUB_RD_RS_O3_0 \
579 
+   {\
580 
+     __asm mov eax, source\
581 
+     __asm mov ebx, dword ptr [OFFSET reg+4*eax]\
582 
+     __asm sub ebx, 0\
583 
+     __asm mov eax, dest\
584 
+     __asm mov dword ptr [OFFSET reg+4*eax], ebx\
585 
+     __asm sets byte ptr N_FLAG\
586 
+     __asm setz byte ptr Z_FLAG\
587 
+     __asm mov byte ptr C_FLAG, 1\
588 
+     __asm mov byte ptr V_FLAG, 0\
589 
+   }
590 
+  #define SUB_RN_O8(d) \
591 
+   {\
592 
+     __asm mov ebx, opcode\
593 
+     __asm and ebx, 255\
594 
+     __asm sub dword ptr [OFFSET reg + 4*(d)], ebx\
595 
+     __asm sets byte ptr N_FLAG\
596 
+     __asm setz byte ptr Z_FLAG\
597 
+     __asm setnc byte ptr C_FLAG\
598 
+     __asm seto byte ptr V_FLAG\
599 
+   }
600 
+  #define MOV_RN_O8(d) \
601 
+   {\
602 
+     __asm mov eax, opcode\
603 
+     __asm and eax, 255\
604 
+     __asm mov dword ptr [OFFSET reg+4*(d)], eax\
605 
+     __asm sets byte ptr N_FLAG\
606 
+     __asm setz byte ptr Z_FLAG\
607 
+   }
608 
+  #define CMP_RN_O8(d) \
609 
+   {\
610 
+     __asm mov eax, dword ptr [OFFSET reg+4*(d)]\
611 
+     __asm mov ebx, opcode\
612 
+     __asm and ebx, 255\
613 
+     __asm sub eax, ebx\
614 
+     __asm sets byte ptr N_FLAG\
615 
+     __asm setz byte ptr Z_FLAG\
616 
+     __asm setnc byte ptr C_FLAG\
617 
+     __asm seto byte ptr V_FLAG\
618 
+   }
619 
+  #define SBC_RD_RS \
620 
+     {\
621 
+       __asm mov ebx, dest\
622 
+       __asm mov ebx, dword ptr [OFFSET reg + 4*ebx]\
623 
+       __asm mov eax, value\
624 
+       __asm bt word ptr C_FLAG, 0\
625 
+       __asm cmc\
626 
+       __asm sbb ebx, eax\
627 
+       __asm mov eax, dest\
628 
+       __asm mov dword ptr [OFFSET reg + 4*eax], ebx\
629 
+       __asm sets byte ptr N_FLAG\
630 
+       __asm setz byte ptr Z_FLAG\
631 
+       __asm setnc byte ptr C_FLAG\
632 
+       __asm seto byte ptr V_FLAG\
633 
+     }
634 
+  #define LSL_RD_RM_I5 \
635 
+     {\
636 
+       __asm mov eax, source\
637 
+       __asm mov eax, dword ptr [OFFSET reg + 4 * eax]\
638 
+       __asm mov cl, byte ptr shift\
639 
+       __asm shl eax, cl\
640 
+       __asm mov value, eax\
641 
+       __asm setc byte ptr C_FLAG\
642 
+     }
643 
+  #define LSL_RD_RS \
644 
+         {\
645 
+           __asm mov eax, dest\
646 
+           __asm mov eax, dword ptr [OFFSET reg + 4 * eax]\
647 
+           __asm mov cl, byte ptr value\
648 
+           __asm shl eax, cl\
649 
+           __asm mov value, eax\
650 
+           __asm setc byte ptr C_FLAG\
651 
+         }
652 
+  #define LSR_RD_RM_I5 \
653 
+     {\
654 
+       __asm mov eax, source\
655 
+       __asm mov eax, dword ptr [OFFSET reg + 4 * eax]\
656 
+       __asm mov cl, byte ptr shift\
657 
+       __asm shr eax, cl\
658 
+       __asm mov value, eax\
659 
+       __asm setc byte ptr C_FLAG\
660 
+     }
661 
+  #define LSR_RD_RS \
662 
+         {\
663 
+           __asm mov eax, dest\
664 
+           __asm mov eax, dword ptr [OFFSET reg + 4 * eax]\
665 
+           __asm mov cl, byte ptr value\
666 
+           __asm shr eax, cl\
667 
+           __asm mov value, eax\
668 
+           __asm setc byte ptr C_FLAG\
669 
+         }
670 
+  #define ASR_RD_RM_I5 \
671 
+     {\
672 
+       __asm mov eax, source\
673 
+       __asm mov eax, dword ptr [OFFSET reg + 4*eax]\
674 
+       __asm mov cl, byte ptr shift\
675 
+       __asm sar eax, cl\
676 
+       __asm mov value, eax\
677 
+       __asm setc byte ptr C_FLAG\
678 
+     }
679 
+  #define ASR_RD_RS \
680 
+         {\
681 
+           __asm mov eax, dest\
682 
+           __asm mov eax, dword ptr [OFFSET reg + 4*eax]\
683 
+           __asm mov cl, byte ptr value\
684 
+           __asm sar eax, cl\
685 
+           __asm mov value, eax\
686 
+           __asm setc byte ptr C_FLAG\
687 
+         }
688 
+  #define ROR_RD_RS \
689 
+         {\
690 
+           __asm mov eax, dest\
691 
+           __asm mov eax, dword ptr [OFFSET reg + 4*eax]\
692 
+           __asm mov cl, byte ptr value\
693 
+           __asm ror eax, cl\
694 
+           __asm mov value, eax\
695 
+           __asm setc byte ptr C_FLAG\
696 
+         }
697 
+  #define NEG_RD_RS \
698 
+     {\
699 
+       __asm mov ebx, source\
700 
+       __asm mov ebx, dword ptr [OFFSET reg+4*ebx]\
701 
+       __asm neg ebx\
702 
+       __asm mov eax, dest\
703 
+       __asm mov dword ptr [OFFSET reg+4*eax],ebx\
704 
+       __asm sets byte ptr N_FLAG\
705 
+       __asm setz byte ptr Z_FLAG\
706 
+       __asm setnc byte ptr C_FLAG\
707 
+       __asm seto byte ptr V_FLAG\
708 
+     }
709 
+  #define CMP_RD_RS \
710 
+     {\
711 
+       __asm mov eax, dest\
712 
+       __asm mov ebx, dword ptr [OFFSET reg+4*eax]\
713 
+       __asm sub ebx, value\
714 
+       __asm sets byte ptr N_FLAG\
715 
+       __asm setz byte ptr Z_FLAG\
716 
+       __asm setnc byte ptr C_FLAG\
717 
+       __asm seto byte ptr V_FLAG\
718 
+     }
719 
+#endif
720 
+#endif
721 
+
722 
+// C core
723 
+#ifndef ADDCARRY
724 
+ #define ADDCARRY(a, b, c) \
725 
+  C_FLAG = ((NEG(a) & NEG(b)) |\
726 
+            (NEG(a) & POS(c)) |\
727 
+            (NEG(b) & POS(c))) ? true : false;
728 
+#endif
729 
+#ifndef ADDOVERFLOW
730 
+ #define ADDOVERFLOW(a, b, c) \
731 
+  V_FLAG = ((NEG(a) & NEG(b) & POS(c)) |\
732 
+            (POS(a) & POS(b) & NEG(c))) ? true : false;
733 
+#endif
734 
+#ifndef SUBCARRY
735 
+ #define SUBCARRY(a, b, c) \
736 
+  C_FLAG = ((NEG(a) & POS(b)) |\
737 
+            (NEG(a) & POS(c)) |\
738 
+            (POS(b) & POS(c))) ? true : false;
739 
+#endif
740 
+#ifndef SUBOVERFLOW
741 
+ #define SUBOVERFLOW(a, b, c)\
742 
+  V_FLAG = ((NEG(a) & POS(b) & POS(c)) |\
743 
+            (POS(a) & NEG(b) & NEG(c))) ? true : false;
744 
+#endif
745 
+#ifndef ADD_RD_RS_RN
746 
+ #define ADD_RD_RS_RN(N) \
747 
+   {\
748 
+     u32 lhs = reg[source].I;\
749 
+     u32 rhs = reg[N].I;\
750 
+     u32 res = lhs + rhs;\
751 
+     reg[dest].I = res;\
752 
+     Z_FLAG = (res == 0) ? true : false;\
753 
+     N_FLAG = NEG(res) ? true : false;\
754 
+     ADDCARRY(lhs, rhs, res);\
755 
+     ADDOVERFLOW(lhs, rhs, res);\
756 
+   }
757 
+#endif
758 
+#ifndef ADD_RD_RS_O3
759 
+ #define ADD_RD_RS_O3(N) \
760 
+   {\
761 
+     u32 lhs = reg[source].I;\
762 
+     u32 rhs = N;\
763 
+     u32 res = lhs + rhs;\
764 
+     reg[dest].I = res;\
765 
+     Z_FLAG = (res == 0) ? true : false;\
766 
+     N_FLAG = NEG(res) ? true : false;\
767 
+     ADDCARRY(lhs, rhs, res);\
768 
+     ADDOVERFLOW(lhs, rhs, res);\
769 
+   }
770 
+#endif
771 
+#ifndef ADD_RD_RS_O3_0
772 
+# define ADD_RD_RS_O3_0 ADD_RD_RS_O3
773 
+#endif
774 
+#ifndef ADD_RN_O8
775 
+ #define ADD_RN_O8(d) \
776 
+   {\
777 
+     u32 lhs = reg[(d)].I;\
778 
+     u32 rhs = (opcode & 255);\
779 
+     u32 res = lhs + rhs;\
780 
+     reg[(d)].I = res;\
781 
+     Z_FLAG = (res == 0) ? true : false;\
782 
+     N_FLAG = NEG(res) ? true : false;\
783 
+     ADDCARRY(lhs, rhs, res);\
784 
+     ADDOVERFLOW(lhs, rhs, res);\
785 
+   }
786 
+#endif
787 
+#ifndef CMN_RD_RS
788 
+ #define CMN_RD_RS \
789 
+   {\
790 
+     u32 lhs = reg[dest].I;\
791 
+     u32 rhs = value;\
792 
+     u32 res = lhs + rhs;\
793 
+     Z_FLAG = (res == 0) ? true : false;\
794 
+     N_FLAG = NEG(res) ? true : false;\
795 
+     ADDCARRY(lhs, rhs, res);\
796 
+     ADDOVERFLOW(lhs, rhs, res);\
797 
+   }
798 
+#endif
799 
+#ifndef ADC_RD_RS
800 
+ #define ADC_RD_RS \
801 
+   {\
802 
+     u32 lhs = reg[dest].I;\
803 
+     u32 rhs = value;\
804 
+     u32 res = lhs + rhs + (u32)C_FLAG;\
805 
+     reg[dest].I = res;\
806 
+     Z_FLAG = (res == 0) ? true : false;\
807 
+     N_FLAG = NEG(res) ? true : false;\
808 
+     ADDCARRY(lhs, rhs, res);\
809 
+     ADDOVERFLOW(lhs, rhs, res);\
810 
+   }
811 
+#endif
812 
+#ifndef SUB_RD_RS_RN
813 
+ #define SUB_RD_RS_RN(N) \
814 
+   {\
815 
+     u32 lhs = reg[source].I;\
816 
+     u32 rhs = reg[N].I;\
817 
+     u32 res = lhs - rhs;\
818 
+     reg[dest].I = res;\
819 
+     Z_FLAG = (res == 0) ? true : false;\
820 
+     N_FLAG = NEG(res) ? true : false;\
821 
+     SUBCARRY(lhs, rhs, res);\
822 
+     SUBOVERFLOW(lhs, rhs, res);\
823 
+   }
824 
+#endif
825 
+#ifndef SUB_RD_RS_O3
826 
+ #define SUB_RD_RS_O3(N) \
827 
+   {\
828 
+     u32 lhs = reg[source].I;\
829 
+     u32 rhs = N;\
830 
+     u32 res = lhs - rhs;\
831 
+     reg[dest].I = res;\
832 
+     Z_FLAG = (res == 0) ? true : false;\
833 
+     N_FLAG = NEG(res) ? true : false;\
834 
+     SUBCARRY(lhs, rhs, res);\
835 
+     SUBOVERFLOW(lhs, rhs, res);\
836 
+   }
837 
+#endif
838 
+#ifndef SUB_RD_RS_O3_0
839 
+# define SUB_RD_RS_O3_0 SUB_RD_RS_O3
840 
+#endif
841 
+#ifndef SUB_RN_O8
842 
+ #define SUB_RN_O8(d) \
843 
+   {\
844 
+     u32 lhs = reg[(d)].I;\
845 
+     u32 rhs = (opcode & 255);\
846 
+     u32 res = lhs - rhs;\
847 
+     reg[(d)].I = res;\
848 
+     Z_FLAG = (res == 0) ? true : false;\
849 
+     N_FLAG = NEG(res) ? true : false;\
850 
+     SUBCARRY(lhs, rhs, res);\
851 
+     SUBOVERFLOW(lhs, rhs, res);\
852 
+   }
853 
+#endif
854 
+#ifndef MOV_RN_O8
855 
+ #define MOV_RN_O8(d) \
856 
+   {\
857 
+     reg[d].I = opcode & 255;\
858 
+     N_FLAG = false;\
859 
+     Z_FLAG = (reg[d].I ? false : true);\
860 
+   }
861 
+#endif
862 
+#ifndef CMP_RN_O8
863 
+ #define CMP_RN_O8(d) \
864 
+   {\
865 
+     u32 lhs = reg[(d)].I;\
866 
+     u32 rhs = (opcode & 255);\
867 
+     u32 res = lhs - rhs;\
868 
+     Z_FLAG = (res == 0) ? true : false;\
869 
+     N_FLAG = NEG(res) ? true : false;\
870 
+     SUBCARRY(lhs, rhs, res);\
871 
+     SUBOVERFLOW(lhs, rhs, res);\
872 
+   }
873 
+#endif
874 
+#ifndef SBC_RD_RS
875 
+ #define SBC_RD_RS \
876 
+   {\
877 
+     u32 lhs = reg[dest].I;\
878 
+     u32 rhs = value;\
879 
+     u32 res = lhs - rhs - !((u32)C_FLAG);\
880 
+     reg[dest].I = res;\
881 
+     Z_FLAG = (res == 0) ? true : false;\
882 
+     N_FLAG = NEG(res) ? true : false;\
883 
+     SUBCARRY(lhs, rhs, res);\
884 
+     SUBOVERFLOW(lhs, rhs, res);\
885 
+   }
886 
+#endif
887 
+#ifndef LSL_RD_RM_I5
888 
+ #define LSL_RD_RM_I5 \
889 
+   {\
890 
+     C_FLAG = (reg[source].I >> (32 - shift)) & 1 ? true : false;\
891 
+     value = reg[source].I << shift;\
892 
+   }
893 
+#endif
894 
+#ifndef LSL_RD_RS
895 
+ #define LSL_RD_RS \
896 
+   {\
897 
+     C_FLAG = (reg[dest].I >> (32 - value)) & 1 ? true : false;\
898 
+     value = reg[dest].I << value;\
899 
+   }
900 
+#endif
901 
+#ifndef LSR_RD_RM_I5
902 
+ #define LSR_RD_RM_I5 \
903 
+   {\
904 
+     C_FLAG = (reg[source].I >> (shift - 1)) & 1 ? true : false;\
905 
+     value = reg[source].I >> shift;\
906 
+   }
907 
+#endif
908 
+#ifndef LSR_RD_RS
909 
+ #define LSR_RD_RS \
910 
+   {\
911 
+     C_FLAG = (reg[dest].I >> (value - 1)) & 1 ? true : false;\
912 
+     value = reg[dest].I >> value;\
913 
+   }
914 
+#endif
915 
+#ifndef ASR_RD_RM_I5
916 
+ #define ASR_RD_RM_I5 \
917 
+   {\
918 
+     C_FLAG = ((s32)reg[source].I >> (int)(shift - 1)) & 1 ? true : false;\
919 
+     value = (s32)reg[source].I >> (int)shift;\
920 
+   }
921 
+#endif
922 
+#ifndef ASR_RD_RS
923 
+ #define ASR_RD_RS \
924 
+   {\
925 
+     C_FLAG = ((s32)reg[dest].I >> (int)(value - 1)) & 1 ? true : false;\
926 
+     value = (s32)reg[dest].I >> (int)value;\
927 
+   }
928 
+#endif
929 
+#ifndef ROR_RD_RS
930 
+ #define ROR_RD_RS \
931 
+   {\
932 
+     C_FLAG = (reg[dest].I >> (value - 1)) & 1 ? true : false;\
933 
+     value = ((reg[dest].I << (32 - value)) |\
934 
+              (reg[dest].I >> value));\
935 
+   }
936 
+#endif
937 
+#ifndef NEG_RD_RS
938 
+ #define NEG_RD_RS \
939 
+   {\
940 
+     u32 lhs = reg[source].I;\
941 
+     u32 rhs = 0;\
942 
+     u32 res = rhs - lhs;\
943 
+     reg[dest].I = res;\
944 
+     Z_FLAG = (res == 0) ? true : false;\
945 
+     N_FLAG = NEG(res) ? true : false;\
946 
+     SUBCARRY(rhs, lhs, res);\
947 
+     SUBOVERFLOW(rhs, lhs, res);\
948 
+   }
949 
+#endif
950 
+#ifndef CMP_RD_RS
951 
+ #define CMP_RD_RS \
952 
+   {\
953 
+     u32 lhs = reg[dest].I;\
954 
+     u32 rhs = value;\
955 
+     u32 res = lhs - rhs;\
956 
+     Z_FLAG = (res == 0) ? true : false;\
957 
+     N_FLAG = NEG(res) ? true : false;\
958 
+     SUBCARRY(lhs, rhs, res);\
959 
+     SUBOVERFLOW(lhs, rhs, res);\
960 
+   }
961 
+#endif
962 
+#ifndef IMM5_INSN
963 
+ #define IMM5_INSN(OP,N) \
964 
+  int dest = opcode & 0x07;\
965 
+  int source = (opcode >> 3) & 0x07;\
966 
+  u32 value;\
967 
+  OP(N);\
968 
+  reg[dest].I = value;\
969 
+  N_FLAG = (value & 0x80000000 ? true : false);\
970 
+  Z_FLAG = (value ? false : true);
971 
+ #define IMM5_INSN_0(OP) \
972 
+  int dest = opcode & 0x07;\
973 
+  int source = (opcode >> 3) & 0x07;\
974 
+  u32 value;\
975 
+  OP;\
976 
+  reg[dest].I = value;\
977 
+  N_FLAG = (value & 0x80000000 ? true : false);\
978 
+  Z_FLAG = (value ? false : true);
979 
+ #define IMM5_LSL(N) \
980 
+  int shift = N;\
981 
+  LSL_RD_RM_I5;
982 
+ #define IMM5_LSL_0 \
983 
+  value = reg[source].I;
984 
+ #define IMM5_LSR(N) \
985 
+  int shift = N;\
986 
+  LSR_RD_RM_I5;
987 
+ #define IMM5_LSR_0 \
988 
+  C_FLAG = reg[source].I & 0x80000000 ? true : false;\
989 
+  value = 0;
990 
+ #define IMM5_ASR(N) \
991 
+  int shift = N;\
992 
+  ASR_RD_RM_I5;
993 
+ #define IMM5_ASR_0 \
994 
+  if(reg[source].I & 0x80000000) {\
995 
+    value = 0xFFFFFFFF;\
996 
+    C_FLAG = true;\
997 
+  } else {\
998 
+    value = 0;\
999 
+    C_FLAG = false;\
1000 
+  }
1001 
+#endif
1002 
+#ifndef THREEARG_INSN
1003 
+ #define THREEARG_INSN(OP,N) \
1004 
+  int dest = opcode & 0x07;          \
1005 
+  int source = (opcode >> 3) & 0x07; \
1006 
+  OP(N);
1007 
+#endif
1008 
+
1009 
+// Shift instructions /////////////////////////////////////////////////////
1010 
+
1011 
+#define DEFINE_IMM5_INSN(OP,BASE) \
1012 
+  static INSN_REGPARM void thumb##BASE##_00(u32 opcode) { IMM5_INSN_0(OP##_0); } \
1013 
+  static INSN_REGPARM void thumb##BASE##_01(u32 opcode) { IMM5_INSN(OP, 1); } \
1014 
+  static INSN_REGPARM void thumb##BASE##_02(u32 opcode) { IMM5_INSN(OP, 2); } \
1015 
+  static INSN_REGPARM void thumb##BASE##_03(u32 opcode) { IMM5_INSN(OP, 3); } \
1016 
+  static INSN_REGPARM void thumb##BASE##_04(u32 opcode) { IMM5_INSN(OP, 4); } \
1017 
+  static INSN_REGPARM void thumb##BASE##_05(u32 opcode) { IMM5_INSN(OP, 5); } \
1018 
+  static INSN_REGPARM void thumb##BASE##_06(u32 opcode) { IMM5_INSN(OP, 6); } \
1019 
+  static INSN_REGPARM void thumb##BASE##_07(u32 opcode) { IMM5_INSN(OP, 7); } \
1020 
+  static INSN_REGPARM void thumb##BASE##_08(u32 opcode) { IMM5_INSN(OP, 8); } \
1021 
+  static INSN_REGPARM void thumb##BASE##_09(u32 opcode) { IMM5_INSN(OP, 9); } \
1022 
+  static INSN_REGPARM void thumb##BASE##_0A(u32 opcode) { IMM5_INSN(OP,10); } \
1023 
+  static INSN_REGPARM void thumb##BASE##_0B(u32 opcode) { IMM5_INSN(OP,11); } \
1024 
+  static INSN_REGPARM void thumb##BASE##_0C(u32 opcode) { IMM5_INSN(OP,12); } \
1025 
+  static INSN_REGPARM void thumb##BASE##_0D(u32 opcode) { IMM5_INSN(OP,13); } \
1026 
+  static INSN_REGPARM void thumb##BASE##_0E(u32 opcode) { IMM5_INSN(OP,14); } \
1027 
+  static INSN_REGPARM void thumb##BASE##_0F(u32 opcode) { IMM5_INSN(OP,15); } \
1028 
+  static INSN_REGPARM void thumb##BASE##_10(u32 opcode) { IMM5_INSN(OP,16); } \
1029 
+  static INSN_REGPARM void thumb##BASE##_11(u32 opcode) { IMM5_INSN(OP,17); } \
1030 
+  static INSN_REGPARM void thumb##BASE##_12(u32 opcode) { IMM5_INSN(OP,18); } \
1031 
+  static INSN_REGPARM void thumb##BASE##_13(u32 opcode) { IMM5_INSN(OP,19); } \
1032 
+  static INSN_REGPARM void thumb##BASE##_14(u32 opcode) { IMM5_INSN(OP,20); } \
1033 
+  static INSN_REGPARM void thumb##BASE##_15(u32 opcode) { IMM5_INSN(OP,21); } \
1034 
+  static INSN_REGPARM void thumb##BASE##_16(u32 opcode) { IMM5_INSN(OP,22); } \
1035 
+  static INSN_REGPARM void thumb##BASE##_17(u32 opcode) { IMM5_INSN(OP,23); } \
1036 
+  static INSN_REGPARM void thumb##BASE##_18(u32 opcode) { IMM5_INSN(OP,24); } \
1037 
+  static INSN_REGPARM void thumb##BASE##_19(u32 opcode) { IMM5_INSN(OP,25); } \
1038 
+  static INSN_REGPARM void thumb##BASE##_1A(u32 opcode) { IMM5_INSN(OP,26); } \
1039 
+  static INSN_REGPARM void thumb##BASE##_1B(u32 opcode) { IMM5_INSN(OP,27); } \
1040 
+  static INSN_REGPARM void thumb##BASE##_1C(u32 opcode) { IMM5_INSN(OP,28); } \
1041 
+  static INSN_REGPARM void thumb##BASE##_1D(u32 opcode) { IMM5_INSN(OP,29); } \
1042 
+  static INSN_REGPARM void thumb##BASE##_1E(u32 opcode) { IMM5_INSN(OP,30); } \
1043 
+  static INSN_REGPARM void thumb##BASE##_1F(u32 opcode) { IMM5_INSN(OP,31); }
1044 
+
1045 
+// LSL Rd, Rm, #Imm 5
1046 
+DEFINE_IMM5_INSN(IMM5_LSL,00)
1047 
+// LSR Rd, Rm, #Imm 5
1048 
+DEFINE_IMM5_INSN(IMM5_LSR,08)
1049 
+// ASR Rd, Rm, #Imm 5
1050 
+DEFINE_IMM5_INSN(IMM5_ASR,10)
1051 
+
1052 
+// 3-argument ADD/SUB /////////////////////////////////////////////////////
1053 
+
1054 
+#define DEFINE_REG3_INSN(OP,BASE) \
1055 
+  static INSN_REGPARM void thumb##BASE##_0(u32 opcode) { THREEARG_INSN(OP,0); } \
1056 
+  static INSN_REGPARM void thumb##BASE##_1(u32 opcode) { THREEARG_INSN(OP,1); } \
1057 
+  static INSN_REGPARM void thumb##BASE##_2(u32 opcode) { THREEARG_INSN(OP,2); } \
1058 
+  static INSN_REGPARM void thumb##BASE##_3(u32 opcode) { THREEARG_INSN(OP,3); } \
1059 
+  static INSN_REGPARM void thumb##BASE##_4(u32 opcode) { THREEARG_INSN(OP,4); } \
1060 
+  static INSN_REGPARM void thumb##BASE##_5(u32 opcode) { THREEARG_INSN(OP,5); } \
1061 
+  static INSN_REGPARM void thumb##BASE##_6(u32 opcode) { THREEARG_INSN(OP,6); } \
1062 
+  static INSN_REGPARM void thumb##BASE##_7(u32 opcode) { THREEARG_INSN(OP,7); }
1063 
+
1064 
+#define DEFINE_IMM3_INSN(OP,BASE) \
1065 
+  static INSN_REGPARM void thumb##BASE##_0(u32 opcode) { THREEARG_INSN(OP##_0,0); } \
1066 
+  static INSN_REGPARM void thumb##BASE##_1(u32 opcode) { THREEARG_INSN(OP,1); } \
1067 
+  static INSN_REGPARM void thumb##BASE##_2(u32 opcode) { THREEARG_INSN(OP,2); } \
1068 
+  static INSN_REGPARM void thumb##BASE##_3(u32 opcode) { THREEARG_INSN(OP,3); } \
1069 
+  static INSN_REGPARM void thumb##BASE##_4(u32 opcode) { THREEARG_INSN(OP,4); } \
1070 
+  static INSN_REGPARM void thumb##BASE##_5(u32 opcode) { THREEARG_INSN(OP,5); } \
1071 
+  static INSN_REGPARM void thumb##BASE##_6(u32 opcode) { THREEARG_INSN(OP,6); } \
1072 
+  static INSN_REGPARM void thumb##BASE##_7(u32 opcode) { THREEARG_INSN(OP,7); }
1073 
+
1074 
+// ADD Rd, Rs, Rn
1075 
+DEFINE_REG3_INSN(ADD_RD_RS_RN,18)
1076 
+// SUB Rd, Rs, Rn
1077 
+DEFINE_REG3_INSN(SUB_RD_RS_RN,1A)
1078 
+// ADD Rd, Rs, #Offset3
1079 
+DEFINE_IMM3_INSN(ADD_RD_RS_O3,1C)
1080 
+// SUB Rd, Rs, #Offset3
1081 
+DEFINE_IMM3_INSN(SUB_RD_RS_O3,1E)
1082 
+
1083 
+// MOV/CMP/ADD/SUB immediate //////////////////////////////////////////////
1084 
+
1085 
+// MOV R0, #Offset8
1086 
+static INSN_REGPARM void thumb20(u32 opcode) { MOV_RN_O8(0); }
1087 
+// MOV R1, #Offset8
1088 
+static INSN_REGPARM void thumb21(u32 opcode) { MOV_RN_O8(1); }
1089 
+// MOV R2, #Offset8
1090 
+static INSN_REGPARM void thumb22(u32 opcode) { MOV_RN_O8(2); }
1091 
+// MOV R3, #Offset8
1092 
+static INSN_REGPARM void thumb23(u32 opcode) { MOV_RN_O8(3); }
1093 
+// MOV R4, #Offset8
1094 
+static INSN_REGPARM void thumb24(u32 opcode) { MOV_RN_O8(4); }
1095 
+// MOV R5, #Offset8
1096 
+static INSN_REGPARM void thumb25(u32 opcode) { MOV_RN_O8(5); }
1097 
+// MOV R6, #Offset8
1098 
+static INSN_REGPARM void thumb26(u32 opcode) { MOV_RN_O8(6); }
1099 
+// MOV R7, #Offset8
1100 
+static INSN_REGPARM void thumb27(u32 opcode) { MOV_RN_O8(7); }
1101 
+
1102 
+// CMP R0, #Offset8
1103 
+static INSN_REGPARM void thumb28(u32 opcode) { CMP_RN_O8(0); }
1104 
+// CMP R1, #Offset8
1105 
+static INSN_REGPARM void thumb29(u32 opcode) { CMP_RN_O8(1); }
1106 
+// CMP R2, #Offset8
1107 
+static INSN_REGPARM void thumb2A(u32 opcode) { CMP_RN_O8(2); }
1108 
+// CMP R3, #Offset8
1109 
+static INSN_REGPARM void thumb2B(u32 opcode) { CMP_RN_O8(3); }
1110 
+// CMP R4, #Offset8
1111 
+static INSN_REGPARM void thumb2C(u32 opcode) { CMP_RN_O8(4); }
1112 
+// CMP R5, #Offset8
1113 
+static INSN_REGPARM void thumb2D(u32 opcode) { CMP_RN_O8(5); }
1114 
+// CMP R6, #Offset8
1115 
+static INSN_REGPARM void thumb2E(u32 opcode) { CMP_RN_O8(6); }
1116 
+// CMP R7, #Offset8
1117 
+static INSN_REGPARM void thumb2F(u32 opcode) { CMP_RN_O8(7); }
1118 
+
1119 
+// ADD R0,#Offset8
1120 
+static INSN_REGPARM void thumb30(u32 opcode) { ADD_RN_O8(0); }
1121 
+// ADD R1,#Offset8
1122 
+static INSN_REGPARM void thumb31(u32 opcode) { ADD_RN_O8(1); }
1123 
+// ADD R2,#Offset8
1124 
+static INSN_REGPARM void thumb32(u32 opcode) { ADD_RN_O8(2); }
1125 
+// ADD R3,#Offset8
1126 
+static INSN_REGPARM void thumb33(u32 opcode) { ADD_RN_O8(3); }
1127 
+// ADD R4,#Offset8
1128 
+static INSN_REGPARM void thumb34(u32 opcode) { ADD_RN_O8(4); }
1129 
+// ADD R5,#Offset8
1130 
+static INSN_REGPARM void thumb35(u32 opcode) { ADD_RN_O8(5); }
1131 
+// ADD R6,#Offset8
1132 
+static INSN_REGPARM void thumb36(u32 opcode) { ADD_RN_O8(6); }
1133 
+// ADD R7,#Offset8
1134 
+static INSN_REGPARM void thumb37(u32 opcode) { ADD_RN_O8(7); }
1135 
+
1136 
+// SUB R0,#Offset8
1137 
+static INSN_REGPARM void thumb38(u32 opcode) { SUB_RN_O8(0); }
1138 
+// SUB R1,#Offset8
1139 
+static INSN_REGPARM void thumb39(u32 opcode) { SUB_RN_O8(1); }
1140 
+// SUB R2,#Offset8
1141 
+static INSN_REGPARM void thumb3A(u32 opcode) { SUB_RN_O8(2); }
1142 
+// SUB R3,#Offset8
1143 
+static INSN_REGPARM void thumb3B(u32 opcode) { SUB_RN_O8(3); }
1144 
+// SUB R4,#Offset8
1145 
+static INSN_REGPARM void thumb3C(u32 opcode) { SUB_RN_O8(4); }
1146 
+// SUB R5,#Offset8
1147 
+static INSN_REGPARM void thumb3D(u32 opcode) { SUB_RN_O8(5); }
1148 
+// SUB R6,#Offset8
1149 
+static INSN_REGPARM void thumb3E(u32 opcode) { SUB_RN_O8(6); }
1150 
+// SUB R7,#Offset8
1151 
+static INSN_REGPARM void thumb3F(u32 opcode) { SUB_RN_O8(7); }
1152 
+
1153 
+// ALU operations /////////////////////////////////////////////////////////
1154 
+
1155 
+// AND Rd, Rs
1156 
+static INSN_REGPARM void thumb40_0(u32 opcode)
1157 
+{
1158 
+  int dest = opcode & 7;
1159 
+  reg[dest].I &= reg[(opcode >> 3)&7].I;
1160 
+  N_FLAG = reg[dest].I & 0x80000000 ? true : false;
1161 
+  Z_FLAG = reg[dest].I ? false : true;
1162 
+  THUMB_CONSOLE_OUTPUT(NULL, reg[2].I);
1163 
+}
1164 
+
1165 
+// EOR Rd, Rs
1166 
+static INSN_REGPARM void thumb40_1(u32 opcode)
1167 
+{
1168 
+  int dest = opcode & 7;
1169 
+  reg[dest].I ^= reg[(opcode >> 3)&7].I;
1170 
+  N_FLAG = reg[dest].I & 0x80000000 ? true : false;
1171 
+  Z_FLAG = reg[dest].I ? false : true;
1172 
+}
1173 
+
1174 
+// LSL Rd, Rs
1175 
+static INSN_REGPARM void thumb40_2(u32 opcode)
1176 
+{
1177 
+  int dest = opcode & 7;
1178 
+  u32 value = reg[(opcode >> 3)&7].B.B0;
1179 
+  if(value) {
1180 
+    if(value == 32) {
1181 
+      value = 0;
1182 
+      C_FLAG = (reg[dest].I & 1 ? true : false);
1183 
+    } else if(value < 32) {
1184 
+      LSL_RD_RS;
1185 
+    } else {
1186 
+      value = 0;
1187 
+      C_FLAG = false;
1188 
+    }
1189 
+    reg[dest].I = value;
1190 
+  }
1191 
+  N_FLAG = reg[dest].I & 0x80000000 ? true : false;
1192 
+  Z_FLAG = reg[dest].I ? false : true;
1193 
+  clockTicks = codeTicksAccess16(armNextPC)+2;
1194 
+}
1195 
+
1196 
+// LSR Rd, Rs
1197 
+static INSN_REGPARM void thumb40_3(u32 opcode)
1198 
+{
1199 
+  int dest = opcode & 7;
1200 
+  u32 value = reg[(opcode >> 3)&7].B.B0;
1201 
+  if(value) {
1202 
+    if(value == 32) {
1203 
+      value = 0;
1204 
+      C_FLAG = (reg[dest].I & 0x80000000 ? true : false);
1205 
+    } else if(value < 32) {
1206 
+      LSR_RD_RS;
1207 
+    } else {
1208 
+      value = 0;
1209 
+      C_FLAG = false;
1210 
+    }
1211 
+    reg[dest].I = value;
1212 
+  }
1213 
+  N_FLAG = reg[dest].I & 0x80000000 ? true : false;
1214 
+  Z_FLAG = reg[dest].I ? false : true;
1215 
+  clockTicks = codeTicksAccess16(armNextPC)+2;
1216 
+}
1217 
+
1218 
+// ASR Rd, Rs
1219 
+static INSN_REGPARM void thumb41_0(u32 opcode)
1220 
+{
1221 
+  int dest = opcode & 7;
1222 
+  u32 value = reg[(opcode >> 3)&7].B.B0;
1223 
+  if(value) {
1224 
+    if(value < 32) {
1225 
+      ASR_RD_RS;
1226 
+      reg[dest].I = value;
1227 
+    } else {
1228 
+      if(reg[dest].I & 0x80000000){
1229 
+        reg[dest].I = 0xFFFFFFFF;
1230 
+        C_FLAG = true;
1231 
+      } else {
1232 
+        reg[dest].I = 0x00000000;
1233 
+        C_FLAG = false;
1234 
+      }
1235 
+    }
1236 
+  }
1237 
+  N_FLAG = reg[dest].I & 0x80000000 ? true : false;
1238 
+  Z_FLAG = reg[dest].I ? false : true;
1239 
+  clockTicks = codeTicksAccess16(armNextPC)+2;
1240 
+}
1241 
+
1242 
+// ADC Rd, Rs
1243 
+static INSN_REGPARM void thumb41_1(u32 opcode)
1244 
+{
1245 
+  int dest = opcode & 0x07;
1246 
+  u32 value = reg[(opcode >> 3)&7].I;
1247 
+  ADC_RD_RS;
1248 
+}
1249 
+
1250 
+// SBC Rd, Rs
1251 
+static INSN_REGPARM void thumb41_2(u32 opcode)
1252 
+{
1253 
+  int dest = opcode & 0x07;
1254 
+  u32 value = reg[(opcode >> 3)&7].I;
1255 
+  SBC_RD_RS;
1256 
+}
1257 
+
1258 
+// ROR Rd, Rs
1259 
+static INSN_REGPARM void thumb41_3(u32 opcode)
1260 
+{
1261 
+  int dest = opcode & 7;
1262 
+  u32 value = reg[(opcode >> 3)&7].B.B0;
1263 
+
1264 
+  if(value) {
1265 
+    value = value & 0x1f;
1266 
+    if(value == 0) {
1267 
+      C_FLAG = (reg[dest].I & 0x80000000 ? true : false);
1268 
+    } else {
1269 
+      ROR_RD_RS;
1270 
+      reg[dest].I = value;
1271 
+    }
1272 
+  }
1273 
+  clockTicks = codeTicksAccess16(armNextPC)+2;
1274 
+  N_FLAG = reg[dest].I & 0x80000000 ? true : false;
1275 
+  Z_FLAG = reg[dest].I ? false : true;
1276 
+}
1277 
+
1278 
+// TST Rd, Rs
1279 
+static INSN_REGPARM void thumb42_0(u32 opcode)
1280 
+{
1281 
+  u32 value = reg[opcode & 7].I & reg[(opcode >> 3) & 7].I;
1282 
+  N_FLAG = value & 0x80000000 ? true : false;
1283 
+  Z_FLAG = value ? false : true;
1284 
+}
1285 
+
1286 
+// NEG Rd, Rs
1287 
+static INSN_REGPARM void thumb42_1(u32 opcode)
1288 
+{
1289 
+  int dest = opcode & 7;
1290 
+  int source = (opcode >> 3) & 7;
1291 
+  NEG_RD_RS;
1292 
+}
1293 
+
1294 
+// CMP Rd, Rs
1295 
+static INSN_REGPARM void thumb42_2(u32 opcode)
1296 
+{
1297 
+  int dest = opcode & 7;
1298 
+  u32 value = reg[(opcode >> 3)&7].I;
1299 
+  CMP_RD_RS;
1300 
+}
1301 
+
1302 
+// CMN Rd, Rs
1303 
+static INSN_REGPARM void thumb42_3(u32 opcode)
1304 
+{
1305 
+  int dest = opcode & 7;
1306 
+  u32 value = reg[(opcode >> 3)&7].I;
1307 
+  CMN_RD_RS;
1308 
+}
1309 
+
1310 
+// ORR Rd, Rs
1311 
+static INSN_REGPARM void thumb43_0(u32 opcode)
1312 
+{
1313 
+  int dest = opcode & 7;
1314 
+  reg[dest].I |= reg[(opcode >> 3) & 7].I;
1315 
+  Z_FLAG = reg[dest].I ? false : true;
1316 
+  N_FLAG = reg[dest].I & 0x80000000 ? true : false;
1317 
+}
1318 
+
1319 
+// MUL Rd, Rs
1320 
+static INSN_REGPARM void thumb43_1(u32 opcode)
1321 
+{
1322 
+  clockTicks = 1;
1323 
+  int dest = opcode & 7;
1324 
+  u32 rm = reg[dest].I;
1325 
+  reg[dest].I = reg[(opcode >> 3) & 7].I * rm;
1326 
+  if (((s32)rm) < 0)
1327 
+    rm = ~rm;
1328 
+  if ((rm & 0xFFFFFF00) == 0)
1329 
+    clockTicks += 0;
1330 
+  else if ((rm & 0xFFFF0000) == 0)
1331 
+    clockTicks += 1;
1332 
+  else if ((rm & 0xFF000000) == 0)
1333 
+    clockTicks += 2;
1334 
+  else
1335 
+    clockTicks += 3;
1336 
+  busPrefetchCount = (busPrefetchCount<<clockTicks) | (0xFF>>(8-clockTicks));
1337 
+  clockTicks += codeTicksAccess16(armNextPC) + 1;
1338 
+  Z_FLAG = reg[dest].I ? false : true;
1339 
+  N_FLAG = reg[dest].I & 0x80000000 ? true : false;
1340 
+}
1341 
+
1342 
+// BIC Rd, Rs
1343 
+static INSN_REGPARM void thumb43_2(u32 opcode)
1344 
+{
1345 
+  int dest = opcode & 7;
1346 
+  reg[dest].I &= (~reg[(opcode >> 3) & 7].I);
1347 
+  Z_FLAG = reg[dest].I ? false : true;
1348 
+  N_FLAG = reg[dest].I & 0x80000000 ? true : false;
1349 
+}
1350 
+
1351 
+// MVN Rd, Rs
1352 
+static INSN_REGPARM void thumb43_3(u32 opcode)
1353 
+{
1354 
+  int dest = opcode & 7;
1355 
+  reg[dest].I = ~reg[(opcode >> 3) & 7].I;
1356 
+  Z_FLAG = reg[dest].I ? false : true;
1357 
+  N_FLAG = reg[dest].I & 0x80000000 ? true : false;
1358 
+}
1359 
+
1360 
+// High-register instructions and BX //////////////////////////////////////
1361 
+
1362 
+// ADD Rd, Hs
1363 
+static INSN_REGPARM void thumb44_1(u32 opcode)
1364 
+{
1365 
+  reg[opcode&7].I += reg[((opcode>>3)&7)+8].I;
1366 
+}
1367 
+
1368 
+// ADD Hd, Rs
1369 
+static INSN_REGPARM void thumb44_2(u32 opcode)
1370 
+{
1371 
+  reg[(opcode&7)+8].I += reg[(opcode>>3)&7].I;
1372 
+  if((opcode&7) == 7) {
1373 
+    reg[15].I &= 0xFFFFFFFE;
1374 
+    armNextPC = reg[15].I;
1375 
+    reg[15].I += 2;
1376 
+    THUMB_PREFETCH;
1377 
+    clockTicks = codeTicksAccessSeq16(armNextPC)*2
1378 
+        + codeTicksAccess16(armNextPC) + 3;
1379 
+  }
1380 
+}
1381 
+
1382 
+// ADD Hd, Hs
1383 
+static INSN_REGPARM void thumb44_3(u32 opcode)
1384 
+{
1385 
+  reg[(opcode&7)+8].I += reg[((opcode>>3)&7)+8].I;
1386 
+  if((opcode&7) == 7) {
1387 
+    reg[15].I &= 0xFFFFFFFE;
1388 
+    armNextPC = reg[15].I;
1389 
+    reg[15].I += 2;
1390 
+    THUMB_PREFETCH;
1391 
+    clockTicks = codeTicksAccessSeq16(armNextPC)*2
1392 
+        + codeTicksAccess16(armNextPC) + 3;
1393 
+  }
1394 
+}
1395 
+
1396 
+// CMP Rd, Hs
1397 
+static INSN_REGPARM void thumb45_1(u32 opcode)
1398 
+{
1399 
+  int dest = opcode & 7;
1400 
+  u32 value = reg[((opcode>>3)&7)+8].I;
1401 
+  CMP_RD_RS;
1402 
+}
1403 
+
1404 
+// CMP Hd, Rs
1405 
+static INSN_REGPARM void thumb45_2(u32 opcode)
1406 
+{
1407 
+  int dest = (opcode & 7) + 8;
1408 
+  u32 value = reg[(opcode>>3)&7].I;
1409 
+  CMP_RD_RS;
1410 
+}
1411 
+
1412 
+// CMP Hd, Hs
1413 
+static INSN_REGPARM void thumb45_3(u32 opcode)
1414 
+{
1415 
+  int dest = (opcode & 7) + 8;
1416 
+  u32 value = reg[((opcode>>3)&7)+8].I;
1417 
+  CMP_RD_RS;
1418 
+}
1419 
+
1420 
+// MOV Rd, Hs
1421 
+static INSN_REGPARM void thumb46_1(u32 opcode)
1422 
+{
1423 
+  reg[opcode&7].I = reg[((opcode>>3)&7)+8].I;
1424 
+}
1425 
+
1426 
+// MOV Hd, Rs
1427 
+static INSN_REGPARM void thumb46_2(u32 opcode)
1428 
+{
1429 
+  reg[(opcode&7)+8].I = reg[(opcode>>3)&7].I;
1430 
+  if((opcode&7) == 7) {
1431 
+    UPDATE_OLDREG;
1432 
+    reg[15].I &= 0xFFFFFFFE;
1433 
+    armNextPC = reg[15].I;
1434 
+    reg[15].I += 2;
1435 
+    THUMB_PREFETCH;
1436 
+    clockTicks = codeTicksAccessSeq16(armNextPC)*2
1437 
+        + codeTicksAccess16(armNextPC) + 3;
1438 
+  }
1439 
+}
1440 
+
1441 
+// MOV Hd, Hs
1442 
+static INSN_REGPARM void thumb46_3(u32 opcode)
1443 
+{
1444 
+  reg[(opcode&7)+8].I = reg[((opcode>>3)&7)+8].I;
1445 
+  if((opcode&7) == 7) {
1446 
+    UPDATE_OLDREG;
1447 
+    reg[15].I &= 0xFFFFFFFE;
1448 
+    armNextPC = reg[15].I;
1449 
+    reg[15].I += 2;
1450 
+    THUMB_PREFETCH;
1451 
+    clockTicks = codeTicksAccessSeq16(armNextPC)*2
1452 
+        + codeTicksAccess16(armNextPC) + 3;
1453 
+  }
1454 
+}
1455 
+
1456 
+
1457 
+// BX Rs
1458 
+static INSN_REGPARM void thumb47(u32 opcode)
1459 
+{
1460 
+  int base = (opcode >> 3) & 15;
1461 
+  busPrefetchCount=0;
1462 
+  UPDATE_OLDREG;
1463 
+  reg[15].I = reg[base].I;
1464 
+  if(reg[base].I & 1) {
1465 
+    armState = false;
1466 
+    reg[15].I &= 0xFFFFFFFE;
1467 
+    armNextPC = reg[15].I;
1468 
+    reg[15].I += 2;
1469 
+    THUMB_PREFETCH;
1470 
+    clockTicks = codeTicksAccessSeq16(armNextPC)
1471 
+        + codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 3;
1472 
+  } else {
1473 
+    armState = true;
1474 
+    reg[15].I &= 0xFFFFFFFC;
1475 
+    armNextPC = reg[15].I;
1476 
+    reg[15].I += 4;
1477 
+    ARM_PREFETCH;
1478 
+    clockTicks = codeTicksAccessSeq32(armNextPC)
1479 
+        + codeTicksAccessSeq32(armNextPC) + codeTicksAccess32(armNextPC) + 3;
1480 
+  }
1481 
+}
1482 
+
1483 
+// Load/store instructions ////////////////////////////////////////////////
1484 
+
1485 
+// LDR R0~R7,[PC, #Imm]
1486 
+static INSN_REGPARM void thumb48(u32 opcode)
1487 
+{
1488 
+  u8 regist = (opcode >> 8) & 7;
1489 
+  if (busPrefetchCount == 0)
1490 
+    busPrefetch = busPrefetchEnable;
1491 
+  u32 address = (reg[15].I & 0xFFFFFFFC) + ((opcode & 0xFF) << 2);
1492 
+  reg[regist].I = CPUReadMemoryQuick(address);
1493 
+  busPrefetchCount=0;
1494 
+  clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
1495 
+}
1496 
+
1497 
+// STR Rd, [Rs, Rn]
1498 
+static INSN_REGPARM void thumb50(u32 opcode)
1499 
+{
1500 
+  if (busPrefetchCount == 0)
1501 
+    busPrefetch = busPrefetchEnable;
1502 
+  u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1503 
+  CPUWriteMemory(address, reg[opcode & 7].I);
1504 
+  clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2;
1505 
+}
1506 
+
1507 
+// STRH Rd, [Rs, Rn]
1508 
+static INSN_REGPARM void thumb52(u32 opcode)
1509 
+{
1510 
+  if (busPrefetchCount == 0)
1511 
+    busPrefetch = busPrefetchEnable;
1512 
+  u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1513 
+  CPUWriteHalfWord(address, reg[opcode&7].W.W0);
1514 
+  clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2;
1515 
+}
1516 
+
1517 
+// STRB Rd, [Rs, Rn]
1518 
+static INSN_REGPARM void thumb54(u32 opcode)
1519 
+{
1520 
+  if (busPrefetchCount == 0)
1521 
+    busPrefetch = busPrefetchEnable;
1522 
+  u32 address = reg[(opcode>>3)&7].I + reg[(opcode >>6)&7].I;
1523 
+  CPUWriteByte(address, reg[opcode & 7].B.B0);
1524 
+  clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2;
1525 
+}
1526 
+
1527 
+// LDSB Rd, [Rs, Rn]
1528 
+static INSN_REGPARM void thumb56(u32 opcode)
1529 
+{
1530 
+  if (busPrefetchCount == 0)
1531 
+    busPrefetch = busPrefetchEnable;
1532 
+  u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1533 
+  reg[opcode&7].I = (s8)CPUReadByte(address);
1534 
+  clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1535 
+}
1536 
+
1537 
+// LDR Rd, [Rs, Rn]
1538 
+static INSN_REGPARM void thumb58(u32 opcode)
1539 
+{
1540 
+  if (busPrefetchCount == 0)
1541 
+    busPrefetch = busPrefetchEnable;
1542 
+  u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1543 
+  reg[opcode&7].I = CPUReadMemory(address);
1544 
+  clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
1545 
+}
1546 
+
1547 
+// LDRH Rd, [Rs, Rn]
1548 
+static INSN_REGPARM void thumb5A(u32 opcode)
1549 
+{
1550 
+  if (busPrefetchCount == 0)
1551 
+    busPrefetch = busPrefetchEnable;
1552 
+  u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1553 
+  reg[opcode&7].I = CPUReadHalfWord(address);
1554 
+  clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
1555 
+}
1556 
+
1557 
+// LDRB Rd, [Rs, Rn]
1558 
+static INSN_REGPARM void thumb5C(u32 opcode)
1559 
+{
1560 
+  if (busPrefetchCount == 0)
1561 
+    busPrefetch = busPrefetchEnable;
1562 
+  u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1563 
+  reg[opcode&7].I = CPUReadByte(address);
1564 
+  clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1565 
+}
1566 
+
1567 
+// LDSH Rd, [Rs, Rn]
1568 
+static INSN_REGPARM void thumb5E(u32 opcode)
1569 
+{
1570 
+  if (busPrefetchCount == 0)
1571 
+    busPrefetch = busPrefetchEnable;
1572 
+  u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
1573 
+  reg[opcode&7].I = (s16)CPUReadHalfWordSigned(address);
1574 
+  clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1575 
+}
1576 
+
1577 
+// STR Rd, [Rs, #Imm]
1578 
+static INSN_REGPARM void thumb60(u32 opcode)
1579 
+{
1580 
+  if (busPrefetchCount == 0)
1581 
+    busPrefetch = busPrefetchEnable;
1582 
+  u32 address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<2);
1583 
+  CPUWriteMemory(address, reg[opcode&7].I);
1584 
+  clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2;
1585 
+}
1586 
+
1587 
+// LDR Rd, [Rs, #Imm]
1588 
+static INSN_REGPARM void thumb68(u32 opcode)
1589 
+{
1590 
+  if (busPrefetchCount == 0)
1591 
+    busPrefetch = busPrefetchEnable;
1592 
+  u32 address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<2);
1593 
+  reg[opcode&7].I = CPUReadMemory(address);
1594 
+  clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
1595 
+}
1596 
+
1597 
+// STRB Rd, [Rs, #Imm]
1598 
+static INSN_REGPARM void thumb70(u32 opcode)
1599 
+{
1600 
+  if (busPrefetchCount == 0)
1601 
+    busPrefetch = busPrefetchEnable;
1602 
+  u32 address = reg[(opcode>>3)&7].I + (((opcode>>6)&31));
1603 
+  CPUWriteByte(address, reg[opcode&7].B.B0);
1604 
+  clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2;
1605 
+}
1606 
+
1607 
+// LDRB Rd, [Rs, #Imm]
1608 
+static INSN_REGPARM void thumb78(u32 opcode)
1609 
+{
1610 
+  if (busPrefetchCount == 0)
1611 
+    busPrefetch = busPrefetchEnable;
1612 
+  u32 address = reg[(opcode>>3)&7].I + (((opcode>>6)&31));
1613 
+  reg[opcode&7].I = CPUReadByte(address);
1614 
+  clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1615 
+}
1616 
+
1617 
+// STRH Rd, [Rs, #Imm]
1618 
+static INSN_REGPARM void thumb80(u32 opcode)
1619 
+{
1620 
+  if (busPrefetchCount == 0)
1621 
+    busPrefetch = busPrefetchEnable;
1622 
+  u32 address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<1);
1623 
+  CPUWriteHalfWord(address, reg[opcode&7].W.W0);
1624 
+  clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2;
1625 
+}
1626 
+
1627 
+// LDRH Rd, [Rs, #Imm]
1628 
+static INSN_REGPARM void thumb88(u32 opcode)
1629 
+{
1630 
+  if (busPrefetchCount == 0)
1631 
+    busPrefetch = busPrefetchEnable;
1632 
+  u32 address = reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<1);
1633 
+  reg[opcode&7].I = CPUReadHalfWord(address);
1634 
+  clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
1635 
+}
1636 
+
1637 
+// STR R0~R7, [SP, #Imm]
1638 
+static INSN_REGPARM void thumb90(u32 opcode)
1639 
+{
1640 
+  u8 regist = (opcode >> 8) & 7;
1641 
+  if (busPrefetchCount == 0)
1642 
+    busPrefetch = busPrefetchEnable;
1643 
+  u32 address = reg[13].I + ((opcode&255)<<2);
1644 
+  CPUWriteMemory(address, reg[regist].I);
1645 
+  clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2;
1646 
+}
1647 
+
1648 
+// LDR R0~R7, [SP, #Imm]
1649 
+static INSN_REGPARM void thumb98(u32 opcode)
1650 
+{
1651 
+  u8 regist = (opcode >> 8) & 7;
1652 
+  if (busPrefetchCount == 0)
1653 
+    busPrefetch = busPrefetchEnable;
1654 
+  u32 address = reg[13].I + ((opcode&255)<<2);
1655 
+  reg[regist].I = CPUReadMemoryQuick(address);
1656 
+  clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC);
1657 
+}
1658 
+
1659 
+// PC/stack-related ///////////////////////////////////////////////////////
1660 
+
1661 
+// ADD R0~R7, PC, Imm
1662 
+static INSN_REGPARM void thumbA0(u32 opcode)
1663 
+{
1664 
+  u8 regist = (opcode >> 8) & 7;
1665 
+  reg[regist].I = (reg[15].I & 0xFFFFFFFC) + ((opcode&255)<<2);
1666 
+}
1667 
+
1668 
+// ADD R0~R7, SP, Imm
1669 
+static INSN_REGPARM void thumbA8(u32 opcode)
1670 
+{
1671 
+  u8 regist = (opcode >> 8) & 7;
1672 
+  reg[regist].I = reg[13].I + ((opcode&255)<<2);
1673 
+}
1674 
+
1675 
+// ADD SP, Imm
1676 
+static INSN_REGPARM void thumbB0(u32 opcode)
1677 
+{
1678 
+  int offset = (opcode & 127) << 2;
1679 
+  if(opcode & 0x80)
1680 
+    offset = -offset;
1681 
+  reg[13].I += offset;
1682 
+}
1683 
+
1684 
+// Push and pop ///////////////////////////////////////////////////////////
1685 
+
1686 
+#define PUSH_REG(val, r)                                    \
1687 
+  if (opcode & (val)) {                                     \
1688 
+    CPUWriteMemory(address, reg[(r)].I);                    \
1689 
+    if (!count) {                                           \
1690 
+        clockTicks += 1 + dataTicksAccess32(address);       \
1691 
+    } else {                                                \
1692 
+        clockTicks += 1 + dataTicksAccessSeq32(address);    \
1693 
+    }                                                       \
1694 
+    count++;                                                \
1695 
+    address += 4;                                           \
1696 
+  }
1697 
+
1698 
+#define POP_REG(val, r)                                     \
1699 
+  if (opcode & (val)) {                                     \
1700 
+    reg[(r)].I = CPUReadMemory(address);                    \
1701 
+    if (!count) {                                           \
1702 
+        clockTicks += 1 + dataTicksAccess32(address);       \
1703 
+    } else {                                                \
1704 
+        clockTicks += 1 + dataTicksAccessSeq32(address);    \
1705 
+    }                                                       \
1706 
+    count++;                                                \
1707 
+    address += 4;                                           \
1708 
+  }
1709 
+
1710 
+// PUSH {Rlist}
1711 
+static INSN_REGPARM void thumbB4(u32 opcode)
1712 
+{
1713 
+  if (busPrefetchCount == 0)
1714 
+    busPrefetch = busPrefetchEnable;
1715 
+  int count = 0;
1716 
+  u32 temp = reg[13].I - 4 * cpuBitsSet[opcode & 0xff];
1717 
+  u32 address = temp & 0xFFFFFFFC;
1718 
+  PUSH_REG(1, 0);
1719 
+  PUSH_REG(2, 1);
1720 
+  PUSH_REG(4, 2);
1721 
+  PUSH_REG(8, 3);
1722 
+  PUSH_REG(16, 4);
1723 
+  PUSH_REG(32, 5);
1724 
+  PUSH_REG(64, 6);
1725 
+  PUSH_REG(128, 7);
1726 
+  clockTicks += 1 + codeTicksAccess16(armNextPC);
1727 
+  reg[13].I = temp;
1728 
+}
1729 
+
1730 
+// PUSH {Rlist, LR}
1731 
+static INSN_REGPARM void thumbB5(u32 opcode)
1732 
+{
1733 
+  if (busPrefetchCount == 0)
1734 
+    busPrefetch = busPrefetchEnable;
1735 
+  int count = 0;
1736 
+  u32 temp = reg[13].I - 4 - 4 * cpuBitsSet[opcode & 0xff];
1737 
+  u32 address = temp & 0xFFFFFFFC;
1738 
+  PUSH_REG(1, 0);
1739 
+  PUSH_REG(2, 1);
1740 
+  PUSH_REG(4, 2);
1741 
+  PUSH_REG(8, 3);
1742 
+  PUSH_REG(16, 4);
1743 
+  PUSH_REG(32, 5);
1744 
+  PUSH_REG(64, 6);
1745 
+  PUSH_REG(128, 7);
1746 
+  PUSH_REG(256, 14);
1747 
+  clockTicks += 1 + codeTicksAccess16(armNextPC);
1748 
+  reg[13].I = temp;
1749 
+}
1750 
+
1751 
+// POP {Rlist}
1752 
+static INSN_REGPARM void thumbBC(u32 opcode)
1753 
+{
1754 
+  if (busPrefetchCount == 0)
1755 
+    busPrefetch = busPrefetchEnable;
1756 
+  int count = 0;
1757 
+  u32 address = reg[13].I & 0xFFFFFFFC;
1758 
+  u32 temp = reg[13].I + 4*cpuBitsSet[opcode & 0xFF];
1759 
+  POP_REG(1, 0);
1760 
+  POP_REG(2, 1);
1761 
+  POP_REG(4, 2);
1762 
+  POP_REG(8, 3);
1763 
+  POP_REG(16, 4);
1764 
+  POP_REG(32, 5);
1765 
+  POP_REG(64, 6);
1766 
+  POP_REG(128, 7);
1767 
+  reg[13].I = temp;
1768 
+  clockTicks = 2 + codeTicksAccess16(armNextPC);
1769 
+}
1770 
+
1771 
+// POP {Rlist, PC}
1772 
+static INSN_REGPARM void thumbBD(u32 opcode)
1773 
+{
1774 
+  if (busPrefetchCount == 0)
1775 
+    busPrefetch = busPrefetchEnable;
1776 
+  int count = 0;
1777 
+  u32 address = reg[13].I & 0xFFFFFFFC;
1778 
+  u32 temp = reg[13].I + 4 + 4*cpuBitsSet[opcode & 0xFF];
1779 
+  POP_REG(1, 0);
1780 
+  POP_REG(2, 1);
1781 
+  POP_REG(4, 2);
1782 
+  POP_REG(8, 3);
1783 
+  POP_REG(16, 4);
1784 
+  POP_REG(32, 5);
1785 
+  POP_REG(64, 6);
1786 
+  POP_REG(128, 7);
1787 
+  reg[15].I = (CPUReadMemory(address) & 0xFFFFFFFE);
1788 
+  if (!count) {
1789 
+    clockTicks += 1 + dataTicksAccess32(address);
1790 
+  } else {
1791 
+    clockTicks += 1 + dataTicksAccessSeq32(address);
1792 
+  }
1793 
+  count++;
1794 
+  armNextPC = reg[15].I;
1795 
+  reg[15].I += 2;
1796 
+  reg[13].I = temp;
1797 
+  THUMB_PREFETCH;
1798 
+  busPrefetchCount = 0;
1799 
+  clockTicks += 3 + codeTicksAccess16(armNextPC) + codeTicksAccess16(armNextPC);
1800 
+}
1801 
+
1802 
+// Load/store multiple ////////////////////////////////////////////////////
1803 
+
1804 
+#define THUMB_STM_REG(val,r,b)                              \
1805 
+  if(opcode & (val)) {                                      \
1806 
+    CPUWriteMemory(address, reg[(r)].I);                    \
1807 
+    reg[(b)].I = temp;                                      \
1808 
+    if (!count) {                                           \
1809 
+        clockTicks += 1 + dataTicksAccess32(address);       \
1810 
+    } else {                                                \
1811 
+        clockTicks += 1 + dataTicksAccessSeq32(address);    \
1812 
+    }                                                       \
1813 
+    count++;                                                \
1814 
+    address += 4;                                           \
1815 
+  }
1816 
+
1817 
+#define THUMB_LDM_REG(val,r)                                \
1818 
+  if(opcode & (val)) {                                      \
1819 
+    reg[(r)].I = CPUReadMemory(address);                    \
1820 
+    if (!count) {                                           \
1821 
+        clockTicks += 1 + dataTicksAccess32(address);       \
1822 
+    } else {                                                \
1823 
+        clockTicks += 1 + dataTicksAccessSeq32(address);    \
1824 
+    }                                                       \
1825 
+    count++;                                                \
1826 
+    address += 4;                                           \
1827 
+  }
1828 
+
1829 
+// STM R0~7!, {Rlist}
1830 
+static INSN_REGPARM void thumbC0(u32 opcode)
1831 
+{
1832 
+  u8 regist = (opcode >> 8) & 7;
1833 
+  if (busPrefetchCount == 0)
1834 
+    busPrefetch = busPrefetchEnable;
1835 
+  u32 address = reg[regist].I & 0xFFFFFFFC;
1836 
+  u32 temp = reg[regist].I + 4*cpuBitsSet[opcode & 0xff];
1837 
+  int count = 0;
1838 
+  // store
1839 
+  THUMB_STM_REG(1, 0, regist);
1840 
+  THUMB_STM_REG(2, 1, regist);
1841 
+  THUMB_STM_REG(4, 2, regist);
1842 
+  THUMB_STM_REG(8, 3, regist);
1843 
+  THUMB_STM_REG(16, 4, regist);
1844 
+  THUMB_STM_REG(32, 5, regist);
1845 
+  THUMB_STM_REG(64, 6, regist);
1846 
+  THUMB_STM_REG(128, 7, regist);
1847 
+  clockTicks = 1 + codeTicksAccess16(armNextPC);
1848 
+}
1849 
+
1850 
+// LDM R0~R7!, {Rlist}
1851 
+static INSN_REGPARM void thumbC8(u32 opcode)
1852 
+{
1853 
+  u8 regist = (opcode >> 8) & 7;
1854 
+  if (busPrefetchCount == 0)
1855 
+    busPrefetch = busPrefetchEnable;
1856 
+  u32 address = reg[regist].I & 0xFFFFFFFC;
1857 
+  u32 temp = reg[regist].I + 4*cpuBitsSet[opcode & 0xFF];
1858 
+  int count = 0;
1859 
+  // load
1860 
+  THUMB_LDM_REG(1, 0);
1861 
+  THUMB_LDM_REG(2, 1);
1862 
+  THUMB_LDM_REG(4, 2);
1863 
+  THUMB_LDM_REG(8, 3);
1864 
+  THUMB_LDM_REG(16, 4);
1865 
+  THUMB_LDM_REG(32, 5);
1866 
+  THUMB_LDM_REG(64, 6);
1867 
+  THUMB_LDM_REG(128, 7);
1868 
+  clockTicks = 2 + codeTicksAccess16(armNextPC);
1869 
+  if(!(opcode & (1<<regist)))
1870 
+    reg[regist].I = temp;
1871 
+}
1872 
+
1873 
+// Conditional branches ///////////////////////////////////////////////////
1874 
+
1875 
+// BEQ offset
1876 
+static INSN_REGPARM void thumbD0(u32 opcode)
1877 
+{
1878 
+  UPDATE_OLDREG;
1879 
+  if(Z_FLAG) {
1880 
+    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1881 
+    armNextPC = reg[15].I;
1882 
+    reg[15].I += 2;
1883 
+    THUMB_PREFETCH;
1884 
+    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
1885 
+        codeTicksAccess16(armNextPC)+3;
1886 
+    busPrefetchCount=0;
1887 
+  }
1888 
+}
1889 
+
1890 
+// BNE offset
1891 
+static INSN_REGPARM void thumbD1(u32 opcode)
1892 
+{
1893 
+  UPDATE_OLDREG;
1894 
+  if(!Z_FLAG) {
1895 
+    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1896 
+    armNextPC = reg[15].I;
1897 
+    reg[15].I += 2;
1898 
+    THUMB_PREFETCH;
1899 
+    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
1900 
+        codeTicksAccess16(armNextPC)+3;
1901 
+    busPrefetchCount=0;
1902 
+  }
1903 
+}
1904 
+
1905 
+// BCS offset
1906 
+static INSN_REGPARM void thumbD2(u32 opcode)
1907 
+{
1908 
+  UPDATE_OLDREG;
1909 
+  if(C_FLAG) {
1910 
+    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1911 
+    armNextPC = reg[15].I;
1912 
+    reg[15].I += 2;
1913 
+    THUMB_PREFETCH;
1914 
+    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
1915 
+        codeTicksAccess16(armNextPC)+3;
1916 
+    busPrefetchCount=0;
1917 
+  }
1918 
+}
1919 
+
1920 
+// BCC offset
1921 
+static INSN_REGPARM void thumbD3(u32 opcode)
1922 
+{
1923 
+  UPDATE_OLDREG;
1924 
+  if(!C_FLAG) {
1925 
+    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1926 
+    armNextPC = reg[15].I;
1927 
+    reg[15].I += 2;
1928 
+    THUMB_PREFETCH;
1929 
+    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
1930 
+        codeTicksAccess16(armNextPC)+3;
1931 
+    busPrefetchCount=0;
1932 
+  }
1933 
+}
1934 
+
1935 
+// BMI offset
1936 
+static INSN_REGPARM void thumbD4(u32 opcode)
1937 
+{
1938 
+  UPDATE_OLDREG;
1939 
+  if(N_FLAG) {
1940 
+    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1941 
+    armNextPC = reg[15].I;
1942 
+    reg[15].I += 2;
1943 
+    THUMB_PREFETCH;
1944 
+    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
1945 
+        codeTicksAccess16(armNextPC)+3;
1946 
+    busPrefetchCount=0;
1947 
+  }
1948 
+}
1949 
+
1950 
+// BPL offset
1951 
+static INSN_REGPARM void thumbD5(u32 opcode)
1952 
+{
1953 
+  UPDATE_OLDREG;
1954 
+  if(!N_FLAG) {
1955 
+    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1956 
+    armNextPC = reg[15].I;
1957 
+    reg[15].I += 2;
1958 
+    THUMB_PREFETCH;
1959 
+    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
1960 
+        codeTicksAccess16(armNextPC)+3;
1961 
+    busPrefetchCount=0;
1962 
+  }
1963 
+}
1964 
+
1965 
+// BVS offset
1966 
+static INSN_REGPARM void thumbD6(u32 opcode)
1967 
+{
1968 
+  UPDATE_OLDREG;
1969 
+  if(V_FLAG) {
1970 
+    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1971 
+    armNextPC = reg[15].I;
1972 
+    reg[15].I += 2;
1973 
+    THUMB_PREFETCH;
1974 
+    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
1975 
+        codeTicksAccess16(armNextPC)+3;
1976 
+    busPrefetchCount=0;
1977 
+  }
1978 
+}
1979 
+
1980 
+// BVC offset
1981 
+static INSN_REGPARM void thumbD7(u32 opcode)
1982 
+{
1983 
+  UPDATE_OLDREG;
1984 
+  if(!V_FLAG) {
1985 
+    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
1986 
+    armNextPC = reg[15].I;
1987 
+    reg[15].I += 2;
1988 
+    THUMB_PREFETCH;
1989 
+    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
1990 
+        codeTicksAccess16(armNextPC)+3;
1991 
+    busPrefetchCount=0;
1992 
+  }
1993 
+}
1994 
+
1995 
+// BHI offset
1996 
+static INSN_REGPARM void thumbD8(u32 opcode)
1997 
+{
1998 
+  UPDATE_OLDREG;
1999 
+  if(C_FLAG && !Z_FLAG) {
2000 
+    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
2001 
+    armNextPC = reg[15].I;
2002 
+    reg[15].I += 2;
2003 
+    THUMB_PREFETCH;
2004 
+    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
2005 
+        codeTicksAccess16(armNextPC)+3;
2006 
+    busPrefetchCount=0;
2007 
+  }
2008 
+}
2009 
+
2010 
+// BLS offset
2011 
+static INSN_REGPARM void thumbD9(u32 opcode)
2012 
+{
2013 
+  UPDATE_OLDREG;
2014 
+  if(!C_FLAG || Z_FLAG) {
2015 
+    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
2016 
+    armNextPC = reg[15].I;
2017 
+    reg[15].I += 2;
2018 
+    THUMB_PREFETCH;
2019 
+    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
2020 
+        codeTicksAccess16(armNextPC)+3;
2021 
+    busPrefetchCount=0;
2022 
+  }
2023 
+}
2024 
+
2025 
+// BGE offset
2026 
+static INSN_REGPARM void thumbDA(u32 opcode)
2027 
+{
2028 
+  UPDATE_OLDREG;
2029 
+  if(N_FLAG == V_FLAG) {
2030 
+    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
2031 
+    armNextPC = reg[15].I;
2032 
+    reg[15].I += 2;
2033 
+    THUMB_PREFETCH;
2034 
+    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
2035 
+        codeTicksAccess16(armNextPC)+3;
2036 
+    busPrefetchCount=0;
2037 
+  }
2038 
+}
2039 
+
2040 
+// BLT offset
2041 
+static INSN_REGPARM void thumbDB(u32 opcode)
2042 
+{
2043 
+  UPDATE_OLDREG;
2044 
+  if(N_FLAG != V_FLAG) {
2045 
+    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
2046 
+    armNextPC = reg[15].I;
2047 
+    reg[15].I += 2;
2048 
+    THUMB_PREFETCH;
2049 
+    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
2050 
+        codeTicksAccess16(armNextPC)+3;
2051 
+    busPrefetchCount=0;
2052 
+  }
2053 
+}
2054 
+
2055 
+// BGT offset
2056 
+static INSN_REGPARM void thumbDC(u32 opcode)
2057 
+{
2058 
+  UPDATE_OLDREG;
2059 
+  if(!Z_FLAG && (N_FLAG == V_FLAG)) {
2060 
+    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
2061 
+    armNextPC = reg[15].I;
2062 
+    reg[15].I += 2;
2063 
+    THUMB_PREFETCH;
2064 
+    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
2065 
+        codeTicksAccess16(armNextPC)+3;
2066 
+    busPrefetchCount=0;
2067 
+  }
2068 
+}
2069 
+
2070 
+// BLE offset
2071 
+static INSN_REGPARM void thumbDD(u32 opcode)
2072 
+{
2073 
+  UPDATE_OLDREG;
2074 
+  if(Z_FLAG || (N_FLAG != V_FLAG)) {
2075 
+    reg[15].I += ((s8)(opcode & 0xFF)) << 1;
2076 
+    armNextPC = reg[15].I;
2077 
+    reg[15].I += 2;
2078 
+    THUMB_PREFETCH;
2079 
+    clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
2080 
+        codeTicksAccess16(armNextPC)+3;
2081 
+    busPrefetchCount=0;
2082 
+  }
2083 
+}
2084 
+
2085 
+// SWI, B, BL /////////////////////////////////////////////////////////////
2086 
+
2087 
+// SWI #comment
2088 
+static INSN_REGPARM void thumbDF(u32 opcode)
2089 
+{
2090 
+  u32 address = 0;
2091 
+  clockTicks = codeTicksAccessSeq16(address) + codeTicksAccessSeq16(address) +
2092 
+      codeTicksAccess16(address)+3;
2093 
+  busPrefetchCount=0;
2094 
+  CPUSoftwareInterrupt(opcode & 0xFF);
2095 
+}
2096 
+
2097 
+// B offset
2098 
+static INSN_REGPARM void thumbE0(u32 opcode)
2099 
+{
2100 
+  int offset = (opcode & 0x3FF) << 1;
2101 
+  if(opcode & 0x0400)
2102 
+    offset |= 0xFFFFF800;
2103 
+  reg[15].I += offset;
2104 
+  armNextPC = reg[15].I;
2105 
+  reg[15].I += 2;
2106 
+  THUMB_PREFETCH;
2107 
+  clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
2108 
+      codeTicksAccess16(armNextPC) + 3;
2109 
+  busPrefetchCount=0;
2110 
+}
2111 
+
2112 
+// BLL #offset (forward)
2113 
+static INSN_REGPARM void thumbF0(u32 opcode)
2114 
+{
2115 
+  int offset = (opcode & 0x7FF);
2116 
+  reg[14].I = reg[15].I + (offset << 12);
2117 
+  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2118 
+}
2119 
+
2120 
+// BLL #offset (backward)
2121 
+static INSN_REGPARM void thumbF4(u32 opcode)
2122 
+{
2123 
+  int offset = (opcode & 0x7FF);
2124 
+  reg[14].I = reg[15].I + ((offset << 12) | 0xFF800000);
2125 
+  clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
2126 
+}
2127 
+
2128 
+// BLH #offset
2129 
+static INSN_REGPARM void thumbF8(u32 opcode)
2130 
+{
2131 
+  int offset = (opcode & 0x7FF);
2132 
+  u32 temp = reg[15].I-2;
2133 
+  reg[15].I = (reg[14].I + (offset<<1))&0xFFFFFFFE;
2134 
+  armNextPC = reg[15].I;
2135 
+  reg[15].I += 2;
2136 
+  reg[14].I = temp|1;
2137 
+  THUMB_PREFETCH;
2138 
+  clockTicks = codeTicksAccessSeq16(armNextPC) +
2139 
+      codeTicksAccess16(armNextPC) + codeTicksAccessSeq16(armNextPC) + 3;
2140 
+  busPrefetchCount = 0;
2141 
+}
2142 
+
2143 
+// Instruction table //////////////////////////////////////////////////////
2144 
+
2145 
+typedef INSN_REGPARM void (*insnfunc_t)(u32 opcode);
2146 
+#define thumbUI thumbUnknownInsn
2147 
+#ifdef BKPT_SUPPORT
2148 
+ #define thumbBP thumbBreakpoint
2149 
+#else
2150 
+ #define thumbBP thumbUnknownInsn
2151 
+#endif
2152 
+static insnfunc_t thumbInsnTable[1024] = {
2153 
+  thumb00_00,thumb00_01,thumb00_02,thumb00_03,thumb00_04,thumb00_05,thumb00_06,thumb00_07,  // 00
2154 
+  thumb00_08,thumb00_09,thumb00_0A,thumb00_0B,thumb00_0C,thumb00_0D,thumb00_0E,thumb00_0F,
2155 
+  thumb00_10,thumb00_11,thumb00_12,thumb00_13,thumb00_14,thumb00_15,thumb00_16,thumb00_17,
2156 
+  thumb00_18,thumb00_19,thumb00_1A,thumb00_1B,thumb00_1C,thumb00_1D,thumb00_1E,thumb00_1F,
2157 
+  thumb08_00,thumb08_01,thumb08_02,thumb08_03,thumb08_04,thumb08_05,thumb08_06,thumb08_07,  // 08
2158 
+  thumb08_08,thumb08_09,thumb08_0A,thumb08_0B,thumb08_0C,thumb08_0D,thumb08_0E,thumb08_0F,
2159 
+  thumb08_10,thumb08_11,thumb08_12,thumb08_13,thumb08_14,thumb08_15,thumb08_16,thumb08_17,
2160 
+  thumb08_18,thumb08_19,thumb08_1A,thumb08_1B,thumb08_1C,thumb08_1D,thumb08_1E,thumb08_1F,
2161 
+  thumb10_00,thumb10_01,thumb10_02,thumb10_03,thumb10_04,thumb10_05,thumb10_06,thumb10_07,  // 10
2162 
+  thumb10_08,thumb10_09,thumb10_0A,thumb10_0B,thumb10_0C,thumb10_0D,thumb10_0E,thumb10_0F,
2163 
+  thumb10_10,thumb10_11,thumb10_12,thumb10_13,thumb10_14,thumb10_15,thumb10_16,thumb10_17,
2164 
+  thumb10_18,thumb10_19,thumb10_1A,thumb10_1B,thumb10_1C,thumb10_1D,thumb10_1E,thumb10_1F,
2165 
+  thumb18_0,thumb18_1,thumb18_2,thumb18_3,thumb18_4,thumb18_5,thumb18_6,thumb18_7,          // 18
2166 
+  thumb1A_0,thumb1A_1,thumb1A_2,thumb1A_3,thumb1A_4,thumb1A_5,thumb1A_6,thumb1A_7,
2167 
+  thumb1C_0,thumb1C_1,thumb1C_2,thumb1C_3,thumb1C_4,thumb1C_5,thumb1C_6,thumb1C_7,
2168 
+  thumb1E_0,thumb1E_1,thumb1E_2,thumb1E_3,thumb1E_4,thumb1E_5,thumb1E_6,thumb1E_7,
2169 
+  thumb20,thumb20,thumb20,thumb20,thumb21,thumb21,thumb21,thumb21,  // 20
2170 
+  thumb22,thumb22,thumb22,thumb22,thumb23,thumb23,thumb23,thumb23,
2171 
+  thumb24,thumb24,thumb24,thumb24,thumb25,thumb25,thumb25,thumb25,
2172 
+  thumb26,thumb26,thumb26,thumb26,thumb27,thumb27,thumb27,thumb27,
2173 
+  thumb28,thumb28,thumb28,thumb28,thumb29,thumb29,thumb29,thumb29,  // 28
2174 
+  thumb2A,thumb2A,thumb2A,thumb2A,thumb2B,thumb2B,thumb2B,thumb2B,
2175 
+  thumb2C,thumb2C,thumb2C,thumb2C,thumb2D,thumb2D,thumb2D,thumb2D,
2176 
+  thumb2E,thumb2E,thumb2E,thumb2E,thumb2F,thumb2F,thumb2F,thumb2F,
2177 
+  thumb30,thumb30,thumb30,thumb30,thumb31,thumb31,thumb31,thumb31,  // 30
2178 
+  thumb32,thumb32,thumb32,thumb32,thumb33,thumb33,thumb33,thumb33,
2179 
+  thumb34,thumb34,thumb34,thumb34,thumb35,thumb35,thumb35,thumb35,
2180 
+  thumb36,thumb36,thumb36,thumb36,thumb37,thumb37,thumb37,thumb37,
2181 
+  thumb38,thumb38,thumb38,thumb38,thumb39,thumb39,thumb39,thumb39,  // 38
2182 
+  thumb3A,thumb3A,thumb3A,thumb3A,thumb3B,thumb3B,thumb3B,thumb3B,
2183 
+  thumb3C,thumb3C,thumb3C,thumb3C,thumb3D,thumb3D,thumb3D,thumb3D,
2184 
+  thumb3E,thumb3E,thumb3E,thumb3E,thumb3F,thumb3F,thumb3F,thumb3F,
2185 
+  thumb40_0,thumb40_1,thumb40_2,thumb40_3,thumb41_0,thumb41_1,thumb41_2,thumb41_3,  // 40
2186 
+  thumb42_0,thumb42_1,thumb42_2,thumb42_3,thumb43_0,thumb43_1,thumb43_2,thumb43_3,
2187 
+  thumbUI,thumb44_1,thumb44_2,thumb44_3,thumbUI,thumb45_1,thumb45_2,thumb45_3,
2188 
+  thumbUI,thumb46_1,thumb46_2,thumb46_3,thumb47,thumb47,thumbUI,thumbUI,
2189 
+  thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,  // 48
2190 
+  thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,
2191 
+  thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,
2192 
+  thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,
2193 
+  thumb50,thumb50,thumb50,thumb50,thumb50,thumb50,thumb50,thumb50,  // 50
2194 
+  thumb52,thumb52,thumb52,thumb52,thumb52,thumb52,thumb52,thumb52,
2195 
+  thumb54,thumb54,thumb54,thumb54,thumb54,thumb54,thumb54,thumb54,
2196 
+  thumb56,thumb56,thumb56,thumb56,thumb56,thumb56,thumb56,thumb56,
2197 
+  thumb58,thumb58,thumb58,thumb58,thumb58,thumb58,thumb58,thumb58,  // 58
2198 
+  thumb5A,thumb5A,thumb5A,thumb5A,thumb5A,thumb5A,thumb5A,thumb5A,
2199 
+  thumb5C,thumb5C,thumb5C,thumb5C,thumb5C,thumb5C,thumb5C,thumb5C,
2200 
+  thumb5E,thumb5E,thumb5E,thumb5E,thumb5E,thumb5E,thumb5E,thumb5E,
2201 
+  thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,  // 60
2202 
+  thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,
2203 
+  thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,
2204 
+  thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,
2205 
+  thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,  // 68
2206 
+  thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,
2207 
+  thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,
2208 
+  thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,
2209 
+  thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,  // 70
2210 
+  thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,
2211 
+  thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,
2212 
+  thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,
2213 
+  thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,  // 78
2214 
+  thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,
2215 
+  thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,
2216 
+  thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,
2217 
+  thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,  // 80
2218 
+  thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,
2219 
+  thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,
2220 
+  thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,
2221 
+  thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,  // 88
2222 
+  thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,
2223 
+  thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,
2224 
+  thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,
2225 
+  thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,  // 90
2226 
+  thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,
2227 
+  thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,
2228 
+  thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,
2229 
+  thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,  // 98
2230 
+  thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,
2231 
+  thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,
2232 
+  thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,
2233 
+  thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,  // A0
2234 
+  thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,
2235 
+  thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,
2236 
+  thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,
2237 
+  thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,  // A8
2238 
+  thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,
2239 
+  thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,
2240 
+  thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,
2241 
+  thumbB0,thumbB0,thumbB0,thumbB0,thumbUI,thumbUI,thumbUI,thumbUI,  // B0
2242 
+  thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,
2243 
+  thumbB4,thumbB4,thumbB4,thumbB4,thumbB5,thumbB5,thumbB5,thumbB5,
2244 
+  thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,
2245 
+  thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,  // B8
2246 
+  thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,
2247 
+  thumbBC,thumbBC,thumbBC,thumbBC,thumbBD,thumbBD,thumbBD,thumbBD,
2248 
+  thumbBP,thumbBP,thumbBP,thumbBP,thumbUI,thumbUI,thumbUI,thumbUI,
2249 
+  thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,  // C0
2250 
+  thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,
2251 
+  thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,
2252 
+  thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,
2253 
+  thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,  // C8
2254 
+  thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,
2255 
+  thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,
2256 
+  thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,
2257 
+  thumbD0,thumbD0,thumbD0,thumbD0,thumbD1,thumbD1,thumbD1,thumbD1,  // D0
2258 
+  thumbD2,thumbD2,thumbD2,thumbD2,thumbD3,thumbD3,thumbD3,thumbD3,
2259 
+  thumbD4,thumbD4,thumbD4,thumbD4,thumbD5,thumbD5,thumbD5,thumbD5,
2260 
+  thumbD6,thumbD6,thumbD6,thumbD6,thumbD7,thumbD7,thumbD7,thumbD7,
2261 
+  thumbD8,thumbD8,thumbD8,thumbD8,thumbD9,thumbD9,thumbD9,thumbD9,  // D8
2262 
+  thumbDA,thumbDA,thumbDA,thumbDA,thumbDB,thumbDB,thumbDB,thumbDB,
2263 
+  thumbDC,thumbDC,thumbDC,thumbDC,thumbDD,thumbDD,thumbDD,thumbDD,
2264 
+  thumbUI,thumbUI,thumbUI,thumbUI,thumbDF,thumbDF,thumbDF,thumbDF,
2265 
+  thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,  // E0
2266 
+  thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,
2267 
+  thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,
2268 
+  thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,
2269 
+  thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,  // E8
2270 
+  thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,
2271 
+  thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,
2272 
+  thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,
2273 
+  thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,  // F0
2274 
+  thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,
2275 
+  thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,
2276 
+  thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,
2277 
+  thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,  // F8
2278 
+  thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,
2279 
+  thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,
2280 
+  thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,
2281 
+};
2282 
+
2283 
+// Wrapper routine (execution loop) ///////////////////////////////////////
2284 
+
2285 
+int thumbExecute()
2286 
+{
2287 
+  do {
2288 
+	  /*if( cheatsEnabled ) {
2289 
+		  cpuMasterCodeCheck();
2290 
+	  }*/
2291 
+
2292 
+    //if ((armNextPC & 0x0803FFFF) == 0x08020000)
2293 
+    //    busPrefetchCount=0x100;
2294 
+
2295 
+    u32 opcode = cpuPrefetch[0];
2296 
+    cpuPrefetch[0] = cpuPrefetch[1];
2297 
+
2298 
+    busPrefetch = false;
2299 
+    if (busPrefetchCount & 0xFFFFFF00)
2300 
+      busPrefetchCount = 0x100 | (busPrefetchCount & 0xFF);
2301 
+    clockTicks = 0;
2302 
+    u32 oldArmNextPC = armNextPC;
2303 
+#ifndef FINAL_VERSION
2304 
+    if(armNextPC == stop) {
2305 
+      armNextPC++;
2306 
+    }
2307 
+#endif
2308 
+
2309 
+    armNextPC = reg[15].I;
2310 
+    reg[15].I += 2;
2311 
+    THUMB_PREFETCH_NEXT;
2312 
+
2313 
+    (*thumbInsnTable[opcode>>6])(opcode);
2314 
+
2315 
+    if (clockTicks < 0)
2316 
+      return 0;
2317 
+    if (clockTicks==0)
2318 
+      clockTicks = codeTicksAccessSeq16(oldArmNextPC) + 1;
2319 
+    cpuTotalTicks += clockTicks;
2320 
+
2321 
+  } while (cpuTotalTicks < cpuNextEvent && !armState && !holdState && !SWITicks);
2322 
+  return 1;
2323 
+}