@@ -129,7 +129,7 @@ uint32_t MMU_struct::MMU_MASK[2][256] =

 		/* 3X*/	DUP16(0x00007FFF),

 		/* 4X*/	DUP16(0x00FFFFFF),

 		/* 5X*/	DUP16(0x000007FF),

-		/* 6X*/	DUP16(0x00FFFFFF),

+		/* 6X*/	DUP16(0x000FFFFF),

 		/* 7X*/	DUP16(0x000007FF),

 		/* 8X*/	DUP16(0x00000003),

 		/* 9X*/	DUP16(0x00000003),

@@ -147,10 +147,10 @@ uint32_t MMU_struct::MMU_MASK[2][256] =

 		/* 2X*/	DUP16(0x003FFFFF),

 		/* 3X*/	DUP8(0x00007FFF),

 				DUP8(0x0000FFFF),

-		/* 4X*/	DUP8(0x00FFFFFF),

+		/* 4X*/	DUP8(0x0000FFFF),

 				DUP8(0x0000FFFF),

 		/* 5X*/	DUP16(0x00000003),

-		/* 6X*/	DUP16(0x00FFFFFF),

+		/* 6X*/	DUP16(0x000FFFFF),

 		/* 7X*/	DUP16(0x00000003),

 		/* 8X*/	DUP16(0x00000003),

 		/* 9X*/	DUP16(0x00000003),

@@ -671,8 +671,8 @@ static inline void MMU_VRAMmapControl(uint8_t block, uint8_t VRAMBankCnt)

 	MMU_VRAMmapRefreshBank(VRAM_BANK_C);

 	MMU_VRAMmapRefreshBank(VRAM_BANK_D);

-	//printf(vramConfiguration.describe().c_str());

-	//printf("vram remapped at vcount=%d\n",nds.VCount);

+	//fprintf(stderr, vramConfiguration.describe().c_str());

+	//fprintf(stderr, "vram remapped at vcount=%d\n",nds.VCount);

 	// -------------------------------

 	// set up arm9 mirrorings

@@ -1065,7 +1065,7 @@ void FASTCALL MMU_writeToGCControl(int PROCNUM, uint32_t val)

 	T1WriteLong(MMU.MMU_MEM[TEST_PROCNUM][0x40], 0x1A4, val);

 	// Launch DMA if start flag was set to "DS Cart"

-	//printf("triggering card dma\n");

+	//fprintf(stderr, "triggering card dma\n");

 	triggerDma(EDMAMode_Card);

 }

@@ -1185,7 +1185,7 @@ static inline uint16_t read_timer(int proc, int timerIndex)

 	int32_t diff = (nds.timerCycle[proc][timerIndex] - nds_timer) & 0xFFFFFFFF;

 	assert(diff >= 0);

 	if (diff < 0)

-		printf("NEW EMULOOP BAD NEWS PLEASE REPORT: TIME READ DIFF < 0 (%d) (%d) (%d)\n", diff, timerIndex, MMU.timerMODE[proc][timerIndex]);

+		fprintf(stderr, "NEW EMULOOP BAD NEWS PLEASE REPORT: TIME READ DIFF < 0 (%d) (%d) (%d)\n", diff, timerIndex, MMU.timerMODE[proc][timerIndex]);

 	int32_t units = diff / (1 << MMU.timerMODE[proc][timerIndex]);

 	int32_t ret;

@@ -1195,7 +1195,7 @@ static inline uint16_t read_timer(int proc, int timerIndex)

 	// whichever instruction setup this counter should advance nds_timer (I think?) and the division should truncate down to 65535 immediately

 	else if (units > 65536)

 	{

-		printf("NEW EMULOOP BAD NEWS PLEASE REPORT: UNITS %d:%d = %d\n", proc, timerIndex, units);

+		fprintf(stderr, "NEW EMULOOP BAD NEWS PLEASE REPORT: UNITS %d:%d = %d\n", proc, timerIndex, units);

 		ret = 0;

 	}

 	else

@@ -1251,7 +1251,7 @@ uint32_t TGXSTAT::read32()

 	ret |= (this->gxfifo_irq & 0x3) << 30; // user's irq flags

-	//printf("vc=%03d Returning gxstat read: %08X\n",nds.VCount,ret);

+	//fprintf(stderr, "vc=%03d Returning gxstat read: %08X\n",nds.VCount,ret);

 	return ret;

 }

@@ -1266,13 +1266,13 @@ void TGXSTAT::write32(uint32_t val)

 		//mtxStack[0].position = 0;

 		this->se = 0; // clear stack error flag

 	}

-	//printf("gxstat write: %08X while gxfifo.size=%d\n",val,gxFIFO.size);

+	//fprintf(stderr, "gxstat write: %08X while gxfifo.size=%d\n",val,gxFIFO.size);

 }

 // this could be inlined...

 void MMU_struct_new::write_dma(int proc, int size, uint32_t _adr, uint32_t val)

 {

-	//printf("%08lld -- write_dma: %d %d %08X %08X\n",nds_timer,proc,size,_adr,val);

+	//fprintf(stderr, "%08lld -- write_dma: %d %d %08X %08X\n",nds_timer,proc,size,_adr,val);

 	uint32_t adr = _adr - _REG_DMA_CONTROL_MIN;

 	uint32_t chan = adr / 12;

 	uint32_t regnum = (adr - chan * 12) >> 2;

@@ -1288,7 +1288,7 @@ uint32_t MMU_struct_new::read_dma(int proc, int size, uint32_t _adr)

 	uint32_t regnum = (adr - chan * 12) >> 2;

 	uint32_t temp = MMU_new.dma[proc][chan].regs[regnum]->read(size, adr);

-	//printf("%08lld --  read_dma: %d %d %08X = %08X\n",nds_timer,proc,size,_adr,temp);

+	//fprintf(stderr, "%08lld --  read_dma: %d %d %08X = %08X\n",nds_timer,proc,size,_adr,temp);

 	return temp;

 }

@@ -1305,7 +1305,7 @@ MMU_struct_new::MMU_struct_new()

 void DmaController::write32(uint32_t val)

 {

-	//printf("dma %d,%d WRITE %08X\n",procnum,chan,val);

+	//fprintf(stderr, "dma %d,%d WRITE %08X\n",procnum,chan,val);

 	this->wordcount = val & 0x1FFFFF;

 	uint8_t wasEnable = this->enable;

 	uint32_t valhi = val >> 16;

@@ -1332,7 +1332,7 @@ void DmaController::write32(uint32_t val)

 		this->daddr = this->daddr_user;

 	}

-	//printf("dma %d,%d set to startmode %d with wordcount set to: %08X\n",procnum,chan,_startmode,wordcount);

+	//fprintf(stderr, "dma %d,%d set to startmode %d with wordcount set to: %08X\n",procnum,chan,_startmode,wordcount);

 	// analyze enabling and startmode.

 	// note that we only do this if the dma was freshly enabled.

 	// we should probably also only be latching these other regs in that case too..

@@ -1463,7 +1463,7 @@ template<int PROCNUM> void DmaController::doCopy()

 	// need to figure out what to do about this

 	if (bogarted)

 	{

-		printf("YOUR GAME IS BOGARTED!!! PLEASE REPORT!!!\n");

+		fprintf(stderr, "YOUR GAME IS BOGARTED!!! PLEASE REPORT!!!\n");

 		assert(false);

 		return;

 	}

@@ -1580,7 +1580,7 @@ uint32_t DmaController::read32()

 	ret |= this->sar << 23;

 	ret |= this->dar << 21;

 	ret |= this->wordcount;

-	//printf("dma %d,%d READ  %08X\n",procnum,chan,ret);

+	//fprintf(stderr, "dma %d,%d READ  %08X\n",procnum,chan,ret);

 	return ret;

 }

@@ -1621,30 +1621,30 @@ void FASTCALL _MMU_ARM9_write08(uint32_t adr, uint8_t val)

 		switch (adr)

 		{

 			case REG_SQRTCNT:

-				printf("ERROR 8bit SQRTCNT WRITE\n");

+				fprintf(stderr, "ERROR 8bit SQRTCNT WRITE\n");

 				return;

 			case REG_SQRTCNT + 1:

-				printf("ERROR 8bit SQRTCNT1 WRITE\n");

+				fprintf(stderr, "ERROR 8bit SQRTCNT1 WRITE\n");

 				return;

 			case REG_SQRTCNT + 2:

-				printf("ERROR 8bit SQRTCNT2 WRITE\n");

+				fprintf(stderr, "ERROR 8bit SQRTCNT2 WRITE\n");

 				return;

 			case REG_SQRTCNT + 3:

-				printf("ERROR 8bit SQRTCNT3 WRITE\n");

+				fprintf(stderr, "ERROR 8bit SQRTCNT3 WRITE\n");

 				return;

 #if 1

 			case REG_DIVCNT:

-				printf("ERROR 8bit DIVCNT WRITE\n");

+				fprintf(stderr, "ERROR 8bit DIVCNT WRITE\n");

 				return;

 			case REG_DIVCNT + 1:

-				printf("ERROR 8bit DIVCNT+1 WRITE\n");

+				fprintf(stderr, "ERROR 8bit DIVCNT+1 WRITE\n");

 				return;

 			case REG_DIVCNT + 2:

-				printf("ERROR 8bit DIVCNT+2 WRITE\n");

+				fprintf(stderr, "ERROR 8bit DIVCNT+2 WRITE\n");

 				return;

 			case REG_DIVCNT + 3:

-				printf("ERROR 8bit DIVCNT+3 WRITE\n");

+				fprintf(stderr, "ERROR 8bit DIVCNT+3 WRITE\n");

 				return;

 #endif

@@ -1734,12 +1734,12 @@ void FASTCALL _MMU_ARM9_write16(uint32_t adr, uint16_t val)

 			case REG_DIVNUMER:

 			case REG_DIVNUMER + 2:

 			case REG_DIVNUMER + 4:

-				printf("DIV: 16 write NUMER %08X. PLEASE REPORT! \n", val);

+				fprintf(stderr, "DIV: 16 write NUMER %08X. PLEASE REPORT! \n", val);

 				break;

 			case REG_DIVDENOM:

 			case REG_DIVDENOM + 2:

 			case REG_DIVDENOM + 4:

-				printf("DIV: 16 write DENOM %08X. PLEASE REPORT! \n", val);

+				fprintf(stderr, "DIV: 16 write DENOM %08X. PLEASE REPORT! \n", val);

 				break;

 #endif

 			case REG_SQRTCNT:

@@ -2024,10 +2024,10 @@ uint8_t FASTCALL _MMU_ARM9_read08(uint32_t adr)

 			// sqrtcnt isnt big enough for these to exist. but they'd probably return 0 so its ok

 			case REG_SQRTCNT + 2:

-				printf("ERROR 8bit SQRTCNT+2 READ\n");

+				fprintf(stderr, "ERROR 8bit SQRTCNT+2 READ\n");

 				return 0;

 			case REG_SQRTCNT + 3:

-				printf("ERROR 8bit SQRTCNT+3 READ\n");

+				fprintf(stderr, "ERROR 8bit SQRTCNT+3 READ\n");

 				return 0;

 			// Nostalgia's options menu requires that these work

@@ -2038,10 +2038,10 @@ uint8_t FASTCALL _MMU_ARM9_read08(uint32_t adr)

 			// divcnt isnt big enough for these to exist. but they'd probably return 0 so its ok

 			case REG_DIVCNT + 2:

-				printf("ERROR 8bit DIVCNT+2 READ\n");

+				fprintf(stderr, "ERROR 8bit DIVCNT+2 READ\n");

 				return 0;

 			case REG_DIVCNT + 3:

-				printf("ERROR 8bit DIVCNT+3 READ\n");

+				fprintf(stderr, "ERROR 8bit DIVCNT+3 READ\n");

 				return 0;

 		}

 	}

@@ -2077,14 +2077,14 @@ uint16_t FASTCALL _MMU_ARM9_read16(uint32_t adr)

 				return MMU_new.sqrt.read16();

 			// sqrtcnt isnt big enough for this to exist. but it'd probably return 0 so its ok

 			case REG_SQRTCNT + 2:

-				printf("ERROR 16bit SQRTCNT+2 READ\n");

+				fprintf(stderr, "ERROR 16bit SQRTCNT+2 READ\n");

 				return 0;

 			case REG_DIVCNT:

 				return MMU_new.div.read16();

 			// divcnt isnt big enough for this to exist. but it'd probably return 0 so its ok

 			case REG_DIVCNT + 2:

-				printf("ERROR 16bit DIVCNT+2 READ\n");

+				fprintf(stderr, "ERROR 16bit DIVCNT+2 READ\n");

 				return 0;

 			case REG_IME:

@@ -2255,7 +2255,7 @@ void FASTCALL _MMU_ARM7_write08(uint32_t adr, uint8_t val)

 				break;

 			case REG_HALTCNT:

-				//printf("halt 0x%02X\n", val);

+				//fprintf(stderr, "halt 0x%02X\n", val);

 				switch (val)

 				{

 					case 0xC0:

@@ -2310,11 +2310,11 @@ void FASTCALL _MMU_ARM7_write16(uint32_t adr, uint16_t val)

 			case REG_DISPA_VCOUNT:

 				if (nds.VCount >= 202 && nds.VCount <= 212)

 				{

-					printf("VCOUNT set to %i (previous value %i)\n", val, nds.VCount);

+					fprintf(stderr, "VCOUNT set to %i (previous value %i)\n", val, nds.VCount);

 					nds.VCount = val;

 				}

 				else

-					printf("Attempt to set VCOUNT while not within 202-212 (%i), ignored\n", nds.VCount);

+					fprintf(stderr, "Attempt to set VCOUNT while not within 202-212 (%i), ignored\n", nds.VCount);

 				return;

 			case REG_EXMEMCNT:

@@ -2379,7 +2379,7 @@ void FASTCALL _MMU_ARM7_write16(uint32_t adr, uint16_t val)

 								// our totally pathetic register handling, only the one thing we've wanted so far

 								if (MMU.powerMan_Reg[0] & PM_SYSTEM_PWR)

 								{

-									printf("SYSTEM POWERED OFF VIA ARM7 SPI POWER DEVICE\n");

+									fprintf(stderr, "SYSTEM POWERED OFF VIA ARM7 SPI POWER DEVICE\n");

 									execute = false;

 								}

 							}

@@ -2413,7 +2413,7 @@ void FASTCALL _MMU_ARM7_write16(uint32_t adr, uint16_t val)

 						}

 						int channel = (MMU.SPI_CMD & 0x70) >> 4;

-						//printf("%08X\n",channel);

+						//fprintf(stderr, "%08X\n",channel);

 						switch (channel)

 						{

 							case TSC_MEASURE_TEMP1:

@@ -174,14 +174,14 @@ uint32_t MMU_struct::MMU_MASK[2][256] =

 static const uint8_t VRAM_PAGE_UNMAPPED = 41;

 static const unsigned VRAM_LCDC_PAGES = 41;

-uint8_t vram_lcdc_map[VRAM_LCDC_PAGES];

+static uint8_t vram_lcdc_map[VRAM_LCDC_PAGES];

 // in the range of 0x06000000 - 0x06800000 in 16KB pages (the ARM9 vram mappable area)

 // this maps to 16KB pages in the LCDC buffer which is what will actually contain the data

 uint8_t vram_arm9_map[VRAM_ARM9_PAGES];

 // this chooses which banks are mapped in the 128K banks starting at 0x06000000 in ARM7

-uint8_t vram_arm7_map[2];

+static uint8_t vram_arm7_map[2];

 struct TVramBankInfo

 {

@@ -1444,9 +1444,6 @@ template<int PROCNUM> void DmaController::doCopy()

 			break;

 		case EDMADestinationUpdate_IncrementReload:

 			dstinc = sz;

-			break;

-		default:

-			bogarted = true;

 	}

 	switch (this->sar)

 	{

@@ -1460,7 +1457,6 @@ template<int PROCNUM> void DmaController::doCopy()

 			srcinc = 0;

 			break;

 		case EDMASourceUpdate_Invalid:

-		default:

 			bogarted = true;

 	}

@@ -433,7 +433,7 @@ static inline void MMU_VRAMmapRefreshBank(int bank)

 					MMU.texInfo.textureSlotAddr[ofs] = MMU_vram_physical(vram_bank_info[bank].page_addr);

 					break;

 				case 4: // BGB or BOBJ

-					if (bank == VRAM_BANK_C) 

+					if (bank == VRAM_BANK_C)

 					{

 						vramConfiguration.banks[bank].purpose = VramConfiguration::BBG;

 						MMU_vram_arm9(bank, VRAM_PAGE_BBG); // BBG

@@ -604,7 +604,7 @@ void MMU_VRAM_unmap_all()

 	vram_arm7_map[0] = VRAM_PAGE_UNMAPPED;

 	vram_arm7_map[1] = VRAM_PAGE_UNMAPPED;

-	for (int i = 0; i < VRAM_LCDC_PAGES; ++i)

+	for (unsigned i = 0; i < VRAM_LCDC_PAGES; ++i)

 		vram_lcdc_map[i] = VRAM_PAGE_UNMAPPED;

 	for (int i = 0; i < VRAM_ARM9_PAGES; ++i)

 		vram_arm9_map[i] = VRAM_PAGE_UNMAPPED;

@@ -636,8 +636,8 @@ static inline void MMU_VRAMmapControl(uint8_t block, uint8_t VRAMBankCnt)

 		return;

 	}

-	//f irst, save the texture info so we can check it for changes and trigger purges of the texcache

-	MMU_struct::TextureInfo oldTexInfo = MMU.texInfo;

+	// first, save the texture info so we can check it for changes and trigger purges of the texcache

+	//MMU_struct::TextureInfo oldTexInfo = MMU.texInfo;

 	// unmap everything

 	MMU_VRAM_unmap_all();

@@ -664,7 +664,7 @@ static inline void MMU_VRAMmapControl(uint8_t block, uint8_t VRAMBankCnt)

 	MMU_VRAMmapRefreshBank(VRAM_BANK_E);

 	// zero 21-jun-2012

 	// tomwi's streaming music demo sets A and D to ABG (the A is an accident).

-	// in this case, D should get priority. 

+	// in this case, D should get priority.

 	// this is somewhat risky. will it break other things?

 	MMU_VRAMmapRefreshBank(VRAM_BANK_A);

 	MMU_VRAMmapRefreshBank(VRAM_BANK_B);

@@ -1392,6 +1392,9 @@ void DmaController::exec()

 		{

 			case EDMAMode_Immediate:

 				this->triggered = true;

+				break;

+			default:

+				break;

 		}

 		if (this->triggered)

@@ -2244,7 +2247,7 @@ void FASTCALL _MMU_ARM7_write08(uint32_t adr, uint8_t val)

 				// The NDS7 register can be written to only from code executed in BIOS.

 				if (NDS_ARM7.instruct_adr > 0x3FFF)

 					return;

-				

+

 				// hack for patched firmwares

 				if (val == 1)

 				{

@@ -214,7 +214,7 @@ static const uint32_t ARM7_HACKY_SIWRAM_LOCATION = 0x03000000;

 // NOTE - this whole approach is probably fundamentally wrong.

 // according to dasShiny research, its possible to map multiple banks to the same addresses. something more sophisticated would be needed.

 // however, it hasnt proven necessary yet for any known test case.

-template<int PROCNUM> static inline uint32_t MMU_LCDmap(uint32_t addr, bool &unmapped, bool &restricted)

+static inline uint32_t MMU_LCDmap(int PROCNUM, uint32_t addr, bool &unmapped, bool &restricted)

 {

 	unmapped = false;

 	restricted = false; // this will track whether 8bit writes are allowed

@@ -988,7 +988,7 @@ uint16_t DSI_TSC::read16()

 // TODO:

 // NAND flash support (used in Made in Ore/WarioWare D.I.Y.)

-template<int PROCNUM> void FASTCALL MMU_writeToGCControl(uint32_t val)

+void FASTCALL MMU_writeToGCControl(int PROCNUM, uint32_t val)

 {

 	int TEST_PROCNUM = PROCNUM;

 	nds_dscard &card = MMU.dscard[TEST_PROCNUM];

@@ -1069,7 +1069,7 @@ template<int PROCNUM> void FASTCALL MMU_writeToGCControl(uint32_t val)

 	triggerDma(EDMAMode_Card);

 }

-template<int PROCNUM> uint32_t MMU_readFromGC()

+uint32_t MMU_readFromGC(int PROCNUM)

 {

 	int TEST_PROCNUM = PROCNUM;

@@ -1109,7 +1109,7 @@ template<int PROCNUM> uint32_t MMU_readFromGC()

 	return val;

 }

-template<int PROCNUM> static void REG_IF_WriteByte(uint32_t addr, uint8_t val)

+static void REG_IF_WriteByte(int PROCNUM, uint32_t addr, uint8_t val)

 {

 	// the following bits are generated from logic and should not be affected here

 	// Bit 21    NDS9 only: Geometry Command FIFO

@@ -1132,18 +1132,18 @@ template<int PROCNUM> static void REG_IF_WriteByte(uint32_t addr, uint8_t val)

 	NDS_Reschedule();

 }

-template<int PROCNUM> static void REG_IF_WriteWord(uint32_t addr, uint16_t val)

+static void REG_IF_WriteWord(int PROCNUM, uint32_t addr, uint16_t val)

 {

-	REG_IF_WriteByte<PROCNUM>(addr, val & 0xFF);

-	REG_IF_WriteByte<PROCNUM>(addr + 1, (val >> 8) & 0xFF);

+	REG_IF_WriteByte(PROCNUM, addr, val & 0xFF);

+	REG_IF_WriteByte(PROCNUM, addr + 1, (val >> 8) & 0xFF);

 }

-template<int PROCNUM> static void REG_IF_WriteLong(uint32_t val)

+static void REG_IF_WriteLong(int PROCNUM, uint32_t val)

 {

-	REG_IF_WriteByte<PROCNUM>(0, val & 0xFF);

-	REG_IF_WriteByte<PROCNUM>(1, (val >> 8) & 0xFF);

-	REG_IF_WriteByte<PROCNUM>(2, (val >> 16) & 0xFF);

-	REG_IF_WriteByte<PROCNUM>(3, (val >> 24) & 0xFF);

+	REG_IF_WriteByte(PROCNUM, 0, val & 0xFF);

+	REG_IF_WriteByte(PROCNUM, 1, (val >> 8) & 0xFF);

+	REG_IF_WriteByte(PROCNUM, 2, (val >> 16) & 0xFF);

+	REG_IF_WriteByte(PROCNUM, 3, (val >> 24) & 0xFF);

 }

 template<int PROCNUM> uint32_t MMU_struct::gen_IF()

@@ -1650,16 +1650,16 @@ void FASTCALL _MMU_ARM9_write08(uint32_t adr, uint8_t val)

 #endif

 			case REG_IF:

-				REG_IF_WriteByte<ARMCPU_ARM9>(0, val);

+				REG_IF_WriteByte(ARMCPU_ARM9, 0, val);

 				break;

 			case REG_IF + 1:

-				REG_IF_WriteByte<ARMCPU_ARM9>(1, val);

+				REG_IF_WriteByte(ARMCPU_ARM9, 1, val);

 				break;

 			case REG_IF + 2:

-				REG_IF_WriteByte<ARMCPU_ARM9>(2, val);

+				REG_IF_WriteByte(ARMCPU_ARM9, 2, val);

 				break;

 			case REG_IF + 3:

-				REG_IF_WriteByte<ARMCPU_ARM9>(3, val);

+				REG_IF_WriteByte(ARMCPU_ARM9, 3, val);

 				break;

 			case REG_VRAMCNTA:

@@ -1779,10 +1779,11 @@ void FASTCALL _MMU_ARM9_write16(uint32_t adr, uint16_t val)

 				MMU.reg_IE[ARMCPU_ARM9] = (MMU.reg_IE[ARMCPU_ARM9] & 0xFFFF) | (val << 16);

 				return;

 			case REG_IF:

-				REG_IF_WriteWord<ARMCPU_ARM9>(0, val);

+				REG_IF_WriteWord(ARMCPU_ARM9, 0, val);

+				return;

+			case REG_IF + 2:

+				REG_IF_WriteWord(ARMCPU_ARM9, 2, val);

 				return;

-			case REG_IF+2:

-				REG_IF_WriteWord<ARMCPU_ARM9>(2, val); return;

 			case REG_IPCSYNC:

 				MMU_IPCSync(ARMCPU_ARM9, val);

@@ -1808,10 +1809,10 @@ void FASTCALL _MMU_ARM9_write16(uint32_t adr, uint16_t val)

 			}

 			case REG_GCROMCTRL:

-				MMU_writeToGCControl<ARMCPU_ARM9>((T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1A4) & 0xFFFF0000) | val);

+				MMU_writeToGCControl(ARMCPU_ARM9, (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1A4) & 0xFFFF0000) | val);

 				return;

 			case REG_GCROMCTRL + 2:

-				MMU_writeToGCControl<ARMCPU_ARM9>((T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1A4) & 0xFFFF) | (val << 16));

+				MMU_writeToGCControl(ARMCPU_ARM9, (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1A4) & 0xFFFF) | (val << 16));

 				return;

 		}

@@ -1820,7 +1821,7 @@ void FASTCALL _MMU_ARM9_write16(uint32_t adr, uint16_t val)

 	}

 	bool unmapped, restricted;

-	adr = MMU_LCDmap<ARMCPU_ARM9>(adr, unmapped, restricted);

+	adr = MMU_LCDmap(ARMCPU_ARM9, adr, unmapped, restricted);

 	if (unmapped)

 		return;

@@ -1892,7 +1893,7 @@ void FASTCALL _MMU_ARM9_write32(uint32_t adr, uint32_t val)

 				return;

 			case REG_IF:

-				REG_IF_WriteLong<ARMCPU_ARM9>(val);

+				REG_IF_WriteLong(ARMCPU_ARM9, val);

 				return;

 			case REG_TM0CNTL:

@@ -1953,7 +1954,7 @@ void FASTCALL _MMU_ARM9_write32(uint32_t adr, uint32_t val)

 				return;

 			case REG_GCROMCTRL:

-				MMU_writeToGCControl<ARMCPU_ARM9>(val);

+				MMU_writeToGCControl(ARMCPU_ARM9, val);

 				return;

 			case REG_DISPA_DISPCAPCNT:

 				T1WriteLong(MMU.ARM9_REG, 0x64, val);

@@ -1969,7 +1970,7 @@ void FASTCALL _MMU_ARM9_write32(uint32_t adr, uint32_t val)

 	}

 	bool unmapped, restricted;

-	adr = MMU_LCDmap<ARMCPU_ARM9>(adr, unmapped, restricted);

+	adr = MMU_LCDmap(ARMCPU_ARM9, adr, unmapped, restricted);

 	if (unmapped)

 		return;

@@ -2047,7 +2048,7 @@ uint8_t FASTCALL _MMU_ARM9_read08(uint32_t adr)

 	}

 	bool unmapped, restricted;

-	adr = MMU_LCDmap<ARMCPU_ARM9>(adr, unmapped, restricted);

+	adr = MMU_LCDmap(ARMCPU_ARM9, adr, unmapped, restricted);

 	if (unmapped)

 		return 0;

@@ -2181,7 +2182,7 @@ uint32_t FASTCALL _MMU_ARM9_read32(uint32_t adr)

 			}

 			case REG_GCDATAIN:

-				return MMU_readFromGC<ARMCPU_ARM9>();

+				return MMU_readFromGC(ARMCPU_ARM9);

 		}

 		return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr >> 20]);

 	}

@@ -2227,16 +2228,16 @@ void FASTCALL _MMU_ARM7_write08(uint32_t adr, uint8_t val)

 		switch (adr)

 		{

 			case REG_IF:

-				REG_IF_WriteByte<ARMCPU_ARM7>(0, val);

+				REG_IF_WriteByte(ARMCPU_ARM7, 0, val);

 				break;

 			case REG_IF + 1:

-				REG_IF_WriteByte<ARMCPU_ARM7>(1, val);

+				REG_IF_WriteByte(ARMCPU_ARM7, 1, val);

 				break;

 			case REG_IF + 2:

-				REG_IF_WriteByte<ARMCPU_ARM7>(2, val);

+				REG_IF_WriteByte(ARMCPU_ARM7, 2, val);

 				break;

 			case REG_IF + 3:

-				REG_IF_WriteByte<ARMCPU_ARM7>(3, val);

+				REG_IF_WriteByte(ARMCPU_ARM7, 3, val);

 				break;

 			case REG_POSTFLG:

@@ -2530,10 +2531,10 @@ void FASTCALL _MMU_ARM7_write16(uint32_t adr, uint16_t val)

 				return;

 			case REG_IF:

-				REG_IF_WriteWord<ARMCPU_ARM7>(0, val);

+				REG_IF_WriteWord(ARMCPU_ARM7, 0, val);

 				return;

 			case REG_IF + 2:

-				REG_IF_WriteWord<ARMCPU_ARM7>(2, val);

+				REG_IF_WriteWord(ARMCPU_ARM7, 2, val);

 				return;

 			case REG_IPCSYNC:

@@ -2560,10 +2561,10 @@ void FASTCALL _MMU_ARM7_write16(uint32_t adr, uint16_t val)

 			}

 			case REG_GCROMCTRL:

-				MMU_writeToGCControl<ARMCPU_ARM7>((T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x1A4) & 0xFFFF0000) | val);

+				MMU_writeToGCControl(ARMCPU_ARM7, (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x1A4) & 0xFFFF0000) | val);

 				return;

 			case REG_GCROMCTRL + 2:

-				MMU_writeToGCControl<ARMCPU_ARM7>((T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x1A4) & 0xFFFF) | (val << 16));

+				MMU_writeToGCControl(ARMCPU_ARM7, (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x1A4) & 0xFFFF) | (val << 16));

 				return;

 		}

@@ -2619,7 +2620,7 @@ void FASTCALL _MMU_ARM7_write32(uint32_t adr, uint32_t val)

 				return;

 			case REG_IF:

-				REG_IF_WriteLong<ARMCPU_ARM7>(val);

+				REG_IF_WriteLong(ARMCPU_ARM7, val);

 				return;

 			case REG_TM0CNTL:

@@ -2645,7 +2646,7 @@ void FASTCALL _MMU_ARM7_write32(uint32_t adr, uint32_t val)

 				return;

 			case REG_GCROMCTRL:

-				MMU_writeToGCControl<ARMCPU_ARM7>(val);

+				MMU_writeToGCControl(ARMCPU_ARM7, val);

 				return;

 			case REG_GCDATAIN:

@@ -2818,7 +2819,7 @@ uint32_t FASTCALL _MMU_ARM7_read32(uint32_t adr)

 			case REG_GCROMCTRL:

 				break;

 			case REG_GCDATAIN:

-				return MMU_readFromGC<ARMCPU_ARM7>();

+				return MMU_readFromGC(ARMCPU_ARM7);

 			case REG_VRAMSTAT:

 				// make sure WRAMSTAT is stashed and then fallthrough return the value from memory. i know, gross.

@@ -41,7 +41,7 @@ static uint64_t isqrt(uint64_t x)

 	 * is even, and the one bit is as far left as is consistant

 	 * with that condition.)

 	 */

-	uint64_t squaredbit = static_cast<uint64_t>((static_cast<uint64_t>(~0LL) >> 1) & ~(static_cast<uint64_t>(~0LL) >> 2));

+	uint64_t squaredbit = (~0LL >> 1) & ~(~0LL >> 2);

 	/* This portable load replaces the loop that used to be

 	 * here, and was donated by  legalize@xmission.com

 	 */

@@ -860,12 +860,12 @@ static void execsqrt()

 	if (mode)

 	{

 		uint64_t v = T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8);

-		ret = static_cast<uint32_t>(isqrt(v));

+		ret = isqrt(v) & 0xFFFFFFFF;

 	}

 	else

 	{

 		uint32_t v = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8);

-		ret = static_cast<uint32_t>(isqrt(v));

+		ret = isqrt(v) & 0xFFFFFFFF;

 	}

 	// clear the result while the sqrt unit is busy

@@ -889,20 +889,20 @@ static void execdiv()

 	switch (mode)

 	{

 		case 0: // 32/32

-			num = static_cast<int64_t>(static_cast<int32_t>(T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290)));

-			den = static_cast<int64_t>(static_cast<int32_t>(T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298)));

+			num = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);

+			den = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);

 			MMU.divCycles = nds_timer + 36;

 			break;

 		case 1: // 64/32

-		case 3: //gbatek says this is same as mode 1

-			num = static_cast<int64_t>(T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290));

-			den = static_cast<int64_t>(static_cast<int32_t>(T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298)));

+		case 3: // gbatek says this is same as mode 1

+			num = T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);

+			den = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);

 			MMU.divCycles = nds_timer + 68;

 			break;

 		case 2: // 64/64

 		default:

-			num = static_cast<int64_t>(T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290));

-			den = static_cast<int64_t>(T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298));

+			num = T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);

+			den = T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);

 			MMU.divCycles = nds_timer + 68;

 	}

@@ -912,7 +912,7 @@ static void execdiv()

 		mod = num;

 		// the DIV0 flag in DIVCNT is set only if the full 64bit DIV_DENOM value is zero, even in 32bit mode

-		if (!static_cast<uint64_t>(T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298)))

+		if (!T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298))

 			MMU_new.div.div0 = 1;

 	}

 	else

@@ -958,7 +958,7 @@ uint16_t DSI_TSC::write16(uint16_t val)

 			return this->read16();

 		case 1:

 			if (!this->read_flag)

-				this->registers[this->reg_selection] = static_cast<uint8_t>(val);

+				this->registers[this->reg_selection] = val & 0xFF;

 			ret = this->read16();

 			++this->reg_selection;

 			this->reg_selection &= 0x7F;

@@ -1128,7 +1128,7 @@ template<int PROCNUM> static void REG_IF_WriteByte(uint32_t addr, uint8_t val)

 	// ZERO 01-dec-2010 : I am no longer sure this approach is correct.. it proved to be wrong for IPC fifo.......

 	// it seems as if IF bits should always be cached (only the user can clear them)

-	MMU.reg_IF_bits[PROCNUM] &= ~(static_cast<uint32_t>(val) << (addr << 3));

+	MMU.reg_IF_bits[PROCNUM] &= ~(val << (addr << 3));

 	NDS_Reschedule();

 }

@@ -1182,7 +1182,7 @@ static inline uint16_t read_timer(int proc, int timerIndex)

 		return MMU.timer[proc][timerIndex];

 	// for unchained timers, we do not keep the timer up to date. its value will need to be calculated here

-	int32_t diff = static_cast<int32_t>(nds.timerCycle[proc][timerIndex] - nds_timer);

+	int32_t diff = (nds.timerCycle[proc][timerIndex] - nds_timer) & 0xFFFFFFFF;

 	assert(diff >= 0);

 	if (diff < 0)

 		printf("NEW EMULOOP BAD NEWS PLEASE REPORT: TIME READ DIFF < 0 (%d) (%d) (%d)\n", diff, timerIndex, MMU.timerMODE[proc][timerIndex]);

@@ -1201,7 +1201,7 @@ static inline uint16_t read_timer(int proc, int timerIndex)

 	else

 		ret = 65535 - units;

-	return static_cast<uint16_t>(ret);

+	return ret & 0xFFFF;

 }

 static inline void write_timer(int proc, int timerIndex, uint16_t val)

@@ -1311,13 +1311,13 @@ void DmaController::write32(uint32_t val)

 	uint32_t valhi = val >> 16;

 	this->dar = static_cast<EDMADestinationUpdate>((valhi >> 5) & 3);

 	this->sar = static_cast<EDMASourceUpdate>((valhi >> 7) & 3);

-	this->repeatMode = static_cast<uint8_t>(BIT9(valhi));

+	this->repeatMode = BIT9(valhi);

 	this->bitWidth = static_cast<EDMABitWidth>(BIT10(valhi));

 	this->_startmode = (valhi >> 11) & 7;

 	if (this->procnum == ARMCPU_ARM7)

 		this->_startmode &= 6;

-	this->irq = static_cast<uint8_t>(BIT14(valhi));

-	this->enable = static_cast<uint8_t>(BIT15(valhi));

+	this->irq = BIT14(valhi);

+	this->enable = BIT15(valhi);

 	// make sure we don't get any old triggers

 	if (!wasEnable && this->enable)

@@ -1434,7 +1434,7 @@ template<int PROCNUM> void DmaController::doCopy()

 			dstinc = sz;

 			break;

 		case EDMADestinationUpdate_Decrement:

-			dstinc = static_cast<uint32_t>(-static_cast<int32_t>(sz));

+			dstinc = -static_cast<int32_t>(sz);

 			break;

 		case EDMADestinationUpdate_Fixed:

 			dstinc = 0;

@@ -1451,7 +1451,7 @@ template<int PROCNUM> void DmaController::doCopy()

 			srcinc = sz;

 			break;

 		case EDMASourceUpdate_Decrement:

-			srcinc = static_cast<uint32_t>(-static_cast<int32_t>(sz));

+			srcinc = -static_cast<int32_t>(sz);

 			break;

 		case EDMASourceUpdate_Fixed:

 			srcinc = 0;

@@ -1479,7 +1479,7 @@ template<int PROCNUM> void DmaController::doCopy()

 	// we might make another function to do just the raw copy op which can use them with checks

 	// outside the loop

 	int time_elapsed = 0;

-	for (int32_t i = static_cast<int32_t>(todo); i > 0; --i)

+	for (int32_t i = todo; i > 0; --i)

 	{

 		if (sz == 4)

 		{

@@ -1672,7 +1672,7 @@ void FASTCALL _MMU_ARM9_write08(uint32_t adr, uint8_t val)

 			case REG_WRAMCNT:

 			case REG_VRAMCNTH:

 			case REG_VRAMCNTI:

-				MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA), val);

+				MMU_VRAMmapControl(adr - REG_VRAMCNTA, val);

 		}

 		MMU.MMU_MEM[ARMCPU_ARM9][adr >> 20][adr & MMU.MMU_MASK[ARMCPU_ARM9][adr >> 20]] = val;

@@ -1761,8 +1761,8 @@ void FASTCALL _MMU_ARM9_write16(uint32_t adr, uint16_t val)

 			case REG_VRAMCNTE:

 			case REG_VRAMCNTG:

 			case REG_VRAMCNTH:

-				MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA), val & 0xFF);

-				MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA + 1), val >> 8);

+				MMU_VRAMmapControl(adr - REG_VRAMCNTA, val & 0xFF);

+				MMU_VRAMmapControl(adr - REG_VRAMCNTA + 1, val >> 8);

 				break;

 			case REG_IME:

@@ -1776,7 +1776,7 @@ void FASTCALL _MMU_ARM9_write16(uint32_t adr, uint16_t val)

 				return;

 			case REG_IE + 2:

 				NDS_Reschedule();

-				MMU.reg_IE[ARMCPU_ARM9] = (MMU.reg_IE[ARMCPU_ARM9] & 0xFFFF) | (static_cast<uint32_t>(val) << 16);

+				MMU.reg_IE[ARMCPU_ARM9] = (MMU.reg_IE[ARMCPU_ARM9] & 0xFFFF) | (val << 16);

 				return;

 			case REG_IF:

 				REG_IF_WriteWord<ARMCPU_ARM9>(0, val);

@@ -1811,7 +1811,7 @@ void FASTCALL _MMU_ARM9_write16(uint32_t adr, uint16_t val)

 				MMU_writeToGCControl<ARMCPU_ARM9>((T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1A4) & 0xFFFF0000) | val);

 				return;

 			case REG_GCROMCTRL + 2:

-				MMU_writeToGCControl<ARMCPU_ARM9>((T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1A4) & 0xFFFF) | (static_cast<uint32_t>(val) << 16));

+				MMU_writeToGCControl<ARMCPU_ARM9>((T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1A4) & 0xFFFF) | (val << 16));

 				return;

 		}

@@ -1862,22 +1862,22 @@ void FASTCALL _MMU_ARM9_write32(uint32_t adr, uint32_t val)

 		switch (adr)

 		{

 			case REG_SQRTCNT:

-				MMU_new.sqrt.write16(static_cast<uint16_t>(val));

+				MMU_new.sqrt.write16(val & 0xFFFF);

 				return;

 			case REG_DIVCNT:

-				MMU_new.div.write16(static_cast<uint16_t>(val));

+				MMU_new.div.write16(val & 0xFFFF);

 				return;

 			case REG_VRAMCNTA:

 			case REG_VRAMCNTE:

-				MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA), val & 0xFF);

-				MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA + 1), (val >> 8) & 0xFF);

-				MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA + 2), (val >> 16) & 0xFF);

-				MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA + 3), (val >> 24) & 0xFF);

+				MMU_VRAMmapControl(adr - REG_VRAMCNTA, val & 0xFF);

+				MMU_VRAMmapControl(adr - REG_VRAMCNTA + 1, (val >> 8) & 0xFF);

+				MMU_VRAMmapControl(adr - REG_VRAMCNTA + 2, (val >> 16) & 0xFF);

+				MMU_VRAMmapControl(adr - REG_VRAMCNTA + 3, (val >> 24) & 0xFF);

 				break;

 			case REG_VRAMCNTH:

-				MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA), val & 0xFF);

-				MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA + 1), (val >> 8) & 0xFF);

+				MMU_VRAMmapControl(adr - REG_VRAMCNTA, val & 0xFF);

+				MMU_VRAMmapControl(adr - REG_VRAMCNTA + 1, (val >> 8) & 0xFF);

 				break;

 			case REG_IME:

@@ -1901,8 +1901,8 @@ void FASTCALL _MMU_ARM9_write32(uint32_t adr, uint32_t val)

 			case REG_TM3CNTL:

 			{

 				int timerIndex = (adr >> 2) & 0x3;

-				MMU.timerReload[ARMCPU_ARM9][timerIndex] = static_cast<uint16_t>(val);

-				T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & 0xFFF, static_cast<uint16_t>(val));

+				MMU.timerReload[ARMCPU_ARM9][timerIndex] = val & 0xFFFF;

+				T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & 0xFFF, val & 0xFFFF);

 				write_timer(ARMCPU_ARM9, timerIndex, val >> 16);

 				return;

 			}

@@ -1946,7 +1946,7 @@ void FASTCALL _MMU_ARM9_write32(uint32_t adr, uint32_t val)

 				MMU_IPCSync(ARMCPU_ARM9, val);

 				return;

 			case REG_IPCFIFOCNT:

-				IPC_FIFOcnt(ARMCPU_ARM9, static_cast<uint16_t>(val));

+				IPC_FIFOcnt(ARMCPU_ARM9, val & 0xFFFF);

 				return;

 			case REG_IPCFIFOSEND:

 				IPC_FIFOsend(ARMCPU_ARM9, val);

@@ -2001,18 +2001,18 @@ uint8_t FASTCALL _MMU_ARM9_read08(uint32_t adr)

 		//Address is an IO register

 		if (MMU_new.is_dma(adr))

-			return static_cast<uint8_t>(MMU_new.read_dma(ARMCPU_ARM9, 8, adr));

+			return MMU_new.read_dma(ARMCPU_ARM9, 8, adr) & 0xFF;

 		switch (adr)

 		{

 			case REG_IF:

-				return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM9>());

+				return MMU.gen_IF<ARMCPU_ARM9>() & 0xFF;

 			case REG_IF + 1:

-				return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM9>() >> 8);

+				return (MMU.gen_IF<ARMCPU_ARM9>() >> 8) & 0xFF;

 			case REG_IF + 2:

-				return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM9>() >> 16);

+				return (MMU.gen_IF<ARMCPU_ARM9>() >> 16) & 0xFF;

 			case REG_IF + 3:

-				return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM9>() >> 24);

+				return (MMU.gen_IF<ARMCPU_ARM9>() >> 24) & 0xFF;

 			case REG_WRAMCNT:

 				return MMU.WRAMCNT;

@@ -2068,7 +2068,7 @@ uint16_t FASTCALL _MMU_ARM9_read16(uint32_t adr)

 	if ((adr >> 24) == 4)

 	{

 		if (MMU_new.is_dma(adr))

-			return static_cast<uint16_t>(MMU_new.read_dma(ARMCPU_ARM9, 16, adr));

+			return MMU_new.read_dma(ARMCPU_ARM9, 16, adr) & 0xFFFF;

 		// Address is an IO register

 		switch (adr)

@@ -2088,21 +2088,21 @@ uint16_t FASTCALL _MMU_ARM9_read16(uint32_t adr)

 				return 0;

 			case REG_IME:

-				return static_cast<uint16_t>(MMU.reg_IME[ARMCPU_ARM9]);

+				return MMU.reg_IME[ARMCPU_ARM9] & 0xFFFF;

 			// WRAMCNT is readable but VRAMCNT is not, so just return WRAM's value

 			case REG_VRAMCNTG:

 				return MMU.WRAMCNT << 8;

 			case REG_IE:

-				return static_cast<uint16_t>(MMU.reg_IE[ARMCPU_ARM9]);

+				return MMU.reg_IE[ARMCPU_ARM9] & 0xFFFF;

 			case REG_IE + 2:

-				return static_cast<uint16_t>(MMU.reg_IE[ARMCPU_ARM9] >> 16);

+				return (MMU.reg_IE[ARMCPU_ARM9] >> 16) & 0xFFFF;

 			case REG_IF:

-				return static_cast<uint16_t>(MMU.gen_IF<ARMCPU_ARM9>());

+				return MMU.gen_IF<ARMCPU_ARM9>() & 0xFFFF;

 			case REG_IF + 2:

-				return static_cast<uint16_t>(MMU.gen_IF<ARMCPU_ARM9>() >> 16);

+				return (MMU.gen_IF<ARMCPU_ARM9>() >> 16) & 0xFFFF;

 			case REG_TM0CNTL:

 			case REG_TM1CNTL:

@@ -2372,7 +2372,7 @@ void FASTCALL _MMU_ARM7_write16(uint32_t adr, uint16_t val)

 							else

 							{

 								// write

-								MMU.powerMan_Reg[reg] = static_cast<uint8_t>(val);

+								MMU.powerMan_Reg[reg] = val & 0xFF;

 								static const uint32_t PM_SYSTEM_PWR = BIT(6); /*!< \brief  Turn the power *off* if set */

@@ -2395,7 +2395,7 @@ void FASTCALL _MMU_ARM7_write16(uint32_t adr, uint16_t val)

 							T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_SPIDATA >> 20) & 0xff], REG_SPIDATA & 0xfff, 0);

 							break;