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Updating the VBA-M code to revision 1231.

Naram Qashat authored on 2014/09/08 12:20:28
Showing 1 changed files
src/in_gsf/vbam/gba/GBAcpu.h
History View file @ bee3026
... ... 
@@ -1,10 +1,9 @@
1 
-#ifndef GBACPU_H
2 
-#define GBACPU_H
1 
+#pragma once
3 2
4 3 
 #include "GBAinline.h"
5 4
6 
-extern int armExecute();
7 
-extern int thumbExecute();
5 
+int armExecute();
6 
+int thumbExecute();
8 7
9 8 
 #ifdef __GNUC__
10 9 
 # ifndef __APPLE__
... ... 
@@ -12,8 +11,8 @@ extern int thumbExecute();
12 11 
 # else
13 12 
 #  define INSN_REGPARM /*nothing*/
14 13 
 # endif
15 
-# define LIKELY(x) __builtin_expect(!!(x),1)
16 
-# define UNLIKELY(x) __builtin_expect(!!(x),0)
14 
+# define LIKELY(x) __builtin_expect(!!(x), 1)
15 
+# define UNLIKELY(x) __builtin_expect(!!(x), 0)
17 16 
 #else
18 17 
 # define INSN_REGPARM /*nothing*/
19 18 
 # define LIKELY(x) (x)
... ... 
@@ -49,11 +48,12 @@ extern uint8_t memoryWait32[16];
49 48 
 extern uint8_t memoryWaitSeq[16];
50 49 
 extern uint8_t memoryWaitSeq32[16];
51 50 
 extern uint8_t cpuBitsSet[256];
52 
-extern void CPUSwitchMode(int mode, bool saveState, bool breakLoop = true);
53 
-extern void CPUUpdateCPSR();
54 
-extern void CPUUpdateFlags(bool breakLoop = true);
55 
-extern void CPUUndefinedException();
56 
-extern void CPUSoftwareInterrupt(int comment);
51 
+
52 
+void CPUSwitchMode(int mode, bool saveState, bool breakLoop = true);
53 
+void CPUUpdateCPSR();
54 
+void CPUUpdateFlags(bool breakLoop = true);
55 
+void CPUUndefinedException();
56 
+void CPUSoftwareInterrupt(int comment);
57 57
58 58 
 // Waitstates when accessing data
59 59 
 inline int dataTicksAccess16(uint32_t address) // DATA 8/16bits NON SEQ
... ... 
@@ -98,27 +98,6 @@ inline int dataTicksAccess32(uint32_t address) // DATA 32bits NON SEQ
98 98 
 	return value;
99 99 
 }
100 100
101 
-inline int dataTicksAccessSeq16(uint32_t address) // DATA 8/16bits SEQ
102 
-{
103 
-	int addr = (address >> 24) & 15;
104 
-	int value = memoryWaitSeq[addr];
105 
-
106 
-	if (addr >= 0x08 || addr < 0x02)
107 
-	{
108 
-		busPrefetchCount = 0;
109 
-		busPrefetch = false;
110 
-	}
111 
-	else if (busPrefetch)
112 
-	{
113 
-		int waitState = value;
114 
-		if (!waitState)
115 
-			waitState = 1;
116 
-		busPrefetchCount = ((busPrefetchCount + 1) << waitState) - 1;
117 
-	}
118 
-
119 
-	return value;
120 
-}
121 
-
122 101 
 inline int dataTicksAccessSeq32(uint32_t address) // DATA 32bits SEQ
123 102 
 {
124 103 
 	int addr = (address >> 24) & 15;
... ... 
@@ -252,5 +231,3 @@ inline int codeTicksAccessSeq32(uint32_t address) // ARM SEQ
252 231 
 	else
253 232 
 		return memoryWaitSeq32[addr];
254 233 
 }
255 
-
256 
-#endif // GBACPU_H
Browse code

[GSF] Some more code cleanup, also removed a few files that were unneeded.

Naram Qashat authored on 2013/05/16 01:25:34
Showing 1 changed files
src/in_gsf/vbam/gba/GBAcpu.h
History View file @ 91cc309
... ... 
@@ -20,7 +20,7 @@ extern int thumbExecute();
20 20 
 # define UNLIKELY(x) (x)
21 21 
 #endif
22 22
23 
-inline void UPDATE_REG(uint32_t address, uint16_t value) { WRITE16LE(&ioMem[address],value); }
23 
+inline void UPDATE_REG(uint32_t address, uint16_t value) { WRITE16LE(&ioMem[address], value); }
24 24
25 25 
 extern uint32_t cpuPrefetch[2];
26 26
Browse code

[GSF] Massive code cleanup.

(As an aside, blargg's code style makes me go blarg myself.)

Naram Qashat authored on 2013/05/14 01:07:18
Showing 1 changed files
src/in_gsf/vbam/gba/GBAcpu.h
History View file @ 260239f
... ... 
@@ -1,15 +1,17 @@
1 1 
 #ifndef GBACPU_H
2 2 
 #define GBACPU_H
3 3
4 
+#include "GBAinline.h"
5 
+
4 6 
 extern int armExecute();
5 7 
 extern int thumbExecute();
6 8
7 9 
 #ifdef __GNUC__
8 
-#ifndef __APPLE__
9 
-# define INSN_REGPARM __attribute__((regparm(1)))
10 
-#else
11 
-# define INSN_REGPARM /*nothing*/
12 
-#endif
10 
+# ifndef __APPLE__
11 
+#  define INSN_REGPARM __attribute__((regparm(1)))
12 
+# else
13 
+#  define INSN_REGPARM /*nothing*/
14 
+# endif
13 15 
 # define LIKELY(x) __builtin_expect(!!(x),1)
14 16 
 # define UNLIKELY(x) __builtin_expect(!!(x),0)
15 17 
 #else
... ... 
@@ -18,270 +20,237 @@ extern int thumbExecute();
18 20 
 # define UNLIKELY(x) (x)
19 21 
 #endif
20 22
21 
-#define UPDATE_REG(address, value)\
22 
-  {\
23 
-    WRITE16LE(((uint16_t *)&ioMem[address]),value);\
24 
-  }\
23 
+inline void UPDATE_REG(uint32_t address, uint16_t value) { WRITE16LE(&ioMem[address],value); }
25 24
26 
-#define ARM_PREFETCH \
27 
-  {\
28 
-    cpuPrefetch[0] = CPUReadMemoryQuick(armNextPC);\
29 
-    cpuPrefetch[1] = CPUReadMemoryQuick(armNextPC+4);\
30 
-  }
25 
+extern uint32_t cpuPrefetch[2];
31 26
32 
-#define THUMB_PREFETCH \
33 
-  {\
34 
-    cpuPrefetch[0] = CPUReadHalfWordQuick(armNextPC);\
35 
-    cpuPrefetch[1] = CPUReadHalfWordQuick(armNextPC+2);\
36 
-  }
27 
+inline void ARM_PREFETCH()
28 
+{
29 
+	cpuPrefetch[0] = CPUReadMemoryQuick(armNextPC);
30 
+	cpuPrefetch[1] = CPUReadMemoryQuick(armNextPC + 4);
31 
+}
37 32
38 
-#define ARM_PREFETCH_NEXT \
39 
-  cpuPrefetch[1] = CPUReadMemoryQuick(armNextPC+4);
33 
+inline void THUMB_PREFETCH()
34 
+{
35 
+	cpuPrefetch[0] = CPUReadHalfWordQuick(armNextPC);
36 
+	cpuPrefetch[1] = CPUReadHalfWordQuick(armNextPC + 2);
37 
+}
40 38
41 
-#define THUMB_PREFETCH_NEXT\
42 
-  cpuPrefetch[1] = CPUReadHalfWordQuick(armNextPC+2);
39 
+inline void ARM_PREFETCH_NEXT() { cpuPrefetch[1] = CPUReadMemoryQuick(armNextPC + 4); }
43 40
41 
+inline void THUMB_PREFETCH_NEXT() { cpuPrefetch[1] = CPUReadHalfWordQuick(armNextPC + 2); }
44 42
45 43 
 extern int SWITicks;
46 
-extern uint32_t mastercode;
47 44 
 extern bool busPrefetch;
48 45 
 extern bool busPrefetchEnable;
49 46 
 extern uint32_t busPrefetchCount;
50 
-extern int cpuNextEvent;
51 
-extern bool holdState;
52 
-extern uint32_t cpuPrefetch[2];
53 
-extern int cpuTotalTicks;
54 47 
 extern uint8_t memoryWait[16];
55 48 
 extern uint8_t memoryWait32[16];
56 49 
 extern uint8_t memoryWaitSeq[16];
57 50 
 extern uint8_t memoryWaitSeq32[16];
58 51 
 extern uint8_t cpuBitsSet[256];
59 
-extern uint8_t cpuLowestBitSet[256];
60 
-extern void CPUSwitchMode(int mode, bool saveState, bool breakLoop);
61 
-extern void CPUSwitchMode(int mode, bool saveState);
52 
+extern void CPUSwitchMode(int mode, bool saveState, bool breakLoop = true);
62 53 
 extern void CPUUpdateCPSR();
63 
-extern void CPUUpdateFlags(bool breakLoop);
64 
-extern void CPUUpdateFlags();
54 
+extern void CPUUpdateFlags(bool breakLoop = true);
65 55 
 extern void CPUUndefinedException();
66 
-extern void CPUSoftwareInterrupt();
67 56 
 extern void CPUSoftwareInterrupt(int comment);
68 57
69 
-
70 58 
 // Waitstates when accessing data
71 59 
 inline int dataTicksAccess16(uint32_t address) // DATA 8/16bits NON SEQ
72 60 
 {
73 
-  int addr = (address>>24)&15;
74 
-  int value =  memoryWait[addr];
75 
-
76 
-  if ((addr>=0x08) || (addr < 0x02))
77 
-  {
78 
-    busPrefetchCount=0;
79 
-    busPrefetch=false;
80 
-  }
81 
-  else if (busPrefetch)
82 
-  {
83 
-    int waitState = value;
84 
-    if (!waitState)
85 
-      waitState = 1;
86 
-    busPrefetchCount = ((busPrefetchCount+1)<<waitState) - 1;
87 
-  }
88 
-
89 
-  return value;
61 
+	int addr = (address >> 24) & 15;
62 
+	int value = memoryWait[addr];
63 
+
64 
+	if (addr >= 0x08 || addr < 0x02)
65 
+	{
66 
+		busPrefetchCount = 0;
67 
+		busPrefetch = false;
68 
+	}
69 
+	else if (busPrefetch)
70 
+	{
71 
+		int waitState = value;
72 
+		if (!waitState)
73 
+			waitState = 1;
74 
+		busPrefetchCount = ((busPrefetchCount + 1) << waitState) - 1;
75 
+	}
76 
+
77 
+	return value;
90 78 
 }
91 79
92 80 
 inline int dataTicksAccess32(uint32_t address) // DATA 32bits NON SEQ
93 81 
 {
94 
-  int addr = (address>>24)&15;
95 
-  int value = memoryWait32[addr];
96 
-
97 
-  if ((addr>=0x08) || (addr < 0x02))
98 
-  {
99 
-    busPrefetchCount=0;
100 
-    busPrefetch=false;
101 
-  }
102 
-  else if (busPrefetch)
103 
-  {
104 
-    int waitState = value;
105 
-    if (!waitState)
106 
-      waitState = 1;
107 
-    busPrefetchCount = ((busPrefetchCount+1)<<waitState) - 1;
108 
-  }
109 
-
110 
-  return value;
82 
+	int addr = (address >> 24) & 15;
83 
+	int value = memoryWait32[addr];
84 
+
85 
+	if (addr >= 0x08 || addr < 0x02)
86 
+	{
87 
+		busPrefetchCount = 0;
88 
+		busPrefetch = false;
89 
+	}
90 
+	else if (busPrefetch)
91 
+	{
92 
+		int waitState = value;
93 
+		if (!waitState)
94 
+			waitState = 1;
95 
+		busPrefetchCount = ((busPrefetchCount + 1) << waitState) - 1;
96 
+	}
97 
+
98 
+	return value;
111 99 
 }
112 100
113 
-inline int dataTicksAccessSeq16(uint32_t address)// DATA 8/16bits SEQ
101 
+inline int dataTicksAccessSeq16(uint32_t address) // DATA 8/16bits SEQ
114 102 
 {
115 
-  int addr = (address>>24)&15;
116 
-  int value = memoryWaitSeq[addr];
117 
-
118 
-  if ((addr>=0x08) || (addr < 0x02))
119 
-  {
120 
-    busPrefetchCount=0;
121 
-    busPrefetch=false;
122 
-  }
123 
-  else if (busPrefetch)
124 
-  {
125 
-    int waitState = value;
126 
-    if (!waitState)
127 
-      waitState = 1;
128 
-    busPrefetchCount = ((busPrefetchCount+1)<<waitState) - 1;
129 
-  }
130 
-
131 
-  return value;
103 
+	int addr = (address >> 24) & 15;
104 
+	int value = memoryWaitSeq[addr];
105 
+
106 
+	if (addr >= 0x08 || addr < 0x02)
107 
+	{
108 
+		busPrefetchCount = 0;
109 
+		busPrefetch = false;
110 
+	}
111 
+	else if (busPrefetch)
112 
+	{
113 
+		int waitState = value;
114 
+		if (!waitState)
115 
+			waitState = 1;
116 
+		busPrefetchCount = ((busPrefetchCount + 1) << waitState) - 1;
117 
+	}
118 
+
119 
+	return value;
132 120 
 }
133 121
134 
-inline int dataTicksAccessSeq32(uint32_t address)// DATA 32bits SEQ
122 
+inline int dataTicksAccessSeq32(uint32_t address) // DATA 32bits SEQ
135 123 
 {
136 
-  int addr = (address>>24)&15;
137 
-  int value =  memoryWaitSeq32[addr];
138 
-
139 
-  if ((addr>=0x08) || (addr < 0x02))
140 
-  {
141 
-    busPrefetchCount=0;
142 
-    busPrefetch=false;
143 
-  }
144 
-  else if (busPrefetch)
145 
-  {
146 
-    int waitState = value;
147 
-    if (!waitState)
148 
-      waitState = 1;
149 
-    busPrefetchCount = ((busPrefetchCount+1)<<waitState) - 1;
150 
-  }
151 
-
152 
-  return value;
124 
+	int addr = (address >> 24) & 15;
125 
+	int value = memoryWaitSeq32[addr];
126 
+
127 
+	if (addr >= 0x08 || addr < 0x02)
128 
+	{
129 
+		busPrefetchCount = 0;
130 
+		busPrefetch = false;
131 
+	}
132 
+	else if (busPrefetch)
133 
+	{
134 
+		int waitState = value;
135 
+		if (!waitState)
136 
+			waitState = 1;
137 
+		busPrefetchCount = ((busPrefetchCount + 1) << waitState) - 1;
138 
+	}
139 
+
140 
+	return value;
153 141 
 }
154 142
155 
-
156 143 
 // Waitstates when executing opcode
157 144 
 inline int codeTicksAccess16(uint32_t address) // THUMB NON SEQ
158 145 
 {
159 
-  int addr = (address>>24)&15;
160 
-
161 
-  if ((addr>=0x08) && (addr<=0x0D))
162 
-  {
163 
-    if (busPrefetchCount&0x1)
164 
-    {
165 
-      if (busPrefetchCount&0x2)
166 
-      {
167 
-        busPrefetchCount = ((busPrefetchCount&0xFF)>>2) | (busPrefetchCount&0xFFFFFF00);
168 
-        return 0;
169 
-      }
170 
-      busPrefetchCount = ((busPrefetchCount&0xFF)>>1) | (busPrefetchCount&0xFFFFFF00);
171 
-      return memoryWaitSeq[addr]-1;
172 
-    }
173 
-    else
174 
-    {
175 
-      busPrefetchCount=0;
176 
-      return memoryWait[addr];
177 
-    }
178 
-  }
179 
-  else
180 
-  {
181 
-    busPrefetchCount = 0;
182 
-    return memoryWait[addr];
183 
-  }
146 
+	int addr = (address >> 24) & 15;
147 
+
148 
+	if (addr >= 0x08 && addr <= 0x0D)
149 
+	{
150 
+		if (busPrefetchCount & 0x1)
151 
+		{
152 
+			if (busPrefetchCount & 0x2)
153 
+			{
154 
+				busPrefetchCount = ((busPrefetchCount & 0xFF) >> 2) | (busPrefetchCount & 0xFFFFFF00);
155 
+				return 0;
156 
+			}
157 
+			busPrefetchCount = ((busPrefetchCount & 0xFF) >> 1) | (busPrefetchCount & 0xFFFFFF00);
158 
+			return memoryWaitSeq[addr] - 1;
159 
+		}
160 
+		else
161 
+		{
162 
+			busPrefetchCount = 0;
163 
+			return memoryWait[addr];
164 
+		}
165 
+	}
166 
+	else
167 
+	{
168 
+		busPrefetchCount = 0;
169 
+		return memoryWait[addr];
170 
+	}
184 171 
 }
185 172
186 173 
 inline int codeTicksAccess32(uint32_t address) // ARM NON SEQ
187 174 
 {
188 
-  int addr = (address>>24)&15;
189 
-
190 
-  if ((addr>=0x08) && (addr<=0x0D))
191 
-  {
192 
-    if (busPrefetchCount&0x1)
193 
-    {
194 
-      if (busPrefetchCount&0x2)
195 
-      {
196 
-        busPrefetchCount = ((busPrefetchCount&0xFF)>>2) | (busPrefetchCount&0xFFFFFF00);
197 
-        return 0;
198 
-      }
199 
-      busPrefetchCount = ((busPrefetchCount&0xFF)>>1) | (busPrefetchCount&0xFFFFFF00);
200 
-      return memoryWaitSeq[addr] - 1;
201 
-    }
202 
-    else
203 
-    {
204 
-      busPrefetchCount = 0;
205 
-      return memoryWait32[addr];
206 
-    }
207 
-  }
208 
-  else
209 
-  {
210 
-    busPrefetchCount = 0;
211 
-    return memoryWait32[addr];
212 
-  }
175 
+	int addr = (address >> 24) & 15;
176 
+
177 
+	if (addr >= 0x08 && addr <= 0x0D)
178 
+	{
179 
+		if (busPrefetchCount & 0x1)
180 
+		{
181 
+			if (busPrefetchCount & 0x2)
182 
+			{
183 
+				busPrefetchCount = ((busPrefetchCount & 0xFF) >> 2) | (busPrefetchCount & 0xFFFFFF00);
184 
+				return 0;
185 
+			}
186 
+			busPrefetchCount = ((busPrefetchCount & 0xFF) >> 1) | (busPrefetchCount & 0xFFFFFF00);
187 
+			return memoryWaitSeq[addr] - 1;
188 
+		}
189 
+		else
190 
+		{
191 
+			busPrefetchCount = 0;
192 
+			return memoryWait32[addr];
193 
+		}
194 
+	}
195 
+	else
196 
+	{
197 
+		busPrefetchCount = 0;
198 
+		return memoryWait32[addr];
199 
+	}
213 200 
 }
214 201
215 202 
 inline int codeTicksAccessSeq16(uint32_t address) // THUMB SEQ
216 203 
 {
217 
-  int addr = (address>>24)&15;
218 
-
219 
-  if ((addr>=0x08) && (addr<=0x0D))
220 
-  {
221 
-    if (busPrefetchCount&0x1)
222 
-    {
223 
-      busPrefetchCount = ((busPrefetchCount&0xFF)>>1) | (busPrefetchCount&0xFFFFFF00);
224 
-      return 0;
225 
-    }
226 
-    else
227 
-    if (busPrefetchCount>0xFF)
228 
-    {
229 
-      busPrefetchCount=0;
230 
-      return memoryWait[addr];
231 
-    }
232 
-    else
233 
-      return memoryWaitSeq[addr];
234 
-  }
235 
-  else
236 
-  {
237 
-    busPrefetchCount = 0;
238 
-    return memoryWaitSeq[addr];
239 
-  }
204 
+	int addr = (address >> 24) & 15;
205 
+
206 
+	if (addr >= 0x08 && addr <= 0x0D)
207 
+	{
208 
+		if (busPrefetchCount & 0x1)
209 
+		{
210 
+			busPrefetchCount = ((busPrefetchCount & 0xFF) >> 1) | (busPrefetchCount & 0xFFFFFF00);
211 
+			return 0;
212 
+		}
213 
+		else if (busPrefetchCount > 0xFF)
214 
+		{
215 
+			busPrefetchCount = 0;
216 
+			return memoryWait[addr];
217 
+		}
218 
+		else
219 
+			return memoryWaitSeq[addr];
220 
+	}
221 
+	else
222 
+	{
223 
+		busPrefetchCount = 0;
224 
+		return memoryWaitSeq[addr];
225 
+	}
240 226 
 }
241 227
242 228 
 inline int codeTicksAccessSeq32(uint32_t address) // ARM SEQ
243 229 
 {
244 
-  int addr = (address>>24)&15;
245 
-
246 
-  if ((addr>=0x08) && (addr<=0x0D))
247 
-  {
248 
-    if (busPrefetchCount&0x1)
249 
-    {
250 
-      if (busPrefetchCount&0x2)
251 
-      {
252 
-        busPrefetchCount = ((busPrefetchCount&0xFF)>>2) | (busPrefetchCount&0xFFFFFF00);
253 
-        return 0;
254 
-      }
255 
-      busPrefetchCount = ((busPrefetchCount&0xFF)>>1) | (busPrefetchCount&0xFFFFFF00);
256 
-      return memoryWaitSeq[addr];
257 
-    }
258 
-    else
259 
-    if (busPrefetchCount>0xFF)
260 
-    {
261 
-      busPrefetchCount=0;
262 
-      return memoryWait32[addr];
263 
-    }
264 
-    else
265 
-      return memoryWaitSeq32[addr];
266 
-  }
267 
-  else
268 
-  {
269 
-    return memoryWaitSeq32[addr];
270 
-  }
230 
+	int addr = (address >> 24) & 15;
231 
+
232 
+	if (addr >= 0x08 && addr <= 0x0D)
233 
+	{
234 
+		if (busPrefetchCount & 0x1)
235 
+		{
236 
+			if (busPrefetchCount & 0x2)
237 
+			{
238 
+				busPrefetchCount = ((busPrefetchCount & 0xFF) >> 2) | (busPrefetchCount & 0xFFFFFF00);
239 
+				return 0;
240 
+			}
241 
+			busPrefetchCount = ((busPrefetchCount & 0xFF) >> 1) | (busPrefetchCount & 0xFFFFFF00);
242 
+			return memoryWaitSeq[addr];
243 
+		}
244 
+		else if (busPrefetchCount > 0xFF)
245 
+		{
246 
+			busPrefetchCount = 0;
247 
+			return memoryWait32[addr];
248 
+		}
249 
+		else
250 
+			return memoryWaitSeq32[addr];
251 
+	}
252 
+	else
253 
+		return memoryWaitSeq32[addr];
271 254 
 }
272 255
273 
-
274 
-// Emulates the Cheat System (m) code
275 
-/*inline void cpuMasterCodeCheck()
276 
-{
277 
-  if((mastercode) && (mastercode == armNextPC))
278 
-  {
279 
-    u32 joy = 0;
280 
-    if(systemReadJoypads())
281 
-      joy = systemReadJoypad(-1);
282 
-    u32 ext = (joy >> 10);
283 
-    cpuTotalTicks += cheatsCheckKeys(P1^0x3FF, ext);
284 
-  }
285 
-}*/
286 
-
287 256 
 #endif // GBACPU_H
Browse code

[GSF] Cleanup, a tiny bit of making sure it was like viogsf, also used the standard integer types and not VBA-M's typedefs.

Naram Qashat authored on 2013/05/10 17:45:36
Showing 1 changed files
src/in_gsf/vbam/gba/GBAcpu.h
History View file @ 58ead5d
... ... 
@@ -20,7 +20,7 @@ extern int thumbExecute();
20 20
21 21 
 #define UPDATE_REG(address, value)\
22 22 
   {\
23 
-    WRITE16LE(((u16 *)&ioMem[address]),value);\
23 
+    WRITE16LE(((uint16_t *)&ioMem[address]),value);\
24 24 
   }\
25 25
26 26 
 #define ARM_PREFETCH \
... ... 
@@ -43,20 +43,20 @@ extern int thumbExecute();
43 43
44 44
45 45 
 extern int SWITicks;
46 
-extern u32 mastercode;
46 
+extern uint32_t mastercode;
47 47 
 extern bool busPrefetch;
48 48 
 extern bool busPrefetchEnable;
49 
-extern u32 busPrefetchCount;
49 
+extern uint32_t busPrefetchCount;
50 50 
 extern int cpuNextEvent;
51 51 
 extern bool holdState;
52 
-extern u32 cpuPrefetch[2];
52 
+extern uint32_t cpuPrefetch[2];
53 53 
 extern int cpuTotalTicks;
54 
-extern u8 memoryWait[16];
55 
-extern u8 memoryWait32[16];
56 
-extern u8 memoryWaitSeq[16];
57 
-extern u8 memoryWaitSeq32[16];
58 
-extern u8 cpuBitsSet[256];
59 
-extern u8 cpuLowestBitSet[256];
54 
+extern uint8_t memoryWait[16];
55 
+extern uint8_t memoryWait32[16];
56 
+extern uint8_t memoryWaitSeq[16];
57 
+extern uint8_t memoryWaitSeq32[16];
58 
+extern uint8_t cpuBitsSet[256];
59 
+extern uint8_t cpuLowestBitSet[256];
60 60 
 extern void CPUSwitchMode(int mode, bool saveState, bool breakLoop);
61 61 
 extern void CPUSwitchMode(int mode, bool saveState);
62 62 
 extern void CPUUpdateCPSR();
... ... 
@@ -68,7 +68,7 @@ extern void CPUSoftwareInterrupt(int comment);
68 68
69 69
70 70 
 // Waitstates when accessing data
71 
-inline int dataTicksAccess16(u32 address) // DATA 8/16bits NON SEQ
71 
+inline int dataTicksAccess16(uint32_t address) // DATA 8/16bits NON SEQ
72 72 
 {
73 73 
   int addr = (address>>24)&15;
74 74 
   int value =  memoryWait[addr];
... ... 
@@ -89,7 +89,7 @@ inline int dataTicksAccess16(u32 address) // DATA 8/16bits NON SEQ
89 89 
   return value;
90 90 
 }
91 91
92 
-inline int dataTicksAccess32(u32 address) // DATA 32bits NON SEQ
92 
+inline int dataTicksAccess32(uint32_t address) // DATA 32bits NON SEQ
93 93 
 {
94 94 
   int addr = (address>>24)&15;
95 95 
   int value = memoryWait32[addr];
... ... 
@@ -110,7 +110,7 @@ inline int dataTicksAccess32(u32 address) // DATA 32bits NON SEQ
110 110 
   return value;
111 111 
 }
112 112
113 
-inline int dataTicksAccessSeq16(u32 address)// DATA 8/16bits SEQ
113 
+inline int dataTicksAccessSeq16(uint32_t address)// DATA 8/16bits SEQ
114 114 
 {
115 115 
   int addr = (address>>24)&15;
116 116 
   int value = memoryWaitSeq[addr];
... ... 
@@ -131,7 +131,7 @@ inline int dataTicksAccessSeq16(u32 address)// DATA 8/16bits SEQ
131 131 
   return value;
132 132 
 }
133 133
134 
-inline int dataTicksAccessSeq32(u32 address)// DATA 32bits SEQ
134 
+inline int dataTicksAccessSeq32(uint32_t address)// DATA 32bits SEQ
135 135 
 {
136 136 
   int addr = (address>>24)&15;
137 137 
   int value =  memoryWaitSeq32[addr];
... ... 
@@ -154,7 +154,7 @@ inline int dataTicksAccessSeq32(u32 address)// DATA 32bits SEQ
154 154
155 155
156 156 
 // Waitstates when executing opcode
157 
-inline int codeTicksAccess16(u32 address) // THUMB NON SEQ
157 
+inline int codeTicksAccess16(uint32_t address) // THUMB NON SEQ
158 158 
 {
159 159 
   int addr = (address>>24)&15;
160 160
... ... 
@@ -183,7 +183,7 @@ inline int codeTicksAccess16(u32 address) // THUMB NON SEQ
183 183 
   }
184 184 
 }
185 185
186 
-inline int codeTicksAccess32(u32 address) // ARM NON SEQ
186 
+inline int codeTicksAccess32(uint32_t address) // ARM NON SEQ
187 187 
 {
188 188 
   int addr = (address>>24)&15;
189 189
... ... 
@@ -212,7 +212,7 @@ inline int codeTicksAccess32(u32 address) // ARM NON SEQ
212 212 
   }
213 213 
 }
214 214
215 
-inline int codeTicksAccessSeq16(u32 address) // THUMB SEQ
215 
+inline int codeTicksAccessSeq16(uint32_t address) // THUMB SEQ
216 216 
 {
217 217 
   int addr = (address>>24)&15;
218 218
... ... 
@@ -239,7 +239,7 @@ inline int codeTicksAccessSeq16(u32 address) // THUMB SEQ
239 239 
   }
240 240 
 }
241 241
242 
-inline int codeTicksAccessSeq32(u32 address) // ARM SEQ
242 
+inline int codeTicksAccessSeq32(uint32_t address) // ARM SEQ
243 243 
 {
244 244 
   int addr = (address>>24)&15;
245 245
Browse code

Import actual code.

Naram Qashat authored on 2013/03/26 02:41:19
Showing 1 changed files
src/in_gsf/vbam/gba/GBAcpu.h
History View file @ bc076aa
1 1 
new file mode 100644
... ... 
@@ -0,0 +1,287 @@
1 
+#ifndef GBACPU_H
2 
+#define GBACPU_H
3 
+
4 
+extern int armExecute();
5 
+extern int thumbExecute();
6 
+
7 
+#ifdef __GNUC__
8 
+#ifndef __APPLE__
9 
+# define INSN_REGPARM __attribute__((regparm(1)))
10 
+#else
11 
+# define INSN_REGPARM /*nothing*/
12 
+#endif
13 
+# define LIKELY(x) __builtin_expect(!!(x),1)
14 
+# define UNLIKELY(x) __builtin_expect(!!(x),0)
15 
+#else
16 
+# define INSN_REGPARM /*nothing*/
17 
+# define LIKELY(x) (x)
18 
+# define UNLIKELY(x) (x)
19 
+#endif
20 
+
21 
+#define UPDATE_REG(address, value)\
22 
+  {\
23 
+    WRITE16LE(((u16 *)&ioMem[address]),value);\
24 
+  }\
25 
+
26 
+#define ARM_PREFETCH \
27 
+  {\
28 
+    cpuPrefetch[0] = CPUReadMemoryQuick(armNextPC);\
29 
+    cpuPrefetch[1] = CPUReadMemoryQuick(armNextPC+4);\
30 
+  }
31 
+
32 
+#define THUMB_PREFETCH \
33 
+  {\
34 
+    cpuPrefetch[0] = CPUReadHalfWordQuick(armNextPC);\
35 
+    cpuPrefetch[1] = CPUReadHalfWordQuick(armNextPC+2);\
36 
+  }
37 
+
38 
+#define ARM_PREFETCH_NEXT \
39 
+  cpuPrefetch[1] = CPUReadMemoryQuick(armNextPC+4);
40 
+
41 
+#define THUMB_PREFETCH_NEXT\
42 
+  cpuPrefetch[1] = CPUReadHalfWordQuick(armNextPC+2);
43 
+
44 
+
45 
+extern int SWITicks;
46 
+extern u32 mastercode;
47 
+extern bool busPrefetch;
48 
+extern bool busPrefetchEnable;
49 
+extern u32 busPrefetchCount;
50 
+extern int cpuNextEvent;
51 
+extern bool holdState;
52 
+extern u32 cpuPrefetch[2];
53 
+extern int cpuTotalTicks;
54 
+extern u8 memoryWait[16];
55 
+extern u8 memoryWait32[16];
56 
+extern u8 memoryWaitSeq[16];
57 
+extern u8 memoryWaitSeq32[16];
58 
+extern u8 cpuBitsSet[256];
59 
+extern u8 cpuLowestBitSet[256];
60 
+extern void CPUSwitchMode(int mode, bool saveState, bool breakLoop);
61 
+extern void CPUSwitchMode(int mode, bool saveState);
62 
+extern void CPUUpdateCPSR();
63 
+extern void CPUUpdateFlags(bool breakLoop);
64 
+extern void CPUUpdateFlags();
65 
+extern void CPUUndefinedException();
66 
+extern void CPUSoftwareInterrupt();
67 
+extern void CPUSoftwareInterrupt(int comment);
68 
+
69 
+
70 
+// Waitstates when accessing data
71 
+inline int dataTicksAccess16(u32 address) // DATA 8/16bits NON SEQ
72 
+{
73 
+  int addr = (address>>24)&15;
74 
+  int value =  memoryWait[addr];
75 
+
76 
+  if ((addr>=0x08) || (addr < 0x02))
77 
+  {
78 
+    busPrefetchCount=0;
79 
+    busPrefetch=false;
80 
+  }
81 
+  else if (busPrefetch)
82 
+  {
83 
+    int waitState = value;
84 
+    if (!waitState)
85 
+      waitState = 1;
86 
+    busPrefetchCount = ((busPrefetchCount+1)<<waitState) - 1;
87 
+  }
88 
+
89 
+  return value;
90 
+}
91 
+
92 
+inline int dataTicksAccess32(u32 address) // DATA 32bits NON SEQ
93 
+{
94 
+  int addr = (address>>24)&15;
95 
+  int value = memoryWait32[addr];
96 
+
97 
+  if ((addr>=0x08) || (addr < 0x02))
98 
+  {
99 
+    busPrefetchCount=0;
100 
+    busPrefetch=false;
101 
+  }
102 
+  else if (busPrefetch)
103 
+  {
104 
+    int waitState = value;
105 
+    if (!waitState)
106 
+      waitState = 1;
107 
+    busPrefetchCount = ((busPrefetchCount+1)<<waitState) - 1;
108 
+  }
109 
+
110 
+  return value;
111 
+}
112 
+
113 
+inline int dataTicksAccessSeq16(u32 address)// DATA 8/16bits SEQ
114 
+{
115 
+  int addr = (address>>24)&15;
116 
+  int value = memoryWaitSeq[addr];
117 
+
118 
+  if ((addr>=0x08) || (addr < 0x02))
119 
+  {
120 
+    busPrefetchCount=0;
121 
+    busPrefetch=false;
122 
+  }
123 
+  else if (busPrefetch)
124 
+  {
125 
+    int waitState = value;
126 
+    if (!waitState)
127 
+      waitState = 1;
128 
+    busPrefetchCount = ((busPrefetchCount+1)<<waitState) - 1;
129 
+  }
130 
+
131 
+  return value;
132 
+}
133 
+
134 
+inline int dataTicksAccessSeq32(u32 address)// DATA 32bits SEQ
135 
+{
136 
+  int addr = (address>>24)&15;
137 
+  int value =  memoryWaitSeq32[addr];
138 
+
139 
+  if ((addr>=0x08) || (addr < 0x02))
140 
+  {
141 
+    busPrefetchCount=0;
142 
+    busPrefetch=false;
143 
+  }
144 
+  else if (busPrefetch)
145 
+  {
146 
+    int waitState = value;
147 
+    if (!waitState)
148 
+      waitState = 1;
149 
+    busPrefetchCount = ((busPrefetchCount+1)<<waitState) - 1;
150 
+  }
151 
+
152 
+  return value;
153 
+}
154 
+
155 
+
156 
+// Waitstates when executing opcode
157 
+inline int codeTicksAccess16(u32 address) // THUMB NON SEQ
158 
+{
159 
+  int addr = (address>>24)&15;
160 
+
161 
+  if ((addr>=0x08) && (addr<=0x0D))
162 
+  {
163 
+    if (busPrefetchCount&0x1)
164 
+    {
165 
+      if (busPrefetchCount&0x2)
166 
+      {
167 
+        busPrefetchCount = ((busPrefetchCount&0xFF)>>2) | (busPrefetchCount&0xFFFFFF00);
168 
+        return 0;
169 
+      }
170 
+      busPrefetchCount = ((busPrefetchCount&0xFF)>>1) | (busPrefetchCount&0xFFFFFF00);
171 
+      return memoryWaitSeq[addr]-1;
172 
+    }
173 
+    else
174 
+    {
175 
+      busPrefetchCount=0;
176 
+      return memoryWait[addr];
177 
+    }
178 
+  }
179 
+  else
180 
+  {
181 
+    busPrefetchCount = 0;
182 
+    return memoryWait[addr];
183 
+  }
184 
+}
185 
+
186 
+inline int codeTicksAccess32(u32 address) // ARM NON SEQ
187 
+{
188 
+  int addr = (address>>24)&15;
189 
+
190 
+  if ((addr>=0x08) && (addr<=0x0D))
191 
+  {
192 
+    if (busPrefetchCount&0x1)
193 
+    {
194 
+      if (busPrefetchCount&0x2)
195 
+      {
196 
+        busPrefetchCount = ((busPrefetchCount&0xFF)>>2) | (busPrefetchCount&0xFFFFFF00);
197 
+        return 0;
198 
+      }
199 
+      busPrefetchCount = ((busPrefetchCount&0xFF)>>1) | (busPrefetchCount&0xFFFFFF00);
200 
+      return memoryWaitSeq[addr] - 1;
201 
+    }
202 
+    else
203 
+    {
204 
+      busPrefetchCount = 0;
205 
+      return memoryWait32[addr];
206 
+    }
207 
+  }
208 
+  else
209 
+  {
210 
+    busPrefetchCount = 0;
211 
+    return memoryWait32[addr];
212 
+  }
213 
+}
214 
+
215 
+inline int codeTicksAccessSeq16(u32 address) // THUMB SEQ
216 
+{
217 
+  int addr = (address>>24)&15;
218 
+
219 
+  if ((addr>=0x08) && (addr<=0x0D))
220 
+  {
221 
+    if (busPrefetchCount&0x1)
222 
+    {
223 
+      busPrefetchCount = ((busPrefetchCount&0xFF)>>1) | (busPrefetchCount&0xFFFFFF00);
224 
+      return 0;
225 
+    }
226 
+    else
227 
+    if (busPrefetchCount>0xFF)
228 
+    {
229 
+      busPrefetchCount=0;
230 
+      return memoryWait[addr];
231 
+    }
232 
+    else
233 
+      return memoryWaitSeq[addr];
234 
+  }
235 
+  else
236 
+  {
237 
+    busPrefetchCount = 0;
238 
+    return memoryWaitSeq[addr];
239 
+  }
240 
+}
241 
+
242 
+inline int codeTicksAccessSeq32(u32 address) // ARM SEQ
243 
+{
244 
+  int addr = (address>>24)&15;
245 
+
246 
+  if ((addr>=0x08) && (addr<=0x0D))
247 
+  {
248 
+    if (busPrefetchCount&0x1)
249 
+    {
250 
+      if (busPrefetchCount&0x2)
251 
+      {
252 
+        busPrefetchCount = ((busPrefetchCount&0xFF)>>2) | (busPrefetchCount&0xFFFFFF00);
253 
+        return 0;
254 
+      }
255 
+      busPrefetchCount = ((busPrefetchCount&0xFF)>>1) | (busPrefetchCount&0xFFFFFF00);
256 
+      return memoryWaitSeq[addr];
257 
+    }
258 
+    else
259 
+    if (busPrefetchCount>0xFF)
260 
+    {
261 
+      busPrefetchCount=0;
262 
+      return memoryWait32[addr];
263 
+    }
264 
+    else
265 
+      return memoryWaitSeq32[addr];
266 
+  }
267 
+  else
268 
+  {
269 
+    return memoryWaitSeq32[addr];
270 
+  }
271 
+}
272 
+
273 
+
274 
+// Emulates the Cheat System (m) code
275 
+/*inline void cpuMasterCodeCheck()
276 
+{
277 
+  if((mastercode) && (mastercode == armNextPC))
278 
+  {
279 
+    u32 joy = 0;
280 
+    if(systemReadJoypads())
281 
+      joy = systemReadJoypad(-1);
282 
+    u32 ext = (joy >> 10);
283 
+    cpuTotalTicks += cheatsCheckKeys(P1^0x3FF, ext);
284 
+  }
285 
+}*/
286 
+
287 
+#endif // GBACPU_H