CW Cyrix's Git Repository Mirror
Browse code

Use #pragma once instead of include guards.

Naram Qashat authored on 2014/09/08 14:47:36
Showing 1 changed files
src/in_2sf/desmume/registers.h
History View file @ b6add6e
... ... 
@@ -16,8 +16,7 @@
16 16 
 	along with the this software.  If not, see <http://www.gnu.org/licenses/>.
17 17 
 */
18 18
19 
-#ifndef REGISTERS_H
20 
-#define REGISTERS_H
19 
+#pragma once
21 20
22 21 
 #define REG_REGION_MASK                         0x0FFFEF80
23 22 
 #define REG_BASE_DISPx                          0x04000000
... ... 
@@ -427,5 +426,3 @@
427 426 
 #define EXMEMCNT_MASK_SLOT2_ROM_1ST_TIME (3<<2)
428 427 
 #define EXMEMCNT_MASK_SLOT2_ROM_2ND_TIME (1<<4)
429 428 
 #define EXMEMCNT_MASK_SLOT2_CLOCKRATE (3<<5)
430 
-
431 
-#endif
Browse code

Import actual code.

Naram Qashat authored on 2013/03/26 02:41:19
Showing 1 changed files
src/in_2sf/desmume/registers.h
History View file @ bc076aa
1 1 
new file mode 100644
... ... 
@@ -0,0 +1,431 @@
1 
+/*
2 
+	Copyright (C) 2006 Theo Berkau
3 
+	Copyright (C) 2006-2011 DeSmuME team
4 
+
5 
+	This file is free software: you can redistribute it and/or modify
6 
+	it under the terms of the GNU General Public License as published by
7 
+	the Free Software Foundation, either version 2 of the License, or
8 
+	(at your option) any later version.
9 
+
10 
+	This file is distributed in the hope that it will be useful,
11 
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
12 
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 
+	GNU General Public License for more details.
14 
+
15 
+	You should have received a copy of the GNU General Public License
16 
+	along with the this software.  If not, see <http://www.gnu.org/licenses/>.
17 
+*/
18 
+
19 
+#ifndef REGISTERS_H
20 
+#define REGISTERS_H
21 
+
22 
+#define REG_REGION_MASK                         0x0FFFEF80
23 
+#define REG_BASE_DISPx                          0x04000000
24 
+#define REG_BASE_DISPA                          0x04000000
25 
+#define REG_BASE_DISPB                          0x04001000
26 
+#define REG_BASE_DMA                            0x04000080
27 
+#define REG_BASE_SIORTCTIMERS                   0x04000100
28 
+#define REG_BASE_ROMIPC                         0x04000180
29 
+#define REG_BASE_MEMIRQ                         0x04000200
30 
+#define REG_BASE_MATH                           0x04000280
31 
+#define REG_BASE_OTHER                          0x04000300
32 
+#define REG_BASE_RCVPORTS                       0x04100000
33 
+
34 
+// Display Engine A
35 
+#define REG_DISPA_DISPCNT                       0x04000000
36 
+#define REG_DISPA_VCOUNT                        0x04000006
37 
+#define REG_DISPA_BG0CNT                        0x04000008
38 
+#define REG_DISPA_BG1CNT                        0x0400000A
39 
+#define REG_DISPA_BG2CNT                        0x0400000C
40 
+#define REG_DISPA_BG3CNT                        0x0400000E
41 
+#define REG_DISPA_BG0HOFS                       0x04000010
42 
+#define REG_DISPA_BG0VOFS                       0x04000012
43 
+#define REG_DISPA_BG1HOFS                       0x04000014
44 
+#define REG_DISPA_BG1VOFS                       0x04000016
45 
+#define REG_DISPA_BG2HOFS                       0x04000018
46 
+#define REG_DISPA_BG2VOFS                       0x0400001A
47 
+#define REG_DISPA_BG3HOFS                       0x0400001C
48 
+#define REG_DISPA_BG3VOFS                       0x0400001E
49 
+#define REG_DISPA_BG2PA                         0x04000020
50 
+#define REG_DISPA_BG2PB                         0x04000022
51 
+#define REG_DISPA_BG2PC                         0x04000024
52 
+#define REG_DISPA_BG2PD                         0x04000026
53 
+#define REG_DISPA_BG2XL                         0x04000028
54 
+#define REG_DISPA_BG2XH                         0x0400002A
55 
+#define REG_DISPA_BG2YL                         0x0400002C
56 
+#define REG_DISPA_BG2YH                         0x0400002E
57 
+#define REG_DISPA_BG3PA                         0x04000030
58 
+#define REG_DISPA_BG3PB                         0x04000032
59 
+#define REG_DISPA_BG3PC                         0x04000034
60 
+#define REG_DISPA_BG3PD                         0x04000036
61 
+#define REG_DISPA_BG3XL                         0x04000038
62 
+#define REG_DISPA_BG3XH                         0x0400003A
63 
+#define REG_DISPA_BG3YL                         0x0400003C
64 
+#define REG_DISPA_BG3YH                         0x0400003E
65 
+#define REG_DISPA_WIN0H                         0x04000040
66 
+#define REG_DISPA_WIN1H                         0x04000042
67 
+#define REG_DISPA_WIN0V                         0x04000044
68 
+#define REG_DISPA_WIN1V                         0x04000046
69 
+#define REG_DISPA_WININ                         0x04000048
70 
+#define REG_DISPA_WINOUT                        0x0400004A
71 
+#define REG_DISPA_MOSAIC                        0x0400004C
72 
+#define REG_DISPA_BLDCNT                        0x04000050
73 
+#define REG_DISPA_BLDALPHA                      0x04000052
74 
+#define REG_DISPA_BLDY                          0x04000054
75 
+#define REG_DISPA_MASTERBRIGHT                  0x0400006C
76 
+
77 
+// DMA
78 
+#define _REG_DMA_CONTROL_MIN                    0x040000B0
79 
+#define REG_DMA0SAD                             0x040000B0
80 
+#define REG_DMA0SADL                            0x040000B0
81 
+#define REG_DMA0SADH                            0x040000B2
82 
+#define REG_DMA0DAD                             0x040000B4
83 
+#define REG_DMA0DADL                            0x040000B4
84 
+#define REG_DMA0DADH                            0x040000B6
85 
+#define REG_DMA0CNTL                            0x040000B8
86 
+#define REG_DMA0CNTH                            0x040000BA
87 
+#define REG_DMA1SAD                             0x040000BC
88 
+#define REG_DMA1SADL                            0x040000BC
89 
+#define REG_DMA1SADH                            0x040000BE
90 
+#define REG_DMA1DAD                             0x040000C0
91 
+#define REG_DMA1DADL                            0x040000C0
92 
+#define REG_DMA1DADH                            0x040000C2
93 
+#define REG_DMA1CNTL                            0x040000C4
94 
+#define REG_DMA1CNTH                            0x040000C6
95 
+#define REG_DMA2SAD                             0x040000C8
96 
+#define REG_DMA2SADL                            0x040000C8
97 
+#define REG_DMA2SADH                            0x040000CA
98 
+#define REG_DMA2DAD                             0x040000CC
99 
+#define REG_DMA2DADL                            0x040000CC
100 
+#define REG_DMA2DADH                            0x040000CE
101 
+#define REG_DMA2CNTL                            0x040000D0
102 
+#define REG_DMA2CNTH                            0x040000D2
103 
+#define REG_DMA3SAD                             0x040000D4
104 
+#define REG_DMA3SADL                            0x040000D4
105 
+#define REG_DMA3SADH                            0x040000D6
106 
+#define REG_DMA3DAD                             0x040000D8
107 
+#define REG_DMA3DADL                            0x040000D8
108 
+#define REG_DMA3DADH                            0x040000DA
109 
+#define REG_DMA3CNTL                            0x040000DC
110 
+#define REG_DMA3CNTH                            0x040000DE
111 
+#define _REG_DMA_CONTROL_MAX                    0x040000DF
112 
+#define REG_DMA0FILL                            0x040000E0
113 
+#define REG_DMA1FILL                            0x040000E4
114 
+#define REG_DMA2FILL                            0x040000E8
115 
+#define REG_DMA3FILL                            0x040000EC
116 
+
117 
+// Timers
118 
+#define REG_TM0CNTL                             0x04000100
119 
+#define REG_TM0CNTH                             0x04000102
120 
+#define REG_TM1CNTL                             0x04000104
121 
+#define REG_TM1CNTH                             0x04000106
122 
+#define REG_TM2CNTL                             0x04000108
123 
+#define REG_TM2CNTH                             0x0400010A
124 
+#define REG_TM3CNTL                             0x0400010C
125 
+#define REG_TM3CNTH                             0x0400010E
126 
+
127 
+// SIO/Keypad Input/RTC
128 
+#define REG_SIODATA32                           0x04000120
129 
+#define REG_SIOCNT                              0x04000128
130 
+#define REG_KEYINPUT                            0x04000130
131 
+#define REG_KEYCNT                              0x04000132
132 
+#define REG_RCNT                                0x04000134
133 
+#define REG_EXTKEYIN                            0x04000136
134 
+#define REG_RTC                                 0x04000138
135 
+
136 
+// IPC
137 
+#define REG_IPCSYNC                             0x04000180
138 
+#define REG_IPCFIFOCNT                          0x04000184
139 
+#define REG_IPCFIFOSEND                         0x04000188
140 
+
141 
+// ROM
142 
+#define REG_AUXSPICNT                           0x040001A0
143 
+#define REG_AUXSPIDATA                          0x040001A2
144 
+#define REG_GCROMCTRL                           0x040001A4
145 
+#define REG_GCCMDOUT                            0x040001A8
146 
+#define REG_ENCSEED0L                           0x040001B0
147 
+#define REG_ENCSEED1L                           0x040001B4
148 
+#define REG_ENCSEED0H                           0x040001B8
149 
+#define REG_ENCSEED1H                           0x040001BC
150 
+#define REG_SPICNT                              0x040001C0
151 
+#define REG_SPIDATA                             0x040001C2
152 
+
153 
+// Memory/IRQ
154 
+#define REG_EXMEMCNT                            0x04000204
155 
+#define REG_WIFIWAITCNT                         0x04000206
156 
+#define REG_IME                                 0x04000208
157 
+#define REG_IE                                  0x04000210
158 
+#define REG_IF                                  0x04000214
159 
+#define REG_VRAMCNTA                            0x04000240
160 
+#define REG_VRAMSTAT                            0x04000240
161 
+#define REG_VRAMCNTB                            0x04000241
162 
+#define REG_WRAMSTAT                            0x04000241
163 
+#define REG_VRAMCNTC                            0x04000242
164 
+#define REG_VRAMCNTD                            0x04000243
165 
+#define REG_VRAMCNTE                            0x04000244
166 
+#define REG_VRAMCNTF                            0x04000245
167 
+#define REG_VRAMCNTG                            0x04000246
168 
+#define REG_WRAMCNT                             0x04000247
169 
+#define REG_VRAMCNTH                            0x04000248
170 
+#define REG_VRAMCNTI                            0x04000249
171 
+
172 
+// Math
173 
+#define REG_DIVCNT                              0x04000280
174 
+#define REG_DIVNUMER                            0x04000290
175 
+#define REG_DIVDENOM                            0x04000298
176 
+#define REG_DIVRESULT                           0x040002A0
177 
+#define REG_DIVREMRESULT                        0x040002A8
178 
+#define REG_SQRTCNT                             0x040002B0
179 
+#define REG_SQRTRESULT                          0x040002B4
180 
+#define REG_SQRTPARAM                           0x040002B8
181 
+
182 
+// Other
183 
+#define REG_POSTFLG                             0x04000300
184 
+#define REG_HALTCNT                             0x04000301
185 
+#define REG_POWCNT1                             0x04000304
186 
+#define REG_POWCNT2                             0x04000304
187 
+#define REG_BIOSPROT                            0x04000308
188 
+
189 
+#define REG_DISPB_DISPCNT                       0x04001000
190 
+#define REG_DISPB_BG0CNT                        0x04001008
191 
+#define REG_DISPB_BG1CNT                        0x0400100A
192 
+#define REG_DISPB_BG2CNT                        0x0400100C
193 
+#define REG_DISPB_BG3CNT                        0x0400100E
194 
+#define REG_DISPB_BG0HOFS                       0x04001010
195 
+#define REG_DISPB_BG0VOFS                       0x04001012
196 
+#define REG_DISPB_BG1HOFS                       0x04001014
197 
+#define REG_DISPB_BG1VOFS                       0x04001016
198 
+#define REG_DISPB_BG2HOFS                       0x04001018
199 
+#define REG_DISPB_BG2VOFS                       0x0400101A
200 
+#define REG_DISPB_BG3HOFS                       0x0400101C
201 
+#define REG_DISPB_BG3VOFS                       0x0400101E
202 
+#define REG_DISPB_BG2PA                         0x04001020
203 
+#define REG_DISPB_BG2PB                         0x04001022
204 
+#define REG_DISPB_BG2PC                         0x04001024
205 
+#define REG_DISPB_BG2PD                         0x04001026
206 
+#define REG_DISPB_BG2XL                         0x04001028
207 
+#define REG_DISPB_BG2XH                         0x0400102A
208 
+#define REG_DISPB_BG2YL                         0x0400102C
209 
+#define REG_DISPB_BG2YH                         0x0400102E
210 
+#define REG_DISPB_BG3PA                         0x04001030
211 
+#define REG_DISPB_BG3PB                         0x04001032
212 
+#define REG_DISPB_BG3PC                         0x04001034
213 
+#define REG_DISPB_BG3PD                         0x04001036
214 
+#define REG_DISPB_BG3XL                         0x04001038
215 
+#define REG_DISPB_BG3XH                         0x0400103A
216 
+#define REG_DISPB_BG3YL                         0x0400103C
217 
+#define REG_DISPB_BG3YH                         0x0400103E
218 
+#define REG_DISPB_WIN0H                         0x04001040
219 
+#define REG_DISPB_WIN1H                         0x04001042
220 
+#define REG_DISPB_WIN0V                         0x04001044
221 
+#define REG_DISPB_WIN1V                         0x04001046
222 
+#define REG_DISPB_WININ                         0x04001048
223 
+#define REG_DISPB_WINOUT                        0x0400104A
224 
+#define REG_DISPB_MOSAIC                        0x0400104C
225 
+#define REG_DISPB_BLDCNT                        0x04001050
226 
+#define REG_DISPB_BLDALPHA                      0x04001052
227 
+#define REG_DISPB_BLDY                          0x04001054
228 
+#define REG_DISPB_MASTERBRIGHT                  0x0400106C
229 
+
230 
+// Receive ports
231 
+#define REG_IPCFIFORECV                         0x04100000
232 
+#define REG_GCDATAIN                            0x04100010
233 
+
234 
+
235 
+
236 
+
237 
+
238 
+#define REG_DISPB                               0x00001000
239 
+// core A and B specific
240 
+#define REG_DISPx_DISPCNT                       0x04000000
241 
+#define REG_DISPx_VCOUNT                        0x04000006
242 
+#define REG_DISPx_BG0CNT                        0x04000008
243 
+#define REG_DISPx_BG1CNT                        0x0400000A
244 
+#define REG_DISPx_BG2CNT                        0x0400000C
245 
+#define REG_DISPx_BG3CNT                        0x0400000E
246 
+#define REG_DISPx_BG0HOFS                       0x04000010
247 
+#define REG_DISPx_BG0VOFS                       0x04000012
248 
+#define REG_DISPx_BG1HOFS                       0x04000014
249 
+#define REG_DISPx_BG1VOFS                       0x04000016
250 
+#define REG_DISPx_BG2HOFS                       0x04000018
251 
+#define REG_DISPx_BG2VOFS                       0x0400001A
252 
+#define REG_DISPx_BG3HOFS                       0x0400001C
253 
+#define REG_DISPx_BG3VOFS                       0x0400001E
254 
+#define REG_DISPx_BG2PA                         0x04000020
255 
+#define REG_DISPx_BG2PB                         0x04000022
256 
+#define REG_DISPx_BG2PC                         0x04000024
257 
+#define REG_DISPx_BG2PD                         0x04000026
258 
+#define REG_DISPx_BG2XL                         0x04000028
259 
+#define REG_DISPx_BG2XH                         0x0400002A
260 
+#define REG_DISPx_BG2YL                         0x0400002C
261 
+#define REG_DISPx_BG2YH                         0x0400002E
262 
+#define REG_DISPx_BG3PA                         0x04000030
263 
+#define REG_DISPx_BG3PB                         0x04000032
264 
+#define REG_DISPx_BG3PC                         0x04000034
265 
+#define REG_DISPx_BG3PD                         0x04000036
266 
+#define REG_DISPx_BG3XL                         0x04000038
267 
+#define REG_DISPx_BG3XH                         0x0400003A
268 
+#define REG_DISPx_BG3YL                         0x0400003C
269 
+#define REG_DISPx_BG3YH                         0x0400003E
270 
+#define REG_DISPx_WIN0H                         0x04000040
271 
+#define REG_DISPx_WIN1H                         0x04000042
272 
+#define REG_DISPx_WIN0V                         0x04000044
273 
+#define REG_DISPx_WIN1V                         0x04000046
274 
+#define REG_DISPx_WININ                         0x04000048
275 
+#define REG_DISPx_WINOUT                        0x0400004A
276 
+#define REG_DISPx_MOSAIC                        0x0400004C
277 
+#define REG_DISPx_BLDCNT                        0x04000050
278 
+#define REG_DISPx_BLDALPHA                      0x04000052
279 
+#define REG_DISPx_BLDY                          0x04000054
280 
+#define REG_DISPx_MASTERBRIGHT                  0x0400006C
281 
+// core A specific
282 
+#define REG_DISPA_DISPSTAT                      0x04000004
283 
+#define REG_DISPA_DISP3DCNT                     0x04000060
284 
+#define REG_DISPA_DISPCAPCNT                    0x04000064
285 
+#define REG_DISPA_DISPMMEMFIFO                  0x04000068
286 
+
287 
+#define REG_DISPA_DISP3DCNT_BIT_RDLINES_UNDERFLOW 0x1000
288 
+#define REG_DISPA_DISP3DCNT_BIT_RAM_OVERFLOW 0x2000
289 
+#define REG_DISPA_DISP3DCNT_BITS_ACK (REG_DISPA_DISP3DCNT_BIT_RDLINES_UNDERFLOW|REG_DISPA_DISP3DCNT_BIT_RAM_OVERFLOW)
290 
+
291 
+
292 
+#define eng_3D_RDLINES_COUNT   0x04000320
293 
+#define eng_3D_EDGE_COLOR      0x04000330
294 
+#define eng_3D_ALPHA_TEST_REF  0x04000340
295 
+#define eng_3D_CLEAR_COLOR     0x04000350
296 
+#define eng_3D_CLEAR_DEPTH     0x04000354
297 
+#define eng_3D_CLRIMAGE_OFFSET 0x04000356
298 
+#define eng_3D_FOG_COLOR       0x04000358
299 
+#define eng_3D_FOG_OFFSET      0x0400035C
300 
+#define eng_3D_FOG_TABLE       0x04000360
301 
+#define eng_3D_TOON_TABLE      0x04000380
302 
+#define eng_3D_GXFIFO          0x04000400
303 
+
304 
+//DSI
305 
+#define REG_DSIMODE 0x04004000
306 
+
307 
+// 3d commands
308 
+#define cmd_3D_MTX_MODE        0x04000440
309 
+#define cmd_3D_MTX_PUSH        0x04000444
310 
+#define cmd_3D_MTX_POP         0x04000448
311 
+#define cmd_3D_MTX_STORE       0x0400044C
312 
+#define cmd_3D_MTX_RESTORE     0x04000450
313 
+#define cmd_3D_MTX_IDENTITY    0x04000454
314 
+#define cmd_3D_MTX_LOAD_4x4    0x04000458
315 
+#define cmd_3D_MTX_LOAD_4x3    0x0400045C
316 
+#define cmd_3D_MTX_MULT_4x4    0x04000460
317 
+#define cmd_3D_MTX_MULT_4x3    0x04000464
318 
+#define cmd_3D_MTX_MULT_3x3    0x04000468
319 
+#define cmd_3D_MTX_SCALE       0x0400046C
320 
+#define cmd_3D_MTX_TRANS       0x04000470
321 
+#define cmd_3D_COLOR           0x04000480
322 
+#define cmd_3D_NORMA           0x04000484
323 
+#define cmd_3D_TEXCOORD        0x04000488
324 
+#define cmd_3D_VTX_16          0x0400048C
325 
+#define cmd_3D_VTX_10          0x04000490
326 
+#define cmd_3D_VTX_XY          0x04000494
327 
+#define cmd_3D_VTX_XZ          0x04000498
328 
+#define cmd_3D_VTX_YZ          0x0400049C
329 
+#define cmd_3D_VTX_DIFF        0x040004A0
330 
+#define cmd_3D_POLYGON_ATTR    0x040004A4
331 
+#define cmd_3D_TEXIMAGE_PARAM  0x040004A8
332 
+#define cmd_3D_PLTT_BASE       0x040004AC
333 
+#define cmd_3D_DIF_AMB         0x040004C0
334 
+#define cmd_3D_SPE_EMI         0x040004C4
335 
+#define cmd_3D_LIGHT_VECTOR    0x040004C8
336 
+#define cmd_3D_LIGHT_COLOR     0x040004CC
337 
+#define cmd_3D_SHININESS       0x040004D0
338 
+#define cmd_3D_BEGIN_VTXS      0x04000500
339 
+#define cmd_3D_END_VTXS        0x04000504
340 
+#define cmd_3D_SWAP_BUFFERS    0x04000540
341 
+#define cmd_3D_VIEWPORT        0x04000580
342 
+#define cmd_3D_BOX_TEST        0x040005C0
343 
+#define cmd_3D_POS_TEST        0x040005C4
344 
+#define cmd_3D_VEC_TEST        0x040005C8
345 
+
346 
+#define eng_3D_GXSTAT          0x04000600
347 
+#define eng_3D_RAM_COUNT       0x04000604
348 
+#define eng_3D_DISP_1DOT_DEPTH 0x04000610
349 
+#define eng_3D_POS_RESULT      0x04000620
350 
+#define eng_3D_VEC_RESULT      0x04000630
351 
+#define eng_3D_CLIPMTX_RESULT  0x04000640
352 
+#define eng_3D_VECMTX_RESULT   0x04000680
353 
+
354 
+#define IPCFIFOCNT_SENDEMPTY 0x0001
355 
+#define IPCFIFOCNT_SENDFULL 0x0002
356 
+#define IPCFIFOCNT_SENDIRQEN 0x0004
357 
+#define IPCFIFOCNT_SENDCLEAR 0x0008
358 
+#define IPCFIFOCNT_RECVEMPTY 0x0100
359 
+#define IPCFIFOCNT_RECVFULL 0x0200
360 
+#define IPCFIFOCNT_RECVIRQEN 0x0400
361 
+#define IPCFIFOCNT_FIFOERROR 0x4000
362 
+#define IPCFIFOCNT_FIFOENABLE 0x8000
363 
+#define IPCFIFOCNT_WRITEABLE (IPCFIFOCNT_SENDIRQEN | IPCFIFOCNT_RECVIRQEN | IPCFIFOCNT_FIFOENABLE)
364 
+
365 
+#define IPCSYNC_IRQ_SEND 0x2000
366 
+#define IPCSYNC_IRQ_RECV 0x4000
367 
+
368 
+#define IRQ_BIT_LCD_VBLANK 0
369 
+#define IRQ_BIT_LCD_HBLANK 1
370 
+#define IRQ_BIT_LCD_VMATCH 2
371 
+#define IRQ_BIT_TIMER_0 3
372 
+#define IRQ_BIT_TIMER_1 4
373 
+#define IRQ_BIT_TIMER_2 5
374 
+#define IRQ_BIT_TIMER_3 6
375 
+#define IRQ_BIT_ARM7_SIO 7
376 
+#define IRQ_BIT_DMA_0 8
377 
+#define IRQ_BIT_DMA_2 9
378 
+#define IRQ_BIT_DMA_3 10
379 
+#define IRQ_BIT_DMA_4 11
380 
+#define IRQ_BIT_KEYPAD 12
381 
+#define IRQ_BIT_GAMEPAK 13
382 
+#define IRQ_BIT_IPCSYNC 16
383 
+#define IRQ_BIT_IPCFIFO_SENDEMPTY 17
384 
+#define IRQ_BIT_IPCFIFO_RECVNONEMPTY 18
385 
+#define IRQ_BIT_GC_TRANSFER_COMPLETE 19
386 
+#define IRQ_BIT_GC_IREQ_MC 20
387 
+#define IRQ_BIT_ARM9_GXFIFO 21
388 
+#define IRQ_BIT_ARM7_FOLD 22
389 
+#define IRQ_BIT_ARM7_SPI 23
390 
+#define IRQ_BIT_ARM7_WIFI 24
391 
+
392 
+#define IRQ_MASK_LCD_VBLANK (1<<0)
393 
+#define IRQ_MASK_LCD_HBLANK (1<<1)
394 
+#define IRQ_MASK_LCD_VMATCH (1<<2)
395 
+#define IRQ_MASK_TIMER_0 (1<<3)
396 
+#define IRQ_MASK_TIMER_1 (1<<4)
397 
+#define IRQ_MASK_TIMER_2 (1<<5)
398 
+#define IRQ_MASK_TIMER_3 (1<<6)
399 
+#define IRQ_MASK_ARM7_SIO (1<<7)
400 
+#define IRQ_MASK_DMA_0 (1<<8)
401 
+#define IRQ_MASK_DMA_2 (1<<9)
402 
+#define IRQ_MASK_DMA_3 (1<<10)
403 
+#define IRQ_MASK_DMA_4 (1<<11)
404 
+#define IRQ_MASK_KEYPAD (1<<12)
405 
+#define IRQ_MASK_GAMEPAK (1<<13)
406 
+#define IRQ_MASK_IPCSYNC (1<<16)
407 
+#define IRQ_MASK_IPCFIFO_SENDEMPTY (1<<17)
408 
+#define IRQ_MASK_IPCFIFO_RECVNONEMPTY (1<<18)
409 
+#define IRQ_MASK_GC_TRANSFER_COMPLETE (1<<19)
410 
+#define IRQ_MASK_GC_IREQ_MC (1<<20)
411 
+#define IRQ_MASK_ARM9_GXFIFO (1<<21)
412 
+#define IRQ_MASK_ARM7_FOLD (1<<22)
413 
+#define IRQ_MASK_ARM7_SPI (1<<23)
414 
+#define IRQ_MASK_ARM7_WIFI (1<<24)
415 
+
416 
+#define TSC_MEASURE_TEMP1    0
417 
+#define TSC_MEASURE_Y        1
418 
+#define TSC_MEASURE_BATTERY  2
419 
+#define TSC_MEASURE_Z1       3
420 
+#define TSC_MEASURE_Z2       4
421 
+#define TSC_MEASURE_X        5
422 
+#define TSC_MEASURE_AUX      6
423 
+#define TSC_MEASURE_TEMP2    7
424 
+
425 
+#define EXMEMCNT_MASK_SLOT2_ARM7 (1<<7)
426 
+#define EXMEMCNT_MASK_SLOT2_SRAM_TIME (3)
427 
+#define EXMEMCNT_MASK_SLOT2_ROM_1ST_TIME (3<<2)
428 
+#define EXMEMCNT_MASK_SLOT2_ROM_2ND_TIME (1<<4)
429 
+#define EXMEMCNT_MASK_SLOT2_CLOCKRATE (3<<5)
430 
+
431 
+#endif