@@ -17,7 +17,7 @@

 static int clockTicks;

-static INSN_REGPARM void armUnknownInsn(uint32_t opcode)

+static INSN_REGPARM void armUnknownInsn(uint32_t)

 {

 	CPUUndefinedException();

 }

@@ -52,578 +52,6 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }

 //    RRX_OFFSET: Used to rotate (RRX) the `offset' parameter for LDR and

 //                STR instructions.

-#ifndef C_CORE

-# if 0  // definitions have changed

-//#ifdef __POWERPC__

-#  define OP_SUBS \

-{ \

-	register int Flags; \

-	register int Result; \

-	asm volatile("subco. %0, %2, %3\n" \

-		"mcrxr cr1\n" \

-		"mfcr %1\n" \

-		: "=r" (Result), \

-		"=r" (Flags) \

-		: "r" (reg[base].I), \

-		"r" (value) \

-		); \

-	reg[dest].I = Result; \

-	Z_FLAG = (Flags >> 29) & 1; \

-	N_FLAG = (Flags >> 31) & 1; \

-	C_FLAG = (Flags >> 25) & 1; \

-	V_FLAG = (Flags >> 26) & 1; \

-}

-#  define OP_RSBS \

-{ \

-	register int Flags; \

-	register int Result; \

-	asm volatile("subfco. %0, %2, %3\n" \

-		"mcrxr cr1\n" \

-		"mfcr %1\n" \

-		: "=r" (Result), \

-		"=r" (Flags) \

-		: "r" (reg[base].I), \

-		"r" (value) \

-		); \

-	reg[dest].I = Result; \

-	Z_FLAG = (Flags >> 29) & 1; \

-	N_FLAG = (Flags >> 31) & 1; \

-	C_FLAG = (Flags >> 25) & 1; \

-	V_FLAG = (Flags >> 26) & 1; \

-}

-#  define OP_ADDS \

-{ \

-	register int Flags; \

-	register int Result; \

-	asm volatile("addco. %0, %2, %3\n" \

-		"mcrxr cr1\n" \

-		"mfcr %1\n" \

-		: "=r" (Result), \

-		"=r" (Flags) \

-		: "r" (reg[base].I), \

-		"r" (value) \

-		); \

-	reg[dest].I = Result; \

-	Z_FLAG = (Flags >> 29) & 1; \

-	N_FLAG = (Flags >> 31) & 1; \

-	C_FLAG = (Flags >> 25) & 1; \

-	V_FLAG = (Flags >> 26) & 1; \

-}

-#  define OP_ADCS \

-{ \

-	register int Flags; \

-	register int Result; \

-	asm volatile("mtspr xer, %4\n" \

-		"addeo. %0, %2, %3\n" \

-		"mcrxr cr1\n" \

-		"mfcr %1\n" \

-		: "=r" (Result), \

-		"=r" (Flags) \

-		: "r" (reg[base].I), \

-		"r" (value), \

-		"r" (C_FLAG << 29) \

-		); \

-	reg[dest].I = Result; \

-	Z_FLAG = (Flags >> 29) & 1; \

-	N_FLAG = (Flags >> 31) & 1; \

-	C_FLAG = (Flags >> 25) & 1; \

-	V_FLAG = (Flags >> 26) & 1; \

-}

-#  define OP_SBCS \

-{ \

-	register int Flags; \

-	register int Result; \

-	asm volatile("mtspr xer, %4\n" \

-		"subfeo. %0, %3, %2\n" \

-		"mcrxr cr1\n" \

-		"mfcr %1\n" \

-		: "=r" (Result), \

-		"=r" (Flags) \

-		: "r" (reg[base].I), \

-		"r" (value), \

-		"r" (C_FLAG << 29) \

-		); \

-	reg[dest].I = Result; \

-	Z_FLAG = (Flags >> 29) & 1; \

-	N_FLAG = (Flags >> 31) & 1; \

-	C_FLAG = (Flags >> 25) & 1; \

-	V_FLAG = (Flags >> 26) & 1; \

-}

-#  define OP_RSCS \

-{ \

-	register int Flags; \

-	register int Result; \

-	asm volatile("mtspr xer, %4\n"\

-		"subfeo. %0, %2, %3\n" \

-		"mcrxr cr1\n" \

-		"mfcr %1\n" \

-		: "=r" (Result), \

-		"=r" (Flags) \

-		: "r" (reg[base].I), \

-		"r" (value), \

-		"r" (C_FLAG << 29) \

-		); \

-	reg[dest].I = Result; \

-	Z_FLAG = (Flags >> 29) & 1; \

-	N_FLAG = (Flags >> 31) & 1; \

-	C_FLAG = (Flags >> 25) & 1; \

-	V_FLAG = (Flags >> 26) & 1; \

-}

-#  define OP_CMP \

-{ \

-	register int Flags; \

-	register int Result; \

-	asm volatile("subco. %0, %2, %3\n" \

-		"mcrxr cr1\n" \

-		"mfcr %1\n" \

-		: "=r" (Result), \

-		"=r" (Flags) \

-		: "r" (reg[base].I), \

-		"r" (value) \

-		); \

-	Z_FLAG = (Flags >> 29) & 1; \

-	N_FLAG = (Flags >> 31) & 1; \

-	C_FLAG = (Flags >> 25) & 1; \

-	V_FLAG = (Flags >> 26) & 1; \

-}

-#  define OP_CMN \

-{ \

-	register int Flags; \

-	register int Result; \

-	asm volatile("addco. %0, %2, %3\n" \

-		"mcrxr cr1\n" \

-		"mfcr %1\n" \

-		: "=r" (Result), \

-		"=r" (Flags) \

-		: "r" (reg[base].I), \

-		"r" (value) \

-		); \

-	Z_FLAG = (Flags >> 29) & 1; \

-	N_FLAG = (Flags >> 31) & 1; \

-	C_FLAG = (Flags >> 25) & 1; \

-	V_FLAG = (Flags >> 26) & 1; \

-}

-# else  // !__POWERPC__

-// Macros to emit instructions in the format used by the particular compiler.

-// We use GNU assembler syntax: "op src, dest" rather than "op dest, src"

-

-#  ifdef __GNUC__

-#   define ALU_HEADER asm("mov %%ecx, %%edi; "

-#   define ALU_TRAILER : "=D" (opcode) : "c" (opcode) : "eax", "ebx", "edx", "esi")

-#   define EMIT0(op) #op "; "

-#   define EMIT1(op, arg) #op " " arg "; "

-#   define EMIT2(op, src, dest) #op " " src ", " dest "; "

-#   define KONST(val) "$" #val

-#   define ASMVAR(cvar) ASMVAR2(__USER_LABEL_PREFIX__, cvar)

-#   define ASMVAR2(prefix, cvar) STRING(prefix) cvar

-#   define STRING(x) #x

-#   define VAR(var) ASMVAR(#var)

-#   define VARL(var) ASMVAR(#var)

-#   define REGREF1(index) ASMVAR("reg(" index ")")

-#   define REGREF2(index, scale) ASMVAR("reg(," index "," #scale ")")

-#   define LABEL(n) #n ": "

-#   define LABELREF(n, dir) #n#dir

-#   define al "%%al"

-#   define ah "%%ah"

-#   define eax "%%eax"

-#   define bl "%%bl"

-#   define bh "%%bh"

-#   define ebx "%%ebx"

-#   define cl "%%cl"

-#   define ch "%%ch"

-#   define ecx "%%ecx"

-#   define dl "%%dl"

-#   define dh "%%dh"

-#   define edx "%%edx"

-#   define esp "%%esp"

-#   define ebp "%%ebp"

-#   define esi "%%esi"

-#   define edi "%%edi"

-#   define movzx movzb

-#  else

-#   define ALU_HEADER __asm { __asm mov ecx, opcode

-#   define ALU_TRAILER }

-#   define EMIT0(op) __asm op

-#   define EMIT1(op, arg) __asm op arg

-#   define EMIT2(op, src, dest) __asm op dest, src

-#   define KONST(val) val

-#   define VAR(var) var

-#   define VARL(var) dword ptr var

-#   define REGREF1(index) reg[index]

-#   define REGREF2(index, scale) reg[index * scale]

-#   define LABEL(n) __asm l##n:

-#   define LABELREF(n, dir) l##n

-#  endif

-

-//X//#ifndef _MSC_VER

-// ALU op register usage:

-//    EAX -> 2nd operand value, result (RSB/RSC)

-//    EBX -> C_OUT (carry flag from shift/rotate)

-//    ECX -> opcode (input), shift/rotate count

-//    EDX -> Rn (base) value, result (all except RSB/RSC)

-//    ESI -> Rd (destination) index * 4

-

-// Helper macros for loading value / shift count

-#  define VALUE_LOAD_IMM \

-	EMIT2(and, KONST(0x0F), eax) \

-	EMIT2(mov, REGREF2(eax, 4), eax) \

-	EMIT2(shr, KONST(7), ecx) \

-	EMIT2(and, KONST(0x1F), ecx)

-#  define VALUE_LOAD_REG \

-	EMIT2(and, KONST(0x0F), eax) \

-	EMIT2(cmp, KONST(0x0F), eax) \

-	EMIT2(mov, REGREF2(eax, 4), eax) \

-	EMIT1(jne, LABELREF(3, f)) \

-	EMIT2(add, KONST(4), eax) \

-	LABEL(3) \

-	EMIT2(movzx, ch, ecx) \

-	EMIT2(and, KONST(0x0F), ecx) \

-	EMIT2(mov, REGREF2(ecx, 4), ecx)

-

-// Helper macros for setting flags

-#  define SETCOND_LOGICAL \

-	EMIT1(sets, VAR(N_FLAG)) \

-	EMIT1(setz, VAR(Z_FLAG)) \

-	EMIT2(mov, bl, VAR(C_FLAG))

-#  define SETCOND_ADD \

-	EMIT1(sets, VAR(N_FLAG)) \

-	EMIT1(setz, VAR(Z_FLAG)) \

-	EMIT1(seto, VAR(V_FLAG)) \

-	EMIT1(setc, VAR(C_FLAG))

-#  define SETCOND_SUB \

-	EMIT1(sets, VAR(N_FLAG)) \

-	EMIT1(setz, VAR(Z_FLAG)) \

-	EMIT1(seto, VAR(V_FLAG)) \

-	EMIT1(setnc, VAR(C_FLAG))

-

-// ALU initialization

-#  define ALU_INIT(LOAD_C_FLAG) \

-	ALU_HEADER \

-	LOAD_C_FLAG \

-	EMIT2(mov, ecx, edx) \

-	EMIT2(shr, KONST(14), edx) \

-	EMIT2(mov, ecx, eax) \

-	EMIT2(mov, ecx, esi) \

-	EMIT2(shr, KONST(10), esi) \

-	EMIT2(and, KONST(0x3C), edx) \

-	EMIT2(mov, REGREF1(edx), edx) \

-	EMIT2(and, KONST(0x3C), esi)

-

-#  define LOAD_C_FLAG_YES EMIT2(mov, VAR(C_FLAG), bl)

-#  define LOAD_C_FLAG_NO /*nothing*/

-#  define ALU_INIT_C ALU_INIT(LOAD_C_FLAG_YES)

-#  define ALU_INIT_NC ALU_INIT(LOAD_C_FLAG_NO)

-

-// Macros to load the value operand for an ALU op; these all set N/Z

-// according to the value

-

-// OP Rd,Rb,Rm LSL #

-#  define VALUE_LSL_IMM_C \

-	VALUE_LOAD_IMM \

-	EMIT1(jnz, LABELREF(1, f)) \

-	EMIT1(jmp, LABELREF(0, f)) \

-	LABEL(1) \

-	EMIT2(shl, cl, eax) \

-	EMIT1(setc, bl) \

-	LABEL(0)

-#  define VALUE_LSL_IMM_NC \

-	VALUE_LOAD_IMM \

-	EMIT2(shl, cl, eax)

-

-// OP Rd,Rb,Rm LSL Rs

-#  define VALUE_LSL_REG_C \

-	VALUE_LOAD_REG \

-	EMIT2(test, cl, cl) \

-	EMIT1(jz, LABELREF(0, f)) \

-	EMIT2(cmp, KONST(0x20), cl) \

-	EMIT1(je, LABELREF(1, f)) \

-	EMIT1(ja, LABELREF(2, f)) \

-	EMIT2(shl, cl, eax) \

-	EMIT1(setc, bl) \

-	EMIT1(jmp, LABELREF(0, f)) \

-	LABEL(1) \

-	EMIT2(test, KONST(1), al) \

-	EMIT1(setnz, bl) \

-	EMIT2(xor, eax, eax) \

-	EMIT1(jmp, LABELREF(0, f)) \

-	LABEL(2) \

-	EMIT2(xor, ebx, ebx) \

-	EMIT2(xor, eax, eax) \

-	LABEL(0)

-#  define VALUE_LSL_REG_NC \

-	VALUE_LOAD_REG \

-	EMIT2(cmp, KONST(0x20), cl) \

-	EMIT1(jae, LABELREF(1, f)) \

-	EMIT2(shl, cl, eax) \

-	EMIT1(jmp, LABELREF(0, f)) \

-	LABEL(1) \

-	EMIT2(xor, eax, eax) \

-	LABEL(0)

-

-// OP Rd,Rb,Rm LSR #

-#  define VALUE_LSR_IMM_C \

-	VALUE_LOAD_IMM \

-	EMIT1(jz, LABELREF(1, f)) \

-	EMIT2(shr, cl, eax) \

-	EMIT1(setc, bl) \

-	EMIT1(jmp, LABELREF(0, f)) \

-	LABEL(1) \

-	EMIT2(test, eax, eax) \

-	EMIT1(sets, bl) \

-	EMIT2(xor, eax, eax) \

-	LABEL(0)

-#  define VALUE_LSR_IMM_NC \

-	VALUE_LOAD_IMM \

-	EMIT1(jz, LABELREF(1, f)) \

-	EMIT2(shr, cl, eax) \

-	EMIT1(jmp, LABELREF(0, f)) \

-	LABEL(1) \

-	EMIT2(xor, eax, eax) \

-	LABEL(0)

-

-// OP Rd,Rb,Rm LSR Rs

-#  define VALUE_LSR_REG_C \

-	VALUE_LOAD_REG \

-	EMIT2(test, cl, cl) \

-	EMIT1(jz, LABELREF(0, f)) \

-	EMIT2(cmp, KONST(0x20), cl) \

-	EMIT1(je, LABELREF(1, f)) \

-	EMIT1(ja, LABELREF(2, f)) \

-	EMIT2(shr, cl, eax) \

-	EMIT1(setc, bl) \

-	EMIT1(jmp, LABELREF(0, f)) \

-	LABEL(1) \

-	EMIT2(test, eax, eax) \

-	EMIT1(sets, bl) \

-	EMIT2(xor, eax, eax) \

-	EMIT1(jmp, LABELREF(0, f)) \

-	LABEL(2) \

-	EMIT2(xor, ebx, ebx) \

-	EMIT2(xor, eax, eax) \

-	LABEL(0)

-#  define VALUE_LSR_REG_NC \

-	VALUE_LOAD_REG \

-	EMIT2(cmp, KONST(0x20), cl) \

-	EMIT1(jae, LABELREF(1, f)) \

-	EMIT2(shr, cl, eax) \

-	EMIT1(jmp, LABELREF(0, f)) \

-	LABEL(1) \

-	EMIT2(xor, eax, eax) \

-	LABEL(0)

-

-// OP Rd,Rb,Rm ASR #

-#  define VALUE_ASR_IMM_C \

-	VALUE_LOAD_IMM \

-	EMIT1(jz, LABELREF(1, f)) \

-	EMIT2(sar, cl, eax) \

-	EMIT1(setc, bl) \

-	EMIT1(jmp, LABELREF(0, f)) \

-	LABEL(1) \

-	EMIT2(sar, KONST(31), eax) \

-	EMIT1(sets, bl) \

-	LABEL(0)

-#  define VALUE_ASR_IMM_NC \

-	VALUE_LOAD_IMM \

-	EMIT1(jz, LABELREF(1, f)) \

-	EMIT2(sar, cl, eax) \

-	EMIT1(jmp, LABELREF(0, f)) \

-	LABEL(1) \

-	EMIT2(sar, KONST(31), eax) \

-	LABEL(0)

-

-// OP Rd,Rb,Rm ASR Rs

-#  define VALUE_ASR_REG_C \

-	VALUE_LOAD_REG \

-	EMIT2(test, cl, cl) \

-	EMIT1(jz, LABELREF(0, f)) \

-	EMIT2(cmp, KONST(0x20), cl) \

-	EMIT1(jae, LABELREF(1, f)) \

-	EMIT2(sar, cl, eax) \

-	EMIT1(setc, bl) \

-	EMIT1(jmp, LABELREF(0, f)) \

-	LABEL(1) \

-	EMIT2(sar, KONST(31), eax) \

-	EMIT1(sets, bl) \

-	LABEL(0)

-#  define VALUE_ASR_REG_NC \

-	VALUE_LOAD_REG \

-	EMIT2(cmp, KONST(0x20), cl) \

-	EMIT1(jae, LABELREF(1, f)) \

-	EMIT2(sar, cl, eax) \

-	EMIT1(jmp, LABELREF(0, f)) \

-	LABEL(1) \

-	EMIT2(sar, KONST(31), eax) \

-	LABEL(0)

-

-// OP Rd,Rb,Rm ROR #

-#  define VALUE_ROR_IMM_C \

-	VALUE_LOAD_IMM \

-	EMIT1(jz, LABELREF(1, f)) \

-	EMIT2(ror, cl, eax) \

-	EMIT1(jmp, LABELREF(0, f)) \

-	LABEL(1) \

-	EMIT2(bt, KONST(0), ebx) \

-	EMIT2(rcr, KONST(1), eax) \

-	LABEL(0) \

-	EMIT1(setc, bl)

-#  define VALUE_ROR_IMM_NC \

-	VALUE_LOAD_IMM \

-	EMIT1(jz, LABELREF(1, f)) \

-	EMIT2(ror, cl, eax) \

-	EMIT1(jmp, LABELREF(0, f)) \

-	LABEL(1) \

-	EMIT2(bt, KONST(0), VARL(C_FLAG)) \

-	EMIT2(rcr, KONST(1), eax) \

-	LABEL(0)

-

-// OP Rd,Rb,Rm ROR Rs

-#  define VALUE_ROR_REG_C \

-	VALUE_LOAD_REG \

-	EMIT2(bt, KONST(0), ebx) \

-	EMIT2(ror, cl, eax) \

-	EMIT1(setc, bl)

-#  define VALUE_ROR_REG_NC \

-	VALUE_LOAD_REG \

-	EMIT2(ror, cl, eax)

-

-// OP Rd,Rb,# ROR #

-#  define VALUE_IMM_C \

-	EMIT2(movzx, ch, ecx) \

-	EMIT2(add, ecx, ecx) \

-	EMIT2(movzx, al, eax) \

-	EMIT2(bt, KONST(0), ebx) \

-	EMIT2(ror, cl, eax) \

-	EMIT1(setc, bl)

-#  define VALUE_IMM_NC \

-	EMIT2(movzx, ch, ecx) \

-	EMIT2(add, ecx, ecx) \

-	EMIT2(movzx, al, eax) \

-	EMIT2(ror, cl, eax)

-

-// Macros to perform ALU ops

-

-// Set condition codes iff the destination register is not R15 (PC)

-#  define CHECK_PC(OP, SETCOND) \

-	EMIT2(cmp, KONST(0x3C), esi) \

-	EMIT1(je, LABELREF(8, f)) \

-	OP SETCOND \

-	EMIT1(jmp, LABELREF(9, f)) \

-	LABEL(8) \

-	OP \

-	LABEL(9)

-

-#  define OP_AND \

-	EMIT2(and, eax, edx) \

-	EMIT2(mov, edx, REGREF1(esi))

-#  define OP_ANDS CHECK_PC(OP_AND, SETCOND_LOGICAL)

-#  define OP_EOR \

-	EMIT2(xor, eax, edx) \

-	EMIT2(mov, edx, REGREF1(esi))

-#  define OP_EORS CHECK_PC(OP_EOR, SETCOND_LOGICAL)

-#  define OP_SUB \

-	EMIT2(sub, eax, edx) \

-	EMIT2(mov, edx, REGREF1(esi))

-#  define OP_SUBS CHECK_PC(OP_SUB, SETCOND_SUB)

-#  define OP_RSB \

-	EMIT2(sub, edx, eax) \

-	EMIT2(mov, eax, REGREF1(esi))

-#  define OP_RSBS CHECK_PC(OP_RSB, SETCOND_SUB)

-#  define OP_ADD \

-	EMIT2(add, eax, edx) \

-	EMIT2(mov, edx, REGREF1(esi))

-#  define OP_ADDS CHECK_PC(OP_ADD, SETCOND_ADD)

-#  define OP_ADC \

-	EMIT2(bt, KONST(0), VARL(C_FLAG)) \

-	EMIT2(adc, eax, edx) \

-	EMIT2(mov, edx, REGREF1(esi))

-#  define OP_ADCS CHECK_PC(OP_ADC, SETCOND_ADD)

-#  define OP_SBC \

-	EMIT2(bt, KONST(0), VARL(C_FLAG)) \

-	EMIT0(cmc) \

-	EMIT2(sbb, eax, edx) \

-	EMIT2(mov, edx, REGREF1(esi))

-#  define OP_SBCS CHECK_PC(OP_SBC, SETCOND_SUB)

-#  define OP_RSC \

-	EMIT2(bt, KONST(0), VARL(C_FLAG)) \

-	EMIT0(cmc) \

-	EMIT2(sbb, edx, eax) \

-	EMIT2(mov, eax, REGREF1(esi))

-#  define OP_RSCS CHECK_PC(OP_RSC, SETCOND_SUB)

-#  define OP_TST \

-	EMIT2(and, eax, edx) \

-	SETCOND_LOGICAL

-#  define OP_TEQ \

-	EMIT2(xor, eax, edx) \

-	SETCOND_LOGICAL

-#  define OP_CMP \

-	EMIT2(sub, eax, edx) \

-	SETCOND_SUB

-#  define OP_CMN \

-	EMIT2(add, eax, edx) \

-	SETCOND_ADD

-#  define OP_ORR \

-	EMIT2(or, eax, edx) \

-	EMIT2(mov, edx, REGREF1(esi))

-#  define OP_ORRS CHECK_PC(OP_ORR, SETCOND_LOGICAL)

-#  define OP_MOV \

-	EMIT2(mov, eax, REGREF1(esi))

-#  define OP_MOVS CHECK_PC(EMIT2(test, eax, eax) EMIT2(mov, eax, REGREF1(esi)), SETCOND_LOGICAL)

-#  define OP_BIC \

-	EMIT1(not, eax) \

-	EMIT2(and, eax, edx) \

-	EMIT2(mov, edx, REGREF1(esi))

-#  define OP_BICS CHECK_PC(OP_BIC, SETCOND_LOGICAL)

-#  define OP_MVN \

-	EMIT1(not, eax) \

-	EMIT2(mov, eax, REGREF1(esi))

-#  define OP_MVNS CHECK_PC(OP_MVN EMIT2(test, eax, eax), SETCOND_LOGICAL)

-

-// ALU cleanup macro

-#  define ALU_FINISH ALU_TRAILER

-

-// End of ALU macros

-//X//#endif //_MSC_VER

-#  ifdef __GNUC__

-#   define ROR_IMM_MSR \

-	asm("ror %%cl, %%eax;" \

-		: "=a" (value) \

-		: "a" (opcode & 0xFF), "c" (shift));

-

-#   define ROR_OFFSET \

-	asm("ror %%cl, %0" \

-		: "=r" (offset) \

-		: "0" (offset), "c" (shift));

-

-#   define RRX_OFFSET \

-	asm(EMIT2(btl, KONST(0), VAR(C_FLAG)) \

-		"rcr $1, %0" \

-		: "=r" (offset) \

-		: "0" (offset));

-#  else  // !__GNUC__, i.e. Visual C++

-#   define ROR_IMM_MSR \

-	__asm \

-	{ \

-		__asm mov ecx, shift \

-		__asm ror value, cl \

-	}

-

-#   define ROR_OFFSET \

-	__asm \

-	{ \

-		__asm mov ecx, shift \

-		__asm ror offset, cl \

-	}

-

-#   define RRX_OFFSET \

-	__asm \

-	{ \

-		__asm bt dword ptr C_FLAG, 0 \

-		__asm rcr offset, 1 \

-	}

-#  endif  // !__GNUC__

-# endif  // !__POWERPC__

-#endif  // !C_CORE

-

 // C core

 #define C_SETCOND_LOGICAL \

@@ -641,15 +69,12 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }

 	V_FLAG = !!((NEG(lhs) & POS(rhs) & POS(res)) | (POS(lhs) & NEG(rhs) & NEG(res))); \

 	C_FLAG = !!((NEG(lhs) & POS(rhs)) | (NEG(lhs) & POS(res)) | (POS(rhs) & POS(res)));

-#ifndef ALU_INIT_C

-# define ALU_INIT_C \

+#define ALU_INIT_C \

 	int dest = (opcode >> 12) & 15; \

 	bool C_OUT = C_FLAG; \

 	uint32_t value;

-#endif

 // OP Rd,Rb,Rm LSL #

-#ifndef VALUE_LSL_IMM_C

-# define VALUE_LSL_IMM_C \

+#define VALUE_LSL_IMM_C \

 	unsigned shift = (opcode >> 7) & 0x1F; \

 	if (LIKELY(!shift)) /* LSL #0 most common? */ \

 		value = reg[opcode & 0x0F].I; \

@@ -659,10 +84,8 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }

 		C_OUT = !!((v >> (32 - shift)) & 1); \

 		value = v << shift; \

 	}

-#endif

 // OP Rd,Rb,Rm LSL Rs

-#ifndef VALUE_LSL_REG_C

-# define VALUE_LSL_REG_C \

+#define VALUE_LSL_REG_C \

 	uint32_t shift = reg[(opcode >> 8) & 15].B.B0; \

 	uint32_t rm = reg[opcode & 0x0F].I; \

 	if ((opcode & 0x0F) == 15) \

@@ -688,10 +111,8 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }

 	} \

 	else \

 		value = rm;

-#endif

 // OP Rd,Rb,Rm LSR #

-#ifndef VALUE_LSR_IMM_C

-# define VALUE_LSR_IMM_C \

+#define VALUE_LSR_IMM_C \

 	uint32_t shift = (opcode >> 7) & 0x1F; \

 	if (LIKELY(shift)) \

 	{ \

@@ -704,10 +125,8 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }

 		value = 0; \

 		C_OUT = !!(reg[opcode & 0x0F].I & 0x80000000); \

 	}

-#endif

 // OP Rd,Rb,Rm LSR Rs

-#ifndef VALUE_LSR_REG_C

-# define VALUE_LSR_REG_C \

+#define VALUE_LSR_REG_C \

 	unsigned shift = reg[(opcode >> 8) & 15].B.B0; \

 	uint32_t rm = reg[opcode & 0x0F].I; \

 	if ((opcode & 0x0F) == 15) \

@@ -733,10 +152,8 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }

 	} \

 	else \

 		value = rm;

-#endif

 // OP Rd,Rb,Rm ASR #

-#ifndef VALUE_ASR_IMM_C

-# define VALUE_ASR_IMM_C \

+#define VALUE_ASR_IMM_C \

 	unsigned shift = (opcode >> 7) & 0x1F; \

 	if (LIKELY(shift)) \

 	{ \

@@ -758,10 +175,8 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }

 			C_OUT = false; \

 		} \

 	}

-#endif

 // OP Rd,Rb,Rm ASR Rs

-#ifndef VALUE_ASR_REG_C

-# define VALUE_ASR_REG_C \

+#define VALUE_ASR_REG_C \

 	unsigned shift = reg[(opcode >> 8) & 15].B.B0; \

 	uint32_t rm = reg[opcode & 0x0F].I; \

 	if ((opcode & 0x0F) == 15) \

@@ -790,10 +205,8 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }

 			C_OUT = false; \

 		} \

 	}

-#endif

 // OP Rd,Rb,Rm ROR #

-#ifndef VALUE_ROR_IMM_C

-# define VALUE_ROR_IMM_C \

+#define VALUE_ROR_IMM_C \

 	unsigned shift = (opcode >> 7) & 0x1F; \

 	uint32_t v = reg[opcode & 0x0F].I; \

 	if (LIKELY(shift)) \

@@ -806,10 +219,8 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }

 		C_OUT = !!(v & 1); \

 		value = (v >> 1) | (C_FLAG << 31); \

 	}

-#endif

 // OP Rd,Rb,Rm ROR Rs

-#ifndef VALUE_ROR_REG_C

-# define VALUE_ROR_REG_C \

+#define VALUE_ROR_REG_C \

 	unsigned shift = reg[(opcode >> 8) & 15].B.B0; \

 	uint32_t rm = reg[opcode & 0x0F].I; \

 	if ((opcode & 0x0F) == 15) \

@@ -826,10 +237,8 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }

 		if (shift) \

 			C_OUT = !!(value & 0x80000000); \

 	}

-#endif

 // OP Rd,Rb,# ROR #

-#ifndef VALUE_IMM_C

-# define VALUE_IMM_C \

+#define VALUE_IMM_C \

 	int shift = (opcode & 0xF00) >> 7; \

 	if (UNLIKELY(shift)) \

 	{ \

@@ -839,206 +248,115 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }

 	} \

 	else \

 		value = opcode & 0xFF;

-#endif

 // Make the non-carry versions default to the carry versions

 // (this is fine for C--the compiler will optimize the dead code out)

-#ifndef ALU_INIT_NC

-# define ALU_INIT_NC ALU_INIT_C

-#endif

-#ifndef VALUE_LSL_IMM_NC

-# define VALUE_LSL_IMM_NC VALUE_LSL_IMM_C

-#endif

-#ifndef VALUE_LSL_REG_NC

-# define VALUE_LSL_REG_NC VALUE_LSL_REG_C

-#endif

-#ifndef VALUE_LSR_IMM_NC

-# define VALUE_LSR_IMM_NC VALUE_LSR_IMM_C

-#endif

-#ifndef VALUE_LSR_REG_NC

-# define VALUE_LSR_REG_NC VALUE_LSR_REG_C

-#endif

-#ifndef VALUE_ASR_IMM_NC

-# define VALUE_ASR_IMM_NC VALUE_ASR_IMM_C

-#endif

-#ifndef VALUE_ASR_REG_NC

-# define VALUE_ASR_REG_NC VALUE_ASR_REG_C

-#endif

-#ifndef VALUE_ROR_IMM_NC

-# define VALUE_ROR_IMM_NC VALUE_ROR_IMM_C

-#endif

-#ifndef VALUE_ROR_REG_NC

-# define VALUE_ROR_REG_NC VALUE_ROR_REG_C

-#endif

-#ifndef VALUE_IMM_NC

-# define VALUE_IMM_NC VALUE_IMM_C

-#endif

+#define ALU_INIT_NC ALU_INIT_C

+#define VALUE_LSL_IMM_NC VALUE_LSL_IMM_C

+#define VALUE_LSL_REG_NC VALUE_LSL_REG_C

+#define VALUE_LSR_IMM_NC VALUE_LSR_IMM_C

+#define VALUE_LSR_REG_NC VALUE_LSR_REG_C

+#define VALUE_ASR_IMM_NC VALUE_ASR_IMM_C

+#define VALUE_ASR_REG_NC VALUE_ASR_REG_C

+#define VALUE_ROR_IMM_NC VALUE_ROR_IMM_C

+#define VALUE_ROR_REG_NC VALUE_ROR_REG_C

+#define VALUE_IMM_NC VALUE_IMM_C

 #define C_CHECK_PC(SETCOND) if (LIKELY(dest != 15)) { SETCOND }

-#ifndef OP_AND

-# define OP_AND \

+#define OP_AND \

 	uint32_t res = reg[(opcode >> 16) & 15].I & value; \

-	reg[dest].I = res;

-#endif

-#ifndef OP_ANDS

-# define OP_ANDS OP_AND C_CHECK_PC(C_SETCOND_LOGICAL)

-#endif

-#ifndef OP_EOR

-# define OP_EOR \

+    reg[dest].I = res;

+#define OP_ANDS OP_AND C_CHECK_PC(C_SETCOND_LOGICAL)

+#define OP_EOR \

 	uint32_t res = reg[(opcode >> 16) & 15].I ^ value; \

 	reg[dest].I = res;

-#endif

-#ifndef OP_EORS

-# define OP_EORS OP_EOR C_CHECK_PC(C_SETCOND_LOGICAL)

-#endif

-#ifndef OP_SUB

-# define OP_SUB \

+#define OP_EORS OP_EOR C_CHECK_PC(C_SETCOND_LOGICAL)

+#define OP_SUB \

 	uint32_t lhs = reg[(opcode >> 16) & 15].I; \

 	uint32_t rhs = value; \

 	uint32_t res = lhs - rhs; \

 	reg[dest].I = res;

-#endif

-#ifndef OP_SUBS

-# define OP_SUBS OP_SUB C_CHECK_PC(C_SETCOND_SUB)

-#endif

-#ifndef OP_RSB

-# define OP_RSB \

+#define OP_SUBS OP_SUB C_CHECK_PC(C_SETCOND_SUB)

+#define OP_RSB \

 	uint32_t lhs = value; \

 	uint32_t rhs = reg[(opcode >> 16) & 15].I; \

 	uint32_t res = lhs - rhs; \

 	reg[dest].I = res;

-#endif

-#ifndef OP_RSBS

-# define OP_RSBS OP_RSB C_CHECK_PC(C_SETCOND_SUB)

-#endif

-#ifndef OP_ADD

-# define OP_ADD \

+#define OP_RSBS OP_RSB C_CHECK_PC(C_SETCOND_SUB)

+#define OP_ADD \

 	uint32_t lhs = reg[(opcode >> 16) & 15].I; \

 	uint32_t rhs = value; \

 	uint32_t res = lhs + rhs; \

 	reg[dest].I = res;

-#endif

-#ifndef OP_ADDS

-# define OP_ADDS OP_ADD C_CHECK_PC(C_SETCOND_ADD)

-#endif

-#ifndef OP_ADC

-# define OP_ADC \

+#define OP_ADDS OP_ADD C_CHECK_PC(C_SETCOND_ADD)

+#define OP_ADC \

 	uint32_t lhs = reg[(opcode >> 16) & 15].I; \

 	uint32_t rhs = value; \

 	uint32_t res = lhs + rhs + static_cast<uint32_t>(C_FLAG); \

 	reg[dest].I = res;

-#endif

-#ifndef OP_ADCS

-# define OP_ADCS OP_ADC C_CHECK_PC(C_SETCOND_ADD)

-#endif

-#ifndef OP_SBC

-# define OP_SBC \

+#define OP_ADCS OP_ADC C_CHECK_PC(C_SETCOND_ADD)

+#define OP_SBC \

 	uint32_t lhs = reg[(opcode >> 16) & 15].I; \

 	uint32_t rhs = value; \

 	uint32_t res = lhs - rhs - !static_cast<uint32_t>(C_FLAG); \

 	reg[dest].I = res;

-#endif

-#ifndef OP_SBCS

-# define OP_SBCS OP_SBC C_CHECK_PC(C_SETCOND_SUB)

-#endif

-#ifndef OP_RSC

-# define OP_RSC \

+#define OP_SBCS OP_SBC C_CHECK_PC(C_SETCOND_SUB)

+#define OP_RSC \

 	uint32_t lhs = value; \

 	uint32_t rhs = reg[(opcode >> 16) & 15].I; \

 	uint32_t res = lhs - rhs - !static_cast<uint32_t>(C_FLAG); \

 	reg[dest].I = res;

-#endif

-#ifndef OP_RSCS

-# define OP_RSCS OP_RSC C_CHECK_PC(C_SETCOND_SUB)

-#endif

-#ifndef OP_TST

-# define OP_TST \

+#define OP_RSCS OP_RSC C_CHECK_PC(C_SETCOND_SUB)

+#define OP_TST \

 	uint32_t res = reg[(opcode >> 16) & 0x0F].I & value; \

 	C_SETCOND_LOGICAL;

-#endif

-#ifndef OP_TEQ

-# define OP_TEQ \

+#define OP_TEQ \

 	uint32_t res = reg[(opcode >> 16) & 0x0F].I ^ value; \

 	C_SETCOND_LOGICAL;

-#endif

-#ifndef OP_CMP

-# define OP_CMP \

+#define OP_CMP \

 	uint32_t lhs = reg[(opcode >> 16) & 15].I; \

 	uint32_t rhs = value; \

 	uint32_t res = lhs - rhs; \

 	C_SETCOND_SUB;

-#endif

-#ifndef OP_CMN

-# define OP_CMN \

+#define OP_CMN \

 	uint32_t lhs = reg[(opcode >> 16) & 15].I; \

 	uint32_t rhs = value; \

 	uint32_t res = lhs + rhs; \

 	C_SETCOND_ADD;

-#endif

-#ifndef OP_ORR

-# define OP_ORR \

+#define OP_ORR \

 	uint32_t res = reg[(opcode >> 16) & 0x0F].I | value; \

 	reg[dest].I = res;

-#endif

-#ifndef OP_ORRS

-# define OP_ORRS OP_ORR C_CHECK_PC(C_SETCOND_LOGICAL)

-#endif