@@ -41,7 +41,7 @@ static uint64_t isqrt(uint64_t x)

 	 * is even, and the one bit is as far left as is consistant

 	 * with that condition.)

 	 */

-	uint64_t squaredbit = static_cast<uint64_t>((static_cast<uint64_t>(~0LL) >> 1) & ~(static_cast<uint64_t>(~0LL) >> 2));

+	uint64_t squaredbit = (~0LL >> 1) & ~(~0LL >> 2);

 	/* This portable load replaces the loop that used to be

 	 * here, and was donated by  legalize@xmission.com

 	 */

@@ -860,12 +860,12 @@ static void execsqrt()

 	if (mode)

 	{

 		uint64_t v = T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8);

-		ret = static_cast<uint32_t>(isqrt(v));

+		ret = isqrt(v) & 0xFFFFFFFF;

 	}

 	else

 	{

 		uint32_t v = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8);

-		ret = static_cast<uint32_t>(isqrt(v));

+		ret = isqrt(v) & 0xFFFFFFFF;

 	}

 	// clear the result while the sqrt unit is busy

@@ -889,20 +889,20 @@ static void execdiv()

 	switch (mode)

 	{

 		case 0: // 32/32

-			num = static_cast<int64_t>(static_cast<int32_t>(T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290)));

-			den = static_cast<int64_t>(static_cast<int32_t>(T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298)));

+			num = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);

+			den = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);

 			MMU.divCycles = nds_timer + 36;

 			break;

 		case 1: // 64/32

-		case 3: //gbatek says this is same as mode 1

-			num = static_cast<int64_t>(T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290));

-			den = static_cast<int64_t>(static_cast<int32_t>(T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298)));

+		case 3: // gbatek says this is same as mode 1

+			num = T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);

+			den = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);

 			MMU.divCycles = nds_timer + 68;

 			break;

 		case 2: // 64/64

 		default:

-			num = static_cast<int64_t>(T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290));

-			den = static_cast<int64_t>(T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298));

+			num = T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);

+			den = T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);

 			MMU.divCycles = nds_timer + 68;

 	}

@@ -912,7 +912,7 @@ static void execdiv()

 		mod = num;

 		// the DIV0 flag in DIVCNT is set only if the full 64bit DIV_DENOM value is zero, even in 32bit mode

-		if (!static_cast<uint64_t>(T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298)))

+		if (!T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298))

 			MMU_new.div.div0 = 1;

 	}

 	else

@@ -958,7 +958,7 @@ uint16_t DSI_TSC::write16(uint16_t val)

 			return this->read16();

 		case 1:

 			if (!this->read_flag)

-				this->registers[this->reg_selection] = static_cast<uint8_t>(val);

+				this->registers[this->reg_selection] = val & 0xFF;

 			ret = this->read16();

 			++this->reg_selection;

 			this->reg_selection &= 0x7F;

@@ -1128,7 +1128,7 @@ template<int PROCNUM> static void REG_IF_WriteByte(uint32_t addr, uint8_t val)

 	// ZERO 01-dec-2010 : I am no longer sure this approach is correct.. it proved to be wrong for IPC fifo.......

 	// it seems as if IF bits should always be cached (only the user can clear them)

-	MMU.reg_IF_bits[PROCNUM] &= ~(static_cast<uint32_t>(val) << (addr << 3));

+	MMU.reg_IF_bits[PROCNUM] &= ~(val << (addr << 3));

 	NDS_Reschedule();

 }

@@ -1182,7 +1182,7 @@ static inline uint16_t read_timer(int proc, int timerIndex)

 		return MMU.timer[proc][timerIndex];

 	// for unchained timers, we do not keep the timer up to date. its value will need to be calculated here

-	int32_t diff = static_cast<int32_t>(nds.timerCycle[proc][timerIndex] - nds_timer);

+	int32_t diff = (nds.timerCycle[proc][timerIndex] - nds_timer) & 0xFFFFFFFF;

 	assert(diff >= 0);

 	if (diff < 0)

 		printf("NEW EMULOOP BAD NEWS PLEASE REPORT: TIME READ DIFF < 0 (%d) (%d) (%d)\n", diff, timerIndex, MMU.timerMODE[proc][timerIndex]);

@@ -1201,7 +1201,7 @@ static inline uint16_t read_timer(int proc, int timerIndex)

 	else

 		ret = 65535 - units;

-	return static_cast<uint16_t>(ret);

+	return ret & 0xFFFF;

 }

 static inline void write_timer(int proc, int timerIndex, uint16_t val)

@@ -1311,13 +1311,13 @@ void DmaController::write32(uint32_t val)

 	uint32_t valhi = val >> 16;

 	this->dar = static_cast<EDMADestinationUpdate>((valhi >> 5) & 3);

 	this->sar = static_cast<EDMASourceUpdate>((valhi >> 7) & 3);

-	this->repeatMode = static_cast<uint8_t>(BIT9(valhi));

+	this->repeatMode = BIT9(valhi);

 	this->bitWidth = static_cast<EDMABitWidth>(BIT10(valhi));

 	this->_startmode = (valhi >> 11) & 7;

 	if (this->procnum == ARMCPU_ARM7)

 		this->_startmode &= 6;

-	this->irq = static_cast<uint8_t>(BIT14(valhi));

-	this->enable = static_cast<uint8_t>(BIT15(valhi));

+	this->irq = BIT14(valhi);

+	this->enable = BIT15(valhi);

 	// make sure we don't get any old triggers

 	if (!wasEnable && this->enable)

@@ -1434,7 +1434,7 @@ template<int PROCNUM> void DmaController::doCopy()

 			dstinc = sz;

 			break;

 		case EDMADestinationUpdate_Decrement:

-			dstinc = static_cast<uint32_t>(-static_cast<int32_t>(sz));

+			dstinc = -static_cast<int32_t>(sz);

 			break;

 		case EDMADestinationUpdate_Fixed:

 			dstinc = 0;

@@ -1451,7 +1451,7 @@ template<int PROCNUM> void DmaController::doCopy()

 			srcinc = sz;

 			break;

 		case EDMASourceUpdate_Decrement:

-			srcinc = static_cast<uint32_t>(-static_cast<int32_t>(sz));

+			srcinc = -static_cast<int32_t>(sz);

 			break;

 		case EDMASourceUpdate_Fixed:

 			srcinc = 0;

@@ -1479,7 +1479,7 @@ template<int PROCNUM> void DmaController::doCopy()

 	// we might make another function to do just the raw copy op which can use them with checks

 	// outside the loop

 	int time_elapsed = 0;

-	for (int32_t i = static_cast<int32_t>(todo); i > 0; --i)

+	for (int32_t i = todo; i > 0; --i)

 	{

 		if (sz == 4)

 		{

@@ -1672,7 +1672,7 @@ void FASTCALL _MMU_ARM9_write08(uint32_t adr, uint8_t val)

 			case REG_WRAMCNT:

 			case REG_VRAMCNTH:

 			case REG_VRAMCNTI:

-				MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA), val);

+				MMU_VRAMmapControl(adr - REG_VRAMCNTA, val);

 		}

 		MMU.MMU_MEM[ARMCPU_ARM9][adr >> 20][adr & MMU.MMU_MASK[ARMCPU_ARM9][adr >> 20]] = val;

@@ -1761,8 +1761,8 @@ void FASTCALL _MMU_ARM9_write16(uint32_t adr, uint16_t val)

 			case REG_VRAMCNTE:

 			case REG_VRAMCNTG:

 			case REG_VRAMCNTH:

-				MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA), val & 0xFF);

-				MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA + 1), val >> 8);

+				MMU_VRAMmapControl(adr - REG_VRAMCNTA, val & 0xFF);

+				MMU_VRAMmapControl(adr - REG_VRAMCNTA + 1, val >> 8);

 				break;

 			case REG_IME:

@@ -1776,7 +1776,7 @@ void FASTCALL _MMU_ARM9_write16(uint32_t adr, uint16_t val)

 				return;

 			case REG_IE + 2:

 				NDS_Reschedule();

-				MMU.reg_IE[ARMCPU_ARM9] = (MMU.reg_IE[ARMCPU_ARM9] & 0xFFFF) | (static_cast<uint32_t>(val) << 16);

+				MMU.reg_IE[ARMCPU_ARM9] = (MMU.reg_IE[ARMCPU_ARM9] & 0xFFFF) | (val << 16);

 				return;

 			case REG_IF:

 				REG_IF_WriteWord<ARMCPU_ARM9>(0, val);

@@ -1811,7 +1811,7 @@ void FASTCALL _MMU_ARM9_write16(uint32_t adr, uint16_t val)

 				MMU_writeToGCControl<ARMCPU_ARM9>((T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1A4) & 0xFFFF0000) | val);

 				return;

 			case REG_GCROMCTRL + 2:

-				MMU_writeToGCControl<ARMCPU_ARM9>((T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1A4) & 0xFFFF) | (static_cast<uint32_t>(val) << 16));

+				MMU_writeToGCControl<ARMCPU_ARM9>((T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1A4) & 0xFFFF) | (val << 16));

 				return;

 		}

@@ -1862,22 +1862,22 @@ void FASTCALL _MMU_ARM9_write32(uint32_t adr, uint32_t val)

 		switch (adr)

 		{

 			case REG_SQRTCNT:

-				MMU_new.sqrt.write16(static_cast<uint16_t>(val));

+				MMU_new.sqrt.write16(val & 0xFFFF);

 				return;

 			case REG_DIVCNT:

-				MMU_new.div.write16(static_cast<uint16_t>(val));

+				MMU_new.div.write16(val & 0xFFFF);

 				return;

 			case REG_VRAMCNTA:

 			case REG_VRAMCNTE:

-				MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA), val & 0xFF);

-				MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA + 1), (val >> 8) & 0xFF);

-				MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA + 2), (val >> 16) & 0xFF);

-				MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA + 3), (val >> 24) & 0xFF);

+				MMU_VRAMmapControl(adr - REG_VRAMCNTA, val & 0xFF);

+				MMU_VRAMmapControl(adr - REG_VRAMCNTA + 1, (val >> 8) & 0xFF);

+				MMU_VRAMmapControl(adr - REG_VRAMCNTA + 2, (val >> 16) & 0xFF);

+				MMU_VRAMmapControl(adr - REG_VRAMCNTA + 3, (val >> 24) & 0xFF);

 				break;

 			case REG_VRAMCNTH:

-				MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA), val & 0xFF);

-				MMU_VRAMmapControl(static_cast<uint8_t>(adr - REG_VRAMCNTA + 1), (val >> 8) & 0xFF);

+				MMU_VRAMmapControl(adr - REG_VRAMCNTA, val & 0xFF);

+				MMU_VRAMmapControl(adr - REG_VRAMCNTA + 1, (val >> 8) & 0xFF);

 				break;

 			case REG_IME:

@@ -1901,8 +1901,8 @@ void FASTCALL _MMU_ARM9_write32(uint32_t adr, uint32_t val)

 			case REG_TM3CNTL:

 			{

 				int timerIndex = (adr >> 2) & 0x3;

-				MMU.timerReload[ARMCPU_ARM9][timerIndex] = static_cast<uint16_t>(val);

-				T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & 0xFFF, static_cast<uint16_t>(val));

+				MMU.timerReload[ARMCPU_ARM9][timerIndex] = val & 0xFFFF;

+				T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & 0xFFF, val & 0xFFFF);

 				write_timer(ARMCPU_ARM9, timerIndex, val >> 16);

 				return;

 			}

@@ -1946,7 +1946,7 @@ void FASTCALL _MMU_ARM9_write32(uint32_t adr, uint32_t val)

 				MMU_IPCSync(ARMCPU_ARM9, val);

 				return;

 			case REG_IPCFIFOCNT:

-				IPC_FIFOcnt(ARMCPU_ARM9, static_cast<uint16_t>(val));

+				IPC_FIFOcnt(ARMCPU_ARM9, val & 0xFFFF);

 				return;

 			case REG_IPCFIFOSEND:

 				IPC_FIFOsend(ARMCPU_ARM9, val);

@@ -2001,18 +2001,18 @@ uint8_t FASTCALL _MMU_ARM9_read08(uint32_t adr)

 		//Address is an IO register

 		if (MMU_new.is_dma(adr))

-			return static_cast<uint8_t>(MMU_new.read_dma(ARMCPU_ARM9, 8, adr));

+			return MMU_new.read_dma(ARMCPU_ARM9, 8, adr) & 0xFF;

 		switch (adr)

 		{

 			case REG_IF:

-				return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM9>());

+				return MMU.gen_IF<ARMCPU_ARM9>() & 0xFF;

 			case REG_IF + 1:

-				return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM9>() >> 8);

+				return (MMU.gen_IF<ARMCPU_ARM9>() >> 8) & 0xFF;

 			case REG_IF + 2:

-				return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM9>() >> 16);

+				return (MMU.gen_IF<ARMCPU_ARM9>() >> 16) & 0xFF;

 			case REG_IF + 3:

-				return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM9>() >> 24);

+				return (MMU.gen_IF<ARMCPU_ARM9>() >> 24) & 0xFF;

 			case REG_WRAMCNT:

 				return MMU.WRAMCNT;

@@ -2068,7 +2068,7 @@ uint16_t FASTCALL _MMU_ARM9_read16(uint32_t adr)

 	if ((adr >> 24) == 4)

 	{

 		if (MMU_new.is_dma(adr))

-			return static_cast<uint16_t>(MMU_new.read_dma(ARMCPU_ARM9, 16, adr));

+			return MMU_new.read_dma(ARMCPU_ARM9, 16, adr) & 0xFFFF;

 		// Address is an IO register

 		switch (adr)

@@ -2088,21 +2088,21 @@ uint16_t FASTCALL _MMU_ARM9_read16(uint32_t adr)

 				return 0;

 			case REG_IME:

-				return static_cast<uint16_t>(MMU.reg_IME[ARMCPU_ARM9]);

+				return MMU.reg_IME[ARMCPU_ARM9] & 0xFFFF;

 			// WRAMCNT is readable but VRAMCNT is not, so just return WRAM's value

 			case REG_VRAMCNTG:

 				return MMU.WRAMCNT << 8;

 			case REG_IE:

-				return static_cast<uint16_t>(MMU.reg_IE[ARMCPU_ARM9]);

+				return MMU.reg_IE[ARMCPU_ARM9] & 0xFFFF;

 			case REG_IE + 2:

-				return static_cast<uint16_t>(MMU.reg_IE[ARMCPU_ARM9] >> 16);

+				return (MMU.reg_IE[ARMCPU_ARM9] >> 16) & 0xFFFF;

 			case REG_IF:

-				return static_cast<uint16_t>(MMU.gen_IF<ARMCPU_ARM9>());

+				return MMU.gen_IF<ARMCPU_ARM9>() & 0xFFFF;

 			case REG_IF + 2:

-				return static_cast<uint16_t>(MMU.gen_IF<ARMCPU_ARM9>() >> 16);

+				return (MMU.gen_IF<ARMCPU_ARM9>() >> 16) & 0xFFFF;

 			case REG_TM0CNTL:

 			case REG_TM1CNTL:

@@ -2372,7 +2372,7 @@ void FASTCALL _MMU_ARM7_write16(uint32_t adr, uint16_t val)

 							else

 							{

 								// write

-								MMU.powerMan_Reg[reg] = static_cast<uint8_t>(val);

+								MMU.powerMan_Reg[reg] = val & 0xFF;

 								static const uint32_t PM_SYSTEM_PWR = BIT(6); /*!< \brief  Turn the power *off* if set */

@@ -2395,7 +2395,7 @@ void FASTCALL _MMU_ARM7_write16(uint32_t adr, uint16_t val)

 							T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_SPIDATA >> 20) & 0xff], REG_SPIDATA & 0xfff, 0);

 							break;

 						}

-						T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_SPIDATA >> 20) & 0xff], REG_SPIDATA & 0xfff, fw_transfer(&MMU.fw, static_cast<uint8_t>(val)));

+						T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_SPIDATA >> 20) & 0xff], REG_SPIDATA & 0xfff, fw_transfer(&MMU.fw, val & 0xFF));

 						return;

 					case 2:

@@ -2526,7 +2526,7 @@ void FASTCALL _MMU_ARM7_write16(uint32_t adr, uint16_t val)

 				return;

 			case REG_IE + 2:

 				NDS_Reschedule();

-				MMU.reg_IE[ARMCPU_ARM7] = (MMU.reg_IE[ARMCPU_ARM7] & 0xFFFF) | (static_cast<uint32_t>(val) << 16);

+				MMU.reg_IE[ARMCPU_ARM7] = (MMU.reg_IE[ARMCPU_ARM7] & 0xFFFF) | (val << 16);

 				return;

 			case REG_IF:

@@ -2563,7 +2563,7 @@ void FASTCALL _MMU_ARM7_write16(uint32_t adr, uint16_t val)

 				MMU_writeToGCControl<ARMCPU_ARM7>((T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x1A4) & 0xFFFF0000) | val);

 				return;

 			case REG_GCROMCTRL + 2:

-				MMU_writeToGCControl<ARMCPU_ARM7>((T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x1A4) & 0xFFFF) | (static_cast<uint32_t>(val) << 16));

+				MMU_writeToGCControl<ARMCPU_ARM7>((T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x1A4) & 0xFFFF) | (val << 16));

 				return;

 		}

@@ -2628,8 +2628,8 @@ void FASTCALL _MMU_ARM7_write32(uint32_t adr, uint32_t val)

 			case REG_TM3CNTL:

 			{

 				int timerIndex = (adr >> 2) & 0x3;

-				MMU.timerReload[ARMCPU_ARM7][timerIndex] = static_cast<uint16_t>(val);

-				T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], adr & 0xFFF, static_cast<uint16_t>(val));

+				MMU.timerReload[ARMCPU_ARM7][timerIndex] = val & 0xFFFF;

+				T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], adr & 0xFFF, val & 0xFFFF);

 				write_timer(ARMCPU_ARM7, timerIndex, val >> 16);

 				return;

 			}

@@ -2638,7 +2638,7 @@ void FASTCALL _MMU_ARM7_write32(uint32_t adr, uint32_t val)

 				MMU_IPCSync(ARMCPU_ARM7, val);

 				return;

 			case REG_IPCFIFOCNT:

-				IPC_FIFOcnt(ARMCPU_ARM7, static_cast<uint16_t>(val));

+				IPC_FIFOcnt(ARMCPU_ARM7, val & 0xFFFF);

 				return;

 			case REG_IPCFIFOSEND:

 				IPC_FIFOsend(ARMCPU_ARM7, val);

@@ -2690,20 +2690,20 @@ uint8_t FASTCALL _MMU_ARM7_read08(uint32_t adr)

 	if ((adr >> 24) == 4)

 	{

 		if (MMU_new.is_dma(adr))

-			return static_cast<uint8_t>(MMU_new.read_dma(ARMCPU_ARM7, 8, adr));

+			return MMU_new.read_dma(ARMCPU_ARM7, 8, adr) & 0xFF;

 		// Address is an IO register

 		switch (adr)

 		{

 			case REG_IF:

-				return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM7>());

+				return MMU.gen_IF<ARMCPU_ARM7>() & 0xFF;

 			case REG_IF + 1:

-				return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM7>() >> 8);

+				return (MMU.gen_IF<ARMCPU_ARM7>() >> 8) & 0xFF;

 			case REG_IF + 2:

-				return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM7>() >> 16);

+				return (MMU.gen_IF<ARMCPU_ARM7>() >> 16) & 0xFF;

 			case REG_IF + 3:

-				return static_cast<uint8_t>(MMU.gen_IF<ARMCPU_ARM7>() >> 24);

+				return (MMU.gen_IF<ARMCPU_ARM7>() >> 24) & 0xFF;

 			case REG_WRAMSTAT:

 				return MMU.WRAMCNT;

@@ -2737,22 +2737,22 @@ uint16_t FASTCALL _MMU_ARM7_read16(uint32_t adr)

 		// Address is an IO register

 		if (MMU_new.is_dma(adr))

-			return static_cast<uint16_t>(MMU_new.read_dma(ARMCPU_ARM7, 16, adr));

+			return MMU_new.read_dma(ARMCPU_ARM7, 16, adr) & 0xFFFF;

 		switch (adr)

 		{

 			case REG_IME:

-				return static_cast<uint16_t>(MMU.reg_IME[ARMCPU_ARM7]);

+				return MMU.reg_IME[ARMCPU_ARM7] & 0xFFFF;

 			case REG_IE:

-				return static_cast<uint16_t>(MMU.reg_IE[ARMCPU_ARM7]);

+				return MMU.reg_IE[ARMCPU_ARM7] & 0xFFFF;

 			case REG_IE + 2:

-				return static_cast<uint16_t>(MMU.reg_IE[ARMCPU_ARM7] >> 16);

+				return (MMU.reg_IE[ARMCPU_ARM7] >> 16) & 0xFFFF;

 			case REG_IF:

-				return static_cast<uint16_t>(MMU.gen_IF<ARMCPU_ARM7>());

+				return MMU.gen_IF<ARMCPU_ARM7>() & 0xFFFF;

 			case REG_IF + 2:

-				return static_cast<uint16_t>(MMU.gen_IF<ARMCPU_ARM7>() >> 16);

+				return (MMU.gen_IF<ARMCPU_ARM7>() >> 16) & 0xFFFF;

 			case REG_TM0CNTL:

 			case REG_TM1CNTL:

@@ -130,8 +130,8 @@ private:

 	enum { ASSOCIATIVITY = 1 << ASSOCIATIVESHIFT };

 	enum { BLOCKSIZE = 1 << BLOCKSIZESHIFT };

 	enum { TAGSHIFT = SIZESHIFT - ASSOCIATIVESHIFT };

-	enum { TAGMASK = static_cast<uint32_t>(~0 << TAGSHIFT) };

-	enum { BLOCKMASK = (static_cast<uint32_t>(~0) >> (32 - TAGSHIFT)) & static_cast<uint32_t>(~0 << BLOCKSIZESHIFT) };

+	enum { TAGMASK = ~0 << TAGSHIFT };

+	enum { BLOCKMASK = (~0 >> (32 - TAGSHIFT)) & (~0 << BLOCKSIZESHIFT) };

 	enum { WORDSIZE = sizeof(uint32_t) };

 	enum { WORDSPERBLOCK = (1 << BLOCKSIZESHIFT) / WORDSIZE };

 	enum { DATAPERWORD = WORDSIZE * ASSOCIATIVITY };

@@ -127,7 +127,7 @@ std::unique_ptr<NDS_header> NDS_getROMHeader()

 	memcpy(header->logo, MMU.CART_ROM + 192, 156);

 	header->logoCRC16 = T1ReadWord(MMU.CART_ROM, 348);

 	header->headerCRC16 = T1ReadWord(MMU.CART_ROM, 350);

-	memcpy(header->reserved, MMU.CART_ROM + 352, std::min(160, static_cast<int>(gameInfo.romsize) - 352));

+	memcpy(header->reserved, MMU.CART_ROM + 352, std::min<size_t>(160, gameInfo.romsize - 352));

 	return header;

 }

@@ -298,10 +298,10 @@ struct TSequenceItem_divider : public TSequenceItem

 		T1WriteQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A0, MMU.divResult);

 		T1WriteQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A8, MMU.divMod);

 #else

-		T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A0, static_cast<uint32_t>(MMU.divResult));

-		T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A4, static_cast<uint32_t>(MMU.divResult >> 32));

-		T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A8, static_cast<uint32_t>(MMU.divMod));

-		T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2AC, static_cast<uint32_t>(MMU.divMod >> 32));

+		T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A0, MMU.divResult & 0xFFFFFFFF);

+		T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A4, (MMU.divResult >> 32) & 0xFFFFFFFF);

+		T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A8, MMU.divMod & 0xFFFFFFFF);

+		T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2AC, (MMU.divMod >> 32) & 0xFFFFFFFF);

 #endif

 		MMU.divRunning = false;

 	}

@@ -556,10 +556,10 @@ static void execHardware_hstart()

 	}

 	// write the new vcount

-	T1WriteWord(MMU.ARM9_REG, 6, static_cast<uint16_t>(nds.VCount));

-	T1WriteWord(MMU.ARM9_REG, 0x1006, static_cast<uint16_t>(nds.VCount));

-	T1WriteWord(MMU.ARM7_REG, 6, static_cast<uint16_t>(nds.VCount));

-	T1WriteWord(MMU.ARM7_REG, 0x1006, static_cast<uint16_t>(nds.VCount));

+	T1WriteWord(MMU.ARM9_REG, 6, nds.VCount & 0xFFFF);

+	T1WriteWord(MMU.ARM9_REG, 0x1006, nds.VCount & 0xFFFF);

+	T1WriteWord(MMU.ARM7_REG, 6, nds.VCount & 0xFFFF);

+	T1WriteWord(MMU.ARM7_REG, 0x1006, nds.VCount & 0xFFFF);

 	// turn off hblank status bit

 	T1WriteWord(MMU.ARM9_REG, 4, T1ReadWord(MMU.ARM9_REG, 4) & 0xFFFD);

@@ -802,9 +802,9 @@ template<bool FORCE> void NDS_exec(int32_t)

 			// cast these down to 32bits so that things run faster on 32bit procs

 			uint64_t nds_timer_base = nds_timer;

-			int32_t arm9 = static_cast<int32_t>(nds_arm9_timer - nds_timer);

-			int32_t arm7 = static_cast<int32_t>(nds_arm7_timer - nds_timer);

-			int32_t s32next = static_cast<int32_t>(next - nds_timer);

+			int32_t arm9 = (nds_arm9_timer - nds_timer) & 0xFFFFFFFF;

+			int32_t arm7 = (nds_arm7_timer - nds_timer) & 0xFFFFFFFF;

+			int32_t s32next = (next - nds_timer) & 0xFFFFFFFF;

 #ifdef HAVE_JIT

 			auto arm9arm7 = CommonSettings.use_jit ? armInnerLoop<true, true, true>(nds_timer_base, s32next, arm9, arm7) : armInnerLoop<true, true, false>(nds_timer_base, s32next, arm9, arm7);

@@ -212,7 +212,7 @@ struct GameInfo

 	{

 		this->resize(size);

 		memcpy(&this->romdata[0], buf, size);

-		this->romsize = static_cast<uint32_t>(size);

+		this->romsize = size;

 		this->fillGap();

 	}

@@ -1,6 +1,6 @@

 #ifndef __GNUC__

-#pragma pack(push, 1)

-#pragma warning(disable : 4103)

+# pragma pack(push, 1)

+# pragma warning(disable : 4103)

 #endif

 #ifndef __PACKED

@@ -36,9 +36,9 @@ static const double M_PI = 3.14159265358979323846;

 #include "NDSSystem.h"

 #include "matrix.h"

-static inline int16_t read16(uint32_t addr) { return static_cast<int16_t>(_MMU_read16<ARMCPU_ARM7,MMU_AT_DEBUG>(addr)); }

+static inline int16_t read16(uint32_t addr) { return _MMU_read16<ARMCPU_ARM7,MMU_AT_DEBUG>(addr); }

 static inline uint8_t read08(uint32_t addr) { return _MMU_read08<ARMCPU_ARM7,MMU_AT_DEBUG>(addr); }

-static inline int8_t read_s8(uint32_t addr) { return static_cast<int8_t>(_MMU_read08<ARMCPU_ARM7,MMU_AT_DEBUG>(addr)); }

+static inline int8_t read_s8(uint32_t addr) { return _MMU_read08<ARMCPU_ARM7,MMU_AT_DEBUG>(addr); }

 static const int K_ADPCM_LOOPING_RECOVERY_INDEX = 99999;

 static const int COSINE_INTERPOLATION_RESOLUTION = 8192;

@@ -172,7 +172,7 @@ int SPU_Init(int coreid, int Buffersize)

 	for (i = 0; i < COSINE_INTERPOLATION_RESOLUTION; ++i)

 		cos_lut[i] = (1.0 - std::cos((static_cast<double>(i) / COSINE_INTERPOLATION_RESOLUTION) * M_PI)) * 0.5;

-	SPU_core.reset(new SPU_struct(static_cast<int>(std::ceil(samples_per_hline))));

+	SPU_core.reset(new SPU_struct(std::ceil(samples_per_hline)));

 	SPU_Reset();

 	int j;

@@ -350,7 +350,7 @@ void SPU_struct::KeyOn(int channel)

 			thischan.x = 0x7FFF;

 	}

-	thischan.double_totlength_shifted = static_cast<double>(thischan.totlength << format_shift[thischan.format]);

+	thischan.double_totlength_shifted = thischan.totlength << format_shift[thischan.format];

 	if (thischan.format != 3 && fEqual(thischan.double_totlength_shifted, 0.0))

 	{

@@ -484,7 +484,7 @@ static GpVar bb_profiler_entry;

 	if (!imm) \

 		imm = 31; \

 	c.sar(rhs, imm); \

-	uint32_t rhs_first = static_cast<int32_t>(cpu->R[REG_POS(i, 0)]) >> imm;

+	uint32_t rhs_first = cpu->R[REG_POS(i, 0)] >> imm;

 #define S_ASR_IMM \

 	JIT_COMMENT("S_ASR_IMM"); \

@@ -512,7 +512,7 @@ static GpVar bb_profiler_entry;

 	} \

 	else \

 		c.ror(rhs, imm); \

-	uint32_t rhs_first = imm ? ROR(cpu->R[REG_POS(i, 0)], imm) : (static_cast<uint32_t>(cpu->CPSR.bits.C) << 31) | (cpu->R[REG_POS(i, 0)] >> 1);

+	uint32_t rhs_first = imm ? ROR(cpu->R[REG_POS(i, 0)], imm) : (cpu->CPSR.bits.C << 31) | (cpu->R[REG_POS(i, 0)] >> 1);

 #define S_ROR_IMM \

 	JIT_COMMENT("S_ROR_IMM"); \

@@ -2136,7 +2136,7 @@ template<int PROCNUM, bool store, int dir, bool null_compiled> static FORCEINLIN

 #ifdef ENABLE_ADVANCED_TIMING

 	cycles = 0;

 #endif

-	uintptr_t *func = reinterpret_cast<uintptr_t *>(&JIT_COMPILED_FUNC(adr, PROCNUM));

+	uintptr_t *func = &JIT_COMPILED_FUNC(adr, PROCNUM);

 #define OP(j) \

 { \

@@ -2247,7 +2247,7 @@ static void call_ldm_stm(GpVar adr, uint32_t bitmask, bool store, int dir)

 		// same prototype, but we have to handle splitting of a u64 arg manually

 		GpVar regs_lo = c.newGpVar(kX86VarTypeGpd);

 		GpVar regs_hi = c.newGpVar(kX86VarTypeGpd);

-		c.mov(regs_lo, static_cast<uint32_t>(get_reg_list(bitmask, dir)));

+		c.mov(regs_lo, get_reg_list(bitmask, dir) & 0xFFFFFFFF);

 		c.mov(regs_hi, get_reg_list(bitmask, dir) >> 32);

 		X86CompilerFuncCall *ctx = c.call(reinterpret_cast<void *>(op_ldm_stm_tab[PROCNUM][store][dir > 0]));

 		ctx->setPrototype(ASMJIT_CALL_CONV, FuncBuilder4<uint32_t, uint32_t, uint32_t, uint32_t, int>());

@@ -3685,7 +3685,7 @@ static int OP_B_COND(uint32_t i)

 {

 	Label skip = c.newLabel();

-	uint32_t dst = bb_r15 + (static_cast<uint32_t>(static_cast<int8_t>(i & 0xFF)) << 1);

+	uint32_t dst = bb_r15 + ((i & 0xFF) << 1);

 	c.mov(cpu_ptr(instruct_adr), bb_next_instruction);

@@ -4149,7 +4149,7 @@ template<int PROCNUM> static uint32_t compile_basicblock()

 #endif

 	c.endFunc();

-	ArmOpCompiled f = reinterpret_cast<ArmOpCompiled>(c.make());

+	ArmOpCompiled f = static_cast<ArmOpCompiled>(c.make());

 	if(c.getError())

 	{

 		fprintf(stderr, "JIT error: %s\n", getErrorString(c.getError()));

@@ -4247,13 +4247,13 @@ void arm_jit_reset(bool enable)

 #if PROFILER_JIT_LEVEL > 0

 static int pcmp(PROFILER_COUNTER_INFO *info1, PROFILER_COUNTER_INFO *info2)

 {

-	return static_cast<int>(info2->count - info1->count);

+	return info2->count - info1->count;

 }

 #if PROFILER_JIT_LEVEL > 1

 static int pcmp_entry(PROFILER_ENTRY *info1, PROFILER_ENTRY *info2)

 {

-	return static_cast<int>(info1->cycles - info2->cycles);

+	return info1->cycles - info2->cycles;

 }

 #endif

 #endif

@@ -281,16 +281,16 @@ TEMPLATE static uint32_t sleep()

 TEMPLATE static uint32_t divide()

 {

-	int32_t num = static_cast<int32_t>(cpu->R[0]);

-	int32_t dnum = static_cast<int32_t>(cpu->R[1]);

+	int32_t num = cpu->R[0];

+	int32_t dnum = cpu->R[1];

 	if (!dnum)

 		return 0;

 	int32_t res = num / dnum;

-	cpu->R[0] = static_cast<uint32_t>(res);

-	cpu->R[1] = static_cast<uint32_t>(num % dnum);

-	cpu->R[3] = static_cast<uint32_t>(std::abs(res));

+	cpu->R[0] = res;

+	cpu->R[1] = num % dnum;

+	cpu->R[3] = std::abs(res);

 	return 6;

 }

@@ -324,7 +324,7 @@ TEMPLATE static uint32_t copy()

 					cnt &= 0x1FFFFF;

 					while (cnt)

 					{

-						_MMU_write16<PROCNUM>(dst, static_cast<uint16_t>(val));

+						_MMU_write16<PROCNUM>(dst, val);

 						--cnt;

 						dst += 2;

 					}

@@ -439,7 +439,7 @@ TEMPLATE static uint32_t LZ77UnCompVram()

 						if (byteCount == 2)

 						{

-							_MMU_write16<PROCNUM>(dest, static_cast<uint16_t>(writeValue));

+							_MMU_write16<PROCNUM>(dest, writeValue & 0xFFFF);

 							dest += 2;

 							byteCount = 0;

 							byteShift = 0;

@@ -457,7 +457,7 @@ TEMPLATE static uint32_t LZ77UnCompVram()

 					++byteCount;

 					if (byteCount == 2)

 					{

-						_MMU_write16<PROCNUM>(dest, static_cast<uint16_t>(writeValue));

+						_MMU_write16<PROCNUM>(dest, writeValue & 0xFFFF);

 						dest += 2;

 						byteCount = 0;

 						byteShift = 0;

@@ -479,7 +479,7 @@ TEMPLATE static uint32_t LZ77UnCompVram()

 				++byteCount;

 				if (byteCount == 2)

 				{

-					_MMU_write16<PROCNUM>(dest, static_cast<uint16_t>(writeValue));

+					_MMU_write16<PROCNUM>(dest, writeValue & 0xFFFF);

 					dest += 2;

 					byteShift = 0;

 					byteCount = 0;

@@ -587,7 +587,7 @@ TEMPLATE static uint32_t RLUnCompVram()

 				if (byteCount == 2)

 				{

-					_MMU_write16<PROCNUM>(dest, static_cast<uint16_t>(writeValue));

+					_MMU_write16<PROCNUM>(dest, writeValue & 0xFFFF);

 					dest += 2;

 					byteCount = 0;

 					byteShift = 0;

@@ -609,7 +609,7 @@ TEMPLATE static uint32_t RLUnCompVram()

 				if (byteCount == 2)

 				{

-					_MMU_write16<PROCNUM>(dest, static_cast<uint16_t>(writeValue));

+					_MMU_write16<PROCNUM>(dest, writeValue & 0xFFFF);

 					dest += 2;

 					byteCount = 0;

 					byteShift = 0;

@@ -738,7 +738,7 @@ TEMPLATE static uint32_t UnCompHuffman()

 				{

 					byteCount = 0;

 					byteShift = 0;

-					_MMU_write08<PROCNUM>(dest, static_cast<uint8_t>(writeValue));

+					_MMU_write08<PROCNUM>(dest, writeValue & 0xFF);

 					writeValue = 0;

 					dest += 4;

 					len -= 4;

@@ -801,7 +801,7 @@ TEMPLATE static uint32_t UnCompHuffman()

 					{

 						byteCount = 0;

 						byteShift = 0;

-						_MMU_write08<PROCNUM>(dest, static_cast<uint8_t>(writeValue));

+						_MMU_write08<PROCNUM>(dest, writeValue & 0xFF);

 						dest += 4;

 						writeValue = 0;

 						len -= 4;

@@ -959,7 +959,7 @@ TEMPLATE static uint32_t bios_sqrt()

 TEMPLATE static uint32_t setHaltCR()

 {

-	_MMU_write08<PROCNUM>(0x4000300+cpu->proc_ID, static_cast<uint8_t>(cpu->R[0]));

+	_MMU_write08<PROCNUM>(0x4000300+cpu->proc_ID, cpu->R[0] & 0xFF);

 	return 1;

 }

@@ -1010,7 +1010,7 @@ TEMPLATE static uint32_t getCRC16()

 	// if this implementation is wrong, then it won't match what the real bios returns,

 	// and savefiles created with a bios will be invalid when loaded with non-bios (and vice-versa)

-	uint16_t crc = static_cast<uint16_t>(cpu->R[0]);

+	uint16_t crc = cpu->R[0] & 0xFFFF;

 	uint32_t datap = cpu->R[1];

 	uint32_t size = cpu->R[2] >> 1;

 	uint16_t currVal = 0;

@@ -384,7 +384,7 @@ bool armcp15_t::moveARM2CP(uint32_t val, uint8_t CRn, uint8_t CRm, uint8_t opcod

 			{

 				// On the NDS bit0,2,7,12..19 are R/W, Bit3..6 are always set, all other bits are always zero.

 				this->ctrl = (val & 0x000FF085) | 0x00000078;

-				MMU.ARM9_RW_MODE = static_cast<uint8_t>(BIT7(val));

+				MMU.ARM9_RW_MODE = BIT7(val);

 				// zero 31-jan-2010: change from 0x0FFF0000 to 0xFFFF0000 per gbatek

 				this->cpu->intVector = 0xFFFF0000 * BIT13(val);

 				this->cpu->LDTBit = !BIT15(val); // TBit

@@ -90,7 +90,7 @@ protected:

 			this->vec->resize(amt);

 	}

 public:

-	EMUFILE_MEMORY(std::vector<uint8_t> *underlying) : vec(underlying), ownvec(false), pos(0), len(static_cast<int32_t>(underlying->size())) { }

+	EMUFILE_MEMORY(std::vector<uint8_t> *underlying) : vec(underlying), ownvec(false), pos(0), len(underlying->size()) { }

 	EMUFILE_MEMORY(uint32_t preallocate) : vec(new std::vector<uint8_t>()), ownvec(true), pos(0), len(0)

 	{

 		this->vec->resize(preallocate);

@@ -196,7 +196,7 @@ public:

 	virtual size_t ftell()

 	{

-		return static_cast<size_t>(::ftell(this->fp));

+		return ::ftell(this->fp);

 	}

 	virtual size_t size()

@@ -18,7 +18,7 @@

 #ifndef _INSTRUCIONS_H_

 #define _INSTRUCIONS_H_

-typedef uint32_t (FASTCALL *OpFunc)(const uint32_t i);

+typedef uint32_t (FASTCALL *OpFunc)(uint32_t i);

 extern const OpFunc arm_instructions_set[2][4096];

 extern const char* arm_instruction_names[4096];

 extern const OpFunc thumb_instructions_set[2][1024];

@@ -284,7 +284,7 @@ void BackupDevice::reset()

 		this->state = RUNNING;

 		int savetype = save_types[CommonSettings.manualBackupType].media_type;

 		int savesize = save_types[CommonSettings.manualBackupType].size;

-		this->ensure(static_cast<uint32_t>(savesize)); // expand properly if necessary

+		this->ensure(savesize); // expand properly if necessary

 		this->resize(savesize); // truncate if necessary

 		this->addr_size = this->addr_size_for_old_save_type(savetype);

 	}

@@ -356,12 +356,12 @@ void BackupDevice::load_old_state(uint32_t addrSize, uint8_t *Data, uint32_t dat

 // =======================================================================

 // =======================================================================

-static int no_gba_unpackSAV(void *in_buf, uint32_t fsize, void *out_buf, uint32_t &size)

+static int no_gba_unpackSAV(const uint8_t *in_buf, uint32_t fsize, uint8_t *out_buf, uint32_t &size)

 {

 	const char no_GBA_HEADER_ID[] = "NocashGbaBackupMediaSavDataFile";

 	const char no_GBA_HEADER_SRAM_ID[] = "SRAM";

-	uint8_t *src = static_cast<uint8_t *>(in_buf);

-	uint8_t *dst = static_cast<uint8_t *>(out_buf);

+	const uint8_t *src = in_buf;

+	uint8_t *dst = out_buf;

 	uint32_t src_pos = 0;

 	uint32_t dst_pos = 0;

 	uint32_t size_unpacked = 0;

@@ -379,11 +379,11 @@ static int no_gba_unpackSAV(void *in_buf, uint32_t fsize, void *out_buf, uint32_

 		if (src[i + 0x40] != no_GBA_HEADER_SRAM_ID[i])

 			return 2;

-	compressMethod = *(reinterpret_cast<uint32_t *>(src + 0x44));

+	compressMethod = *(reinterpret_cast<const uint32_t *>(src + 0x44));

 	if (!compressMethod) // unpacked

 	{

-		size_unpacked = *(reinterpret_cast<uint32_t *>(src + 0x48));

+		size_unpacked = *(reinterpret_cast<const uint32_t *>(src + 0x48));

 		src_pos = 0x4C;

 		for (uint32_t i = 0; i < size_unpacked; ++i)

 			dst[dst_pos++] = src[src_pos++];

@@ -393,7 +393,7 @@ static int no_gba_unpackSAV(void *in_buf, uint32_t fsize, void *out_buf, uint32_

 	if (compressMethod == 1) // packed (method 1)

 	{

-		size_unpacked = *(reinterpret_cast<uint32_t *>(src + 0x4C));

+		size_unpacked = *(reinterpret_cast<const uint32_t *>(src + 0x4C));

 		src_pos = 0x50;

 		while (true)

@@ -408,7 +408,7 @@ static int no_gba_unpackSAV(void *in_buf, uint32_t fsize, void *out_buf, uint32_

 			if (cc == 0x80)

 			{

-				uint16_t tsize = *(reinterpret_cast<uint16_t *>(src + src_pos + 1));

+				uint16_t tsize = *(reinterpret_cast<const uint16_t *>(src + src_pos + 1));

 				for (int t = 0; t < tsize; ++t)

 					dst[dst_pos++] = src[src_pos];

 				src_pos += 3;

@@ -433,11 +433,11 @@ static int no_gba_unpackSAV(void *in_buf, uint32_t fsize, void *out_buf, uint32_

 	return 200;

 }

-static uint32_t no_gba_savTrim(void *buf, uint32_t size)

+static uint32_t no_gba_savTrim(uint8_t *buf, uint32_t size)

 {

 	uint32_t rows = size / 16;

 	uint32_t pos = (size - 16);

-	uint8_t *src = static_cast<uint8_t *>(buf);

+	uint8_t *src = buf;

 	for (unsigned i = 0; i < rows; ++i, pos -= 16)

 	{

@@ -539,7 +539,7 @@ void BackupDevice::loadfile()

 	else

 	{

 		// scan for desmume save footer

-		int32_t cookieLen = static_cast<int32_t>(strlen(kDesmumeSaveCookie));

+		int32_t cookieLen = strlen(kDesmumeSaveCookie);

 		auto sigbuf = std::unique_ptr<char[]>(new char[cookieLen]);

 		inf->fseek(-cookieLen, SEEK_END);

 		inf->fread(&sigbuf[0], cookieLen);

@@ -610,7 +610,7 @@ bool BackupDevice::load_raw(const char *fn, uint32_t force_size)

 		return false;

 	fseek(inf, 0, SEEK_END);

-	uint32_t size = static_cast<uint32_t>(ftell(inf));

+	uint32_t size = ftell(inf);

 	uint32_t left = 0;

 	if (force_size > 0)

@@ -43,7 +43,7 @@ inline uint16_t T1ReadWord_guaranteedAligned(const uint8_t *const mem, uint32_t

 {

 	assert(!(addr & 1));

 #ifdef WORDS_BIGENDIAN

-	return (static_cast<uint8_t *>(mem)[addr + 1] << 8) | static_cast<uint8_t *>(mem)[addr];

+	return (mem[addr + 1] << 8) | mem[addr];

 #else

 	return *reinterpret_cast<const uint16_t *>(mem + addr);

 #endif

@@ -52,7 +52,7 @@ inline uint16_t T1ReadWord_guaranteedAligned(const uint8_t *const mem, uint32_t

 inline uint16_t T1ReadWord(const uint8_t *const mem, uint32_t addr)

 {

 #ifdef WORDS_BIGENDIAN

-	return (static_cast<uint8_t *>(mem)[addr + 1] << 8) | static_cast<uint8_t *>(mem)[addr];

+	return (mem[addr + 1] << 8) | mem[addr];

 #else

 	return *reinterpret_cast<const uint16_t *>(mem + addr);

 #endif

@@ -62,7 +62,7 @@ inline uint32_t T1ReadLong_guaranteedAligned(const uint8_t *const mem, uint32_t

 {

 	assert(!(addr & 3));

 #ifdef WORDS_BIGENDIAN

-	return  mem[addr + 3] << 24 | mem[addr + 2] << 16 | mem[addr + 1] << 8 | mem[addr];

+	return (mem[addr + 3] << 24) | (mem[addr + 2] << 16) | (mem[addr + 1] << 8) | mem[addr];

 #else

 	return *reinterpret_cast<const uint32_t *>(mem + addr);

 #endif

@@ -72,7 +72,7 @@ inline uint32_t T1ReadLong(const uint8_t *const mem, uint32_t addr)

 {

 	addr &= ~3;

 #ifdef WORDS_BIGENDIAN

-	return  mem[addr + 3] << 24 | mem[addr + 2] << 16 | mem[addr + 1] << 8 | mem[addr];

+	return (mem[addr + 3] << 24) | (mem[addr + 2] << 16) | (mem[addr + 1] << 8) | mem[addr];

 #else

 	return *reinterpret_cast<const uint32_t *>(mem + addr);

 #endif

@@ -81,8 +81,7 @@ inline uint32_t T1ReadLong(const uint8_t *const mem, uint32_t addr)

 inline uint64_t T1ReadQuad(const uint8_t *const mem, uint32_t addr)

 {

 #ifdef WORDS_BIGENDIAN

-	return  uint64_t(mem[addr + 7]) << 56 | uint64_t(mem[addr + 6]) << 48 | uint64_t(mem[addr + 5]) << 40 | uint64_t(mem[addr + 4]) << 32 |

-		uint64_t(mem[addr + 3]) << 24 | uint64_t(mem[addr + 2]) << 16 | uint64_t(mem[addr + 1]) << 8  | uint64_t(mem[addr]);

+	return (mem[addr + 7] << 56) | (mem[addr + 6] << 48) | (mem[addr + 5] << 40) | (mem[addr + 4] << 32) | (mem[addr + 3] << 24) | (mem[addr + 2] << 16) | (mem[addr + 1] << 8)  | mem[addr];

 #else

 	return *reinterpret_cast<const uint64_t *>(mem + addr);

 #endif

@@ -118,7 +117,7 @@ inline void T1WriteLong(uint8_t *const mem, uint32_t addr, uint32_t val)

 inline void T1WriteQuad(uint8_t *const mem, uint32_t addr, uint64_t val)

 {

 #ifdef WORDS_BIGENDIAN

-	mem[addr + 7] = (val >> 56);

+	mem[addr + 7] = val >> 56;

 	mem[addr + 6] = (val >> 48) & 0xFF;

 	mem[addr + 5] = (val >> 40) & 0xFF;

 	mem[addr + 4] = (val >> 32) & 0xFF;

@@ -36,7 +36,7 @@ StereoOut32::StereoOut32(const StereoOutFloat &src) : Left(static_cast<int32_t>(

 StereoOut16 StereoOut32::DownSample() const

 {

-	return StereoOut16(static_cast<int16_t>(Left >> SndOutVolumeShift), static_cast<int16_t>(Right >> SndOutVolumeShift));

+	return StereoOut16((Left >> SndOutVolumeShift) & 0xFFFF, (Right >> SndOutVolumeShift) & 0xFFFF);

 }

 std::unique_ptr<StereoOut32[]> SndBuffer::m_buffer;