Browse code

Update snes9x code from 1.53 to 1.6.0.

Notable differences from upstream:
* Did not use the same #include setup for the new byuu apu and instead chose to do things more traditionally, as the latter is also much easier to deal with in Visual Studio than just including .cpp files into other .cpp files...
* MSU1 support not included (I see no need for this in a plugin meant to be used for original SNES music).
* The dynamic rate control on the APU not included (I also see no need for it in this plugin).
* The extra resamplers I added in were removed as the original hermite resampler was folded into a single non-inhertiable resampler.
* Bits of cleanup.

Naram Qashat authored on 2021/04/19 21:20:36
Showing 1 changed files
... ...
@@ -1,179 +1,8 @@
1
-/***********************************************************************************
1
+/*****************************************************************************\
2 2
   Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
3
-
4
-  (c) Copyright 1996 - 2002  Gary Henderson (gary.henderson@ntlworld.com),
5
-                             Jerremy Koot (jkoot@snes9x.com)
6
-
7
-  (c) Copyright 2002 - 2004  Matthew Kendora
8
-
9
-  (c) Copyright 2002 - 2005  Peter Bortas (peter@bortas.org)
10
-
11
-  (c) Copyright 2004 - 2005  Joel Yliluoma (http://iki.fi/bisqwit/)
12
-
13
-  (c) Copyright 2001 - 2006  John Weidman (jweidman@slip.net)
14
-
15
-  (c) Copyright 2002 - 2006  funkyass (funkyass@spam.shaw.ca),
16
-                             Kris Bleakley (codeviolation@hotmail.com)
17
-
18
-  (c) Copyright 2002 - 2010  Brad Jorsch (anomie@users.sourceforge.net),
19
-                             Nach (n-a-c-h@users.sourceforge.net),
20
-
21
-  (c) Copyright 2002 - 2011  zones (kasumitokoduck@yahoo.com)
22
-
23
-  (c) Copyright 2006 - 2007  nitsuja
24
-
25
-  (c) Copyright 2009 - 2011  BearOso,
26
-                             OV2
27
-
28
-
29
-  BS-X C emulator code
30
-  (c) Copyright 2005 - 2006  Dreamer Nom,
31
-                             zones
32
-
33
-  C4 x86 assembler and some C emulation code
34
-  (c) Copyright 2000 - 2003  _Demo_ (_demo_@zsnes.com),
35
-                             Nach,
36
-                             zsKnight (zsknight@zsnes.com)
37
-
38
-  C4 C++ code
39
-  (c) Copyright 2003 - 2006  Brad Jorsch,
40
-                             Nach
41
-
42
-  DSP-1 emulator code
43
-  (c) Copyright 1998 - 2006  _Demo_,
44
-                             Andreas Naive (andreasnaive@gmail.com),
45
-                             Gary Henderson,
46
-                             Ivar (ivar@snes9x.com),
47
-                             John Weidman,
48
-                             Kris Bleakley,
49
-                             Matthew Kendora,
50
-                             Nach,
51
-                             neviksti (neviksti@hotmail.com)
52
-
53
-  DSP-2 emulator code
54
-  (c) Copyright 2003         John Weidman,
55
-                             Kris Bleakley,
56
-                             Lord Nightmare (lord_nightmare@users.sourceforge.net),
57
-                             Matthew Kendora,
58
-                             neviksti
59
-
60
-  DSP-3 emulator code
61
-  (c) Copyright 2003 - 2006  John Weidman,
62
-                             Kris Bleakley,
63
-                             Lancer,
64
-                             z80 gaiden
65
-
66
-  DSP-4 emulator code
67
-  (c) Copyright 2004 - 2006  Dreamer Nom,
68
-                             John Weidman,
69
-                             Kris Bleakley,
70
-                             Nach,
71
-                             z80 gaiden
72
-
73
-  OBC1 emulator code
74
-  (c) Copyright 2001 - 2004  zsKnight,
75
-                             pagefault (pagefault@zsnes.com),
76
-                             Kris Bleakley
77
-                             Ported from x86 assembler to C by sanmaiwashi
78
-
79
-  SPC7110 and RTC C++ emulator code used in 1.39-1.51
80
-  (c) Copyright 2002         Matthew Kendora with research by
81
-                             zsKnight,
82
-                             John Weidman,
83
-                             Dark Force
84
-
85
-  SPC7110 and RTC C++ emulator code used in 1.52+
86
-  (c) Copyright 2009         byuu,
87
-                             neviksti
88
-
89
-  S-DD1 C emulator code
90
-  (c) Copyright 2003         Brad Jorsch with research by
91
-                             Andreas Naive,
92
-                             John Weidman
93
-
94
-  S-RTC C emulator code
95
-  (c) Copyright 2001 - 2006  byuu,
96
-                             John Weidman
97
-
98
-  ST010 C++ emulator code
99
-  (c) Copyright 2003         Feather,
100
-                             John Weidman,
101
-                             Kris Bleakley,
102
-                             Matthew Kendora
103
-
104
-  Super FX x86 assembler emulator code
105
-  (c) Copyright 1998 - 2003  _Demo_,
106
-                             pagefault,
107
-                             zsKnight
108
-
109
-  Super FX C emulator code
110
-  (c) Copyright 1997 - 1999  Ivar,
111
-                             Gary Henderson,
112
-                             John Weidman
113
-
114
-  Sound emulator code used in 1.5-1.51
115
-  (c) Copyright 1998 - 2003  Brad Martin
116
-  (c) Copyright 1998 - 2006  Charles Bilyue'
117
-
118
-  Sound emulator code used in 1.52+
119
-  (c) Copyright 2004 - 2007  Shay Green (gblargg@gmail.com)
120
-
121
-  SH assembler code partly based on x86 assembler code
122
-  (c) Copyright 2002 - 2004  Marcus Comstedt (marcus@mc.pp.se)
123
-
124
-  2xSaI filter
125
-  (c) Copyright 1999 - 2001  Derek Liauw Kie Fa
126
-
127
-  HQ2x, HQ3x, HQ4x filters
128
-  (c) Copyright 2003         Maxim Stepin (maxim@hiend3d.com)
129
-
130
-  NTSC filter
131
-  (c) Copyright 2006 - 2007  Shay Green
132
-
133
-  GTK+ GUI code
134
-  (c) Copyright 2004 - 2011  BearOso
135
-
136
-  Win32 GUI code
137
-  (c) Copyright 2003 - 2006  blip,
138
-                             funkyass,
139
-                             Matthew Kendora,
140
-                             Nach,
141
-                             nitsuja
142
-  (c) Copyright 2009 - 2011  OV2
143
-
144
-  Mac OS GUI code
145
-  (c) Copyright 1998 - 2001  John Stiles
146
-  (c) Copyright 2001 - 2011  zones
147
-
148
-
149
-  Specific ports contains the works of other authors. See headers in
150
-  individual files.
151
-
152
-
153
-  Snes9x homepage: http://www.snes9x.com/
154
-
155
-  Permission to use, copy, modify and/or distribute Snes9x in both binary
156
-  and source form, for non-commercial purposes, is hereby granted without
157
-  fee, providing that this license information and copyright notice appear
158
-  with all copies and any derived work.
159
-
160
-  This software is provided 'as-is', without any express or implied
161
-  warranty. In no event shall the authors be held liable for any damages
162
-  arising from the use of this software or it's derivatives.
163
-
164
-  Snes9x is freeware for PERSONAL USE only. Commercial users should
165
-  seek permission of the copyright holders first. Commercial use includes,
166
-  but is not limited to, charging money for Snes9x or software derived from
167
-  Snes9x, including Snes9x or derivatives in commercial game bundles, and/or
168
-  using Snes9x as a promotion for your commercial product.
169
-
170
-  The copyright holders request that bug fixes and improvements to the code
171
-  should be forwarded to them so everyone can benefit from the modifications
172
-  in future versions.
173
-
174
-  Super NES and Super Nintendo Entertainment System are trademarks of
175
-  Nintendo Co., Limited and its subsidiary companies.
176
- ***********************************************************************************/
3
+                This file is licensed under the Snes9x License.
4
+   For further information, consult the LICENSE file in the root directory.
5
+\*****************************************************************************/
177 6
 
178 7
 #pragma once
179 8
 
... ...
@@ -183,9 +12,7 @@ inline void addCyclesInMemoryAccess(int32_t speed)
183 12
 {
184 13
 	if (!CPU.InDMAorHDMA)
185 14
 	{
186
-		CPU.PrevCycles = CPU.Cycles;
187 15
 		CPU.Cycles += speed;
188
-		S9xCheckInterrupts();
189 16
 		while (CPU.Cycles >= CPU.NextEvent)
190 17
 			S9xDoHEventProcessing();
191 18
 	}
... ...
@@ -195,9 +22,7 @@ inline void addCyclesInMemoryAccess_x2(int32_t speed)
195 22
 {
196 23
 	if (!CPU.InDMAorHDMA)
197 24
 	{
198
-		CPU.PrevCycles = CPU.Cycles;
199 25
 		CPU.Cycles += speed << 1;
200
-		S9xCheckInterrupts();
201 26
 		while (CPU.Cycles >= CPU.NextEvent)
202 27
 			S9xDoHEventProcessing();
203 28
 	}
... ...
@@ -278,34 +103,35 @@ inline uint8_t S9xGetByte(uint32_t Address)
278 103
 
279 104
 inline uint16_t S9xGetWord(uint32_t Address, s9xwrap_t w = WRAP_NONE)
280 105
 {
106
+	uint16_t word;
107
+
281 108
 	uint32_t mask = MEMMAP_MASK & (w == WRAP_PAGE ? 0xff : (w == WRAP_BANK ? 0xffff : 0xffffff));
282 109
 	if ((Address & mask) == mask)
283 110
 	{
284 111
 		PC_t a;
285 112
 
286
-		OpenBus = S9xGetByte(Address);
113
+		word = OpenBus = S9xGetByte(Address);
287 114
 
288 115
 		switch (w)
289 116
 		{
290 117
 			case WRAP_PAGE:
291 118
 				a.xPBPC = Address;
292 119
 				++a.B.xPCl;
293
-				return OpenBus | (S9xGetByte(a.xPBPC) << 8);
120
+				return word | (S9xGetByte(a.xPBPC) << 8);
294 121
 
295 122
 			case WRAP_BANK:
296 123
 				a.xPBPC = Address;
297 124
 				++a.W.xPC;
298
-				return OpenBus | (S9xGetByte(a.xPBPC) << 8);
125
+				return word | (S9xGetByte(a.xPBPC) << 8);
299 126
 
300 127
 			default:
301
-				return OpenBus | (S9xGetByte(Address + 1) << 8);
128
+				return word | (S9xGetByte(Address + 1) << 8);
302 129
 		}
303 130
 	}
304 131
 
305 132
 	int block = (Address & 0xffffff) >> MEMMAP_SHIFT;
306 133
 	uint8_t *GetAddress = Memory.Map[block];
307 134
 	int32_t speed = memory_speed(Address);
308
-	uint16_t word;
309 135
 
310 136
 	if (GetAddress >= reinterpret_cast<uint8_t *>(CMemory::MAP_LAST))
311 137
 	{
... ...
@@ -326,8 +152,8 @@ inline uint16_t S9xGetWord(uint32_t Address, s9xwrap_t w = WRAP_NONE)
326 152
 		case CMemory::MAP_PPU:
327 153
 			if (CPU.InDMAorHDMA)
328 154
 			{
329
-				OpenBus = S9xGetByte(Address);
330
-				return OpenBus | (S9xGetByte(Address + 1) << 8);
155
+				word = OpenBus = S9xGetByte(Address);
156
+				return word | (S9xGetByte(Address + 1) << 8);
331 157
 			}
332 158
 
333 159
 			word  = S9xGetPPU(Address & 0xffff);
... ...
@@ -550,8 +376,7 @@ inline void S9xSetPCBase(uint32_t Address)
550 376
 	Registers.PC.xPBPC = Address & 0xffffff;
551 377
 	ICPU.ShiftedPB = Address & 0xff0000;
552 378
 
553
-	int block;
554
-	uint8_t *GetAddress = Memory.Map[block = ((Address & 0xffffff) >> MEMMAP_SHIFT)];
379
+	uint8_t *GetAddress = Memory.Map[static_cast<int>((Address & 0xffffff) >> MEMMAP_SHIFT)];
555 380
 
556 381
 	CPU.MemSpeed = memory_speed(Address);
557 382
 	CPU.MemSpeedx2 = CPU.MemSpeed << 1;
Browse code

* Fixes for gcc and clang (while they can compile the code, the DLLs made aren't functional, but oh well).

* [2SF] Used more up-to-date asmjit, despite the ugly looking code.

Naram Qashat authored on 2014/09/17 19:51:45
Showing 1 changed files
... ...
@@ -363,7 +363,7 @@ inline uint16_t S9xGetWord(uint32_t Address, s9xwrap_t w = WRAP_NONE)
363 363
 	}
364 364
 }
365 365
 
366
-inline void S9xSetByte(uint8_t Byte, uint32_t Address)
366
+inline void S9xSetByte(uint8_t Byt, uint32_t Address)
367 367
 {
368 368
 	int block = (Address & 0xffffff) >> MEMMAP_SHIFT;
369 369
 	uint8_t *SetAddress = Memory.WriteMap[block];
... ...
@@ -371,7 +371,7 @@ inline void S9xSetByte(uint8_t Byte, uint32_t Address)
371 371
 
372 372
 	if (SetAddress >= reinterpret_cast<uint8_t *>(CMemory::MAP_LAST))
373 373
 	{
374
-		SetAddress[Address & 0xffff] = Byte;
374
+		SetAddress[Address & 0xffff] = Byt;
375 375
 		addCyclesInMemoryAccess(speed);
376 376
 		return;
377 377
 	}
... ...
@@ -379,7 +379,7 @@ inline void S9xSetByte(uint8_t Byte, uint32_t Address)
379 379
 	switch (reinterpret_cast<intptr_t>(SetAddress))
380 380
 	{
381 381
 		case CMemory::MAP_CPU:
382
-			S9xSetCPU(Byte, Address & 0xffff);
382
+			S9xSetCPU(Byt, Address & 0xffff);
383 383
 			addCyclesInMemoryAccess(speed);
384 384
 			break;
385 385
 
... ...
@@ -387,26 +387,26 @@ inline void S9xSetByte(uint8_t Byte, uint32_t Address)
387 387
 			if (CPU.InDMAorHDMA && (Address & 0xff00) == 0x2100)
388 388
 				return;
389 389
 
390
-			S9xSetPPU(Byte, Address & 0xffff);
390
+			S9xSetPPU(Byt, Address & 0xffff);
391 391
 			addCyclesInMemoryAccess(speed);
392 392
 			break;
393 393
 
394 394
 		case CMemory::MAP_LOROM_SRAM:
395 395
 			if (Memory.SRAMMask)
396
-				Memory.SRAM[(((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask] = Byte;
396
+				Memory.SRAM[(((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask] = Byt;
397 397
 
398 398
 			addCyclesInMemoryAccess(speed);
399 399
 			break;
400 400
 
401 401
 		case CMemory::MAP_HIROM_SRAM:
402 402
 			if (Memory.SRAMMask)
403
-				Memory.SRAM[((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask] = Byte;
403
+				Memory.SRAM[((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask] = Byt;
404 404
 
405 405
 			addCyclesInMemoryAccess(speed);
406 406
 			break;
407 407
 
408 408
 		case CMemory::MAP_SA1RAM:
409
-			Memory.SRAM[Address & 0xffff] = Byte;
409
+			Memory.SRAM[Address & 0xffff] = Byt;
410 410
 			addCyclesInMemoryAccess(speed);
411 411
 			break;
412 412
 
Browse code

Use #pragma once instead of include guards.

Naram Qashat authored on 2014/09/08 14:47:36
Showing 1 changed files
... ...
@@ -175,8 +175,7 @@
175 175
   Nintendo Co., Limited and its subsidiary companies.
176 176
  ***********************************************************************************/
177 177
 
178
-#ifndef _GETSET_H_
179
-#define _GETSET_H_
178
+#pragma once
180 179
 
181 180
 #include "cpuexec.h"
182 181
 
... ...
@@ -641,5 +640,3 @@ inline uint8_t *S9xGetMemPointer(uint32_t Address)
641 640
 			return nullptr;
642 641
 	}
643 642
 }
644
-
645
-#endif
Browse code

[SNSF] Massive code cleanup, as well as removing as much unused code/variables as possible.

Naram Qashat authored on 2013/05/23 06:02:16
Showing 1 changed files
... ...
@@ -175,42 +175,38 @@
175 175
   Nintendo Co., Limited and its subsidiary companies.
176 176
  ***********************************************************************************/
177 177
 
178
-
179 178
 #ifndef _GETSET_H_
180 179
 #define _GETSET_H_
181 180
 
182 181
 #include "cpuexec.h"
183
-//#include "dsp.h"
184
-//#include "sa1.h"
185
-//#include "spc7110.h"
186
-//#include "c4.h"
187
-//#include "obc1.h"
188
-//#include "seta.h"
189
-//#include "bsx.h"
190
-
191
-#define addCyclesInMemoryAccess \
192
-	if (!CPU.InDMAorHDMA) \
193
-	{ \
194
-		CPU.PrevCycles = CPU.Cycles; \
195
-		CPU.Cycles += speed; \
196
-		S9xCheckInterrupts(); \
197
-		while (CPU.Cycles >= CPU.NextEvent) \
198
-			S9xDoHEventProcessing(); \
182
+
183
+inline void addCyclesInMemoryAccess(int32_t speed)
184
+{
185
+	if (!CPU.InDMAorHDMA)
186
+	{
187
+		CPU.PrevCycles = CPU.Cycles;
188
+		CPU.Cycles += speed;
189
+		S9xCheckInterrupts();
190
+		while (CPU.Cycles >= CPU.NextEvent)
191
+			S9xDoHEventProcessing();
199 192
 	}
193
+}
200 194
 
201
-#define addCyclesInMemoryAccess_x2 \
202
-	if (!CPU.InDMAorHDMA) \
203
-	{ \
204
-		CPU.PrevCycles = CPU.Cycles; \
205
-		CPU.Cycles += speed << 1; \
206
-		S9xCheckInterrupts(); \
207
-		while (CPU.Cycles >= CPU.NextEvent) \
208
-			S9xDoHEventProcessing(); \
195
+inline void addCyclesInMemoryAccess_x2(int32_t speed)
196
+{
197
+	if (!CPU.InDMAorHDMA)
198
+	{
199
+		CPU.PrevCycles = CPU.Cycles;
200
+		CPU.Cycles += speed << 1;
201
+		S9xCheckInterrupts();
202
+		while (CPU.Cycles >= CPU.NextEvent)
203
+			S9xDoHEventProcessing();
209 204
 	}
205
+}
210 206
 
211
-extern uint8_t	OpenBus;
207
+extern uint8_t OpenBus;
212 208
 
213
-static inline int32_t memory_speed (uint32_t address)
209
+inline int32_t memory_speed(uint32_t address)
214 210
 {
215 211
 	if (address & 0x408000)
216 212
 	{
... ...
@@ -229,25 +225,25 @@ static inline int32_t memory_speed (uint32_t address)
229 225
 	return TWO_CYCLES;
230 226
 }
231 227
 
232
-inline uint8_t S9xGetByte (uint32_t Address)
228
+inline uint8_t S9xGetByte(uint32_t Address)
233 229
 {
234
-	int		block = (Address & 0xffffff) >> MEMMAP_SHIFT;
235
-	uint8_t	*GetAddress = Memory.Map[block];
236
-	int32_t	speed = memory_speed(Address);
237
-	uint8_t	byte;
230
+	int block = (Address & 0xffffff) >> MEMMAP_SHIFT;
231
+	uint8_t *GetAddress = Memory.Map[block];
232
+	int32_t speed = memory_speed(Address);
233
+	uint8_t byte;
238 234
 
239
-	if (GetAddress >= (uint8_t *) CMemory::MAP_LAST)
235
+	if (GetAddress >= reinterpret_cast<uint8_t *>(CMemory::MAP_LAST))
240 236
 	{
241
-		byte = *(GetAddress + (Address & 0xffff));
242
-		addCyclesInMemoryAccess;
237
+		byte = GetAddress[Address & 0xffff];
238
+		addCyclesInMemoryAccess(speed);
243 239
 		return byte;
244 240
 	}
245 241
 
246
-	switch ((intptr_t) GetAddress)
242
+	switch (reinterpret_cast<intptr_t>(GetAddress))
247 243
 	{
248 244
 		case CMemory::MAP_CPU:
249 245
 			byte = S9xGetCPU(Address & 0xffff);
250
-			addCyclesInMemoryAccess;
246
+			addCyclesInMemoryAccess(speed);
251 247
 			return byte;
252 248
 
253 249
 		case CMemory::MAP_PPU:
... ...
@@ -255,7 +251,7 @@ inline uint8_t S9xGetByte (uint32_t Address)
255 251
 				return OpenBus;
256 252
 
257 253
 			byte = S9xGetPPU(Address & 0xffff);
258
-			addCyclesInMemoryAccess;
254
+			addCyclesInMemoryAccess(speed);
259 255
 			return byte;
260 256
 
261 257
 		case CMemory::MAP_LOROM_SRAM:
... ...
@@ -264,80 +260,29 @@ inline uint8_t S9xGetByte (uint32_t Address)
264 260
 			// Address & 0xff0000 : bank
265 261
 			// bank >> 1 | offset : SRAM address, unbound
266 262
 			// unbound & SRAMMask : SRAM offset
267
-			byte = *(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask));
268
-			addCyclesInMemoryAccess;
269
-			return byte;
270
-
271
-		case CMemory::MAP_LOROM_SRAM_B:
272
-			byte = *(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB));
273
-			addCyclesInMemoryAccess;
263
+			byte = Memory.SRAM[(((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask];
264
+			addCyclesInMemoryAccess(speed);
274 265
 			return byte;
275 266
 
276 267
 		case CMemory::MAP_HIROM_SRAM:
277 268
 		case CMemory::MAP_RONLY_SRAM:
278
-			byte = *(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask));
279
-			addCyclesInMemoryAccess;
269
+			byte = Memory.SRAM[((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask];
270
+			addCyclesInMemoryAccess(speed);
280 271
 			return byte;
281 272
 
282
-		case CMemory::MAP_BWRAM:
283
-			byte = *(Memory.BWRAM + ((Address & 0x7fff) - 0x6000));
284
-			addCyclesInMemoryAccess;
285
-			return byte;
286
-
287
-		/*case CMemory::MAP_DSP:
288
-			byte = S9xGetDSP(Address & 0xffff);
289
-			addCyclesInMemoryAccess;
290
-			return byte;
291
-
292
-		case CMemory::MAP_SPC7110_ROM:
293
-			byte = S9xGetSPC7110Byte(Address);
294
-			addCyclesInMemoryAccess;
295
-			return byte;
296
-
297
-		case CMemory::MAP_SPC7110_DRAM:
298
-			byte = S9xGetSPC7110(0x4800);
299
-			addCyclesInMemoryAccess;
300
-			return byte;
301
-
302
-		case CMemory::MAP_C4:
303
-			byte = S9xGetC4(Address & 0xffff);
304
-			addCyclesInMemoryAccess;
305
-			return byte;
306
-
307
-		case CMemory::MAP_OBC_RAM:
308
-			byte = S9xGetOBC1(Address & 0xffff);
309
-			addCyclesInMemoryAccess;
310
-			return byte;
311
-
312
-		case CMemory::MAP_SETA_DSP:
313
-			byte = S9xGetSetaDSP(Address);
314
-			addCyclesInMemoryAccess;
315
-			return byte;
316
-
317
-		case CMemory::MAP_SETA_RISC:
318
-			byte = S9xGetST018(Address);
319
-			addCyclesInMemoryAccess;
320
-			return byte;
321
-
322
-		case CMemory::MAP_BSX:
323
-			byte = S9xGetBSX(Address);
324
-			addCyclesInMemoryAccess;
325
-			return byte;*/
326
-
327
-		case CMemory::MAP_NONE:
328 273
 		default:
329 274
 			byte = OpenBus;
330
-			addCyclesInMemoryAccess;
275
+			addCyclesInMemoryAccess(speed);
331 276
 			return byte;
332 277
 	}
333 278
 }
334 279
 
335
-inline uint16_t S9xGetWord (uint32_t Address, enum s9xwrap_t w = WRAP_NONE)
280
+inline uint16_t S9xGetWord(uint32_t Address, s9xwrap_t w = WRAP_NONE)
336 281
 {
337
-	uint32_t	mask = MEMMAP_MASK & (w == WRAP_PAGE ? 0xff : (w == WRAP_BANK ? 0xffff : 0xffffff));
282
+	uint32_t mask = MEMMAP_MASK & (w == WRAP_PAGE ? 0xff : (w == WRAP_BANK ? 0xffff : 0xffffff));
338 283
 	if ((Address & mask) == mask)
339 284
 	{
340
-		PC_t	a;
285
+		PC_t a;
341 286
 
342 287
 		OpenBus = S9xGetByte(Address);
343 288
 
... ...
@@ -345,39 +290,38 @@ inline uint16_t S9xGetWord (uint32_t Address, enum s9xwrap_t w = WRAP_NONE)
345 290
 		{
346 291
 			case WRAP_PAGE:
347 292
 				a.xPBPC = Address;
348
-				a.B.xPCl++;
293
+				++a.B.xPCl;
349 294
 				return OpenBus | (S9xGetByte(a.xPBPC) << 8);
350 295
 
351 296
 			case WRAP_BANK:
352 297
 				a.xPBPC = Address;
353
-				a.W.xPC++;
298
+				++a.W.xPC;
354 299
 				return OpenBus | (S9xGetByte(a.xPBPC) << 8);
355 300
 
356
-			case WRAP_NONE:
357 301
 			default:
358 302
 				return OpenBus | (S9xGetByte(Address + 1) << 8);
359 303
 		}
360 304
 	}
361 305
 
362
-	int		block = (Address & 0xffffff) >> MEMMAP_SHIFT;
363
-	uint8_t	*GetAddress = Memory.Map[block];
364
-	int32_t	speed = memory_speed(Address);
365
-	uint16_t	word;
306
+	int block = (Address & 0xffffff) >> MEMMAP_SHIFT;
307
+	uint8_t *GetAddress = Memory.Map[block];
308
+	int32_t speed = memory_speed(Address);
309
+	uint16_t word;
366 310
 
367
-	if (GetAddress >= (uint8_t *) CMemory::MAP_LAST)
311
+	if (GetAddress >= reinterpret_cast<uint8_t *>(CMemory::MAP_LAST))
368 312
 	{
369
-		word = READ_WORD(GetAddress + (Address & 0xffff));
370
-		addCyclesInMemoryAccess_x2;
313
+		word = READ_WORD(&GetAddress[Address & 0xffff]);
314
+		addCyclesInMemoryAccess_x2(speed);
371 315
 		return word;
372 316
 	}
373 317
 
374
-	switch ((intptr_t) GetAddress)
318
+	switch (reinterpret_cast<intptr_t>(GetAddress))
375 319
 	{
376 320
 		case CMemory::MAP_CPU:
377 321
 			word  = S9xGetCPU(Address & 0xffff);
378
-			addCyclesInMemoryAccess;
322
+			addCyclesInMemoryAccess(speed);
379 323
 			word |= S9xGetCPU((Address + 1) & 0xffff) << 8;
380
-			addCyclesInMemoryAccess;
324
+			addCyclesInMemoryAccess(speed);
381 325
 			return word;
382 326
 
383 327
 		case CMemory::MAP_PPU:
... ...
@@ -388,644 +332,313 @@ inline uint16_t S9xGetWord (uint32_t Address, enum s9xwrap_t w = WRAP_NONE)
388 332
 			}
389 333
 
390 334
 			word  = S9xGetPPU(Address & 0xffff);
391
-			addCyclesInMemoryAccess;
335
+			addCyclesInMemoryAccess(speed);
392 336
 			word |= S9xGetPPU((Address + 1) & 0xffff) << 8;
393
-			addCyclesInMemoryAccess;
394
-			return (word);
337
+			addCyclesInMemoryAccess(speed);
338
+			return word;
395 339
 
396 340
 		case CMemory::MAP_LOROM_SRAM:
397 341
 		case CMemory::MAP_SA1RAM:
398 342
 			if (Memory.SRAMMask >= MEMMAP_MASK)
399
-				word = READ_WORD(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask));
343
+				word = READ_WORD(&Memory.SRAM[(((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask]);
400 344
 			else
401
-				word = (*(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask))) |
402
-					  ((*(Memory.SRAM + (((((Address + 1) & 0xff0000) >> 1) | ((Address + 1) & 0x7fff)) & Memory.SRAMMask))) << 8);
403
-			addCyclesInMemoryAccess_x2;
404
-			return word;
405
-
406
-		case CMemory::MAP_LOROM_SRAM_B:
407
-			if (Multi.sramMaskB >= MEMMAP_MASK)
408
-				word = READ_WORD(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB));
409
-			else
410
-				word = (*(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB))) |
411
-					  ((*(Multi.sramB + (((((Address + 1) & 0xff0000) >> 1) | ((Address + 1) & 0x7fff)) & Multi.sramMaskB))) << 8);
412
-			addCyclesInMemoryAccess_x2;
345
+				word = Memory.SRAM[(((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask] |
346
+					(Memory.SRAM[((((Address + 1) & 0xff0000) >> 1) | ((Address + 1) & 0x7fff)) & Memory.SRAMMask] << 8);
347
+			addCyclesInMemoryAccess_x2(speed);
413 348
 			return word;
414 349
 
415 350
 		case CMemory::MAP_HIROM_SRAM:
416 351
 		case CMemory::MAP_RONLY_SRAM:
417 352
 			if (Memory.SRAMMask >= MEMMAP_MASK)
418
-				word = READ_WORD(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask));
353
+				word = READ_WORD(&Memory.SRAM[((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask]);
419 354
 			else
420
-				word = (*(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask)) |
421
-					   (*(Memory.SRAM + ((((Address + 1) & 0x7fff) - 0x6000 + (((Address + 1) & 0xf0000) >> 3)) & Memory.SRAMMask)) << 8));
422
-			addCyclesInMemoryAccess_x2;
423
-			return word;
424
-
425
-		case CMemory::MAP_BWRAM:
426
-			word = READ_WORD(Memory.BWRAM + ((Address & 0x7fff) - 0x6000));
427
-			addCyclesInMemoryAccess_x2;
428
-			return word;
429
-
430
-		/*case CMemory::MAP_DSP:
431
-			word  = S9xGetDSP(Address & 0xffff);
432
-			addCyclesInMemoryAccess;
433
-			word |= S9xGetDSP((Address + 1) & 0xffff) << 8;
434
-			addCyclesInMemoryAccess;
435
-			return word;
436
-
437
-		case CMemory::MAP_SPC7110_ROM:
438
-			word  = S9xGetSPC7110Byte(Address);
439
-			addCyclesInMemoryAccess;
440
-			word |= S9xGetSPC7110Byte(Address + 1) << 8;
441
-			addCyclesInMemoryAccess;
355
+				word = Memory.SRAM[((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask] |
356
+					(Memory.SRAM[(((Address + 1) & 0x7fff) - 0x6000 + (((Address + 1) & 0xf0000) >> 3)) & Memory.SRAMMask] << 8);
357
+			addCyclesInMemoryAccess_x2(speed);
442 358
 			return word;
443 359
 
444
-		case CMemory::MAP_SPC7110_DRAM:
445
-			word  = S9xGetSPC7110(0x4800);
446
-			addCyclesInMemoryAccess;
447
-			word |= S9xGetSPC7110(0x4800) << 8;
448
-			addCyclesInMemoryAccess;
449
-			return word;
450
-
451
-		case CMemory::MAP_C4:
452
-			word  = S9xGetC4(Address & 0xffff);
453
-			addCyclesInMemoryAccess;
454
-			word |= S9xGetC4((Address + 1) & 0xffff) << 8;
455
-			addCyclesInMemoryAccess;
456
-			return word;
457
-
458
-		case CMemory::MAP_OBC_RAM:
459
-			word  = S9xGetOBC1(Address & 0xffff);
460
-			addCyclesInMemoryAccess;
461
-			word |= S9xGetOBC1((Address + 1) & 0xffff) << 8;
462
-			addCyclesInMemoryAccess;
463
-			return word;
464
-
465
-		case CMemory::MAP_SETA_DSP:
466
-			word  = S9xGetSetaDSP(Address);
467
-			addCyclesInMemoryAccess;
468
-			word |= S9xGetSetaDSP(Address + 1) << 8;
469
-			addCyclesInMemoryAccess;
470
-			return word;
471
-
472
-		case CMemory::MAP_SETA_RISC:
473
-			word  = S9xGetST018(Address);
474
-			addCyclesInMemoryAccess;
475
-			word |= S9xGetST018(Address + 1) << 8;
476
-			addCyclesInMemoryAccess;
477
-			return word;
478
-
479
-		case CMemory::MAP_BSX:
480
-			word  = S9xGetBSX(Address);
481
-			addCyclesInMemoryAccess;
482
-			word |= S9xGetBSX(Address + 1) << 8;
483
-			addCyclesInMemoryAccess;
484
-			return word;*/
485
-
486
-		case CMemory::MAP_NONE:
487 360
 		default:
488 361
 			word = OpenBus | (OpenBus << 8);
489
-			addCyclesInMemoryAccess_x2;
362
+			addCyclesInMemoryAccess_x2(speed);
490 363
 			return word;
491 364
 	}
492 365
 }
493 366
 
494
-inline void S9xSetByte (uint8_t Byte, uint32_t Address)
367
+inline void S9xSetByte(uint8_t Byte, uint32_t Address)
495 368
 {
496
-	int		block = (Address & 0xffffff) >> MEMMAP_SHIFT;
497
-	uint8_t	*SetAddress = Memory.WriteMap[block];
498
-	int32_t	speed = memory_speed(Address);
369
+	int block = (Address & 0xffffff) >> MEMMAP_SHIFT;
370
+	uint8_t *SetAddress = Memory.WriteMap[block];
371
+	int32_t speed = memory_speed(Address);
499 372
 
500
-	if (SetAddress >= (uint8_t *) CMemory::MAP_LAST)
373
+	if (SetAddress >= reinterpret_cast<uint8_t *>(CMemory::MAP_LAST))
501 374
 	{
502
-		*(SetAddress + (Address & 0xffff)) = Byte;
503
-		addCyclesInMemoryAccess;
375
+		SetAddress[Address & 0xffff] = Byte;
376
+		addCyclesInMemoryAccess(speed);
504 377
 		return;
505 378
 	}
506 379
 
507
-	switch ((intptr_t) SetAddress)
380
+	switch (reinterpret_cast<intptr_t>(SetAddress))
508 381
 	{
509 382
 		case CMemory::MAP_CPU:
510 383
 			S9xSetCPU(Byte, Address & 0xffff);
511
-			addCyclesInMemoryAccess;
512
-			return;
384
+			addCyclesInMemoryAccess(speed);
385
+			break;
513 386
 
514 387
 		case CMemory::MAP_PPU:
515 388
 			if (CPU.InDMAorHDMA && (Address & 0xff00) == 0x2100)
516 389
 				return;
517 390
 
518 391
 			S9xSetPPU(Byte, Address & 0xffff);
519
-			addCyclesInMemoryAccess;
520
-			return;
392
+			addCyclesInMemoryAccess(speed);
393
+			break;
521 394
 
522 395
 		case CMemory::MAP_LOROM_SRAM:
523 396
 			if (Memory.SRAMMask)
524
-			{
525
-				*(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask)) = Byte;
526
-				CPU.SRAMModified = true;
527
-			}
397
+				Memory.SRAM[(((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask] = Byte;
528 398
 
529
-			addCyclesInMemoryAccess;
530
-			return;
531
-
532
-		case CMemory::MAP_LOROM_SRAM_B:
533
-			if (Multi.sramMaskB)
534
-			{
535
-				*(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB)) = Byte;
536
-				CPU.SRAMModified = true;
537
-			}
538
-
539
-			addCyclesInMemoryAccess;
540
-			return;
399
+			addCyclesInMemoryAccess(speed);
400
+			break;
541 401
 
542 402
 		case CMemory::MAP_HIROM_SRAM:
543 403
 			if (Memory.SRAMMask)
544
-			{
545
-				*(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask)) = Byte;
546
-				CPU.SRAMModified = true;
547
-			}
548
-
549
-			addCyclesInMemoryAccess;
550
-			return;
404
+				Memory.SRAM[((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask] = Byte;
551 405
 
552
-		case CMemory::MAP_BWRAM:
553
-			*(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)) = Byte;
554
-			CPU.SRAMModified = true;
555
-			addCyclesInMemoryAccess;
556
-			return;
406
+			addCyclesInMemoryAccess(speed);
407
+			break;
557 408
 
558 409
 		case CMemory::MAP_SA1RAM:
559
-			*(Memory.SRAM + (Address & 0xffff)) = Byte;
560
-			addCyclesInMemoryAccess;
561
-			return;
562
-
563
-		/*case CMemory::MAP_DSP:
564
-			S9xSetDSP(Byte, Address & 0xffff);
565
-			addCyclesInMemoryAccess;
566
-			return;
567
-
568
-		case CMemory::MAP_C4:
569
-			S9xSetC4(Byte, Address & 0xffff);
570
-			addCyclesInMemoryAccess;
571
-			return;
572
-
573
-		case CMemory::MAP_OBC_RAM:
574
-			S9xSetOBC1(Byte, Address & 0xffff);
575
-			addCyclesInMemoryAccess;
576
-			return;
577
-
578
-		case CMemory::MAP_SETA_DSP:
579
-			S9xSetSetaDSP(Byte, Address);
580
-			addCyclesInMemoryAccess;
581
-			return;
582
-
583
-		case CMemory::MAP_SETA_RISC:
584
-			S9xSetST018(Byte, Address);
585
-			addCyclesInMemoryAccess;
586
-			return;
587
-
588
-		case CMemory::MAP_BSX:
589
-			S9xSetBSX(Byte, Address);
590
-			addCyclesInMemoryAccess;
591
-			return;*/
592
-
593
-		case CMemory::MAP_NONE:
410
+			Memory.SRAM[Address & 0xffff] = Byte;
411
+			addCyclesInMemoryAccess(speed);
412
+			break;
413
+
594 414
 		default:
595
-			addCyclesInMemoryAccess;
596
-			return;
415
+			addCyclesInMemoryAccess(speed);
597 416
 	}
598 417
 }
599 418
 
600
-inline void S9xSetWord (uint16_t Word, uint32_t Address, enum s9xwrap_t w = WRAP_NONE, enum s9xwriteorder_t o = WRITE_01)
419
+inline void S9xSetWord(uint16_t Word, uint32_t Address, s9xwrap_t w = WRAP_NONE, s9xwriteorder_t o = WRITE_01)
601 420
 {
602
-	uint32_t	mask = MEMMAP_MASK & (w == WRAP_PAGE ? 0xff : (w == WRAP_BANK ? 0xffff : 0xffffff));
421
+	uint32_t mask = MEMMAP_MASK & (w == WRAP_PAGE ? 0xff : (w == WRAP_BANK ? 0xffff : 0xffffff));
603 422
 	if ((Address & mask) == mask)
604 423
 	{
605
-		PC_t	a;
424
+		PC_t a;
606 425
 
607 426
 		if (!o)
608
-			S9xSetByte((uint8_t) Word, Address);
427
+			S9xSetByte(static_cast<uint8_t>(Word), Address);
609 428
 
610 429
 		switch (w)
611 430
 		{
612 431
 			case WRAP_PAGE:
613 432
 				a.xPBPC = Address;
614
-				a.B.xPCl++;
433
+				++a.B.xPCl;
615 434
 				S9xSetByte(Word >> 8, a.xPBPC);
616 435
 				break;
617 436
 
618 437
 			case WRAP_BANK:
619 438
 				a.xPBPC = Address;
620
-				a.W.xPC++;
439
+				++a.W.xPC;
621 440
 				S9xSetByte(Word >> 8, a.xPBPC);
622 441
 				break;
623 442
 
624
-			case WRAP_NONE:
625 443
 			default:
626 444
 				S9xSetByte(Word >> 8, Address + 1);
627
-				break;
628 445
 		}
629 446
 
630 447
 		if (o)
631
-			S9xSetByte((uint8_t) Word, Address);
448
+			S9xSetByte(static_cast<uint8_t>(Word), Address);
632 449
 
633 450
 		return;
634 451
 	}
635 452
 
636
-	int		block = (Address & 0xffffff) >> MEMMAP_SHIFT;
637
-	uint8_t	*SetAddress = Memory.WriteMap[block];
638
-	int32_t	speed = memory_speed(Address);
453
+	int block = (Address & 0xffffff) >> MEMMAP_SHIFT;
454
+	uint8_t *SetAddress = Memory.WriteMap[block];
455
+	int32_t speed = memory_speed(Address);
639 456
 
640
-	if (SetAddress >= (uint8_t *) CMemory::MAP_LAST)
457
+	if (SetAddress >= reinterpret_cast<uint8_t *>(CMemory::MAP_LAST))
641 458
 	{
642
-		WRITE_WORD(SetAddress + (Address & 0xffff), Word);
643
-		addCyclesInMemoryAccess_x2;
459
+		WRITE_WORD(&SetAddress[Address & 0xffff], Word);
460
+		addCyclesInMemoryAccess_x2(speed);
644 461
 		return;
645 462
 	}
646 463
 
647
-	switch ((intptr_t) SetAddress)
464
+	switch (reinterpret_cast<intptr_t>(SetAddress))
648 465
 	{
649 466
 		case CMemory::MAP_CPU:
650 467
 			if (o)
651 468
 			{
652 469
 				S9xSetCPU(Word >> 8, (Address + 1) & 0xffff);
653
-				addCyclesInMemoryAccess;
654
-				S9xSetCPU((uint8_t) Word, Address & 0xffff);
655
-				addCyclesInMemoryAccess;
656
-				return;
470
+				addCyclesInMemoryAccess(speed);
471
+				S9xSetCPU(static_cast<uint8_t>(Word), Address & 0xffff);
472
+				addCyclesInMemoryAccess(speed);
657 473
 			}
658 474
 			else
659 475
 			{
660
-				S9xSetCPU((uint8_t) Word, Address & 0xffff);
661
-				addCyclesInMemoryAccess;
476
+				S9xSetCPU(static_cast<uint8_t>(Word), Address & 0xffff);
477
+				addCyclesInMemoryAccess(speed);
662 478
 				S9xSetCPU(Word >> 8, (Address + 1) & 0xffff);
663
-				addCyclesInMemoryAccess;
664
-				return;
479
+				addCyclesInMemoryAccess(speed);
665 480
 			}
481
+			break;
666 482
 
667 483
 		case CMemory::MAP_PPU:
668 484
 			if (CPU.InDMAorHDMA)
669 485
 			{
670 486
 				if ((Address & 0xff00) != 0x2100)
671
-					S9xSetPPU((uint8_t) Word, Address & 0xffff);
487
+					S9xSetPPU(static_cast<uint8_t>(Word), Address & 0xffff);
672 488
 				if (((Address + 1) & 0xff00) != 0x2100)
673 489
 					S9xSetPPU(Word >> 8, (Address + 1) & 0xffff);
674
-				return;
490
+				break;
675 491
 			}
676 492
 
677 493
 			if (o)
678 494
 			{
679 495
 				S9xSetPPU(Word >> 8, (Address + 1) & 0xffff);
680
-				addCyclesInMemoryAccess;
681
-				S9xSetPPU((uint8_t) Word, Address & 0xffff);
682
-				addCyclesInMemoryAccess;
683
-				return;
496
+				addCyclesInMemoryAccess(speed);
497
+				S9xSetPPU(static_cast<uint8_t>(Word), Address & 0xffff);
498
+				addCyclesInMemoryAccess(speed);
684 499
 			}
685 500
 			else
686 501
 			{
687
-				S9xSetPPU((uint8_t) Word, Address & 0xffff);
688
-				addCyclesInMemoryAccess;
502
+				S9xSetPPU(static_cast<uint8_t>(Word), Address & 0xffff);
503
+				addCyclesInMemoryAccess(speed);
689 504
 				S9xSetPPU(Word >> 8, (Address + 1) & 0xffff);
690
-				addCyclesInMemoryAccess;
691
-				return;
505
+				addCyclesInMemoryAccess(speed);
692 506
 			}
507
+			break;
693 508
 
694 509
 		case CMemory::MAP_LOROM_SRAM:
695 510
 			if (Memory.SRAMMask)
696 511
 			{
697 512
 				if (Memory.SRAMMask >= MEMMAP_MASK)
698
-					WRITE_WORD(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask), Word);
699
-				else
700
-				{
701
-					*(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask)) = (uint8_t) Word;
702
-					*(Memory.SRAM + (((((Address + 1) & 0xff0000) >> 1) | ((Address + 1) & 0x7fff)) & Memory.SRAMMask)) = Word >> 8;
703
-				}
704
-
705
-				CPU.SRAMModified = true;
706
-			}
707
-
708
-			addCyclesInMemoryAccess_x2;
709
-			return;
710
-
711
-		case CMemory::MAP_LOROM_SRAM_B:
712
-			if (Multi.sramMaskB)
713
-			{
714
-				if (Multi.sramMaskB >= MEMMAP_MASK)
715
-					WRITE_WORD(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB), Word);
513
+					WRITE_WORD(&Memory.SRAM[(((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask], Word);
716 514
 				else
717 515
 				{
718
-					*(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB)) = (uint8_t) Word;
719
-					*(Multi.sramB + (((((Address + 1) & 0xff0000) >> 1) | ((Address + 1) & 0x7fff)) & Multi.sramMaskB)) = Word >> 8;
516
+					Memory.SRAM[(((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask] = static_cast<uint8_t>(Word);
517
+					Memory.SRAM[((((Address + 1) & 0xff0000) >> 1) | ((Address + 1) & 0x7fff)) & Memory.SRAMMask] = Word >> 8;
720 518
 				}
721
-
722
-				CPU.SRAMModified = true;
723 519
 			}
724 520
 
725
-			addCyclesInMemoryAccess_x2;
726
-			return;
521
+			addCyclesInMemoryAccess_x2(speed);
522
+			break;
727 523
 
728 524
 		case CMemory::MAP_HIROM_SRAM:
729 525
 			if (Memory.SRAMMask)
730 526
 			{
731 527
 				if (Memory.SRAMMask >= MEMMAP_MASK)
732
-					WRITE_WORD(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask), Word);
528
+					WRITE_WORD(&Memory.SRAM[((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask], Word);
733 529
 				else
734 530
 				{
735
-					*(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask)) = (uint8_t) Word;
736
-					*(Memory.SRAM + ((((Address + 1) & 0x7fff) - 0x6000 + (((Address + 1) & 0xf0000) >> 3)) & Memory.SRAMMask)) = Word >> 8;
531
+					Memory.SRAM[((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask] = static_cast<uint8_t>(Word);
532
+					Memory.SRAM[(((Address + 1) & 0x7fff) - 0x6000 + (((Address + 1) & 0xf0000) >> 3)) & Memory.SRAMMask] = Word >> 8;
737 533
 				}
738
-
739
-				CPU.SRAMModified = true;
740 534
 			}
741 535
 
742
-			addCyclesInMemoryAccess_x2;
743
-			return;
744
-
745
-		case CMemory::MAP_BWRAM:
746
-			WRITE_WORD(Memory.BWRAM + ((Address & 0x7fff) - 0x6000), Word);
747
-			CPU.SRAMModified = true;
748
-			addCyclesInMemoryAccess_x2;
749
-			return;
536
+			addCyclesInMemoryAccess_x2(speed);
537
+			break;
750 538
 
751 539
 		case CMemory::MAP_SA1RAM:
752
-			WRITE_WORD(Memory.SRAM + (Address & 0xffff), Word);
753
-			addCyclesInMemoryAccess_x2;
754
-			return;
540
+			WRITE_WORD(&Memory.SRAM[Address & 0xffff], Word);
541
+			addCyclesInMemoryAccess_x2(speed);
542
+			break;
755 543
 
756
-		/*case CMemory::MAP_DSP:
757
-			if (o)
758
-			{
759
-				S9xSetDSP(Word >> 8, (Address + 1) & 0xffff);
760
-				addCyclesInMemoryAccess;
761
-				S9xSetDSP((uint8_t) Word, Address & 0xffff);
762
-				addCyclesInMemoryAccess;
763
-				return;
764
-			}
765
-			else
766
-			{
767
-				S9xSetDSP((uint8_t) Word, Address & 0xffff);
768
-				addCyclesInMemoryAccess;
769
-				S9xSetDSP(Word >> 8, (Address + 1) & 0xffff);
770
-				addCyclesInMemoryAccess;
771
-				return;
772
-			}
773
-
774
-		case CMemory::MAP_C4:
775
-			if (o)
776
-			{
777
-				S9xSetC4(Word >> 8, (Address + 1) & 0xffff);
778
-				addCyclesInMemoryAccess;
779
-				S9xSetC4((uint8_t) Word, Address & 0xffff);
780
-				addCyclesInMemoryAccess;
781
-				return;
782
-			}
783
-			else
784
-			{
785
-				S9xSetC4((uint8_t) Word, Address & 0xffff);
786
-				addCyclesInMemoryAccess;
787
-				S9xSetC4(Word >> 8, (Address + 1) & 0xffff);
788
-				addCyclesInMemoryAccess;
789
-				return;
790
-			}
791
-
792
-		case CMemory::MAP_OBC_RAM:
793
-			if (o)
794
-			{
795
-				S9xSetOBC1(Word >> 8, (Address + 1) & 0xffff);
796
-				addCyclesInMemoryAccess;
797
-				S9xSetOBC1((uint8_t) Word, Address & 0xffff);
798
-				addCyclesInMemoryAccess;
799
-				return;
800
-			}
801
-			else
802
-			{
803
-				S9xSetOBC1((uint8_t) Word, Address & 0xffff);
804
-				addCyclesInMemoryAccess;
805
-				S9xSetOBC1(Word >> 8, (Address + 1) & 0xffff);
806
-				addCyclesInMemoryAccess;
807
-				return;
808
-			}
809
-
810
-		case CMemory::MAP_SETA_DSP:
811
-			if (o)
812
-			{
813
-				S9xSetSetaDSP(Word >> 8, Address + 1);
814
-				addCyclesInMemoryAccess;
815
-				S9xSetSetaDSP((uint8_t) Word, Address);
816
-				addCyclesInMemoryAccess;
817
-				return;
818
-			}
819
-			else
820
-			{
821
-				S9xSetSetaDSP((uint8_t) Word, Address);
822
-				addCyclesInMemoryAccess;
823
-				S9xSetSetaDSP(Word >> 8, Address + 1);
824
-				addCyclesInMemoryAccess;
825
-				return;
826
-			}
827
-
828
-		case CMemory::MAP_SETA_RISC:
829
-			if (o)
830
-			{
831
-				S9xSetST018(Word >> 8, Address + 1);
832
-				addCyclesInMemoryAccess;
833
-				S9xSetST018((uint8_t) Word, Address);
834
-				addCyclesInMemoryAccess;
835
-				return;
836
-			}
837
-			else
838
-			{
839
-				S9xSetST018((uint8_t) Word, Address);
840
-				addCyclesInMemoryAccess;
841
-				S9xSetST018(Word >> 8, Address + 1);
842
-				addCyclesInMemoryAccess;
843
-				return;
844
-			}
845
-
846
-		case CMemory::MAP_BSX:
847
-			if (o)
848
-			{
849
-				S9xSetBSX(Word >> 8, Address + 1);
850
-				addCyclesInMemoryAccess;
851
-				S9xSetBSX((uint8_t) Word, Address);
852
-				addCyclesInMemoryAccess;
853
-				return;
854
-			}
855
-			else
856
-			{
857
-				S9xSetBSX((uint8_t) Word, Address);
858
-				addCyclesInMemoryAccess;
859
-				S9xSetBSX(Word >> 8, Address + 1);
860
-				addCyclesInMemoryAccess;
861
-				return;
862
-			}*/
863
-
864
-		case CMemory::MAP_NONE:
865 544
 		default:
866
-			addCyclesInMemoryAccess_x2;
867
-			return;
545
+			addCyclesInMemoryAccess_x2(speed);
868 546
 	}
869 547
 }
870 548
 
871
-inline void S9xSetPCBase (uint32_t Address)
549
+inline void S9xSetPCBase(uint32_t Address)
872 550
 {
873
-	Registers.PBPC = Address & 0xffffff;
551
+	Registers.PC.xPBPC = Address & 0xffffff;
874 552
 	ICPU.ShiftedPB = Address & 0xff0000;
875 553
 
876
-	int		block;
877
-	uint8_t	*GetAddress = Memory.Map[block = ((Address & 0xffffff) >> MEMMAP_SHIFT)];
554
+	int block;
555
+	uint8_t *GetAddress = Memory.Map[block = ((Address & 0xffffff) >> MEMMAP_SHIFT)];
878 556
 
879 557
 	CPU.MemSpeed = memory_speed(Address);
880 558
 	CPU.MemSpeedx2 = CPU.MemSpeed << 1;
881 559
 
882
-	if (GetAddress >= (uint8_t *) CMemory::MAP_LAST)
560
+	if (GetAddress >= reinterpret_cast<uint8_t *>(CMemory::MAP_LAST))
883 561
 	{
884 562
 		CPU.PCBase = GetAddress;
885 563
 		return;
886 564
 	}
887 565
 
888
-	switch ((intptr_t) GetAddress)
566
+	switch (reinterpret_cast<intptr_t>(GetAddress))
889 567
 	{
890 568
 		case CMemory::MAP_LOROM_SRAM:
891 569
 			if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK)
892
-				CPU.PCBase = NULL;
893
-			else
894
-				CPU.PCBase = Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask) - (Address & 0xffff);
895
-			return;
896
-
897
-		case CMemory::MAP_LOROM_SRAM_B:
898
-			if ((Multi.sramMaskB & MEMMAP_MASK) != MEMMAP_MASK)
899
-				CPU.PCBase = NULL;
570
+				CPU.PCBase = nullptr;
900 571
 			else
901
-				CPU.PCBase = Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB) - (Address & 0xffff);
902
-			return;
572
+				CPU.PCBase = &Memory.SRAM[((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask) - (Address & 0xffff)];
573
+			break;
903 574
 
904 575
 		case CMemory::MAP_HIROM_SRAM:
905 576
 			if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK)
906
-				CPU.PCBase = NULL;
577
+				CPU.PCBase = nullptr;
907 578
 			else
908
-				CPU.PCBase = Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask) - (Address & 0xffff);
909
-			return;
910
-
911
-		case CMemory::MAP_BWRAM:
912
-			CPU.PCBase = Memory.BWRAM - 0x6000 - (Address & 0x8000);
913
-			return;
579
+				CPU.PCBase = &Memory.SRAM[(((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask) - (Address & 0xffff)];
580
+			break;
914 581
 
915 582
 		case CMemory::MAP_SA1RAM:
916
-			CPU.PCBase = Memory.SRAM;
917
-			return;
918
-
919
-		/*case CMemory::MAP_SPC7110_ROM:
920
-			CPU.PCBase = S9xGetBasePointerSPC7110(Address);
921
-			return;
583
+			CPU.PCBase = &Memory.SRAM[0];
584
+			break;
922 585
 
923
-		case CMemory::MAP_C4:
924
-			CPU.PCBase = S9xGetBasePointerC4(Address & 0xffff);
925
-			return;
926
-
927
-		case CMemory::MAP_OBC_RAM:
928
-			CPU.PCBase = S9xGetBasePointerOBC1(Address & 0xffff);
929
-			return;
930
-
931
-		case CMemory::MAP_BSX:
932
-			CPU.PCBase = S9xGetBasePointerBSX(Address);
933
-			return;*/
934
-
935
-		case CMemory::MAP_NONE:
936 586
 		default:
937
-			CPU.PCBase = NULL;
938
-			return;
587
+			CPU.PCBase = nullptr;
939 588
 	}
940 589
 }
941 590
 
942
-inline uint8_t * S9xGetBasePointer (uint32_t Address)
591
+inline uint8_t *S9xGetBasePointer(uint32_t Address)
943 592
 {
944
-	uint8_t	*GetAddress = Memory.Map[(Address & 0xffffff) >> MEMMAP_SHIFT];
593
+	uint8_t *GetAddress = Memory.Map[(Address & 0xffffff) >> MEMMAP_SHIFT];
945 594
 
946
-	if (GetAddress >= (uint8_t *) CMemory::MAP_LAST)
595
+	if (GetAddress >= reinterpret_cast<uint8_t *>(CMemory::MAP_LAST))
947 596
 		return GetAddress;
948 597
 
949
-	switch ((intptr_t) GetAddress)
598
+	switch (reinterpret_cast<intptr_t>(GetAddress))
950 599
 	{
951 600
 		case CMemory::MAP_LOROM_SRAM:
952 601
 			if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK)
953
-				return NULL;
954
-			return Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask) - (Address & 0xffff);
955
-
956
-		case CMemory::MAP_LOROM_SRAM_B:
957
-			if ((Multi.sramMaskB & MEMMAP_MASK) != MEMMAP_MASK)
958
-				return NULL;
959
-			return Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB) - (Address & 0xffff);
602
+				return nullptr;
603
+			return &Memory.SRAM[((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask) - (Address & 0xffff)];
960 604
 
961 605
 		case CMemory::MAP_HIROM_SRAM:
962 606
 			if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK)
963
-				return NULL;
964
-			return Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask) - (Address & 0xffff);
965
-
966
-		case CMemory::MAP_BWRAM:
967
-			return Memory.BWRAM - 0x6000 - (Address & 0x8000);
607
+				return nullptr;
608
+			return &Memory.SRAM[(((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask) - (Address & 0xffff)];
968 609
 
969 610
 		case CMemory::MAP_SA1RAM:
970
-			return Memory.SRAM;
971
-
972
-		/*case CMemory::MAP_SPC7110_ROM:
973
-			return S9xGetBasePointerSPC7110(Address);
974
-
975
-		case CMemory::MAP_C4:
976
-			return S9xGetBasePointerC4(Address & 0xffff);
611
+			return &Memory.SRAM[0];
977 612
 
978
-		case CMemory::MAP_OBC_RAM:
979
-			return S9xGetBasePointerOBC1(Address & 0xffff);*/
980
-
981
-		case CMemory::MAP_NONE:
982 613
 		default:
983
-			return NULL;
614
+			return nullptr;
984 615
 	}
985 616
 }
986 617
 
987
-inline uint8_t * S9xGetMemPointer (uint32_t Address)
618
+inline uint8_t *S9xGetMemPointer(uint32_t Address)
988 619
 {
989
-	uint8_t	*GetAddress = Memory.Map[(Address & 0xffffff) >> MEMMAP_SHIFT];
620
+	uint8_t *GetAddress = Memory.Map[(Address & 0xffffff) >> MEMMAP_SHIFT];
990 621
 
991
-	if (GetAddress >= (uint8_t *) CMemory::MAP_LAST)
992
-		return GetAddress + (Address & 0xffff);
622
+	if (GetAddress >= reinterpret_cast<uint8_t *>(CMemory::MAP_LAST))
623
+		return &GetAddress[Address & 0xffff];
993 624
 
994
-	switch ((intptr_t) GetAddress)
625
+	switch (reinterpret_cast<intptr_t>(GetAddress))
995 626
 	{
996 627
 		case CMemory::MAP_LOROM_SRAM:
997 628
 			if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK)
998
-				return NULL;
999
-			return Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask);
1000
-
1001
-		case CMemory::MAP_LOROM_SRAM_B:
1002
-			if ((Multi.sramMaskB & MEMMAP_MASK) != MEMMAP_MASK)
1003
-				return NULL;
1004
-			return Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB);
629
+				return nullptr;
630
+			return &Memory.SRAM[(((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask];
1005 631
 
1006 632
 		case CMemory::MAP_HIROM_SRAM:
1007 633
 			if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK)
1008
-				return NULL;
1009
-			return Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask);
1010
-
1011
-		case CMemory::MAP_BWRAM:
1012
-			return Memory.BWRAM - 0x6000 + (Address & 0x7fff);
634
+				return nullptr;
635
+			return &Memory.SRAM[((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask];
1013 636
 
1014 637
 		case CMemory::MAP_SA1RAM:
1015
-			return Memory.SRAM + (Address & 0xffff);
1016
-
1017
-		/*case CMemory::MAP_SPC7110_ROM:
1018
-			return S9xGetBasePointerSPC7110(Address) + (Address & 0xffff);
1019
-
1020
-		case CMemory::MAP_C4:
1021
-			return S9xGetMemPointerC4(Address & 0xffff);
1022
-
1023
-		case CMemory::MAP_OBC_RAM:
1024
-			return S9xGetMemPointerOBC1(Address & 0xffff);*/
638
+			return &Memory.SRAM[Address & 0xffff];
1025 639
 
1026
-		case CMemory::MAP_NONE:
1027 640
 		default:
1028
-			return NULL;
641
+			return nullptr;
1029 642
 	}
1030 643
 }
1031 644
 
Browse code

Import actual code.

Naram Qashat authored on 2013/03/26 02:41:19
Showing 1 changed files
1 1
new file mode 100644
... ...
@@ -0,0 +1,1032 @@
1
+/***********************************************************************************
2
+  Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
3
+
4
+  (c) Copyright 1996 - 2002  Gary Henderson (gary.henderson@ntlworld.com),
5
+                             Jerremy Koot (jkoot@snes9x.com)
6
+
7
+  (c) Copyright 2002 - 2004  Matthew Kendora
8
+
9
+  (c) Copyright 2002 - 2005  Peter Bortas (peter@bortas.org)
10
+
11
+  (c) Copyright 2004 - 2005  Joel Yliluoma (http://iki.fi/bisqwit/)
12
+
13
+  (c) Copyright 2001 - 2006  John Weidman (jweidman@slip.net)
14
+
15
+  (c) Copyright 2002 - 2006  funkyass (funkyass@spam.shaw.ca),
16
+                             Kris Bleakley (codeviolation@hotmail.com)
17
+
18
+  (c) Copyright 2002 - 2010  Brad Jorsch (anomie@users.sourceforge.net),
19
+                             Nach (n-a-c-h@users.sourceforge.net),
20
+
21
+  (c) Copyright 2002 - 2011  zones (kasumitokoduck@yahoo.com)
22
+
23
+  (c) Copyright 2006 - 2007  nitsuja
24
+
25
+  (c) Copyright 2009 - 2011  BearOso,
26
+                             OV2
27
+
28
+
29
+  BS-X C emulator code
30
+  (c) Copyright 2005 - 2006  Dreamer Nom,
31
+                             zones
32
+
33
+  C4 x86 assembler and some C emulation code
34
+  (c) Copyright 2000 - 2003  _Demo_ (_demo_@zsnes.com),
35
+                             Nach,
36
+                             zsKnight (zsknight@zsnes.com)
37
+
38
+  C4 C++ code
39
+  (c) Copyright 2003 - 2006  Brad Jorsch,
40
+                             Nach
41
+
42
+  DSP-1 emulator code
43
+  (c) Copyright 1998 - 2006  _Demo_,
44
+                             Andreas Naive (andreasnaive@gmail.com),
45
+                             Gary Henderson,
46
+                             Ivar (ivar@snes9x.com),
47
+                             John Weidman,
48
+                             Kris Bleakley,
49
+                             Matthew Kendora,
50
+                             Nach,
51
+                             neviksti (neviksti@hotmail.com)
52
+
53
+  DSP-2 emulator code
54
+  (c) Copyright 2003         John Weidman,
55
+                             Kris Bleakley,
56
+                             Lord Nightmare (lord_nightmare@users.sourceforge.net),
57
+                             Matthew Kendora,
58
+                             neviksti
59
+
60
+  DSP-3 emulator code
61
+  (c) Copyright 2003 - 2006  John Weidman,
62
+                             Kris Bleakley,
63
+                             Lancer,
64
+                             z80 gaiden
65
+
66
+  DSP-4 emulator code
67
+  (c) Copyright 2004 - 2006  Dreamer Nom,
68
+                             John Weidman,
69
+                             Kris Bleakley,
70
+                             Nach,
71
+                             z80 gaiden
72
+
73
+  OBC1 emulator code
74
+  (c) Copyright 2001 - 2004  zsKnight,
75
+                             pagefault (pagefault@zsnes.com),
76
+                             Kris Bleakley
77
+                             Ported from x86 assembler to C by sanmaiwashi
78
+
79
+  SPC7110 and RTC C++ emulator code used in 1.39-1.51
80
+  (c) Copyright 2002         Matthew Kendora with research by
81
+                             zsKnight,
82
+                             John Weidman,
83
+                             Dark Force
84
+
85
+  SPC7110 and RTC C++ emulator code used in 1.52+
86
+  (c) Copyright 2009         byuu,
87
+                             neviksti
88
+
89
+  S-DD1 C emulator code
90
+  (c) Copyright 2003         Brad Jorsch with research by
91
+                             Andreas Naive,
92
+                             John Weidman
93
+
94
+  S-RTC C emulator code
95
+  (c) Copyright 2001 - 2006  byuu,
96
+                             John Weidman
97
+
98
+  ST010 C++ emulator code
99
+  (c) Copyright 2003         Feather,
100
+                             John Weidman,
101
+                             Kris Bleakley,
102
+                             Matthew Kendora
103
+
104
+  Super FX x86 assembler emulator code
105
+  (c) Copyright 1998 - 2003  _Demo_,
106
+                             pagefault,
107
+                             zsKnight
108
+
109
+  Super FX C emulator code
110
+  (c) Copyright 1997 - 1999  Ivar,
111
+                             Gary Henderson,
112
+                             John Weidman
113
+
114
+  Sound emulator code used in 1.5-1.51
115
+  (c) Copyright 1998 - 2003  Brad Martin
116
+  (c) Copyright 1998 - 2006  Charles Bilyue'
117
+
118
+  Sound emulator code used in 1.52+
119
+  (c) Copyright 2004 - 2007  Shay Green (gblargg@gmail.com)
120
+
121
+  SH assembler code partly based on x86 assembler code
122
+  (c) Copyright 2002 - 2004  Marcus Comstedt (marcus@mc.pp.se)
123
+
124
+  2xSaI filter
125
+  (c) Copyright 1999 - 2001  Derek Liauw Kie Fa
126
+
127
+  HQ2x, HQ3x, HQ4x filters
128
+  (c) Copyright 2003         Maxim Stepin (maxim@hiend3d.com)
129
+
130
+  NTSC filter
131
+  (c) Copyright 2006 - 2007  Shay Green
132
+
133
+  GTK+ GUI code
134
+  (c) Copyright 2004 - 2011  BearOso
135
+
136
+  Win32 GUI code
137
+  (c) Copyright 2003 - 2006  blip,
138
+                             funkyass,
139
+                             Matthew Kendora,
140
+                             Nach,
141
+                             nitsuja
142
+  (c) Copyright 2009 - 2011  OV2
143
+
144
+  Mac OS GUI code
145
+  (c) Copyright 1998 - 2001  John Stiles
146
+  (c) Copyright 2001 - 2011  zones
147
+
148
+
149
+  Specific ports contains the works of other authors. See headers in
150
+  individual files.
151
+
152
+
153
+  Snes9x homepage: http://www.snes9x.com/
154
+
155
+  Permission to use, copy, modify and/or distribute Snes9x in both binary
156
+  and source form, for non-commercial purposes, is hereby granted without
157
+  fee, providing that this license information and copyright notice appear
158
+  with all copies and any derived work.
159
+
160
+  This software is provided 'as-is', without any express or implied
161
+  warranty. In no event shall the authors be held liable for any damages
162
+  arising from the use of this software or it's derivatives.
163
+
164
+  Snes9x is freeware for PERSONAL USE only. Commercial users should
165
+  seek permission of the copyright holders first. Commercial use includes,
166
+  but is not limited to, charging money for Snes9x or software derived from
167
+  Snes9x, including Snes9x or derivatives in commercial game bundles, and/or
168
+  using Snes9x as a promotion for your commercial product.
169
+
170
+  The copyright holders request that bug fixes and improvements to the code
171
+  should be forwarded to them so everyone can benefit from the modifications
172
+  in future versions.
173
+
174
+  Super NES and Super Nintendo Entertainment System are trademarks of
175
+  Nintendo Co., Limited and its subsidiary companies.
176
+ ***********************************************************************************/
177
+
178
+
179
+#ifndef _GETSET_H_
180
+#define _GETSET_H_
181
+
182
+#include "cpuexec.h"
183
+//#include "dsp.h"
184
+//#include "sa1.h"
185
+//#include "spc7110.h"
186
+//#include "c4.h"
187
+//#include "obc1.h"
188
+//#include "seta.h"
189
+//#include "bsx.h"
190
+
191
+#define addCyclesInMemoryAccess \
192
+	if (!CPU.InDMAorHDMA) \
193
+	{ \
194
+		CPU.PrevCycles = CPU.Cycles; \
195
+		CPU.Cycles += speed; \
196
+		S9xCheckInterrupts(); \
197
+		while (CPU.Cycles >= CPU.NextEvent) \
198
+			S9xDoHEventProcessing(); \
199
+	}
200
+
201
+#define addCyclesInMemoryAccess_x2 \
202
+	if (!CPU.InDMAorHDMA) \
203
+	{ \
204
+		CPU.PrevCycles = CPU.Cycles; \
205
+		CPU.Cycles += speed << 1; \
206
+		S9xCheckInterrupts(); \
207
+		while (CPU.Cycles >= CPU.NextEvent) \
208
+			S9xDoHEventProcessing(); \
209
+	}
210
+
211
+extern uint8_t	OpenBus;
212
+
213
+static inline int32_t memory_speed (uint32_t address)
214
+{
215
+	if (address & 0x408000)
216
+	{
217
+		if (address & 0x800000)
218
+			return CPU.FastROMSpeed;
219
+
220
+		return SLOW_ONE_CYCLE;
221
+	}
222
+
223
+	if ((address + 0x6000) & 0x4000)
224
+		return SLOW_ONE_CYCLE;
225
+
226
+	if ((address - 0x4000) & 0x7e00)
227
+		return ONE_CYCLE;
228
+
229
+	return TWO_CYCLES;
230
+}
231
+
232
+inline uint8_t S9xGetByte (uint32_t Address)
233
+{
234
+	int		block = (Address & 0xffffff) >> MEMMAP_SHIFT;
235
+	uint8_t	*GetAddress = Memory.Map[block];
236
+	int32_t	speed = memory_speed(Address);
237
+	uint8_t	byte;
238
+
239
+	if (GetAddress >= (uint8_t *) CMemory::MAP_LAST)
240
+	{
241
+		byte = *(GetAddress + (Address & 0xffff));
242
+		addCyclesInMemoryAccess;
243
+		return byte;
244
+	}
245
+
246
+	switch ((intptr_t) GetAddress)
247
+	{
248
+		case CMemory::MAP_CPU:
249
+			byte = S9xGetCPU(Address & 0xffff);
250
+			addCyclesInMemoryAccess;
251
+			return byte;
252
+
253
+		case CMemory::MAP_PPU:
254
+			if (CPU.InDMAorHDMA && (Address & 0xff00) == 0x2100)
255
+				return OpenBus;
256
+
257
+			byte = S9xGetPPU(Address & 0xffff);
258
+			addCyclesInMemoryAccess;
259
+			return byte;
260
+
261
+		case CMemory::MAP_LOROM_SRAM:
262
+		case CMemory::MAP_SA1RAM:
263
+			// Address & 0x7fff   : offset into bank
264
+			// Address & 0xff0000 : bank
265
+			// bank >> 1 | offset : SRAM address, unbound
266
+			// unbound & SRAMMask : SRAM offset
267
+			byte = *(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask));
268
+			addCyclesInMemoryAccess;
269
+			return byte;
270
+
271
+		case CMemory::MAP_LOROM_SRAM_B:
272
+			byte = *(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB));
273
+			addCyclesInMemoryAccess;
274
+			return byte;
275
+
276
+		case CMemory::MAP_HIROM_SRAM:
277
+		case CMemory::MAP_RONLY_SRAM:
278
+			byte = *(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask));
279
+			addCyclesInMemoryAccess;
280
+			return byte;
281
+
282
+		case CMemory::MAP_BWRAM:
283
+			byte = *(Memory.BWRAM + ((Address & 0x7fff) - 0x6000));
284
+			addCyclesInMemoryAccess;
285
+			return byte;
286
+
287
+		/*case CMemory::MAP_DSP:
288
+			byte = S9xGetDSP(Address & 0xffff);
289
+			addCyclesInMemoryAccess;
290
+			return byte;
291
+
292
+		case CMemory::MAP_SPC7110_ROM:
293
+			byte = S9xGetSPC7110Byte(Address);
294
+			addCyclesInMemoryAccess;
295
+			return byte;
296
+
297
+		case CMemory::MAP_SPC7110_DRAM:
298
+			byte = S9xGetSPC7110(0x4800);
299
+			addCyclesInMemoryAccess;
300
+			return byte;
301
+
302
+		case CMemory::MAP_C4:
303
+			byte = S9xGetC4(Address & 0xffff);
304
+			addCyclesInMemoryAccess;
305
+			return byte;
306
+
307
+		case CMemory::MAP_OBC_RAM:
308
+			byte = S9xGetOBC1(Address & 0xffff);
309
+			addCyclesInMemoryAccess;
310
+			return byte;
311
+
312
+		case CMemory::MAP_SETA_DSP:
313
+			byte = S9xGetSetaDSP(Address);
314
+			addCyclesInMemoryAccess;
315
+			return byte;
316
+
317
+		case CMemory::MAP_SETA_RISC:
318
+			byte = S9xGetST018(Address);
319
+			addCyclesInMemoryAccess;
320
+			return byte;
321
+
322
+		case CMemory::MAP_BSX:
323
+			byte = S9xGetBSX(Address);
324
+			addCyclesInMemoryAccess;
325
+			return byte;*/
326
+
327
+		case CMemory::MAP_NONE:
328
+		default:
329
+			byte = OpenBus;
330
+			addCyclesInMemoryAccess;
331
+			return byte;
332
+	}
333
+}
334
+
335
+inline uint16_t S9xGetWord (uint32_t Address, enum s9xwrap_t w = WRAP_NONE)
336
+{
337
+	uint32_t	mask = MEMMAP_MASK & (w == WRAP_PAGE ? 0xff : (w == WRAP_BANK ? 0xffff : 0xffffff));
338
+	if ((Address & mask) == mask)
339
+	{
340
+		PC_t	a;
341
+
342
+		OpenBus = S9xGetByte(Address);
343
+
344
+		switch (w)
345
+		{
346
+			case WRAP_PAGE:
347
+				a.xPBPC = Address;
348
+				a.B.xPCl++;
349
+				return OpenBus | (S9xGetByte(a.xPBPC) << 8);
350
+
351
+			case WRAP_BANK:
352
+				a.xPBPC = Address;
353
+				a.W.xPC++;
354
+				return OpenBus | (S9xGetByte(a.xPBPC) << 8);
355
+
356
+			case WRAP_NONE:
357
+			default:
358
+				return OpenBus | (S9xGetByte(Address + 1) << 8);
359
+		}
360
+	}
361
+
362
+	int		block = (Address & 0xffffff) >> MEMMAP_SHIFT;
363
+	uint8_t	*GetAddress = Memory.Map[block];
364
+	int32_t	speed = memory_speed(Address);
365
+	uint16_t	word;
366
+
367
+	if (GetAddress >= (uint8_t *) CMemory::MAP_LAST)
368
+	{
369
+		word = READ_WORD(GetAddress + (Address & 0xffff));
370
+		addCyclesInMemoryAccess_x2;
371
+		return word;
372
+	}
373
+
374
+	switch ((intptr_t) GetAddress)
375
+	{
376
+		case CMemory::MAP_CPU:
377
+			word  = S9xGetCPU(Address & 0xffff);
378
+			addCyclesInMemoryAccess;
379
+			word |= S9xGetCPU((Address + 1) & 0xffff) << 8;
380
+			addCyclesInMemoryAccess;
381
+			return word;
382
+
383
+		case CMemory::MAP_PPU:
384
+			if (CPU.InDMAorHDMA)
385
+			{
386
+				OpenBus = S9xGetByte(Address);
387
+				return OpenBus | (S9xGetByte(Address + 1) << 8);
388
+			}
389
+
390
+			word  = S9xGetPPU(Address & 0xffff);
391
+			addCyclesInMemoryAccess;
392
+			word |= S9xGetPPU((Address + 1) & 0xffff) << 8;
393
+			addCyclesInMemoryAccess;
394
+			return (word);
395
+
396
+		case CMemory::MAP_LOROM_SRAM:
397
+		case CMemory::MAP_SA1RAM:
398
+			if (Memory.SRAMMask >= MEMMAP_MASK)
399
+				word = READ_WORD(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask));
400
+			else
401
+				word = (*(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask))) |
402
+					  ((*(Memory.SRAM + (((((Address + 1) & 0xff0000) >> 1) | ((Address + 1) & 0x7fff)) & Memory.SRAMMask))) << 8);
403
+			addCyclesInMemoryAccess_x2;
404
+			return word;
405
+
406
+		case CMemory::MAP_LOROM_SRAM_B:
407
+			if (Multi.sramMaskB >= MEMMAP_MASK)
408
+				word = READ_WORD(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB));
409
+			else
410
+				word = (*(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB))) |
411
+					  ((*(Multi.sramB + (((((Address + 1) & 0xff0000) >> 1) | ((Address + 1) & 0x7fff)) & Multi.sramMaskB))) << 8);
412
+			addCyclesInMemoryAccess_x2;
413
+			return word;
414
+
415
+		case CMemory::MAP_HIROM_SRAM:
416
+		case CMemory::MAP_RONLY_SRAM:
417
+			if (Memory.SRAMMask >= MEMMAP_MASK)
418
+				word = READ_WORD(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask));
419
+			else
420
+				word = (*(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask)) |
421
+					   (*(Memory.SRAM + ((((Address + 1) & 0x7fff) - 0x6000 + (((Address + 1) & 0xf0000) >> 3)) & Memory.SRAMMask)) << 8));
422
+			addCyclesInMemoryAccess_x2;
423
+			return word;
424
+
425
+		case CMemory::MAP_BWRAM:
426
+			word = READ_WORD(Memory.BWRAM + ((Address & 0x7fff) - 0x6000));
427
+			addCyclesInMemoryAccess_x2;
428
+			return word;
429
+
430
+		/*case CMemory::MAP_DSP:
431
+			word  = S9xGetDSP(Address & 0xffff);
432
+			addCyclesInMemoryAccess;
433
+			word |= S9xGetDSP((Address + 1) & 0xffff) << 8;
434
+			addCyclesInMemoryAccess;
435
+			return word;
436
+
437
+		case CMemory::MAP_SPC7110_ROM:
438
+			word  = S9xGetSPC7110Byte(Address);
439
+			addCyclesInMemoryAccess;
440
+			word |= S9xGetSPC7110Byte(Address + 1) << 8;
441
+			addCyclesInMemoryAccess;
442
+			return word;
443
+
444
+		case CMemory::MAP_SPC7110_DRAM:
445
+			word  = S9xGetSPC7110(0x4800);
446
+			addCyclesInMemoryAccess;
447
+			word |= S9xGetSPC7110(0x4800) << 8;
448
+			addCyclesInMemoryAccess;
449
+			return word;
450
+
451
+		case CMemory::MAP_C4:
452
+			word  = S9xGetC4(Address & 0xffff);
453
+			addCyclesInMemoryAccess;
454
+			word |= S9xGetC4((Address + 1) & 0xffff) << 8;
455
+			addCyclesInMemoryAccess;
456
+			return word;
457
+
458
+		case CMemory::MAP_OBC_RAM:
459
+			word  = S9xGetOBC1(Address & 0xffff);
460
+			addCyclesInMemoryAccess;
461
+			word |= S9xGetOBC1((Address + 1) & 0xffff) << 8;
462
+			addCyclesInMemoryAccess;
463
+			return word;
464
+
465
+		case CMemory::MAP_SETA_DSP:
466
+			word  = S9xGetSetaDSP(Address);
467
+			addCyclesInMemoryAccess;
468
+			word |= S9xGetSetaDSP(Address + 1) << 8;
469
+			addCyclesInMemoryAccess;
470
+			return word;
471
+
472
+		case CMemory::MAP_SETA_RISC:
473
+			word  = S9xGetST018(Address);
474
+			addCyclesInMemoryAccess;
475
+			word |= S9xGetST018(Address + 1) << 8;
476
+			addCyclesInMemoryAccess;
477
+			return word;
478
+
479
+		case CMemory::MAP_BSX:
480
+			word  = S9xGetBSX(Address);
481
+			addCyclesInMemoryAccess;
482
+			word |= S9xGetBSX(Address + 1) << 8;
483
+			addCyclesInMemoryAccess;
484
+			return word;*/
485
+
486
+		case CMemory::MAP_NONE:
487
+		default:
488
+			word = OpenBus | (OpenBus << 8);
489
+			addCyclesInMemoryAccess_x2;
490
+			return word;
491
+	}
492
+}
493
+
494
+inline void S9xSetByte (uint8_t Byte, uint32_t Address)
495
+{
496
+	int		block = (Address & 0xffffff) >> MEMMAP_SHIFT;
497
+	uint8_t	*SetAddress = Memory.WriteMap[block];
498
+	int32_t	speed = memory_speed(Address);
499
+
500
+	if (SetAddress >= (uint8_t *) CMemory::MAP_LAST)
501
+	{
502
+		*(SetAddress + (Address & 0xffff)) = Byte;
503
+		addCyclesInMemoryAccess;
504
+		return;
505
+	}
506
+
507
+	switch ((intptr_t) SetAddress)
508
+	{
509
+		case CMemory::MAP_CPU:
510
+			S9xSetCPU(Byte, Address & 0xffff);
511
+			addCyclesInMemoryAccess;
512
+			return;
513
+
514
+		case CMemory::MAP_PPU:
515
+			if (CPU.InDMAorHDMA && (Address & 0xff00) == 0x2100)
516
+				return;
517
+
518
+			S9xSetPPU(Byte, Address & 0xffff);
519
+			addCyclesInMemoryAccess;
520
+			return;
521
+
522
+		case CMemory::MAP_LOROM_SRAM:
523
+			if (Memory.SRAMMask)
524
+			{
525
+				*(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask)) = Byte;
526
+				CPU.SRAMModified = true;
527
+			}
528
+
529
+			addCyclesInMemoryAccess;
530
+			return;
531
+
532
+		case CMemory::MAP_LOROM_SRAM_B:
533
+			if (Multi.sramMaskB)
534
+			{
535
+				*(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB)) = Byte;
536
+				CPU.SRAMModified = true;
537
+			}
538
+
539
+			addCyclesInMemoryAccess;
540
+			return;
541
+
542
+		case CMemory::MAP_HIROM_SRAM:
543
+			if (Memory.SRAMMask)
544
+			{
545
+				*(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask)) = Byte;
546
+				CPU.SRAMModified = true;
547
+			}
548
+
549
+			addCyclesInMemoryAccess;
550
+			return;
551
+
552
+		case CMemory::MAP_BWRAM:
553
+			*(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)) = Byte;
554
+			CPU.SRAMModified = true;
555
+			addCyclesInMemoryAccess;
556
+			return;
557
+
558
+		case CMemory::MAP_SA1RAM:
559
+			*(Memory.SRAM + (Address & 0xffff)) = Byte;
560
+			addCyclesInMemoryAccess;
561
+			return;
562
+
563
+		/*case CMemory::MAP_DSP:
564
+			S9xSetDSP(Byte, Address & 0xffff);
565
+			addCyclesInMemoryAccess;
566
+			return;
567
+
568
+		case CMemory::MAP_C4:
569
+			S9xSetC4(Byte, Address & 0xffff);
570
+			addCyclesInMemoryAccess;
571
+			return;
572
+
573
+		case CMemory::MAP_OBC_RAM:
574
+			S9xSetOBC1(Byte, Address & 0xffff);
575
+			addCyclesInMemoryAccess;
576
+			return;
577
+
578
+		case CMemory::MAP_SETA_DSP:
579
+			S9xSetSetaDSP(Byte, Address);
580
+			addCyclesInMemoryAccess;
581
+			return;
582
+
583
+		case CMemory::MAP_SETA_RISC:
584
+			S9xSetST018(Byte, Address);
585
+			addCyclesInMemoryAccess;
586
+			return;
587
+
588
+		case CMemory::MAP_BSX:
589
+			S9xSetBSX(Byte, Address);
590
+			addCyclesInMemoryAccess;
591
+			return;*/
592
+
593
+		case CMemory::MAP_NONE:
594
+		default:
595
+			addCyclesInMemoryAccess;
596
+			return;
597
+	}
598
+}
599
+
600
+inline void S9xSetWord (uint16_t Word, uint32_t Address, enum s9xwrap_t w = WRAP_NONE, enum s9xwriteorder_t o = WRITE_01)
601
+{
602
+	uint32_t	mask = MEMMAP_MASK & (w == WRAP_PAGE ? 0xff : (w == WRAP_BANK ? 0xffff : 0xffffff));
603
+	if ((Address & mask) == mask)
604
+	{
605
+		PC_t	a;
606
+
607
+		if (!o)
608
+			S9xSetByte((uint8_t) Word, Address);
609
+
610
+		switch (w)
611
+		{
612
+			case WRAP_PAGE:
613
+				a.xPBPC = Address;
614
+				a.B.xPCl++;
615
+				S9xSetByte(Word >> 8, a.xPBPC);
616
+				break;
617
+
618
+			case WRAP_BANK:
619
+				a.xPBPC = Address;
620
+				a.W.xPC++;
621
+				S9xSetByte(Word >> 8, a.xPBPC);
622
+				break;
623
+
624
+			case WRAP_NONE:
625
+			default:
626
+				S9xSetByte(Word >> 8, Address + 1);
627
+				break;
628
+		}
629
+
630
+		if (o)
631
+			S9xSetByte((uint8_t) Word, Address);
632
+
633
+		return;
634
+	}
635
+
636
+	int		block = (Address & 0xffffff) >> MEMMAP_SHIFT;
637
+	uint8_t	*SetAddress = Memory.WriteMap[block];
638
+	int32_t	speed = memory_speed(Address);
639
+
640
+	if (SetAddress >= (uint8_t *) CMemory::MAP_LAST)
641
+	{
642
+		WRITE_WORD(SetAddress + (Address & 0xffff), Word);
643
+		addCyclesInMemoryAccess_x2;
644
+		return;
645
+	}
646
+
647
+	switch ((intptr_t) SetAddress)
648
+	{
649
+		case CMemory::MAP_CPU:
650
+			if (o)
651
+			{
652
+				S9xSetCPU(Word >> 8, (Address + 1) & 0xffff);
653
+				addCyclesInMemoryAccess;
654
+				S9xSetCPU((uint8_t) Word, Address & 0xffff);
655
+				addCyclesInMemoryAccess;
656
+				return;
657
+			}
658
+			else
659
+			{
660
+				S9xSetCPU((uint8_t) Word, Address & 0xffff);
661
+				addCyclesInMemoryAccess;
662
+				S9xSetCPU(Word >> 8, (Address + 1) & 0xffff);
663
+				addCyclesInMemoryAccess;
664
+				return;
665
+			}
666
+
667
+		case CMemory::MAP_PPU:
668
+			if (CPU.InDMAorHDMA)
669
+			{
670
+				if ((Address & 0xff00) != 0x2100)
671
+					S9xSetPPU((uint8_t) Word, Address & 0xffff);
672
+				if (((Address + 1) & 0xff00) != 0x2100)
673
+					S9xSetPPU(Word >> 8, (Address + 1) & 0xffff);
674
+				return;
675
+			}
676
+
677
+			if (o)
678
+			{
679
+				S9xSetPPU(Word >> 8, (Address + 1) & 0xffff);
680
+				addCyclesInMemoryAccess;
681
+				S9xSetPPU((uint8_t) Word, Address & 0xffff);
682
+				addCyclesInMemoryAccess;
683
+				return;
684
+			}
685
+			else
686
+			{
687
+				S9xSetPPU((uint8_t) Word, Address & 0xffff);
688
+				addCyclesInMemoryAccess;
689
+				S9xSetPPU(Word >> 8, (Address + 1) & 0xffff);
690
+				addCyclesInMemoryAccess;
691
+				return;
692
+			}
693
+
694
+		case CMemory::MAP_LOROM_SRAM:
695
+			if (Memory.SRAMMask)
696
+			{
697
+				if (Memory.SRAMMask >= MEMMAP_MASK)
698
+					WRITE_WORD(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask), Word);
699
+				else
700
+				{
701
+					*(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask)) = (uint8_t) Word;
702
+					*(Memory.SRAM + (((((Address + 1) & 0xff0000) >> 1) | ((Address + 1) & 0x7fff)) & Memory.SRAMMask)) = Word >> 8;
703
+				}
704
+
705
+				CPU.SRAMModified = true;
706
+			}
707
+
708
+			addCyclesInMemoryAccess_x2;
709
+			return;
710
+
711
+		case CMemory::MAP_LOROM_SRAM_B:
712
+			if (Multi.sramMaskB)
713
+			{
714
+				if (Multi.sramMaskB >= MEMMAP_MASK)
715
+					WRITE_WORD(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB), Word);
716
+				else
717
+				{
718
+					*(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB)) = (uint8_t) Word;
719
+					*(Multi.sramB + (((((Address + 1) & 0xff0000) >> 1) | ((Address + 1) & 0x7fff)) & Multi.sramMaskB)) = Word >> 8;
720
+				}
721
+
722
+				CPU.SRAMModified = true;
723
+			}
724
+
725
+			addCyclesInMemoryAccess_x2;
726
+			return;
727
+
728
+		case CMemory::MAP_HIROM_SRAM:
729
+			if (Memory.SRAMMask)
730
+			{
731
+				if (Memory.SRAMMask >= MEMMAP_MASK)
732
+					WRITE_WORD(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask), Word);
733
+				else
734
+				{
735
+					*(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask)) = (uint8_t) Word;
736
+					*(Memory.SRAM + ((((Address + 1) & 0x7fff) - 0x6000 + (((Address + 1) & 0xf0000) >> 3)) & Memory.SRAMMask)) = Word >> 8;
737
+				}
738
+
739
+				CPU.SRAMModified = true;
740
+			}
741
+
742
+			addCyclesInMemoryAccess_x2;
743
+			return;
744
+
745
+		case CMemory::MAP_BWRAM:
746
+			WRITE_WORD(Memory.BWRAM + ((Address & 0x7fff) - 0x6000), Word);
747
+			CPU.SRAMModified = true;
748
+			addCyclesInMemoryAccess_x2;
749
+			return;
750
+
751
+		case CMemory::MAP_SA1RAM:
752
+			WRITE_WORD(Memory.SRAM + (Address & 0xffff), Word);
753
+			addCyclesInMemoryAccess_x2;
754
+			return;
755
+
756
+		/*case CMemory::MAP_DSP:
757
+			if (o)
758
+			{
759
+				S9xSetDSP(Word >> 8, (Address + 1) & 0xffff);
760
+				addCyclesInMemoryAccess;
761
+				S9xSetDSP((uint8_t) Word, Address & 0xffff);
762
+				addCyclesInMemoryAccess;
763
+				return;
764
+			}
765
+			else
766
+			{
767
+				S9xSetDSP((uint8_t) Word, Address & 0xffff);
768
+				addCyclesInMemoryAccess;
769
+				S9xSetDSP(Word >> 8, (Address + 1) & 0xffff);
770
+				addCyclesInMemoryAccess;
771
+				return;
772
+			}
773
+
774
+		case CMemory::MAP_C4:
775
+			if (o)
776
+			{
777
+				S9xSetC4(Word >> 8, (Address + 1) & 0xffff);
778
+				addCyclesInMemoryAccess;
779
+				S9xSetC4((uint8_t) Word, Address & 0xffff);
780
+				addCyclesInMemoryAccess;
781
+				return;
782
+			}
783
+			else
784
+			{
785
+				S9xSetC4((uint8_t) Word, Address & 0xffff);
786
+				addCyclesInMemoryAccess;
787
+				S9xSetC4(Word >> 8, (Address + 1) & 0xffff);
788
+				addCyclesInMemoryAccess;
789
+				return;
790
+			}
791
+
792
+		case CMemory::MAP_OBC_RAM:
793
+			if (o)
794
+			{
795
+				S9xSetOBC1(Word >> 8, (Address + 1) & 0xffff);
796
+				addCyclesInMemoryAccess;
797
+				S9xSetOBC1((uint8_t) Word, Address & 0xffff);
798
+				addCyclesInMemoryAccess;
799
+				return;
800
+			}
801
+			else
802
+			{
803
+				S9xSetOBC1((uint8_t) Word, Address & 0xffff);
804
+				addCyclesInMemoryAccess;
805
+				S9xSetOBC1(Word >> 8, (Address + 1) & 0xffff);
806
+				addCyclesInMemoryAccess;
807
+				return;
808
+			}
809
+
810
+		case CMemory::MAP_SETA_DSP:
811
+			if (o)
812
+			{
813
+				S9xSetSetaDSP(Word >> 8, Address + 1);
814
+				addCyclesInMemoryAccess;
815
+				S9xSetSetaDSP((uint8_t) Word, Address);
816
+				addCyclesInMemoryAccess;
817
+				return;
818
+			}
819
+			else
820
+			{
821
+				S9xSetSetaDSP((uint8_t) Word, Address);
822
+				addCyclesInMemoryAccess;
823
+				S9xSetSetaDSP(Word >> 8, Address + 1);
824
+				addCyclesInMemoryAccess;
825
+				return;
826
+			}
827
+
828
+		case CMemory::MAP_SETA_RISC:
829
+			if (o)
830
+			{
831
+				S9xSetST018(Word >> 8, Address + 1);
832
+				addCyclesInMemoryAccess;
833
+				S9xSetST018((uint8_t) Word, Address);
834
+				addCyclesInMemoryAccess;
835
+				return;
836
+			}
837
+			else
838
+			{
839
+				S9xSetST018((uint8_t) Word, Address);
840
+				addCyclesInMemoryAccess;
841
+				S9xSetST018(Word >> 8, Address + 1);
842
+				addCyclesInMemoryAccess;
843
+				return;
844
+			}
845
+
846
+		case CMemory::MAP_BSX:
847
+			if (o)
848
+			{
849
+				S9xSetBSX(Word >> 8, Address + 1);
850
+				addCyclesInMemoryAccess;
851
+				S9xSetBSX((uint8_t) Word, Address);
852
+				addCyclesInMemoryAccess;
853
+				return;
854
+			}
855
+			else
856
+			{
857
+				S9xSetBSX((uint8_t) Word, Address);
858
+				addCyclesInMemoryAccess;
859
+				S9xSetBSX(Word >> 8, Address + 1);
860
+				addCyclesInMemoryAccess;
861
+				return;
862
+			}*/
863
+
864
+		case CMemory::MAP_NONE:
865
+		default:
866
+			addCyclesInMemoryAccess_x2;
867
+			return;
868
+	}
869
+}
870
+
871
+inline void S9xSetPCBase (uint32_t Address)
872
+{
873
+	Registers.PBPC = Address & 0xffffff;
874
+	ICPU.ShiftedPB = Address & 0xff0000;
875
+
876
+	int		block;
877
+	uint8_t	*GetAddress = Memory.Map[block = ((Address & 0xffffff) >> MEMMAP_SHIFT)];
878
+
879
+	CPU.MemSpeed = memory_speed(Address);
880
+	CPU.MemSpeedx2 = CPU.MemSpeed << 1;
881
+
882
+	if (GetAddress >= (uint8_t *) CMemory::MAP_LAST)
883
+	{
884
+		CPU.PCBase = GetAddress;
885
+		return;
886
+	}
887
+
888
+	switch ((intptr_t) GetAddress)
889
+	{
890
+		case CMemory::MAP_LOROM_SRAM:
891
+			if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK)
892
+				CPU.PCBase = NULL;
893
+			else
894
+				CPU.PCBase = Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask) - (Address & 0xffff);
895
+			return;
896
+
897
+		case CMemory::MAP_LOROM_SRAM_B:
898
+			if ((Multi.sramMaskB & MEMMAP_MASK) != MEMMAP_MASK)
899
+				CPU.PCBase = NULL;
900
+			else
901
+				CPU.PCBase = Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB) - (Address & 0xffff);
902
+			return;
903
+
904
+		case CMemory::MAP_HIROM_SRAM:
905
+			if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK)
906
+				CPU.PCBase = NULL;
907
+			else
908
+				CPU.PCBase = Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask) - (Address & 0xffff);
909
+			return;
910
+
911
+		case CMemory::MAP_BWRAM:
912
+			CPU.PCBase = Memory.BWRAM - 0x6000 - (Address & 0x8000);
913
+			return;
914
+
915
+		case CMemory::MAP_SA1RAM:
916
+			CPU.PCBase = Memory.SRAM;
917
+			return;
918
+
919
+		/*case CMemory::MAP_SPC7110_ROM:
920
+			CPU.PCBase = S9xGetBasePointerSPC7110(Address);
921
+			return;
922
+
923
+		case CMemory::MAP_C4:
924
+			CPU.PCBase = S9xGetBasePointerC4(Address & 0xffff);
925
+			return;
926
+
927
+		case CMemory::MAP_OBC_RAM:
928
+			CPU.PCBase = S9xGetBasePointerOBC1(Address & 0xffff);
929
+			return;
930
+
931
+		case CMemory::MAP_BSX:
932
+			CPU.PCBase = S9xGetBasePointerBSX(Address);
933
+			return;*/
934
+
935
+		case CMemory::MAP_NONE:
936
+		default:
937
+			CPU.PCBase = NULL;
938
+			return;
939
+	}
940
+}
941
+
942
+inline uint8_t * S9xGetBasePointer (uint32_t Address)
943
+{
944
+	uint8_t	*GetAddress = Memory.Map[(Address & 0xffffff) >> MEMMAP_SHIFT];
945
+
946
+	if (GetAddress >= (uint8_t *) CMemory::MAP_LAST)
947
+		return GetAddress;
948
+
949
+	switch ((intptr_t) GetAddress)
950
+	{
951
+		case CMemory::MAP_LOROM_SRAM:
952
+			if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK)
953
+				return NULL;
954
+			return Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask) - (Address & 0xffff);
955
+
956
+		case CMemory::MAP_LOROM_SRAM_B:
957
+			if ((Multi.sramMaskB & MEMMAP_MASK) != MEMMAP_MASK)
958
+				return NULL;
959
+			return Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB) - (Address & 0xffff);
960
+
961
+		case CMemory::MAP_HIROM_SRAM:
962
+			if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK)
963
+				return NULL;
964
+			return Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask) - (Address & 0xffff);
965
+
966
+		case CMemory::MAP_BWRAM:
967
+			return Memory.BWRAM - 0x6000 - (Address & 0x8000);
968
+
969
+		case CMemory::MAP_SA1RAM:
970
+			return Memory.SRAM;
971
+
972
+		/*case CMemory::MAP_SPC7110_ROM:
973
+			return S9xGetBasePointerSPC7110(Address);
974
+
975
+		case CMemory::MAP_C4:
976
+			return S9xGetBasePointerC4(Address & 0xffff);
977
+
978
+		case CMemory::MAP_OBC_RAM:
979
+			return S9xGetBasePointerOBC1(Address & 0xffff);*/
980
+
981
+		case CMemory::MAP_NONE:
982
+		default:
983
+			return NULL;
984
+	}
985
+}
986
+
987
+inline uint8_t * S9xGetMemPointer (uint32_t Address)
988
+{
989
+	uint8_t	*GetAddress = Memory.Map[(Address & 0xffffff) >> MEMMAP_SHIFT];
990
+
991
+	if (GetAddress >= (uint8_t *) CMemory::MAP_LAST)
992
+		return GetAddress + (Address & 0xffff);
993
+
994
+	switch ((intptr_t) GetAddress)
995
+	{
996
+		case CMemory::MAP_LOROM_SRAM:
997
+			if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK)
998
+				return NULL;
999
+			return Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask);
1000
+
1001
+		case CMemory::MAP_LOROM_SRAM_B:
1002
+			if ((Multi.sramMaskB & MEMMAP_MASK) != MEMMAP_MASK)
1003
+				return NULL;
1004
+			return Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB);
1005
+
1006
+		case CMemory::MAP_HIROM_SRAM:
1007
+			if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK)
1008
+				return NULL;
1009
+			return Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask);
1010
+
1011
+		case CMemory::MAP_BWRAM:
1012
+			return Memory.BWRAM - 0x6000 + (Address & 0x7fff);
1013
+
1014
+		case CMemory::MAP_SA1RAM:
1015
+			return Memory.SRAM + (Address & 0xffff);
1016
+
1017
+		/*case CMemory::MAP_SPC7110_ROM:
1018
+			return S9xGetBasePointerSPC7110(Address) + (Address & 0xffff);
1019
+
1020
+		case CMemory::MAP_C4:
1021
+			return S9xGetMemPointerC4(Address & 0xffff);
1022
+
1023
+		case CMemory::MAP_OBC_RAM:
1024
+			return S9xGetMemPointerOBC1(Address & 0xffff);*/
1025
+
1026
+		case CMemory::MAP_NONE:
1027
+		default:
1028
+			return NULL;
1029
+	}
1030
+}
1031
+
1032
+#endif