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Update snes9x code from 1.53 to 1.6.0.

Notable differences from upstream:
* Did not use the same #include setup for the new byuu apu and instead chose to do things more traditionally, as the latter is also much easier to deal with in Visual Studio than just including .cpp files into other .cpp files...
* MSU1 support not included (I see no need for this in a plugin meant to be used for original SNES music).
* The dynamic rate control on the APU not included (I also see no need for it in this plugin).
* The extra resamplers I added in were removed as the original hermite resampler was folded into a single non-inhertiable resampler.
* Bits of cleanup.

Naram Qashat authored on 2021/04/19 21:20:36
Showing 1 changed files
src/in_snsf/snes9x/cpuops.cpp
History View file @ 6d78469
... ... 
@@ -1,185 +1,14 @@
1 
-/***********************************************************************************
1 
+/*****************************************************************************\
2 2 
   Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
3 
-
4 
-  (c) Copyright 1996 - 2002  Gary Henderson (gary.henderson@ntlworld.com),
5 
-                             Jerremy Koot (jkoot@snes9x.com)
6 
-
7 
-  (c) Copyright 2002 - 2004  Matthew Kendora
8 
-
9 
-  (c) Copyright 2002 - 2005  Peter Bortas (peter@bortas.org)
10 
-
11 
-  (c) Copyright 2004 - 2005  Joel Yliluoma (http://iki.fi/bisqwit/)
12 
-
13 
-  (c) Copyright 2001 - 2006  John Weidman (jweidman@slip.net)
14 
-
15 
-  (c) Copyright 2002 - 2006  funkyass (funkyass@spam.shaw.ca),
16 
-                             Kris Bleakley (codeviolation@hotmail.com)
17 
-
18 
-  (c) Copyright 2002 - 2010  Brad Jorsch (anomie@users.sourceforge.net),
19 
-                             Nach (n-a-c-h@users.sourceforge.net),
20 
-
21 
-  (c) Copyright 2002 - 2011  zones (kasumitokoduck@yahoo.com)
22 
-
23 
-  (c) Copyright 2006 - 2007  nitsuja
24 
-
25 
-  (c) Copyright 2009 - 2011  BearOso,
26 
-                             OV2
27 
-
28 
-
29 
-  BS-X C emulator code
30 
-  (c) Copyright 2005 - 2006  Dreamer Nom,
31 
-                             zones
32 
-
33 
-  C4 x86 assembler and some C emulation code
34 
-  (c) Copyright 2000 - 2003  _Demo_ (_demo_@zsnes.com),
35 
-                             Nach,
36 
-                             zsKnight (zsknight@zsnes.com)
37 
-
38 
-  C4 C++ code
39 
-  (c) Copyright 2003 - 2006  Brad Jorsch,
40 
-                             Nach
41 
-
42 
-  DSP-1 emulator code
43 
-  (c) Copyright 1998 - 2006  _Demo_,
44 
-                             Andreas Naive (andreasnaive@gmail.com),
45 
-                             Gary Henderson,
46 
-                             Ivar (ivar@snes9x.com),
47 
-                             John Weidman,
48 
-                             Kris Bleakley,
49 
-                             Matthew Kendora,
50 
-                             Nach,
51 
-                             neviksti (neviksti@hotmail.com)
52 
-
53 
-  DSP-2 emulator code
54 
-  (c) Copyright 2003         John Weidman,
55 
-                             Kris Bleakley,
56 
-                             Lord Nightmare (lord_nightmare@users.sourceforge.net),
57 
-                             Matthew Kendora,
58 
-                             neviksti
59 
-
60 
-  DSP-3 emulator code
61 
-  (c) Copyright 2003 - 2006  John Weidman,
62 
-                             Kris Bleakley,
63 
-                             Lancer,
64 
-                             z80 gaiden
65 
-
66 
-  DSP-4 emulator code
67 
-  (c) Copyright 2004 - 2006  Dreamer Nom,
68 
-                             John Weidman,
69 
-                             Kris Bleakley,
70 
-                             Nach,
71 
-                             z80 gaiden
72 
-
73 
-  OBC1 emulator code
74 
-  (c) Copyright 2001 - 2004  zsKnight,
75 
-                             pagefault (pagefault@zsnes.com),
76 
-                             Kris Bleakley
77 
-                             Ported from x86 assembler to C by sanmaiwashi
78 
-
79 
-  SPC7110 and RTC C++ emulator code used in 1.39-1.51
80 
-  (c) Copyright 2002         Matthew Kendora with research by
81 
-                             zsKnight,
82 
-                             John Weidman,
83 
-                             Dark Force
84 
-
85 
-  SPC7110 and RTC C++ emulator code used in 1.52+
86 
-  (c) Copyright 2009         byuu,
87 
-                             neviksti
88 
-
89 
-  S-DD1 C emulator code
90 
-  (c) Copyright 2003         Brad Jorsch with research by
91 
-                             Andreas Naive,
92 
-                             John Weidman
93 
-
94 
-  S-RTC C emulator code
95 
-  (c) Copyright 2001 - 2006  byuu,
96 
-                             John Weidman
97 
-
98 
-  ST010 C++ emulator code
99 
-  (c) Copyright 2003         Feather,
100 
-                             John Weidman,
101 
-                             Kris Bleakley,
102 
-                             Matthew Kendora
103 
-
104 
-  Super FX x86 assembler emulator code
105 
-  (c) Copyright 1998 - 2003  _Demo_,
106 
-                             pagefault,
107 
-                             zsKnight
108 
-
109 
-  Super FX C emulator code
110 
-  (c) Copyright 1997 - 1999  Ivar,
111 
-                             Gary Henderson,
112 
-                             John Weidman
113 
-
114 
-  Sound emulator code used in 1.5-1.51
115 
-  (c) Copyright 1998 - 2003  Brad Martin
116 
-  (c) Copyright 1998 - 2006  Charles Bilyue'
117 
-
118 
-  Sound emulator code used in 1.52+
119 
-  (c) Copyright 2004 - 2007  Shay Green (gblargg@gmail.com)
120 
-
121 
-  SH assembler code partly based on x86 assembler code
122 
-  (c) Copyright 2002 - 2004  Marcus Comstedt (marcus@mc.pp.se)
123 
-
124 
-  2xSaI filter
125 
-  (c) Copyright 1999 - 2001  Derek Liauw Kie Fa
126 
-
127 
-  HQ2x, HQ3x, HQ4x filters
128 
-  (c) Copyright 2003         Maxim Stepin (maxim@hiend3d.com)
129 
-
130 
-  NTSC filter
131 
-  (c) Copyright 2006 - 2007  Shay Green
132 
-
133 
-  GTK+ GUI code
134 
-  (c) Copyright 2004 - 2011  BearOso
135 
-
136 
-  Win32 GUI code
137 
-  (c) Copyright 2003 - 2006  blip,
138 
-                             funkyass,
139 
-                             Matthew Kendora,
140 
-                             Nach,
141 
-                             nitsuja
142 
-  (c) Copyright 2009 - 2011  OV2
143 
-
144 
-  Mac OS GUI code
145 
-  (c) Copyright 1998 - 2001  John Stiles
146 
-  (c) Copyright 2001 - 2011  zones
147 
-
148 
-
149 
-  Specific ports contains the works of other authors. See headers in
150 
-  individual files.
151 
-
152 
-
153 
-  Snes9x homepage: http://www.snes9x.com/
154 
-
155 
-  Permission to use, copy, modify and/or distribute Snes9x in both binary
156 
-  and source form, for non-commercial purposes, is hereby granted without
157 
-  fee, providing that this license information and copyright notice appear
158 
-  with all copies and any derived work.
159 
-
160 
-  This software is provided 'as-is', without any express or implied
161 
-  warranty. In no event shall the authors be held liable for any damages
162 
-  arising from the use of this software or it's derivatives.
163 
-
164 
-  Snes9x is freeware for PERSONAL USE only. Commercial users should
165 
-  seek permission of the copyright holders first. Commercial use includes,
166 
-  but is not limited to, charging money for Snes9x or software derived from
167 
-  Snes9x, including Snes9x or derivatives in commercial game bundles, and/or
168 
-  using Snes9x as a promotion for your commercial product.
169 
-
170 
-  The copyright holders request that bug fixes and improvements to the code
171 
-  should be forwarded to them so everyone can benefit from the modifications
172 
-  in future versions.
173 
-
174 
-  Super NES and Super Nintendo Entertainment System are trademarks of
175 
-  Nintendo Co., Limited and its subsidiary companies.
176 
- ***********************************************************************************/
3 
+                This file is licensed under the Snes9x License.
4 
+   For further information, consult the LICENSE file in the root directory.
5 
+\*****************************************************************************/
177 6
178 7 
 #include "snes9x.h"
179 8 
 #include "memmap.h"
180 9 
 #include "apu/apu.h"
181 10
182 
-static inline void AddCycles(int32_t n) { CPU.PrevCycles = CPU.Cycles; CPU.Cycles += n; S9xCheckInterrupts(); while (CPU.Cycles >= CPU.NextEvent) S9xDoHEventProcessing(); }
11 
+static inline void AddCycles(int32_t n) { CPU.Cycles += n; while (CPU.Cycles >= CPU.NextEvent) S9xDoHEventProcessing(); }
183 12
184 13 
 #include "cpuaddr.h"
185 14 
 #include "cpuops.h"
... ... 
@@ -1537,15 +1366,17 @@ static void OpF8()
1537 1366 
 // CLI
1538 1367 
 static void Op58()
1539 1368 
 {
1540 
-	ClearIRQ();
1541 1369 
 	AddCycles(ONE_CYCLE);
1370 
+
1371 
+	Timings.IRQFlagChanging |= IRQ_CLEAR_FLAG;
1542 1372 
 }
1543 1373
1544 1374 
 // SEI
1545 1375 
 static void Op78()
1546 1376 
 {
1547 
-	SetIRQ();
1548 1377 
 	AddCycles(ONE_CYCLE);
1378 
+
1379 
+	Timings.IRQFlagChanging |= IRQ_SET_FLAG;
1549 1380 
 }
1550 1381
1551 1382 
 // CLV
... ... 
@@ -2843,8 +2674,9 @@ static void Op40Slow()
2843 2674 
 static void OpCB()
2844 2675 
 {
2845 2676 
 	CPU.WaitingForInterrupt = true;
2677 
+
2846 2678 
 	--Registers.PC.W.xPC;
2847 
-	AddCycles(TWO_CYCLES);
2679 
+	AddCycles(ONE_CYCLE);
2848 2680 
 }
2849 2681
2850 2682 
 // STP
Browse code

* Fixes for gcc and clang (while they can compile the code, the DLLs made aren't functional, but oh well).

* [2SF] Used more up-to-date asmjit, despite the ugly looking code.

Naram Qashat authored on 2014/09/17 19:51:45
Showing 1 changed files
src/in_snsf/snes9x/cpuops.cpp
History View file @ 9315374
... ... 
@@ -187,16 +187,16 @@ static inline void AddCycles(int32_t n) { CPU.PrevCycles = CPU.Cycles; CPU.Cycle
187 187
188 188 
 /* ADC ********************************************************************* */
189 189
190 
-template<typename T> static inline void ADC(T Work)
190 
+template<typename T> static inline void ADC(T)
191 191 
 {
192 192 
 }
193 193
194 
-template<> static inline void ADC<uint16_t>(uint16_t Work16)
194 
+template<> inline void ADC<uint16_t>(uint16_t Work16)
195 195 
 {
196 196 
 	ADC16(Work16);
197 197 
 }
198 198
199 
-template<> static inline void ADC<uint8_t>(uint8_t Work8)
199 
+template<> inline void ADC<uint8_t>(uint8_t Work8)
200 200 
 {
201 201 
 	ADC8(Work8);
202 202 
 }
... ... 
@@ -1199,16 +1199,16 @@ static void Op7ESlow() { mOPM(AbsoluteIndexedXSlow, ROR8, ROR16); }
1199 1199
1200 1200 
 /* SBC ********************************************************************* */
1201 1201
1202 
-template<typename T> static inline void SBC(T Work)
1202 
+template<typename T> static inline void SBC(T)
1203 1203 
 {
1204 1204 
 }
1205 1205
1206 
-template<> static inline void SBC<uint16_t>(uint16_t Work16)
1206 
+template<> inline void SBC<uint16_t>(uint16_t Work16)
1207 1207 
 {
1208 1208 
 	SBC16(Work16);
1209 1209 
 }
1210 1210
1211 
-template<> static inline void SBC<uint8_t>(uint8_t Work8)
1211 
+template<> inline void SBC<uint8_t>(uint8_t Work8)
1212 1212 
 {
1213 1213 
 	SBC8(Work8);
1214 1214 
 }
Browse code

[SNSF] Massive code cleanup, as well as removing as much unused code/variables as possible.

Naram Qashat authored on 2013/05/23 06:02:16
Showing 1 changed files
src/in_snsf/snes9x/cpuops.cpp
History View file @ 5035fcf
... ... 
@@ -179,21 +179,7 @@
179 179 
 #include "memmap.h"
180 180 
 #include "apu/apu.h"
181 181
182 
-// for "Magic WDM" features
183 
-#ifdef DEBUGGER
184 
-#include "snapshot.h"
185 
-#include "display.h"
186 
-#include "debug.h"
187 
-#include "missing.h"
188 
-#endif
189 
-
190 
-#ifdef SA1_OPCODES
191 
-//#define AddCycles(n)	{ SA1.Cycles += (n); }
192 
-static inline void AddCycles(int32_t n) { SA1.Cycles += n; }
193 
-#else
194 
-//#define AddCycles(n)	{ CPU.PrevCycles = CPU.Cycles; CPU.Cycles += (n); S9xCheckInterrupts(); while (CPU.Cycles >= CPU.NextEvent) S9xDoHEventProcessing(); }
195 182 
 static inline void AddCycles(int32_t n) { CPU.PrevCycles = CPU.Cycles; CPU.Cycles += n; S9xCheckInterrupts(); while (CPU.Cycles >= CPU.NextEvent) S9xDoHEventProcessing(); }
196 
-#endif
197 183
198 184 
 #include "cpuaddr.h"
199 185 
 #include "cpuops.h"
... ... 
@@ -201,847 +187,794 @@ static inline void AddCycles(int32_t n) { CPU.PrevCycles = CPU.Cycles; CPU.Cycle
201 187
202 188 
 /* ADC ********************************************************************* */
203 189
190 
+template<typename T> static inline void ADC(T Work)
191 
+{
192 
+}
193 
+
194 
+template<> static inline void ADC<uint16_t>(uint16_t Work16)
195 
+{
196 
+	ADC16(Work16);
197 
+}
198 
+
199 
+template<> static inline void ADC<uint8_t>(uint8_t Work8)
200 
+{
201 
+	ADC8(Work8);
202 
+}
203 
+
204 
+template<typename F> static inline void Op69Wrapper(F f)
205 
+{
206 
+	ADC(f(READ));
207 
+}
208 
+
204 209 
 static void Op69M1()
205 210 
 {
206 
-	ADC(Immediate8(READ));
211 
+	Op69Wrapper(Immediate8);
207 212 
 }
208 213
209 214 
 static void Op69M0()
210 215 
 {
211 
-	ADC(Immediate16(READ));
216 
+	Op69Wrapper(Immediate16);
212 217 
 }
213 218
214 219 
 static void Op69Slow()
215 220 
 {
216 221 
 	if (CheckMemory())
217 
-		ADC(Immediate8Slow(READ));
222 
+		Op69Wrapper(Immediate8Slow);
218 223 
 	else
219 
-		ADC(Immediate16Slow(READ));
220 
-}
221 
-
222 
-rOP8 (65M1,     Direct,                           WRAP_BANK, ADC)
223 
-rOP16(65M0,     Direct,                           WRAP_BANK, ADC)
224 
-rOPM (65Slow,   DirectSlow,                       WRAP_BANK, ADC)
225 
-
226 
-rOP8 (75E1,     DirectIndexedXE1,                 WRAP_BANK, ADC)
227 
-rOP8 (75E0M1,   DirectIndexedXE0,                 WRAP_BANK, ADC)
228 
-rOP16(75E0M0,   DirectIndexedXE0,                 WRAP_BANK, ADC)
229 
-rOPM (75Slow,   DirectIndexedXSlow,               WRAP_BANK, ADC)
230 
-
231 
-rOP8 (72E1,     DirectIndirectE1,                 WRAP_NONE, ADC)
232 
-rOP8 (72E0M1,   DirectIndirectE0,                 WRAP_NONE, ADC)
233 
-rOP16(72E0M0,   DirectIndirectE0,                 WRAP_NONE, ADC)
234 
-rOPM (72Slow,   DirectIndirectSlow,               WRAP_NONE, ADC)
235 
-
236 
-rOP8 (61E1,     DirectIndexedIndirectE1,          WRAP_NONE, ADC)
237 
-rOP8 (61E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, ADC)
238 
-rOP16(61E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, ADC)
239 
-rOPM (61Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, ADC)
240 
-
241 
-rOP8 (71E1,     DirectIndirectIndexedE1,          WRAP_NONE, ADC)
242 
-rOP8 (71E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, ADC)
243 
-rOP16(71E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, ADC)
244 
-rOP8 (71E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, ADC)
245 
-rOP16(71E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, ADC)
246 
-rOPM (71Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, ADC)
247 
-
248 
-rOP8 (67M1,     DirectIndirectLong,               WRAP_NONE, ADC)
249 
-rOP16(67M0,     DirectIndirectLong,               WRAP_NONE, ADC)
250 
-rOPM (67Slow,   DirectIndirectLongSlow,           WRAP_NONE, ADC)
251 
-
252 
-rOP8 (77M1,     DirectIndirectIndexedLong,        WRAP_NONE, ADC)
253 
-rOP16(77M0,     DirectIndirectIndexedLong,        WRAP_NONE, ADC)
254 
-rOPM (77Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, ADC)
255 
-
256 
-rOP8 (6DM1,     Absolute,                         WRAP_NONE, ADC)
257 
-rOP16(6DM0,     Absolute,                         WRAP_NONE, ADC)
258 
-rOPM (6DSlow,   AbsoluteSlow,                     WRAP_NONE, ADC)
259 
-
260 
-rOP8 (7DM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, ADC)
261 
-rOP16(7DM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, ADC)
262 
-rOP8 (7DM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, ADC)
263 
-rOP16(7DM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, ADC)
264 
-rOPM (7DSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, ADC)
265 
-
266 
-rOP8 (79M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, ADC)
267 
-rOP16(79M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, ADC)
268 
-rOP8 (79M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, ADC)
269 
-rOP16(79M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, ADC)
270 
-rOPM (79Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, ADC)
271 
-
272 
-rOP8 (6FM1,     AbsoluteLong,                     WRAP_NONE, ADC)
273 
-rOP16(6FM0,     AbsoluteLong,                     WRAP_NONE, ADC)
274 
-rOPM (6FSlow,   AbsoluteLongSlow,                 WRAP_NONE, ADC)
275 
-
276 
-rOP8 (7FM1,     AbsoluteLongIndexedX,             WRAP_NONE, ADC)
277 
-rOP16(7FM0,     AbsoluteLongIndexedX,             WRAP_NONE, ADC)
278 
-rOPM (7FSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, ADC)
279 
-
280 
-rOP8 (63M1,     StackRelative,                    WRAP_NONE, ADC)
281 
-rOP16(63M0,     StackRelative,                    WRAP_NONE, ADC)
282 
-rOPM (63Slow,   StackRelativeSlow,                WRAP_NONE, ADC)
283 
-
284 
-rOP8 (73M1,     StackRelativeIndirectIndexed,     WRAP_NONE, ADC)
285 
-rOP16(73M0,     StackRelativeIndirectIndexed,     WRAP_NONE, ADC)
286 
-rOPM (73Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, ADC)
224 
+		Op69Wrapper(Immediate16Slow);
225 
+}
226 
+
227 
+static void Op65M1() { rOP8(Direct, ADC8); }
228 
+static void Op65M0() { rOP16(Direct, ADC16, WRAP_BANK); }
229 
+static void Op65Slow() { rOPM(DirectSlow, ADC8, ADC16, WRAP_BANK); }
230 
+
231 
+static void Op75E1() { rOP8(DirectIndexedXE1, ADC8); }
232 
+static void Op75E0M1() { rOP8(DirectIndexedXE0, ADC8); }
233 
+static void Op75E0M0() { rOP16(DirectIndexedXE0, ADC16, WRAP_BANK); }
234 
+static void Op75Slow() { rOPM(DirectIndexedXSlow, ADC8, ADC16, WRAP_BANK); }
235 
+
236 
+static void Op72E1() { rOP8(DirectIndirectE1, ADC8); }
237 
+static void Op72E0M1() { rOP8(DirectIndirectE0, ADC8); }
238 
+static void Op72E0M0() { rOP16(DirectIndirectE0, ADC16); }
239 
+static void Op72Slow() { rOPM(DirectIndirectSlow, ADC8, ADC16); }
240 
+
241 
+static void Op61E1() { rOP8(DirectIndexedIndirectE1, ADC8); }
242 
+static void Op61E0M1() { rOP8(DirectIndexedIndirectE0, ADC8); }
243 
+static void Op61E0M0() { rOP16(DirectIndexedIndirectE0, ADC16); }
244 
+static void Op61Slow() { rOPM(DirectIndexedIndirectSlow, ADC8, ADC16); }
245 
+
246 
+static void Op71E1() { rOP8(DirectIndirectIndexedE1, ADC8); }
247 
+static void Op71E0M1X1() { rOP8(DirectIndirectIndexedE0X1, ADC8); }
248 
+static void Op71E0M0X1() { rOP16(DirectIndirectIndexedE0X1, ADC16); }
249 
+static void Op71E0M1X0() { rOP8(DirectIndirectIndexedE0X0, ADC8); }
250 
+static void Op71E0M0X0() { rOP16(DirectIndirectIndexedE0X0, ADC16); }
251 
+static void Op71Slow() { rOPM(DirectIndirectIndexedSlow, ADC8, ADC16); }
252 
+
253 
+static void Op67M1() { rOP8(DirectIndirectLong, ADC8); }
254 
+static void Op67M0() { rOP16(DirectIndirectLong, ADC16); }
255 
+static void Op67Slow() { rOPM(DirectIndirectLongSlow, ADC8, ADC16); }
256 
+
257 
+static void Op77M1() { rOP8(DirectIndirectIndexedLong, ADC8); }
258 
+static void Op77M0() { rOP16(DirectIndirectIndexedLong, ADC16); }
259 
+static void Op77Slow() { rOPM(DirectIndirectIndexedLongSlow, ADC8, ADC16); }
260 
+
261 
+static void Op6DM1() { rOP8(Absolute, ADC8); }
262 
+static void Op6DM0() { rOP16(Absolute, ADC16); }
263 
+static void Op6DSlow() { rOPM(AbsoluteSlow, ADC8, ADC16); }
264 
+
265 
+static void Op7DM1X1() { rOP8(AbsoluteIndexedXX1, ADC8); }
266 
+static void Op7DM0X1() { rOP16(AbsoluteIndexedXX1, ADC16); }
267 
+static void Op7DM1X0() { rOP8(AbsoluteIndexedXX0, ADC8); }
268 
+static void Op7DM0X0() { rOP16(AbsoluteIndexedXX0, ADC16); }
269 
+static void Op7DSlow() { rOPM(AbsoluteIndexedXSlow, ADC8, ADC16); }
270 
+
271 
+static void Op79M1X1() { rOP8(AbsoluteIndexedYX1, ADC8); }
272 
+static void Op79M0X1() { rOP16(AbsoluteIndexedYX1, ADC16); }
273 
+static void Op79M1X0() { rOP8(AbsoluteIndexedYX0, ADC8); }
274 
+static void Op79M0X0() { rOP16(AbsoluteIndexedYX0, ADC16); }
275 
+static void Op79Slow() { rOPM(AbsoluteIndexedYSlow, ADC8, ADC16); }
276 
+
277 
+static void Op6FM1() { rOP8(AbsoluteLong, ADC8); }
278 
+static void Op6FM0() { rOP16(AbsoluteLong, ADC16); }
279 
+static void Op6FSlow() { rOPM(AbsoluteLongSlow, ADC8, ADC16); }
280 
+
281 
+static void Op7FM1() { rOP8(AbsoluteLongIndexedX, ADC8); }
282 
+static void Op7FM0() { rOP16(AbsoluteLongIndexedX, ADC16); }
283 
+static void Op7FSlow() { rOPM(AbsoluteLongIndexedXSlow, ADC8, ADC16); }
284 
+
285 
+static void Op63M1() { rOP8(StackRelative, ADC8); }
286 
+static void Op63M0() { rOP16(StackRelative, ADC16); }
287 
+static void Op63Slow() { rOPM(StackRelativeSlow, ADC8, ADC16); }
288 
+
289 
+static void Op73M1() { rOP8(StackRelativeIndirectIndexed, ADC8); }
290 
+static void Op73M0() { rOP16(StackRelativeIndirectIndexed, ADC16); }
291 
+static void Op73Slow() { rOPM(StackRelativeIndirectIndexedSlow, ADC8, ADC16); }
287 292
288 293 
 /* AND ********************************************************************* */
289 294
295 
+template<typename T, typename F> static inline void Op29Wrapper(T &reg, F f)
296 
+{
297 
+	reg &= f(READ);
298 
+	SetZN(reg);
299 
+}
300 
+
290 301 
 static void Op29M1()
291 302 
 {
292 
-	Registers.AL &= Immediate8(READ);
293 
-	SetZN(Registers.AL);
303 
+	Op29Wrapper(Registers.A.B.l, Immediate8);
294 304 
 }
295 305
296 306 
 static void Op29M0()
297 307 
 {
298 
-	Registers.A.W &= Immediate16(READ);
299 
-	SetZN(Registers.A.W);
308 
+	Op29Wrapper(Registers.A.W, Immediate16);
300 309 
 }
301 310
302 311 
 static void Op29Slow()
303 312 
 {
304 313 
 	if (CheckMemory())
305 
-	{
306 
-		Registers.AL &= Immediate8Slow(READ);
307 
-		SetZN(Registers.AL);
308 
-	}
314 
+		Op29Wrapper(Registers.A.B.l, Immediate8Slow);
309 315 
 	else
310 
-	{
311 
-		Registers.A.W &= Immediate16Slow(READ);
312 
-		SetZN(Registers.A.W);
313 
-	}
314 
-}
315 
-
316 
-rOP8 (25M1,     Direct,                           WRAP_BANK, AND)
317 
-rOP16(25M0,     Direct,                           WRAP_BANK, AND)
318 
-rOPM (25Slow,   DirectSlow,                       WRAP_BANK, AND)
319 
-
320 
-rOP8 (35E1,     DirectIndexedXE1,                 WRAP_BANK, AND)
321 
-rOP8 (35E0M1,   DirectIndexedXE0,                 WRAP_BANK, AND)
322 
-rOP16(35E0M0,   DirectIndexedXE0,                 WRAP_BANK, AND)
323 
-rOPM (35Slow,   DirectIndexedXSlow,               WRAP_BANK, AND)
324 
-
325 
-rOP8 (32E1,     DirectIndirectE1,                 WRAP_NONE, AND)
326 
-rOP8 (32E0M1,   DirectIndirectE0,                 WRAP_NONE, AND)
327 
-rOP16(32E0M0,   DirectIndirectE0,                 WRAP_NONE, AND)
328 
-rOPM (32Slow,   DirectIndirectSlow,               WRAP_NONE, AND)
329 
-
330 
-rOP8 (21E1,     DirectIndexedIndirectE1,          WRAP_NONE, AND)
331 
-rOP8 (21E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, AND)
332 
-rOP16(21E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, AND)
333 
-rOPM (21Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, AND)
334 
-
335 
-rOP8 (31E1,     DirectIndirectIndexedE1,          WRAP_NONE, AND)
336 
-rOP8 (31E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, AND)
337 
-rOP16(31E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, AND)
338 
-rOP8 (31E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, AND)
339 
-rOP16(31E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, AND)
340 
-rOPM (31Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, AND)
341 
-
342 
-rOP8 (27M1,     DirectIndirectLong,               WRAP_NONE, AND)
343 
-rOP16(27M0,     DirectIndirectLong,               WRAP_NONE, AND)
344 
-rOPM (27Slow,   DirectIndirectLongSlow,           WRAP_NONE, AND)
345 
-
346 
-rOP8 (37M1,     DirectIndirectIndexedLong,        WRAP_NONE, AND)
347 
-rOP16(37M0,     DirectIndirectIndexedLong,        WRAP_NONE, AND)
348 
-rOPM (37Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, AND)
349 
-
350 
-rOP8 (2DM1,     Absolute,                         WRAP_NONE, AND)
351 
-rOP16(2DM0,     Absolute,                         WRAP_NONE, AND)
352 
-rOPM (2DSlow,   AbsoluteSlow,                     WRAP_NONE, AND)
353 
-
354 
-rOP8 (3DM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, AND)
355 
-rOP16(3DM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, AND)
356 
-rOP8 (3DM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, AND)
357 
-rOP16(3DM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, AND)
358 
-rOPM (3DSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, AND)
359 
-
360 
-rOP8 (39M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, AND)
361 
-rOP16(39M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, AND)
362 
-rOP8 (39M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, AND)
363 
-rOP16(39M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, AND)
364 
-rOPM (39Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, AND)
365 
-
366 
-rOP8 (2FM1,     AbsoluteLong,                     WRAP_NONE, AND)
367 
-rOP16(2FM0,     AbsoluteLong,                     WRAP_NONE, AND)
368 
-rOPM (2FSlow,   AbsoluteLongSlow,                 WRAP_NONE, AND)
369 
-
370 
-rOP8 (3FM1,     AbsoluteLongIndexedX,             WRAP_NONE, AND)
371 
-rOP16(3FM0,     AbsoluteLongIndexedX,             WRAP_NONE, AND)
372 
-rOPM (3FSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, AND)
373 
-
374 
-rOP8 (23M1,     StackRelative,                    WRAP_NONE, AND)
375 
-rOP16(23M0,     StackRelative,                    WRAP_NONE, AND)
376 
-rOPM (23Slow,   StackRelativeSlow,                WRAP_NONE, AND)
377 
-
378 
-rOP8 (33M1,     StackRelativeIndirectIndexed,     WRAP_NONE, AND)
379 
-rOP16(33M0,     StackRelativeIndirectIndexed,     WRAP_NONE, AND)
380 
-rOPM (33Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, AND)
316 
+		Op29Wrapper(Registers.A.W, Immediate16Slow);
317 
+}
318 
+
319 
+static void Op25M1() { rOP8(Direct, AND8); }
320 
+static void Op25M0() { rOP16(Direct, AND16, WRAP_BANK); }
321 
+static void Op25Slow() { rOPM(DirectSlow, AND8, AND16, WRAP_BANK); }
322 
+
323 
+static void Op35E1() { rOP8(DirectIndexedXE1, AND8); }
324 
+static void Op35E0M1() { rOP8(DirectIndexedXE0, AND8); }
325 
+static void Op35E0M0() { rOP16(DirectIndexedXE0, AND16, WRAP_BANK); }
326 
+static void Op35Slow() { rOPM(DirectIndexedXSlow, AND8, AND16, WRAP_BANK); }
327 
+
328 
+static void Op32E1() { rOP8(DirectIndirectE1, AND8); }
329 
+static void Op32E0M1() { rOP8(DirectIndirectE0, AND8); }
330 
+static void Op32E0M0() { rOP16(DirectIndirectE0, AND16); }
331 
+static void Op32Slow() { rOPM(DirectIndirectSlow, AND8, AND16); }
332 
+
333 
+static void Op21E1() { rOP8(DirectIndexedIndirectE1, AND8); }
334 
+static void Op21E0M1() { rOP8(DirectIndexedIndirectE0, AND8); }
335 
+static void Op21E0M0() { rOP16(DirectIndexedIndirectE0, AND16); }
336 
+static void Op21Slow() { rOPM(DirectIndexedIndirectSlow, AND8, AND16); }
337 
+
338 
+static void Op31E1() { rOP8(DirectIndirectIndexedE1, AND8); }
339 
+static void Op31E0M1X1() { rOP8(DirectIndirectIndexedE0X1, AND8); }
340 
+static void Op31E0M0X1() { rOP16(DirectIndirectIndexedE0X1, AND16); }
341 
+static void Op31E0M1X0() { rOP8(DirectIndirectIndexedE0X0, AND8); }
342 
+static void Op31E0M0X0() { rOP16(DirectIndirectIndexedE0X0, AND16); }
343 
+static void Op31Slow() { rOPM(DirectIndirectIndexedSlow, AND8, AND16); }
344 
+
345 
+static void Op27M1() { rOP8(DirectIndirectLong, AND8); }
346 
+static void Op27M0() { rOP16(DirectIndirectLong, AND16); }
347 
+static void Op27Slow() { rOPM(DirectIndirectLongSlow, AND8, AND16); }
348 
+
349 
+static void Op37M1() { rOP8(DirectIndirectIndexedLong, AND8); }
350 
+static void Op37M0() { rOP16(DirectIndirectIndexedLong, AND16); }
351 
+static void Op37Slow() { rOPM(DirectIndirectIndexedLongSlow, AND8, AND16); }
352 
+
353 
+static void Op2DM1() { rOP8(Absolute, AND8); }
354 
+static void Op2DM0() { rOP16(Absolute, AND16); }
355 
+static void Op2DSlow() { rOPM(AbsoluteSlow, AND8, AND16); }
356 
+
357 
+static void Op3DM1X1() { rOP8(AbsoluteIndexedXX1, AND8); }
358 
+static void Op3DM0X1() { rOP16(AbsoluteIndexedXX1, AND16); }
359 
+static void Op3DM1X0() { rOP8(AbsoluteIndexedXX0, AND8); }
360 
+static void Op3DM0X0() { rOP16(AbsoluteIndexedXX0, AND16); }
361 
+static void Op3DSlow() { rOPM(AbsoluteIndexedXSlow, AND8, AND16); }
362 
+
363 
+static void Op39M1X1() { rOP8(AbsoluteIndexedYX1, AND8); }
364 
+static void Op39M0X1() { rOP16(AbsoluteIndexedYX1, AND16); }
365 
+static void Op39M1X0() { rOP8(AbsoluteIndexedYX0, AND8); }
366 
+static void Op39M0X0() { rOP16(AbsoluteIndexedYX0, AND16); }
367 
+static void Op39Slow() { rOPM(AbsoluteIndexedYSlow, AND8, AND16); }
368 
+
369 
+static void Op2FM1() { rOP8(AbsoluteLong, AND8); }
370 
+static void Op2FM0() { rOP16(AbsoluteLong, AND16); }
371 
+static void Op2FSlow() { rOPM(AbsoluteLongSlow, AND8, AND16); }
372 
+
373 
+static void Op3FM1() { rOP8(AbsoluteLongIndexedX, AND8); }
374 
+static void Op3FM0() { rOP16(AbsoluteLongIndexedX, AND16); }
375 
+static void Op3FSlow() { rOPM(AbsoluteLongIndexedXSlow, AND8, AND16); }
376 
+
377 
+static void Op23M1() { rOP8(StackRelative, AND8); }
378 
+static void Op23M0() { rOP16(StackRelative, AND16); }
379 
+static void Op23Slow() { rOPM(StackRelativeSlow, AND8, AND16); }
380 
+
381 
+static void Op33M1() { rOP8(StackRelativeIndirectIndexed, AND8); }
382 
+static void Op33M0() { rOP16(StackRelativeIndirectIndexed, AND16); }
383 
+static void Op33Slow() { rOPM(StackRelativeIndirectIndexedSlow, AND8, AND16); }
381 384
382 385 
 /* ASL ********************************************************************* */
383 386
384 
-static void Op0AM1()
387 
+static inline void Op0AM1()
385 388 
 {
386 389 
 	AddCycles(ONE_CYCLE);
387 
-	ICPU._Carry = (Registers.AL & 0x80) != 0;
388 
-	Registers.AL <<= 1;
389 
-	SetZN(Registers.AL);
390 
+	ICPU._Carry = !!(Registers.A.B.l & 0x80);
391 
+	Registers.A.B.l <<= 1;
392 
+	SetZN(Registers.A.B.l);
390 393 
 }
391 394
392 
-static void Op0AM0()
395 
+static inline void Op0AM0()
393 396 
 {
394 397 
 	AddCycles(ONE_CYCLE);
395 
-	ICPU._Carry = (Registers.AH & 0x80) != 0;
398 
+	ICPU._Carry = !!(Registers.A.B.h & 0x80);
396 399 
 	Registers.A.W <<= 1;
397 400 
 	SetZN(Registers.A.W);
398 401 
 }
399 402
400 403 
 static void Op0ASlow()
401 404 
 {
402 
-	AddCycles(ONE_CYCLE);
403 
-
404 405 
 	if (CheckMemory())
405 
-	{
406 
-		ICPU._Carry = (Registers.AL & 0x80) != 0;
407 
-		Registers.AL <<= 1;
408 
-		SetZN(Registers.AL);
409 
-	}
406 
+		Op0AM1();
410 407 
 	else
411 
-	{
412 
-		ICPU._Carry = (Registers.AH & 0x80) != 0;
413 
-		Registers.A.W <<= 1;
414 
-		SetZN(Registers.A.W);
415 
-	}
408 
+		Op0AM0();
416 409 
 }
417 410
418 
-mOP8 (06M1,     Direct,                           WRAP_BANK, ASL)
419 
-mOP16(06M0,     Direct,                           WRAP_BANK, ASL)
420 
-mOPM (06Slow,   DirectSlow,                       WRAP_BANK, ASL)
411 
+static void Op06M1() { mOP8(Direct, ASL8); }
412 
+static void Op06M0() { mOP16(Direct, ASL16, WRAP_BANK); }
413 
+static void Op06Slow() { mOPM(DirectSlow, ASL8, ASL16, WRAP_BANK); }
421 414
422 
-mOP8 (16E1,     DirectIndexedXE1,                 WRAP_BANK, ASL)
423 
-mOP8 (16E0M1,   DirectIndexedXE0,                 WRAP_BANK, ASL)
424 
-mOP16(16E0M0,   DirectIndexedXE0,                 WRAP_BANK, ASL)
425 
-mOPM (16Slow,   DirectIndexedXSlow,               WRAP_BANK, ASL)
415 
+static void Op16E1() { mOP8(DirectIndexedXE1, ASL8); }
416 
+static void Op16E0M1() { mOP8(DirectIndexedXE0, ASL8); }
417 
+static void Op16E0M0() { mOP16(DirectIndexedXE0, ASL16, WRAP_BANK); }
418 
+static void Op16Slow() { mOPM(DirectIndexedXSlow, ASL8, ASL16, WRAP_BANK); }
426 419
427 
-mOP8 (0EM1,     Absolute,                         WRAP_NONE, ASL)
428 
-mOP16(0EM0,     Absolute,                         WRAP_NONE, ASL)
429 
-mOPM (0ESlow,   AbsoluteSlow,                     WRAP_NONE, ASL)
420 
+static void Op0EM1() { mOP8(Absolute, ASL8); }
421 
+static void Op0EM0() { mOP16(Absolute, ASL16); }
422 
+static void Op0ESlow() { mOPM(AbsoluteSlow, ASL8, ASL16); }
430 423
431 
-mOP8 (1EM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, ASL)
432 
-mOP16(1EM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, ASL)
433 
-mOP8 (1EM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, ASL)
434 
-mOP16(1EM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, ASL)
435 
-mOPM (1ESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, ASL)
424 
+static void Op1EM1X1() { mOP8(AbsoluteIndexedXX1, ASL8); }
425 
+static void Op1EM0X1() { mOP16(AbsoluteIndexedXX1, ASL16); }
426 
+static void Op1EM1X0() { mOP8(AbsoluteIndexedXX0, ASL8); }
427 
+static void Op1EM0X0() { mOP16(AbsoluteIndexedXX0, ASL16); }
428 
+static void Op1ESlow() { mOPM(AbsoluteIndexedXSlow, ASL8, ASL16); }
436 429
437 430 
 /* BIT ********************************************************************* */
438 431
432 
+template<typename T, typename F> static inline void Op89Wrapper(const T &reg, F f)
433 
+{
434 
+	ICPU._Zero = !!(reg & f(READ));
435 
+}
436 
+
439 437 
 static void Op89M1()
440 438 
 {
441 
-	ICPU._Zero = Registers.AL & Immediate8(READ);
439 
+	Op89Wrapper(Registers.A.B.l, Immediate8);
442 440 
 }
443 441
444 442 
 static void Op89M0()
445 443 
 {
446 
-	ICPU._Zero = (Registers.A.W & Immediate16(READ)) != 0;
444 
+	Op89Wrapper(Registers.A.W, Immediate16);
447 445 
 }
448 446
449 447 
 static void Op89Slow()
450 448 
 {
451 449 
 	if (CheckMemory())
452 
-		ICPU._Zero = Registers.AL & Immediate8Slow(READ);
450 
+		Op89Wrapper(Registers.A.B.l, Immediate8Slow);
453 451 
 	else
454 
-		ICPU._Zero = (Registers.A.W & Immediate16Slow(READ)) != 0;
452 
+		Op89Wrapper(Registers.A.W, Immediate16Slow);
455 453 
 }
456 454
457 
-rOP8 (24M1,     Direct,                           WRAP_BANK, BIT)
458 
-rOP16(24M0,     Direct,                           WRAP_BANK, BIT)
459 
-rOPM (24Slow,   DirectSlow,                       WRAP_BANK, BIT)
455 
+static void Op24M1() { rOP8(Direct, BIT8); }
456 
+static void Op24M0() { rOP16(Direct, BIT16, WRAP_BANK); }
457 
+static void Op24Slow() { rOPM(DirectSlow, BIT8, BIT16, WRAP_BANK); }
460 458
461 
-rOP8 (34E1,     DirectIndexedXE1,                 WRAP_BANK, BIT)
462 
-rOP8 (34E0M1,   DirectIndexedXE0,                 WRAP_BANK, BIT)
463 
-rOP16(34E0M0,   DirectIndexedXE0,                 WRAP_BANK, BIT)
464 
-rOPM (34Slow,   DirectIndexedXSlow,               WRAP_BANK, BIT)
459 
+static void Op34E1() { rOP8(DirectIndexedXE1, BIT8); }
460 
+static void Op34E0M1() { rOP8(DirectIndexedXE0, BIT8); }
461 
+static void Op34E0M0() { rOP16(DirectIndexedXE0, BIT16, WRAP_BANK); }
462 
+static void Op34Slow() { rOPM(DirectIndexedXSlow, BIT8, BIT16, WRAP_BANK); }
465 463
466 
-rOP8 (2CM1,     Absolute,                         WRAP_NONE, BIT)
467 
-rOP16(2CM0,     Absolute,                         WRAP_NONE, BIT)
468 
-rOPM (2CSlow,   AbsoluteSlow,                     WRAP_NONE, BIT)
464 
+static void Op2CM1() { rOP8(Absolute, BIT8); }
465 
+static void Op2CM0() { rOP16(Absolute, BIT16); }
466 
+static void Op2CSlow() { rOPM(AbsoluteSlow, BIT8, BIT16); }
469 467
470 
-rOP8 (3CM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, BIT)
471 
-rOP16(3CM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, BIT)
472 
-rOP8 (3CM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, BIT)
473 
-rOP16(3CM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, BIT)
474 
-rOPM (3CSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, BIT)
468 
+static void Op3CM1X1() { rOP8(AbsoluteIndexedXX1, BIT8); }
469 
+static void Op3CM0X1() { rOP16(AbsoluteIndexedXX1, BIT16); }
470 
+static void Op3CM1X0() { rOP8(AbsoluteIndexedXX0, BIT8); }
471 
+static void Op3CM0X0() { rOP16(AbsoluteIndexedXX0, BIT16); }
472 
+static void Op3CSlow() { rOPM(AbsoluteIndexedXSlow, BIT8, BIT16); }
475 473
476 474 
 /* CMP ********************************************************************* */
477 475
476 
+template<typename Tint, typename Treg, typename F> static inline void CxPxWrapper(const Treg &reg, F f)
477 
+{
478 
+	Tint intVal = static_cast<Tint>(reg) - static_cast<Tint>(f(READ));
479 
+	ICPU._Carry = intVal >= 0;
480 
+	SetZN(static_cast<Treg>(intVal));
481 
+}
482 
+
478 483 
 static void OpC9M1()
479 484 
 {
480 
-	int16_t	Int16 = (int16_t) Registers.AL - (int16_t) Immediate8(READ);
481 
-	ICPU._Carry = Int16 >= 0;
482 
-	SetZN((uint8_t) Int16);
485 
+	CxPxWrapper<int16_t>(Registers.A.B.l, Immediate8);
483 486 
 }
484 487
485 488 
 static void OpC9M0()
486 489 
 {
487 
-	int32_t	Int32 = (int32_t) Registers.A.W - (int32_t) Immediate16(READ);
488 
-	ICPU._Carry = Int32 >= 0;
489 
-	SetZN((uint16_t) Int32);
490 
+	CxPxWrapper<int32_t>(Registers.A.W, Immediate16);
490 491 
 }
491 492
492 493 
 static void OpC9Slow()
493 494 
 {
494 495 
 	if (CheckMemory())
495 
-	{
496 
-		int16_t	Int16 = (int16_t) Registers.AL - (int16_t) Immediate8Slow(READ);
497 
-		ICPU._Carry = Int16 >= 0;
498 
-		SetZN((uint8_t) Int16);
499 
-	}
496 
+		CxPxWrapper<int16_t>(Registers.A.B.l, Immediate8Slow);
500 497 
 	else
501 
-	{
502 
-		int32_t	Int32 = (int32_t) Registers.A.W - (int32_t) Immediate16Slow(READ);
503 
-		ICPU._Carry = Int32 >= 0;
504 
-		SetZN((uint16_t) Int32);
505 
-	}
506 
-}
507 
-
508 
-rOP8 (C5M1,     Direct,                           WRAP_BANK, CMP)
509 
-rOP16(C5M0,     Direct,                           WRAP_BANK, CMP)
510 
-rOPM (C5Slow,   DirectSlow,                       WRAP_BANK, CMP)
511 
-
512 
-rOP8 (D5E1,     DirectIndexedXE1,                 WRAP_BANK, CMP)
513 
-rOP8 (D5E0M1,   DirectIndexedXE0,                 WRAP_BANK, CMP)
514 
-rOP16(D5E0M0,   DirectIndexedXE0,                 WRAP_BANK, CMP)
515 
-rOPM (D5Slow,   DirectIndexedXSlow,               WRAP_BANK, CMP)
516 
-
517 
-rOP8 (D2E1,     DirectIndirectE1,                 WRAP_NONE, CMP)
518 
-rOP8 (D2E0M1,   DirectIndirectE0,                 WRAP_NONE, CMP)
519 
-rOP16(D2E0M0,   DirectIndirectE0,                 WRAP_NONE, CMP)
520 
-rOPM (D2Slow,   DirectIndirectSlow,               WRAP_NONE, CMP)
521 
-
522 
-rOP8 (C1E1,     DirectIndexedIndirectE1,          WRAP_NONE, CMP)
523 
-rOP8 (C1E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, CMP)
524 
-rOP16(C1E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, CMP)
525 
-rOPM (C1Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, CMP)
526 
-
527 
-rOP8 (D1E1,     DirectIndirectIndexedE1,          WRAP_NONE, CMP)
528 
-rOP8 (D1E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, CMP)
529 
-rOP16(D1E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, CMP)
530 
-rOP8 (D1E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, CMP)
531 
-rOP16(D1E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, CMP)
532 
-rOPM (D1Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, CMP)
533 
-
534 
-rOP8 (C7M1,     DirectIndirectLong,               WRAP_NONE, CMP)
535 
-rOP16(C7M0,     DirectIndirectLong,               WRAP_NONE, CMP)
536 
-rOPM (C7Slow,   DirectIndirectLongSlow,           WRAP_NONE, CMP)
537 
-
538 
-rOP8 (D7M1,     DirectIndirectIndexedLong,        WRAP_NONE, CMP)
539 
-rOP16(D7M0,     DirectIndirectIndexedLong,        WRAP_NONE, CMP)
540 
-rOPM (D7Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, CMP)
541 
-
542 
-rOP8 (CDM1,     Absolute,                         WRAP_NONE, CMP)
543 
-rOP16(CDM0,     Absolute,                         WRAP_NONE, CMP)
544 
-rOPM (CDSlow,   AbsoluteSlow,                     WRAP_NONE, CMP)
545 
-
546 
-rOP8 (DDM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, CMP)
547 
-rOP16(DDM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, CMP)
548 
-rOP8 (DDM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, CMP)
549 
-rOP16(DDM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, CMP)
550 
-rOPM (DDSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, CMP)
551 
-
552 
-rOP8 (D9M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, CMP)
553 
-rOP16(D9M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, CMP)
554 
-rOP8 (D9M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, CMP)
555 
-rOP16(D9M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, CMP)
556 
-rOPM (D9Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, CMP)
557 
-
558 
-rOP8 (CFM1,     AbsoluteLong,                     WRAP_NONE, CMP)
559 
-rOP16(CFM0,     AbsoluteLong,                     WRAP_NONE, CMP)
560 
-rOPM (CFSlow,   AbsoluteLongSlow,                 WRAP_NONE, CMP)
561 
-
562 
-rOP8 (DFM1,     AbsoluteLongIndexedX,             WRAP_NONE, CMP)
563 
-rOP16(DFM0,     AbsoluteLongIndexedX,             WRAP_NONE, CMP)
564 
-rOPM (DFSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, CMP)
565 
-
566 
-rOP8 (C3M1,     StackRelative,                    WRAP_NONE, CMP)
567 
-rOP16(C3M0,     StackRelative,                    WRAP_NONE, CMP)
568 
-rOPM (C3Slow,   StackRelativeSlow,                WRAP_NONE, CMP)
569 
-
570 
-rOP8 (D3M1,     StackRelativeIndirectIndexed,     WRAP_NONE, CMP)
571 
-rOP16(D3M0,     StackRelativeIndirectIndexed,     WRAP_NONE, CMP)
572 
-rOPM (D3Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, CMP)
498 
+		CxPxWrapper<int32_t>(Registers.A.W, Immediate16Slow);
499 
+}
500 
+
501 
+static void OpC5M1() { rOP8(Direct, CMP8); }
502 
+static void OpC5M0() { rOP16(Direct, CMP16, WRAP_BANK); }
503 
+static void OpC5Slow() { rOPM(DirectSlow, CMP8, CMP16, WRAP_BANK); }
504 
+
505 
+static void OpD5E1() { rOP8(DirectIndexedXE1, CMP8); }
506 
+static void OpD5E0M1() { rOP8(DirectIndexedXE0, CMP8); }
507 
+static void OpD5E0M0() { rOP16(DirectIndexedXE0, CMP16, WRAP_BANK); }
508 
+static void OpD5Slow() { rOPM(DirectIndexedXSlow, CMP8, CMP16, WRAP_BANK); }
509 
+
510 
+static void OpD2E1() { rOP8(DirectIndirectE1, CMP8); }
511 
+static void OpD2E0M1() { rOP8(DirectIndirectE0, CMP8); }
512 
+static void OpD2E0M0() { rOP16(DirectIndirectE0, CMP16); }
513 
+static void OpD2Slow() { rOPM(DirectIndirectSlow, CMP8, CMP16); }
514 
+
515 
+static void OpC1E1() { rOP8(DirectIndexedIndirectE1, CMP8); }
516 
+static void OpC1E0M1() { rOP8(DirectIndexedIndirectE0, CMP8); }
517 
+static void OpC1E0M0() { rOP16(DirectIndexedIndirectE0, CMP16); }
518 
+static void OpC1Slow() { rOPM(DirectIndexedIndirectSlow, CMP8, CMP16); }
519 
+
520 
+static void OpD1E1() { rOP8(DirectIndirectIndexedE1, CMP8); }
521 
+static void OpD1E0M1X1() { rOP8(DirectIndirectIndexedE0X1, CMP8); }
522 
+static void OpD1E0M0X1() { rOP16(DirectIndirectIndexedE0X1, CMP16); }
523 
+static void OpD1E0M1X0() { rOP8(DirectIndirectIndexedE0X0, CMP8); }
524 
+static void OpD1E0M0X0() { rOP16(DirectIndirectIndexedE0X0, CMP16); }
525 
+static void OpD1Slow() { rOPM(DirectIndirectIndexedSlow, CMP8, CMP16); }
526 
+
527 
+static void OpC7M1() { rOP8(DirectIndirectLong, CMP8); }
528 
+static void OpC7M0() { rOP16(DirectIndirectLong, CMP16); }
529 
+static void OpC7Slow() { rOPM(DirectIndirectLongSlow, CMP8, CMP16); }
530 
+
531 
+static void OpD7M1() { rOP8(DirectIndirectIndexedLong, CMP8); }
532 
+static void OpD7M0() { rOP16(DirectIndirectIndexedLong, CMP16); }
533 
+static void OpD7Slow() { rOPM(DirectIndirectIndexedLongSlow, CMP8, CMP16); }
534 
+
535 
+static void OpCDM1() { rOP8(Absolute, CMP8); }
536 
+static void OpCDM0() { rOP16(Absolute, CMP16); }
537 
+static void OpCDSlow() { rOPM(AbsoluteSlow, CMP8, CMP16); }
538 
+
539 
+static void OpDDM1X1() { rOP8(AbsoluteIndexedXX1, CMP8); }
540 
+static void OpDDM0X1() { rOP16(AbsoluteIndexedXX1, CMP16); }
541 
+static void OpDDM1X0() { rOP8(AbsoluteIndexedXX0, CMP8); }
542 
+static void OpDDM0X0() { rOP16(AbsoluteIndexedXX0, CMP16); }
543 
+static void OpDDSlow() { rOPM(AbsoluteIndexedXSlow, CMP8, CMP16); }
544 
+
545 
+static void OpD9M1X1() { rOP8(AbsoluteIndexedYX1, CMP8); }
546 
+static void OpD9M0X1() { rOP16(AbsoluteIndexedYX1, CMP16); }
547 
+static void OpD9M1X0() { rOP8(AbsoluteIndexedYX0, CMP8); }
548 
+static void OpD9M0X0() { rOP16(AbsoluteIndexedYX0, CMP16); }
549 
+static void OpD9Slow() { rOPM(AbsoluteIndexedYSlow, CMP8, CMP16); }
550 
+
551 
+static void OpCFM1() { rOP8(AbsoluteLong, CMP8); }
552 
+static void OpCFM0() { rOP16(AbsoluteLong, CMP16); }
553 
+static void OpCFSlow() { rOPM(AbsoluteLongSlow, CMP8, CMP16); }
554 
+
555 
+static void OpDFM1() { rOP8(AbsoluteLongIndexedX, CMP8); }
556 
+static void OpDFM0() { rOP16(AbsoluteLongIndexedX, CMP16); }
557 
+static void OpDFSlow() { rOPM(AbsoluteLongIndexedXSlow, CMP8, CMP16); }
558 
+
559 
+static void OpC3M1() { rOP8(StackRelative, CMP8); }
560 
+static void OpC3M0() { rOP16(StackRelative, CMP16); }
561 
+static void OpC3Slow() { rOPM(StackRelativeSlow, CMP8, CMP16); }
562 
+
563 
+static void OpD3M1() { rOP8(StackRelativeIndirectIndexed, CMP8); }
564 
+static void OpD3M0() { rOP16(StackRelativeIndirectIndexed, CMP16); }
565 
+static void OpD3Slow() { rOPM(StackRelativeIndirectIndexedSlow, CMP8, CMP16); }
573 566
574 567 
 /* CPX ********************************************************************* */
575 568
576 569 
 static void OpE0X1()
577 570 
 {
578 
-	int16_t	Int16 = (int16_t) Registers.XL - (int16_t) Immediate8(READ);
579 
-	ICPU._Carry = Int16 >= 0;
580 
-	SetZN((uint8_t) Int16);
571 
+	CxPxWrapper<int16_t>(Registers.X.B.l, Immediate8);
581 572 
 }
582 573
583 574 
 static void OpE0X0()
584 575 
 {
585 
-	int32_t	Int32 = (int32_t) Registers.X.W - (int32_t) Immediate16(READ);
586 
-	ICPU._Carry = Int32 >= 0;
587 
-	SetZN((uint16_t) Int32);
576 
+	CxPxWrapper<int32_t>(Registers.X.W, Immediate16);
588 577 
 }
589 578
590 579 
 static void OpE0Slow()
591 580 
 {
592 581 
 	if (CheckIndex())
593 
-	{
594 
-		int16_t	Int16 = (int16_t) Registers.XL - (int16_t) Immediate8Slow(READ);
595 
-		ICPU._Carry = Int16 >= 0;
596 
-		SetZN((uint8_t) Int16);
597 
-	}
582 
+		CxPxWrapper<int16_t>(Registers.X.B.l, Immediate8Slow);
598 583 
 	else
599 
-	{
600 
-		int32_t	Int32 = (int32_t) Registers.X.W - (int32_t) Immediate16Slow(READ);
601 
-		ICPU._Carry = Int32 >= 0;
602 
-		SetZN((uint16_t) Int32);
603 
-	}
584 
+		CxPxWrapper<int32_t>(Registers.X.W, Immediate16Slow);
604 585 
 }
605 586
606 
-rOP8 (E4X1,     Direct,                           WRAP_BANK, CPX)
607 
-rOP16(E4X0,     Direct,                           WRAP_BANK, CPX)
608 
-rOPX (E4Slow,   DirectSlow,                       WRAP_BANK, CPX)
587 
+static void OpE4X1() { rOP8(Direct, CPX8); }
588 
+static void OpE4X0() { rOP16(Direct, CPX16, WRAP_BANK); }
589 
+static void OpE4Slow() { rOPX(DirectSlow, CPX8, CPX16, WRAP_BANK); }
609 590
610 
-rOP8 (ECX1,     Absolute,                         WRAP_NONE, CPX)
611 
-rOP16(ECX0,     Absolute,                         WRAP_NONE, CPX)
612 
-rOPX (ECSlow,   AbsoluteSlow,                     WRAP_NONE, CPX)
591 
+static void OpECX1() { rOP8(Absolute, CPX8); }
592 
+static void OpECX0() { rOP16(Absolute, CPX16); }
593 
+static void OpECSlow() { rOPX(AbsoluteSlow, CPX8, CPX16); }
613 594
614 595 
 /* CPY ********************************************************************* */
615 596
616 597 
 static void OpC0X1()
617 598 
 {
618 
-	int16_t	Int16 = (int16_t) Registers.YL - (int16_t) Immediate8(READ);
619 
-	ICPU._Carry = Int16 >= 0;
620 
-	SetZN((uint8_t) Int16);
599 
+	CxPxWrapper<int16_t>(Registers.Y.B.l, Immediate8);
621 600 
 }
622 601
623 602 
 static void OpC0X0()
624 603 
 {
625 
-	int32_t	Int32 = (int32_t) Registers.Y.W - (int32_t) Immediate16(READ);
626 
-	ICPU._Carry = Int32 >= 0;
627 
-	SetZN((uint16_t) Int32);
604 
+	CxPxWrapper<int32_t>(Registers.Y.W, Immediate16);
628 605 
 }
629 606
630 607 
 static void OpC0Slow()
631 608 
 {
632 609 
 	if (CheckIndex())
633 
-	{
634 
-		int16_t	Int16 = (int16_t) Registers.YL - (int16_t) Immediate8Slow(READ);
635 
-		ICPU._Carry = Int16 >= 0;
636 
-		SetZN((uint8_t) Int16);
637 
-	}
610 
+		CxPxWrapper<int16_t>(Registers.Y.B.l, Immediate8Slow);
638 611 
 	else
639 
-	{
640 
-		int32_t	Int32 = (int32_t) Registers.Y.W - (int32_t) Immediate16Slow(READ);
641 
-		ICPU._Carry = Int32 >= 0;
642 
-		SetZN((uint16_t) Int32);
643 
-	}
612 
+		CxPxWrapper<int32_t>(Registers.Y.W, Immediate16Slow);
644 613 
 }
645 614
646 
-rOP8 (C4X1,     Direct,                           WRAP_BANK, CPY)
647 
-rOP16(C4X0,     Direct,                           WRAP_BANK, CPY)
648 
-rOPX (C4Slow,   DirectSlow,                       WRAP_BANK, CPY)
615 
+static void OpC4X1() { rOP8(Direct, CPY8); }
616 
+static void OpC4X0() { rOP16(Direct, CPY16, WRAP_BANK); }
617 
+static void OpC4Slow() { rOPX(DirectSlow, CPY8, CPY16, WRAP_BANK); }
649 618
650 
-rOP8 (CCX1,     Absolute,                         WRAP_NONE, CPY)
651 
-rOP16(CCX0,     Absolute,                         WRAP_NONE, CPY)
652 
-rOPX (CCSlow,   AbsoluteSlow,                     WRAP_NONE, CPY)
619 
+static void OpCCX1() { rOP8(Absolute, CPY8); }
620 
+static void OpCCX0() { rOP16(Absolute, CPY16); }
621 
+static void OpCCSlow() { rOPX(AbsoluteSlow, CPY8, CPY16); }
653 622
654 623 
 /* DEC ********************************************************************* */
655 624
656 
-static void Op3AM1()
625 
+static inline void Op3AM1()
657 626 
 {
658 627 
 	AddCycles(ONE_CYCLE);
659 
-	Registers.AL--;
660 
-	SetZN(Registers.AL);
628 
+	--Registers.A.B.l;
629 
+	SetZN(Registers.A.B.l);
661 630 
 }
662 631
663 
-static void Op3AM0()
632 
+static inline void Op3AM0()
664 633 
 {
665 634 
 	AddCycles(ONE_CYCLE);
666 
-	Registers.A.W--;
635 
+	--Registers.A.W;
667 636 
 	SetZN(Registers.A.W);
668 637 
 }
669 638
670 639 
 static void Op3ASlow()
671 640 
 {
672 
-	AddCycles(ONE_CYCLE);
673 
-
674 641 
 	if (CheckMemory())
675 
-	{
676 
-		Registers.AL--;
677 
-		SetZN(Registers.AL);
678 
-	}
642 
+		Op3AM1();
679 643 
 	else
680 
-	{
681 
-		Registers.A.W--;
682 
-		SetZN(Registers.A.W);
683 
-	}
644 
+		Op3AM0();
684 645 
 }
685 646
686 
-mOP8 (C6M1,     Direct,                           WRAP_BANK, DEC)
687 
-mOP16(C6M0,     Direct,                           WRAP_BANK, DEC)
688 
-mOPM (C6Slow,   DirectSlow,                       WRAP_BANK, DEC)
647 
+static void OpC6M1() { mOP8(Direct, DEC8); }
648 
+static void OpC6M0() { mOP16(Direct, DEC16, WRAP_BANK); }
649 
+static void OpC6Slow() { mOPM(DirectSlow, DEC8, DEC16, WRAP_BANK); }
689 650
690 
-mOP8 (D6E1,     DirectIndexedXE1,                 WRAP_BANK, DEC)
691 
-mOP8 (D6E0M1,   DirectIndexedXE0,                 WRAP_BANK, DEC)
692 
-mOP16(D6E0M0,   DirectIndexedXE0,                 WRAP_BANK, DEC)
693 
-mOPM (D6Slow,   DirectIndexedXSlow,               WRAP_BANK, DEC)
651 
+static void OpD6E1() { mOP8(DirectIndexedXE1, DEC8); }
652 
+static void OpD6E0M1() { mOP8(DirectIndexedXE0, DEC8); }
653 
+static void OpD6E0M0() { mOP16(DirectIndexedXE0, DEC16, WRAP_BANK); }
654 
+static void OpD6Slow() { mOPM(DirectIndexedXSlow, DEC8, DEC16, WRAP_BANK); }
694 655
695 
-mOP8 (CEM1,     Absolute,                         WRAP_NONE, DEC)
696 
-mOP16(CEM0,     Absolute,                         WRAP_NONE, DEC)
697 
-mOPM (CESlow,   AbsoluteSlow,                     WRAP_NONE, DEC)
656 
+static void OpCEM1() { mOP8(Absolute, DEC8); }
657 
+static void OpCEM0() { mOP16(Absolute, DEC16); }
658 
+static void OpCESlow() { mOPM(AbsoluteSlow, DEC8, DEC16); }
698 659
699 
-mOP8 (DEM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, DEC)
700 
-mOP16(DEM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, DEC)
701 
-mOP8 (DEM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, DEC)
702 
-mOP16(DEM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, DEC)
703 
-mOPM (DESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, DEC)
660 
+static void OpDEM1X1() { mOP8(AbsoluteIndexedXX1, DEC8); }
661 
+static void OpDEM0X1() { mOP16(AbsoluteIndexedXX1, DEC16); }
662 
+static void OpDEM1X0() { mOP8(AbsoluteIndexedXX0, DEC8); }
663 
+static void OpDEM0X0() { mOP16(AbsoluteIndexedXX0, DEC16); }
664 
+static void OpDESlow() { mOPM(AbsoluteIndexedXSlow, DEC8, DEC16); }
704 665
705 666 
 /* EOR ********************************************************************* */
706 667
668 
+template<typename T, typename F> static inline void Op49Wrapper(T &reg, F f)
669 
+{
670 
+	reg ^= f(READ);
671 
+	SetZN(reg);
672 
+}
673 
+
707 674 
 static void Op49M1()
708 675 
 {
709 
-	Registers.AL ^= Immediate8(READ);
710 
-	SetZN(Registers.AL);
676 
+	Op49Wrapper(Registers.A.B.l, Immediate8);
711 677 
 }
712 678
713 679 
 static void Op49M0()
714 680 
 {
715 
-	Registers.A.W ^= Immediate16(READ);
716 
-	SetZN(Registers.A.W);
681 
+	Op49Wrapper(Registers.A.W, Immediate16);
717 682 
 }
718 683
719 684 
 static void Op49Slow()
720 685 
 {
721 686 
 	if (CheckMemory())
722 
-	{
723 
-		Registers.AL ^= Immediate8Slow(READ);
724 
-		SetZN(Registers.AL);
725 
-	}
687 
+		Op49Wrapper(Registers.A.B.l, Immediate8Slow);
726 688 
 	else
727 
-	{
728 
-		Registers.A.W ^= Immediate16Slow(READ);
729 
-		SetZN(Registers.A.W);
730 
-	}
731 
-}
732 
-
733 
-rOP8 (45M1,     Direct,                           WRAP_BANK, EOR)
734 
-rOP16(45M0,     Direct,                           WRAP_BANK, EOR)
735 
-rOPM (45Slow,   DirectSlow,                       WRAP_BANK, EOR)
736 
-
737 
-rOP8 (55E1,     DirectIndexedXE1,                 WRAP_BANK, EOR)
738 
-rOP8 (55E0M1,   DirectIndexedXE0,                 WRAP_BANK, EOR)
739 
-rOP16(55E0M0,   DirectIndexedXE0,                 WRAP_BANK, EOR)
740 
-rOPM (55Slow,   DirectIndexedXSlow,               WRAP_BANK, EOR)
741 
-
742 
-rOP8 (52E1,     DirectIndirectE1,                 WRAP_NONE, EOR)
743 
-rOP8 (52E0M1,   DirectIndirectE0,                 WRAP_NONE, EOR)
744 
-rOP16(52E0M0,   DirectIndirectE0,                 WRAP_NONE, EOR)
745 
-rOPM (52Slow,   DirectIndirectSlow,               WRAP_NONE, EOR)
746 
-
747 
-rOP8 (41E1,     DirectIndexedIndirectE1,          WRAP_NONE, EOR)
748 
-rOP8 (41E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, EOR)
749 
-rOP16(41E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, EOR)
750 
-rOPM (41Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, EOR)
751 
-
752 
-rOP8 (51E1,     DirectIndirectIndexedE1,          WRAP_NONE, EOR)
753 
-rOP8 (51E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, EOR)
754 
-rOP16(51E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, EOR)
755 
-rOP8 (51E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, EOR)
756 
-rOP16(51E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, EOR)
757 
-rOPM (51Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, EOR)
758 
-
759 
-rOP8 (47M1,     DirectIndirectLong,               WRAP_NONE, EOR)
760 
-rOP16(47M0,     DirectIndirectLong,               WRAP_NONE, EOR)
761 
-rOPM (47Slow,   DirectIndirectLongSlow,           WRAP_NONE, EOR)
762 
-
763 
-rOP8 (57M1,     DirectIndirectIndexedLong,        WRAP_NONE, EOR)
764 
-rOP16(57M0,     DirectIndirectIndexedLong,        WRAP_NONE, EOR)
765 
-rOPM (57Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, EOR)
766 
-
767 
-rOP8 (4DM1,     Absolute,                         WRAP_NONE, EOR)
768 
-rOP16(4DM0,     Absolute,                         WRAP_NONE, EOR)
769 
-rOPM (4DSlow,   AbsoluteSlow,                     WRAP_NONE, EOR)
770 
-
771 
-rOP8 (5DM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, EOR)
772 
-rOP16(5DM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, EOR)
773 
-rOP8 (5DM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, EOR)
774 
-rOP16(5DM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, EOR)
775 
-rOPM (5DSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, EOR)
776 
-
777 
-rOP8 (59M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, EOR)
778 
-rOP16(59M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, EOR)
779 
-rOP8 (59M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, EOR)
780 
-rOP16(59M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, EOR)
781 
-rOPM (59Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, EOR)
782 
-
783 
-rOP8 (4FM1,     AbsoluteLong,                     WRAP_NONE, EOR)
784 
-rOP16(4FM0,     AbsoluteLong,                     WRAP_NONE, EOR)
785 
-rOPM (4FSlow,   AbsoluteLongSlow,                 WRAP_NONE, EOR)
786 
-
787 
-rOP8 (5FM1,     AbsoluteLongIndexedX,             WRAP_NONE, EOR)
788 
-rOP16(5FM0,     AbsoluteLongIndexedX,             WRAP_NONE, EOR)
789 
-rOPM (5FSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, EOR)
790 
-
791 
-rOP8 (43M1,     StackRelative,                    WRAP_NONE, EOR)
792 
-rOP16(43M0,     StackRelative,                    WRAP_NONE, EOR)
793 
-rOPM (43Slow,   StackRelativeSlow,                WRAP_NONE, EOR)
794 
-
795 
-rOP8 (53M1,     StackRelativeIndirectIndexed,     WRAP_NONE, EOR)
796 
-rOP16(53M0,     StackRelativeIndirectIndexed,     WRAP_NONE, EOR)
797 
-rOPM (53Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, EOR)
689 
+		Op49Wrapper(Registers.A.W, Immediate16Slow);
690 
+}
691 
+
692 
+static void Op45M1() { rOP8(Direct, EOR8); }
693 
+static void Op45M0() { rOP16(Direct, EOR16, WRAP_BANK); }
694 
+static void Op45Slow() { rOPM(DirectSlow, EOR8, EOR16, WRAP_BANK); }
695 
+
696 
+static void Op55E1() { rOP8(DirectIndexedXE1, EOR8); }
697 
+static void Op55E0M1() { rOP8(DirectIndexedXE0, EOR8); }
698 
+static void Op55E0M0() { rOP16(DirectIndexedXE0, EOR16, WRAP_BANK); }
699 
+static void Op55Slow() { rOPM(DirectIndexedXSlow, EOR8, EOR16, WRAP_BANK); }
700 
+
701 
+static void Op52E1() { rOP8(DirectIndirectE1, EOR8); }
702 
+static void Op52E0M1() { rOP8(DirectIndirectE0, EOR8); }
703 
+static void Op52E0M0() { rOP16(DirectIndirectE0, EOR16); }
704 
+static void Op52Slow() { rOPM(DirectIndirectSlow, EOR8, EOR16); }
705 
+
706 
+static void Op41E1() { rOP8(DirectIndexedIndirectE1, EOR8); }
707 
+static void Op41E0M1() { rOP8(DirectIndexedIndirectE0, EOR8); }
708 
+static void Op41E0M0() { rOP16(DirectIndexedIndirectE0, EOR16); }
709 
+static void Op41Slow() { rOPM(DirectIndexedIndirectSlow, EOR8, EOR16); }
710 
+
711 
+static void Op51E1() { rOP8(DirectIndirectIndexedE1, EOR8); }
712 
+static void Op51E0M1X1() { rOP8(DirectIndirectIndexedE0X1, EOR8); }
713 
+static void Op51E0M0X1() { rOP16(DirectIndirectIndexedE0X1, EOR16); }
714 
+static void Op51E0M1X0() { rOP8(DirectIndirectIndexedE0X0, EOR8); }
715 
+static void Op51E0M0X0() { rOP16(DirectIndirectIndexedE0X0, EOR16); }
716 
+static void Op51Slow() { rOPM(DirectIndirectIndexedSlow, EOR8, EOR16); }
717 
+
718 
+static void Op47M1() { rOP8(DirectIndirectLong, EOR8); }
719 
+static void Op47M0() { rOP16(DirectIndirectLong, EOR16); }
720 
+static void Op47Slow() { rOPM(DirectIndirectLongSlow, EOR8, EOR16); }
721 
+
722 
+static void Op57M1() { rOP8(DirectIndirectIndexedLong, EOR8); }
723 
+static void Op57M0() { rOP16(DirectIndirectIndexedLong, EOR16); }
724 
+static void Op57Slow() { rOPM(DirectIndirectIndexedLongSlow, EOR8, EOR16); }
725 
+
726 
+static void Op4DM1() { rOP8(Absolute, EOR8); }
727 
+static void Op4DM0() { rOP16(Absolute, EOR16); }
728 
+static void Op4DSlow() { rOPM(AbsoluteSlow, EOR8, EOR16); }
729 
+
730 
+static void Op5DM1X1() { rOP8(AbsoluteIndexedXX1, EOR8); }
731 
+static void Op5DM0X1() { rOP16(AbsoluteIndexedXX1, EOR16); }
732 
+static void Op5DM1X0() { rOP8(AbsoluteIndexedXX0, EOR8); }
733 
+static void Op5DM0X0() { rOP16(AbsoluteIndexedXX0, EOR16); }
734 
+static void Op5DSlow() { rOPM(AbsoluteIndexedXSlow, EOR8, EOR16); }
735 
+
736 
+static void Op59M1X1() { rOP8(AbsoluteIndexedYX1, EOR8); }
737 
+static void Op59M0X1() { rOP16(AbsoluteIndexedYX1, EOR16); }
738 
+static void Op59M1X0() { rOP8(AbsoluteIndexedYX0, EOR8); }
739 
+static void Op59M0X0() { rOP16(AbsoluteIndexedYX0, EOR16); }
740 
+static void Op59Slow() { rOPM(AbsoluteIndexedYSlow, EOR8, EOR16); }
741 
+
742 
+static void Op4FM1() { rOP8(AbsoluteLong, EOR8); }
743 
+static void Op4FM0() { rOP16(AbsoluteLong, EOR16); }
744 
+static void Op4FSlow() { rOPM(AbsoluteLongSlow, EOR8, EOR16); }
745 
+
746 
+static void Op5FM1() { rOP8(AbsoluteLongIndexedX, EOR8); }
747 
+static void Op5FM0() { rOP16(AbsoluteLongIndexedX, EOR16); }
748 
+static void Op5FSlow() { rOPM(AbsoluteLongIndexedXSlow, EOR8, EOR16); }
749 
+
750 
+static void Op43M1() { rOP8(StackRelative, EOR8); }
751 
+static void Op43M0() { rOP16(StackRelative, EOR16); }
752 
+static void Op43Slow() { rOPM(StackRelativeSlow, EOR8, EOR16); }
753 
+
754 
+static void Op53M1() { rOP8(StackRelativeIndirectIndexed, EOR8); }
755 
+static void Op53M0() { rOP16(StackRelativeIndirectIndexed, EOR16); }
756 
+static void Op53Slow() { rOPM(StackRelativeIndirectIndexedSlow, EOR8, EOR16); }
798 757
799 758 
 /* INC ********************************************************************* */
800 759
801 
-static void Op1AM1()
760 
+static inline void Op1AM1()
802 761 
 {
803 762 
 	AddCycles(ONE_CYCLE);
804 
-	Registers.AL++;
805 
-	SetZN(Registers.AL);
763 
+	++Registers.A.B.l;
764 
+	SetZN(Registers.A.B.l);
806 765 
 }
807 766
808 
-static void Op1AM0()
767 
+static inline void Op1AM0()
809 768 
 {
810 769 
 	AddCycles(ONE_CYCLE);
811 
-	Registers.A.W++;
770 
+	++Registers.A.W;
812 771 
 	SetZN(Registers.A.W);
813 772 
 }
814 773
815 774 
 static void Op1ASlow()
816 775 
 {
817 
-	AddCycles(ONE_CYCLE);
818 
-
819 776 
 	if (CheckMemory())
820 
-	{
821 
-		Registers.AL++;
822 
-		SetZN(Registers.AL);
823 
-	}
777 
+		Op1AM1();
824 778 
 	else
825 
-	{
826 
-		Registers.A.W++;
827 
-		SetZN(Registers.A.W);
828 
-	}
779 
+		Op1AM0();
829 780 
 }
830 781
831 
-mOP8 (E6M1,     Direct,                           WRAP_BANK, INC)
832 
-mOP16(E6M0,     Direct,                           WRAP_BANK, INC)
833 
-mOPM (E6Slow,   DirectSlow,                       WRAP_BANK, INC)
782 
+static void OpE6M1() { mOP8(Direct, INC8); }
783 
+static void OpE6M0() { mOP16(Direct, INC16, WRAP_BANK); }
784 
+static void OpE6Slow() { mOPM(DirectSlow, INC8, INC16, WRAP_BANK); }
834 785
835 
-mOP8 (F6E1,     DirectIndexedXE1,                 WRAP_BANK, INC)
836 
-mOP8 (F6E0M1,   DirectIndexedXE0,                 WRAP_BANK, INC)
837 
-mOP16(F6E0M0,   DirectIndexedXE0,                 WRAP_BANK, INC)
838 
-mOPM (F6Slow,   DirectIndexedXSlow,               WRAP_BANK, INC)
786 
+static void OpF6E1() { mOP8(DirectIndexedXE1, INC8); }
787 
+static void OpF6E0M1() { mOP8(DirectIndexedXE0, INC8); }
788 
+static void OpF6E0M0() { mOP16(DirectIndexedXE0, INC16, WRAP_BANK); }
789 
+static void OpF6Slow() { mOPM(DirectIndexedXSlow, INC8, INC16, WRAP_BANK); }
839 790
840 
-mOP8 (EEM1,     Absolute,                         WRAP_NONE, INC)
841 
-mOP16(EEM0,     Absolute,                         WRAP_NONE, INC)
842 
-mOPM (EESlow,   AbsoluteSlow,                     WRAP_NONE, INC)
791 
+static void OpEEM1() { mOP8(Absolute, INC8); }
792 
+static void OpEEM0() { mOP16(Absolute, INC16); }
793 
+static void OpEESlow() { mOPM(AbsoluteSlow, INC8, INC16); }
843 794
844 
-mOP8 (FEM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, INC)
845 
-mOP16(FEM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, INC)
846 
-mOP8 (FEM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, INC)
847 
-mOP16(FEM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, INC)
848 
-mOPM (FESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, INC)
795 
+static void OpFEM1X1() { mOP8(AbsoluteIndexedXX1, INC8); }
796 
+static void OpFEM0X1() { mOP16(AbsoluteIndexedXX1, INC16); }
797 
+static void OpFEM1X0() { mOP8(AbsoluteIndexedXX0, INC8); }
798 
+static void OpFEM0X0() { mOP16(AbsoluteIndexedXX0, INC16); }
799 
+static void OpFESlow() { mOPM(AbsoluteIndexedXSlow, INC8, INC16); }
849 800
850 801 
 /* LDA ********************************************************************* */
851 802
803 
+template<typename T, typename F> static inline void LDWrapper(T &reg, F f)
804 
+{
805 
+	reg = f(READ);
806 
+	SetZN(reg);
807 
+}
808 
+
852 809 
 static void OpA9M1()
853 810 
 {
854 
-	Registers.AL = Immediate8(READ);
855 
-	SetZN(Registers.AL);
811 
+	LDWrapper(Registers.A.B.l, Immediate8);
856 812 
 }
857 813
858 814 
 static void OpA9M0()
859 815 
 {
860 
-	Registers.A.W = Immediate16(READ);
861 
-	SetZN(Registers.A.W);
816 
+	LDWrapper(Registers.A.W, Immediate16);
862 817 
 }
863 818
864 819 
 static void OpA9Slow()
865 820 
 {
866 821 
 	if (CheckMemory())
867 
-	{
868 
-		Registers.AL = Immediate8Slow(READ);
869 
-		SetZN(Registers.AL);
870 
-	}
822 
+		LDWrapper(Registers.A.B.l, Immediate8Slow);
871 823 
 	else
872 
-	{
873 
-		Registers.A.W = Immediate16Slow(READ);
874 
-		SetZN(Registers.A.W);
875 
-	}
876 
-}
877 
-
878 
-rOP8 (A5M1,     Direct,                           WRAP_BANK, LDA)
879 
-rOP16(A5M0,     Direct,                           WRAP_BANK, LDA)
880 
-rOPM (A5Slow,   DirectSlow,                       WRAP_BANK, LDA)
881 
-
882 
-rOP8 (B5E1,     DirectIndexedXE1,                 WRAP_BANK, LDA)
883 
-rOP8 (B5E0M1,   DirectIndexedXE0,                 WRAP_BANK, LDA)
884 
-rOP16(B5E0M0,   DirectIndexedXE0,                 WRAP_BANK, LDA)
885 
-rOPM (B5Slow,   DirectIndexedXSlow,               WRAP_BANK, LDA)
886 
-
887 
-rOP8 (B2E1,     DirectIndirectE1,                 WRAP_NONE, LDA)
888 
-rOP8 (B2E0M1,   DirectIndirectE0,                 WRAP_NONE, LDA)
889 
-rOP16(B2E0M0,   DirectIndirectE0,                 WRAP_NONE, LDA)
890 
-rOPM (B2Slow,   DirectIndirectSlow,               WRAP_NONE, LDA)
891 
-
892 
-rOP8 (A1E1,     DirectIndexedIndirectE1,          WRAP_NONE, LDA)
893 
-rOP8 (A1E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, LDA)
894 
-rOP16(A1E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, LDA)
895 
-rOPM (A1Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, LDA)
896 
-
897 
-rOP8 (B1E1,     DirectIndirectIndexedE1,          WRAP_NONE, LDA)
898 
-rOP8 (B1E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, LDA)
899 
-rOP16(B1E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, LDA)
900 
-rOP8 (B1E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, LDA)
901 
-rOP16(B1E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, LDA)
902 
-rOPM (B1Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, LDA)
903 
-
904 
-rOP8 (A7M1,     DirectIndirectLong,               WRAP_NONE, LDA)
905 
-rOP16(A7M0,     DirectIndirectLong,               WRAP_NONE, LDA)
906 
-rOPM (A7Slow,   DirectIndirectLongSlow,           WRAP_NONE, LDA)
907 
-
908 
-rOP8 (B7M1,     DirectIndirectIndexedLong,        WRAP_NONE, LDA)
909 
-rOP16(B7M0,     DirectIndirectIndexedLong,        WRAP_NONE, LDA)
910 
-rOPM (B7Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, LDA)
911 
-
912 
-rOP8 (ADM1,     Absolute,                         WRAP_NONE, LDA)
913 
-rOP16(ADM0,     Absolute,                         WRAP_NONE, LDA)
914 
-rOPM (ADSlow,   AbsoluteSlow,                     WRAP_NONE, LDA)
915 
-
916 
-rOP8 (BDM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, LDA)
917 
-rOP16(BDM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, LDA)
918 
-rOP8 (BDM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, LDA)
919 
-rOP16(BDM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, LDA)
920 
-rOPM (BDSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, LDA)
921 
-
922 
-rOP8 (B9M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, LDA)
923 
-rOP16(B9M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, LDA)
924 
-rOP8 (B9M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, LDA)
925 
-rOP16(B9M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, LDA)
926 
-rOPM (B9Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, LDA)
927 
-
928 
-rOP8 (AFM1,     AbsoluteLong,                     WRAP_NONE, LDA)
929 
-rOP16(AFM0,     AbsoluteLong,                     WRAP_NONE, LDA)
930 
-rOPM (AFSlow,   AbsoluteLongSlow,                 WRAP_NONE, LDA)
931 
-
932 
-rOP8 (BFM1,     AbsoluteLongIndexedX,             WRAP_NONE, LDA)
933 
-rOP16(BFM0,     AbsoluteLongIndexedX,             WRAP_NONE, LDA)
934 
-rOPM (BFSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, LDA)
935 
-
936 
-rOP8 (A3M1,     StackRelative,                    WRAP_NONE, LDA)
937 
-rOP16(A3M0,     StackRelative,                    WRAP_NONE, LDA)
938 
-rOPM (A3Slow,   StackRelativeSlow,                WRAP_NONE, LDA)
939 
-
940 
-rOP8 (B3M1,     StackRelativeIndirectIndexed,     WRAP_NONE, LDA)
941 
-rOP16(B3M0,     StackRelativeIndirectIndexed,     WRAP_NONE, LDA)
942 
-rOPM (B3Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, LDA)
824 
+		LDWrapper(Registers.A.W, Immediate16Slow);
825 
+}
826 
+
827 
+static void OpA5M1() { rOP8(Direct, LDA8); }
828 
+static void OpA5M0() { rOP16(Direct, LDA16, WRAP_BANK); }
829 
+static void OpA5Slow() { rOPM(DirectSlow, LDA8, LDA16, WRAP_BANK); }
830 
+
831 
+static void OpB5E1() { rOP8(DirectIndexedXE1, LDA8); }
832 
+static void OpB5E0M1() { rOP8(DirectIndexedXE0, LDA8); }
833 
+static void OpB5E0M0() { rOP16(DirectIndexedXE0, LDA16, WRAP_BANK); }
834 
+static void OpB5Slow() { rOPM(DirectIndexedXSlow, LDA8, LDA16, WRAP_BANK); }
835 
+
836 
+static void OpB2E1() { rOP8(DirectIndirectE1, LDA8); }
837 
+static void OpB2E0M1() { rOP8(DirectIndirectE0, LDA8); }
838 
+static void OpB2E0M0() { rOP16(DirectIndirectE0, LDA16); }
839 
+static void OpB2Slow() { rOPM(DirectIndirectSlow, LDA8, LDA16); }
840 
+
841 
+static void OpA1E1() { rOP8(DirectIndexedIndirectE1, LDA8); }
842 
+static void OpA1E0M1() { rOP8(DirectIndexedIndirectE0, LDA8); }
843 
+static void OpA1E0M0() { rOP16(DirectIndexedIndirectE0, LDA16); }
844 
+static void OpA1Slow() { rOPM(DirectIndexedIndirectSlow, LDA8, LDA16); }
845 
+
846 
+static void OpB1E1() { rOP8(DirectIndirectIndexedE1, LDA8); }
847 
+static void OpB1E0M1X1() { rOP8(DirectIndirectIndexedE0X1, LDA8); }
848 
+static void OpB1E0M0X1() { rOP16(DirectIndirectIndexedE0X1, LDA16); }
849 
+static void OpB1E0M1X0() { rOP8(DirectIndirectIndexedE0X0, LDA8); }
850 
+static void OpB1E0M0X0() { rOP16(DirectIndirectIndexedE0X0, LDA16); }
851 
+static void OpB1Slow() { rOPM(DirectIndirectIndexedSlow, LDA8, LDA16); }
852 
+
853 
+static void OpA7M1() { rOP8(DirectIndirectLong, LDA8); }
854 
+static void OpA7M0() { rOP16(DirectIndirectLong, LDA16); }
855 
+static void OpA7Slow() { rOPM(DirectIndirectLongSlow, LDA8, LDA16); }
856 
+
857 
+static void OpB7M1() { rOP8(DirectIndirectIndexedLong, LDA8); }
858 
+static void OpB7M0() { rOP16(DirectIndirectIndexedLong, LDA16); }
859 
+static void OpB7Slow() { rOPM(DirectIndirectIndexedLongSlow, LDA8, LDA16); }
860 
+
861 
+static void OpADM1() { rOP8(Absolute, LDA8); }
862 
+static void OpADM0() { rOP16(Absolute, LDA16); }
863 
+static void OpADSlow() { rOPM(AbsoluteSlow, LDA8, LDA16); }
864 
+
865 
+static void OpBDM1X1() { rOP8(AbsoluteIndexedXX1, LDA8); }
866 
+static void OpBDM0X1() { rOP16(AbsoluteIndexedXX1, LDA16); }
867 
+static void OpBDM1X0() { rOP8(AbsoluteIndexedXX0, LDA8); }
868 
+static void OpBDM0X0() { rOP16(AbsoluteIndexedXX0, LDA16); }
869 
+static void OpBDSlow() { rOPM(AbsoluteIndexedXSlow, LDA8, LDA16); }
870 
+
871 
+static void OpB9M1X1() { rOP8(AbsoluteIndexedYX1, LDA8); }
872 
+static void OpB9M0X1() { rOP16(AbsoluteIndexedYX1, LDA16); }
873 
+static void OpB9M1X0() { rOP8(AbsoluteIndexedYX0, LDA8); }
874 
+static void OpB9M0X0() { rOP16(AbsoluteIndexedYX0, LDA16); }
875 
+static void OpB9Slow() { rOPM(AbsoluteIndexedYSlow, LDA8, LDA16); }
876 
+
877 
+static void OpAFM1() { rOP8(AbsoluteLong, LDA8); }
878 
+static void OpAFM0() { rOP16(AbsoluteLong, LDA16); }
879 
+static void OpAFSlow() { rOPM(AbsoluteLongSlow, LDA8, LDA16); }
880 
+
881 
+static void OpBFM1() { rOP8(AbsoluteLongIndexedX, LDA8); }
882 
+static void OpBFM0() { rOP16(AbsoluteLongIndexedX, LDA16); }
883 
+static void OpBFSlow() { rOPM(AbsoluteLongIndexedXSlow, LDA8, LDA16); }
884 
+
885 
+static void OpA3M1() { rOP8(StackRelative, LDA8); }
886 
+static void OpA3M0() { rOP16(StackRelative, LDA16); }
887 
+static void OpA3Slow() { rOPM(StackRelativeSlow, LDA8, LDA16); }
888 
+
889 
+static void OpB3M1() { rOP8(StackRelativeIndirectIndexed, LDA8); }
890 
+static void OpB3M0() { rOP16(StackRelativeIndirectIndexed, LDA16); }
891 
+static void OpB3Slow() { rOPM(StackRelativeIndirectIndexedSlow, LDA8, LDA16); }
943 892
944 893 
 /* LDX ********************************************************************* */
945 894
946 895 
 static void OpA2X1()
947 896 
 {
948 
-	Registers.XL = Immediate8(READ);
949 
-	SetZN(Registers.XL);
897 
+	LDWrapper(Registers.X.B.l, Immediate8);
950 898 
 }
951 899
952 900 
 static void OpA2X0()
953 901 
 {
954 
-	Registers.X.W = Immediate16(READ);
955 
-	SetZN(Registers.X.W);
902 
+	LDWrapper(Registers.X.W, Immediate16);
956 903 
 }
957 904
958 905 
 static void OpA2Slow()
959 906 
 {
960 907 
 	if (CheckIndex())
961 
-	{
962 
-		Registers.XL = Immediate8Slow(READ);
963 
-		SetZN(Registers.XL);
964 
-	}
908 
+		LDWrapper(Registers.X.B.l, Immediate8Slow);
965 909 
 	else
966 
-	{
967 
-		Registers.X.W = Immediate16Slow(READ);
968 
-		SetZN(Registers.X.W);
969 
-	}
910 
+		LDWrapper(Registers.X.W, Immediate16Slow);
970 911 
 }
971 912
972 
-rOP8 (A6X1,     Direct,                           WRAP_BANK, LDX)
973 
-rOP16(A6X0,     Direct,                           WRAP_BANK, LDX)
974 
-rOPX (A6Slow,   DirectSlow,                       WRAP_BANK, LDX)
913 
+static void OpA6X1() { rOP8(Direct, LDX8); }
914 
+static void OpA6X0() { rOP16(Direct, LDX16, WRAP_BANK); }
915 
+static void OpA6Slow() { rOPX(DirectSlow, LDX8, LDX16, WRAP_BANK); }
975 916
976 
-rOP8 (B6E1,     DirectIndexedYE1,                 WRAP_BANK, LDX)
977 
-rOP8 (B6E0X1,   DirectIndexedYE0,                 WRAP_BANK, LDX)
978 
-rOP16(B6E0X0,   DirectIndexedYE0,                 WRAP_BANK, LDX)
979 
-rOPX (B6Slow,   DirectIndexedYSlow,               WRAP_BANK, LDX)
917 
+static void OpB6E1() { rOP8(DirectIndexedYE1, LDX8); }
918 
+static void OpB6E0X1() { rOP8(DirectIndexedYE0, LDX8); }
919 
+static void OpB6E0X0() { rOP16(DirectIndexedYE0, LDX16, WRAP_BANK); }
920 
+static void OpB6Slow() { rOPX(DirectIndexedYSlow, LDX8, LDX16, WRAP_BANK); }
980 921
981 
-rOP8 (AEX1,     Absolute,                         WRAP_BANK, LDX)
982 
-rOP16(AEX0,     Absolute,                         WRAP_BANK, LDX)
983 
-rOPX (AESlow,   AbsoluteSlow,                     WRAP_BANK, LDX)
922 
+static void OpAEX1() { rOP8(Absolute, LDX8); }
923 
+static void OpAEX0() { rOP16(Absolute, LDX16, WRAP_BANK); }
924 
+static void OpAESlow() { rOPX(AbsoluteSlow, LDX8, LDX16, WRAP_BANK); }
984 925
985 
-rOP8 (BEX1,     AbsoluteIndexedYX1,               WRAP_BANK, LDX)
986 
-rOP16(BEX0,     AbsoluteIndexedYX0,               WRAP_BANK, LDX)
987 
-rOPX (BESlow,   AbsoluteIndexedYSlow,             WRAP_BANK, LDX)
926 
+static void OpBEX1() { rOP8(AbsoluteIndexedYX1, LDX8); }
927 
+static void OpBEX0() { rOP16(AbsoluteIndexedYX0, LDX16, WRAP_BANK); }
928 
+static void OpBESlow() { rOPX(AbsoluteIndexedYSlow, LDX8, LDX16, WRAP_BANK); }
988 929
989 930 
 /* LDY ********************************************************************* */
990 931
991 932 
 static void OpA0X1()
992 933 
 {
993 
-	Registers.YL = Immediate8(READ);
994 
-	SetZN(Registers.YL);
934 
+	LDWrapper(Registers.Y.B.l, Immediate8);
995 935 
 }
996 936
997 937 
 static void OpA0X0()
998 938 
 {
999 
-	Registers.Y.W = Immediate16(READ);
1000 
-	SetZN(Registers.Y.W);
939 
+	LDWrapper(Registers.Y.W, Immediate16);
1001 940 
 }
1002 941
1003 942 
 static void OpA0Slow()
1004 943 
 {
1005 944 
 	if (CheckIndex())
1006 
-	{
1007 
-		Registers.YL = Immediate8Slow(READ);
1008 
-		SetZN(Registers.YL);
1009 
-	}
945 
+		LDWrapper(Registers.Y.B.l, Immediate8Slow);
1010 946 
 	else
1011 
-	{
1012 
-		Registers.Y.W = Immediate16Slow(READ);
1013 
-		SetZN(Registers.Y.W);
1014 
-	}
947 
+		LDWrapper(Registers.Y.W, Immediate16Slow);
1015 948 
 }
1016 949
1017 
-rOP8 (A4X1,     Direct,                           WRAP_BANK, LDY)
1018 
-rOP16(A4X0,     Direct,                           WRAP_BANK, LDY)
1019 
-rOPX (A4Slow,   DirectSlow,                       WRAP_BANK, LDY)
950 
+static void OpA4X1() { rOP8(Direct, LDY8); }
951 
+static void OpA4X0() { rOP16(Direct, LDY16, WRAP_BANK); }
952 
+static void OpA4Slow() { rOPX(DirectSlow, LDY8, LDY16, WRAP_BANK); }
1020 953
1021 
-rOP8 (B4E1,     DirectIndexedXE1,                 WRAP_BANK, LDY)
1022 
-rOP8 (B4E0X1,   DirectIndexedXE0,                 WRAP_BANK, LDY)
1023 
-rOP16(B4E0X0,   DirectIndexedXE0,                 WRAP_BANK, LDY)
1024 
-rOPX (B4Slow,   DirectIndexedXSlow,               WRAP_BANK, LDY)
954 
+static void OpB4E1() { rOP8(DirectIndexedXE1, LDY8); }
955 
+static void OpB4E0X1() { rOP8(DirectIndexedXE0, LDY8); }
956 
+static void OpB4E0X0() { rOP16(DirectIndexedXE0, LDY16, WRAP_BANK); }
957 
+static void OpB4Slow() { rOPX(DirectIndexedXSlow, LDY8, LDY16, WRAP_BANK); }
1025 958
1026 
-rOP8 (ACX1,     Absolute,                         WRAP_BANK, LDY)
1027 
-rOP16(ACX0,     Absolute,                         WRAP_BANK, LDY)
1028 
-rOPX (ACSlow,   AbsoluteSlow,                     WRAP_BANK, LDY)
959 
+static void OpACX1() { rOP8(Absolute, LDY8); }
960 
+static void OpACX0() { rOP16(Absolute, LDY16, WRAP_BANK); }
961 
+static void OpACSlow() { rOPX(AbsoluteSlow, LDY8, LDY16, WRAP_BANK); }
1029 962
1030 
-rOP8 (BCX1,     AbsoluteIndexedXX1,               WRAP_BANK, LDY)
1031 
-rOP16(BCX0,     AbsoluteIndexedXX0,               WRAP_BANK, LDY)
1032 
-rOPX (BCSlow,   AbsoluteIndexedXSlow,             WRAP_BANK, LDY)
963 
+static void OpBCX1() { rOP8(AbsoluteIndexedXX1, LDY8); }
964 
+static void OpBCX0() { rOP16(AbsoluteIndexedXX0, LDY16, WRAP_BANK); }
965 
+static void OpBCSlow() { rOPX(AbsoluteIndexedXSlow, LDY8, LDY16, WRAP_BANK); }
1033 966
1034 967 
 /* LSR ********************************************************************* */
1035 968
1036 
-static void Op4AM1()
969 
+static inline void Op4AM1()
1037 970 
 {
1038 971 
 	AddCycles(ONE_CYCLE);
1039 
-	ICPU._Carry = Registers.AL & 1;
1040 
-	Registers.AL >>= 1;
1041 
-	SetZN(Registers.AL);
972 
+	ICPU._Carry = Registers.A.B.l & 1;
973 
+	Registers.A.B.l >>= 1;
974 
+	SetZN(Registers.A.B.l);
1042 975 
 }
1043 976
1044 
-static void Op4AM0()
977 
+static inline void Op4AM0()
1045 978 
 {
1046 979 
 	AddCycles(ONE_CYCLE);
1047 980 
 	ICPU._Carry = Registers.A.W & 1;
... ... 
@@ -1051,538 +984,524 @@ static void Op4AM0()
1051 984
1052 985 
 static void Op4ASlow()
1053 986 
 {
1054 
-	AddCycles(ONE_CYCLE);
1055 
-
1056 987 
 	if (CheckMemory())
1057 
-	{
1058 
-		ICPU._Carry = Registers.AL & 1;
1059 
-		Registers.AL >>= 1;
1060 
-		SetZN(Registers.AL);
1061 
-	}
988 
+		Op4AM1();
1062 989 
 	else
1063 
-	{
1064 
-		ICPU._Carry = Registers.A.W & 1;
1065 
-		Registers.A.W >>= 1;
1066 
-		SetZN(Registers.A.W);
1067 
-	}
990 
+		Op4AM0();
1068 991 
 }
1069 992
1070 
-mOP8 (46M1,     Direct,                           WRAP_BANK, LSR)
1071 
-mOP16(46M0,     Direct,                           WRAP_BANK, LSR)
1072 
-mOPM (46Slow,   DirectSlow,                       WRAP_BANK, LSR)
993 
+static void Op46M1() { mOP8(Direct, LSR8); }
994 
+static void Op46M0() { mOP16(Direct, LSR16, WRAP_BANK); }
995 
+static void Op46Slow() { mOPM(DirectSlow, LSR8, LSR16, WRAP_BANK); }
1073 996
1074 
-mOP8 (56E1,     DirectIndexedXE1,                 WRAP_BANK, LSR)
1075 
-mOP8 (56E0M1,   DirectIndexedXE0,                 WRAP_BANK, LSR)
1076 
-mOP16(56E0M0,   DirectIndexedXE0,                 WRAP_BANK, LSR)
1077 
-mOPM (56Slow,   DirectIndexedXSlow,               WRAP_BANK, LSR)
997 
+static void Op56E1() { mOP8(DirectIndexedXE1, LSR8); }
998 
+static void Op56E0M1() { mOP8(DirectIndexedXE0, LSR8); }
999 
+static void Op56E0M0() { mOP16(DirectIndexedXE0, LSR16, WRAP_BANK); }
1000 
+static void Op56Slow() { mOPM(DirectIndexedXSlow, LSR8, LSR16, WRAP_BANK); }
1078 1001
1079 
-mOP8 (4EM1,     Absolute,                         WRAP_NONE, LSR)
1080 
-mOP16(4EM0,     Absolute,                         WRAP_NONE, LSR)
1081 
-mOPM (4ESlow,   AbsoluteSlow,                     WRAP_NONE, LSR)
1002 
+static void Op4EM1() { mOP8(Absolute, LSR8); }
1003 
+static void Op4EM0() { mOP16(Absolute, LSR16); }
1004 
+static void Op4ESlow() { mOPM(AbsoluteSlow, LSR8, LSR16); }
1082 1005
1083 
-mOP8 (5EM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, LSR)
1084 
-mOP16(5EM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, LSR)
1085 
-mOP8 (5EM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, LSR)
1086 
-mOP16(5EM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, LSR)
1087 
-mOPM (5ESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, LSR)
1006 
+static void Op5EM1X1() { mOP8(AbsoluteIndexedXX1, LSR8); }
1007 
+static void Op5EM0X1() { mOP16(AbsoluteIndexedXX1, LSR16); }
1008 
+static void Op5EM1X0() { mOP8(AbsoluteIndexedXX0, LSR8); }
1009 
+static void Op5EM0X0() { mOP16(AbsoluteIndexedXX0, LSR16); }
1010 
+static void Op5ESlow() { mOPM(AbsoluteIndexedXSlow, LSR8, LSR16); }
1088 1011
1089 1012 
 /* ORA ********************************************************************* */
1090 1013
1014 
+template<typename T, typename F> static inline void Op09Wrapper(T &reg, F f)
1015 
+{
1016 
+	reg |= f(READ);
1017 
+	SetZN(reg);
1018 
+}
1019 
+
1091 1020 
 static void Op09M1()
1092 1021 
 {
1093 
-	Registers.AL |= Immediate8(READ);
1094 
-	SetZN(Registers.AL);
1022 
+	Op09Wrapper(Registers.A.B.l, Immediate8);
1095 1023 
 }
1096 1024
1097 1025 
 static void Op09M0()
1098 1026 
 {
1099 
-	Registers.A.W |= Immediate16(READ);
1100 
-	SetZN(Registers.A.W);
1027 
+	Op09Wrapper(Registers.A.W, Immediate16);
1101 1028 
 }
1102 1029
1103 1030 
 static void Op09Slow()
1104 1031 
 {
1105 1032 
 	if (CheckMemory())
1106 
-	{
1107 
-		Registers.AL |= Immediate8Slow(READ);
1108 
-		SetZN(Registers.AL);
1109 
-	}
1033 
+		Op09Wrapper(Registers.A.B.l, Immediate8Slow);
1110 1034 
 	else
1111 
-	{
1112 
-		Registers.A.W |= Immediate16Slow(READ);
1113 
-		SetZN(Registers.A.W);
1114 
-	}
1115 
-}
1116 
-
1117 
-rOP8 (05M1,     Direct,                           WRAP_BANK, ORA)
1118 
-rOP16(05M0,     Direct,                           WRAP_BANK, ORA)
1119 
-rOPM (05Slow,   DirectSlow,                       WRAP_BANK, ORA)
1120 
-
1121 
-rOP8 (15E1,     DirectIndexedXE1,                 WRAP_BANK, ORA)
1122 
-rOP8 (15E0M1,   DirectIndexedXE0,                 WRAP_BANK, ORA)
1123 
-rOP16(15E0M0,   DirectIndexedXE0,                 WRAP_BANK, ORA)
1124 
-rOPM (15Slow,   DirectIndexedXSlow,               WRAP_BANK, ORA)
1125 
-
1126 
-rOP8 (12E1,     DirectIndirectE1,                 WRAP_NONE, ORA)
1127 
-rOP8 (12E0M1,   DirectIndirectE0,                 WRAP_NONE, ORA)
1128 
-rOP16(12E0M0,   DirectIndirectE0,                 WRAP_NONE, ORA)
1129 
-rOPM (12Slow,   DirectIndirectSlow,               WRAP_NONE, ORA)
1130 
-
1131 
-rOP8 (01E1,     DirectIndexedIndirectE1,          WRAP_NONE, ORA)
1132 
-rOP8 (01E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, ORA)
1133 
-rOP16(01E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, ORA)
1134 
-rOPM (01Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, ORA)
1135 
-
1136 
-rOP8 (11E1,     DirectIndirectIndexedE1,          WRAP_NONE, ORA)
1137 
-rOP8 (11E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, ORA)
1138 
-rOP16(11E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, ORA)
1139 
-rOP8 (11E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, ORA)
1140 
-rOP16(11E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, ORA)
1141 
-rOPM (11Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, ORA)
1142 
-
1143 
-rOP8 (07M1,     DirectIndirectLong,               WRAP_NONE, ORA)
1144 
-rOP16(07M0,     DirectIndirectLong,               WRAP_NONE, ORA)
1145 
-rOPM (07Slow,   DirectIndirectLongSlow,           WRAP_NONE, ORA)
1146 
-
1147 
-rOP8 (17M1,     DirectIndirectIndexedLong,        WRAP_NONE, ORA)
1148 
-rOP16(17M0,     DirectIndirectIndexedLong,        WRAP_NONE, ORA)
1149 
-rOPM (17Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, ORA)
1150 
-
1151 
-rOP8 (0DM1,     Absolute,                         WRAP_NONE, ORA)
1152 
-rOP16(0DM0,     Absolute,                         WRAP_NONE, ORA)
1153 
-rOPM (0DSlow,   AbsoluteSlow,                     WRAP_NONE, ORA)
1154 
-
1155 
-rOP8 (1DM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, ORA)
1156 
-rOP16(1DM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, ORA)
1157 
-rOP8 (1DM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, ORA)
1158 
-rOP16(1DM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, ORA)
1159 
-rOPM (1DSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, ORA)
1160 
-
1161 
-rOP8 (19M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, ORA)
1162 
-rOP16(19M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, ORA)
1163 
-rOP8 (19M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, ORA)
1164 
-rOP16(19M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, ORA)
1165 
-rOPM (19Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, ORA)
1166 
-
1167 
-rOP8 (0FM1,     AbsoluteLong,                     WRAP_NONE, ORA)
1168 
-rOP16(0FM0,     AbsoluteLong,                     WRAP_NONE, ORA)
1169 
-rOPM (0FSlow,   AbsoluteLongSlow,                 WRAP_NONE, ORA)
1170 
-
1171 
-rOP8 (1FM1,     AbsoluteLongIndexedX,             WRAP_NONE, ORA)
1172 
-rOP16(1FM0,     AbsoluteLongIndexedX,             WRAP_NONE, ORA)
1173 
-rOPM (1FSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, ORA)
1174 
-
1175 
-rOP8 (03M1,     StackRelative,                    WRAP_NONE, ORA)
1176 
-rOP16(03M0,     StackRelative,                    WRAP_NONE, ORA)
1177 
-rOPM (03Slow,   StackRelativeSlow,                WRAP_NONE, ORA)
1178 
-
1179 
-rOP8 (13M1,     StackRelativeIndirectIndexed,     WRAP_NONE, ORA)
1180 
-rOP16(13M0,     StackRelativeIndirectIndexed,     WRAP_NONE, ORA)
1181 
-rOPM (13Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, ORA)
1035 
+		Op09Wrapper(Registers.A.W, Immediate16Slow);
1036 
+}
1037 
+
1038 
+static void Op05M1() { rOP8(Direct, ORA8); }
1039 
+static void Op05M0() { rOP16(Direct, ORA16, WRAP_BANK); }
1040 
+static void Op05Slow() { rOPM(DirectSlow, ORA8, ORA16, WRAP_BANK); }
1041 
+
1042 
+static void Op15E1() { rOP8(DirectIndexedXE1, ORA8); }
1043 
+static void Op15E0M1() { rOP8(DirectIndexedXE0, ORA8); }
1044 
+static void Op15E0M0() { rOP16(DirectIndexedXE0, ORA16, WRAP_BANK); }
1045 
+static void Op15Slow() { rOPM(DirectIndexedXSlow, ORA8, ORA16, WRAP_BANK); }
1046 
+
1047 
+static void Op12E1() { rOP8(DirectIndirectE1, ORA8); }
1048 
+static void Op12E0M1() { rOP8(DirectIndirectE0, ORA8); }
1049 
+static void Op12E0M0() { rOP16(DirectIndirectE0, ORA16); }
1050 
+static void Op12Slow() { rOPM(DirectIndirectSlow, ORA8, ORA16); }
1051 
+
1052 
+static void Op01E1() { rOP8(DirectIndexedIndirectE1, ORA8); }
1053 
+static void Op01E0M1() { rOP8(DirectIndexedIndirectE0, ORA8); }
1054 
+static void Op01E0M0() { rOP16(DirectIndexedIndirectE0, ORA16); }
1055 
+static void Op01Slow() { rOPM(DirectIndexedIndirectSlow, ORA8, ORA16); }
1056 
+
1057 
+static void Op11E1() { rOP8(DirectIndirectIndexedE1, ORA8); }
1058 
+static void Op11E0M1X1() { rOP8(DirectIndirectIndexedE0X1, ORA8); }
1059 
+static void Op11E0M0X1() { rOP16(DirectIndirectIndexedE0X1, ORA16); }
1060 
+static void Op11E0M1X0() { rOP8(DirectIndirectIndexedE0X0, ORA8); }
1061 
+static void Op11E0M0X0() { rOP16(DirectIndirectIndexedE0X0, ORA16); }
1062 
+static void Op11Slow() { rOPM(DirectIndirectIndexedSlow, ORA8, ORA16); }
1063 
+
1064 
+static void Op07M1() { rOP8(DirectIndirectLong, ORA8); }
1065 
+static void Op07M0() { rOP16(DirectIndirectLong, ORA16); }
1066 
+static void Op07Slow() { rOPM(DirectIndirectLongSlow, ORA8, ORA16); }
1067 
+
1068 
+static void Op17M1() { rOP8(DirectIndirectIndexedLong, ORA8); }
1069 
+static void Op17M0() { rOP16(DirectIndirectIndexedLong, ORA16); }
1070 
+static void Op17Slow() { rOPM(DirectIndirectIndexedLongSlow, ORA8, ORA16); }
1071 
+
1072 
+static void Op0DM1() { rOP8(Absolute, ORA8); }
1073 
+static void Op0DM0() { rOP16(Absolute, ORA16); }
1074 
+static void Op0DSlow() { rOPM(AbsoluteSlow, ORA8, ORA16); }
1075 
+
1076 
+static void Op1DM1X1() { rOP8(AbsoluteIndexedXX1, ORA8); }
1077 
+static void Op1DM0X1() { rOP16(AbsoluteIndexedXX1, ORA16); }
1078 
+static void Op1DM1X0() { rOP8(AbsoluteIndexedXX0, ORA8); }
1079 
+static void Op1DM0X0() { rOP16(AbsoluteIndexedXX0, ORA16); }
1080 
+static void Op1DSlow() { rOPM(AbsoluteIndexedXSlow, ORA8, ORA16); }
1081 
+
1082 
+static void Op19M1X1() { rOP8(AbsoluteIndexedYX1, ORA8); }
1083 
+static void Op19M0X1() { rOP16(AbsoluteIndexedYX1, ORA16); }
1084 
+static void Op19M1X0() { rOP8(AbsoluteIndexedYX0, ORA8); }
1085 
+static void Op19M0X0() { rOP16(AbsoluteIndexedYX0, ORA16); }
1086 
+static void Op19Slow() { rOPM(AbsoluteIndexedYSlow, ORA8, ORA16); }
1087 
+
1088 
+static void Op0FM1() { rOP8(AbsoluteLong, ORA8); }
1089 
+static void Op0FM0() { rOP16(AbsoluteLong, ORA16); }
1090 
+static void Op0FSlow() { rOPM(AbsoluteLongSlow, ORA8, ORA16); }
1091 
+
1092 
+static void Op1FM1() { rOP8(AbsoluteLongIndexedX, ORA8); }
1093 
+static void Op1FM0() { rOP16(AbsoluteLongIndexedX, ORA16); }
1094 
+static void Op1FSlow() { rOPM(AbsoluteLongIndexedXSlow, ORA8, ORA16); }
1095 
+
1096 
+static void Op03M1() { rOP8(StackRelative, ORA8); }
1097 
+static void Op03M0() { rOP16(StackRelative, ORA16); }
1098 
+static void Op03Slow() { rOPM(StackRelativeSlow, ORA8, ORA16); }
1099 
+
1100 
+static void Op13M1() { rOP8(StackRelativeIndirectIndexed, ORA8); }
1101 
+static void Op13M0() { rOP16(StackRelativeIndirectIndexed, ORA16); }
1102 
+static void Op13Slow() { rOPM(StackRelativeIndirectIndexedSlow, ORA8, ORA16); }
1182 1103
1183 1104 
 /* ROL ********************************************************************* */
1184 1105
1185 
-static void Op2AM1()
1106 
+static inline void Op2AM1()
1186 1107 
 {
1187 1108 
 	AddCycles(ONE_CYCLE);
1188 
-	uint16_t	w = (((uint16_t) Registers.AL) << 1) | CheckCarry();
1109 
+	uint16_t w = (static_cast<uint16_t>(Registers.A.B.l) << 1) | static_cast<uint16_t>(CheckCarry());
1189 1110 
 	ICPU._Carry = w >= 0x100;
1190 
-	Registers.AL = (uint8_t) w;
1191 
-	SetZN(Registers.AL);
1111 
+	Registers.A.B.l = static_cast<uint8_t>(w);
1112 
+	SetZN(Registers.A.B.l);
1192 1113 
 }
1193 1114
1194 
-static void Op2AM0()
1115 
+static inline void Op2AM0()
1195 1116 
 {
1196 1117 
 	AddCycles(ONE_CYCLE);
1197 
-	uint32_t	w = (((uint32_t) Registers.A.W) << 1) | CheckCarry();
1118 
+	uint32_t w = (static_cast<uint32_t>(Registers.A.W) << 1) | static_cast<uint32_t>(CheckCarry());
1198 1119 
 	ICPU._Carry = w >= 0x10000;
1199 
-	Registers.A.W = (uint16_t) w;
1120 
+	Registers.A.W = static_cast<uint16_t>(w);
1200 1121 
 	SetZN(Registers.A.W);
1201 1122 
 }
1202 1123
1203 1124 
 static void Op2ASlow()
1204 1125 
 {
1205 
-	AddCycles(ONE_CYCLE);
1206 
-
1207 1126 
 	if (CheckMemory())
1208 
-	{
1209 
-		uint16_t	w = (((uint16_t) Registers.AL) << 1) | CheckCarry();
1210 
-		ICPU._Carry = w >= 0x100;
1211 
-		Registers.AL = (uint8_t) w;
1212 
-		SetZN(Registers.AL);
1213 
-	}
1127 
+		Op2AM1();
1214 1128 
 	else
1215 
-	{
1216 
-		uint32_t	w = (((uint32_t) Registers.A.W) << 1) | CheckCarry();
1217 
-		ICPU._Carry = w >= 0x10000;
1218 
-		Registers.A.W = (uint16_t) w;
1219 
-		SetZN(Registers.A.W);
1220 
-	}
1129 
+		Op2AM0();
1221 1130 
 }
1222 1131
1223 
-mOP8 (26M1,     Direct,                           WRAP_BANK, ROL)
1224 
-mOP16(26M0,     Direct,                           WRAP_BANK, ROL)
1225 
-mOPM (26Slow,   DirectSlow,                       WRAP_BANK, ROL)
1132 
+static void Op26M1() { mOP8(Direct, ROL8); }
1133 
+static void Op26M0() { mOP16(Direct, ROL16, WRAP_BANK); }
1134 
+static void Op26Slow() { mOPM(DirectSlow, ROL8, ROL16, WRAP_BANK); }
1226 1135
1227 
-mOP8 (36E1,     DirectIndexedXE1,                 WRAP_BANK, ROL)
1228 
-mOP8 (36E0M1,   DirectIndexedXE0,                 WRAP_BANK, ROL)
1229 
-mOP16(36E0M0,   DirectIndexedXE0,                 WRAP_BANK, ROL)
1230 
-mOPM (36Slow,   DirectIndexedXSlow,               WRAP_BANK, ROL)
1136 
+static void Op36E1() { mOP8(DirectIndexedXE1, ROL8); }
1137 
+static void Op36E0M1() { mOP8(DirectIndexedXE0, ROL8); }
1138 
+static void Op36E0M0() { mOP16(DirectIndexedXE0, ROL16, WRAP_BANK); }
1139 
+static void Op36Slow() { mOPM(DirectIndexedXSlow, ROL8, ROL16, WRAP_BANK); }
1231 1140
1232 
-mOP8 (2EM1,     Absolute,                         WRAP_NONE, ROL)
1233 
-mOP16(2EM0,     Absolute,                         WRAP_NONE, ROL)
1234 
-mOPM (2ESlow,   AbsoluteSlow,                     WRAP_NONE, ROL)
1141 
+static void Op2EM1() { mOP8(Absolute, ROL8); }
1142 
+static void Op2EM0() { mOP16(Absolute, ROL16); }
1143 
+static void Op2ESlow() { mOPM(AbsoluteSlow, ROL8, ROL16); }
1235 1144
1236 
-mOP8 (3EM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, ROL)
1237 
-mOP16(3EM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, ROL)
1238 
-mOP8 (3EM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, ROL)
1239 
-mOP16(3EM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, ROL)
1240 
-mOPM (3ESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, ROL)
1145 
+static void Op3EM1X1() { mOP8(AbsoluteIndexedXX1, ROL8); }
1146 
+static void Op3EM0X1() { mOP16(AbsoluteIndexedXX1, ROL16); }
1147 
+static void Op3EM1X0() { mOP8(AbsoluteIndexedXX0, ROL8); }
1148 
+static void Op3EM0X0() { mOP16(AbsoluteIndexedXX0, ROL16); }
1149 
+static void Op3ESlow() { mOPM(AbsoluteIndexedXSlow, ROL8, ROL16); }
1241 1150
1242 1151 
 /* ROR ********************************************************************* */
1243 1152
1244 
-static void Op6AM1()
1153 
+static inline void Op6AM1()
1245 1154 
 {
1246 1155 
 	AddCycles(ONE_CYCLE);
1247 
-	uint16_t	w = ((uint16_t) Registers.AL) | (((uint16_t) CheckCarry()) << 8);
1156 
+	uint16_t w = static_cast<uint16_t>(Registers.A.B.l) | (static_cast<uint16_t>(CheckCarry()) << 8);
1248 1157 
 	ICPU._Carry = w & 1;
1249 1158 
 	w >>= 1;
1250 
-	Registers.AL = (uint8_t) w;
1251 
-	SetZN(Registers.AL);
1159 
+	Registers.A.B.l = static_cast<uint8_t>(w);
1160 
+	SetZN(Registers.A.B.l);
1252 1161 
 }
1253 1162
1254 
-static void Op6AM0()
1163 
+static inline void Op6AM0()
1255 1164 
 {
1256 1165 
 	AddCycles(ONE_CYCLE);
1257 
-	uint32_t	w = ((uint32_t) Registers.A.W) | (((uint32_t) CheckCarry()) << 16);
1166 
+	uint32_t w = static_cast<uint32_t>(Registers.A.W) | (static_cast<uint32_t>(CheckCarry()) << 16);
1258 1167 
 	ICPU._Carry = w & 1;
1259 1168 
 	w >>= 1;
1260 
-	Registers.A.W = (uint16_t) w;
1169 
+	Registers.A.W = static_cast<uint16_t>(w);
1261 1170 
 	SetZN(Registers.A.W);
1262 1171 
 }
1263 1172
1264 1173 
 static void Op6ASlow()
1265 1174 
 {
1266 
-	AddCycles(ONE_CYCLE);
1267 
-
1268 1175 
 	if (CheckMemory())
1269 
-	{
1270 
-		uint16_t	w = ((uint16_t) Registers.AL) | (((uint16_t) CheckCarry()) << 8);
1271 
-		ICPU._Carry = w & 1;
1272 
-		w >>= 1;
1273 
-		Registers.AL = (uint8_t) w;
1274 
-		SetZN(Registers.AL);
1275 
-	}
1176 
+		Op6AM1();
1276 1177 
 	else
1277 
-	{
1278 
-		uint32_t	w = ((uint32_t) Registers.A.W) | (((uint32_t) CheckCarry()) << 16);
1279 
-		ICPU._Carry = w & 1;
1280 
-		w >>= 1;
1281 
-		Registers.A.W = (uint16_t) w;
1282 
-		SetZN(Registers.A.W);
1283 
-	}
1178 
+		Op6AM0();
1284 1179 
 }
1285 1180
1286 
-mOP8 (66M1,     Direct,                           WRAP_BANK, ROR)
1287 
-mOP16(66M0,     Direct,                           WRAP_BANK, ROR)
1288 
-mOPM (66Slow,   DirectSlow,                       WRAP_BANK, ROR)
1181 
+static void Op66M1() { mOP8(Direct, ROR8); }
1182 
+static void Op66M0() { mOP16(Direct, ROR16, WRAP_BANK); }
1183 
+static void Op66Slow() { mOPM(DirectSlow, ROR8, ROR16, WRAP_BANK); }
1289 1184
1290 
-mOP8 (76E1,     DirectIndexedXE1,                 WRAP_BANK, ROR)
1291 
-mOP8 (76E0M1,   DirectIndexedXE0,                 WRAP_BANK, ROR)
1292 
-mOP16(76E0M0,   DirectIndexedXE0,                 WRAP_BANK, ROR)
1293 
-mOPM (76Slow,   DirectIndexedXSlow,               WRAP_BANK, ROR)
1185 
+static void Op76E1() { mOP8(DirectIndexedXE1, ROR8); }
1186 
+static void Op76E0M1() { mOP8(DirectIndexedXE0, ROR8); }
1187 
+static void Op76E0M0() { mOP16(DirectIndexedXE0, ROR16, WRAP_BANK); }
1188 
+static void Op76Slow() { mOPM(DirectIndexedXSlow, ROR8, ROR16, WRAP_BANK); }
1294 1189
1295 
-mOP8 (6EM1,     Absolute,                         WRAP_NONE, ROR)
1296 
-mOP16(6EM0,     Absolute,                         WRAP_NONE, ROR)
1297 
-mOPM (6ESlow,   AbsoluteSlow,                     WRAP_NONE, ROR)
1190 
+static void Op6EM1() { mOP8(Absolute, ROR8); }
1191 
+static void Op6EM0() { mOP16(Absolute, ROR16); }
1192 
+static void Op6ESlow() { mOPM(AbsoluteSlow, ROR8, ROR16); }
1298 1193
1299 
-mOP8 (7EM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, ROR)
1300 
-mOP16(7EM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, ROR)
1301 
-mOP8 (7EM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, ROR)
1302 
-mOP16(7EM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, ROR)
1303 
-mOPM (7ESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, ROR)
1194 
+static void Op7EM1X1() { mOP8(AbsoluteIndexedXX1, ROR8); }
1195 
+static void Op7EM0X1() { mOP16(AbsoluteIndexedXX1, ROR16); }
1196 
+static void Op7EM1X0() { mOP8(AbsoluteIndexedXX0, ROR8); }
1197 
+static void Op7EM0X0() { mOP16(AbsoluteIndexedXX0, ROR16); }
1198 
+static void Op7ESlow() { mOPM(AbsoluteIndexedXSlow, ROR8, ROR16); }
1304 1199
1305 1200 
 /* SBC ********************************************************************* */
1306 1201
1202 
+template<typename T> static inline void SBC(T Work)
1203 
+{
1204 
+}
1205 
+
1206 
+template<> static inline void SBC<uint16_t>(uint16_t Work16)
1207 
+{
1208 
+	SBC16(Work16);
1209 
+}
1210 
+
1211 
+template<> static inline void SBC<uint8_t>(uint8_t Work8)
1212 
+{
1213 
+	SBC8(Work8);
1214 
+}
1215 
+
1216 
+template<typename F> static inline void OpE9Wrapper(F f)
1217 
+{
1218 
+	SBC(f(READ));
1219 
+}
1220 
+
1307 1221 
 static void OpE9M1()
1308 1222 
 {
1309 
-	SBC(Immediate8(READ));
1223 
+	OpE9Wrapper(Immediate8);
1310 1224 
 }
1311 1225
1312 1226 
 static void OpE9M0()
1313 1227 
 {
1314 
-	SBC(Immediate16(READ));
1228 
+	OpE9Wrapper(Immediate16);
1315 1229 
 }
1316 1230
1317 1231 
 static void OpE9Slow()
1318 1232 
 {
1319 1233 
 	if (CheckMemory())
1320 
-		SBC(Immediate8Slow(READ));
1234 
+		OpE9Wrapper(Immediate8Slow);
1321 1235 
 	else
1322 
-		SBC(Immediate16Slow(READ));
1323 
-}
1324 
-
1325 
-rOP8 (E5M1,     Direct,                           WRAP_BANK, SBC)
1326 
-rOP16(E5M0,     Direct,                           WRAP_BANK, SBC)
1327 
-rOPM (E5Slow,   DirectSlow,                       WRAP_BANK, SBC)
1328 
-
1329 
-rOP8 (F5E1,     DirectIndexedXE1,                 WRAP_BANK, SBC)
1330 
-rOP8 (F5E0M1,   DirectIndexedXE0,                 WRAP_BANK, SBC)
1331 
-rOP16(F5E0M0,   DirectIndexedXE0,                 WRAP_BANK, SBC)
1332 
-rOPM (F5Slow,   DirectIndexedXSlow,               WRAP_BANK, SBC)
1333 
-
1334 
-rOP8 (F2E1,     DirectIndirectE1,                 WRAP_NONE, SBC)
1335 
-rOP8 (F2E0M1,   DirectIndirectE0,                 WRAP_NONE, SBC)
1336 
-rOP16(F2E0M0,   DirectIndirectE0,                 WRAP_NONE, SBC)
1337 
-rOPM (F2Slow,   DirectIndirectSlow,               WRAP_NONE, SBC)
1338 
-
1339 
-rOP8 (E1E1,     DirectIndexedIndirectE1,          WRAP_NONE, SBC)
1340 
-rOP8 (E1E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, SBC)
1341 
-rOP16(E1E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, SBC)
1342 
-rOPM (E1Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, SBC)
1343 
-
1344 
-rOP8 (F1E1,     DirectIndirectIndexedE1,          WRAP_NONE, SBC)
1345 
-rOP8 (F1E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, SBC)
1346 
-rOP16(F1E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, SBC)
1347 
-rOP8 (F1E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, SBC)
1348 
-rOP16(F1E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, SBC)
1349 
-rOPM (F1Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, SBC)
1350 
-
1351 
-rOP8 (E7M1,     DirectIndirectLong,               WRAP_NONE, SBC)
1352 
-rOP16(E7M0,     DirectIndirectLong,               WRAP_NONE, SBC)
1353 
-rOPM (E7Slow,   DirectIndirectLongSlow,           WRAP_NONE, SBC)
1354 
-
1355 
-rOP8 (F7M1,     DirectIndirectIndexedLong,        WRAP_NONE, SBC)
1356 
-rOP16(F7M0,     DirectIndirectIndexedLong,        WRAP_NONE, SBC)
1357 
-rOPM (F7Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, SBC)
1358 
-
1359 
-rOP8 (EDM1,     Absolute,                         WRAP_NONE, SBC)
1360 
-rOP16(EDM0,     Absolute,                         WRAP_NONE, SBC)
1361 
-rOPM (EDSlow,   AbsoluteSlow,                     WRAP_NONE, SBC)
1362 
-
1363 
-rOP8 (FDM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, SBC)
1364 
-rOP16(FDM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, SBC)
1365 
-rOP8 (FDM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, SBC)
1366 
-rOP16(FDM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, SBC)
1367 
-rOPM (FDSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, SBC)
1368 
-
1369 
-rOP8 (F9M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, SBC)
1370 
-rOP16(F9M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, SBC)
1371 
-rOP8 (F9M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, SBC)
1372 
-rOP16(F9M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, SBC)
1373 
-rOPM (F9Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, SBC)
1374 
-
1375 
-rOP8 (EFM1,     AbsoluteLong,                     WRAP_NONE, SBC)
1376 
-rOP16(EFM0,     AbsoluteLong,                     WRAP_NONE, SBC)
1377 
-rOPM (EFSlow,   AbsoluteLongSlow,                 WRAP_NONE, SBC)
1378 
-
1379 
-rOP8 (FFM1,     AbsoluteLongIndexedX,             WRAP_NONE, SBC)
1380 
-rOP16(FFM0,     AbsoluteLongIndexedX,             WRAP_NONE, SBC)
1381 
-rOPM (FFSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, SBC)
1382 
-
1383 
-rOP8 (E3M1,     StackRelative,                    WRAP_NONE, SBC)
1384 
-rOP16(E3M0,     StackRelative,                    WRAP_NONE, SBC)
1385 
-rOPM (E3Slow,   StackRelativeSlow,                WRAP_NONE, SBC)
1386 
-
1387 
-rOP8 (F3M1,     StackRelativeIndirectIndexed,     WRAP_NONE, SBC)
1388 
-rOP16(F3M0,     StackRelativeIndirectIndexed,     WRAP_NONE, SBC)
1389 
-rOPM (F3Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, SBC)
1236 
+		OpE9Wrapper(Immediate16Slow);
1237 
+}
1238 
+
1239 
+static void OpE5M1() { rOP8(Direct, SBC8); }
1240 
+static void OpE5M0() { rOP16(Direct, SBC16, WRAP_BANK); }
1241 
+static void OpE5Slow() { rOPM(DirectSlow, SBC8, SBC16, WRAP_BANK); }
1242 
+
1243 
+static void OpF5E1() { rOP8(DirectIndexedXE1, SBC8); }
1244 
+static void OpF5E0M1() { rOP8(DirectIndexedXE0, SBC8); }
1245 
+static void OpF5E0M0() { rOP16(DirectIndexedXE0, SBC16, WRAP_BANK); }
1246 
+static void OpF5Slow() { rOPM(DirectIndexedXSlow, SBC8, SBC16, WRAP_BANK); }
1247 
+
1248 
+static void OpF2E1() { rOP8(DirectIndirectE1, SBC8); }
1249 
+static void OpF2E0M1() { rOP8(DirectIndirectE0, SBC8); }
1250 
+static void OpF2E0M0() { rOP16(DirectIndirectE0, SBC16); }
1251 
+static void OpF2Slow() { rOPM(DirectIndirectSlow, SBC8, SBC16); }
1252 
+
1253 
+static void OpE1E1() { rOP8(DirectIndexedIndirectE1, SBC8); }
1254 
+static void OpE1E0M1() { rOP8(DirectIndexedIndirectE0, SBC8); }
1255 
+static void OpE1E0M0() { rOP16(DirectIndexedIndirectE0, SBC16); }
1256 
+static void OpE1Slow() { rOPM(DirectIndexedIndirectSlow, SBC8, SBC16); }
1257 
+
1258 
+static void OpF1E1() { rOP8(DirectIndirectIndexedE1, SBC8); }
1259 
+static void OpF1E0M1X1() { rOP8(DirectIndirectIndexedE0X1, SBC8); }
1260 
+static void OpF1E0M0X1() { rOP16(DirectIndirectIndexedE0X1, SBC16); }
1261 
+static void OpF1E0M1X0() { rOP8(DirectIndirectIndexedE0X0, SBC8); }
1262 
+static void OpF1E0M0X0() { rOP16(DirectIndirectIndexedE0X0, SBC16); }
1263 
+static void OpF1Slow() { rOPM(DirectIndirectIndexedSlow, SBC8, SBC16); }
1264 
+
1265 
+static void OpE7M1() { rOP8(DirectIndirectLong, SBC8); }
1266 
+static void OpE7M0() { rOP16(DirectIndirectLong, SBC16); }
1267 
+static void OpE7Slow() { rOPM(DirectIndirectLongSlow, SBC8, SBC16); }
1268 
+
1269 
+static void OpF7M1() { rOP8(DirectIndirectIndexedLong, SBC8); }
1270 
+static void OpF7M0() { rOP16(DirectIndirectIndexedLong, SBC16); }
1271 
+static void OpF7Slow() { rOPM(DirectIndirectIndexedLongSlow, SBC8, SBC16); }
1272 
+
1273 
+static void OpEDM1() { rOP8(Absolute, SBC8); }
1274 
+static void OpEDM0() { rOP16(Absolute, SBC16); }
1275 
+static void OpEDSlow() { rOPM(AbsoluteSlow, SBC8, SBC16); }
1276 
+
1277 
+static void OpFDM1X1() { rOP8(AbsoluteIndexedXX1, SBC8); }
1278 
+static void OpFDM0X1() { rOP16(AbsoluteIndexedXX1, SBC16); }
1279 
+static void OpFDM1X0() { rOP8(AbsoluteIndexedXX0, SBC8); }
1280 
+static void OpFDM0X0() { rOP16(AbsoluteIndexedXX0, SBC16); }
1281 
+static void OpFDSlow() { rOPM(AbsoluteIndexedXSlow, SBC8, SBC16); }
1282 
+
1283 
+static void OpF9M1X1() { rOP8(AbsoluteIndexedYX1, SBC8); }
1284 
+static void OpF9M0X1() { rOP16(AbsoluteIndexedYX1, SBC16); }
1285 
+static void OpF9M1X0() { rOP8(AbsoluteIndexedYX0, SBC8); }
1286 
+static void OpF9M0X0() { rOP16(AbsoluteIndexedYX0, SBC16); }
1287 
+static void OpF9Slow() { rOPM(AbsoluteIndexedYSlow, SBC8, SBC16); }
1288 
+
1289 
+static void OpEFM1() { rOP8(AbsoluteLong, SBC8); }
1290 
+static void OpEFM0() { rOP16(AbsoluteLong, SBC16); }
1291 
+static void OpEFSlow() { rOPM(AbsoluteLongSlow, SBC8, SBC16); }
1292 
+
1293 
+static void OpFFM1() { rOP8(AbsoluteLongIndexedX, SBC8); }
1294 
+static void OpFFM0() { rOP16(AbsoluteLongIndexedX, SBC16); }
1295 
+static void OpFFSlow() { rOPM(AbsoluteLongIndexedXSlow, SBC8, SBC16); }
1296 
+
1297 
+static void OpE3M1() { rOP8(StackRelative, SBC8); }
1298 
+static void OpE3M0() { rOP16(StackRelative, SBC16); }
1299 
+static void OpE3Slow() { rOPM(StackRelativeSlow, SBC8, SBC16); }
1300 
+
1301 
+static void OpF3M1() { rOP8(StackRelativeIndirectIndexed, SBC8); }
1302 
+static void OpF3M0() { rOP16(StackRelativeIndirectIndexed, SBC16); }
1303 
+static void OpF3Slow() { rOPM(StackRelativeIndirectIndexedSlow, SBC8, SBC16); }
1390 1304
1391 1305 
 /* STA ********************************************************************* */
1392 1306
1393 
-wOP8 (85M1,     Direct,                           WRAP_BANK, STA)
1394 
-wOP16(85M0,     Direct,                           WRAP_BANK, STA)
1395 
-wOPM (85Slow,   DirectSlow,                       WRAP_BANK, STA)
1396 
-
1397 
-wOP8 (95E1,     DirectIndexedXE1,                 WRAP_BANK, STA)
1398 
-wOP8 (95E0M1,   DirectIndexedXE0,                 WRAP_BANK, STA)
1399 
-wOP16(95E0M0,   DirectIndexedXE0,                 WRAP_BANK, STA)
1400 
-wOPM (95Slow,   DirectIndexedXSlow,               WRAP_BANK, STA)
1401 
-
1402 
-wOP8 (92E1,     DirectIndirectE1,                 WRAP_NONE, STA)
1403 
-wOP8 (92E0M1,   DirectIndirectE0,                 WRAP_NONE, STA)
1404 
-wOP16(92E0M0,   DirectIndirectE0,                 WRAP_NONE, STA)
1405 
-wOPM (92Slow,   DirectIndirectSlow,               WRAP_NONE, STA)
1406 
-
1407 
-wOP8 (81E1,     DirectIndexedIndirectE1,          WRAP_NONE, STA)
1408 
-wOP8 (81E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, STA)
1409 
-wOP16(81E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, STA)
1410 
-wOPM (81Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, STA)
1411 
-
1412 
-wOP8 (91E1,     DirectIndirectIndexedE1,          WRAP_NONE, STA)
1413 
-wOP8 (91E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, STA)
1414 
-wOP16(91E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, STA)
1415 
-wOP8 (91E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, STA)
1416 
-wOP16(91E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, STA)
1417 
-wOPM (91Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, STA)
1418 
-
1419 
-wOP8 (87M1,     DirectIndirectLong,               WRAP_NONE, STA)
1420 
-wOP16(87M0,     DirectIndirectLong,               WRAP_NONE, STA)
1421 
-wOPM (87Slow,   DirectIndirectLongSlow,           WRAP_NONE, STA)
1422 
-
1423 
-wOP8 (97M1,     DirectIndirectIndexedLong,        WRAP_NONE, STA)
1424 
-wOP16(97M0,     DirectIndirectIndexedLong,        WRAP_NONE, STA)
1425 
-wOPM (97Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, STA)
1426 
-
1427 
-wOP8 (8DM1,     Absolute,                         WRAP_NONE, STA)
1428 
-wOP16(8DM0,     Absolute,                         WRAP_NONE, STA)
1429 
-wOPM (8DSlow,   AbsoluteSlow,                     WRAP_NONE, STA)
1430 
-
1431 
-wOP8 (9DM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, STA)
1432 
-wOP16(9DM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, STA)
1433 
-wOP8 (9DM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, STA)
1434 
-wOP16(9DM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, STA)
1435 
-wOPM (9DSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, STA)
1436 
-
1437 
-wOP8 (99M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, STA)
1438 
-wOP16(99M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, STA)
1439 
-wOP8 (99M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, STA)
1440 
-wOP16(99M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, STA)
1441 
-wOPM (99Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, STA)
1442 
-
1443 
-wOP8 (8FM1,     AbsoluteLong,                     WRAP_NONE, STA)
1444 
-wOP16(8FM0,     AbsoluteLong,                     WRAP_NONE, STA)
1445 
-wOPM (8FSlow,   AbsoluteLongSlow,                 WRAP_NONE, STA)
1446 
-
1447 
-wOP8 (9FM1,     AbsoluteLongIndexedX,             WRAP_NONE, STA)
1448 
-wOP16(9FM0,     AbsoluteLongIndexedX,             WRAP_NONE, STA)
1449 
-wOPM (9FSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, STA)
1450 
-
1451 
-wOP8 (83M1,     StackRelative,                    WRAP_NONE, STA)
1452 
-wOP16(83M0,     StackRelative,                    WRAP_NONE, STA)
1453 
-wOPM (83Slow,   StackRelativeSlow,                WRAP_NONE, STA)
1454 
-
1455 
-wOP8 (93M1,     StackRelativeIndirectIndexed,     WRAP_NONE, STA)
1456 
-wOP16(93M0,     StackRelativeIndirectIndexed,     WRAP_NONE, STA)
1457 
-wOPM (93Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, STA)
1307 
+static void Op85M1() { wOP8(Direct, STA8); }
1308 
+static void Op85M0() { wOP16(Direct, STA16, WRAP_BANK); }
1309 
+static void Op85Slow() { wOPM(DirectSlow, STA8, STA16, WRAP_BANK); }
1310 
+
1311 
+static void Op95E1() { wOP8(DirectIndexedXE1, STA8); }
1312 
+static void Op95E0M1() { wOP8(DirectIndexedXE0, STA8); }
1313 
+static void Op95E0M0() { wOP16(DirectIndexedXE0, STA16, WRAP_BANK); }
1314 
+static void Op95Slow() { wOPM(DirectIndexedXSlow, STA8, STA16, WRAP_BANK); }
1315 
+
1316 
+static void Op92E1() { wOP8(DirectIndirectE1, STA8); }
1317 
+static void Op92E0M1() { wOP8(DirectIndirectE0, STA8); }
1318 
+static void Op92E0M0() { wOP16(DirectIndirectE0, STA16); }
1319 
+static void Op92Slow() { wOPM(DirectIndirectSlow, STA8, STA16); }
1320 
+
1321 
+static void Op81E1() { wOP8(DirectIndexedIndirectE1, STA8); }
1322 
+static void Op81E0M1() { wOP8(DirectIndexedIndirectE0, STA8); }
1323 
+static void Op81E0M0() { wOP16(DirectIndexedIndirectE0, STA16); }
1324 
+static void Op81Slow() { wOPM(DirectIndexedIndirectSlow, STA8, STA16); }
1325 
+
1326 
+static void Op91E1() { wOP8(DirectIndirectIndexedE1, STA8); }
1327 
+static void Op91E0M1X1() { wOP8(DirectIndirectIndexedE0X1, STA8); }
1328 
+static void Op91E0M0X1() { wOP16(DirectIndirectIndexedE0X1, STA16); }
1329 
+static void Op91E0M1X0() { wOP8(DirectIndirectIndexedE0X0, STA8); }
1330 
+static void Op91E0M0X0() { wOP16(DirectIndirectIndexedE0X0, STA16); }
1331 
+static void Op91Slow() { wOPM(DirectIndirectIndexedSlow, STA8, STA16); }
1332 
+
1333 
+static void Op87M1() { wOP8(DirectIndirectLong, STA8); }
1334 
+static void Op87M0() { wOP16(DirectIndirectLong, STA16); }
1335 
+static void Op87Slow() { wOPM(DirectIndirectLongSlow, STA8, STA16); }
1336 
+
1337 
+static void Op97M1() { wOP8(DirectIndirectIndexedLong, STA8); }
1338 
+static void Op97M0() { wOP16(DirectIndirectIndexedLong, STA16); }
1339 
+static void Op97Slow() { wOPM(DirectIndirectIndexedLongSlow, STA8, STA16); }
1340 
+
1341 
+static void Op8DM1() { wOP8(Absolute, STA8); }
1342 
+static void Op8DM0() { wOP16(Absolute, STA16); }
1343 
+static void Op8DSlow() { wOPM(AbsoluteSlow, STA8, STA16); }
1344 
+
1345 
+static void Op9DM1X1() { wOP8(AbsoluteIndexedXX1, STA8); }
1346 
+static void Op9DM0X1() { wOP16(AbsoluteIndexedXX1, STA16); }
1347 
+static void Op9DM1X0() { wOP8(AbsoluteIndexedXX0, STA8); }
1348 
+static void Op9DM0X0() { wOP16(AbsoluteIndexedXX0, STA16); }
1349 
+static void Op9DSlow() { wOPM(AbsoluteIndexedXSlow, STA8, STA16); }
1350 
+
1351 
+static void Op99M1X1() { wOP8(AbsoluteIndexedYX1, STA8); }
1352 
+static void Op99M0X1() { wOP16(AbsoluteIndexedYX1, STA16); }
1353 
+static void Op99M1X0() { wOP8(AbsoluteIndexedYX0, STA8); }
1354 
+static void Op99M0X0() { wOP16(AbsoluteIndexedYX0, STA16); }
1355 
+static void Op99Slow() { wOPM(AbsoluteIndexedYSlow, STA8, STA16); }
1356 
+
1357 
+static void Op8FM1() { wOP8(AbsoluteLong, STA8); }
1358 
+static void Op8FM0() { wOP16(AbsoluteLong, STA16); }
1359 
+static void Op8FSlow() { wOPM(AbsoluteLongSlow, STA8, STA16); }
1360 
+
1361 
+static void Op9FM1() { wOP8(AbsoluteLongIndexedX, STA8); }
1362 
+static void Op9FM0() { wOP16(AbsoluteLongIndexedX, STA16); }
1363 
+static void Op9FSlow() { wOPM(AbsoluteLongIndexedXSlow, STA8, STA16); }
1364 
+
1365 
+static void Op83M1() { wOP8(StackRelative, STA8); }
1366 
+static void Op83M0() { wOP16(StackRelative, STA16); }
1367 
+static void Op83Slow() { wOPM(StackRelativeSlow, STA8, STA16); }
1368 
+
1369 
+static void Op93M1() { wOP8(StackRelativeIndirectIndexed, STA8); }
1370 
+static void Op93M0() { wOP16(StackRelativeIndirectIndexed, STA16); }
1371 
+static void Op93Slow() { wOPM(StackRelativeIndirectIndexedSlow, STA8, STA16); }
1458 1372
1459 1373 
 /* STX ********************************************************************* */
1460 1374
1461 
-wOP8 (86X1,     Direct,                           WRAP_BANK, STX)
1462 
-wOP16(86X0,     Direct,                           WRAP_BANK, STX)
1463 
-wOPX (86Slow,   DirectSlow,                       WRAP_BANK, STX)
1375 
+static void Op86X1() { wOP8(Direct, STX8); }
1376 
+static void Op86X0() { wOP16(Direct, STX16, WRAP_BANK); }
1377 
+static void Op86Slow() { wOPX(DirectSlow, STX8, STX16, WRAP_BANK); }
1464 1378
1465 
-wOP8 (96E1,     DirectIndexedYE1,                 WRAP_BANK, STX)
1466 
-wOP8 (96E0X1,   DirectIndexedYE0,                 WRAP_BANK, STX)
1467 
-wOP16(96E0X0,   DirectIndexedYE0,                 WRAP_BANK, STX)
1468 
-wOPX (96Slow,   DirectIndexedYSlow,               WRAP_BANK, STX)
1379 
+static void Op96E1() { wOP8(DirectIndexedYE1, STX8); }
1380 
+static void Op96E0X1() { wOP8(DirectIndexedYE0, STX8); }
1381 
+static void Op96E0X0() { wOP16(DirectIndexedYE0, STX16, WRAP_BANK); }
1382 
+static void Op96Slow() { wOPX(DirectIndexedYSlow, STX8, STX16, WRAP_BANK); }
1469 1383
1470 
-wOP8 (8EX1,     Absolute,                         WRAP_BANK, STX)
1471 
-wOP16(8EX0,     Absolute,                         WRAP_BANK, STX)
1472 
-wOPX (8ESlow,   AbsoluteSlow,                     WRAP_BANK, STX)
1384 
+static void Op8EX1() { wOP8(Absolute, STX8); }
1385 
+static void Op8EX0() { wOP16(Absolute, STX16, WRAP_BANK); }
1386 
+static void Op8ESlow() { wOPX(AbsoluteSlow, STX8, STX16, WRAP_BANK); }
1473 1387
1474 1388 
 /* STY ********************************************************************* */
1475 1389
1476 
-wOP8 (84X1,     Direct,                           WRAP_BANK, STY)
1477 
-wOP16(84X0,     Direct,                           WRAP_BANK, STY)
1478 
-wOPX (84Slow,   DirectSlow,                       WRAP_BANK, STY)
1390 
+static void Op84X1() { wOP8(Direct, STY8); }
1391 
+static void Op84X0() { wOP16(Direct, STY16, WRAP_BANK); }
1392 
+static void Op84Slow() { wOPX(DirectSlow, STY8, STY16, WRAP_BANK); }
1479 1393
1480 
-wOP8 (94E1,     DirectIndexedXE1,                 WRAP_BANK, STY)
1481 
-wOP8 (94E0X1,   DirectIndexedXE0,                 WRAP_BANK, STY)
1482 
-wOP16(94E0X0,   DirectIndexedXE0,                 WRAP_BANK, STY)
1483 
-wOPX (94Slow,   DirectIndexedXSlow,               WRAP_BANK, STY)
1394 
+static void Op94E1() { wOP8(DirectIndexedXE1, STY8); }
1395 
+static void Op94E0X1() { wOP8(DirectIndexedXE0, STY8); }
1396 
+static void Op94E0X0() { wOP16(DirectIndexedXE0, STY16, WRAP_BANK); }
1397 
+static void Op94Slow() { wOPX(DirectIndexedXSlow, STY8, STY16, WRAP_BANK); }
1484 1398
1485 
-wOP8 (8CX1,     Absolute,                         WRAP_BANK, STY)
1486 
-wOP16(8CX0,     Absolute,                         WRAP_BANK, STY)
1487 
-wOPX (8CSlow,   AbsoluteSlow,                     WRAP_BANK, STY)
1399 
+static void Op8CX1() { wOP8(Absolute, STY8); }
1400 
+static void Op8CX0() { wOP16(Absolute, STY16, WRAP_BANK); }
1401 
+static void Op8CSlow() { wOPX(AbsoluteSlow, STY8, STY16, WRAP_BANK); }
1488 1402
1489 1403 
 /* STZ ********************************************************************* */
1490 1404
1491 
-wOP8 (64M1,     Direct,                           WRAP_BANK, STZ)
1492 
-wOP16(64M0,     Direct,                           WRAP_BANK, STZ)
1493 
-wOPM (64Slow,   DirectSlow,                       WRAP_BANK, STZ)
1405 
+static void Op64M1() { wOP8(Direct, STZ8); }
1406 
+static void Op64M0() { wOP16(Direct, STZ16, WRAP_BANK); }
1407 
+static void Op64Slow() { wOPM(DirectSlow, STZ8, STZ16, WRAP_BANK); }
1494 1408
1495 
-wOP8 (74E1,     DirectIndexedXE1,                 WRAP_BANK, STZ)
1496 
-wOP8 (74E0M1,   DirectIndexedXE0,                 WRAP_BANK, STZ)
1497 
-wOP16(74E0M0,   DirectIndexedXE0,                 WRAP_BANK, STZ)
1498 
-wOPM (74Slow,   DirectIndexedXSlow,               WRAP_BANK, STZ)
1409 
+static void Op74E1() { wOP8(DirectIndexedXE1, STZ8); }
1410 
+static void Op74E0M1() { wOP8(DirectIndexedXE0, STZ8); }
1411 
+static void Op74E0M0() { wOP16(DirectIndexedXE0, STZ16, WRAP_BANK); }
1412 
+static void Op74Slow() { wOPM(DirectIndexedXSlow, STZ8, STZ16, WRAP_BANK); }
1499 1413
1500 
-wOP8 (9CM1,     Absolute,                         WRAP_NONE, STZ)
1501 
-wOP16(9CM0,     Absolute,                         WRAP_NONE, STZ)
1502 
-wOPM (9CSlow,   AbsoluteSlow,                     WRAP_NONE, STZ)
1414 
+static void Op9CM1() { wOP8(Absolute, STZ8); }
1415 
+static void Op9CM0() { wOP16(Absolute, STZ16); }
1416 
+static void Op9CSlow() { wOPM(AbsoluteSlow, STZ8, STZ16); }
1503 1417
1504 
-wOP8 (9EM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, STZ)
1505 
-wOP16(9EM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, STZ)
1506 
-wOP8 (9EM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, STZ)
1507 
-wOP16(9EM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, STZ)
1508 
-wOPM (9ESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, STZ)
1418 
+static void Op9EM1X1() { wOP8(AbsoluteIndexedXX1, STZ8); }
1419 
+static void Op9EM0X1() { wOP16(AbsoluteIndexedXX1, STZ16); }
1420 
+static void Op9EM1X0() { wOP8(AbsoluteIndexedXX0, STZ8); }
1421 
+static void Op9EM0X0() { wOP16(AbsoluteIndexedXX0, STZ16); }
1422 
+static void Op9ESlow() { wOPM(AbsoluteIndexedXSlow, STZ8, STZ16); }
1509 1423
1510 1424 
 /* TRB ********************************************************************* */
1511 1425
1512 
-mOP8 (14M1,     Direct,                           WRAP_BANK, TRB)
1513 
-mOP16(14M0,     Direct,                           WRAP_BANK, TRB)
1514 
-mOPM (14Slow,   DirectSlow,                       WRAP_BANK, TRB)
1426 
+static void Op14M1() { mOP8(Direct, TRB8); }
1427 
+static void Op14M0() { mOP16(Direct, TRB16, WRAP_BANK); }
1428 
+static void Op14Slow() { mOPM(DirectSlow, TRB8, TRB16, WRAP_BANK); }
1515 1429
1516 
-mOP8 (1CM1,     Absolute,                         WRAP_BANK, TRB)
1517 
-mOP16(1CM0,     Absolute,                         WRAP_BANK, TRB)
1518 
-mOPM (1CSlow,   AbsoluteSlow,                     WRAP_BANK, TRB)
1430 
+static void Op1CM1() { mOP8(Absolute, TRB8); }
1431 
+static void Op1CM0() { mOP16(Absolute, TRB16, WRAP_BANK); }
1432 
+static void Op1CSlow() { mOPM(AbsoluteSlow, TRB8, TRB16, WRAP_BANK); }
1519 1433
1520 1434 
 /* TSB ********************************************************************* */
1521 1435
1522 
-mOP8 (04M1,     Direct,                           WRAP_BANK, TSB)
1523 
-mOP16(04M0,     Direct,                           WRAP_BANK, TSB)
1524 
-mOPM (04Slow,   DirectSlow,                       WRAP_BANK, TSB)
1436 
+static void Op04M1() { mOP8(Direct, TSB8); }
1437 
+static void Op04M0() { mOP16(Direct, TSB16, WRAP_BANK); }
1438 
+static void Op04Slow() { mOPM(DirectSlow, TSB8, TSB16, WRAP_BANK); }
1525 1439
1526 
-mOP8 (0CM1,     Absolute,                         WRAP_BANK, TSB)
1527 
-mOP16(0CM0,     Absolute,                         WRAP_BANK, TSB)
1528 
-mOPM (0CSlow,   AbsoluteSlow,                     WRAP_BANK, TSB)
1440 
+static void Op0CM1() { mOP8(Absolute, TSB8); }
1441 
+static void Op0CM0() { mOP16(Absolute, TSB16, WRAP_BANK); }
1442 
+static void Op0CSlow() { mOPM(AbsoluteSlow, TSB8, TSB16, WRAP_BANK); }
1529 1443
1530 1444 
 /* Branch Instructions ***************************************************** */
1531 1445
1532 1446 
 // BCC
1533 
-bOP(90E0,   Relative,     !CheckCarry(),    0, 0)
1534 
-bOP(90E1,   Relative,     !CheckCarry(),    0, 1)
1535 
-bOP(90Slow, RelativeSlow, !CheckCarry(),    0, CheckEmulation())
1447 
+static void Op90E0() { bOP(Relative, !CheckCarry(), false); }
1448 
+static void Op90E1() { bOP(Relative, !CheckCarry(), true); }
1449 
+static void Op90Slow() { bOP(RelativeSlow, !CheckCarry(), CheckEmulation()); }
1536 1450
1537 1451 
 // BCS
1538 
-bOP(B0E0,   Relative,      CheckCarry(),    0, 0)
1539 
-bOP(B0E1,   Relative,      CheckCarry(),    0, 1)
1540 
-bOP(B0Slow, RelativeSlow,  CheckCarry(),    0, CheckEmulation())
1452 
+static void OpB0E0() { bOP(Relative, CheckCarry(), false); }
1453 
+static void OpB0E1() { bOP(Relative, CheckCarry(), true); }
1454 
+static void OpB0Slow() { bOP(RelativeSlow, CheckCarry(), CheckEmulation()); }
1541 1455
1542 1456 
 // BEQ
1543 
-bOP(F0E0,   Relative,      CheckZero(),     2, 0)
1544 
-bOP(F0E1,   Relative,      CheckZero(),     2, 1)
1545 
-bOP(F0Slow, RelativeSlow,  CheckZero(),     2, CheckEmulation())
1457 
+static void OpF0E0() { bOP(Relative, CheckZero(), false); }
1458 
+static void OpF0E1() { bOP(Relative, CheckZero(), true); }
1459 
+static void OpF0Slow() { bOP(RelativeSlow, CheckZero(), CheckEmulation()); }
1546 1460
1547 1461 
 // BMI
1548 
-bOP(30E0,   Relative,      CheckNegative(), 1, 0)
1549 
-bOP(30E1,   Relative,      CheckNegative(), 1, 1)
1550 
-bOP(30Slow, RelativeSlow,  CheckNegative(), 1, CheckEmulation())
1462 
+static void Op30E0() { bOP(Relative, CheckNegative(), false); }
1463 
+static void Op30E1() { bOP(Relative, CheckNegative(), true); }
1464 
+static void Op30Slow() { bOP(RelativeSlow, CheckNegative(), CheckEmulation()); }
1551 1465
1552 1466 
 // BNE
1553 
-bOP(D0E0,   Relative,     !CheckZero(),     1, 0)
1554 
-bOP(D0E1,   Relative,     !CheckZero(),     1, 1)
1555 
-bOP(D0Slow, RelativeSlow, !CheckZero(),     1, CheckEmulation())
1467 
+static void OpD0E0() { bOP(Relative, !CheckZero(), false); }
1468 
+static void OpD0E1() { bOP(Relative, !CheckZero(), true); }
1469 
+static void OpD0Slow() { bOP(RelativeSlow, !CheckZero(), CheckEmulation()); }
1556 1470
1557 1471 
 // BPL
1558 
-bOP(10E0,   Relative,     !CheckNegative(), 1, 0)
1559 
-bOP(10E1,   Relative,     !CheckNegative(), 1, 1)
1560 
-bOP(10Slow, RelativeSlow, !CheckNegative(), 1, CheckEmulation())
1472 
+static void Op10E0() { bOP(Relative, !CheckNegative(), false); }
1473 
+static void Op10E1() { bOP(Relative, !CheckNegative(), true); }
1474 
+static void Op10Slow() { bOP(RelativeSlow, !CheckNegative(), CheckEmulation()); }
1561 1475
1562 1476 
 // BRA
1563 
-bOP(80E0,   Relative,     1,                X, 0)
1564 
-bOP(80E1,   Relative,     1,                X, 1)
1565 
-bOP(80Slow, RelativeSlow, 1,                X, CheckEmulation())
1477 
+static void Op80E0() { bOP(Relative, true, false); }
1478 
+static void Op80E1() { bOP(Relative, true, true); }
1479 
+static void Op80Slow() { bOP(RelativeSlow, true, CheckEmulation()); }
1566 1480
1567 1481 
 // BVC
1568 
-bOP(50E0,   Relative,     !CheckOverflow(), 0, 0)
1569 
-bOP(50E1,   Relative,     !CheckOverflow(), 0, 1)
1570 
-bOP(50Slow, RelativeSlow, !CheckOverflow(), 0, CheckEmulation())
1482 
+static void Op50E0() { bOP(Relative, !CheckOverflow(), false); }
1483 
+static void Op50E1() { bOP(Relative, !CheckOverflow(), true); }
1484 
+static void Op50Slow() { bOP(RelativeSlow, !CheckOverflow(), CheckEmulation()); }
1571 1485
1572 1486 
 // BVS
1573 
-bOP(70E0,   Relative,      CheckOverflow(), 0, 0)
1574 
-bOP(70E1,   Relative,      CheckOverflow(), 0, 1)
1575 
-bOP(70Slow, RelativeSlow,  CheckOverflow(), 0, CheckEmulation())
1487 
+static void Op70E0() { bOP(Relative, CheckOverflow(), false); }
1488 
+static void Op70E1() { bOP(Relative, CheckOverflow(), true); }
1489 
+static void Op70Slow() { bOP(RelativeSlow, CheckOverflow(), CheckEmulation()); }
1576 1490
1577 1491 
 // BRL
1492 
+template<typename F> static inline void Op82Wrapper(F f)
1493 
+{
1494 
+	S9xSetPCBase(ICPU.ShiftedPB + f(JUMP));
1495 
+}
1496 
+
1578 1497 
 static void Op82()
1579 1498 
 {
1580 
-	S9xSetPCBase(ICPU.ShiftedPB + RelativeLong(JUMP));
1499 
+	Op82Wrapper(RelativeLong);
1581 1500 
 }
1582 1501
1583 1502 
 static void Op82Slow()
1584 1503 
 {
1585 
-	S9xSetPCBase(ICPU.ShiftedPB + RelativeLongSlow(JUMP));
1504 
+	Op82Wrapper(RelativeLongSlow);
1586 1505 
 }
1587 1506
1588 1507 
 /* Flag Instructions ******************************************************* */
... ... 
@@ -1613,9 +1532,6 @@ static void OpF8()
1613 1532 
 {
1614 1533 
 	SetDecimal();
1615 1534 
 	AddCycles(ONE_CYCLE);
1616 
-#ifdef DEBUGGER
1617 
-	missing.decimal_mode = 1;
1618 
-#endif
1619 1535 
 }
1620 1536
1621 1537 
 // CLI
... ... 
@@ -1623,7 +1539,6 @@ static void Op58()
1623 1539 
 {
1624 1540 
 	ClearIRQ();
1625 1541 
 	AddCycles(ONE_CYCLE);
1626 
-	CHECK_FOR_IRQ();
1627 1542 
 }
1628 1543
1629 1544 
 // SEI
... ... 
@@ -1642,126 +1557,92 @@ static void OpB8()
1642 1557
1643 1558 
 /* DEX/DEY ***************************************************************** */
1644 1559
1645 
-static void OpCAX1()
1560 
+template<typename T> static inline void DEWrapper(T &reg)
1646 1561 
 {
1647 1562 
 	AddCycles(ONE_CYCLE);
1648 
-	Registers.XL--;
1649 
-	SetZN(Registers.XL);
1563 
+	--reg;
1564 
+	SetZN(reg);
1650 1565 
 }
1651 1566
1652 
-static void OpCAX0()
1567 
+static inline void OpCAX1()
1653 1568 
 {
1654 
-	AddCycles(ONE_CYCLE);
1655 
-	Registers.X.W--;
1656 
-	SetZN(Registers.X.W);
1569 
+	DEWrapper(Registers.X.B.l);
1657 1570 
 }
1658 1571
1659 
-static void OpCASlow()
1572 
+static inline void OpCAX0()
1660 1573 
 {
1661 
-	AddCycles(ONE_CYCLE);
1574 
+	DEWrapper(Registers.X.W);
1575 
+}
1662 1576
1577 
+static void OpCASlow()
1578 
+{
1663 1579 
 	if (CheckIndex())
1664 
-	{
1665 
-		Registers.XL--;
1666 
-		SetZN(Registers.XL);
1667 
-	}
1580 
+		OpCAX1();
1668 1581 
 	else
1669 
-	{
1670 
-		Registers.X.W--;
1671 
-		SetZN(Registers.X.W);
1672 
-	}
1582 
+		OpCAX0();
1673 1583 
 }
1674 1584
1675 
-static void Op88X1()
1585 
+static inline void Op88X1()
1676 1586 
 {
1677 
-	AddCycles(ONE_CYCLE);
1678 
-	Registers.YL--;
1679 
-	SetZN(Registers.YL);
1587 
+	DEWrapper(Registers.Y.B.l);
1680 1588 
 }
1681 1589
1682 
-static void Op88X0()
1590 
+static inline void Op88X0()
1683 1591 
 {
1684 
-	AddCycles(ONE_CYCLE);
1685 
-	Registers.Y.W--;
1686 
-	SetZN(Registers.Y.W);
1592 
+	DEWrapper(Registers.Y.W);
1687 1593 
 }
1688 1594
1689 1595 
 static void Op88Slow()
1690 1596 
 {
1691 
-	AddCycles(ONE_CYCLE);
1692 
-
1693 1597 
 	if (CheckIndex())
1694 
-	{
1695 
-		Registers.YL--;
1696 
-		SetZN(Registers.YL);
1697 
-	}
1598 
+		Op88X1();
1698 1599 
 	else
1699 
-	{
1700 
-		Registers.Y.W--;
1701 
-		SetZN(Registers.Y.W);
1702 
-	}
1600 
+		Op88X0();
1703 1601 
 }
1704 1602
1705 1603 
 /* INX/INY ***************************************************************** */
1706 1604
1707 
-static void OpE8X1()
1605 
+template<typename T> static inline void INWrapper(T &reg)
1708 1606 
 {
1709 1607 
 	AddCycles(ONE_CYCLE);
1710 
-	Registers.XL++;
1711 
-	SetZN(Registers.XL);
1608 
+	++reg;
1609 
+	SetZN(reg);
1712 1610 
 }
1713 1611
1714 
-static void OpE8X0()
1612 
+static inline void OpE8X1()
1715 1613 
 {
1716 
-	AddCycles(ONE_CYCLE);
1717 
-	Registers.X.W++;
1718 
-	SetZN(Registers.X.W);
1614 
+	INWrapper(Registers.X.B.l);
1719 1615 
 }
1720 1616
1721 
-static void OpE8Slow()
1617 
+static inline void OpE8X0()
1722 1618 
 {
1723 
-	AddCycles(ONE_CYCLE);
1619 
+	INWrapper(Registers.X.W);
1620 
+}
1724 1621
1622 
+static void OpE8Slow()
1623 
+{
1725 1624 
 	if (CheckIndex())
1726 
-	{
1727 
-		Registers.XL++;
1728 
-		SetZN(Registers.XL);
1729 
-	}
1625 
+		OpE8X1();
1730 1626 
 	else
1731 
-	{
1732 
-		Registers.X.W++;
1733 
-		SetZN(Registers.X.W);
1734 
-	}
1627 
+		OpE8X0();
1735 1628 
 }
1736 1629
1737 
-static void OpC8X1()
1630 
+static inline void OpC8X1()
1738 1631 
 {
1739 
-	AddCycles(ONE_CYCLE);
1740 
-	Registers.YL++;
1741 
-	SetZN(Registers.YL);
1632 
+	INWrapper(Registers.Y.B.l);
1742 1633 
 }
1743 1634
1744 
-static void OpC8X0()
1635 
+static inline void OpC8X0()
1745 1636 
 {
1746 
-	AddCycles(ONE_CYCLE);
1747 
-	Registers.Y.W++;
1748 
-	SetZN(Registers.Y.W);
1637 
+	INWrapper(Registers.Y.W);
1749 1638 
 }
1750 1639
1751 1640 
 static void OpC8Slow()
1752 1641 
 {
1753 
-	AddCycles(ONE_CYCLE);
1754 
-
1755 1642 
 	if (CheckIndex())
1756 
-	{
1757 
-		Registers.YL--;
1758 
-		SetZN(Registers.YL);
1759 
-	}
1643 
+		OpC8X1();
1760 1644 
 	else
1761 
-	{
1762 
-		Registers.Y.W--;
1763 
-		SetZN(Registers.Y.W);
1764 
-	}
1645 
+		OpC8X0();
1765 1646 
 }
1766 1647
1767 1648 
 /* NOP ********************************************************************* */
... ... 
@@ -1773,517 +1654,395 @@ static void OpEA()
1773 1654
1774 1655 
 /* PUSH Instructions ******************************************************* */
1775 1656
1776 
-#define PushW(w) \
1777 
-	S9xSetWord(w, Registers.S.W - 1, WRAP_BANK, WRITE_10); \
1657 
+static inline void PushW(uint16_t w)
1658 
+{
1659 
+	S9xSetWord(w, Registers.S.W - 1, WRAP_BANK, WRITE_10);
1778 1660 
 	Registers.S.W -= 2;
1661 
+}
1779 1662
1780 
-#define PushWE(w) \
1781 
-	Registers.SL--; \
1782 
-	S9xSetWord(w, Registers.S.W, WRAP_PAGE, WRITE_10); \
1783 
-	Registers.SL--;
1663 
+static inline void PushWE(uint16_t w)
1664 
+{
1665 
+	--Registers.S.B.l;
1666 
+	S9xSetWord(w, Registers.S.W, WRAP_PAGE, WRITE_10);
1667 
+	--Registers.S.B.l;
1668 
+}
1784 1669
1785 
-#define PushB(b) \
1670 
+static inline void PushB(uint8_t b)
1671 
+{
1786 1672 
 	S9xSetByte(b, Registers.S.W--);
1673 
+}
1787 1674
1788 
-#define PushBE(b) \
1789 
-	S9xSetByte(b, Registers.S.W); \
1790 
-	Registers.SL--;
1675 
+static inline void PushBE(uint8_t b)
1676 
+{
1677 
+	S9xSetByte(b, Registers.S.W);
1678 
+	--Registers.S.B.l;
1679 
+}
1791 1680
1792 
-// PEA
1793 
-static void OpF4E0()
1681 
+template<typename F> static inline void PEWrapper(F f, bool cond)
1794 1682 
 {
1795 
-	uint16_t	val = (uint16_t) Absolute(NONE);
1683 
+	uint16_t val = static_cast<uint16_t>(f(NONE));
1796 1684 
 	PushW(val);
1797 1685 
 	OpenBus = val & 0xff;
1686 
+	if (cond)
1687 
+		Registers.S.B.h = 1;
1688 
+}
1689 
+
1690 
+// PEA
1691 
+static void OpF4E0()
1692 
+{
1693 
+	PEWrapper(Absolute, false);
1798 1694 
 }
1799 1695
1800 1696 
 static void OpF4E1()
1801 1697 
 {
1802 1698 
 	// Note: PEA is a new instruction,
1803 1699 
 	// and so doesn't respect the emu-mode stack bounds.
1804 
-	uint16_t	val = (uint16_t) Absolute(NONE);
1805 
-	PushW(val);
1806 
-	OpenBus = val & 0xff;
1807 
-	Registers.SH = 1;
1700 
+	PEWrapper(Absolute, true);
1808 1701 
 }
1809 1702
1810 1703 
 static void OpF4Slow()
1811 1704 
 {
1812 
-	uint16_t	val = (uint16_t) AbsoluteSlow(NONE);
1813 
-	PushW(val);
1814 
-	OpenBus = val & 0xff;
1815 
-	if (CheckEmulation())
1816 
-		Registers.SH = 1;
1705 
+	PEWrapper(AbsoluteSlow, CheckEmulation());
1817 1706 
 }
1818 1707
1819 1708 
 // PEI
1820 1709 
 static void OpD4E0()
1821 1710 
 {
1822 
-	uint16_t	val = (uint16_t) DirectIndirectE0(NONE);
1823 
-	PushW(val);
1824 
-	OpenBus = val & 0xff;
1711 
+	PEWrapper(DirectIndirectE0, false);
1825 1712 
 }
1826 1713
1827 1714 
 static void OpD4E1()
1828 1715 
 {
1829 1716 
 	// Note: PEI is a new instruction,
1830 1717 
 	// and so doesn't respect the emu-mode stack bounds.
1831 
-	uint16_t	val = (uint16_t) DirectIndirectE1(NONE);
1832 
-	PushW(val);
1833 
-	OpenBus = val & 0xff;
1834 
-	Registers.SH = 1;
1718 
+	PEWrapper(DirectIndirectE1, true);
1835 1719 
 }
1836 1720
1837 1721 
 static void OpD4Slow()
1838 1722 
 {
1839 
-	uint16_t	val = (uint16_t) DirectIndirectSlow(NONE);
1840 
-	PushW(val);
1841 
-	OpenBus = val & 0xff;
1842 
-	if (CheckEmulation())
1843 
-		Registers.SH = 1;
1723 
+	PEWrapper(DirectIndirectSlow, CheckEmulation());
1844 1724 
 }
1845 1725
1846 1726 
 // PER
1847 1727 
 static void Op62E0()
1848 1728 
 {
1849 
-	uint16_t	val = (uint16_t) RelativeLong(NONE);
1850 
-	PushW(val);
1851 
-	OpenBus = val & 0xff;
1729 
+	PEWrapper(RelativeLong, false);
1852 1730 
 }
1853 1731
1854 1732 
 static void Op62E1()
1855 1733 
 {
1856 1734 
 	// Note: PER is a new instruction,
1857 1735 
 	// and so doesn't respect the emu-mode stack bounds.
1858 
-	uint16_t	val = (uint16_t) RelativeLong(NONE);
1859 
-	PushW(val);
1860 
-	OpenBus = val & 0xff;
1861 
-	Registers.SH = 1;
1736 
+	PEWrapper(RelativeLong, true);
1862 1737 
 }
1863 1738
1864 1739 
 static void Op62Slow()
1865 1740 
 {
1866 
-	uint16_t	val = (uint16_t) RelativeLongSlow(NONE);
1867 
-	PushW(val);
1868 
-	OpenBus = val & 0xff;
1869 
-	if (CheckEmulation())
1870 
-		Registers.SH = 1;
1741 
+	PEWrapper(RelativeLongSlow, CheckEmulation());
1871 1742 
 }
1872 1743
1873 
-// PHA
1874 
-static void Op48E1()
1744 
+template<typename Treg, typename Tob, typename F> static inline void PHWrapper(const Treg &pushReg, const Tob &obReg, F f, bool cond)
1875 1745 
 {
1876 1746 
 	AddCycles(ONE_CYCLE);
1877 
-	PushBE(Registers.AL);
1878 
-	OpenBus = Registers.AL;
1747 
+	f(pushReg);
1748 
+	OpenBus = obReg;
1749 
+	if (cond)
1750 
+		Registers.S.B.h = 1;
1879 1751 
 }
1880 1752
1881 
-static void Op48E0M1()
1753 
+// PHA
1754 
+static inline void Op48E1()
1882 1755 
 {
1883 
-	AddCycles(ONE_CYCLE);
1884 
-	PushB(Registers.AL);
1885 
-	OpenBus = Registers.AL;
1756 
+	PHWrapper(Registers.A.B.l, Registers.A.B.l, PushBE, false);
1886 1757 
 }
1887 1758
1888 
-static void Op48E0M0()
1759 
+static inline void Op48E0M1()
1889 1760 
 {
1890 
-	AddCycles(ONE_CYCLE);
1891 
-	PushW(Registers.A.W);
1892 
-	OpenBus = Registers.AL;
1761 
+	PHWrapper(Registers.A.B.l, Registers.A.B.l, PushB, false);
1893 1762 
 }
1894 1763
1895 
-static void Op48Slow()
1764 
+static inline void Op48E0M0()
1896 1765 
 {
1897 
-	AddCycles(ONE_CYCLE);
1766 
+	PHWrapper(Registers.A.W, Registers.A.B.l, PushW, false);
1767 
+}
1898 1768
1769 
+static void Op48Slow()
1770 
+{
1899 1771 
 	if (CheckEmulation())
1900 
-	{
1901 
-		PushBE(Registers.AL);
1902 
-	}
1903 
-	else
1904 
-	if (CheckMemory())
1905 
-	{
1906 
-		PushB(Registers.AL);
1907 
-	}
1772 
+		Op48E1();
1773 
+	else if (CheckMemory())
1774 
+		Op48E0M1();
1908 1775 
 	else
1909 
-	{
1910 
-		PushW(Registers.A.W);
1911 
-	}
1912 
-
1913 
-	OpenBus = Registers.AL;
1776 
+		Op48E0M0();
1914 1777 
 }
1915 1778
1916 1779 
 // PHB
1917 
-static void Op8BE1()
1780 
+static inline void Op8BE1()
1918 1781 
 {
1919 
-	AddCycles(ONE_CYCLE);
1920 
-	PushBE(Registers.DB);
1921 
-	OpenBus = Registers.DB;
1782 
+	PHWrapper(Registers.DB, Registers.DB, PushBE, false);
1922 1783 
 }
1923 1784
1924 
-static void Op8BE0()
1785 
+static inline void Op8BE0()
1925 1786 
 {
1926 
-	AddCycles(ONE_CYCLE);
1927 
-	PushB(Registers.DB);
1928 
-	OpenBus = Registers.DB;
1787 
+	PHWrapper(Registers.DB, Registers.DB, PushB, false);
1929 1788 
 }
1930 1789
1931 1790 
 static void Op8BSlow()
1932 1791 
 {
1933 
-	AddCycles(ONE_CYCLE);
1934 
-
1935 1792 
 	if (CheckEmulation())
1936 
-	{
1937 
-		PushBE(Registers.DB);
1938 
-	}
1793 
+		Op8BE1();
1939 1794 
 	else
1940 
-	{
1941 
-		PushB(Registers.DB);
1942 
-	}
1943 
-
1944 
-	OpenBus = Registers.DB;
1795 
+		Op8BE0();
1945 1796 
 }
1946 1797
1947 1798 
 // PHD
1948 1799 
 static void Op0BE0()
1949 1800 
 {
1950 
-	AddCycles(ONE_CYCLE);
1951 
-	PushW(Registers.D.W);
1952 
-	OpenBus = Registers.DL;
1801 
+	PHWrapper(Registers.D.W, Registers.D.B.l, PushW, false);
1953 1802 
 }
1954 1803
1955 1804 
 static void Op0BE1()
1956 1805 
 {
1957 1806 
 	// Note: PHD is a new instruction,
1958 1807 
 	// and so doesn't respect the emu-mode stack bounds.
1959 
-	AddCycles(ONE_CYCLE);
1960 
-	PushW(Registers.D.W);
1961 
-	OpenBus = Registers.DL;
1962 
-	Registers.SH = 1;
1808 
+	PHWrapper(Registers.D.W, Registers.D.B.l, PushW, true);
1963 1809 
 }
1964 1810
1965 1811 
 static void Op0BSlow()
1966 1812 
 {
1967 
-	AddCycles(ONE_CYCLE);
1968 
-	PushW(Registers.D.W);
1969 
-	OpenBus = Registers.DL;
1970 
-	if (CheckEmulation())
1971 
-		Registers.SH = 1;
1813 
+	PHWrapper(Registers.D.W, Registers.D.B.l, PushW, CheckEmulation());
1972 1814 
 }
1973 1815
1974 1816 
 // PHK
1975 
-static void Op4BE1()
1817 
+static inline void Op4BE1()
1976 1818 
 {
1977 
-	AddCycles(ONE_CYCLE);
1978 
-	PushBE(Registers.PB);
1979 
-	OpenBus = Registers.PB;
1819 
+	PHWrapper(Registers.PC.B.xPB, Registers.PC.B.xPB, PushBE, false);
1980 1820 
 }
1981 1821
1982 
-static void Op4BE0()
1822 
+static inline void Op4BE0()
1983 1823 
 {
1984 
-	AddCycles(ONE_CYCLE);
1985 
-	PushB(Registers.PB);
1986 
-	OpenBus = Registers.PB;
1824 
+	PHWrapper(Registers.PC.B.xPB, Registers.PC.B.xPB, PushB, false);
1987 1825 
 }
1988 1826
1989 1827 
 static void Op4BSlow()
1990 1828 
 {
1991 
-	AddCycles(ONE_CYCLE);
1992 
-
1993 1829 
 	if (CheckEmulation())
1994 
-	{
1995 
-		PushBE(Registers.PB);
1996 
-	}
1830 
+		Op4BE1();
1997 1831 
 	else
1998 
-	{
1999 
-		PushB(Registers.PB);
2000 
-	}
2001 
-
2002 
-	OpenBus = Registers.PB;
1832 
+		Op4BE0();
2003 1833 
 }
2004 1834
2005 1835 
 // PHP
2006 
-static void Op08E0()
1836 
+static inline void Op08E1()
2007 1837 
 {
2008 1838 
 	S9xPackStatus();
2009 
-	AddCycles(ONE_CYCLE);
2010 
-	PushB(Registers.PL);
2011 
-	OpenBus = Registers.PL;
1839 
+	PHWrapper(Registers.P.B.l, Registers.P.B.l, PushBE, false);
2012 1840 
 }
2013 1841
2014 
-static void Op08E1()
1842 
+static inline void Op08E0()
2015 1843 
 {
2016 1844 
 	S9xPackStatus();
2017 
-	AddCycles(ONE_CYCLE);
2018 
-	PushBE(Registers.PL);
2019 
-	OpenBus = Registers.PL;
1845 
+	PHWrapper(Registers.P.B.l, Registers.P.B.l, PushB, false);
2020 1846 
 }
2021 1847
2022 1848 
 static void Op08Slow()
2023 1849 
 {
2024 
-	S9xPackStatus();
2025 
-	AddCycles(ONE_CYCLE);
2026 
-
2027 1850 
 	if (CheckEmulation())
2028 
-	{
2029 
-		PushBE(Registers.PL);
2030 
-	}
1851 
+		Op08E1();
2031 1852 
 	else
2032 
-	{
2033 
-		PushB(Registers.PL);
2034 
-	}
2035 
-
2036 
-	OpenBus = Registers.PL;
1853 
+		Op08E0();
2037 1854 
 }
2038 1855
2039 1856 
 // PHX
2040 
-static void OpDAE1()
1857 
+static inline void OpDAE1()
2041 1858 
 {
2042 
-	AddCycles(ONE_CYCLE);
2043 
-	PushBE(Registers.XL);
2044 
-	OpenBus = Registers.XL;
1859 
+	PHWrapper(Registers.X.B.l, Registers.X.B.l, PushBE, false);
2045 1860 
 }
2046 1861
2047 
-static void OpDAE0X1()
1862 
+static inline void OpDAE0X1()
2048 1863 
 {
2049 
-	AddCycles(ONE_CYCLE);
2050 
-	PushB(Registers.XL);
2051 
-	OpenBus = Registers.XL;
1864 
+	PHWrapper(Registers.X.B.l, Registers.X.B.l, PushB, false);
2052 1865 
 }
2053 1866
2054 
-static void OpDAE0X0()
1867 
+static inline void OpDAE0X0()
2055 1868 
 {
2056 
-	AddCycles(ONE_CYCLE);
2057 
-	PushW(Registers.X.W);
2058 
-	OpenBus = Registers.XL;
1869 
+	PHWrapper(Registers.X.W, Registers.X.B.l, PushW, false);
2059 1870 
 }
2060 1871
2061 1872 
 static void OpDASlow()
2062 1873 
 {
2063 
-	AddCycles(ONE_CYCLE);
2064 
-
2065 1874 
 	if (CheckEmulation())
2066 
-	{
2067 
-		PushBE(Registers.XL);
2068 
-	}
2069 
-	else
2070 
-	if (CheckIndex())
2071 
-	{
2072 
-		PushB(Registers.XL);
2073 
-	}
1875 
+		OpDAE1();
1876 
+	else if (CheckIndex())
1877 
+		OpDAE0X1();
2074 1878 
 	else
2075 
-	{
2076 
-		PushW(Registers.X.W);
2077 
-	}
2078 
-
2079 
-	OpenBus = Registers.XL;
1879 
+		OpDAE0X0();
2080 1880 
 }
2081 1881
2082 1882 
 // PHY
2083 
-static void Op5AE1()
1883 
+static inline void Op5AE1()
2084 1884 
 {
2085 
-	AddCycles(ONE_CYCLE);
2086 
-	PushBE(Registers.YL);
2087 
-	OpenBus = Registers.YL;
1885 
+	PHWrapper(Registers.Y.B.l, Registers.Y.B.l, PushBE, false);
2088 1886 
 }
2089 1887
2090 
-static void Op5AE0X1()
1888 
+static inline void Op5AE0X1()
2091 1889 
 {
2092 
-	AddCycles(ONE_CYCLE);
2093 
-	PushB(Registers.YL);
2094 
-	OpenBus = Registers.YL;
1890 
+	PHWrapper(Registers.Y.B.l, Registers.Y.B.l, PushB, false);
2095 1891 
 }
2096 1892
2097 
-static void Op5AE0X0()
1893 
+static inline void Op5AE0X0()
2098 1894 
 {
2099 
-	AddCycles(ONE_CYCLE);
2100 
-	PushW(Registers.Y.W);
2101 
-	OpenBus = Registers.YL;
1895 
+	PHWrapper(Registers.Y.W, Registers.Y.B.l, PushW, false);
2102 1896 
 }
2103 1897
2104 1898 
 static void Op5ASlow()
2105 1899 
 {
2106 
-	AddCycles(ONE_CYCLE);
2107 
-
2108 1900 
 	if (CheckEmulation())
2109 
-	{
2110 
-		PushBE(Registers.YL);
2111 
-	}
1901 
+		Op5AE1();
1902 
+	else if (CheckIndex())
1903 
+		Op5AE0X1();
2112 1904 
 	else
2113 
-	if (CheckIndex())
2114 
-	{
2115 
-		PushB(Registers.YL);
2116 
-	}
2117 
-	else
2118 
-	{
2119 
-		PushW(Registers.Y.W);
2120 
-	}
2121 
-
2122 
-	OpenBus = Registers.YL;
1905 
+		Op5AE0X0();
2123 1906 
 }
2124 1907
2125 1908 
 /* PULL Instructions ******************************************************* */
2126 1909
2127 
-#define PullW(w) \
2128 
-	w = S9xGetWord(Registers.S.W + 1, WRAP_BANK); \
1910 
+static inline void PullW(uint16_t &w)
1911 
+{
1912 
+	w = S9xGetWord(Registers.S.W + 1, WRAP_BANK);
2129 1913 
 	Registers.S.W += 2;
1914 
+}
2130 1915
2131 
-#define PullWE(w) \
2132 
-	Registers.SL++; \
2133 
-	w = S9xGetWord(Registers.S.W, WRAP_PAGE); \
2134 
-	Registers.SL++;
1916 
+static inline void PullWE(uint16_t &w)
1917 
+{
1918 
+	++Registers.S.B.l;
1919 
+	w = S9xGetWord(Registers.S.W, WRAP_PAGE);
1920 
+	++Registers.S.B.l;
1921 
+}
2135 1922
2136 
-#define PullB(b) \
1923 
+static inline void PullB(uint8_t &b)
1924 
+{
2137 1925 
 	b = S9xGetByte(++Registers.S.W);
1926 
+}
2138 1927
2139 
-#define PullBE(b) \
2140 
-	Registers.SL++; \
1928 
+static inline void PullBE(uint8_t &b)
1929 
+{
1930 
+	++Registers.S.B.l;
2141 1931 
 	b = S9xGetByte(Registers.S.W);
1932 
+}
2142 1933
2143 1934 
 // PLA
2144 
-static void Op68E1()
1935 
+template<typename Treg, typename Tob, typename F> static inline void Op68Wrapper(Treg &pullReg, const Tob &obReg, F f)
2145 1936 
 {
2146 1937 
 	AddCycles(TWO_CYCLES);
2147 
-	PullBE(Registers.AL);
2148 
-	SetZN(Registers.AL);
2149 
-	OpenBus = Registers.AL;
1938 
+	f(pullReg);
1939 
+	SetZN(pullReg);
1940 
+	OpenBus = obReg;
2150 1941 
 }
2151 1942
2152 
-static void Op68E0M1()
1943 
+static inline void Op68E1()
2153 1944 
 {
2154 
-	AddCycles(TWO_CYCLES);
2155 
-	PullB(Registers.AL);
2156 
-	SetZN(Registers.AL);
2157 
-	OpenBus = Registers.AL;
1945 
+	Op68Wrapper(Registers.A.B.l, Registers.A.B.l, PullBE);
2158 1946 
 }
2159 1947
2160 
-static void Op68E0M0()
1948 
+static inline void Op68E0M1()
2161 1949 
 {
2162 
-	AddCycles(TWO_CYCLES);
2163 
-	PullW(Registers.A.W);
2164 
-	SetZN(Registers.A.W);
2165 
-	OpenBus = Registers.AH;
1950 
+	Op68Wrapper(Registers.A.B.l, Registers.A.B.l, PullB);
2166 1951 
 }
2167 1952
2168 
-static void Op68Slow()
1953 
+static inline void Op68E0M0()
2169 1954 
 {
2170 
-	AddCycles(TWO_CYCLES);
1955 
+	Op68Wrapper(Registers.A.W, Registers.A.B.h, PullW);
1956 
+}
2171 1957
1958 
+static void Op68Slow()
1959 
+{
2172 1960 
 	if (CheckEmulation())
2173 
-	{
2174 
-		PullBE(Registers.AL);
2175 
-		SetZN(Registers.AL);
2176 
-		OpenBus = Registers.AL;
2177 
-	}
2178 
-	else
2179 
-	if (CheckMemory())
2180 
-	{
2181 
-		PullB(Registers.AL);
2182 
-		SetZN(Registers.AL);
2183 
-		OpenBus = Registers.AL;
2184 
-	}
1961 
+		Op68E1();
1962 
+	else if (CheckMemory())
1963 
+		Op68E0M1();
2185 1964 
 	else
2186 
-	{
2187 
-		PullW(Registers.A.W);
2188 
-		SetZN(Registers.A.W);
2189 
-		OpenBus = Registers.AH;
2190 
-	}
1965 
+		Op68E0M0();
2191 1966 
 }
2192 1967
2193 1968 
 // PLB
2194 
-static void OpABE1()
1969 
+template<typename F> static inline void OpABWrapper(F f)
2195 1970 
 {
2196 1971 
 	AddCycles(TWO_CYCLES);
2197 
-	PullBE(Registers.DB);
1972 
+	f(Registers.DB);
2198 1973 
 	SetZN(Registers.DB);
2199 1974 
 	ICPU.ShiftedDB = Registers.DB << 16;
2200 1975 
 	OpenBus = Registers.DB;
2201 1976 
 }
2202 1977
2203 
-static void OpABE0()
1978 
+static inline void OpABE1()
2204 1979 
 {
2205 
-	AddCycles(TWO_CYCLES);
2206 
-	PullB(Registers.DB);
2207 
-	SetZN(Registers.DB);
2208 
-	ICPU.ShiftedDB = Registers.DB << 16;
2209 
-	OpenBus = Registers.DB;
1980 
+	OpABWrapper(PullBE);
2210 1981 
 }
2211 1982
2212 
-static void OpABSlow()
1983 
+static inline void OpABE0()
2213 1984 
 {
2214 
-	AddCycles(TWO_CYCLES);
1985 
+	OpABWrapper(PullB);
1986 
+}
2215 1987
1988 
+static void OpABSlow()
1989 
+{
2216 1990 
 	if (CheckEmulation())
2217 
-	{
2218 
-		PullBE(Registers.DB);
2219 
-	}
1991 
+		OpABE1();
2220 1992 
 	else
2221 
-	{
2222 
-		PullB(Registers.DB);
2223 
-	}
2224 
-
2225 
-	SetZN(Registers.DB);
2226 
-	ICPU.ShiftedDB = Registers.DB << 16;
2227 
-	OpenBus = Registers.DB;
1993 
+		OpABE0();
2228 1994 
 }
2229 1995
2230 1996 
 // PLD
2231 
-static void Op2BE0()
1997 
+static inline void Op2BWrapper(bool cond)
2232 1998 
 {
2233 1999 
 	AddCycles(TWO_CYCLES);
2234 2000 
 	PullW(Registers.D.W);
2235 2001 
 	SetZN(Registers.D.W);
2236 
-	OpenBus = Registers.DH;
2002 
+	OpenBus = Registers.D.B.h;
2003 
+	if (cond)
2004 
+		Registers.S.B.h = 1;
2005 
+}
2006 
+
2007 
+static void Op2BE0()
2008 
+{
2009 
+	Op2BWrapper(false);
2237 2010 
 }
2238 2011
2239 2012 
 static void Op2BE1()
2240 2013 
 {
2241 2014 
 	// Note: PLD is a new instruction,
2242 2015 
 	// and so doesn't respect the emu-mode stack bounds.
2243 
-	AddCycles(TWO_CYCLES);
2244 
-	PullW(Registers.D.W);
2245 
-	SetZN(Registers.D.W);
2246 
-	OpenBus = Registers.DH;
2247 
-	Registers.SH = 1;
2016 
+	Op2BWrapper(true);
2248 2017 
 }
2249 2018
2250 2019 
 static void Op2BSlow()
2251 2020 
 {
2252 
-	AddCycles(TWO_CYCLES);
2253 
-	PullW(Registers.D.W);
2254 
-	SetZN(Registers.D.W);
2255 
-	OpenBus = Registers.DH;
2256 
-	if (CheckEmulation())
2257 
-		Registers.SH = 1;
2021 
+	Op2BWrapper(CheckEmulation());
2258 2022 
 }
2259 2023
2260 2024 
 // PLP
2261 2025 
 static void Op28E1()
2262 2026 
 {
2263 2027 
 	AddCycles(TWO_CYCLES);
2264 
-	PullBE(Registers.PL);
2265 
-	OpenBus = Registers.PL;
2028 
+	PullBE(Registers.P.B.l);
2029 
+	OpenBus = Registers.P.B.l;
2266 2030 
 	SetFlags(MemoryFlag | IndexFlag);
2267 2031 
 	S9xUnpackStatus();
2268 2032 
 	S9xFixCycles();
2269 
-	CHECK_FOR_IRQ();
2270 2033 
 }
2271 2034
2272 2035 
 static void Op28E0()
2273 2036 
 {
2274 2037 
 	AddCycles(TWO_CYCLES);
2275 
-	PullB(Registers.PL);
2276 
-	OpenBus = Registers.PL;
2038 
+	PullB(Registers.P.B.l);
2039 
+	OpenBus = Registers.P.B.l;
2277 2040 
 	S9xUnpackStatus();
2278 2041
2279 2042 
 	if (CheckIndex())
2280 
-	{
2281 
-		Registers.XH = 0;
2282 
-		Registers.YH = 0;
2283 
-	}
2043 
+		Registers.X.B.h = Registers.Y.B.h = 0;
2284 2044
2285 2045 
 	S9xFixCycles();
2286 
-	CHECK_FOR_IRQ();
2287 2046 
 }
2288 2047
2289 2048 
 static void Op28Slow()
... ... 
@@ -2292,198 +2051,145 @@ static void Op28Slow()
2292 2051
2293 2052 
 	if (CheckEmulation())
2294 2053 
 	{
2295 
-		PullBE(Registers.PL);
2296 
-		OpenBus = Registers.PL;
2054 
+		PullBE(Registers.P.B.l);
2055 
+		OpenBus = Registers.P.B.l;
2297 2056 
 		SetFlags(MemoryFlag | IndexFlag);
2298 2057 
 	}
2299 2058 
 	else
2300 2059 
 	{
2301 
-		PullB(Registers.PL);
2302 
-		OpenBus = Registers.PL;
2060 
+		PullB(Registers.P.B.l);
2061 
+		OpenBus = Registers.P.B.l;
2303 2062 
 	}
2304 2063
2305 2064 
 	S9xUnpackStatus();
2306 2065
2307 2066 
 	if (CheckIndex())
2308 
-	{
2309 
-		Registers.XH = 0;
2310 
-		Registers.YH = 0;
2311 
-	}
2067 
+		Registers.X.B.h = Registers.Y.B.h = 0;
2312 2068
2313 2069 
 	S9xFixCycles();
2314 
-	CHECK_FOR_IRQ();
2315 2070 
 }
2316 2071
2317 2072 
 // PLX
2318 
-static void OpFAE1()
2073 
+static inline void OpFAE1()
2319 2074 
 {
2320 2075 
 	AddCycles(TWO_CYCLES);
2321 
-	PullBE(Registers.XL);
2322 
-	SetZN(Registers.XL);
2323 
-	OpenBus = Registers.XL;
2076 
+	PullBE(Registers.X.B.l);
2077 
+	SetZN(Registers.X.B.l);
2078 
+	OpenBus = Registers.X.B.l;
2324 2079 
 }
2325 2080
2326 
-static void OpFAE0X1()
2081 
+static inline void OpFAE0X1()
2327 2082 
 {
2328 2083 
 	AddCycles(TWO_CYCLES);
2329 
-	PullB(Registers.XL);
2330 
-	SetZN(Registers.XL);
2331 
-	OpenBus = Registers.XL;
2084 
+	PullB(Registers.X.B.l);
2085 
+	SetZN(Registers.X.B.l);
2086 
+	OpenBus = Registers.X.B.l;
2332 2087 
 }
2333 2088
2334 
-static void OpFAE0X0()
2089 
+static inline void OpFAE0X0()
2335 2090 
 {
2336 2091 
 	AddCycles(TWO_CYCLES);
2337 2092 
 	PullW(Registers.X.W);
2338 2093 
 	SetZN(Registers.X.W);
2339 
-	OpenBus = Registers.XH;
2094 
+	OpenBus = Registers.X.B.h;
2340 2095 
 }
2341 2096
2342 2097 
 static void OpFASlow()
2343 2098 
 {
2344 
-	AddCycles(TWO_CYCLES);
2345 
-
2346 2099 
 	if (CheckEmulation())
2347 
-	{
2348 
-		PullBE(Registers.XL);
2349 
-		SetZN(Registers.XL);
2350 
-		OpenBus = Registers.XL;
2351 
-	}
2352 
-	else
2353 
-	if (CheckIndex())
2354 
-	{
2355 
-		PullB(Registers.XL);
2356 
-		SetZN(Registers.XL);
2357 
-		OpenBus = Registers.XL;
2358 
-	}
2100 
+		OpFAE1();
2101 
+	else if (CheckIndex())
2102 
+		OpFAE0X1();
2359 2103 
 	else
2360 
-	{
2361 
-		PullW(Registers.X.W);
2362 
-		SetZN(Registers.X.W);
2363 
-		OpenBus = Registers.XH;
2364 
-	}
2104 
+		OpFAE0X0();
2365 2105 
 }
2366 2106
2367 2107 
 // PLY
2368 
-static void Op7AE1()
2108 
+static inline void Op7AE1()
2369 2109 
 {
2370 2110 
 	AddCycles(TWO_CYCLES);
2371 
-	PullBE(Registers.YL);
2372 
-	SetZN(Registers.YL);
2373 
-	OpenBus = Registers.YL;
2111 
+	PullBE(Registers.Y.B.l);
2112 
+	SetZN(Registers.Y.B.l);
2113 
+	OpenBus = Registers.Y.B.l;
2374 2114 
 }
2375 2115
2376 
-static void Op7AE0X1()
2116 
+static inline void Op7AE0X1()
2377 2117 
 {
2378 2118 
 	AddCycles(TWO_CYCLES);
2379 
-	PullB(Registers.YL);
2380 
-	SetZN(Registers.YL);
2381 
-	OpenBus = Registers.YL;
2119 
+	PullB(Registers.Y.B.l);
2120 
+	SetZN(Registers.Y.B.l);
2121 
+	OpenBus = Registers.Y.B.l;
2382 2122 
 }
2383 2123
2384 
-static void Op7AE0X0()
2124 
+static inline void Op7AE0X0()
2385 2125 
 {
2386 2126 
 	AddCycles(TWO_CYCLES);
2387 2127 
 	PullW(Registers.Y.W);
2388 2128 
 	SetZN(Registers.Y.W);
2389 
-	OpenBus = Registers.YH;
2129 
+	OpenBus = Registers.Y.B.h;
2390 2130 
 }
2391 2131
2392 2132 
 static void Op7ASlow()
2393 2133 
 {
2394 
-	AddCycles(TWO_CYCLES);
2395 
-
2396 2134 
 	if (CheckEmulation())
2397 
-	{
2398 
-		PullBE(Registers.YL);
2399 
-		SetZN(Registers.YL);
2400 
-		OpenBus = Registers.YL;
2401 
-	}
2135 
+		Op7AE1();
2136 
+	else if (CheckIndex())
2137 
+		Op7AE0X1();
2402 2138 
 	else
2403 
-	if (CheckIndex())
2404 
-	{
2405 
-		PullB(Registers.YL);
2406 
-		SetZN(Registers.YL);
2407 
-		OpenBus = Registers.YL;
2408 
-	}
2409 
-	else
2410 
-	{
2411 
-		PullW(Registers.Y.W);
2412 
-		SetZN(Registers.Y.W);
2413 
-		OpenBus = Registers.YH;
2414 
-	}
2139 
+		Op7AE0X0();
2415 2140 
 }
2416 2141
2417 2142 
 /* Transfer Instructions *************************************************** */
2418 2143
2419 
-// TAX
2420 
-static void OpAAX1()
2144 
+template<typename T> static inline void TransferWrapper(T &reg1, const T &reg2)
2421 2145 
 {
2422 2146 
 	AddCycles(ONE_CYCLE);
2423 
-	Registers.XL = Registers.AL;
2424 
-	SetZN(Registers.XL);
2147 
+	reg1 = reg2;
2148 
+	SetZN(reg1);
2425 2149 
 }
2426 2150
2427 
-static void OpAAX0()
2151 
+// TAX
2152 
+static inline void OpAAX1()
2428 2153 
 {
2429 
-	AddCycles(ONE_CYCLE);
2430 
-	Registers.X.W = Registers.A.W;
2431 
-	SetZN(Registers.X.W);
2154 
+	TransferWrapper(Registers.X.B.l, Registers.A.B.l);
2432 2155 
 }
2433 2156
2434 
-static void OpAASlow()
2157 
+static inline void OpAAX0()
2435 2158 
 {
2436 
-	AddCycles(ONE_CYCLE);
2159 
+	TransferWrapper(Registers.X.W, Registers.A.W);
2160 
+}
2437 2161
2162 
+static void OpAASlow()
2163 
+{
2438 2164 
 	if (CheckIndex())
2439 
-	{
2440 
-		Registers.XL = Registers.AL;
2441 
-		SetZN(Registers.XL);
2442 
-	}
2165 
+		OpAAX1();
2443 2166 
 	else
2444 
-	{
2445 
-		Registers.X.W = Registers.A.W;
2446 
-		SetZN(Registers.X.W);
2447 
-	}
2167 
+		OpAAX0();
2448 2168 
 }
2449 2169
2450 2170 
 // TAY
2451 
-static void OpA8X1()
2171 
+static inline void OpA8X1()
2452 2172 
 {
2453 
-	AddCycles(ONE_CYCLE);
2454 
-	Registers.YL = Registers.AL;
2455 
-	SetZN(Registers.YL);
2173 
+	TransferWrapper(Registers.Y.B.l, Registers.A.B.l);
2456 2174 
 }
2457 2175
2458 
-static void OpA8X0()
2176 
+static inline void OpA8X0()
2459 2177 
 {
2460 
-	AddCycles(ONE_CYCLE);
2461 
-	Registers.Y.W = Registers.A.W;
2462 
-	SetZN(Registers.Y.W);
2178 
+	TransferWrapper(Registers.Y.W, Registers.A.W);
2463 2179 
 }
2464 2180
2465 2181 
 static void OpA8Slow()
2466 2182 
 {
2467 
-	AddCycles(ONE_CYCLE);
2468 
-
2469 2183 
 	if (CheckIndex())
2470 
-	{
2471 
-		Registers.YL = Registers.AL;
2472 
-		SetZN(Registers.YL);
2473 
-	}
2184 
+		OpA8X1();
2474 2185 
 	else
2475 
-	{
2476 
-		Registers.Y.W = Registers.A.W;
2477 
-		SetZN(Registers.Y.W);
2478 
-	}
2186 
+		OpA8X0();
2479 2187 
 }
2480 2188
2481 2189 
 // TCD
2482 2190 
 static void Op5B()
2483 2191 
 {
2484 
-	AddCycles(ONE_CYCLE);
2485 
-	Registers.D.W = Registers.A.W;
2486 
-	SetZN(Registers.D.W);
2192 
+	TransferWrapper(Registers.D.W, Registers.A.W);
2487 2193 
 }
2488 2194
2489 2195 
 // TCS
... ... 
@@ -2492,85 +2198,57 @@ static void Op1B()
2492 2198 
 	AddCycles(ONE_CYCLE);
2493 2199 
 	Registers.S.W = Registers.A.W;
2494 2200 
 	if (CheckEmulation())
2495 
-		Registers.SH = 1;
2201 
+		Registers.S.B.h = 1;
2496 2202 
 }
2497 2203
2498 2204 
 // TDC
2499 2205 
 static void Op7B()
2500 2206 
 {
2501 
-	AddCycles(ONE_CYCLE);
2502 
-	Registers.A.W = Registers.D.W;
2503 
-	SetZN(Registers.A.W);
2207 
+	TransferWrapper(Registers.A.W, Registers.D.W);
2504 2208 
 }
2505 2209
2506 2210 
 // TSC
2507 2211 
 static void Op3B()
2508 2212 
 {
2509 
-	AddCycles(ONE_CYCLE);
2510 
-	Registers.A.W = Registers.S.W;
2511 
-	SetZN(Registers.A.W);
2213 
+	TransferWrapper(Registers.A.W, Registers.S.W);
2512 2214 
 }
2513 2215
2514 2216 
 // TSX
2515 
-static void OpBAX1()
2217 
+static inline void OpBAX1()
2516 2218 
 {
2517 
-	AddCycles(ONE_CYCLE);
2518 
-	Registers.XL = Registers.SL;
2519 
-	SetZN(Registers.XL);
2219 
+	TransferWrapper(Registers.X.B.l, Registers.S.B.l);
2520 2220 
 }
2521 2221
2522 
-static void OpBAX0()
2222 
+static inline void OpBAX0()
2523 2223 
 {
2524 
-	AddCycles(ONE_CYCLE);
2525 
-	Registers.X.W = Registers.S.W;
2526 
-	SetZN(Registers.X.W);
2224 
+	TransferWrapper(Registers.X.W, Registers.S.W);
2527 2225 
 }
2528 2226
2529 2227 
 static void OpBASlow()
2530 2228 
 {
2531 
-	AddCycles(ONE_CYCLE);
2532 
-
2533 2229 
 	if (CheckIndex())
2534 
-	{
2535 
-		Registers.XL = Registers.SL;
2536 
-		SetZN(Registers.XL);
2537 
-	}
2230 
+		OpBAX1();
2538 2231 
 	else
2539 
-	{
2540 
-		Registers.X.W = Registers.S.W;
2541 
-		SetZN(Registers.X.W);
2542 
-	}
2232 
+		OpBAX0();
2543 2233 
 }
2544 2234
2545 2235 
 // TXA
2546 
-static void Op8AM1()
2236 
+static inline void Op8AM1()
2547 2237 
 {
2548 
-	AddCycles(ONE_CYCLE);
2549 
-	Registers.AL = Registers.XL;
2550 
-	SetZN(Registers.AL);
2238 
+	TransferWrapper(Registers.A.B.l, Registers.X.B.l);
2551 2239 
 }
2552 2240
2553 
-static void Op8AM0()
2241 
+static inline void Op8AM0()
2554 2242 
 {
2555 
-	AddCycles(ONE_CYCLE);
2556 
-	Registers.A.W = Registers.X.W;
2557 
-	SetZN(Registers.A.W);
2243 
+	TransferWrapper(Registers.A.W, Registers.X.W);
2558 2244 
 }
2559 2245
2560 2246 
 static void Op8ASlow()
2561 2247 
 {
2562 
-	AddCycles(ONE_CYCLE);
2563 
-
2564 2248 
 	if (CheckMemory())
2565 
-	{
2566 
-		Registers.AL = Registers.XL;
2567 
-		SetZN(Registers.AL);
2568 
-	}
2249 
+		Op8AM1();
2569 2250 
 	else
2570 
-	{
2571 
-		Registers.A.W = Registers.X.W;
2572 
-		SetZN(Registers.A.W);
2573 
-	}
2251 
+		Op8AM0();
2574 2252 
 }
2575 2253
2576 2254 
 // TXS
... ... 
@@ -2579,100 +2257,64 @@ static void Op9A()
2579 2257 
 	AddCycles(ONE_CYCLE);
2580 2258 
 	Registers.S.W = Registers.X.W;
2581 2259 
 	if (CheckEmulation())
2582 
-		Registers.SH = 1;
2260 
+		Registers.S.B.h = 1;
2583 2261 
 }
2584 2262
2585 2263 
 // TXY
2586 
-static void Op9BX1()
2264 
+static inline void Op9BX1()
2587 2265 
 {
2588 
-	AddCycles(ONE_CYCLE);
2589 
-	Registers.YL = Registers.XL;
2590 
-	SetZN(Registers.YL);
2266 
+	TransferWrapper(Registers.Y.B.l, Registers.X.B.l);
2591 2267 
 }
2592 2268
2593 
-static void Op9BX0()
2269 
+static inline void Op9BX0()
2594 2270 
 {
2595 
-	AddCycles(ONE_CYCLE);
2596 
-	Registers.Y.W = Registers.X.W;
2597 
-	SetZN(Registers.Y.W);
2271 
+	TransferWrapper(Registers.Y.W, Registers.X.W);
2598 2272 
 }
2599 2273
2600 2274 
 static void Op9BSlow()
2601 2275 
 {
2602 
-	AddCycles(ONE_CYCLE);
2603 
-
2604 2276 
 	if (CheckIndex())
2605 
-	{
2606 
-		Registers.YL = Registers.XL;
2607 
-		SetZN(Registers.YL);
2608 
-	}
2277 
+		Op9BX1();
2609 2278 
 	else
2610 
-	{
2611 
-		Registers.Y.W = Registers.X.W;
2612 
-		SetZN(Registers.Y.W);
2613 
-	}
2279 
+		Op9BX0();
2614 2280 
 }
2615 2281
2616 2282 
 // TYA
2617 
-static void Op98M1()
2283 
+static inline void Op98M1()
2618 2284 
 {
2619 
-	AddCycles(ONE_CYCLE);
2620 
-	Registers.AL = Registers.YL;
2621 
-	SetZN(Registers.AL);
2285 
+	TransferWrapper(Registers.A.B.l, Registers.Y.B.l);
2622 2286 
 }
2623 2287
2624 
-static void Op98M0()
2288 
+static inline void Op98M0()
2625 2289 
 {
2626 
-	AddCycles(ONE_CYCLE);
2627 
-	Registers.A.W = Registers.Y.W;
2628 
-	SetZN(Registers.A.W);
2290 
+	TransferWrapper(Registers.A.W, Registers.Y.W);
2629 2291 
 }
2630 2292
2631 2293 
 static void Op98Slow()
2632 2294 
 {
2633 
-	AddCycles(ONE_CYCLE);
2634 
-
2635 2295 
 	if (CheckMemory())
2636 
-	{
2637 
-		Registers.AL = Registers.YL;
2638 
-		SetZN(Registers.AL);
2639 
-	}
2296 
+		Op98M1();
2640 2297 
 	else
2641 
-	{
2642 
-		Registers.A.W = Registers.Y.W;
2643 
-		SetZN(Registers.A.W);
2644 
-	}
2298 
+		Op98M0();
2645 2299 
 }
2646 2300
2647 2301 
 // TYX
2648 
-static void OpBBX1()
2302 
+static inline void OpBBX1()
2649 2303 
 {
2650 
-	AddCycles(ONE_CYCLE);
2651 
-	Registers.XL = Registers.YL;
2652 
-	SetZN(Registers.XL);
2304 
+	TransferWrapper(Registers.X.B.l, Registers.Y.B.l);
2653 2305 
 }
2654 2306
2655 
-static void OpBBX0()
2307 
+static inline void OpBBX0()
2656 2308 
 {
2657 
-	AddCycles(ONE_CYCLE);
2658 
-	Registers.X.W = Registers.Y.W;
2659 
-	SetZN(Registers.X.W);
2309 
+	TransferWrapper(Registers.X.W, Registers.Y.W);
2660 2310 
 }
2661 2311
2662 2312 
 static void OpBBSlow()
2663 2313 
 {
2664 
-	AddCycles(ONE_CYCLE);
2665 
-
2666 2314 
 	if (CheckIndex())
2667 
-	{
2668 
-		Registers.XL = Registers.YL;
2669 
-		SetZN(Registers.XL);
2670 
-	}
2315 
+		OpBBX1();
2671 2316 
 	else
2672 
-	{
2673 
-		Registers.X.W = Registers.Y.W;
2674 
-		SetZN(Registers.X.W);
2675 
-	}
2317 
+		OpBBX0();
2676 2318 
 }
2677 2319
2678 2320 
 /* XCE ********************************************************************* */
... ... 
@@ -2681,26 +2323,20 @@ static void OpFB()
2681 2323 
 {
2682 2324 
 	AddCycles(ONE_CYCLE);
2683 2325
2684 
-	uint8_t	A1 = ICPU._Carry;
2685 
-	uint8_t	A2 = Registers.PH;
2326 
+	uint8_t A1 = ICPU._Carry;
2327 
+	uint8_t A2 = Registers.P.B.h;
2686 2328
2687 2329 
 	ICPU._Carry = A2 & 1;
2688 
-	Registers.PH = A1;
2330 
+	Registers.P.B.h = A1;
2689 2331
2690 2332 
 	if (CheckEmulation())
2691 2333 
 	{
2692 2334 
 		SetFlags(MemoryFlag | IndexFlag);
2693 
-		Registers.SH = 1;
2694 
-	#ifdef DEBUGGER
2695 
-		missing.emulate6502 = 1;
2696 
-	#endif
2335 
+		Registers.S.B.h = 1;
2697 2336 
 	}
2698 2337
2699 2338 
 	if (CheckIndex())
2700 
-	{
2701 
-		Registers.XH = 0;
2702 
-		Registers.YH = 0;
2703 
-	}
2339 
+		Registers.X.B.h = Registers.Y.B.h = 0;
2704 2340
2705 2341 
 	S9xFixCycles();
2706 2342 
 }
... ... 
@@ -2709,38 +2345,26 @@ static void OpFB()
2709 2345
2710 2346 
 static void Op00()
2711 2347 
 {
2712 
-#ifdef DEBUGGER
2713 
-	if (CPU.Flags & TRACE_FLAG)
2714 
-		S9xTraceMessage("*** BRK");
2715 
-#endif
2716 
-
2717 2348 
 	AddCycles(CPU.MemSpeed);
2718 2349
2719 
-	uint16_t	addr;
2720 
-
2721 2350 
 	if (!CheckEmulation())
2722 2351 
 	{
2723 
-		PushB(Registers.PB);
2724 
-		PushW(Registers.PCw + 1);
2352 
+		PushB(Registers.PC.B.xPB);
2353 
+		PushW(Registers.PC.W.xPC + 1);
2725 2354 
 		S9xPackStatus();
2726 
-		PushB(Registers.PL);
2727 
-		OpenBus = Registers.PL;
2728 
-		ClearDecimal();
2729 
-		SetIRQ();
2730 
-
2731 
-		addr = S9xGetWord(0xFFE6);
2355 
+		PushB(Registers.P.B.l);
2732 2356 
 	}
2733 2357 
 	else
2734 2358 
 	{
2735 
-		PushWE(Registers.PCw + 1);
2359 
+		PushWE(Registers.PC.W.xPC + 1);
2736 2360 
 		S9xPackStatus();
2737 
-		PushBE(Registers.PL);
2738 
-		OpenBus = Registers.PL;
2739 
-		ClearDecimal();
2740 
-		SetIRQ();
2741 
-
2742 
-		addr = S9xGetWord(0xFFFE);
2361 
+		PushBE(Registers.P.B.l);
2743 2362 
 	}
2363 
+	OpenBus = Registers.P.B.l;
2364 
+	ClearDecimal();
2365 
+	SetIRQ();
2366 
+
2367 
+	uint16_t addr = S9xGetWord(0xFFFE);
2744 2368
2745 2369 
 	S9xSetPCBase(addr);
2746 2370 
 	OpenBus = addr >> 8;
... ... 
@@ -2750,188 +2374,96 @@ static void Op00()
2750 2374
2751 2375 
 void S9xOpcode_IRQ()
2752 2376 
 {
2753 
-#ifdef DEBUGGER
2754 
-	if (CPU.Flags & TRACE_FLAG)
2755 
-	#ifdef SA1_OPCODES
2756 
-		S9xTraceMessage("*** SA1 IRQ");
2757 
-	#else
2758 
-		S9xTraceMessage("*** IRQ");
2759 
-	#endif
2760 
-#endif
2761 
-
2762 2377 
 	// IRQ and NMI do an opcode fetch as their first "IO" cycle.
2763 2378 
 	AddCycles(CPU.MemSpeed + ONE_CYCLE);
2764 2379
2380 
+	uint16_t addr;
2765 2381 
 	if (!CheckEmulation())
2766 2382 
 	{
2767 
-		PushB(Registers.PB);
2768 
-		PushW(Registers.PCw);
2383 
+		PushB(Registers.PC.B.xPB);
2384 
+		PushW(Registers.PC.W.xPC);
2769 2385 
 		S9xPackStatus();
2770 
-		PushB(Registers.PL);
2771 
-		OpenBus = Registers.PL;
2386 
+		PushB(Registers.P.B.l);
2387 
+		OpenBus = Registers.P.B.l;
2772 2388 
 		ClearDecimal();
2773 2389 
 		SetIRQ();
2774 2390
2775 
-	#ifdef SA1_OPCODES
2776 
-		OpenBus = Memory.FillRAM[0x2208];
2777 
-		AddCycles(2 * SLOW_ONE_CYCLE);
2778 
-		S9xSA1SetPCBase(Memory.FillRAM[0x2207] | (Memory.FillRAM[0x2208] << 8));
2779 
-	#else
2780 
-		if (Settings.SA1 && (Memory.FillRAM[0x2209] & 0x40))
2781 
-		{
2782 
-			OpenBus = Memory.FillRAM[0x220f];
2783 
-			AddCycles(2 * SLOW_ONE_CYCLE);
2784 
-			S9xSetPCBase(Memory.FillRAM[0x220e] | (Memory.FillRAM[0x220f] << 8));
2785 
-		}
2786 
-		else
2787 
-		{
2788 
-			uint16_t	addr = S9xGetWord(0xFFEE);
2789 
-			OpenBus = addr >> 8;
2790 
-			S9xSetPCBase(addr);
2791 
-		}
2792 
-	#endif
2391 
+		addr = S9xGetWord(0xFFEE);
2793 2392 
 	}
2794 2393 
 	else
2795 2394 
 	{
2796 
-		PushWE(Registers.PCw);
2395 
+		PushWE(Registers.PC.W.xPC);
2797 2396 
 		S9xPackStatus();
2798 
-		PushBE(Registers.PL);
2799 
-		OpenBus = Registers.PL;
2397 
+		PushBE(Registers.P.B.l);
2398 
+		OpenBus = Registers.P.B.l;
2800 2399 
 		ClearDecimal();
2801 2400 
 		SetIRQ();
2802 2401
2803 
-	#ifdef SA1_OPCODES
2804 
-		OpenBus = Memory.FillRAM[0x2208];
2805 
-		AddCycles(2 * SLOW_ONE_CYCLE);
2806 
-		S9xSA1SetPCBase(Memory.FillRAM[0x2207] | (Memory.FillRAM[0x2208] << 8));
2807 
-	#else
2808 
-		if (Settings.SA1 && (Memory.FillRAM[0x2209] & 0x40))
2809 
-		{
2810 
-			OpenBus = Memory.FillRAM[0x220f];
2811 
-			AddCycles(2 * SLOW_ONE_CYCLE);
2812 
-			S9xSetPCBase(Memory.FillRAM[0x220e] | (Memory.FillRAM[0x220f] << 8));
2813 
-		}
2814 
-		else
2815 
-		{
2816 
-			uint16_t	addr = S9xGetWord(0xFFFE);
2817 
-			OpenBus = addr >> 8;
2818 
-			S9xSetPCBase(addr);
2819 
-		}
2820 
-	#endif
2402 
+		addr = S9xGetWord(0xFFFE);
2821 2403 
 	}
2404 
+	OpenBus = addr >> 8;
2405 
+	S9xSetPCBase(addr);
2822 2406 
 }
2823 2407
2824 2408 
 /* NMI ********************************************************************* */
2825 2409
2826 2410 
 void S9xOpcode_NMI()
2827 2411 
 {
2828 
-#ifdef DEBUGGER
2829 
-	if (CPU.Flags & TRACE_FLAG)
2830 
-	#ifdef SA1_OPCODES
2831 
-		S9xTraceMessage("*** SA1 NMI");
2832 
-	#else
2833 
-		S9xTraceMessage("*** NMI");
2834 
-	#endif
2835 
-#endif
2836 
-
2837 2412 
 	// IRQ and NMI do an opcode fetch as their first "IO" cycle.
2838 2413 
 	AddCycles(CPU.MemSpeed + ONE_CYCLE);
2839 2414
2415 
+	uint16_t addr;
2840 2416 
 	if (!CheckEmulation())
2841 2417 
 	{
2842 
-		PushB(Registers.PB);
2843 
-		PushW(Registers.PCw);
2418 
+		PushB(Registers.PC.B.xPB);
2419 
+		PushW(Registers.PC.W.xPC);
2844 2420 
 		S9xPackStatus();
2845 
-		PushB(Registers.PL);
2846 
-		OpenBus = Registers.PL;
2421 
+		PushB(Registers.P.B.l);
2422 
+		OpenBus = Registers.P.B.l;
2847 2423 
 		ClearDecimal();
2848 2424 
 		SetIRQ();
2849 2425
2850 
-	#ifdef SA1_OPCODES
2851 
-		OpenBus = Memory.FillRAM[0x2206];
2852 
-		AddCycles(2 * SLOW_ONE_CYCLE);
2853 
-		S9xSA1SetPCBase(Memory.FillRAM[0x2205] | (Memory.FillRAM[0x2206] << 8));
2854 
-	#else
2855 
-		if (Settings.SA1 && (Memory.FillRAM[0x2209] & 0x10))
2856 
-		{
2857 
-			OpenBus = Memory.FillRAM[0x220d];
2858 
-			AddCycles(2 * SLOW_ONE_CYCLE);
2859 
-			S9xSetPCBase(Memory.FillRAM[0x220c] | (Memory.FillRAM[0x220d] << 8));
2860 
-		}
2861 
-		else
2862 
-		{
2863 
-			uint16_t	addr = S9xGetWord(0xFFEA);
2864 
-			OpenBus = addr >> 8;
2865 
-			S9xSetPCBase(addr);
2866 
-		}
2867 
-	#endif
2426 
+		addr = S9xGetWord(0xFFEA);
2868 2427 
 	}
2869 2428 
 	else
2870 2429 
 	{
2871 
-		PushWE(Registers.PCw);
2430 
+		PushWE(Registers.PC.W.xPC);
2872 2431 
 		S9xPackStatus();
2873 
-		PushBE(Registers.PL);
2874 
-		OpenBus = Registers.PL;
2432 
+		PushBE(Registers.P.B.l);
2433 
+		OpenBus = Registers.P.B.l;
2875 2434 
 		ClearDecimal();
2876 2435 
 		SetIRQ();
2877 2436
2878 
-	#ifdef SA1_OPCODES
2879 
-		OpenBus = Memory.FillRAM[0x2206];
2880 
-		AddCycles(2 * SLOW_ONE_CYCLE);
2881 
-		S9xSA1SetPCBase(Memory.FillRAM[0x2205] | (Memory.FillRAM[0x2206] << 8));
2882 
-	#else
2883 
-		if (Settings.SA1 && (Memory.FillRAM[0x2209] & 0x10))
2884 
-		{
2885 
-			OpenBus = Memory.FillRAM[0x220d];
2886 
-			AddCycles(2 * SLOW_ONE_CYCLE);
2887 
-			S9xSetPCBase(Memory.FillRAM[0x220c] | (Memory.FillRAM[0x220d] << 8));
2888 
-		}
2889 
-		else
2890 
-		{
2891 
-			uint16_t	addr = S9xGetWord(0xFFFA);
2892 
-			OpenBus = addr >> 8;
2893 
-			S9xSetPCBase(addr);
2894 
-		}
2895 
-	#endif
2437 
+		addr = S9xGetWord(0xFFFA);
2896 2438 
 	}
2439 
+	OpenBus = addr >> 8;
2440 
+	S9xSetPCBase(addr);
2897 2441 
 }
2898 2442
2899 2443 
 /* COP ********************************************************************* */
2900 2444
2901 2445 
 static void Op02()
2902 2446 
 {
2903 
-#ifdef DEBUGGER
2904 
-	if (CPU.Flags & TRACE_FLAG)
2905 
-		S9xTraceMessage("*** COP");
2906 
-#endif
2907 
-
2908 2447 
 	AddCycles(CPU.MemSpeed);
2909 2448
2910 
-	uint16_t	addr;
2911 
-
2912 2449 
 	if (!CheckEmulation())
2913 2450 
 	{
2914 
-		PushB(Registers.PB);
2915 
-		PushW(Registers.PCw + 1);
2451 
+		PushB(Registers.PC.B.xPB);
2452 
+		PushW(Registers.PC.W.xPC + 1);
2916 2453 
 		S9xPackStatus();
2917 
-		PushB(Registers.PL);
2918 
-		OpenBus = Registers.PL;
2919 
-		ClearDecimal();
2920 
-		SetIRQ();
2921 
-
2922 
-		addr = S9xGetWord(0xFFE4);
2454 
+		PushB(Registers.P.B.l);
2923 2455 
 	}
2924 2456 
 	else
2925 2457 
 	{
2926 
-		PushWE(Registers.PCw + 1);
2458 
+		PushWE(Registers.PC.W.xPC + 1);
2927 2459 
 		S9xPackStatus();
2928 
-		PushBE(Registers.PL);
2929 
-		OpenBus = Registers.PL;
2930 
-		ClearDecimal();
2931 
-		SetIRQ();
2932 
-
2933 
-		addr = S9xGetWord(0xFFF4);
2460 
+		PushBE(Registers.P.B.l);
2934 2461 
 	}
2462 
+	OpenBus = Registers.P.B.l;
2463 
+	ClearDecimal();
2464 
+	SetIRQ();
2465 
+
2466 
+	uint16_t addr = S9xGetWord(0xFFF4);
2935 2467
2936 2468 
 	S9xSetPCBase(addr);
2937 2469 
 	OpenBus = addr >> 8;
... ... 
@@ -2939,417 +2471,304 @@ static void Op02()
2939 2471
2940 2472 
 /* JML ********************************************************************* */
2941 2473
2474 
+template<typename F> static inline void JMLWrapper(F f)
2475 
+{
2476 
+	S9xSetPCBase(f(JUMP));
2477 
+}
2478 
+
2942 2479 
 static void OpDC()
2943 2480 
 {
2944 
-	S9xSetPCBase(AbsoluteIndirectLong(JUMP));
2481 
+	JMLWrapper(AbsoluteIndirectLong);
2945 2482 
 }
2946 2483
2947 2484 
 static void OpDCSlow()
2948 2485 
 {
2949 
-	S9xSetPCBase(AbsoluteIndirectLongSlow(JUMP));
2486 
+	JMLWrapper(AbsoluteIndirectLongSlow);
2950 2487 
 }
2951 2488
2952 2489 
 static void Op5C()
2953 2490 
 {
2954 
-	S9xSetPCBase(AbsoluteLong(JUMP));
2491 
+	JMLWrapper(AbsoluteLong);
2955 2492 
 }
2956 2493
2957 2494 
 static void Op5CSlow()
2958 2495 
 {
2959 
-	S9xSetPCBase(AbsoluteLongSlow(JUMP));
2496 
+	JMLWrapper(AbsoluteLongSlow);
2960 2497 
 }
2961 2498
2962 2499 
 /* JMP ********************************************************************* */
2963 2500
2501 
+template<typename F> static inline void JMPWrapper(F f)
2502 
+{
2503 
+	S9xSetPCBase(ICPU.ShiftedPB + static_cast<uint16_t>(f(JUMP)));
2504 
+}
2505 
+
2964 2506 
 static void Op4C()
2965 2507 
 {
2966 
-	S9xSetPCBase(ICPU.ShiftedPB + ((uint16_t) Absolute(JUMP)));
2508 
+	JMPWrapper(Absolute);
2967 2509 
 }
2968 2510
2969 2511 
 static void Op4CSlow()
2970 2512 
 {
2971 
-	S9xSetPCBase(ICPU.ShiftedPB + ((uint16_t) AbsoluteSlow(JUMP)));
2513 
+	JMPWrapper(AbsoluteSlow);
2972 2514 
 }
2973 2515
2974 2516 
 static void Op6C()
2975 2517 
 {
2976 
-	S9xSetPCBase(ICPU.ShiftedPB + ((uint16_t) AbsoluteIndirect(JUMP)));
2518 
+	JMPWrapper(AbsoluteIndirect);
2977 2519 
 }
2978 2520
2979 2521 
 static void Op6CSlow()
2980 2522 
 {
2981 
-	S9xSetPCBase(ICPU.ShiftedPB + ((uint16_t) AbsoluteIndirectSlow(JUMP)));
2523 
+	JMPWrapper(AbsoluteIndirectSlow);
2982 2524 
 }
2983 2525
2984 2526 
 static void Op7C()
2985 2527 
 {
2986 
-	S9xSetPCBase(ICPU.ShiftedPB + ((uint16_t) AbsoluteIndexedIndirect(JUMP)));
2528 
+	JMPWrapper(AbsoluteIndexedIndirect);
2987 2529 
 }
2988 2530
2989 2531 
 static void Op7CSlow()
2990 2532 
 {
2991 
-	S9xSetPCBase(ICPU.ShiftedPB + ((uint16_t) AbsoluteIndexedIndirectSlow(JUMP)));
2533 
+	JMPWrapper(AbsoluteIndexedIndirectSlow);
2992 2534 
 }
2993 2535
2994 2536 
 /* JSL/RTL ***************************************************************** */
2995 2537
2996 
-static void Op22E1()
2538 
+template<typename F> static inline void Op22Wrapper(F f, bool cond)
2997 2539 
 {
2998 
-	// Note: JSL is a new instruction,
2999 
-	// and so doesn't respect the emu-mode stack bounds.
3000 
-	uint32_t	addr = AbsoluteLong(JSR);
3001 
-	PushB(Registers.PB);
3002 
-	PushW(Registers.PCw - 1);
3003 
-	Registers.SH = 1;
2540 
+	uint32_t addr = f(JSR);
2541 
+	PushB(Registers.PC.B.xPB);
2542 
+	PushW(Registers.PC.W.xPC - 1);
2543 
+	if (cond)
2544 
+		Registers.S.B.h = 1;
3004 2545 
 	S9xSetPCBase(addr);
3005 2546 
 }
3006 2547
3007 2548 
 static void Op22E0()
3008 2549 
 {
3009 
-	uint32_t	addr = AbsoluteLong(JSR);
3010 
-	PushB(Registers.PB);
3011 
-	PushW(Registers.PCw - 1);
3012 
-	S9xSetPCBase(addr);
2550 
+	Op22Wrapper(AbsoluteLong, false);
2551 
+}
2552 
+
2553 
+static void Op22E1()
2554 
+{
2555 
+	// Note: JSL is a new instruction,
2556 
+	// and so doesn't respect the emu-mode stack bounds.
2557 
+	Op22Wrapper(AbsoluteLong, true);
3013 2558 
 }
3014 2559
3015 2560 
 static void Op22Slow()
3016 2561 
 {
3017 
-	uint32_t	addr = AbsoluteLongSlow(JSR);
3018 
-	PushB(Registers.PB);
3019 
-	PushW(Registers.PCw - 1);
3020 
-	if (CheckEmulation())
3021 
-		Registers.SH = 1;
3022 
-	S9xSetPCBase(addr);
2562 
+	Op22Wrapper(AbsoluteLongSlow, CheckEmulation());
3023 2563 
 }
3024 2564
3025 
-static void Op6BE1()
2565 
+static inline void Op6BWrapper(bool cond)
3026 2566 
 {
3027 
-	// Note: RTL is a new instruction,
3028 
-	// and so doesn't respect the emu-mode stack bounds.
3029 2567 
 	AddCycles(TWO_CYCLES);
3030 
-	PullW(Registers.PCw);
3031 
-	PullB(Registers.PB);
3032 
-	Registers.SH = 1;
3033 
-	Registers.PCw++;
3034 
-	S9xSetPCBase(Registers.PBPC);
2568 
+	PullW(Registers.PC.W.xPC);
2569 
+	PullB(Registers.PC.B.xPB);
2570 
+	if (cond)
2571 
+		Registers.S.B.h = 1;
2572 
+	++Registers.PC.W.xPC;
2573 
+	S9xSetPCBase(Registers.PC.xPBPC);
3035 2574 
 }
3036 2575
3037 2576 
 static void Op6BE0()
3038 2577 
 {
3039 
-	AddCycles(TWO_CYCLES);
3040 
-	PullW(Registers.PCw);
3041 
-	PullB(Registers.PB);
3042 
-	Registers.PCw++;
3043 
-	S9xSetPCBase(Registers.PBPC);
2578 
+	Op6BWrapper(false);
2579 
+}
2580 
+
2581 
+static void Op6BE1()
2582 
+{
2583 
+	// Note: RTL is a new instruction,
2584 
+	// and so doesn't respect the emu-mode stack bounds.
2585 
+	Op6BWrapper(true);
3044 2586 
 }
3045 2587
3046 2588 
 static void Op6BSlow()
3047 2589 
 {
3048 
-	AddCycles(TWO_CYCLES);
3049 
-	PullW(Registers.PCw);
3050 
-	PullB(Registers.PB);
3051 
-	if (CheckEmulation())
3052 
-		Registers.SH = 1;
3053 
-	Registers.PCw++;
3054 
-	S9xSetPCBase(Registers.PBPC);
2590 
+	Op6BWrapper(CheckEmulation());
3055 2591 
 }
3056 2592
3057 2593 
 /* JSR/RTS ***************************************************************** */
3058 2594
3059 
-static void Op20E1()
2595 
+template<typename F> static inline void Op20Wrapper(F f)
3060 2596 
 {
3061 
-	uint16_t	addr = Absolute(JSR);
2597 
+	uint16_t addr = Absolute(JSR);
3062 2598 
 	AddCycles(ONE_CYCLE);
3063 
-	PushWE(Registers.PCw - 1);
2599 
+	f(Registers.PC.W.xPC - 1);
3064 2600 
 	S9xSetPCBase(ICPU.ShiftedPB + addr);
3065 2601 
 }
3066 2602
3067 
-static void Op20E0()
2603 
+static inline void Op20E1()
3068 2604 
 {
3069 
-	uint16_t	addr = Absolute(JSR);
3070 
-	AddCycles(ONE_CYCLE);
3071 
-	PushW(Registers.PCw - 1);
3072 
-	S9xSetPCBase(ICPU.ShiftedPB + addr);
2605 
+	Op20Wrapper(PushWE);
3073 2606 
 }
3074 2607
3075 
-static void Op20Slow()
2608 
+static void Op20E0()
3076 2609 
 {
3077 
-	uint16_t	addr = AbsoluteSlow(JSR);
3078 
-
3079 
-	AddCycles(ONE_CYCLE);
2610 
+	Op20Wrapper(PushW);
2611 
+}
3080 2612
2613 
+static inline void Op20Slow()
2614 
+{
3081 2615 
 	if (CheckEmulation())
3082 
-	{
3083 
-		PushWE(Registers.PCw - 1);
3084 
-	}
2616 
+		Op20E1();
3085 2617 
 	else
3086 
-	{
3087 
-		PushW(Registers.PCw - 1);
3088 
-	}
3089 
-
3090 
-	S9xSetPCBase(ICPU.ShiftedPB + addr);
2618 
+		Op20E0();
3091 2619 
 }
3092 2620
3093 
-static void OpFCE1()
2621 
+template<typename F> static inline void OpFCWrapper(F f, bool cond)
3094 2622 
 {
3095 
-	// Note: JSR (a,X) is a new instruction,
3096 
-	// and so doesn't respect the emu-mode stack bounds.
3097 
-	uint16_t	addr = AbsoluteIndexedIndirect(JSR);
3098 
-	PushW(Registers.PCw - 1);
3099 
-	Registers.SH = 1;
2623 
+	uint16_t addr = f(JSR);
2624 
+	PushW(Registers.PC.W.xPC - 1);
2625 
+	if (cond)
2626 
+		Registers.S.B.h = 1;
3100 2627 
 	S9xSetPCBase(ICPU.ShiftedPB + addr);
3101 2628 
 }
3102 2629
3103 2630 
 static void OpFCE0()
3104 2631 
 {
3105 
-	uint16_t	addr = AbsoluteIndexedIndirect(JSR);
3106 
-	PushW(Registers.PCw - 1);
3107 
-	S9xSetPCBase(ICPU.ShiftedPB + addr);
2632 
+	OpFCWrapper(AbsoluteIndexedIndirect, false);
3108 2633 
 }
3109 2634
3110 
-static void OpFCSlow()
2635 
+static void OpFCE1()
3111 2636 
 {
3112 
-	uint16_t	addr = AbsoluteIndexedIndirectSlow(JSR);
3113 
-	PushW(Registers.PCw - 1);
3114 
-	if (CheckEmulation())
3115 
-		Registers.SH = 1;
3116 
-	S9xSetPCBase(ICPU.ShiftedPB + addr);
2637 
+	// Note: JSR (a,X) is a new instruction,
2638 
+	// and so doesn't respect the emu-mode stack bounds.
2639 
+	OpFCWrapper(AbsoluteIndexedIndirect, true);
3117 2640 
 }
3118 2641
3119 
-static void Op60E1()
2642 
+static void OpFCSlow()
3120 2643 
 {
3121 
-	AddCycles(TWO_CYCLES);
3122 
-	PullWE(Registers.PCw);
3123 
-	AddCycles(ONE_CYCLE);
3124 
-	Registers.PCw++;
3125 
-	S9xSetPCBase(Registers.PBPC);
2644 
+	OpFCWrapper(AbsoluteIndexedIndirectSlow, CheckEmulation());
3126 2645 
 }
3127 2646
3128 
-static void Op60E0()
2647 
+template<typename F> static inline void Op60Wrapper(F f)
3129 2648 
 {
3130 2649 
 	AddCycles(TWO_CYCLES);
3131 
-	PullW(Registers.PCw);
2650 
+	f(Registers.PC.W.xPC);
3132 2651 
 	AddCycles(ONE_CYCLE);
3133 
-	Registers.PCw++;
3134 
-	S9xSetPCBase(Registers.PBPC);
2652 
+	++Registers.PC.W.xPC;
2653 
+	S9xSetPCBase(Registers.PC.xPBPC);
3135 2654 
 }
3136 2655
3137 
-static void Op60Slow()
2656 
+static inline void Op60E1()
3138 2657 
 {
3139 
-	AddCycles(TWO_CYCLES);
3140 
-
3141 
-	if (CheckEmulation())
3142 
-	{
3143 
-		PullWE(Registers.PCw);
3144 
-	}
3145 
-	else
3146 
-	{
3147 
-		PullW(Registers.PCw);
3148 
-	}
3149 
-
3150 
-	AddCycles(ONE_CYCLE);
3151 
-	Registers.PCw++;
3152 
-	S9xSetPCBase(Registers.PBPC);
2658 
+	Op60Wrapper(PullWE);
3153 2659 
 }
3154 2660
3155 
-/* MVN/MVP ***************************************************************** */
3156 
-
3157 
-static void Op54X1()
2661 
+static inline void Op60E0()
3158 2662 
 {
3159 
-	uint32_t	SrcBank;
3160 
-
3161 
-	Registers.DB = Immediate8(NONE);
3162 
-	ICPU.ShiftedDB = Registers.DB << 16;
3163 
-	OpenBus = SrcBank = Immediate8(NONE);
3164 
-
3165 
-	S9xSetByte(OpenBus = S9xGetByte((SrcBank << 16) + Registers.X.W), ICPU.ShiftedDB + Registers.Y.W);
3166 
-
3167 
-	Registers.XL++;
3168 
-	Registers.YL++;
3169 
-	Registers.A.W--;
3170 
-	if (Registers.A.W != 0xffff)
3171 
-		Registers.PCw -= 3;
3172 
-
3173 
-	AddCycles(TWO_CYCLES);
2663 
+	Op60Wrapper(PullW);
3174 2664 
 }
3175 2665
3176 
-static void Op54X0()
2666 
+static void Op60Slow()
3177 2667 
 {
3178 
-	uint32_t	SrcBank;
3179 
-
3180 
-	Registers.DB = Immediate8(NONE);
3181 
-	ICPU.ShiftedDB = Registers.DB << 16;
3182 
-	OpenBus = SrcBank = Immediate8(NONE);
3183 
-
3184 
-	S9xSetByte(OpenBus = S9xGetByte((SrcBank << 16) + Registers.X.W), ICPU.ShiftedDB + Registers.Y.W);
3185 
-
3186 
-	Registers.X.W++;
3187 
-	Registers.Y.W++;
3188 
-	Registers.A.W--;
3189 
-	if (Registers.A.W != 0xffff)
3190 
-		Registers.PCw -= 3;
3191 
-
3192 
-	AddCycles(TWO_CYCLES);
2668 
+	if (CheckEmulation())
2669 
+		Op60E1();
2670 
+	else
2671 
+		Op60E0();
3193 2672 
 }
3194 2673
3195 
-static void Op54Slow()
2674 
+/* MVN/MVP ***************************************************************** */
2675 
+
2676 
+template<typename F> static inline void MVWrapper(F f, bool cond, int inc, bool setOpenBusOnFirstF = false)
3196 2677 
 {
3197 
-	uint32_t	SrcBank;
2678 
+	uint32_t SrcBank;
3198 2679
3199 
-	OpenBus = Registers.DB = Immediate8Slow(NONE);
2680 
+	Registers.DB = f(NONE);
2681 
+	if (setOpenBusOnFirstF)
2682 
+		OpenBus = Registers.DB;
3200 2683 
 	ICPU.ShiftedDB = Registers.DB << 16;
3201 
-	OpenBus = SrcBank = Immediate8Slow(NONE);
2684 
+	OpenBus = SrcBank = f(NONE);
3202 2685
3203 2686 
 	S9xSetByte(OpenBus = S9xGetByte((SrcBank << 16) + Registers.X.W), ICPU.ShiftedDB + Registers.Y.W);
3204 2687
3205 
-	if (CheckIndex())
2688 
+	if (cond)
3206 2689 
 	{
3207 
-		Registers.XL++;
3208 
-		Registers.YL++;
2690 
+		Registers.X.B.l += inc;
2691 
+		Registers.Y.B.l += inc;
3209 2692 
 	}
3210 2693 
 	else
3211 2694 
 	{
3212 
-		Registers.X.W++;
3213 
-		Registers.Y.W++;
2695 
+		Registers.X.W += inc;
2696 
+		Registers.Y.W += inc;
3214 2697 
 	}
3215 2698
3216 
-	Registers.A.W--;
2699 
+	--Registers.A.W;
3217 2700 
 	if (Registers.A.W != 0xffff)
3218 
-		Registers.PCw -= 3;
2701 
+		Registers.PC.W.xPC -= 3;
3219 2702
3220 2703 
 	AddCycles(TWO_CYCLES);
3221 2704 
 }
3222 2705
3223 
-static void Op44X1()
2706 
+static void Op54X1()
3224 2707 
 {
3225 
-	uint32_t	SrcBank;
3226 
-
3227 
-	Registers.DB = Immediate8(NONE);
3228 
-	ICPU.ShiftedDB = Registers.DB << 16;
3229 
-	OpenBus = SrcBank = Immediate8(NONE);
2708 
+	MVWrapper(Immediate8, true, 1);
2709 
+}
3230 2710
3231 
-	S9xSetByte(OpenBus = S9xGetByte((SrcBank << 16) + Registers.X.W), ICPU.ShiftedDB + Registers.Y.W);
2711 
+static void Op54X0()
2712 
+{
2713 
+	MVWrapper(Immediate8, false, 1);
2714 
+}
3232 2715
3233 
-	Registers.XL--;
3234 
-	Registers.YL--;
3235 
-	Registers.A.W--;
3236 
-	if (Registers.A.W != 0xffff)
3237 
-		Registers.PCw -= 3;
2716 
+static void Op54Slow()
2717 
+{
2718 
+	MVWrapper(Immediate8Slow, CheckIndex(), 1, true);
2719 
+}
3238 2720
3239 
-	AddCycles(TWO_CYCLES);
2721 
+static void Op44X1()
2722 
+{
2723 
+	MVWrapper(Immediate8, true, -1);
3240 2724 
 }
3241 2725
3242 2726 
 static void Op44X0()
3243 2727 
 {
3244 
-	uint32_t	SrcBank;
3245 
-
3246 
-	Registers.DB = Immediate8(NONE);
3247 
-	ICPU.ShiftedDB = Registers.DB << 16;
3248 
-	OpenBus = SrcBank = Immediate8(NONE);
3249 
-
3250 
-	S9xSetByte(OpenBus = S9xGetByte((SrcBank << 16) + Registers.X.W), ICPU.ShiftedDB + Registers.Y.W);
3251 
-
3252 
-	Registers.X.W--;
3253 
-	Registers.Y.W--;
3254 
-	Registers.A.W--;
3255 
-	if (Registers.A.W != 0xffff)
3256 
-		Registers.PCw -= 3;
3257 
-
3258 
-	AddCycles(TWO_CYCLES);
2728 
+	MVWrapper(Immediate8, false, -1);
3259 2729 
 }
3260 2730
3261 2731 
 static void Op44Slow()
3262 2732 
 {
3263 
-	uint32_t	SrcBank;
3264 
-
3265 
-	OpenBus = Registers.DB = Immediate8Slow(NONE);
3266 
-	ICPU.ShiftedDB = Registers.DB << 16;
3267 
-	OpenBus = SrcBank = Immediate8Slow(NONE);
3268 
-
3269 
-	S9xSetByte(OpenBus = S9xGetByte((SrcBank << 16) + Registers.X.W), ICPU.ShiftedDB + Registers.Y.W);
3270 
-
3271 
-	if (CheckIndex())
3272 
-	{
3273 
-		Registers.XL--;
3274 
-		Registers.YL--;
3275 
-	}
3276 
-	else
3277 
-	{
3278 
-		Registers.X.W--;
3279 
-		Registers.Y.W--;
3280 
-	}
3281 
-
3282 
-	Registers.A.W--;
3283 
-	if (Registers.A.W != 0xffff)
3284 
-		Registers.PCw -= 3;
3285 
-
3286 
-	AddCycles(TWO_CYCLES);
2733 
+	MVWrapper(Immediate8Slow, CheckIndex(), -1, true);
3287 2734 
 }
3288 2735
3289 2736 
 /* REP/SEP ***************************************************************** */
3290 2737
3291 
-static void OpC2()
2738 
+template<typename F> static inline void OpC2Wrapper(F f)
3292 2739 
 {
3293 
-	uint8_t	Work8 = ~Immediate8(READ);
3294 
-	Registers.PL &= Work8;
2740 
+	uint8_t Work8 = ~f(READ);
2741 
+	Registers.P.B.l &= Work8;
3295 2742 
 	ICPU._Carry &= Work8;
3296 
-	ICPU._Overflow &= (Work8 >> 6);
2743 
+	ICPU._Overflow &= Work8 >> 6;
3297 2744 
 	ICPU._Negative &= Work8;
3298 2745 
 	ICPU._Zero |= ~Work8 & Zero;
3299 2746
3300 2747 
 	AddCycles(ONE_CYCLE);
3301 2748
3302 2749 
 	if (CheckEmulation())
3303 
-	{
3304 2750 
 		SetFlags(MemoryFlag | IndexFlag);
3305 
-	#ifdef DEBUGGER
3306 
-		missing.emulate6502 = 1;
3307 
-	#endif
3308 
-	}
3309 2751
3310 2752 
 	if (CheckIndex())
3311 
-	{
3312 
-		Registers.XH = 0;
3313 
-		Registers.YH = 0;
3314 
-	}
2753 
+		Registers.X.B.h = Registers.Y.B.h = 0;
3315 2754
3316 2755 
 	S9xFixCycles();
3317 
-	CHECK_FOR_IRQ();
3318 2756 
 }
3319 2757
3320 
-static void OpC2Slow()
2758 
+static void OpC2()
3321 2759 
 {
3322 
-	uint8_t	Work8 = ~Immediate8Slow(READ);
3323 
-	Registers.PL &= Work8;
3324 
-	ICPU._Carry &= Work8;
3325 
-	ICPU._Overflow &= (Work8 >> 6);
3326 
-	ICPU._Negative &= Work8;
3327 
-	ICPU._Zero |= ~Work8 & Zero;
3328 
-
3329 
-	AddCycles(ONE_CYCLE);
3330 
-
3331 
-	if (CheckEmulation())
3332 
-	{
3333 
-		SetFlags(MemoryFlag | IndexFlag);
3334 
-	#ifdef DEBUGGER
3335 
-		missing.emulate6502 = 1;
3336 
-	#endif
3337 
-	}
3338 
-
3339 
-	if (CheckIndex())
3340 
-	{
3341 
-		Registers.XH = 0;
3342 
-		Registers.YH = 0;
3343 
-	}
2760 
+	OpC2Wrapper(Immediate8);
2761 
+}
3344 2762
3345 
-	S9xFixCycles();
3346 
-	CHECK_FOR_IRQ();
2763 
+static void OpC2Slow()
2764 
+{
2765 
+	OpC2Wrapper(Immediate8Slow);
3347 2766 
 }
3348 2767
3349 
-static void OpE2()
2768 
+template<typename F> static inline void OpE2Wrapper(F f)
3350 2769 
 {
3351 
-	uint8_t	Work8 = Immediate8(READ);
3352 
-	Registers.PL |= Work8;
2770 
+	uint8_t Work8 = f(READ);
2771 
+	Registers.P.B.l |= Work8;
3353 2772 
 	ICPU._Carry |= Work8 & 1;
3354 2773 
 	ICPU._Overflow |= (Work8 >> 6) & 1;
3355 2774 
 	ICPU._Negative |= Work8;
... ... 
@@ -3359,59 +2778,30 @@ static void OpE2()
3359 2778 
 	AddCycles(ONE_CYCLE);
3360 2779
3361 2780 
 	if (CheckEmulation())
3362 
-	{
3363 2781 
 		SetFlags(MemoryFlag | IndexFlag);
3364 
-	#ifdef DEBUGGER
3365 
-		missing.emulate6502 = 1;
3366 
-	#endif
3367 
-	}
3368 2782
3369 2783 
 	if (CheckIndex())
3370 
-	{
3371 
-		Registers.XH = 0;
3372 
-		Registers.YH = 0;
3373 
-	}
2784 
+		Registers.X.B.h = Registers.Y.B.h = 0;
3374 2785
3375 2786 
 	S9xFixCycles();
3376 2787 
 }
3377 2788
3378 
-static void OpE2Slow()
2789 
+static void OpE2()
3379 2790 
 {
3380 
-	uint8_t	Work8 = Immediate8Slow(READ);
3381 
-	Registers.PL |= Work8;
3382 
-	ICPU._Carry |= Work8 & 1;
3383 
-	ICPU._Overflow |= (Work8 >> 6) & 1;
3384 
-	ICPU._Negative |= Work8;
3385 
-	if (Work8 & Zero)
3386 
-		ICPU._Zero = 0;
3387 
-
3388 
-	AddCycles(ONE_CYCLE);
3389 
-
3390 
-	if (CheckEmulation())
3391 
-	{
3392 
-		SetFlags(MemoryFlag | IndexFlag);
3393 
-	#ifdef DEBUGGER
3394 
-		missing.emulate6502 = 1;
3395 
-	#endif
3396 
-	}
3397 
-
3398 
-	if (CheckIndex())
3399 
-	{
3400 
-		Registers.XH = 0;
3401 
-		Registers.YH = 0;
3402 
-	}
2791 
+	OpE2Wrapper(Immediate8);
2792 
+}
3403 2793
3404 
-	S9xFixCycles();
2794 
+static void OpE2Slow()
2795 
+{
2796 
+	OpE2Wrapper(Immediate8Slow);
3405 2797 
 }
3406 2798
3407 2799 
 /* XBA ********************************************************************* */
3408 2800
3409 2801 
 static void OpEB()
3410 2802 
 {
3411 
-	uint8_t	Work8 = Registers.AL;
3412 
-	Registers.AL = Registers.AH;
3413 
-	Registers.AH = Work8;
3414 
-	SetZN(Registers.AL);
2803 
+	std::swap(Registers.A.B.l, Registers.A.B.h);
2804 
+	SetZN(Registers.A.B.l);
3415 2805 
 	AddCycles(TWO_CYCLES);
3416 2806 
 }
3417 2807
... ... 
@@ -3423,35 +2813,28 @@ static void Op40Slow()
3423 2813
3424 2814 
 	if (!CheckEmulation())
3425 2815 
 	{
3426 
-		PullB(Registers.PL);
2816 
+		PullB(Registers.P.B.l);
3427 2817 
 		S9xUnpackStatus();
3428 
-		PullW(Registers.PCw);
3429 
-		PullB(Registers.PB);
3430 
-		OpenBus = Registers.PB;
3431 
-		ICPU.ShiftedPB = Registers.PB << 16;
2818 
+		PullW(Registers.PC.W.xPC);
2819 
+		PullB(Registers.PC.B.xPB);
2820 
+		OpenBus = Registers.PC.B.xPB;
2821 
+		ICPU.ShiftedPB = Registers.PC.B.xPB << 16;
3432 2822 
 	}
3433 2823 
 	else
3434 2824 
 	{
3435 
-		PullBE(Registers.PL);
2825 
+		PullBE(Registers.P.B.l);
3436 2826 
 		S9xUnpackStatus();
3437 
-		PullWE(Registers.PCw);
3438 
-		OpenBus = Registers.PCh;
2827 
+		PullWE(Registers.PC.W.xPC);
2828 
+		OpenBus = Registers.PC.B.xPCh;
3439 2829 
 		SetFlags(MemoryFlag | IndexFlag);
3440 
-	#ifdef DEBUGGER
3441 
-		missing.emulate6502 = 1;
3442 
-	#endif
3443 2830 
 	}
3444 2831
3445 
-	S9xSetPCBase(Registers.PBPC);
2832 
+	S9xSetPCBase(Registers.PC.xPBPC);
3446 2833
3447 2834 
 	if (CheckIndex())
3448 
-	{
3449 
-		Registers.XH = 0;
3450 
-		Registers.YH = 0;
3451 
-	}
2835 
+		Registers.X.B.h = Registers.Y.B.h = 0;
3452 2836
3453 2837 
 	S9xFixCycles();
3454 
-	CHECK_FOR_IRQ();
3455 2838 
 }
3456 2839
3457 2840 
 /* STP/WAI ***************************************************************** */
... ... 
@@ -3459,92 +2842,24 @@ static void Op40Slow()
3459 2842 
 // WAI
3460 2843 
 static void OpCB()
3461 2844 
 {
3462 
-#ifdef SA1_OPCODES
3463 
-	SA1.WaitingForInterrupt = true;
3464 
-	Registers.PCw--;
3465 
-	AddCycles(TWO_CYCLES);
3466 
-#else
3467 2845 
 	CPU.WaitingForInterrupt = true;
3468 
-	Registers.PCw--;
2846 
+	--Registers.PC.W.xPC;
3469 2847 
 	AddCycles(TWO_CYCLES);
3470 
-#endif
3471 2848 
 }
3472 2849
3473 2850 
 // STP
3474 2851 
 static void OpDB()
3475 2852 
 {
3476 
-	Registers.PCw--;
2853 
+	--Registers.PC.W.xPC;
3477 2854 
 	CPU.Flags |= DEBUG_MODE_FLAG | HALTED_FLAG;
3478 2855 
 }
3479 2856
3480 2857 
 /* WDM (Reserved S9xOpcode) ************************************************ */
3481 2858
3482 
-#ifdef DEBUGGER
3483 
-extern FILE	*trace, *trace2;
3484 
-#endif
3485 
-
3486 2859 
 static void Op42()
3487 2860 
 {
3488 
-#ifdef DEBUGGER
3489 
-	uint8_t	byte = (uint8_t) S9xGetWord(Registers.PBPC);
3490 
-#else
3491 
-	S9xGetWord(Registers.PBPC);
3492 
-#endif
3493 
-	Registers.PCw++;
3494 
-
3495 
-#ifdef DEBUGGER
3496 
-	// Hey, let's use this to trigger debug modes.
3497 
-	switch (byte)
3498 
-	{
3499 
-		case 0xdb: // "STP" = Enter debug mode
3500 
-			CPU.Flags |= DEBUG_MODE_FLAG;
3501 
-			break;
3502 
-
3503 
-	#ifndef SA1_OPCODES
3504 
-		case 0xe2: // "SEP" = Trace on
3505 
-			if (!(CPU.Flags & TRACE_FLAG))
3506 
-			{
3507 
-				char	buf[25];
3508 
-				CPU.Flags |= TRACE_FLAG;
3509 
-				snprintf(buf, 25, "WDM trace on at $%02X:%04X", Registers.PB, Registers.PCw);
3510 
-				S9xMessage(S9X_DEBUG, S9X_DEBUG_OUTPUT, buf);
3511 
-				if (trace != NULL)
3512 
-					fclose(trace);
3513 
-				ENSURE_TRACE_OPEN(trace, "WDMtrace.log", "ab")
3514 
-			}
3515 
-
3516 
-			break;
3517 
-
3518 
-		case 0xc2: // "REP" = Trace off
3519 
-			if (CPU.Flags & TRACE_FLAG)
3520 
-			{
3521 
-				char	buf[26];
3522 
-				CPU.Flags &= ~TRACE_FLAG;
3523 
-				snprintf(buf, 26, "WDM trace off at $%02X:%04X", Registers.PB, Registers.PCw);
3524 
-				S9xMessage(S9X_DEBUG, S9X_DEBUG_OUTPUT, buf);
3525 
-				if (trace != NULL)
3526 
-					fclose(trace);
3527 
-				trace = NULL;
3528 
-			}
3529 
-
3530 
-			break;
3531 
-	#endif
3532 
-
3533 
-		case 0x42: // "WDM" = Snapshot
3534 
-			char	filename[PATH_MAX + 1], drive[_MAX_DRIVE + 1], dir[_MAX_DIR + 1], def[PATH_MAX + 1], ext[_MAX_EXT + 1];
3535 
-
3536 
-			_splitpath(Memory.ROMFilename, drive, dir, def, ext);
3537 
-			snprintf(filename, PATH_MAX, "%s%s%s-%06X.wdm", S9xGetDirectory(SNAPSHOT_DIR), SLASH_STR, def, Registers.PBPC & 0xffffff);
3538 
-			sprintf(def, "WDM Snapshot at $%02X:%04X: %s", Registers.PB, Registers.PCw, filename);
3539 
-			S9xMessage(S9X_DEBUG, S9X_DEBUG_OUTPUT, def);
3540 
-			S9xFreezeGame(filename);
3541 
-
3542 
-			break;
3543 
-
3544 
-		default:
3545 
-			break;
3546 
-	}
3547 
-#endif
2861 
+	S9xGetWord(Registers.PC.xPBPC);
2862 
+	++Registers.PC.W.xPC;
3548 2863 
 }
3549 2864
3550 2865 
 /* CPU-S9xOpcodes Definitions ************************************************/
Browse code

Import actual code.

Naram Qashat authored on 2013/03/26 02:41:19
Showing 1 changed files
src/in_snsf/snes9x/cpuops.cpp
History View file @ bc076aa
1 1 
new file mode 100644
... ... 
@@ -0,0 +1,3886 @@
1 
+/***********************************************************************************
2 
+  Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
3 
+
4 
+  (c) Copyright 1996 - 2002  Gary Henderson (gary.henderson@ntlworld.com),
5 
+                             Jerremy Koot (jkoot@snes9x.com)
6 
+
7 
+  (c) Copyright 2002 - 2004  Matthew Kendora
8 
+
9 
+  (c) Copyright 2002 - 2005  Peter Bortas (peter@bortas.org)
10 
+
11 
+  (c) Copyright 2004 - 2005  Joel Yliluoma (http://iki.fi/bisqwit/)
12 
+
13 
+  (c) Copyright 2001 - 2006  John Weidman (jweidman@slip.net)
14 
+
15 
+  (c) Copyright 2002 - 2006  funkyass (funkyass@spam.shaw.ca),
16 
+                             Kris Bleakley (codeviolation@hotmail.com)
17 
+
18 
+  (c) Copyright 2002 - 2010  Brad Jorsch (anomie@users.sourceforge.net),
19 
+                             Nach (n-a-c-h@users.sourceforge.net),
20 
+
21 
+  (c) Copyright 2002 - 2011  zones (kasumitokoduck@yahoo.com)
22 
+
23 
+  (c) Copyright 2006 - 2007  nitsuja
24 
+
25 
+  (c) Copyright 2009 - 2011  BearOso,
26 
+                             OV2
27 
+
28 
+
29 
+  BS-X C emulator code
30 
+  (c) Copyright 2005 - 2006  Dreamer Nom,
31 
+                             zones
32 
+
33 
+  C4 x86 assembler and some C emulation code
34 
+  (c) Copyright 2000 - 2003  _Demo_ (_demo_@zsnes.com),
35 
+                             Nach,
36 
+                             zsKnight (zsknight@zsnes.com)
37 
+
38 
+  C4 C++ code
39 
+  (c) Copyright 2003 - 2006  Brad Jorsch,
40 
+                             Nach
41 
+
42 
+  DSP-1 emulator code
43 
+  (c) Copyright 1998 - 2006  _Demo_,
44 
+                             Andreas Naive (andreasnaive@gmail.com),
45 
+                             Gary Henderson,
46 
+                             Ivar (ivar@snes9x.com),
47 
+                             John Weidman,
48 
+                             Kris Bleakley,
49 
+                             Matthew Kendora,
50 
+                             Nach,
51 
+                             neviksti (neviksti@hotmail.com)
52 
+
53 
+  DSP-2 emulator code
54 
+  (c) Copyright 2003         John Weidman,
55 
+                             Kris Bleakley,
56 
+                             Lord Nightmare (lord_nightmare@users.sourceforge.net),
57 
+                             Matthew Kendora,
58 
+                             neviksti
59 
+
60 
+  DSP-3 emulator code
61 
+  (c) Copyright 2003 - 2006  John Weidman,
62 
+                             Kris Bleakley,
63 
+                             Lancer,
64 
+                             z80 gaiden
65 
+
66 
+  DSP-4 emulator code
67 
+  (c) Copyright 2004 - 2006  Dreamer Nom,
68 
+                             John Weidman,
69 
+                             Kris Bleakley,
70 
+                             Nach,
71 
+                             z80 gaiden
72 
+
73 
+  OBC1 emulator code
74 
+  (c) Copyright 2001 - 2004  zsKnight,
75 
+                             pagefault (pagefault@zsnes.com),
76 
+                             Kris Bleakley
77 
+                             Ported from x86 assembler to C by sanmaiwashi
78 
+
79 
+  SPC7110 and RTC C++ emulator code used in 1.39-1.51
80 
+  (c) Copyright 2002         Matthew Kendora with research by
81 
+                             zsKnight,
82 
+                             John Weidman,
83 
+                             Dark Force
84 
+
85 
+  SPC7110 and RTC C++ emulator code used in 1.52+
86 
+  (c) Copyright 2009         byuu,
87 
+                             neviksti
88 
+
89 
+  S-DD1 C emulator code
90 
+  (c) Copyright 2003         Brad Jorsch with research by
91 
+                             Andreas Naive,
92 
+                             John Weidman
93 
+
94 
+  S-RTC C emulator code
95 
+  (c) Copyright 2001 - 2006  byuu,
96 
+                             John Weidman
97 
+
98 
+  ST010 C++ emulator code
99 
+  (c) Copyright 2003         Feather,
100 
+                             John Weidman,
101 
+                             Kris Bleakley,
102 
+                             Matthew Kendora
103 
+
104 
+  Super FX x86 assembler emulator code
105 
+  (c) Copyright 1998 - 2003  _Demo_,
106 
+                             pagefault,
107 
+                             zsKnight
108 
+
109 
+  Super FX C emulator code
110 
+  (c) Copyright 1997 - 1999  Ivar,
111 
+                             Gary Henderson,
112 
+                             John Weidman
113 
+
114 
+  Sound emulator code used in 1.5-1.51
115 
+  (c) Copyright 1998 - 2003  Brad Martin
116 
+  (c) Copyright 1998 - 2006  Charles Bilyue'
117 
+
118 
+  Sound emulator code used in 1.52+
119 
+  (c) Copyright 2004 - 2007  Shay Green (gblargg@gmail.com)
120 
+
121 
+  SH assembler code partly based on x86 assembler code
122 
+  (c) Copyright 2002 - 2004  Marcus Comstedt (marcus@mc.pp.se)
123 
+
124 
+  2xSaI filter
125 
+  (c) Copyright 1999 - 2001  Derek Liauw Kie Fa
126 
+
127 
+  HQ2x, HQ3x, HQ4x filters
128 
+  (c) Copyright 2003         Maxim Stepin (maxim@hiend3d.com)
129 
+
130 
+  NTSC filter
131 
+  (c) Copyright 2006 - 2007  Shay Green
132 
+
133 
+  GTK+ GUI code
134 
+  (c) Copyright 2004 - 2011  BearOso
135 
+
136 
+  Win32 GUI code
137 
+  (c) Copyright 2003 - 2006  blip,
138 
+                             funkyass,
139 
+                             Matthew Kendora,
140 
+                             Nach,
141 
+                             nitsuja
142 
+  (c) Copyright 2009 - 2011  OV2
143 
+
144 
+  Mac OS GUI code
145 
+  (c) Copyright 1998 - 2001  John Stiles
146 
+  (c) Copyright 2001 - 2011  zones
147 
+
148 
+
149 
+  Specific ports contains the works of other authors. See headers in
150 
+  individual files.
151 
+
152 
+
153 
+  Snes9x homepage: http://www.snes9x.com/
154 
+
155 
+  Permission to use, copy, modify and/or distribute Snes9x in both binary
156 
+  and source form, for non-commercial purposes, is hereby granted without
157 
+  fee, providing that this license information and copyright notice appear
158 
+  with all copies and any derived work.
159 
+
160 
+  This software is provided 'as-is', without any express or implied
161 
+  warranty. In no event shall the authors be held liable for any damages
162 
+  arising from the use of this software or it's derivatives.
163 
+
164 
+  Snes9x is freeware for PERSONAL USE only. Commercial users should
165 
+  seek permission of the copyright holders first. Commercial use includes,
166 
+  but is not limited to, charging money for Snes9x or software derived from
167 
+  Snes9x, including Snes9x or derivatives in commercial game bundles, and/or
168 
+  using Snes9x as a promotion for your commercial product.
169 
+
170 
+  The copyright holders request that bug fixes and improvements to the code
171 
+  should be forwarded to them so everyone can benefit from the modifications
172 
+  in future versions.
173 
+
174 
+  Super NES and Super Nintendo Entertainment System are trademarks of
175 
+  Nintendo Co., Limited and its subsidiary companies.
176 
+ ***********************************************************************************/
177 
+
178 
+#include "snes9x.h"
179 
+#include "memmap.h"
180 
+#include "apu/apu.h"
181 
+
182 
+// for "Magic WDM" features
183 
+#ifdef DEBUGGER
184 
+#include "snapshot.h"
185 
+#include "display.h"
186 
+#include "debug.h"
187 
+#include "missing.h"
188 
+#endif
189 
+
190 
+#ifdef SA1_OPCODES
191 
+//#define AddCycles(n)	{ SA1.Cycles += (n); }
192 
+static inline void AddCycles(int32_t n) { SA1.Cycles += n; }
193 
+#else
194 
+//#define AddCycles(n)	{ CPU.PrevCycles = CPU.Cycles; CPU.Cycles += (n); S9xCheckInterrupts(); while (CPU.Cycles >= CPU.NextEvent) S9xDoHEventProcessing(); }
195 
+static inline void AddCycles(int32_t n) { CPU.PrevCycles = CPU.Cycles; CPU.Cycles += n; S9xCheckInterrupts(); while (CPU.Cycles >= CPU.NextEvent) S9xDoHEventProcessing(); }
196 
+#endif
197 
+
198 
+#include "cpuaddr.h"
199 
+#include "cpuops.h"
200 
+#include "cpumacro.h"
201 
+
202 
+/* ADC ********************************************************************* */
203 
+
204 
+static void Op69M1()
205 
+{
206 
+	ADC(Immediate8(READ));
207 
+}
208 
+
209 
+static void Op69M0()
210 
+{
211 
+	ADC(Immediate16(READ));
212 
+}
213 
+
214 
+static void Op69Slow()
215 
+{
216 
+	if (CheckMemory())
217 
+		ADC(Immediate8Slow(READ));
218 
+	else
219 
+		ADC(Immediate16Slow(READ));
220 
+}
221 
+
222 
+rOP8 (65M1,     Direct,                           WRAP_BANK, ADC)
223 
+rOP16(65M0,     Direct,                           WRAP_BANK, ADC)
224 
+rOPM (65Slow,   DirectSlow,                       WRAP_BANK, ADC)
225 
+
226 
+rOP8 (75E1,     DirectIndexedXE1,                 WRAP_BANK, ADC)
227 
+rOP8 (75E0M1,   DirectIndexedXE0,                 WRAP_BANK, ADC)
228 
+rOP16(75E0M0,   DirectIndexedXE0,                 WRAP_BANK, ADC)
229 
+rOPM (75Slow,   DirectIndexedXSlow,               WRAP_BANK, ADC)
230 
+
231 
+rOP8 (72E1,     DirectIndirectE1,                 WRAP_NONE, ADC)
232 
+rOP8 (72E0M1,   DirectIndirectE0,                 WRAP_NONE, ADC)
233 
+rOP16(72E0M0,   DirectIndirectE0,                 WRAP_NONE, ADC)
234 
+rOPM (72Slow,   DirectIndirectSlow,               WRAP_NONE, ADC)
235 
+
236 
+rOP8 (61E1,     DirectIndexedIndirectE1,          WRAP_NONE, ADC)
237 
+rOP8 (61E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, ADC)
238 
+rOP16(61E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, ADC)
239 
+rOPM (61Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, ADC)
240 
+
241 
+rOP8 (71E1,     DirectIndirectIndexedE1,          WRAP_NONE, ADC)
242 
+rOP8 (71E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, ADC)
243 
+rOP16(71E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, ADC)
244 
+rOP8 (71E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, ADC)
245 
+rOP16(71E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, ADC)
246 
+rOPM (71Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, ADC)
247 
+
248 
+rOP8 (67M1,     DirectIndirectLong,               WRAP_NONE, ADC)
249 
+rOP16(67M0,     DirectIndirectLong,               WRAP_NONE, ADC)
250 
+rOPM (67Slow,   DirectIndirectLongSlow,           WRAP_NONE, ADC)
251 
+
252 
+rOP8 (77M1,     DirectIndirectIndexedLong,        WRAP_NONE, ADC)
253 
+rOP16(77M0,     DirectIndirectIndexedLong,        WRAP_NONE, ADC)
254 
+rOPM (77Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, ADC)
255 
+
256 
+rOP8 (6DM1,     Absolute,                         WRAP_NONE, ADC)
257 
+rOP16(6DM0,     Absolute,                         WRAP_NONE, ADC)
258 
+rOPM (6DSlow,   AbsoluteSlow,                     WRAP_NONE, ADC)
259 
+
260 
+rOP8 (7DM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, ADC)
261 
+rOP16(7DM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, ADC)
262 
+rOP8 (7DM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, ADC)
263 
+rOP16(7DM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, ADC)
264 
+rOPM (7DSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, ADC)
265 
+
266 
+rOP8 (79M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, ADC)
267 
+rOP16(79M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, ADC)
268 
+rOP8 (79M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, ADC)
269 
+rOP16(79M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, ADC)
270 
+rOPM (79Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, ADC)
271 
+
272 
+rOP8 (6FM1,     AbsoluteLong,                     WRAP_NONE, ADC)
273 
+rOP16(6FM0,     AbsoluteLong,                     WRAP_NONE, ADC)
274 
+rOPM (6FSlow,   AbsoluteLongSlow,                 WRAP_NONE, ADC)
275 
+
276 
+rOP8 (7FM1,     AbsoluteLongIndexedX,             WRAP_NONE, ADC)
277 
+rOP16(7FM0,     AbsoluteLongIndexedX,             WRAP_NONE, ADC)
278 
+rOPM (7FSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, ADC)
279 
+
280 
+rOP8 (63M1,     StackRelative,                    WRAP_NONE, ADC)
281 
+rOP16(63M0,     StackRelative,                    WRAP_NONE, ADC)
282 
+rOPM (63Slow,   StackRelativeSlow,                WRAP_NONE, ADC)
283 
+
284 
+rOP8 (73M1,     StackRelativeIndirectIndexed,     WRAP_NONE, ADC)
285 
+rOP16(73M0,     StackRelativeIndirectIndexed,     WRAP_NONE, ADC)
286 
+rOPM (73Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, ADC)
287 
+
288 
+/* AND ********************************************************************* */
289 
+
290 
+static void Op29M1()
291 
+{
292 
+	Registers.AL &= Immediate8(READ);
293 
+	SetZN(Registers.AL);
294 
+}
295 
+
296 
+static void Op29M0()
297 
+{
298 
+	Registers.A.W &= Immediate16(READ);
299 
+	SetZN(Registers.A.W);
300 
+}
301 
+
302 
+static void Op29Slow()
303 
+{
304 
+	if (CheckMemory())
305 
+	{
306 
+		Registers.AL &= Immediate8Slow(READ);
307 
+		SetZN(Registers.AL);
308 
+	}
309 
+	else
310 
+	{
311 
+		Registers.A.W &= Immediate16Slow(READ);
312 
+		SetZN(Registers.A.W);
313 
+	}
314 
+}
315 
+
316 
+rOP8 (25M1,     Direct,                           WRAP_BANK, AND)
317 
+rOP16(25M0,     Direct,                           WRAP_BANK, AND)
318 
+rOPM (25Slow,   DirectSlow,                       WRAP_BANK, AND)
319 
+
320 
+rOP8 (35E1,     DirectIndexedXE1,                 WRAP_BANK, AND)
321 
+rOP8 (35E0M1,   DirectIndexedXE0,                 WRAP_BANK, AND)
322 
+rOP16(35E0M0,   DirectIndexedXE0,                 WRAP_BANK, AND)
323 
+rOPM (35Slow,   DirectIndexedXSlow,               WRAP_BANK, AND)
324 
+
325 
+rOP8 (32E1,     DirectIndirectE1,                 WRAP_NONE, AND)
326 
+rOP8 (32E0M1,   DirectIndirectE0,                 WRAP_NONE, AND)
327 
+rOP16(32E0M0,   DirectIndirectE0,                 WRAP_NONE, AND)
328 
+rOPM (32Slow,   DirectIndirectSlow,               WRAP_NONE, AND)
329 
+
330 
+rOP8 (21E1,     DirectIndexedIndirectE1,          WRAP_NONE, AND)
331 
+rOP8 (21E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, AND)
332 
+rOP16(21E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, AND)
333 
+rOPM (21Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, AND)
334 
+
335 
+rOP8 (31E1,     DirectIndirectIndexedE1,          WRAP_NONE, AND)
336 
+rOP8 (31E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, AND)
337 
+rOP16(31E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, AND)
338 
+rOP8 (31E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, AND)
339 
+rOP16(31E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, AND)
340 
+rOPM (31Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, AND)
341 
+
342 
+rOP8 (27M1,     DirectIndirectLong,               WRAP_NONE, AND)
343 
+rOP16(27M0,     DirectIndirectLong,               WRAP_NONE, AND)
344 
+rOPM (27Slow,   DirectIndirectLongSlow,           WRAP_NONE, AND)
345 
+
346 
+rOP8 (37M1,     DirectIndirectIndexedLong,        WRAP_NONE, AND)
347 
+rOP16(37M0,     DirectIndirectIndexedLong,        WRAP_NONE, AND)
348 
+rOPM (37Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, AND)
349 
+
350 
+rOP8 (2DM1,     Absolute,                         WRAP_NONE, AND)
351 
+rOP16(2DM0,     Absolute,                         WRAP_NONE, AND)
352 
+rOPM (2DSlow,   AbsoluteSlow,                     WRAP_NONE, AND)
353 
+
354 
+rOP8 (3DM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, AND)
355 
+rOP16(3DM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, AND)
356 
+rOP8 (3DM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, AND)
357 
+rOP16(3DM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, AND)
358 
+rOPM (3DSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, AND)
359 
+
360 
+rOP8 (39M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, AND)
361 
+rOP16(39M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, AND)
362 
+rOP8 (39M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, AND)
363 
+rOP16(39M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, AND)
364 
+rOPM (39Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, AND)
365 
+
366 
+rOP8 (2FM1,     AbsoluteLong,                     WRAP_NONE, AND)
367 
+rOP16(2FM0,     AbsoluteLong,                     WRAP_NONE, AND)
368 
+rOPM (2FSlow,   AbsoluteLongSlow,                 WRAP_NONE, AND)
369 
+
370 
+rOP8 (3FM1,     AbsoluteLongIndexedX,             WRAP_NONE, AND)
371 
+rOP16(3FM0,     AbsoluteLongIndexedX,             WRAP_NONE, AND)
372 
+rOPM (3FSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, AND)
373 
+
374 
+rOP8 (23M1,     StackRelative,                    WRAP_NONE, AND)
375 
+rOP16(23M0,     StackRelative,                    WRAP_NONE, AND)
376 
+rOPM (23Slow,   StackRelativeSlow,                WRAP_NONE, AND)
377 
+
378 
+rOP8 (33M1,     StackRelativeIndirectIndexed,     WRAP_NONE, AND)
379 
+rOP16(33M0,     StackRelativeIndirectIndexed,     WRAP_NONE, AND)
380 
+rOPM (33Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, AND)
381 
+
382 
+/* ASL ********************************************************************* */
383 
+
384 
+static void Op0AM1()
385 
+{
386 
+	AddCycles(ONE_CYCLE);
387 
+	ICPU._Carry = (Registers.AL & 0x80) != 0;
388 
+	Registers.AL <<= 1;
389 
+	SetZN(Registers.AL);
390 
+}
391 
+
392 
+static void Op0AM0()
393 
+{
394 
+	AddCycles(ONE_CYCLE);
395 
+	ICPU._Carry = (Registers.AH & 0x80) != 0;
396 
+	Registers.A.W <<= 1;
397 
+	SetZN(Registers.A.W);
398 
+}
399 
+
400 
+static void Op0ASlow()
401 
+{
402 
+	AddCycles(ONE_CYCLE);
403 
+
404 
+	if (CheckMemory())
405 
+	{
406 
+		ICPU._Carry = (Registers.AL & 0x80) != 0;
407 
+		Registers.AL <<= 1;
408 
+		SetZN(Registers.AL);
409 
+	}
410 
+	else
411 
+	{
412 
+		ICPU._Carry = (Registers.AH & 0x80) != 0;
413 
+		Registers.A.W <<= 1;
414 
+		SetZN(Registers.A.W);
415 
+	}
416 
+}
417 
+
418 
+mOP8 (06M1,     Direct,                           WRAP_BANK, ASL)
419 
+mOP16(06M0,     Direct,                           WRAP_BANK, ASL)
420 
+mOPM (06Slow,   DirectSlow,                       WRAP_BANK, ASL)
421 
+
422 
+mOP8 (16E1,     DirectIndexedXE1,                 WRAP_BANK, ASL)
423 
+mOP8 (16E0M1,   DirectIndexedXE0,                 WRAP_BANK, ASL)
424 
+mOP16(16E0M0,   DirectIndexedXE0,                 WRAP_BANK, ASL)
425 
+mOPM (16Slow,   DirectIndexedXSlow,               WRAP_BANK, ASL)
426 
+
427 
+mOP8 (0EM1,     Absolute,                         WRAP_NONE, ASL)
428 
+mOP16(0EM0,     Absolute,                         WRAP_NONE, ASL)
429 
+mOPM (0ESlow,   AbsoluteSlow,                     WRAP_NONE, ASL)
430 
+
431 
+mOP8 (1EM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, ASL)
432 
+mOP16(1EM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, ASL)
433 
+mOP8 (1EM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, ASL)
434 
+mOP16(1EM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, ASL)
435 
+mOPM (1ESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, ASL)
436 
+
437 
+/* BIT ********************************************************************* */
438 
+
439 
+static void Op89M1()
440 
+{
441 
+	ICPU._Zero = Registers.AL & Immediate8(READ);
442 
+}
443 
+
444 
+static void Op89M0()
445 
+{
446 
+	ICPU._Zero = (Registers.A.W & Immediate16(READ)) != 0;
447 
+}
448 
+
449 
+static void Op89Slow()
450 
+{
451 
+	if (CheckMemory())
452 
+		ICPU._Zero = Registers.AL & Immediate8Slow(READ);
453 
+	else
454 
+		ICPU._Zero = (Registers.A.W & Immediate16Slow(READ)) != 0;
455 
+}
456 
+
457 
+rOP8 (24M1,     Direct,                           WRAP_BANK, BIT)
458 
+rOP16(24M0,     Direct,                           WRAP_BANK, BIT)
459 
+rOPM (24Slow,   DirectSlow,                       WRAP_BANK, BIT)
460 
+
461 
+rOP8 (34E1,     DirectIndexedXE1,                 WRAP_BANK, BIT)
462 
+rOP8 (34E0M1,   DirectIndexedXE0,                 WRAP_BANK, BIT)
463 
+rOP16(34E0M0,   DirectIndexedXE0,                 WRAP_BANK, BIT)
464 
+rOPM (34Slow,   DirectIndexedXSlow,               WRAP_BANK, BIT)
465 
+
466 
+rOP8 (2CM1,     Absolute,                         WRAP_NONE, BIT)
467 
+rOP16(2CM0,     Absolute,                         WRAP_NONE, BIT)
468 
+rOPM (2CSlow,   AbsoluteSlow,                     WRAP_NONE, BIT)
469 
+
470 
+rOP8 (3CM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, BIT)
471 
+rOP16(3CM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, BIT)
472 
+rOP8 (3CM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, BIT)
473 
+rOP16(3CM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, BIT)
474 
+rOPM (3CSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, BIT)
475 
+
476 
+/* CMP ********************************************************************* */
477 
+
478 
+static void OpC9M1()
479 
+{
480 
+	int16_t	Int16 = (int16_t) Registers.AL - (int16_t) Immediate8(READ);
481 
+	ICPU._Carry = Int16 >= 0;
482 
+	SetZN((uint8_t) Int16);
483 
+}
484 
+
485 
+static void OpC9M0()
486 
+{
487 
+	int32_t	Int32 = (int32_t) Registers.A.W - (int32_t) Immediate16(READ);
488 
+	ICPU._Carry = Int32 >= 0;
489 
+	SetZN((uint16_t) Int32);
490 
+}
491 
+
492 
+static void OpC9Slow()
493 
+{
494 
+	if (CheckMemory())
495 
+	{
496 
+		int16_t	Int16 = (int16_t) Registers.AL - (int16_t) Immediate8Slow(READ);
497 
+		ICPU._Carry = Int16 >= 0;
498 
+		SetZN((uint8_t) Int16);
499 
+	}
500 
+	else
501 
+	{
502 
+		int32_t	Int32 = (int32_t) Registers.A.W - (int32_t) Immediate16Slow(READ);
503 
+		ICPU._Carry = Int32 >= 0;
504 
+		SetZN((uint16_t) Int32);
505 
+	}
506 
+}
507 
+
508 
+rOP8 (C5M1,     Direct,                           WRAP_BANK, CMP)
509 
+rOP16(C5M0,     Direct,                           WRAP_BANK, CMP)
510 
+rOPM (C5Slow,   DirectSlow,                       WRAP_BANK, CMP)
511 
+
512 
+rOP8 (D5E1,     DirectIndexedXE1,                 WRAP_BANK, CMP)
513 
+rOP8 (D5E0M1,   DirectIndexedXE0,                 WRAP_BANK, CMP)
514 
+rOP16(D5E0M0,   DirectIndexedXE0,                 WRAP_BANK, CMP)
515 
+rOPM (D5Slow,   DirectIndexedXSlow,               WRAP_BANK, CMP)
516 
+
517 
+rOP8 (D2E1,     DirectIndirectE1,                 WRAP_NONE, CMP)
518 
+rOP8 (D2E0M1,   DirectIndirectE0,                 WRAP_NONE, CMP)
519 
+rOP16(D2E0M0,   DirectIndirectE0,                 WRAP_NONE, CMP)
520 
+rOPM (D2Slow,   DirectIndirectSlow,               WRAP_NONE, CMP)
521 
+
522 
+rOP8 (C1E1,     DirectIndexedIndirectE1,          WRAP_NONE, CMP)
523 
+rOP8 (C1E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, CMP)
524 
+rOP16(C1E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, CMP)
525 
+rOPM (C1Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, CMP)
526 
+
527 
+rOP8 (D1E1,     DirectIndirectIndexedE1,          WRAP_NONE, CMP)
528 
+rOP8 (D1E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, CMP)
529 
+rOP16(D1E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, CMP)
530 
+rOP8 (D1E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, CMP)
531 
+rOP16(D1E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, CMP)
532 
+rOPM (D1Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, CMP)
533 
+
534 
+rOP8 (C7M1,     DirectIndirectLong,               WRAP_NONE, CMP)
535 
+rOP16(C7M0,     DirectIndirectLong,               WRAP_NONE, CMP)
536 
+rOPM (C7Slow,   DirectIndirectLongSlow,           WRAP_NONE, CMP)
537 
+
538 
+rOP8 (D7M1,     DirectIndirectIndexedLong,        WRAP_NONE, CMP)
539 
+rOP16(D7M0,     DirectIndirectIndexedLong,        WRAP_NONE, CMP)
540 
+rOPM (D7Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, CMP)
541 
+
542 
+rOP8 (CDM1,     Absolute,                         WRAP_NONE, CMP)
543 
+rOP16(CDM0,     Absolute,                         WRAP_NONE, CMP)
544 
+rOPM (CDSlow,   AbsoluteSlow,                     WRAP_NONE, CMP)
545 
+
546 
+rOP8 (DDM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, CMP)
547 
+rOP16(DDM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, CMP)
548 
+rOP8 (DDM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, CMP)
549 
+rOP16(DDM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, CMP)
550 
+rOPM (DDSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, CMP)
551 
+
552 
+rOP8 (D9M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, CMP)
553 
+rOP16(D9M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, CMP)
554 
+rOP8 (D9M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, CMP)
555 
+rOP16(D9M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, CMP)
556 
+rOPM (D9Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, CMP)
557 
+
558 
+rOP8 (CFM1,     AbsoluteLong,                     WRAP_NONE, CMP)
559 
+rOP16(CFM0,     AbsoluteLong,                     WRAP_NONE, CMP)
560 
+rOPM (CFSlow,   AbsoluteLongSlow,                 WRAP_NONE, CMP)
561 
+
562 
+rOP8 (DFM1,     AbsoluteLongIndexedX,             WRAP_NONE, CMP)
563 
+rOP16(DFM0,     AbsoluteLongIndexedX,             WRAP_NONE, CMP)
564 
+rOPM (DFSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, CMP)
565 
+
566 
+rOP8 (C3M1,     StackRelative,                    WRAP_NONE, CMP)
567 
+rOP16(C3M0,     StackRelative,                    WRAP_NONE, CMP)
568 
+rOPM (C3Slow,   StackRelativeSlow,                WRAP_NONE, CMP)
569 
+
570 
+rOP8 (D3M1,     StackRelativeIndirectIndexed,     WRAP_NONE, CMP)
571 
+rOP16(D3M0,     StackRelativeIndirectIndexed,     WRAP_NONE, CMP)
572 
+rOPM (D3Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, CMP)
573 
+
574 
+/* CPX ********************************************************************* */
575 
+
576 
+static void OpE0X1()
577 
+{
578 
+	int16_t	Int16 = (int16_t) Registers.XL - (int16_t) Immediate8(READ);
579 
+	ICPU._Carry = Int16 >= 0;
580 
+	SetZN((uint8_t) Int16);
581 
+}
582 
+
583 
+static void OpE0X0()
584 
+{
585 
+	int32_t	Int32 = (int32_t) Registers.X.W - (int32_t) Immediate16(READ);
586 
+	ICPU._Carry = Int32 >= 0;
587 
+	SetZN((uint16_t) Int32);
588 
+}
589 
+
590 
+static void OpE0Slow()
591 
+{
592 
+	if (CheckIndex())
593 
+	{
594 
+		int16_t	Int16 = (int16_t) Registers.XL - (int16_t) Immediate8Slow(READ);
595 
+		ICPU._Carry = Int16 >= 0;
596 
+		SetZN((uint8_t) Int16);
597 
+	}
598 
+	else
599 
+	{
600 
+		int32_t	Int32 = (int32_t) Registers.X.W - (int32_t) Immediate16Slow(READ);
601 
+		ICPU._Carry = Int32 >= 0;
602 
+		SetZN((uint16_t) Int32);
603 
+	}
604 
+}
605 
+
606 
+rOP8 (E4X1,     Direct,                           WRAP_BANK, CPX)
607 
+rOP16(E4X0,     Direct,                           WRAP_BANK, CPX)
608 
+rOPX (E4Slow,   DirectSlow,                       WRAP_BANK, CPX)
609 
+
610 
+rOP8 (ECX1,     Absolute,                         WRAP_NONE, CPX)
611 
+rOP16(ECX0,     Absolute,                         WRAP_NONE, CPX)
612 
+rOPX (ECSlow,   AbsoluteSlow,                     WRAP_NONE, CPX)
613 
+
614 
+/* CPY ********************************************************************* */
615 
+
616 
+static void OpC0X1()
617 
+{
618 
+	int16_t	Int16 = (int16_t) Registers.YL - (int16_t) Immediate8(READ);
619 
+	ICPU._Carry = Int16 >= 0;
620 
+	SetZN((uint8_t) Int16);
621 
+}
622 
+
623 
+static void OpC0X0()
624 
+{
625 
+	int32_t	Int32 = (int32_t) Registers.Y.W - (int32_t) Immediate16(READ);
626 
+	ICPU._Carry = Int32 >= 0;
627 
+	SetZN((uint16_t) Int32);
628 
+}
629 
+
630 
+static void OpC0Slow()
631 
+{
632 
+	if (CheckIndex())
633 
+	{
634 
+		int16_t	Int16 = (int16_t) Registers.YL - (int16_t) Immediate8Slow(READ);
635 
+		ICPU._Carry = Int16 >= 0;
636 
+		SetZN((uint8_t) Int16);
637 
+	}
638 
+	else
639 
+	{
640 
+		int32_t	Int32 = (int32_t) Registers.Y.W - (int32_t) Immediate16Slow(READ);
641 
+		ICPU._Carry = Int32 >= 0;
642 
+		SetZN((uint16_t) Int32);
643 
+	}
644 
+}
645 
+
646 
+rOP8 (C4X1,     Direct,                           WRAP_BANK, CPY)
647 
+rOP16(C4X0,     Direct,                           WRAP_BANK, CPY)
648 
+rOPX (C4Slow,   DirectSlow,                       WRAP_BANK, CPY)
649 
+
650 
+rOP8 (CCX1,     Absolute,                         WRAP_NONE, CPY)
651 
+rOP16(CCX0,     Absolute,                         WRAP_NONE, CPY)
652 
+rOPX (CCSlow,   AbsoluteSlow,                     WRAP_NONE, CPY)
653 
+
654 
+/* DEC ********************************************************************* */
655 
+
656 
+static void Op3AM1()
657 
+{
658 
+	AddCycles(ONE_CYCLE);
659 
+	Registers.AL--;
660 
+	SetZN(Registers.AL);
661 
+}
662 
+
663 
+static void Op3AM0()
664 
+{
665 
+	AddCycles(ONE_CYCLE);
666 
+	Registers.A.W--;
667 
+	SetZN(Registers.A.W);
668 
+}
669 
+
670 
+static void Op3ASlow()
671 
+{
672 
+	AddCycles(ONE_CYCLE);
673 
+
674 
+	if (CheckMemory())
675 
+	{
676 
+		Registers.AL--;
677 
+		SetZN(Registers.AL);
678 
+	}
679 
+	else
680 
+	{
681 
+		Registers.A.W--;
682 
+		SetZN(Registers.A.W);
683 
+	}
684 
+}
685 
+
686 
+mOP8 (C6M1,     Direct,                           WRAP_BANK, DEC)
687 
+mOP16(C6M0,     Direct,                           WRAP_BANK, DEC)
688 
+mOPM (C6Slow,   DirectSlow,                       WRAP_BANK, DEC)
689 
+
690 
+mOP8 (D6E1,     DirectIndexedXE1,                 WRAP_BANK, DEC)
691 
+mOP8 (D6E0M1,   DirectIndexedXE0,                 WRAP_BANK, DEC)
692 
+mOP16(D6E0M0,   DirectIndexedXE0,                 WRAP_BANK, DEC)
693 
+mOPM (D6Slow,   DirectIndexedXSlow,               WRAP_BANK, DEC)
694 
+
695 
+mOP8 (CEM1,     Absolute,                         WRAP_NONE, DEC)
696 
+mOP16(CEM0,     Absolute,                         WRAP_NONE, DEC)
697 
+mOPM (CESlow,   AbsoluteSlow,                     WRAP_NONE, DEC)
698 
+
699 
+mOP8 (DEM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, DEC)
700 
+mOP16(DEM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, DEC)
701 
+mOP8 (DEM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, DEC)
702 
+mOP16(DEM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, DEC)
703 
+mOPM (DESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, DEC)
704 
+
705 
+/* EOR ********************************************************************* */
706 
+
707 
+static void Op49M1()
708 
+{
709 
+	Registers.AL ^= Immediate8(READ);
710 
+	SetZN(Registers.AL);
711 
+}
712 
+
713 
+static void Op49M0()
714 
+{
715 
+	Registers.A.W ^= Immediate16(READ);
716 
+	SetZN(Registers.A.W);
717 
+}
718 
+
719 
+static void Op49Slow()
720 
+{
721 
+	if (CheckMemory())
722 
+	{
723 
+		Registers.AL ^= Immediate8Slow(READ);
724 
+		SetZN(Registers.AL);
725 
+	}
726 
+	else
727 
+	{
728 
+		Registers.A.W ^= Immediate16Slow(READ);
729 
+		SetZN(Registers.A.W);
730 
+	}
731 
+}
732 
+
733 
+rOP8 (45M1,     Direct,                           WRAP_BANK, EOR)
734 
+rOP16(45M0,     Direct,                           WRAP_BANK, EOR)
735 
+rOPM (45Slow,   DirectSlow,                       WRAP_BANK, EOR)
736 
+
737 
+rOP8 (55E1,     DirectIndexedXE1,                 WRAP_BANK, EOR)
738 
+rOP8 (55E0M1,   DirectIndexedXE0,                 WRAP_BANK, EOR)
739 
+rOP16(55E0M0,   DirectIndexedXE0,                 WRAP_BANK, EOR)
740 
+rOPM (55Slow,   DirectIndexedXSlow,               WRAP_BANK, EOR)
741 
+
742 
+rOP8 (52E1,     DirectIndirectE1,                 WRAP_NONE, EOR)
743 
+rOP8 (52E0M1,   DirectIndirectE0,                 WRAP_NONE, EOR)
744 
+rOP16(52E0M0,   DirectIndirectE0,                 WRAP_NONE, EOR)
745 
+rOPM (52Slow,   DirectIndirectSlow,               WRAP_NONE, EOR)
746 
+
747 
+rOP8 (41E1,     DirectIndexedIndirectE1,          WRAP_NONE, EOR)
748 
+rOP8 (41E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, EOR)
749 
+rOP16(41E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, EOR)
750 
+rOPM (41Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, EOR)
751 
+
752 
+rOP8 (51E1,     DirectIndirectIndexedE1,          WRAP_NONE, EOR)
753 
+rOP8 (51E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, EOR)
754 
+rOP16(51E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, EOR)
755 
+rOP8 (51E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, EOR)
756 
+rOP16(51E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, EOR)
757 
+rOPM (51Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, EOR)
758 
+
759 
+rOP8 (47M1,     DirectIndirectLong,               WRAP_NONE, EOR)
760 
+rOP16(47M0,     DirectIndirectLong,               WRAP_NONE, EOR)
761 
+rOPM (47Slow,   DirectIndirectLongSlow,           WRAP_NONE, EOR)
762 
+
763 
+rOP8 (57M1,     DirectIndirectIndexedLong,        WRAP_NONE, EOR)
764 
+rOP16(57M0,     DirectIndirectIndexedLong,        WRAP_NONE, EOR)
765 
+rOPM (57Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, EOR)
766 
+
767 
+rOP8 (4DM1,     Absolute,                         WRAP_NONE, EOR)
768 
+rOP16(4DM0,     Absolute,                         WRAP_NONE, EOR)
769 
+rOPM (4DSlow,   AbsoluteSlow,                     WRAP_NONE, EOR)
770 
+
771 
+rOP8 (5DM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, EOR)
772 
+rOP16(5DM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, EOR)
773 
+rOP8 (5DM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, EOR)
774 
+rOP16(5DM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, EOR)
775 
+rOPM (5DSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, EOR)
776 
+
777 
+rOP8 (59M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, EOR)
778 
+rOP16(59M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, EOR)
779 
+rOP8 (59M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, EOR)
780 
+rOP16(59M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, EOR)
781 
+rOPM (59Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, EOR)
782 
+
783 
+rOP8 (4FM1,     AbsoluteLong,                     WRAP_NONE, EOR)
784 
+rOP16(4FM0,     AbsoluteLong,                     WRAP_NONE, EOR)
785 
+rOPM (4FSlow,   AbsoluteLongSlow,                 WRAP_NONE, EOR)
786 
+
787 
+rOP8 (5FM1,     AbsoluteLongIndexedX,             WRAP_NONE, EOR)
788 
+rOP16(5FM0,     AbsoluteLongIndexedX,             WRAP_NONE, EOR)
789 
+rOPM (5FSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, EOR)
790 
+
791 
+rOP8 (43M1,     StackRelative,                    WRAP_NONE, EOR)
792 
+rOP16(43M0,     StackRelative,                    WRAP_NONE, EOR)
793 
+rOPM (43Slow,   StackRelativeSlow,                WRAP_NONE, EOR)
794 
+
795 
+rOP8 (53M1,     StackRelativeIndirectIndexed,     WRAP_NONE, EOR)
796 
+rOP16(53M0,     StackRelativeIndirectIndexed,     WRAP_NONE, EOR)
797 
+rOPM (53Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, EOR)
798 
+
799 
+/* INC ********************************************************************* */
800 
+
801 
+static void Op1AM1()
802 
+{
803 
+	AddCycles(ONE_CYCLE);
804 
+	Registers.AL++;
805 
+	SetZN(Registers.AL);
806 
+}
807 
+
808 
+static void Op1AM0()
809 
+{
810 
+	AddCycles(ONE_CYCLE);
811 
+	Registers.A.W++;
812 
+	SetZN(Registers.A.W);
813 
+}
814 
+
815 
+static void Op1ASlow()
816 
+{
817 
+	AddCycles(ONE_CYCLE);
818 
+
819 
+	if (CheckMemory())
820 
+	{
821 
+		Registers.AL++;
822 
+		SetZN(Registers.AL);
823 
+	}
824 
+	else
825 
+	{
826 
+		Registers.A.W++;
827 
+		SetZN(Registers.A.W);
828 
+	}
829 
+}
830 
+
831 
+mOP8 (E6M1,     Direct,                           WRAP_BANK, INC)
832 
+mOP16(E6M0,     Direct,                           WRAP_BANK, INC)
833 
+mOPM (E6Slow,   DirectSlow,                       WRAP_BANK, INC)
834 
+
835 
+mOP8 (F6E1,     DirectIndexedXE1,                 WRAP_BANK, INC)
836 
+mOP8 (F6E0M1,   DirectIndexedXE0,                 WRAP_BANK, INC)
837 
+mOP16(F6E0M0,   DirectIndexedXE0,                 WRAP_BANK, INC)
838 
+mOPM (F6Slow,   DirectIndexedXSlow,               WRAP_BANK, INC)
839 
+
840 
+mOP8 (EEM1,     Absolute,                         WRAP_NONE, INC)
841 
+mOP16(EEM0,     Absolute,                         WRAP_NONE, INC)
842 
+mOPM (EESlow,   AbsoluteSlow,                     WRAP_NONE, INC)
843 
+
844 
+mOP8 (FEM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, INC)
845 
+mOP16(FEM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, INC)
846 
+mOP8 (FEM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, INC)
847 
+mOP16(FEM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, INC)
848 
+mOPM (FESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, INC)
849 
+
850 
+/* LDA ********************************************************************* */
851 
+
852 
+static void OpA9M1()
853 
+{
854 
+	Registers.AL = Immediate8(READ);
855 
+	SetZN(Registers.AL);
856 
+}
857 
+
858 
+static void OpA9M0()
859 
+{
860 
+	Registers.A.W = Immediate16(READ);
861 
+	SetZN(Registers.A.W);
862 
+}
863 
+
864 
+static void OpA9Slow()
865 
+{
866 
+	if (CheckMemory())
867 
+	{
868 
+		Registers.AL = Immediate8Slow(READ);
869 
+		SetZN(Registers.AL);
870 
+	}
871 
+	else
872 
+	{
873 
+		Registers.A.W = Immediate16Slow(READ);
874 
+		SetZN(Registers.A.W);
875 
+	}
876 
+}
877 
+
878 
+rOP8 (A5M1,     Direct,                           WRAP_BANK, LDA)
879 
+rOP16(A5M0,     Direct,                           WRAP_BANK, LDA)
880 
+rOPM (A5Slow,   DirectSlow,                       WRAP_BANK, LDA)
881 
+
882 
+rOP8 (B5E1,     DirectIndexedXE1,                 WRAP_BANK, LDA)
883 
+rOP8 (B5E0M1,   DirectIndexedXE0,                 WRAP_BANK, LDA)
884 
+rOP16(B5E0M0,   DirectIndexedXE0,                 WRAP_BANK, LDA)
885 
+rOPM (B5Slow,   DirectIndexedXSlow,               WRAP_BANK, LDA)
886 
+
887 
+rOP8 (B2E1,     DirectIndirectE1,                 WRAP_NONE, LDA)
888 
+rOP8 (B2E0M1,   DirectIndirectE0,                 WRAP_NONE, LDA)
889 
+rOP16(B2E0M0,   DirectIndirectE0,                 WRAP_NONE, LDA)
890 
+rOPM (B2Slow,   DirectIndirectSlow,               WRAP_NONE, LDA)
891 
+
892 
+rOP8 (A1E1,     DirectIndexedIndirectE1,          WRAP_NONE, LDA)
893 
+rOP8 (A1E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, LDA)
894 
+rOP16(A1E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, LDA)
895 
+rOPM (A1Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, LDA)
896 
+
897 
+rOP8 (B1E1,     DirectIndirectIndexedE1,          WRAP_NONE, LDA)
898 
+rOP8 (B1E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, LDA)
899 
+rOP16(B1E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, LDA)
900 
+rOP8 (B1E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, LDA)
901 
+rOP16(B1E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, LDA)
902 
+rOPM (B1Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, LDA)
903 
+
904 
+rOP8 (A7M1,     DirectIndirectLong,               WRAP_NONE, LDA)
905 
+rOP16(A7M0,     DirectIndirectLong,               WRAP_NONE, LDA)
906 
+rOPM (A7Slow,   DirectIndirectLongSlow,           WRAP_NONE, LDA)
907 
+
908 
+rOP8 (B7M1,     DirectIndirectIndexedLong,        WRAP_NONE, LDA)
909 
+rOP16(B7M0,     DirectIndirectIndexedLong,        WRAP_NONE, LDA)
910 
+rOPM (B7Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, LDA)
911 
+
912 
+rOP8 (ADM1,     Absolute,                         WRAP_NONE, LDA)
913 
+rOP16(ADM0,     Absolute,                         WRAP_NONE, LDA)
914 
+rOPM (ADSlow,   AbsoluteSlow,                     WRAP_NONE, LDA)
915 
+
916 
+rOP8 (BDM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, LDA)
917 
+rOP16(BDM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, LDA)
918 
+rOP8 (BDM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, LDA)
919 
+rOP16(BDM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, LDA)
920 
+rOPM (BDSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, LDA)
921 
+
922 
+rOP8 (B9M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, LDA)
923 
+rOP16(B9M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, LDA)
924 
+rOP8 (B9M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, LDA)
925 
+rOP16(B9M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, LDA)
926 
+rOPM (B9Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, LDA)
927 
+
928 
+rOP8 (AFM1,     AbsoluteLong,                     WRAP_NONE, LDA)
929 
+rOP16(AFM0,     AbsoluteLong,                     WRAP_NONE, LDA)
930 
+rOPM (AFSlow,   AbsoluteLongSlow,                 WRAP_NONE, LDA)
931 
+
932 
+rOP8 (BFM1,     AbsoluteLongIndexedX,             WRAP_NONE, LDA)
933 
+rOP16(BFM0,     AbsoluteLongIndexedX,             WRAP_NONE, LDA)
934 
+rOPM (BFSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, LDA)
935 
+
936 
+rOP8 (A3M1,     StackRelative,                    WRAP_NONE, LDA)
937 
+rOP16(A3M0,     StackRelative,                    WRAP_NONE, LDA)
938 
+rOPM (A3Slow,   StackRelativeSlow,                WRAP_NONE, LDA)
939 
+
940 
+rOP8 (B3M1,     StackRelativeIndirectIndexed,     WRAP_NONE, LDA)
941 
+rOP16(B3M0,     StackRelativeIndirectIndexed,     WRAP_NONE, LDA)
942 
+rOPM (B3Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, LDA)
943 
+
944 
+/* LDX ********************************************************************* */
945 
+
946 
+static void OpA2X1()
947 
+{
948 
+	Registers.XL = Immediate8(READ);
949 
+	SetZN(Registers.XL);
950 
+}
951 
+
952 
+static void OpA2X0()
953 
+{
954 
+	Registers.X.W = Immediate16(READ);
955 
+	SetZN(Registers.X.W);
956 
+}
957 
+
958 
+static void OpA2Slow()
959 
+{
960 
+	if (CheckIndex())
961 
+	{
962 
+		Registers.XL = Immediate8Slow(READ);
963 
+		SetZN(Registers.XL);
964 
+	}
965 
+	else
966 
+	{
967 
+		Registers.X.W = Immediate16Slow(READ);
968 
+		SetZN(Registers.X.W);
969 
+	}
970 
+}
971 
+
972 
+rOP8 (A6X1,     Direct,                           WRAP_BANK, LDX)
973 
+rOP16(A6X0,     Direct,                           WRAP_BANK, LDX)
974 
+rOPX (A6Slow,   DirectSlow,                       WRAP_BANK, LDX)
975 
+
976 
+rOP8 (B6E1,     DirectIndexedYE1,                 WRAP_BANK, LDX)
977 
+rOP8 (B6E0X1,   DirectIndexedYE0,                 WRAP_BANK, LDX)
978 
+rOP16(B6E0X0,   DirectIndexedYE0,                 WRAP_BANK, LDX)
979 
+rOPX (B6Slow,   DirectIndexedYSlow,               WRAP_BANK, LDX)
980 
+
981 
+rOP8 (AEX1,     Absolute,                         WRAP_BANK, LDX)
982 
+rOP16(AEX0,     Absolute,                         WRAP_BANK, LDX)
983 
+rOPX (AESlow,   AbsoluteSlow,                     WRAP_BANK, LDX)
984 
+
985 
+rOP8 (BEX1,     AbsoluteIndexedYX1,               WRAP_BANK, LDX)
986 
+rOP16(BEX0,     AbsoluteIndexedYX0,               WRAP_BANK, LDX)
987 
+rOPX (BESlow,   AbsoluteIndexedYSlow,             WRAP_BANK, LDX)
988 
+
989 
+/* LDY ********************************************************************* */
990 
+
991 
+static void OpA0X1()
992 
+{
993 
+	Registers.YL = Immediate8(READ);
994 
+	SetZN(Registers.YL);
995 
+}
996 
+
997 
+static void OpA0X0()
998 
+{
999 
+	Registers.Y.W = Immediate16(READ);
1000 
+	SetZN(Registers.Y.W);
1001 
+}
1002 
+
1003 
+static void OpA0Slow()
1004 
+{
1005 
+	if (CheckIndex())
1006 
+	{
1007 
+		Registers.YL = Immediate8Slow(READ);
1008 
+		SetZN(Registers.YL);
1009 
+	}
1010 
+	else
1011 
+	{
1012 
+		Registers.Y.W = Immediate16Slow(READ);
1013 
+		SetZN(Registers.Y.W);
1014 
+	}
1015 
+}
1016 
+
1017 
+rOP8 (A4X1,     Direct,                           WRAP_BANK, LDY)
1018 
+rOP16(A4X0,     Direct,                           WRAP_BANK, LDY)
1019 
+rOPX (A4Slow,   DirectSlow,                       WRAP_BANK, LDY)
1020 
+
1021 
+rOP8 (B4E1,     DirectIndexedXE1,                 WRAP_BANK, LDY)
1022 
+rOP8 (B4E0X1,   DirectIndexedXE0,                 WRAP_BANK, LDY)
1023 
+rOP16(B4E0X0,   DirectIndexedXE0,                 WRAP_BANK, LDY)
1024 
+rOPX (B4Slow,   DirectIndexedXSlow,               WRAP_BANK, LDY)
1025 
+
1026 
+rOP8 (ACX1,     Absolute,                         WRAP_BANK, LDY)
1027 
+rOP16(ACX0,     Absolute,                         WRAP_BANK, LDY)
1028 
+rOPX (ACSlow,   AbsoluteSlow,                     WRAP_BANK, LDY)
1029 
+
1030 
+rOP8 (BCX1,     AbsoluteIndexedXX1,               WRAP_BANK, LDY)
1031 
+rOP16(BCX0,     AbsoluteIndexedXX0,               WRAP_BANK, LDY)
1032 
+rOPX (BCSlow,   AbsoluteIndexedXSlow,             WRAP_BANK, LDY)
1033 
+
1034 
+/* LSR ********************************************************************* */
1035 
+
1036 
+static void Op4AM1()
1037 
+{
1038 
+	AddCycles(ONE_CYCLE);
1039 
+	ICPU._Carry = Registers.AL & 1;
1040 
+	Registers.AL >>= 1;
1041 
+	SetZN(Registers.AL);
1042 
+}
1043 
+
1044 
+static void Op4AM0()
1045 
+{
1046 
+	AddCycles(ONE_CYCLE);
1047 
+	ICPU._Carry = Registers.A.W & 1;
1048 
+	Registers.A.W >>= 1;
1049 
+	SetZN(Registers.A.W);
1050 
+}
1051 
+
1052 
+static void Op4ASlow()
1053 
+{
1054 
+	AddCycles(ONE_CYCLE);
1055 
+
1056 
+	if (CheckMemory())
1057 
+	{
1058 
+		ICPU._Carry = Registers.AL & 1;
1059 
+		Registers.AL >>= 1;
1060 
+		SetZN(Registers.AL);
1061 
+	}
1062 
+	else
1063 
+	{
1064 
+		ICPU._Carry = Registers.A.W & 1;
1065 
+		Registers.A.W >>= 1;
1066 
+		SetZN(Registers.A.W);
1067 
+	}
1068 
+}
1069 
+
1070 
+mOP8 (46M1,     Direct,                           WRAP_BANK, LSR)
1071 
+mOP16(46M0,     Direct,                           WRAP_BANK, LSR)
1072 
+mOPM (46Slow,   DirectSlow,                       WRAP_BANK, LSR)
1073 
+
1074 
+mOP8 (56E1,     DirectIndexedXE1,                 WRAP_BANK, LSR)
1075 
+mOP8 (56E0M1,   DirectIndexedXE0,                 WRAP_BANK, LSR)
1076 
+mOP16(56E0M0,   DirectIndexedXE0,                 WRAP_BANK, LSR)
1077 
+mOPM (56Slow,   DirectIndexedXSlow,               WRAP_BANK, LSR)
1078 
+
1079 
+mOP8 (4EM1,     Absolute,                         WRAP_NONE, LSR)
1080 
+mOP16(4EM0,     Absolute,                         WRAP_NONE, LSR)
1081 
+mOPM (4ESlow,   AbsoluteSlow,                     WRAP_NONE, LSR)
1082 
+
1083 
+mOP8 (5EM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, LSR)
1084 
+mOP16(5EM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, LSR)
1085 
+mOP8 (5EM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, LSR)
1086 
+mOP16(5EM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, LSR)
1087 
+mOPM (5ESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, LSR)
1088 
+
1089 
+/* ORA ********************************************************************* */
1090 
+
1091 
+static void Op09M1()
1092 
+{
1093 
+	Registers.AL |= Immediate8(READ);
1094 
+	SetZN(Registers.AL);
1095 
+}
1096 
+
1097 
+static void Op09M0()
1098 
+{
1099 
+	Registers.A.W |= Immediate16(READ);
1100 
+	SetZN(Registers.A.W);
1101 
+}
1102 
+
1103 
+static void Op09Slow()
1104 
+{
1105 
+	if (CheckMemory())
1106 
+	{
1107 
+		Registers.AL |= Immediate8Slow(READ);
1108 
+		SetZN(Registers.AL);
1109 
+	}
1110 
+	else
1111 
+	{
1112 
+		Registers.A.W |= Immediate16Slow(READ);
1113 
+		SetZN(Registers.A.W);
1114 
+	}
1115 
+}
1116 
+
1117 
+rOP8 (05M1,     Direct,                           WRAP_BANK, ORA)
1118 
+rOP16(05M0,     Direct,                           WRAP_BANK, ORA)
1119 
+rOPM (05Slow,   DirectSlow,                       WRAP_BANK, ORA)
1120 
+
1121 
+rOP8 (15E1,     DirectIndexedXE1,                 WRAP_BANK, ORA)
1122 
+rOP8 (15E0M1,   DirectIndexedXE0,                 WRAP_BANK, ORA)
1123 
+rOP16(15E0M0,   DirectIndexedXE0,                 WRAP_BANK, ORA)
1124 
+rOPM (15Slow,   DirectIndexedXSlow,               WRAP_BANK, ORA)
1125 
+
1126 
+rOP8 (12E1,     DirectIndirectE1,                 WRAP_NONE, ORA)
1127 
+rOP8 (12E0M1,   DirectIndirectE0,                 WRAP_NONE, ORA)
1128 
+rOP16(12E0M0,   DirectIndirectE0,                 WRAP_NONE, ORA)
1129 
+rOPM (12Slow,   DirectIndirectSlow,               WRAP_NONE, ORA)
1130 
+
1131 
+rOP8 (01E1,     DirectIndexedIndirectE1,          WRAP_NONE, ORA)
1132 
+rOP8 (01E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, ORA)
1133 
+rOP16(01E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, ORA)
1134 
+rOPM (01Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, ORA)
1135 
+
1136 
+rOP8 (11E1,     DirectIndirectIndexedE1,          WRAP_NONE, ORA)
1137 
+rOP8 (11E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, ORA)
1138 
+rOP16(11E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, ORA)
1139 
+rOP8 (11E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, ORA)
1140 
+rOP16(11E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, ORA)
1141 
+rOPM (11Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, ORA)
1142 
+
1143 
+rOP8 (07M1,     DirectIndirectLong,               WRAP_NONE, ORA)
1144 
+rOP16(07M0,     DirectIndirectLong,               WRAP_NONE, ORA)
1145 
+rOPM (07Slow,   DirectIndirectLongSlow,           WRAP_NONE, ORA)
1146 
+
1147 
+rOP8 (17M1,     DirectIndirectIndexedLong,        WRAP_NONE, ORA)
1148 
+rOP16(17M0,     DirectIndirectIndexedLong,        WRAP_NONE, ORA)
1149 
+rOPM (17Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, ORA)
1150 
+
1151 
+rOP8 (0DM1,     Absolute,                         WRAP_NONE, ORA)
1152 
+rOP16(0DM0,     Absolute,                         WRAP_NONE, ORA)
1153 
+rOPM (0DSlow,   AbsoluteSlow,                     WRAP_NONE, ORA)
1154 
+
1155 
+rOP8 (1DM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, ORA)
1156 
+rOP16(1DM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, ORA)
1157 
+rOP8 (1DM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, ORA)
1158 
+rOP16(1DM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, ORA)
1159 
+rOPM (1DSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, ORA)
1160 
+
1161 
+rOP8 (19M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, ORA)
1162 
+rOP16(19M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, ORA)
1163 
+rOP8 (19M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, ORA)
1164 
+rOP16(19M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, ORA)
1165 
+rOPM (19Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, ORA)
1166 
+
1167 
+rOP8 (0FM1,     AbsoluteLong,                     WRAP_NONE, ORA)
1168 
+rOP16(0FM0,     AbsoluteLong,                     WRAP_NONE, ORA)
1169 
+rOPM (0FSlow,   AbsoluteLongSlow,                 WRAP_NONE, ORA)
1170 
+
1171 
+rOP8 (1FM1,     AbsoluteLongIndexedX,             WRAP_NONE, ORA)
1172 
+rOP16(1FM0,     AbsoluteLongIndexedX,             WRAP_NONE, ORA)
1173 
+rOPM (1FSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, ORA)
1174 
+
1175 
+rOP8 (03M1,     StackRelative,                    WRAP_NONE, ORA)
1176 
+rOP16(03M0,     StackRelative,                    WRAP_NONE, ORA)
1177 
+rOPM (03Slow,   StackRelativeSlow,                WRAP_NONE, ORA)
1178 
+
1179 
+rOP8 (13M1,     StackRelativeIndirectIndexed,     WRAP_NONE, ORA)
1180 
+rOP16(13M0,     StackRelativeIndirectIndexed,     WRAP_NONE, ORA)
1181 
+rOPM (13Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, ORA)
1182 
+
1183 
+/* ROL ********************************************************************* */
1184 
+
1185 
+static void Op2AM1()
1186 
+{
1187 
+	AddCycles(ONE_CYCLE);
1188 
+	uint16_t	w = (((uint16_t) Registers.AL) << 1) | CheckCarry();
1189 
+	ICPU._Carry = w >= 0x100;
1190 
+	Registers.AL = (uint8_t) w;
1191 
+	SetZN(Registers.AL);
1192 
+}
1193 
+
1194 
+static void Op2AM0()
1195 
+{
1196 
+	AddCycles(ONE_CYCLE);
1197 
+	uint32_t	w = (((uint32_t) Registers.A.W) << 1) | CheckCarry();
1198 
+	ICPU._Carry = w >= 0x10000;
1199 
+	Registers.A.W = (uint16_t) w;
1200 
+	SetZN(Registers.A.W);
1201 
+}
1202 
+
1203 
+static void Op2ASlow()
1204 
+{
1205 
+	AddCycles(ONE_CYCLE);
1206 
+
1207 
+	if (CheckMemory())
1208 
+	{
1209 
+		uint16_t	w = (((uint16_t) Registers.AL) << 1) | CheckCarry();
1210 
+		ICPU._Carry = w >= 0x100;
1211 
+		Registers.AL = (uint8_t) w;
1212 
+		SetZN(Registers.AL);
1213 
+	}
1214 
+	else
1215 
+	{
1216 
+		uint32_t	w = (((uint32_t) Registers.A.W) << 1) | CheckCarry();
1217 
+		ICPU._Carry = w >= 0x10000;
1218 
+		Registers.A.W = (uint16_t) w;
1219 
+		SetZN(Registers.A.W);
1220 
+	}
1221 
+}
1222 
+
1223 
+mOP8 (26M1,     Direct,                           WRAP_BANK, ROL)
1224 
+mOP16(26M0,     Direct,                           WRAP_BANK, ROL)
1225 
+mOPM (26Slow,   DirectSlow,                       WRAP_BANK, ROL)
1226 
+
1227 
+mOP8 (36E1,     DirectIndexedXE1,                 WRAP_BANK, ROL)
1228 
+mOP8 (36E0M1,   DirectIndexedXE0,                 WRAP_BANK, ROL)
1229 
+mOP16(36E0M0,   DirectIndexedXE0,                 WRAP_BANK, ROL)
1230 
+mOPM (36Slow,   DirectIndexedXSlow,               WRAP_BANK, ROL)
1231 
+
1232 
+mOP8 (2EM1,     Absolute,                         WRAP_NONE, ROL)
1233 
+mOP16(2EM0,     Absolute,                         WRAP_NONE, ROL)
1234 
+mOPM (2ESlow,   AbsoluteSlow,                     WRAP_NONE, ROL)
1235 
+
1236 
+mOP8 (3EM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, ROL)
1237 
+mOP16(3EM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, ROL)
1238 
+mOP8 (3EM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, ROL)
1239 
+mOP16(3EM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, ROL)
1240 
+mOPM (3ESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, ROL)
1241 
+
1242 
+/* ROR ********************************************************************* */
1243 
+
1244 
+static void Op6AM1()
1245 
+{
1246 
+	AddCycles(ONE_CYCLE);
1247 
+	uint16_t	w = ((uint16_t) Registers.AL) | (((uint16_t) CheckCarry()) << 8);
1248 
+	ICPU._Carry = w & 1;
1249 
+	w >>= 1;
1250 
+	Registers.AL = (uint8_t) w;
1251 
+	SetZN(Registers.AL);
1252 
+}
1253 
+
1254 
+static void Op6AM0()
1255 
+{
1256 
+	AddCycles(ONE_CYCLE);
1257 
+	uint32_t	w = ((uint32_t) Registers.A.W) | (((uint32_t) CheckCarry()) << 16);
1258 
+	ICPU._Carry = w & 1;
1259 
+	w >>= 1;
1260 
+	Registers.A.W = (uint16_t) w;
1261 
+	SetZN(Registers.A.W);
1262 
+}
1263 
+
1264 
+static void Op6ASlow()
1265 
+{
1266 
+	AddCycles(ONE_CYCLE);
1267 
+
1268 
+	if (CheckMemory())
1269 
+	{
1270 
+		uint16_t	w = ((uint16_t) Registers.AL) | (((uint16_t) CheckCarry()) << 8);
1271 
+		ICPU._Carry = w & 1;
1272 
+		w >>= 1;
1273 
+		Registers.AL = (uint8_t) w;
1274 
+		SetZN(Registers.AL);
1275 
+	}
1276 
+	else
1277 
+	{
1278 
+		uint32_t	w = ((uint32_t) Registers.A.W) | (((uint32_t) CheckCarry()) << 16);
1279 
+		ICPU._Carry = w & 1;
1280 
+		w >>= 1;
1281 
+		Registers.A.W = (uint16_t) w;
1282 
+		SetZN(Registers.A.W);
1283 
+	}
1284 
+}
1285 
+
1286 
+mOP8 (66M1,     Direct,                           WRAP_BANK, ROR)
1287 
+mOP16(66M0,     Direct,                           WRAP_BANK, ROR)
1288 
+mOPM (66Slow,   DirectSlow,                       WRAP_BANK, ROR)
1289 
+
1290 
+mOP8 (76E1,     DirectIndexedXE1,                 WRAP_BANK, ROR)
1291 
+mOP8 (76E0M1,   DirectIndexedXE0,                 WRAP_BANK, ROR)
1292 
+mOP16(76E0M0,   DirectIndexedXE0,                 WRAP_BANK, ROR)
1293 
+mOPM (76Slow,   DirectIndexedXSlow,               WRAP_BANK, ROR)
1294 
+
1295 
+mOP8 (6EM1,     Absolute,                         WRAP_NONE, ROR)
1296 
+mOP16(6EM0,     Absolute,                         WRAP_NONE, ROR)
1297 
+mOPM (6ESlow,   AbsoluteSlow,                     WRAP_NONE, ROR)
1298 
+
1299 
+mOP8 (7EM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, ROR)
1300 
+mOP16(7EM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, ROR)
1301 
+mOP8 (7EM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, ROR)
1302 
+mOP16(7EM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, ROR)
1303 
+mOPM (7ESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, ROR)
1304 
+
1305 
+/* SBC ********************************************************************* */
1306 
+
1307 
+static void OpE9M1()
1308 
+{
1309 
+	SBC(Immediate8(READ));
1310 
+}
1311 
+
1312 
+static void OpE9M0()
1313 
+{
1314 
+	SBC(Immediate16(READ));
1315 
+}
1316 
+
1317 
+static void OpE9Slow()
1318 
+{
1319 
+	if (CheckMemory())
1320 
+		SBC(Immediate8Slow(READ));
1321 
+	else
1322 
+		SBC(Immediate16Slow(READ));
1323 
+}
1324 
+
1325 
+rOP8 (E5M1,     Direct,                           WRAP_BANK, SBC)
1326 
+rOP16(E5M0,     Direct,                           WRAP_BANK, SBC)
1327 
+rOPM (E5Slow,   DirectSlow,                       WRAP_BANK, SBC)
1328 
+
1329 
+rOP8 (F5E1,     DirectIndexedXE1,                 WRAP_BANK, SBC)
1330 
+rOP8 (F5E0M1,   DirectIndexedXE0,                 WRAP_BANK, SBC)
1331 
+rOP16(F5E0M0,   DirectIndexedXE0,                 WRAP_BANK, SBC)
1332 
+rOPM (F5Slow,   DirectIndexedXSlow,               WRAP_BANK, SBC)
1333 
+
1334 
+rOP8 (F2E1,     DirectIndirectE1,                 WRAP_NONE, SBC)
1335 
+rOP8 (F2E0M1,   DirectIndirectE0,                 WRAP_NONE, SBC)
1336 
+rOP16(F2E0M0,   DirectIndirectE0,                 WRAP_NONE, SBC)
1337 
+rOPM (F2Slow,   DirectIndirectSlow,               WRAP_NONE, SBC)
1338 
+
1339 
+rOP8 (E1E1,     DirectIndexedIndirectE1,          WRAP_NONE, SBC)
1340 
+rOP8 (E1E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, SBC)
1341 
+rOP16(E1E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, SBC)
1342 
+rOPM (E1Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, SBC)
1343 
+
1344 
+rOP8 (F1E1,     DirectIndirectIndexedE1,          WRAP_NONE, SBC)
1345 
+rOP8 (F1E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, SBC)
1346 
+rOP16(F1E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, SBC)
1347 
+rOP8 (F1E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, SBC)
1348 
+rOP16(F1E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, SBC)
1349 
+rOPM (F1Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, SBC)
1350 
+
1351 
+rOP8 (E7M1,     DirectIndirectLong,               WRAP_NONE, SBC)
1352 
+rOP16(E7M0,     DirectIndirectLong,               WRAP_NONE, SBC)
1353 
+rOPM (E7Slow,   DirectIndirectLongSlow,           WRAP_NONE, SBC)
1354 
+
1355 
+rOP8 (F7M1,     DirectIndirectIndexedLong,        WRAP_NONE, SBC)
1356 
+rOP16(F7M0,     DirectIndirectIndexedLong,        WRAP_NONE, SBC)
1357 
+rOPM (F7Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, SBC)
1358 
+
1359 
+rOP8 (EDM1,     Absolute,                         WRAP_NONE, SBC)
1360 
+rOP16(EDM0,     Absolute,                         WRAP_NONE, SBC)
1361 
+rOPM (EDSlow,   AbsoluteSlow,                     WRAP_NONE, SBC)
1362 
+
1363 
+rOP8 (FDM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, SBC)
1364 
+rOP16(FDM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, SBC)
1365 
+rOP8 (FDM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, SBC)
1366 
+rOP16(FDM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, SBC)
1367 
+rOPM (FDSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, SBC)
1368 
+
1369 
+rOP8 (F9M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, SBC)
1370 
+rOP16(F9M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, SBC)
1371 
+rOP8 (F9M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, SBC)
1372 
+rOP16(F9M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, SBC)
1373 
+rOPM (F9Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, SBC)
1374 
+
1375 
+rOP8 (EFM1,     AbsoluteLong,                     WRAP_NONE, SBC)
1376 
+rOP16(EFM0,     AbsoluteLong,                     WRAP_NONE, SBC)
1377 
+rOPM (EFSlow,   AbsoluteLongSlow,                 WRAP_NONE, SBC)
1378 
+
1379 
+rOP8 (FFM1,     AbsoluteLongIndexedX,             WRAP_NONE, SBC)
1380 
+rOP16(FFM0,     AbsoluteLongIndexedX,             WRAP_NONE, SBC)
1381 
+rOPM (FFSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, SBC)
1382 
+
1383 
+rOP8 (E3M1,     StackRelative,                    WRAP_NONE, SBC)
1384 
+rOP16(E3M0,     StackRelative,                    WRAP_NONE, SBC)
1385 
+rOPM (E3Slow,   StackRelativeSlow,                WRAP_NONE, SBC)
1386 
+
1387 
+rOP8 (F3M1,     StackRelativeIndirectIndexed,     WRAP_NONE, SBC)
1388 
+rOP16(F3M0,     StackRelativeIndirectIndexed,     WRAP_NONE, SBC)
1389 
+rOPM (F3Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, SBC)
1390 
+
1391 
+/* STA ********************************************************************* */
1392 
+
1393 
+wOP8 (85M1,     Direct,                           WRAP_BANK, STA)
1394 
+wOP16(85M0,     Direct,                           WRAP_BANK, STA)
1395 
+wOPM (85Slow,   DirectSlow,                       WRAP_BANK, STA)
1396 
+
1397 
+wOP8 (95E1,     DirectIndexedXE1,                 WRAP_BANK, STA)
1398 
+wOP8 (95E0M1,   DirectIndexedXE0,                 WRAP_BANK, STA)
1399 
+wOP16(95E0M0,   DirectIndexedXE0,                 WRAP_BANK, STA)
1400 
+wOPM (95Slow,   DirectIndexedXSlow,               WRAP_BANK, STA)
1401 
+
1402 
+wOP8 (92E1,     DirectIndirectE1,                 WRAP_NONE, STA)
1403 
+wOP8 (92E0M1,   DirectIndirectE0,                 WRAP_NONE, STA)
1404 
+wOP16(92E0M0,   DirectIndirectE0,                 WRAP_NONE, STA)
1405 
+wOPM (92Slow,   DirectIndirectSlow,               WRAP_NONE, STA)
1406 
+
1407 
+wOP8 (81E1,     DirectIndexedIndirectE1,          WRAP_NONE, STA)
1408 
+wOP8 (81E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, STA)
1409 
+wOP16(81E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, STA)
1410 
+wOPM (81Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, STA)
1411 
+
1412 
+wOP8 (91E1,     DirectIndirectIndexedE1,          WRAP_NONE, STA)
1413 
+wOP8 (91E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, STA)
1414 
+wOP16(91E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, STA)
1415 
+wOP8 (91E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, STA)
1416 
+wOP16(91E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, STA)
1417 
+wOPM (91Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, STA)
1418 
+
1419 
+wOP8 (87M1,     DirectIndirectLong,               WRAP_NONE, STA)
1420 
+wOP16(87M0,     DirectIndirectLong,               WRAP_NONE, STA)
1421 
+wOPM (87Slow,   DirectIndirectLongSlow,           WRAP_NONE, STA)
1422 
+
1423 
+wOP8 (97M1,     DirectIndirectIndexedLong,        WRAP_NONE, STA)
1424 
+wOP16(97M0,     DirectIndirectIndexedLong,        WRAP_NONE, STA)
1425 
+wOPM (97Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, STA)
1426 
+
1427 
+wOP8 (8DM1,     Absolute,                         WRAP_NONE, STA)
1428 
+wOP16(8DM0,     Absolute,                         WRAP_NONE, STA)
1429 
+wOPM (8DSlow,   AbsoluteSlow,                     WRAP_NONE, STA)
1430 
+
1431 
+wOP8 (9DM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, STA)
1432 
+wOP16(9DM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, STA)
1433 
+wOP8 (9DM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, STA)
1434 
+wOP16(9DM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, STA)
1435 
+wOPM (9DSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, STA)
1436 
+
1437 
+wOP8 (99M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, STA)
1438 
+wOP16(99M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, STA)
1439 
+wOP8 (99M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, STA)
1440 
+wOP16(99M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, STA)
1441 
+wOPM (99Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, STA)
1442 
+
1443 
+wOP8 (8FM1,     AbsoluteLong,                     WRAP_NONE, STA)
1444 
+wOP16(8FM0,     AbsoluteLong,                     WRAP_NONE, STA)
1445 
+wOPM (8FSlow,   AbsoluteLongSlow,                 WRAP_NONE, STA)
1446 
+
1447 
+wOP8 (9FM1,     AbsoluteLongIndexedX,             WRAP_NONE, STA)
1448 
+wOP16(9FM0,     AbsoluteLongIndexedX,             WRAP_NONE, STA)
1449 
+wOPM (9FSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, STA)
1450 
+
1451 
+wOP8 (83M1,     StackRelative,                    WRAP_NONE, STA)
1452 
+wOP16(83M0,     StackRelative,                    WRAP_NONE, STA)
1453 
+wOPM (83Slow,   StackRelativeSlow,                WRAP_NONE, STA)
1454 
+
1455 
+wOP8 (93M1,     StackRelativeIndirectIndexed,     WRAP_NONE, STA)
1456 
+wOP16(93M0,     StackRelativeIndirectIndexed,     WRAP_NONE, STA)
1457 
+wOPM (93Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, STA)
1458 
+
1459 
+/* STX ********************************************************************* */
1460 
+
1461 
+wOP8 (86X1,     Direct,                           WRAP_BANK, STX)
1462 
+wOP16(86X0,     Direct,                           WRAP_BANK, STX)
1463 
+wOPX (86Slow,   DirectSlow,                       WRAP_BANK, STX)
1464 
+
1465 
+wOP8 (96E1,     DirectIndexedYE1,                 WRAP_BANK, STX)
1466 
+wOP8 (96E0X1,   DirectIndexedYE0,                 WRAP_BANK, STX)
1467 
+wOP16(96E0X0,   DirectIndexedYE0,                 WRAP_BANK, STX)
1468 
+wOPX (96Slow,   DirectIndexedYSlow,               WRAP_BANK, STX)
1469 
+
1470 
+wOP8 (8EX1,     Absolute,                         WRAP_BANK, STX)
1471 
+wOP16(8EX0,     Absolute,                         WRAP_BANK, STX)
1472 
+wOPX (8ESlow,   AbsoluteSlow,                     WRAP_BANK, STX)
1473 
+
1474 
+/* STY ********************************************************************* */
1475 
+
1476 
+wOP8 (84X1,     Direct,                           WRAP_BANK, STY)
1477 
+wOP16(84X0,     Direct,                           WRAP_BANK, STY)
1478 
+wOPX (84Slow,   DirectSlow,                       WRAP_BANK, STY)
1479 
+
1480 
+wOP8 (94E1,     DirectIndexedXE1,                 WRAP_BANK, STY)
1481 
+wOP8 (94E0X1,   DirectIndexedXE0,                 WRAP_BANK, STY)
1482 
+wOP16(94E0X0,   DirectIndexedXE0,                 WRAP_BANK, STY)
1483 
+wOPX (94Slow,   DirectIndexedXSlow,               WRAP_BANK, STY)
1484 
+
1485 
+wOP8 (8CX1,     Absolute,                         WRAP_BANK, STY)
1486 
+wOP16(8CX0,     Absolute,                         WRAP_BANK, STY)
1487 
+wOPX (8CSlow,   AbsoluteSlow,                     WRAP_BANK, STY)
1488 
+
1489 
+/* STZ ********************************************************************* */
1490 
+
1491 
+wOP8 (64M1,     Direct,                           WRAP_BANK, STZ)
1492 
+wOP16(64M0,     Direct,                           WRAP_BANK, STZ)
1493 
+wOPM (64Slow,   DirectSlow,                       WRAP_BANK, STZ)
1494 
+
1495 
+wOP8 (74E1,     DirectIndexedXE1,                 WRAP_BANK, STZ)
1496 
+wOP8 (74E0M1,   DirectIndexedXE0,                 WRAP_BANK, STZ)
1497 
+wOP16(74E0M0,   DirectIndexedXE0,                 WRAP_BANK, STZ)
1498 
+wOPM (74Slow,   DirectIndexedXSlow,               WRAP_BANK, STZ)
1499 
+
1500 
+wOP8 (9CM1,     Absolute,                         WRAP_NONE, STZ)
1501 
+wOP16(9CM0,     Absolute,                         WRAP_NONE, STZ)
1502 
+wOPM (9CSlow,   AbsoluteSlow,                     WRAP_NONE, STZ)
1503 
+
1504 
+wOP8 (9EM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, STZ)
1505 
+wOP16(9EM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, STZ)
1506 
+wOP8 (9EM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, STZ)
1507 
+wOP16(9EM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, STZ)
1508 
+wOPM (9ESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, STZ)
1509 
+
1510 
+/* TRB ********************************************************************* */
1511 
+
1512 
+mOP8 (14M1,     Direct,                           WRAP_BANK, TRB)
1513 
+mOP16(14M0,     Direct,                           WRAP_BANK, TRB)
1514 
+mOPM (14Slow,   DirectSlow,                       WRAP_BANK, TRB)
1515 
+
1516 
+mOP8 (1CM1,     Absolute,                         WRAP_BANK, TRB)
1517 
+mOP16(1CM0,     Absolute,                         WRAP_BANK, TRB)
1518 
+mOPM (1CSlow,   AbsoluteSlow,                     WRAP_BANK, TRB)
1519 
+
1520 
+/* TSB ********************************************************************* */
1521 
+
1522 
+mOP8 (04M1,     Direct,                           WRAP_BANK, TSB)
1523 
+mOP16(04M0,     Direct,                           WRAP_BANK, TSB)
1524 
+mOPM (04Slow,   DirectSlow,                       WRAP_BANK, TSB)
1525 
+
1526 
+mOP8 (0CM1,     Absolute,                         WRAP_BANK, TSB)
1527 
+mOP16(0CM0,     Absolute,                         WRAP_BANK, TSB)
1528 
+mOPM (0CSlow,   AbsoluteSlow,                     WRAP_BANK, TSB)
1529 
+
1530 
+/* Branch Instructions ***************************************************** */
1531 
+
1532 
+// BCC
1533 
+bOP(90E0,   Relative,     !CheckCarry(),    0, 0)
1534 
+bOP(90E1,   Relative,     !CheckCarry(),    0, 1)
1535 
+bOP(90Slow, RelativeSlow, !CheckCarry(),    0, CheckEmulation())
1536 
+
1537 
+// BCS
1538 
+bOP(B0E0,   Relative,      CheckCarry(),    0, 0)
1539 
+bOP(B0E1,   Relative,      CheckCarry(),    0, 1)
1540 
+bOP(B0Slow, RelativeSlow,  CheckCarry(),    0, CheckEmulation())
1541 
+
1542 
+// BEQ
1543 
+bOP(F0E0,   Relative,      CheckZero(),     2, 0)
1544 
+bOP(F0E1,   Relative,      CheckZero(),     2, 1)
1545 
+bOP(F0Slow, RelativeSlow,  CheckZero(),     2, CheckEmulation())
1546 
+
1547 
+// BMI
1548 
+bOP(30E0,   Relative,      CheckNegative(), 1, 0)
1549 
+bOP(30E1,   Relative,      CheckNegative(), 1, 1)
1550 
+bOP(30Slow, RelativeSlow,  CheckNegative(), 1, CheckEmulation())
1551 
+
1552 
+// BNE
1553 
+bOP(D0E0,   Relative,     !CheckZero(),     1, 0)
1554 
+bOP(D0E1,   Relative,     !CheckZero(),     1, 1)
1555 
+bOP(D0Slow, RelativeSlow, !CheckZero(),     1, CheckEmulation())
1556 
+
1557 
+// BPL
1558 
+bOP(10E0,   Relative,     !CheckNegative(), 1, 0)
1559 
+bOP(10E1,   Relative,     !CheckNegative(), 1, 1)
1560 
+bOP(10Slow, RelativeSlow, !CheckNegative(), 1, CheckEmulation())
1561 
+
1562 
+// BRA
1563 
+bOP(80E0,   Relative,     1,                X, 0)
1564 
+bOP(80E1,   Relative,     1,                X, 1)
1565 
+bOP(80Slow, RelativeSlow, 1,                X, CheckEmulation())
1566 
+
1567 
+// BVC
1568 
+bOP(50E0,   Relative,     !CheckOverflow(), 0, 0)
1569 
+bOP(50E1,   Relative,     !CheckOverflow(), 0, 1)
1570 
+bOP(50Slow, RelativeSlow, !CheckOverflow(), 0, CheckEmulation())
1571 
+
1572 
+// BVS
1573 
+bOP(70E0,   Relative,      CheckOverflow(), 0, 0)
1574 
+bOP(70E1,   Relative,      CheckOverflow(), 0, 1)
1575 
+bOP(70Slow, RelativeSlow,  CheckOverflow(), 0, CheckEmulation())
1576 
+
1577 
+// BRL
1578 
+static void Op82()
1579 
+{
1580 
+	S9xSetPCBase(ICPU.ShiftedPB + RelativeLong(JUMP));
1581 
+}
1582 
+
1583 
+static void Op82Slow()
1584 
+{
1585 
+	S9xSetPCBase(ICPU.ShiftedPB + RelativeLongSlow(JUMP));
1586 
+}
1587 
+
1588 
+/* Flag Instructions ******************************************************* */
1589 
+
1590 
+// CLC
1591 
+static void Op18()
1592 
+{
1593 
+	ClearCarry();
1594 
+	AddCycles(ONE_CYCLE);
1595 
+}
1596 
+
1597 
+// SEC
1598 
+static void Op38()
1599 
+{
1600 
+	SetCarry();
1601 
+	AddCycles(ONE_CYCLE);
1602 
+}
1603 
+
1604 
+// CLD
1605 
+static void OpD8()
1606 
+{
1607 
+	ClearDecimal();
1608 
+	AddCycles(ONE_CYCLE);
1609 
+}
1610 
+
1611 
+// SED
1612 
+static void OpF8()
1613 
+{
1614 
+	SetDecimal();
1615 
+	AddCycles(ONE_CYCLE);
1616 
+#ifdef DEBUGGER
1617 
+	missing.decimal_mode = 1;
1618 
+#endif
1619 
+}
1620 
+
1621 
+// CLI
1622 
+static void Op58()
1623 
+{
1624 
+	ClearIRQ();
1625 
+	AddCycles(ONE_CYCLE);
1626 
+	CHECK_FOR_IRQ();
1627 
+}
1628 
+
1629 
+// SEI
1630 
+static void Op78()
1631 
+{
1632 
+	SetIRQ();
1633 
+	AddCycles(ONE_CYCLE);
1634 
+}
1635 
+
1636 
+// CLV
1637 
+static void OpB8()
1638 
+{
1639 
+	ClearOverflow();
1640 
+	AddCycles(ONE_CYCLE);
1641 
+}
1642 
+
1643 
+/* DEX/DEY ***************************************************************** */
1644 
+
1645 
+static void OpCAX1()
1646 
+{
1647 
+	AddCycles(ONE_CYCLE);
1648 
+	Registers.XL--;
1649 
+	SetZN(Registers.XL);
1650 
+}
1651 
+
1652 
+static void OpCAX0()
1653 
+{
1654 
+	AddCycles(ONE_CYCLE);
1655 
+	Registers.X.W--;
1656 
+	SetZN(Registers.X.W);
1657 
+}
1658 
+
1659 
+static void OpCASlow()
1660 
+{
1661 
+	AddCycles(ONE_CYCLE);
1662 
+
1663 
+	if (CheckIndex())
1664 
+	{
1665 
+		Registers.XL--;
1666 
+		SetZN(Registers.XL);
1667 
+	}
1668 
+	else
1669 
+	{
1670 
+		Registers.X.W--;
1671 
+		SetZN(Registers.X.W);
1672 
+	}
1673 
+}
1674 
+
1675 
+static void Op88X1()
1676 
+{
1677 
+	AddCycles(ONE_CYCLE);
1678 
+	Registers.YL--;
1679 
+	SetZN(Registers.YL);
1680 
+}
1681 
+
1682 
+static void Op88X0()
1683 
+{
1684 
+	AddCycles(ONE_CYCLE);
1685 
+	Registers.Y.W--;
1686 
+	SetZN(Registers.Y.W);
1687 
+}
1688 
+
1689 
+static void Op88Slow()
1690 
+{
1691 
+	AddCycles(ONE_CYCLE);
1692 
+
1693 
+	if (CheckIndex())
1694 
+	{
1695 
+		Registers.YL--;
1696 
+		SetZN(Registers.YL);
1697 
+	}
1698 
+	else
1699 
+	{
1700 
+		Registers.Y.W--;
1701 
+		SetZN(Registers.Y.W);
1702 
+	}
1703 
+}
1704 
+
1705 
+/* INX/INY ***************************************************************** */
1706 
+
1707 
+static void OpE8X1()
1708 
+{
1709 
+	AddCycles(ONE_CYCLE);
1710 
+	Registers.XL++;
1711 
+	SetZN(Registers.XL);
1712 
+}
1713 
+
1714 
+static void OpE8X0()
1715 
+{
1716 
+	AddCycles(ONE_CYCLE);
1717 
+	Registers.X.W++;
1718 
+	SetZN(Registers.X.W);
1719 
+}
1720 
+
1721 
+static void OpE8Slow()
1722 
+{
1723 
+	AddCycles(ONE_CYCLE);
1724 
+
1725 
+	if (CheckIndex())
1726 
+	{
1727 
+		Registers.XL++;
1728 
+		SetZN(Registers.XL);
1729 
+	}
1730 
+	else
1731 
+	{
1732 
+		Registers.X.W++;
1733 
+		SetZN(Registers.X.W);
1734 
+	}
1735 
+}
1736 
+
1737 
+static void OpC8X1()
1738 
+{
1739 
+	AddCycles(ONE_CYCLE);
1740 
+	Registers.YL++;
1741 
+	SetZN(Registers.YL);
1742 
+}
1743 
+
1744 
+static void OpC8X0()
1745 
+{
1746 
+	AddCycles(ONE_CYCLE);
1747 
+	Registers.Y.W++;
1748 
+	SetZN(Registers.Y.W);
1749 
+}
1750 
+
1751 
+static void OpC8Slow()
1752 
+{
1753 
+	AddCycles(ONE_CYCLE);
1754 
+
1755 
+	if (CheckIndex())
1756 
+	{
1757 
+		Registers.YL--;
1758 
+		SetZN(Registers.YL);
1759 
+	}
1760 
+	else
1761 
+	{
1762 
+		Registers.Y.W--;
1763 
+		SetZN(Registers.Y.W);
1764 
+	}
1765 
+}
1766 
+
1767 
+/* NOP ********************************************************************* */
1768 
+
1769 
+static void OpEA()
1770 
+{
1771 
+	AddCycles(ONE_CYCLE);
1772 
+}
1773 
+
1774 
+/* PUSH Instructions ******************************************************* */
1775 
+
1776 
+#define PushW(w) \
1777 
+	S9xSetWord(w, Registers.S.W - 1, WRAP_BANK, WRITE_10); \
1778 
+	Registers.S.W -= 2;
1779 
+
1780 
+#define PushWE(w) \
1781 
+	Registers.SL--; \
1782 
+	S9xSetWord(w, Registers.S.W, WRAP_PAGE, WRITE_10); \
1783 
+	Registers.SL--;
1784 
+
1785 
+#define PushB(b) \
1786 
+	S9xSetByte(b, Registers.S.W--);
1787 
+
1788 
+#define PushBE(b) \
1789 
+	S9xSetByte(b, Registers.S.W); \
1790 
+	Registers.SL--;
1791 
+
1792 
+// PEA
1793 
+static void OpF4E0()
1794 
+{
1795 
+	uint16_t	val = (uint16_t) Absolute(NONE);
1796 
+	PushW(val);
1797 
+	OpenBus = val & 0xff;
1798 
+}
1799 
+
1800 
+static void OpF4E1()
1801 
+{
1802 
+	// Note: PEA is a new instruction,
1803 
+	// and so doesn't respect the emu-mode stack bounds.
1804 
+	uint16_t	val = (uint16_t) Absolute(NONE);
1805 
+	PushW(val);
1806 
+	OpenBus = val & 0xff;
1807 
+	Registers.SH = 1;
1808 
+}
1809 
+
1810 
+static void OpF4Slow()
1811 
+{
1812 
+	uint16_t	val = (uint16_t) AbsoluteSlow(NONE);
1813 
+	PushW(val);
1814 
+	OpenBus = val & 0xff;
1815 
+	if (CheckEmulation())
1816 
+		Registers.SH = 1;
1817 
+}
1818 
+
1819 
+// PEI
1820 
+static void OpD4E0()
1821 
+{
1822 
+	uint16_t	val = (uint16_t) DirectIndirectE0(NONE);
1823 
+	PushW(val);
1824 
+	OpenBus = val & 0xff;
1825 
+}
1826 
+
1827 
+static void OpD4E1()
1828 
+{
1829 
+	// Note: PEI is a new instruction,
1830 
+	// and so doesn't respect the emu-mode stack bounds.
1831 
+	uint16_t	val = (uint16_t) DirectIndirectE1(NONE);
1832 
+	PushW(val);
1833 
+	OpenBus = val & 0xff;
1834 
+	Registers.SH = 1;
1835 
+}
1836 
+
1837 
+static void OpD4Slow()
1838 
+{
1839 
+	uint16_t	val = (uint16_t) DirectIndirectSlow(NONE);
1840 
+	PushW(val);
1841 
+	OpenBus = val & 0xff;
1842 
+	if (CheckEmulation())
1843 
+		Registers.SH = 1;
1844 
+}
1845 
+
1846 
+// PER
1847 
+static void Op62E0()
1848 
+{
1849 
+	uint16_t	val = (uint16_t) RelativeLong(NONE);
1850 
+	PushW(val);
1851 
+	OpenBus = val & 0xff;
1852 
+}
1853 
+
1854 
+static void Op62E1()
1855 
+{
1856 
+	// Note: PER is a new instruction,
1857 
+	// and so doesn't respect the emu-mode stack bounds.
1858 
+	uint16_t	val = (uint16_t) RelativeLong(NONE);
1859 
+	PushW(val);
1860 
+	OpenBus = val & 0xff;
1861 
+	Registers.SH = 1;
1862 
+}
1863 
+
1864 
+static void Op62Slow()
1865 
+{
1866 
+	uint16_t	val = (uint16_t) RelativeLongSlow(NONE);
1867 
+	PushW(val);
1868 
+	OpenBus = val & 0xff;
1869 
+	if (CheckEmulation())
1870 
+		Registers.SH = 1;
1871 
+}
1872 
+
1873 
+// PHA
1874 
+static void Op48E1()
1875 
+{
1876 
+	AddCycles(ONE_CYCLE);
1877 
+	PushBE(Registers.AL);
1878 
+	OpenBus = Registers.AL;
1879 
+}
1880 
+
1881 
+static void Op48E0M1()
1882 
+{
1883 
+	AddCycles(ONE_CYCLE);
1884 
+	PushB(Registers.AL);
1885 
+	OpenBus = Registers.AL;
1886 
+}
1887 
+
1888 
+static void Op48E0M0()
1889 
+{
1890 
+	AddCycles(ONE_CYCLE);
1891 
+	PushW(Registers.A.W);
1892 
+	OpenBus = Registers.AL;
1893 
+}
1894 
+
1895 
+static void Op48Slow()
1896 
+{
1897 
+	AddCycles(ONE_CYCLE);
1898 
+
1899 
+	if (CheckEmulation())
1900 
+	{
1901 
+		PushBE(Registers.AL);
1902 
+	}
1903 
+	else
1904 
+	if (CheckMemory())
1905 
+	{
1906 
+		PushB(Registers.AL);
1907 
+	}
1908 
+	else
1909 
+	{
1910 
+		PushW(Registers.A.W);
1911 
+	}
1912 
+
1913 
+	OpenBus = Registers.AL;
1914 
+}
1915 
+
1916 
+// PHB
1917 
+static void Op8BE1()
1918 
+{
1919 
+	AddCycles(ONE_CYCLE);
1920 
+	PushBE(Registers.DB);
1921 
+	OpenBus = Registers.DB;
1922 
+}
1923 
+
1924 
+static void Op8BE0()
1925 
+{
1926 
+	AddCycles(ONE_CYCLE);
1927 
+	PushB(Registers.DB);
1928 
+	OpenBus = Registers.DB;
1929 
+}
1930 
+
1931 
+static void Op8BSlow()
1932 
+{
1933 
+	AddCycles(ONE_CYCLE);
1934 
+
1935 
+	if (CheckEmulation())
1936 
+	{
1937 
+		PushBE(Registers.DB);
1938 
+	}
1939 
+	else
1940 
+	{
1941 
+		PushB(Registers.DB);
1942 
+	}
1943 
+
1944 
+	OpenBus = Registers.DB;
1945 
+}
1946 
+
1947 
+// PHD
1948 
+static void Op0BE0()
1949 
+{
1950 
+	AddCycles(ONE_CYCLE);
1951 
+	PushW(Registers.D.W);
1952 
+	OpenBus = Registers.DL;
1953 
+}
1954 
+
1955 
+static void Op0BE1()
1956 
+{
1957 
+	// Note: PHD is a new instruction,
1958 
+	// and so doesn't respect the emu-mode stack bounds.
1959 
+	AddCycles(ONE_CYCLE);
1960 
+	PushW(Registers.D.W);
1961 
+	OpenBus = Registers.DL;
1962 
+	Registers.SH = 1;
1963 
+}
1964 
+
1965 
+static void Op0BSlow()
1966 
+{
1967 
+	AddCycles(ONE_CYCLE);
1968 
+	PushW(Registers.D.W);
1969 
+	OpenBus = Registers.DL;
1970 
+	if (CheckEmulation())
1971 
+		Registers.SH = 1;
1972 
+}
1973 
+
1974 
+// PHK
1975 
+static void Op4BE1()
1976 
+{
1977 
+	AddCycles(ONE_CYCLE);
1978 
+	PushBE(Registers.PB);
1979 
+	OpenBus = Registers.PB;
1980 
+}
1981 
+
1982 
+static void Op4BE0()
1983 
+{
1984 
+	AddCycles(ONE_CYCLE);
1985 
+	PushB(Registers.PB);
1986 
+	OpenBus = Registers.PB;
1987 
+}
1988 
+
1989 
+static void Op4BSlow()
1990 
+{
1991 
+	AddCycles(ONE_CYCLE);
1992 
+
1993 
+	if (CheckEmulation())
1994 
+	{
1995 
+		PushBE(Registers.PB);
1996 
+	}
1997 
+	else
1998 
+	{
1999 
+		PushB(Registers.PB);
2000 
+	}
2001 
+
2002 
+	OpenBus = Registers.PB;
2003 
+}
2004 
+
2005 
+// PHP
2006 
+static void Op08E0()
2007 
+{
2008 
+	S9xPackStatus();
2009 
+	AddCycles(ONE_CYCLE);
2010 
+	PushB(Registers.PL);
2011 
+	OpenBus = Registers.PL;
2012 
+}
2013 
+
2014 
+static void Op08E1()
2015 
+{
2016 
+	S9xPackStatus();
2017 
+	AddCycles(ONE_CYCLE);
2018 
+	PushBE(Registers.PL);
2019 
+	OpenBus = Registers.PL;
2020 
+}
2021 
+
2022 
+static void Op08Slow()
2023 
+{
2024 
+	S9xPackStatus();
2025 
+	AddCycles(ONE_CYCLE);
2026 
+
2027 
+	if (CheckEmulation())
2028 
+	{
2029 
+		PushBE(Registers.PL);
2030 
+	}
2031 
+	else
2032 
+	{
2033 
+		PushB(Registers.PL);
2034 
+	}
2035 
+
2036 
+	OpenBus = Registers.PL;
2037 
+}
2038 
+
2039 
+// PHX
2040 
+static void OpDAE1()
2041 
+{
2042 
+	AddCycles(ONE_CYCLE);
2043 
+	PushBE(Registers.XL);
2044 
+	OpenBus = Registers.XL;
2045 
+}
2046 
+
2047 
+static void OpDAE0X1()
2048 
+{
2049 
+	AddCycles(ONE_CYCLE);
2050 
+	PushB(Registers.XL);
2051 
+	OpenBus = Registers.XL;
2052 
+}
2053 
+
2054 
+static void OpDAE0X0()
2055 
+{
2056 
+	AddCycles(ONE_CYCLE);
2057 
+	PushW(Registers.X.W);
2058 
+	OpenBus = Registers.XL;
2059 
+}
2060 
+
2061 
+static void OpDASlow()
2062 
+{
2063 
+	AddCycles(ONE_CYCLE);
2064 
+
2065 
+	if (CheckEmulation())
2066 
+	{
2067 
+		PushBE(Registers.XL);
2068 
+	}
2069 
+	else
2070 
+	if (CheckIndex())
2071 
+	{
2072 
+		PushB(Registers.XL);
2073 
+	}
2074 
+	else
2075 
+	{
2076 
+		PushW(Registers.X.W);
2077 
+	}
2078 
+
2079 
+	OpenBus = Registers.XL;
2080 
+}
2081 
+
2082 
+// PHY
2083 
+static void Op5AE1()
2084 
+{
2085 
+	AddCycles(ONE_CYCLE);
2086 
+	PushBE(Registers.YL);
2087 
+	OpenBus = Registers.YL;
2088 
+}
2089 
+
2090 
+static void Op5AE0X1()
2091 
+{
2092 
+	AddCycles(ONE_CYCLE);
2093 
+	PushB(Registers.YL);
2094 
+	OpenBus = Registers.YL;
2095 
+}
2096 
+
2097 
+static void Op5AE0X0()
2098 
+{
2099 
+	AddCycles(ONE_CYCLE);
2100 
+	PushW(Registers.Y.W);
2101 
+	OpenBus = Registers.YL;
2102 
+}
2103 
+
2104 
+static void Op5ASlow()
2105 
+{
2106 
+	AddCycles(ONE_CYCLE);
2107 
+
2108 
+	if (CheckEmulation())
2109 
+	{
2110 
+		PushBE(Registers.YL);
2111 
+	}
2112 
+	else
2113 
+	if (CheckIndex())
2114 
+	{
2115 
+		PushB(Registers.YL);
2116 
+	}
2117 
+	else
2118 
+	{
2119 
+		PushW(Registers.Y.W);
2120 
+	}
2121 
+
2122 
+	OpenBus = Registers.YL;
2123 
+}
2124 
+
2125 
+/* PULL Instructions ******************************************************* */
2126 
+
2127 
+#define PullW(w) \
2128 
+	w = S9xGetWord(Registers.S.W + 1, WRAP_BANK); \
2129 
+	Registers.S.W += 2;
2130 
+
2131 
+#define PullWE(w) \
2132 
+	Registers.SL++; \
2133 
+	w = S9xGetWord(Registers.S.W, WRAP_PAGE); \
2134 
+	Registers.SL++;
2135 
+
2136 
+#define PullB(b) \
2137 
+	b = S9xGetByte(++Registers.S.W);
2138 
+
2139 
+#define PullBE(b) \
2140 
+	Registers.SL++; \
2141 
+	b = S9xGetByte(Registers.S.W);
2142 
+
2143 
+// PLA
2144 
+static void Op68E1()
2145 
+{
2146 
+	AddCycles(TWO_CYCLES);
2147 
+	PullBE(Registers.AL);
2148 
+	SetZN(Registers.AL);
2149 
+	OpenBus = Registers.AL;
2150 
+}
2151 
+
2152 
+static void Op68E0M1()
2153 
+{
2154 
+	AddCycles(TWO_CYCLES);
2155 
+	PullB(Registers.AL);
2156 
+	SetZN(Registers.AL);
2157 
+	OpenBus = Registers.AL;
2158 
+}
2159 
+
2160 
+static void Op68E0M0()
2161 
+{
2162 
+	AddCycles(TWO_CYCLES);
2163 
+	PullW(Registers.A.W);
2164 
+	SetZN(Registers.A.W);
2165 
+	OpenBus = Registers.AH;
2166 
+}
2167 
+
2168 
+static void Op68Slow()
2169 
+{
2170 
+	AddCycles(TWO_CYCLES);
2171 
+
2172 
+	if (CheckEmulation())
2173 
+	{
2174 
+		PullBE(Registers.AL);
2175 
+		SetZN(Registers.AL);
2176 
+		OpenBus = Registers.AL;
2177 
+	}
2178 
+	else
2179 
+	if (CheckMemory())
2180 
+	{
2181 
+		PullB(Registers.AL);
2182 
+		SetZN(Registers.AL);
2183 
+		OpenBus = Registers.AL;
2184 
+	}
2185 
+	else
2186 
+	{
2187 
+		PullW(Registers.A.W);
2188 
+		SetZN(Registers.A.W);
2189 
+		OpenBus = Registers.AH;
2190 
+	}
2191 
+}
2192 
+
2193 
+// PLB
2194 
+static void OpABE1()
2195 
+{
2196 
+	AddCycles(TWO_CYCLES);
2197 
+	PullBE(Registers.DB);
2198 
+	SetZN(Registers.DB);
2199 
+	ICPU.ShiftedDB = Registers.DB << 16;
2200 
+	OpenBus = Registers.DB;
2201 
+}
2202 
+
2203 
+static void OpABE0()
2204 
+{
2205 
+	AddCycles(TWO_CYCLES);
2206 
+	PullB(Registers.DB);
2207 
+	SetZN(Registers.DB);
2208 
+	ICPU.ShiftedDB = Registers.DB << 16;
2209 
+	OpenBus = Registers.DB;
2210 
+}
2211 
+
2212 
+static void OpABSlow()
2213 
+{
2214 
+	AddCycles(TWO_CYCLES);
2215 
+
2216 
+	if (CheckEmulation())
2217 
+	{
2218 
+		PullBE(Registers.DB);
2219 
+	}
2220 
+	else
2221 
+	{
2222 
+		PullB(Registers.DB);
2223 
+	}
2224 
+
2225 
+	SetZN(Registers.DB);
2226 
+	ICPU.ShiftedDB = Registers.DB << 16;
2227 
+	OpenBus = Registers.DB;
2228 
+}
2229 
+
2230 
+// PLD
2231 
+static void Op2BE0()
2232 
+{
2233 
+	AddCycles(TWO_CYCLES);
2234 
+	PullW(Registers.D.W);
2235 
+	SetZN(Registers.D.W);
2236 
+	OpenBus = Registers.DH;
2237 
+}
2238 
+
2239 
+static void Op2BE1()
2240 
+{
2241 
+	// Note: PLD is a new instruction,
2242 
+	// and so doesn't respect the emu-mode stack bounds.
2243 
+	AddCycles(TWO_CYCLES);
2244 
+	PullW(Registers.D.W);
2245 
+	SetZN(Registers.D.W);
2246 
+	OpenBus = Registers.DH;
2247 
+	Registers.SH = 1;
2248 
+}
2249 
+
2250 
+static void Op2BSlow()
2251 
+{
2252 
+	AddCycles(TWO_CYCLES);
2253 
+	PullW(Registers.D.W);
2254 
+	SetZN(Registers.D.W);
2255 
+	OpenBus = Registers.DH;
2256 
+	if (CheckEmulation())
2257 
+		Registers.SH = 1;
2258 
+}
2259 
+
2260 
+// PLP
2261 
+static void Op28E1()
2262 
+{
2263 
+	AddCycles(TWO_CYCLES);
2264 
+	PullBE(Registers.PL);
2265 
+	OpenBus = Registers.PL;
2266 
+	SetFlags(MemoryFlag | IndexFlag);
2267 
+	S9xUnpackStatus();
2268 
+	S9xFixCycles();
2269 
+	CHECK_FOR_IRQ();
2270 
+}
2271 
+
2272 
+static void Op28E0()
2273 
+{
2274 
+	AddCycles(TWO_CYCLES);
2275 
+	PullB(Registers.PL);
2276 
+	OpenBus = Registers.PL;
2277 
+	S9xUnpackStatus();
2278 
+
2279 
+	if (CheckIndex())
2280 
+	{
2281 
+		Registers.XH = 0;
2282 
+		Registers.YH = 0;
2283 
+	}
2284 
+
2285 
+	S9xFixCycles();
2286 
+	CHECK_FOR_IRQ();
2287 
+}
2288 
+
2289 
+static void Op28Slow()
2290 
+{
2291 
+	AddCycles(TWO_CYCLES);
2292 
+
2293 
+	if (CheckEmulation())
2294 
+	{
2295 
+		PullBE(Registers.PL);
2296 
+		OpenBus = Registers.PL;
2297 
+		SetFlags(MemoryFlag | IndexFlag);
2298 
+	}
2299 
+	else
2300 
+	{
2301 
+		PullB(Registers.PL);
2302 
+		OpenBus = Registers.PL;
2303 
+	}
2304 
+
2305 
+	S9xUnpackStatus();
2306 
+
2307 
+	if (CheckIndex())
2308 
+	{
2309 
+		Registers.XH = 0;
2310 
+		Registers.YH = 0;
2311 
+	}
2312 
+
2313 
+	S9xFixCycles();
2314 
+	CHECK_FOR_IRQ();
2315 
+}
2316 
+
2317 
+// PLX
2318 
+static void OpFAE1()
2319 
+{
2320 
+	AddCycles(TWO_CYCLES);
2321 
+	PullBE(Registers.XL);
2322 
+	SetZN(Registers.XL);
2323 
+	OpenBus = Registers.XL;
2324 
+}
2325 
+
2326 
+static void OpFAE0X1()
2327 
+{
2328 
+	AddCycles(TWO_CYCLES);
2329 
+	PullB(Registers.XL);
2330 
+	SetZN(Registers.XL);
2331 
+	OpenBus = Registers.XL;
2332 
+}
2333 
+
2334 
+static void OpFAE0X0()
2335 
+{
2336 
+	AddCycles(TWO_CYCLES);
2337 
+	PullW(Registers.X.W);
2338 
+	SetZN(Registers.X.W);
2339 
+	OpenBus = Registers.XH;
2340 
+}
2341 
+
2342 
+static void OpFASlow()
2343 
+{
2344 
+	AddCycles(TWO_CYCLES);
2345 
+
2346 
+	if (CheckEmulation())
2347 
+	{
2348 
+		PullBE(Registers.XL);
2349 
+		SetZN(Registers.XL);
2350 
+		OpenBus = Registers.XL;
2351 
+	}
2352 
+	else
2353 
+	if (CheckIndex())
2354 
+	{
2355 
+		PullB(Registers.XL);
2356 
+		SetZN(Registers.XL);
2357 
+		OpenBus = Registers.XL;
2358 
+	}
2359 
+	else
2360 
+	{
2361 
+		PullW(Registers.X.W);
2362 
+		SetZN(Registers.X.W);
2363 
+		OpenBus = Registers.XH;
2364 
+	}
2365 
+}
2366 
+
2367 
+// PLY
2368 
+static void Op7AE1()
2369 
+{
2370 
+	AddCycles(TWO_CYCLES);
2371 
+	PullBE(Registers.YL);
2372 
+	SetZN(Registers.YL);
2373 
+	OpenBus = Registers.YL;
2374 
+}
2375 
+
2376 
+static void Op7AE0X1()
2377 
+{
2378 
+	AddCycles(TWO_CYCLES);
2379 
+	PullB(Registers.YL);
2380 
+	SetZN(Registers.YL);
2381 
+	OpenBus = Registers.YL;
2382 
+}
2383 
+
2384 
+static void Op7AE0X0()
2385 
+{
2386 
+	AddCycles(TWO_CYCLES);
2387 
+	PullW(Registers.Y.W);
2388 
+	SetZN(Registers.Y.W);
2389 
+	OpenBus = Registers.YH;
2390 
+}
2391 
+
2392 
+static void Op7ASlow()
2393 
+{
2394 
+	AddCycles(TWO_CYCLES);
2395 
+
2396 
+	if (CheckEmulation())
2397 
+	{
2398 
+		PullBE(Registers.YL);
2399 
+		SetZN(Registers.YL);
2400 
+		OpenBus = Registers.YL;
2401 
+	}
2402 
+	else
2403 
+	if (CheckIndex())
2404 
+	{
2405 
+		PullB(Registers.YL);
2406 
+		SetZN(Registers.YL);
2407 
+		OpenBus = Registers.YL;
2408 
+	}
2409 
+	else
2410 
+	{
2411 
+		PullW(Registers.Y.W);
2412 
+		SetZN(Registers.Y.W);
2413 
+		OpenBus = Registers.YH;
2414 
+	}
2415 
+}
2416 
+
2417 
+/* Transfer Instructions *************************************************** */
2418 
+
2419 
+// TAX
2420 
+static void OpAAX1()
2421 
+{
2422 
+	AddCycles(ONE_CYCLE);
2423 
+	Registers.XL = Registers.AL;
2424 
+	SetZN(Registers.XL);
2425 
+}
2426 
+
2427 
+static void OpAAX0()
2428 
+{
2429 
+	AddCycles(ONE_CYCLE);
2430 
+	Registers.X.W = Registers.A.W;
2431 
+	SetZN(Registers.X.W);
2432 
+}
2433 
+
2434 
+static void OpAASlow()
2435 
+{
2436 
+	AddCycles(ONE_CYCLE);
2437 
+
2438 
+	if (CheckIndex())
2439 
+	{
2440 
+		Registers.XL = Registers.AL;
2441 
+		SetZN(Registers.XL);
2442 
+	}
2443 
+	else
2444 
+	{
2445 
+		Registers.X.W = Registers.A.W;
2446 
+		SetZN(Registers.X.W);
2447 
+	}
2448 
+}
2449 
+
2450 
+// TAY
2451 
+static void OpA8X1()
2452 
+{
2453 
+	AddCycles(ONE_CYCLE);
2454 
+	Registers.YL = Registers.AL;
2455 
+	SetZN(Registers.YL);
2456 
+}
2457 
+
2458 
+static void OpA8X0()
2459 
+{
2460 
+	AddCycles(ONE_CYCLE);
2461 
+	Registers.Y.W = Registers.A.W;
2462 
+	SetZN(Registers.Y.W);
2463 
+}
2464 
+
2465 
+static void OpA8Slow()
2466 
+{
2467 
+	AddCycles(ONE_CYCLE);
2468 
+
2469 
+	if (CheckIndex())
2470 
+	{
2471 
+		Registers.YL = Registers.AL;
2472 
+		SetZN(Registers.YL);
2473 
+	}
2474 
+	else
2475 
+	{
2476 
+		Registers.Y.W = Registers.A.W;
2477 
+		SetZN(Registers.Y.W);
2478 
+	}
2479 
+}
2480 
+
2481 
+// TCD
2482 
+static void Op5B()
2483 
+{
2484 
+	AddCycles(ONE_CYCLE);
2485 
+	Registers.D.W = Registers.A.W;
2486 
+	SetZN(Registers.D.W);
2487 
+}
2488 
+
2489 
+// TCS
2490 
+static void Op1B()
2491 
+{
2492 
+	AddCycles(ONE_CYCLE);
2493 
+	Registers.S.W = Registers.A.W;
2494 
+	if (CheckEmulation())
2495 
+		Registers.SH = 1;
2496 
+}
2497 
+
2498 
+// TDC
2499 
+static void Op7B()
2500 
+{
2501 
+	AddCycles(ONE_CYCLE);
2502 
+	Registers.A.W = Registers.D.W;
2503 
+	SetZN(Registers.A.W);
2504 
+}
2505 
+
2506 
+// TSC
2507 
+static void Op3B()
2508 
+{
2509 
+	AddCycles(ONE_CYCLE);
2510 
+	Registers.A.W = Registers.S.W;
2511 
+	SetZN(Registers.A.W);
2512 
+}
2513 
+
2514 
+// TSX
2515 
+static void OpBAX1()
2516 
+{
2517 
+	AddCycles(ONE_CYCLE);
2518 
+	Registers.XL = Registers.SL;
2519 
+	SetZN(Registers.XL);
2520 
+}
2521 
+
2522 
+static void OpBAX0()
2523 
+{
2524 
+	AddCycles(ONE_CYCLE);
2525 
+	Registers.X.W = Registers.S.W;
2526 
+	SetZN(Registers.X.W);
2527 
+}
2528 
+
2529 
+static void OpBASlow()
2530 
+{
2531 
+	AddCycles(ONE_CYCLE);
2532 
+
2533 
+	if (CheckIndex())
2534 
+	{
2535 
+		Registers.XL = Registers.SL;
2536 
+		SetZN(Registers.XL);
2537 
+	}
2538 
+	else
2539 
+	{
2540 
+		Registers.X.W = Registers.S.W;
2541 
+		SetZN(Registers.X.W);
2542 
+	}
2543 
+}
2544 
+
2545 
+// TXA
2546 
+static void Op8AM1()
2547 
+{
2548 
+	AddCycles(ONE_CYCLE);
2549 
+	Registers.AL = Registers.XL;
2550 
+	SetZN(Registers.AL);
2551 
+}
2552 
+
2553 
+static void Op8AM0()
2554 
+{
2555 
+	AddCycles(ONE_CYCLE);
2556 
+	Registers.A.W = Registers.X.W;
2557 
+	SetZN(Registers.A.W);
2558 
+}
2559 
+
2560 
+static void Op8ASlow()
2561 
+{
2562 
+	AddCycles(ONE_CYCLE);
2563 
+
2564 
+	if (CheckMemory())
2565 
+	{
2566 
+		Registers.AL = Registers.XL;
2567 
+		SetZN(Registers.AL);
2568 
+	}
2569 
+	else
2570 
+	{
2571 
+		Registers.A.W = Registers.X.W;
2572 
+		SetZN(Registers.A.W);
2573 
+	}
2574 
+}
2575 
+
2576 
+// TXS
2577 
+static void Op9A()
2578 
+{
2579 
+	AddCycles(ONE_CYCLE);
2580 
+	Registers.S.W = Registers.X.W;
2581 
+	if (CheckEmulation())
2582 
+		Registers.SH = 1;
2583 
+}
2584 
+
2585 
+// TXY
2586 
+static void Op9BX1()
2587 
+{
2588 
+	AddCycles(ONE_CYCLE);
2589 
+	Registers.YL = Registers.XL;
2590 
+	SetZN(Registers.YL);
2591 
+}
2592 
+
2593 
+static void Op9BX0()
2594 
+{
2595 
+	AddCycles(ONE_CYCLE);
2596 
+	Registers.Y.W = Registers.X.W;
2597 
+	SetZN(Registers.Y.W);
2598 
+}
2599 
+
2600 
+static void Op9BSlow()
2601 
+{
2602 
+	AddCycles(ONE_CYCLE);
2603 
+
2604 
+	if (CheckIndex())
2605 
+	{
2606 
+		Registers.YL = Registers.XL;
2607 
+		SetZN(Registers.YL);
2608 
+	}
2609 
+	else
2610 
+	{
2611 
+		Registers.Y.W = Registers.X.W;
2612 
+		SetZN(Registers.Y.W);
2613 
+	}
2614 
+}
2615 
+
2616 
+// TYA
2617 
+static void Op98M1()
2618 
+{
2619 
+	AddCycles(ONE_CYCLE);
2620 
+	Registers.AL = Registers.YL;
2621 
+	SetZN(Registers.AL);
2622 
+}
2623 
+
2624 
+static void Op98M0()
2625 
+{
2626 
+	AddCycles(ONE_CYCLE);
2627 
+	Registers.A.W = Registers.Y.W;
2628 
+	SetZN(Registers.A.W);
2629 
+}
2630 
+
2631 
+static void Op98Slow()
2632 
+{
2633 
+	AddCycles(ONE_CYCLE);
2634 
+
2635 
+	if (CheckMemory())
2636 
+	{
2637 
+		Registers.AL = Registers.YL;
2638 
+		SetZN(Registers.AL);
2639 
+	}
2640 
+	else
2641 
+	{
2642 
+		Registers.A.W = Registers.Y.W;
2643 
+		SetZN(Registers.A.W);
2644 
+	}
2645 
+}
2646 
+
2647 
+// TYX
2648 
+static void OpBBX1()
2649 
+{
2650 
+	AddCycles(ONE_CYCLE);
2651 
+	Registers.XL = Registers.YL;
2652 
+	SetZN(Registers.XL);
2653 
+}
2654 
+
2655 
+static void OpBBX0()
2656 
+{
2657 
+	AddCycles(ONE_CYCLE);
2658 
+	Registers.X.W = Registers.Y.W;
2659 
+	SetZN(Registers.X.W);
2660 
+}
2661 
+
2662 
+static void OpBBSlow()
2663 
+{
2664 
+	AddCycles(ONE_CYCLE);
2665 
+
2666 
+	if (CheckIndex())
2667 
+	{
2668 
+		Registers.XL = Registers.YL;
2669 
+		SetZN(Registers.XL);
2670 
+	}
2671 
+	else
2672 
+	{
2673 
+		Registers.X.W = Registers.Y.W;
2674 
+		SetZN(Registers.X.W);
2675 
+	}
2676 
+}
2677 
+
2678 
+/* XCE ********************************************************************* */
2679 
+
2680 
+static void OpFB()
2681 
+{
2682 
+	AddCycles(ONE_CYCLE);
2683 
+
2684 
+	uint8_t	A1 = ICPU._Carry;
2685 
+	uint8_t	A2 = Registers.PH;
2686 
+
2687 
+	ICPU._Carry = A2 & 1;
2688 
+	Registers.PH = A1;
2689 
+
2690 
+	if (CheckEmulation())
2691 
+	{
2692 
+		SetFlags(MemoryFlag | IndexFlag);
2693 
+		Registers.SH = 1;
2694 
+	#ifdef DEBUGGER
2695 
+		missing.emulate6502 = 1;
2696 
+	#endif
2697 
+	}
2698 
+
2699 
+	if (CheckIndex())
2700 
+	{
2701 
+		Registers.XH = 0;
2702 
+		Registers.YH = 0;
2703 
+	}
2704 
+
2705 
+	S9xFixCycles();
2706 
+}
2707 
+
2708 
+/* BRK ********************************************************************* */
2709 
+
2710 
+static void Op00()
2711 
+{
2712 
+#ifdef DEBUGGER
2713 
+	if (CPU.Flags & TRACE_FLAG)
2714 
+		S9xTraceMessage("*** BRK");
2715 
+#endif
2716 
+
2717 
+	AddCycles(CPU.MemSpeed);
2718 
+
2719 
+	uint16_t	addr;
2720 
+
2721 
+	if (!CheckEmulation())
2722 
+	{
2723 
+		PushB(Registers.PB);
2724 
+		PushW(Registers.PCw + 1);
2725 
+		S9xPackStatus();
2726 
+		PushB(Registers.PL);
2727 
+		OpenBus = Registers.PL;
2728 
+		ClearDecimal();
2729 
+		SetIRQ();
2730 
+
2731 
+		addr = S9xGetWord(0xFFE6);
2732 
+	}
2733 
+	else
2734 
+	{
2735 
+		PushWE(Registers.PCw + 1);
2736 
+		S9xPackStatus();
2737 
+		PushBE(Registers.PL);
2738 
+		OpenBus = Registers.PL;
2739 
+		ClearDecimal();
2740 
+		SetIRQ();
2741 
+
2742 
+		addr = S9xGetWord(0xFFFE);
2743 
+	}
2744 
+
2745 
+	S9xSetPCBase(addr);
2746 
+	OpenBus = addr >> 8;
2747 
+}
2748 
+
2749 
+/* IRQ ********************************************************************* */
2750 
+
2751 
+void S9xOpcode_IRQ()
2752 
+{
2753 
+#ifdef DEBUGGER
2754 
+	if (CPU.Flags & TRACE_FLAG)
2755 
+	#ifdef SA1_OPCODES
2756 
+		S9xTraceMessage("*** SA1 IRQ");
2757 
+	#else
2758 
+		S9xTraceMessage("*** IRQ");
2759 
+	#endif
2760 
+#endif
2761 
+
2762 
+	// IRQ and NMI do an opcode fetch as their first "IO" cycle.
2763 
+	AddCycles(CPU.MemSpeed + ONE_CYCLE);
2764 
+
2765 
+	if (!CheckEmulation())
2766 
+	{
2767 
+		PushB(Registers.PB);
2768 
+		PushW(Registers.PCw);
2769 
+		S9xPackStatus();
2770 
+		PushB(Registers.PL);
2771 
+		OpenBus = Registers.PL;
2772 
+		ClearDecimal();
2773 
+		SetIRQ();
2774 
+
2775 
+	#ifdef SA1_OPCODES
2776 
+		OpenBus = Memory.FillRAM[0x2208];
2777 
+		AddCycles(2 * SLOW_ONE_CYCLE);
2778 
+		S9xSA1SetPCBase(Memory.FillRAM[0x2207] | (Memory.FillRAM[0x2208] << 8));
2779 
+	#else
2780 
+		if (Settings.SA1 && (Memory.FillRAM[0x2209] & 0x40))
2781 
+		{
2782 
+			OpenBus = Memory.FillRAM[0x220f];
2783 
+			AddCycles(2 * SLOW_ONE_CYCLE);
2784 
+			S9xSetPCBase(Memory.FillRAM[0x220e] | (Memory.FillRAM[0x220f] << 8));
2785 
+		}
2786 
+		else
2787 
+		{
2788 
+			uint16_t	addr = S9xGetWord(0xFFEE);
2789 
+			OpenBus = addr >> 8;
2790 
+			S9xSetPCBase(addr);
2791 
+		}
2792 
+	#endif
2793 
+	}
2794 
+	else
2795 
+	{
2796 
+		PushWE(Registers.PCw);
2797 
+		S9xPackStatus();
2798 
+		PushBE(Registers.PL);
2799 
+		OpenBus = Registers.PL;
2800 
+		ClearDecimal();
2801 
+		SetIRQ();
2802 
+
2803 
+	#ifdef SA1_OPCODES
2804 
+		OpenBus = Memory.FillRAM[0x2208];
2805 
+		AddCycles(2 * SLOW_ONE_CYCLE);
2806 
+		S9xSA1SetPCBase(Memory.FillRAM[0x2207] | (Memory.FillRAM[0x2208] << 8));
2807 
+	#else
2808 
+		if (Settings.SA1 && (Memory.FillRAM[0x2209] & 0x40))
2809 
+		{
2810 
+			OpenBus = Memory.FillRAM[0x220f];
2811 
+			AddCycles(2 * SLOW_ONE_CYCLE);
2812 
+			S9xSetPCBase(Memory.FillRAM[0x220e] | (Memory.FillRAM[0x220f] << 8));
2813 
+		}
2814 
+		else
2815 
+		{
2816 
+			uint16_t	addr = S9xGetWord(0xFFFE);
2817 
+			OpenBus = addr >> 8;
2818 
+			S9xSetPCBase(addr);
2819 
+		}
2820 
+	#endif
2821 
+	}
2822 
+}
2823 
+
2824 
+/* NMI ********************************************************************* */
2825 
+
2826 
+void S9xOpcode_NMI()
2827 
+{
2828 
+#ifdef DEBUGGER
2829 
+	if (CPU.Flags & TRACE_FLAG)
2830 
+	#ifdef SA1_OPCODES
2831 
+		S9xTraceMessage("*** SA1 NMI");
2832 
+	#else
2833 
+		S9xTraceMessage("*** NMI");
2834 
+	#endif
2835 
+#endif
2836 
+
2837 
+	// IRQ and NMI do an opcode fetch as their first "IO" cycle.
2838 
+	AddCycles(CPU.MemSpeed + ONE_CYCLE);
2839 
+
2840 
+	if (!CheckEmulation())
2841 
+	{
2842 
+		PushB(Registers.PB);
2843 
+		PushW(Registers.PCw);
2844 
+		S9xPackStatus();
2845 
+		PushB(Registers.PL);
2846 
+		OpenBus = Registers.PL;
2847 
+		ClearDecimal();
2848 
+		SetIRQ();
2849 
+
2850 
+	#ifdef SA1_OPCODES
2851 
+		OpenBus = Memory.FillRAM[0x2206];
2852 
+		AddCycles(2 * SLOW_ONE_CYCLE);
2853 
+		S9xSA1SetPCBase(Memory.FillRAM[0x2205] | (Memory.FillRAM[0x2206] << 8));
2854 
+	#else
2855 
+		if (Settings.SA1 && (Memory.FillRAM[0x2209] & 0x10))
2856 
+		{
2857 
+			OpenBus = Memory.FillRAM[0x220d];
2858 
+			AddCycles(2 * SLOW_ONE_CYCLE);
2859 
+			S9xSetPCBase(Memory.FillRAM[0x220c] | (Memory.FillRAM[0x220d] << 8));
2860 
+		}
2861 
+		else
2862 
+		{
2863 
+			uint16_t	addr = S9xGetWord(0xFFEA);
2864 
+			OpenBus = addr >> 8;
2865 
+			S9xSetPCBase(addr);
2866 
+		}
2867 
+	#endif
2868 
+	}
2869 
+	else
2870 
+	{
2871 
+		PushWE(Registers.PCw);
2872 
+		S9xPackStatus();
2873 
+		PushBE(Registers.PL);
2874 
+		OpenBus = Registers.PL;
2875 
+		ClearDecimal();
2876 
+		SetIRQ();
2877 
+
2878 
+	#ifdef SA1_OPCODES
2879 
+		OpenBus = Memory.FillRAM[0x2206];
2880 
+		AddCycles(2 * SLOW_ONE_CYCLE);
2881 
+		S9xSA1SetPCBase(Memory.FillRAM[0x2205] | (Memory.FillRAM[0x2206] << 8));
2882 
+	#else
2883 
+		if (Settings.SA1 && (Memory.FillRAM[0x2209] & 0x10))
2884 
+		{
2885 
+			OpenBus = Memory.FillRAM[0x220d];
2886 
+			AddCycles(2 * SLOW_ONE_CYCLE);
2887 
+			S9xSetPCBase(Memory.FillRAM[0x220c] | (Memory.FillRAM[0x220d] << 8));
2888 
+		}
2889 
+		else
2890 
+		{
2891 
+			uint16_t	addr = S9xGetWord(0xFFFA);
2892 
+			OpenBus = addr >> 8;
2893 
+			S9xSetPCBase(addr);
2894 
+		}
2895 
+	#endif
2896 
+	}
2897 
+}
2898 
+
2899 
+/* COP ********************************************************************* */
2900 
+
2901 
+static void Op02()
2902 
+{
2903 
+#ifdef DEBUGGER
2904 
+	if (CPU.Flags & TRACE_FLAG)
2905 
+		S9xTraceMessage("*** COP");
2906 
+#endif
2907 
+
2908 
+	AddCycles(CPU.MemSpeed);
2909 
+
2910 
+	uint16_t	addr;
2911 
+
2912 
+	if (!CheckEmulation())
2913 
+	{
2914 
+		PushB(Registers.PB);
2915 
+		PushW(Registers.PCw + 1);
2916 
+		S9xPackStatus();
2917 
+		PushB(Registers.PL);
2918 
+		OpenBus = Registers.PL;
2919 
+		ClearDecimal();
2920 
+		SetIRQ();
2921 
+
2922 
+		addr = S9xGetWord(0xFFE4);
2923 
+	}
2924 
+	else
2925 
+	{
2926 
+		PushWE(Registers.PCw + 1);
2927 
+		S9xPackStatus();
2928 
+		PushBE(Registers.PL);
2929 
+		OpenBus = Registers.PL;
2930 
+		ClearDecimal();
2931 
+		SetIRQ();
2932 
+
2933 
+		addr = S9xGetWord(0xFFF4);
2934 
+	}
2935 
+
2936 
+	S9xSetPCBase(addr);
2937 
+	OpenBus = addr >> 8;
2938 
+}
2939 
+
2940 
+/* JML ********************************************************************* */
2941 
+
2942 
+static void OpDC()
2943 
+{
2944 
+	S9xSetPCBase(AbsoluteIndirectLong(JUMP));
2945 
+}
2946 
+
2947 
+static void OpDCSlow()
2948 
+{
2949 
+	S9xSetPCBase(AbsoluteIndirectLongSlow(JUMP));
2950 
+}
2951 
+
2952 
+static void Op5C()
2953 
+{
2954 
+	S9xSetPCBase(AbsoluteLong(JUMP));
2955 
+}
2956 
+
2957 
+static void Op5CSlow()
2958 
+{
2959 
+	S9xSetPCBase(AbsoluteLongSlow(JUMP));
2960 
+}
2961 
+
2962 
+/* JMP ********************************************************************* */
2963 
+
2964 
+static void Op4C()
2965 
+{
2966 
+	S9xSetPCBase(ICPU.ShiftedPB + ((uint16_t) Absolute(JUMP)));
2967 
+}
2968 
+
2969 
+static void Op4CSlow()
2970 
+{
2971 
+	S9xSetPCBase(ICPU.ShiftedPB + ((uint16_t) AbsoluteSlow(JUMP)));
2972 
+}
2973 
+
2974 
+static void Op6C()
2975 
+{
2976 
+	S9xSetPCBase(ICPU.ShiftedPB + ((uint16_t) AbsoluteIndirect(JUMP)));
2977 
+}
2978 
+
2979 
+static void Op6CSlow()
2980 
+{
2981 
+	S9xSetPCBase(ICPU.ShiftedPB + ((uint16_t) AbsoluteIndirectSlow(JUMP)));
2982 
+}
2983 
+
2984 
+static void Op7C()
2985 
+{
2986 
+	S9xSetPCBase(ICPU.ShiftedPB + ((uint16_t) AbsoluteIndexedIndirect(JUMP)));
2987 
+}
2988 
+
2989 
+static void Op7CSlow()
2990 
+{
2991 
+	S9xSetPCBase(ICPU.ShiftedPB + ((uint16_t) AbsoluteIndexedIndirectSlow(JUMP)));
2992 
+}
2993 
+
2994 
+/* JSL/RTL ***************************************************************** */
2995 
+
2996 
+static void Op22E1()
2997 
+{
2998 
+	// Note: JSL is a new instruction,
2999 
+	// and so doesn't respect the emu-mode stack bounds.
3000 
+	uint32_t	addr = AbsoluteLong(JSR);
3001 
+	PushB(Registers.PB);
3002 
+	PushW(Registers.PCw - 1);
3003 
+	Registers.SH = 1;
3004 
+	S9xSetPCBase(addr);
3005 
+}
3006 
+
3007 
+static void Op22E0()
3008 
+{
3009 
+	uint32_t	addr = AbsoluteLong(JSR);
3010 
+	PushB(Registers.PB);
3011 
+	PushW(Registers.PCw - 1);
3012 
+	S9xSetPCBase(addr);
3013 
+}
3014 
+
3015 
+static void Op22Slow()
3016 
+{
3017 
+	uint32_t	addr = AbsoluteLongSlow(JSR);
3018 
+	PushB(Registers.PB);
3019 
+	PushW(Registers.PCw - 1);
3020 
+	if (CheckEmulation())
3021 
+		Registers.SH = 1;
3022 
+	S9xSetPCBase(addr);
3023 
+}
3024 
+
3025 
+static void Op6BE1()
3026 
+{
3027 
+	// Note: RTL is a new instruction,
3028 
+	// and so doesn't respect the emu-mode stack bounds.
3029 
+	AddCycles(TWO_CYCLES);
3030 
+	PullW(Registers.PCw);
3031 
+	PullB(Registers.PB);
3032 
+	Registers.SH = 1;
3033 
+	Registers.PCw++;
3034 
+	S9xSetPCBase(Registers.PBPC);
3035 
+}
3036 
+
3037 
+static void Op6BE0()
3038 
+{
3039 
+	AddCycles(TWO_CYCLES);
3040 
+	PullW(Registers.PCw);
3041 
+	PullB(Registers.PB);
3042 
+	Registers.PCw++;
3043 
+	S9xSetPCBase(Registers.PBPC);
3044 
+}
3045 
+
3046 
+static void Op6BSlow()
3047 
+{
3048 
+	AddCycles(TWO_CYCLES);
3049 
+	PullW(Registers.PCw);
3050 
+	PullB(Registers.PB);
3051 
+	if (CheckEmulation())
3052 
+		Registers.SH = 1;
3053 
+	Registers.PCw++;
3054 
+	S9xSetPCBase(Registers.PBPC);
3055 
+}
3056 
+
3057 
+/* JSR/RTS ***************************************************************** */
3058 
+
3059 
+static void Op20E1()
3060 
+{
3061 
+	uint16_t	addr = Absolute(JSR);
3062 
+	AddCycles(ONE_CYCLE);
3063 
+	PushWE(Registers.PCw - 1);
3064 
+	S9xSetPCBase(ICPU.ShiftedPB + addr);
3065 
+}
3066 
+
3067 
+static void Op20E0()
3068 
+{
3069 
+	uint16_t	addr = Absolute(JSR);
3070 
+	AddCycles(ONE_CYCLE);
3071 
+	PushW(Registers.PCw - 1);
3072 
+	S9xSetPCBase(ICPU.ShiftedPB + addr);
3073 
+}
3074 
+
3075 
+static void Op20Slow()
3076 
+{
3077 
+	uint16_t	addr = AbsoluteSlow(JSR);
3078 
+
3079 
+	AddCycles(ONE_CYCLE);
3080 
+
3081 
+	if (CheckEmulation())
3082 
+	{
3083 
+		PushWE(Registers.PCw - 1);
3084 
+	}
3085 
+	else
3086 
+	{
3087 
+		PushW(Registers.PCw - 1);
3088 
+	}
3089 
+
3090 
+	S9xSetPCBase(ICPU.ShiftedPB + addr);
3091 
+}
3092 
+
3093 
+static void OpFCE1()
3094 
+{
3095 
+	// Note: JSR (a,X) is a new instruction,
3096 
+	// and so doesn't respect the emu-mode stack bounds.
3097 
+	uint16_t	addr = AbsoluteIndexedIndirect(JSR);
3098 
+	PushW(Registers.PCw - 1);
3099 
+	Registers.SH = 1;
3100 
+	S9xSetPCBase(ICPU.ShiftedPB + addr);
3101 
+}
3102 
+
3103 
+static void OpFCE0()
3104 
+{
3105 
+	uint16_t	addr = AbsoluteIndexedIndirect(JSR);
3106 
+	PushW(Registers.PCw - 1);
3107 
+	S9xSetPCBase(ICPU.ShiftedPB + addr);
3108 
+}
3109 
+
3110 
+static void OpFCSlow()
3111 
+{
3112 
+	uint16_t	addr = AbsoluteIndexedIndirectSlow(JSR);
3113 
+	PushW(Registers.PCw - 1);
3114 
+	if (CheckEmulation())
3115 
+		Registers.SH = 1;
3116 
+	S9xSetPCBase(ICPU.ShiftedPB + addr);
3117 
+}
3118 
+
3119 
+static void Op60E1()
3120 
+{
3121 
+	AddCycles(TWO_CYCLES);
3122 
+	PullWE(Registers.PCw);
3123 
+	AddCycles(ONE_CYCLE);
3124 
+	Registers.PCw++;
3125 
+	S9xSetPCBase(Registers.PBPC);
3126 
+}
3127 
+
3128 
+static void Op60E0()
3129 
+{
3130 
+	AddCycles(TWO_CYCLES);
3131 
+	PullW(Registers.PCw);
3132 
+	AddCycles(ONE_CYCLE);
3133 
+	Registers.PCw++;
3134 
+	S9xSetPCBase(Registers.PBPC);
3135 
+}
3136 
+
3137 
+static void Op60Slow()
3138 
+{
3139 
+	AddCycles(TWO_CYCLES);
3140 
+
3141 
+	if (CheckEmulation())
3142 
+	{
3143 
+		PullWE(Registers.PCw);
3144 
+	}
3145 
+	else
3146 
+	{
3147 
+		PullW(Registers.PCw);
3148 
+	}
3149 
+
3150 
+	AddCycles(ONE_CYCLE);
3151 
+	Registers.PCw++;
3152 
+	S9xSetPCBase(Registers.PBPC);
3153 
+}
3154 
+
3155 
+/* MVN/MVP ***************************************************************** */
3156 
+
3157 
+static void Op54X1()
3158 
+{
3159 
+	uint32_t	SrcBank;
3160 
+
3161 
+	Registers.DB = Immediate8(NONE);
3162 
+	ICPU.ShiftedDB = Registers.DB << 16;
3163 
+	OpenBus = SrcBank = Immediate8(NONE);
3164 
+
3165 
+	S9xSetByte(OpenBus = S9xGetByte((SrcBank << 16) + Registers.X.W), ICPU.ShiftedDB + Registers.Y.W);
3166 
+
3167 
+	Registers.XL++;
3168 
+	Registers.YL++;
3169 
+	Registers.A.W--;
3170 
+	if (Registers.A.W != 0xffff)
3171 
+		Registers.PCw -= 3;
3172 
+
3173 
+	AddCycles(TWO_CYCLES);
3174 
+}
3175 
+
3176 
+static void Op54X0()
3177 
+{
3178 
+	uint32_t	SrcBank;
3179 
+
3180 
+	Registers.DB = Immediate8(NONE);
3181 
+	ICPU.ShiftedDB = Registers.DB << 16;
3182 
+	OpenBus = SrcBank = Immediate8(NONE);
3183 
+
3184 
+	S9xSetByte(OpenBus = S9xGetByte((SrcBank << 16) + Registers.X.W), ICPU.ShiftedDB + Registers.Y.W);
3185 
+
3186 
+	Registers.X.W++;
3187 
+	Registers.Y.W++;
3188 
+	Registers.A.W--;
3189 
+	if (Registers.A.W != 0xffff)
3190 
+		Registers.PCw -= 3;
3191 
+
3192 
+	AddCycles(TWO_CYCLES);
3193 
+}
3194 
+
3195 
+static void Op54Slow()
3196 
+{
3197 
+	uint32_t	SrcBank;
3198 
+
3199 
+	OpenBus = Registers.DB = Immediate8Slow(NONE);
3200 
+	ICPU.ShiftedDB = Registers.DB << 16;
3201 
+	OpenBus = SrcBank = Immediate8Slow(NONE);
3202 
+
3203 
+	S9xSetByte(OpenBus = S9xGetByte((SrcBank << 16) + Registers.X.W), ICPU.ShiftedDB + Registers.Y.W);
3204 
+
3205 
+	if (CheckIndex())
3206 
+	{
3207 
+		Registers.XL++;
3208 
+		Registers.YL++;
3209 
+	}
3210 
+	else
3211 
+	{
3212 
+		Registers.X.W++;
3213 
+		Registers.Y.W++;
3214 
+	}
3215 
+
3216 
+	Registers.A.W--;
3217 
+	if (Registers.A.W != 0xffff)
3218 
+		Registers.PCw -= 3;
3219 
+
3220 
+	AddCycles(TWO_CYCLES);
3221 
+}
3222 
+
3223 
+static void Op44X1()
3224 
+{
3225 
+	uint32_t	SrcBank;
3226 
+
3227 
+	Registers.DB = Immediate8(NONE);
3228 
+	ICPU.ShiftedDB = Registers.DB << 16;
3229 
+	OpenBus = SrcBank = Immediate8(NONE);
3230 
+
3231 
+	S9xSetByte(OpenBus = S9xGetByte((SrcBank << 16) + Registers.X.W), ICPU.ShiftedDB + Registers.Y.W);
3232 
+
3233 
+	Registers.XL--;
3234 
+	Registers.YL--;
3235 
+	Registers.A.W--;
3236 
+	if (Registers.A.W != 0xffff)
3237 
+		Registers.PCw -= 3;
3238 
+
3239 
+	AddCycles(TWO_CYCLES);
3240 
+}
3241 
+
3242 
+static void Op44X0()
3243 
+{
3244 
+	uint32_t	SrcBank;
3245 
+
3246 
+	Registers.DB = Immediate8(NONE);
3247 
+	ICPU.ShiftedDB = Registers.DB << 16;
3248 
+	OpenBus = SrcBank = Immediate8(NONE);
3249 
+
3250 
+	S9xSetByte(OpenBus = S9xGetByte((SrcBank << 16) + Registers.X.W), ICPU.ShiftedDB + Registers.Y.W);
3251 
+
3252 
+	Registers.X.W--;
3253 
+	Registers.Y.W--;
3254 
+	Registers.A.W--;
3255 
+	if (Registers.A.W != 0xffff)
3256 
+		Registers.PCw -= 3;
3257 
+
3258 
+	AddCycles(TWO_CYCLES);
3259 
+}
3260 
+
3261 
+static void Op44Slow()
3262 
+{
3263 
+	uint32_t	SrcBank;
3264 
+
3265 
+	OpenBus = Registers.DB = Immediate8Slow(NONE);
3266 
+	ICPU.ShiftedDB = Registers.DB << 16;
3267 
+	OpenBus = SrcBank = Immediate8Slow(NONE);
3268 
+
3269 
+	S9xSetByte(OpenBus = S9xGetByte((SrcBank << 16) + Registers.X.W), ICPU.ShiftedDB + Registers.Y.W);
3270 
+
3271 
+	if (CheckIndex())
3272 
+	{
3273 
+		Registers.XL--;
3274 
+		Registers.YL--;
3275 
+	}
3276 
+	else
3277 
+	{
3278 
+		Registers.X.W--;
3279 
+		Registers.Y.W--;
3280 
+	}
3281 
+
3282 
+	Registers.A.W--;
3283 
+	if (Registers.A.W != 0xffff)
3284 
+		Registers.PCw -= 3;
3285 
+
3286 
+	AddCycles(TWO_CYCLES);
3287 
+}
3288 
+
3289 
+/* REP/SEP ***************************************************************** */
3290 
+
3291 
+static void OpC2()
3292 
+{
3293 
+	uint8_t	Work8 = ~Immediate8(READ);
3294 
+	Registers.PL &= Work8;
3295 
+	ICPU._Carry &= Work8;
3296 
+	ICPU._Overflow &= (Work8 >> 6);
3297 
+	ICPU._Negative &= Work8;
3298 
+	ICPU._Zero |= ~Work8 & Zero;
3299 
+
3300 
+	AddCycles(ONE_CYCLE);
3301 
+
3302 
+	if (CheckEmulation())
3303 
+	{
3304 
+		SetFlags(MemoryFlag | IndexFlag);
3305 
+	#ifdef DEBUGGER
3306 
+		missing.emulate6502 = 1;
3307 
+	#endif
3308 
+	}
3309 
+
3310 
+	if (CheckIndex())
3311 
+	{
3312 
+		Registers.XH = 0;
3313 
+		Registers.YH = 0;
3314 
+	}
3315 
+
3316 
+	S9xFixCycles();
3317 
+	CHECK_FOR_IRQ();
3318 
+}
3319 
+
3320 
+static void OpC2Slow()
3321 
+{
3322 
+	uint8_t	Work8 = ~Immediate8Slow(READ);
3323 
+	Registers.PL &= Work8;
3324 
+	ICPU._Carry &= Work8;
3325 
+	ICPU._Overflow &= (Work8 >> 6);
3326 
+	ICPU._Negative &= Work8;
3327 
+	ICPU._Zero |= ~Work8 & Zero;
3328 
+
3329 
+	AddCycles(ONE_CYCLE);
3330 
+
3331 
+	if (CheckEmulation())
3332 
+	{
3333 
+		SetFlags(MemoryFlag | IndexFlag);
3334 
+	#ifdef DEBUGGER
3335 
+		missing.emulate6502 = 1;
3336 
+	#endif
3337 
+	}
3338 
+
3339 
+	if (CheckIndex())
3340 
+	{
3341 
+		Registers.XH = 0;
3342 
+		Registers.YH = 0;
3343 
+	}
3344 
+
3345 
+	S9xFixCycles();
3346 
+	CHECK_FOR_IRQ();
3347 
+}
3348 
+
3349 
+static void OpE2()
3350 
+{
3351 
+	uint8_t	Work8 = Immediate8(READ);
3352 
+	Registers.PL |= Work8;
3353 
+	ICPU._Carry |= Work8 & 1;
3354 
+	ICPU._Overflow |= (Work8 >> 6) & 1;
3355 
+	ICPU._Negative |= Work8;
3356 
+	if (Work8 & Zero)
3357 
+		ICPU._Zero = 0;
3358 
+
3359 
+	AddCycles(ONE_CYCLE);
3360 
+
3361 
+	if (CheckEmulation())
3362 
+	{
3363 
+		SetFlags(MemoryFlag | IndexFlag);
3364 
+	#ifdef DEBUGGER
3365 
+		missing.emulate6502 = 1;
3366 
+	#endif
3367 
+	}
3368 
+
3369 
+	if (CheckIndex())
3370 
+	{
3371 
+		Registers.XH = 0;
3372 
+		Registers.YH = 0;
3373 
+	}
3374 
+
3375 
+	S9xFixCycles();
3376 
+}
3377 
+
3378 
+static void OpE2Slow()
3379 
+{
3380 
+	uint8_t	Work8 = Immediate8Slow(READ);
3381 
+	Registers.PL |= Work8;
3382 
+	ICPU._Carry |= Work8 & 1;
3383 
+	ICPU._Overflow |= (Work8 >> 6) & 1;
3384 
+	ICPU._Negative |= Work8;
3385 
+	if (Work8 & Zero)
3386 
+		ICPU._Zero = 0;
3387 
+
3388 
+	AddCycles(ONE_CYCLE);
3389 
+
3390 
+	if (CheckEmulation())
3391 
+	{
3392 
+		SetFlags(MemoryFlag | IndexFlag);
3393 
+	#ifdef DEBUGGER
3394 
+		missing.emulate6502 = 1;
3395 
+	#endif
3396 
+	}
3397 
+
3398 
+	if (CheckIndex())
3399 
+	{
3400 
+		Registers.XH = 0;
3401 
+		Registers.YH = 0;
3402 
+	}
3403 
+
3404 
+	S9xFixCycles();
3405 
+}
3406 
+
3407 
+/* XBA ********************************************************************* */
3408 
+
3409 
+static void OpEB()
3410 
+{
3411 
+	uint8_t	Work8 = Registers.AL;
3412 
+	Registers.AL = Registers.AH;
3413 
+	Registers.AH = Work8;
3414 
+	SetZN(Registers.AL);
3415 
+	AddCycles(TWO_CYCLES);
3416 
+}
3417 
+
3418 
+/* RTI ********************************************************************* */
3419 
+
3420 
+static void Op40Slow()
3421 
+{
3422 
+	AddCycles(TWO_CYCLES);
3423 
+
3424 
+	if (!CheckEmulation())
3425 
+	{
3426 
+		PullB(Registers.PL);
3427 
+		S9xUnpackStatus();
3428 
+		PullW(Registers.PCw);
3429 
+		PullB(Registers.PB);
3430 
+		OpenBus = Registers.PB;
3431 
+		ICPU.ShiftedPB = Registers.PB << 16;
3432 
+	}
3433 
+	else
3434 
+	{
3435 
+		PullBE(Registers.PL);
3436 
+		S9xUnpackStatus();
3437 
+		PullWE(Registers.PCw);
3438 
+		OpenBus = Registers.PCh;
3439 
+		SetFlags(MemoryFlag | IndexFlag);
3440 
+	#ifdef DEBUGGER
3441 
+		missing.emulate6502 = 1;
3442 
+	#endif
3443 
+	}
3444 
+
3445 
+	S9xSetPCBase(Registers.PBPC);
3446 
+
3447 
+	if (CheckIndex())
3448 
+	{
3449 
+		Registers.XH = 0;
3450 
+		Registers.YH = 0;
3451 
+	}
3452 
+
3453 
+	S9xFixCycles();
3454 
+	CHECK_FOR_IRQ();
3455 
+}
3456 
+
3457 
+/* STP/WAI ***************************************************************** */
3458 
+
3459 
+// WAI
3460 
+static void OpCB()
3461 
+{
3462 
+#ifdef SA1_OPCODES
3463 
+	SA1.WaitingForInterrupt = true;
3464 
+	Registers.PCw--;
3465 
+	AddCycles(TWO_CYCLES);
3466 
+#else
3467 
+	CPU.WaitingForInterrupt = true;
3468 
+	Registers.PCw--;
3469 
+	AddCycles(TWO_CYCLES);
3470 
+#endif
3471 
+}
3472 
+
3473 
+// STP
3474 
+static void OpDB()
3475 
+{
3476 
+	Registers.PCw--;
3477 
+	CPU.Flags |= DEBUG_MODE_FLAG | HALTED_FLAG;
3478 
+}
3479 
+
3480 
+/* WDM (Reserved S9xOpcode) ************************************************ */
3481 
+
3482 
+#ifdef DEBUGGER
3483 
+extern FILE	*trace, *trace2;
3484 
+#endif
3485 
+
3486 
+static void Op42()
3487 
+{
3488 
+#ifdef DEBUGGER
3489 
+	uint8_t	byte = (uint8_t) S9xGetWord(Registers.PBPC);
3490 
+#else
3491 
+	S9xGetWord(Registers.PBPC);
3492 
+#endif
3493 
+	Registers.PCw++;
3494 
+
3495 
+#ifdef DEBUGGER
3496 
+	// Hey, let's use this to trigger debug modes.
3497 
+	switch (byte)
3498 
+	{
3499 
+		case 0xdb: // "STP" = Enter debug mode
3500 
+			CPU.Flags |= DEBUG_MODE_FLAG;
3501 
+			break;
3502 
+
3503 
+	#ifndef SA1_OPCODES
3504 
+		case 0xe2: // "SEP" = Trace on
3505 
+			if (!(CPU.Flags & TRACE_FLAG))
3506 
+			{
3507 
+				char	buf[25];
3508 
+				CPU.Flags |= TRACE_FLAG;
3509 
+				snprintf(buf, 25, "WDM trace on at $%02X:%04X", Registers.PB, Registers.PCw);
3510 
+				S9xMessage(S9X_DEBUG, S9X_DEBUG_OUTPUT, buf);
3511 
+				if (trace != NULL)
3512 
+					fclose(trace);
3513 
+				ENSURE_TRACE_OPEN(trace, "WDMtrace.log", "ab")
3514 
+			}
3515 
+
3516 
+			break;
3517 
+
3518 
+		case 0xc2: // "REP" = Trace off
3519 
+			if (CPU.Flags & TRACE_FLAG)
3520 
+			{
3521 
+				char	buf[26];
3522 
+				CPU.Flags &= ~TRACE_FLAG;
3523 
+				snprintf(buf, 26, "WDM trace off at $%02X:%04X", Registers.PB, Registers.PCw);
3524 
+				S9xMessage(S9X_DEBUG, S9X_DEBUG_OUTPUT, buf);
3525 
+				if (trace != NULL)
3526 
+					fclose(trace);
3527 
+				trace = NULL;
3528 
+			}
3529 
+
3530 
+			break;
3531 
+	#endif
3532 
+
3533 
+		case 0x42: // "WDM" = Snapshot
3534 
+			char	filename[PATH_MAX + 1], drive[_MAX_DRIVE + 1], dir[_MAX_DIR + 1], def[PATH_MAX + 1], ext[_MAX_EXT + 1];
3535 
+
3536 
+			_splitpath(Memory.ROMFilename, drive, dir, def, ext);
3537 
+			snprintf(filename, PATH_MAX, "%s%s%s-%06X.wdm", S9xGetDirectory(SNAPSHOT_DIR), SLASH_STR, def, Registers.PBPC & 0xffffff);
3538 
+			sprintf(def, "WDM Snapshot at $%02X:%04X: %s", Registers.PB, Registers.PCw, filename);
3539 
+			S9xMessage(S9X_DEBUG, S9X_DEBUG_OUTPUT, def);
3540 
+			S9xFreezeGame(filename);
3541 
+
3542 
+			break;
3543 
+
3544 
+		default:
3545 
+			break;
3546 
+	}
3547 
+#endif
3548 
+}
3549 
+
3550 
+/* CPU-S9xOpcodes Definitions ************************************************/
3551 
+
3552 
+struct SOpcodes S9xOpcodesM1X1[256] =
3553 
+{
3554 
+	{ Op00 },        { Op01E0M1 },    { Op02 },        { Op03M1 },      { Op04M1 },
3555 
+	{ Op05M1 },      { Op06M1 },      { Op07M1 },      { Op08E0 },      { Op09M1 },
3556 
+	{ Op0AM1 },      { Op0BE0 },      { Op0CM1 },      { Op0DM1 },      { Op0EM1 },
3557 
+	{ Op0FM1 },      { Op10E0 },      { Op11E0M1X1 },  { Op12E0M1 },    { Op13M1 },
3558 
+	{ Op14M1 },      { Op15E0M1 },    { Op16E0M1 },    { Op17M1 },      { Op18 },
3559 
+	{ Op19M1X1 },    { Op1AM1 },      { Op1B },        { Op1CM1 },      { Op1DM1X1 },
3560 
+	{ Op1EM1X1 },    { Op1FM1 },      { Op20E0 },      { Op21E0M1 },    { Op22E0 },
3561 
+	{ Op23M1 },      { Op24M1 },      { Op25M1 },      { Op26M1 },      { Op27M1 },
3562 
+	{ Op28E0 },      { Op29M1 },      { Op2AM1 },      { Op2BE0 },      { Op2CM1 },
3563 
+	{ Op2DM1 },      { Op2EM1 },      { Op2FM1 },      { Op30E0 },      { Op31E0M1X1 },
3564 
+	{ Op32E0M1 },    { Op33M1 },      { Op34E0M1 },    { Op35E0M1 },    { Op36E0M1 },
3565 
+	{ Op37M1 },      { Op38 },        { Op39M1X1 },    { Op3AM1 },      { Op3B },
3566 
+	{ Op3CM1X1 },    { Op3DM1X1 },    { Op3EM1X1 },    { Op3FM1 },      { Op40Slow },
3567 
+	{ Op41E0M1 },    { Op42 },        { Op43M1 },      { Op44X1 },      { Op45M1 },
3568 
+	{ Op46M1 },      { Op47M1 },      { Op48E0M1 },    { Op49M1 },      { Op4AM1 },
3569 
+	{ Op4BE0 },      { Op4C },        { Op4DM1 },      { Op4EM1 },      { Op4FM1 },
3570 
+	{ Op50E0 },      { Op51E0M1X1 },  { Op52E0M1 },    { Op53M1 },      { Op54X1 },
3571 
+	{ Op55E0M1 },    { Op56E0M1 },    { Op57M1 },      { Op58 },        { Op59M1X1 },
3572 
+	{ Op5AE0X1 },    { Op5B },        { Op5C },        { Op5DM1X1 },    { Op5EM1X1 },
3573 
+	{ Op5FM1 },      { Op60E0 },      { Op61E0M1 },    { Op62E0 },      { Op63M1 },
3574 
+	{ Op64M1 },      { Op65M1 },      { Op66M1 },      { Op67M1 },      { Op68E0M1 },
3575 
+	{ Op69M1 },      { Op6AM1 },      { Op6BE0 },      { Op6C },        { Op6DM1 },
3576 
+	{ Op6EM1 },      { Op6FM1 },      { Op70E0 },      { Op71E0M1X1 },  { Op72E0M1 },
3577 
+	{ Op73M1 },      { Op74E0M1 },    { Op75E0M1 },    { Op76E0M1 },    { Op77M1 },
3578 
+	{ Op78 },        { Op79M1X1 },    { Op7AE0X1 },    { Op7B },        { Op7C },
3579 
+	{ Op7DM1X1 },    { Op7EM1X1 },    { Op7FM1 },      { Op80E0 },      { Op81E0M1 },
3580 
+	{ Op82 },        { Op83M1 },      { Op84X1 },      { Op85M1 },      { Op86X1 },
3581 
+	{ Op87M1 },      { Op88X1 },      { Op89M1 },      { Op8AM1 },      { Op8BE0 },
3582 
+	{ Op8CX1 },      { Op8DM1 },      { Op8EX1 },      { Op8FM1 },      { Op90E0 },
3583 
+	{ Op91E0M1X1 },  { Op92E0M1 },    { Op93M1 },      { Op94E0X1 },    { Op95E0M1 },
3584 
+	{ Op96E0X1 },    { Op97M1 },      { Op98M1 },      { Op99M1X1 },    { Op9A },
3585 
+	{ Op9BX1 },      { Op9CM1 },      { Op9DM1X1 },    { Op9EM1X1 },    { Op9FM1 },
3586 
+	{ OpA0X1 },      { OpA1E0M1 },    { OpA2X1 },      { OpA3M1 },      { OpA4X1 },
3587 
+	{ OpA5M1 },      { OpA6X1 },      { OpA7M1 },      { OpA8X1 },      { OpA9M1 },
3588 
+	{ OpAAX1 },      { OpABE0 },      { OpACX1 },      { OpADM1 },      { OpAEX1 },
3589 
+	{ OpAFM1 },      { OpB0E0 },      { OpB1E0M1X1 },  { OpB2E0M1 },    { OpB3M1 },
3590 
+	{ OpB4E0X1 },    { OpB5E0M1 },    { OpB6E0X1 },    { OpB7M1 },      { OpB8 },
3591 
+	{ OpB9M1X1 },    { OpBAX1 },      { OpBBX1 },      { OpBCX1 },      { OpBDM1X1 },
3592 
+	{ OpBEX1 },      { OpBFM1 },      { OpC0X1 },      { OpC1E0M1 },    { OpC2 },
3593 
+	{ OpC3M1 },      { OpC4X1 },      { OpC5M1 },      { OpC6M1 },      { OpC7M1 },
3594 
+	{ OpC8X1 },      { OpC9M1 },      { OpCAX1 },      { OpCB },        { OpCCX1 },
3595 
+	{ OpCDM1 },      { OpCEM1 },      { OpCFM1 },      { OpD0E0 },      { OpD1E0M1X1 },
3596 
+	{ OpD2E0M1 },    { OpD3M1 },      { OpD4E0 },      { OpD5E0M1 },    { OpD6E0M1 },
3597 
+	{ OpD7M1 },      { OpD8 },        { OpD9M1X1 },    { OpDAE0X1 },    { OpDB },
3598 
+	{ OpDC },        { OpDDM1X1 },    { OpDEM1X1 },    { OpDFM1 },      { OpE0X1 },
3599 
+	{ OpE1E0M1 },    { OpE2 },        { OpE3M1 },      { OpE4X1 },      { OpE5M1 },
3600 
+	{ OpE6M1 },      { OpE7M1 },      { OpE8X1 },      { OpE9M1 },      { OpEA },
3601 
+	{ OpEB },        { OpECX1 },      { OpEDM1 },      { OpEEM1 },      { OpEFM1 },
3602 
+	{ OpF0E0 },      { OpF1E0M1X1 },  { OpF2E0M1 },    { OpF3M1 },      { OpF4E0 },
3603 
+	{ OpF5E0M1 },    { OpF6E0M1 },    { OpF7M1 },      { OpF8 },        { OpF9M1X1 },
3604 
+	{ OpFAE0X1 },    { OpFB },        { OpFCE0 },      { OpFDM1X1 },    { OpFEM1X1 },
3605 
+	{ OpFFM1 }
3606 
+};
3607 
+
3608 
+struct SOpcodes S9xOpcodesE1[256] =
3609 
+{
3610 
+	{ Op00 },        { Op01E1 },      { Op02 },        { Op03M1 },      { Op04M1 },
3611 
+	{ Op05M1 },      { Op06M1 },      { Op07M1 },      { Op08E1 },      { Op09M1 },
3612 
+	{ Op0AM1 },      { Op0BE1 },      { Op0CM1 },      { Op0DM1 },      { Op0EM1 },
3613 
+	{ Op0FM1 },      { Op10E1 },      { Op11E1 },      { Op12E1 },      { Op13M1 },
3614 
+	{ Op14M1 },      { Op15E1 },      { Op16E1 },      { Op17M1 },      { Op18 },
3615 
+	{ Op19M1X1 },    { Op1AM1 },      { Op1B },        { Op1CM1 },      { Op1DM1X1 },
3616 
+	{ Op1EM1X1 },    { Op1FM1 },      { Op20E1 },      { Op21E1 },      { Op22E1 },
3617 
+	{ Op23M1 },      { Op24M1 },      { Op25M1 },      { Op26M1 },      { Op27M1 },
3618 
+	{ Op28E1 },      { Op29M1 },      { Op2AM1 },      { Op2BE1 },      { Op2CM1 },
3619 
+	{ Op2DM1 },      { Op2EM1 },      { Op2FM1 },      { Op30E1 },      { Op31E1 },
3620 
+	{ Op32E1 },      { Op33M1 },      { Op34E1 },      { Op35E1 },      { Op36E1 },
3621 
+	{ Op37M1 },      { Op38 },        { Op39M1X1 },    { Op3AM1 },      { Op3B },
3622 
+	{ Op3CM1X1 },    { Op3DM1X1 },    { Op3EM1X1 },    { Op3FM1 },      { Op40Slow },
3623 
+	{ Op41E1 },      { Op42 },        { Op43M1 },      { Op44X1 },      { Op45M1 },
3624 
+	{ Op46M1 },      { Op47M1 },      { Op48E1 },      { Op49M1 },      { Op4AM1 },
3625 
+	{ Op4BE1 },      { Op4C },        { Op4DM1 },      { Op4EM1 },      { Op4FM1 },
3626 
+	{ Op50E1 },      { Op51E1 },      { Op52E1 },      { Op53M1 },      { Op54X1 },
3627 
+	{ Op55E1 },      { Op56E1 },      { Op57M1 },      { Op58 },        { Op59M1X1 },
3628 
+	{ Op5AE1 },      { Op5B },        { Op5C },        { Op5DM1X1 },    { Op5EM1X1 },
3629 
+	{ Op5FM1 },      { Op60E1 },      { Op61E1 },      { Op62E1 },      { Op63M1 },
3630 
+	{ Op64M1 },      { Op65M1 },      { Op66M1 },      { Op67M1 },      { Op68E1 },
3631 
+	{ Op69M1 },      { Op6AM1 },      { Op6BE1 },      { Op6C },        { Op6DM1 },
3632 
+	{ Op6EM1 },      { Op6FM1 },      { Op70E1 },      { Op71E1 },      { Op72E1 },
3633 
+	{ Op73M1 },      { Op74E1 },      { Op75E1 },      { Op76E1 },      { Op77M1 },
3634 
+	{ Op78 },        { Op79M1X1 },    { Op7AE1 },      { Op7B },        { Op7C },
3635 
+	{ Op7DM1X1 },    { Op7EM1X1 },    { Op7FM1 },      { Op80E1 },      { Op81E1 },
3636 
+	{ Op82 },        { Op83M1 },      { Op84X1 },      { Op85M1 },      { Op86X1 },
3637 
+	{ Op87M1 },      { Op88X1 },      { Op89M1 },      { Op8AM1 },      { Op8BE1 },
3638 
+	{ Op8CX1 },      { Op8DM1 },      { Op8EX1 },      { Op8FM1 },      { Op90E1 },
3639 
+	{ Op91E1 },      { Op92E1 },      { Op93M1 },      { Op94E1 },      { Op95E1 },
3640 
+	{ Op96E1 },      { Op97M1 },      { Op98M1 },      { Op99M1X1 },    { Op9A },
3641 
+	{ Op9BX1 },      { Op9CM1 },      { Op9DM1X1 },    { Op9EM1X1 },    { Op9FM1 },
3642 
+	{ OpA0X1 },      { OpA1E1 },      { OpA2X1 },      { OpA3M1 },      { OpA4X1 },
3643 
+	{ OpA5M1 },      { OpA6X1 },      { OpA7M1 },      { OpA8X1 },      { OpA9M1 },
3644 
+	{ OpAAX1 },      { OpABE1 },      { OpACX1 },      { OpADM1 },      { OpAEX1 },
3645 
+	{ OpAFM1 },      { OpB0E1 },      { OpB1E1 },      { OpB2E1 },      { OpB3M1 },
3646 
+	{ OpB4E1 },      { OpB5E1 },      { OpB6E1 },      { OpB7M1 },      { OpB8 },
3647 
+	{ OpB9M1X1 },    { OpBAX1 },      { OpBBX1 },      { OpBCX1 },      { OpBDM1X1 },
3648 
+	{ OpBEX1 },      { OpBFM1 },      { OpC0X1 },      { OpC1E1 },      { OpC2 },
3649 
+	{ OpC3M1 },      { OpC4X1 },      { OpC5M1 },      { OpC6M1 },      { OpC7M1 },
3650 
+	{ OpC8X1 },      { OpC9M1 },      { OpCAX1 },      { OpCB },        { OpCCX1 },
3651 
+	{ OpCDM1 },      { OpCEM1 },      { OpCFM1 },      { OpD0E1 },      { OpD1E1 },
3652 
+	{ OpD2E1 },      { OpD3M1 },      { OpD4E1 },      { OpD5E1 },      { OpD6E1 },
3653 
+	{ OpD7M1 },      { OpD8 },        { OpD9M1X1 },    { OpDAE1 },      { OpDB },
3654 
+	{ OpDC },        { OpDDM1X1 },    { OpDEM1X1 },    { OpDFM1 },      { OpE0X1 },
3655 
+	{ OpE1E1 },      { OpE2 },        { OpE3M1 },      { OpE4X1 },      { OpE5M1 },
3656 
+	{ OpE6M1 },      { OpE7M1 },      { OpE8X1 },      { OpE9M1 },      { OpEA },
3657 
+	{ OpEB },        { OpECX1 },      { OpEDM1 },      { OpEEM1 },      { OpEFM1 },
3658 
+	{ OpF0E1 },      { OpF1E1 },      { OpF2E1 },      { OpF3M1 },      { OpF4E1 },
3659 
+	{ OpF5E1 },      { OpF6E1 },      { OpF7M1 },      { OpF8 },        { OpF9M1X1 },
3660 
+	{ OpFAE1 },      { OpFB },        { OpFCE1 },      { OpFDM1X1 },    { OpFEM1X1 },
3661 
+	{ OpFFM1 }
3662 
+};
3663 
+
3664 
+struct SOpcodes S9xOpcodesM1X0[256] =
3665 
+{
3666 
+	{ Op00 },        { Op01E0M1 },    { Op02 },        { Op03M1 },      { Op04M1 },
3667 
+	{ Op05M1 },      { Op06M1 },      { Op07M1 },      { Op08E0 },      { Op09M1 },
3668 
+	{ Op0AM1 },      { Op0BE0 },      { Op0CM1 },      { Op0DM1 },      { Op0EM1 },
3669 
+	{ Op0FM1 },      { Op10E0 },      { Op11E0M1X0 },  { Op12E0M1 },    { Op13M1 },
3670 
+	{ Op14M1 },      { Op15E0M1 },    { Op16E0M1 },    { Op17M1 },      { Op18 },
3671 
+	{ Op19M1X0 },    { Op1AM1 },      { Op1B },        { Op1CM1 },      { Op1DM1X0 },
3672 
+	{ Op1EM1X0 },    { Op1FM1 },      { Op20E0 },      { Op21E0M1 },    { Op22E0 },
3673 
+	{ Op23M1 },      { Op24M1 },      { Op25M1 },      { Op26M1 },      { Op27M1 },
3674 
+	{ Op28E0 },      { Op29M1 },      { Op2AM1 },      { Op2BE0 },      { Op2CM1 },
3675 
+	{ Op2DM1 },      { Op2EM1 },      { Op2FM1 },      { Op30E0 },      { Op31E0M1X0 },
3676 
+	{ Op32E0M1 },    { Op33M1 },      { Op34E0M1 },    { Op35E0M1 },    { Op36E0M1 },
3677 
+	{ Op37M1 },      { Op38 },        { Op39M1X0 },    { Op3AM1 },      { Op3B },
3678 
+	{ Op3CM1X0 },    { Op3DM1X0 },    { Op3EM1X0 },    { Op3FM1 },      { Op40Slow },
3679 
+	{ Op41E0M1 },    { Op42 },        { Op43M1 },      { Op44X0 },      { Op45M1 },
3680 
+	{ Op46M1 },      { Op47M1 },      { Op48E0M1 },    { Op49M1 },      { Op4AM1 },
3681 
+	{ Op4BE0 },      { Op4C },        { Op4DM1 },      { Op4EM1 },      { Op4FM1 },
3682 
+	{ Op50E0 },      { Op51E0M1X0 },  { Op52E0M1 },    { Op53M1 },      { Op54X0 },
3683 
+	{ Op55E0M1 },    { Op56E0M1 },    { Op57M1 },      { Op58 },        { Op59M1X0 },
3684 
+	{ Op5AE0X0 },    { Op5B },        { Op5C },        { Op5DM1X0 },    { Op5EM1X0 },
3685 
+	{ Op5FM1 },      { Op60E0 },      { Op61E0M1 },    { Op62E0 },      { Op63M1 },
3686 
+	{ Op64M1 },      { Op65M1 },      { Op66M1 },      { Op67M1 },      { Op68E0M1 },
3687 
+	{ Op69M1 },      { Op6AM1 },      { Op6BE0 },      { Op6C },        { Op6DM1 },
3688 
+	{ Op6EM1 },      { Op6FM1 },      { Op70E0 },      { Op71E0M1X0 },  { Op72E0M1 },
3689 
+	{ Op73M1 },      { Op74E0M1 },    { Op75E0M1 },    { Op76E0M1 },    { Op77M1 },
3690 
+	{ Op78 },        { Op79M1X0 },    { Op7AE0X0 },    { Op7B },        { Op7C },
3691 
+	{ Op7DM1X0 },    { Op7EM1X0 },    { Op7FM1 },      { Op80E0 },      { Op81E0M1 },
3692 
+	{ Op82 },        { Op83M1 },      { Op84X0 },      { Op85M1 },      { Op86X0 },
3693 
+	{ Op87M1 },      { Op88X0 },      { Op89M1 },      { Op8AM1 },      { Op8BE0 },
3694 
+	{ Op8CX0 },      { Op8DM1 },      { Op8EX0 },      { Op8FM1 },      { Op90E0 },
3695 
+	{ Op91E0M1X0 },  { Op92E0M1 },    { Op93M1 },      { Op94E0X0 },    { Op95E0M1 },
3696 
+	{ Op96E0X0 },    { Op97M1 },      { Op98M1 },      { Op99M1X0 },    { Op9A },
3697 
+	{ Op9BX0 },      { Op9CM1 },      { Op9DM1X0 },    { Op9EM1X0 },    { Op9FM1 },
3698 
+	{ OpA0X0 },      { OpA1E0M1 },    { OpA2X0 },      { OpA3M1 },      { OpA4X0 },
3699 
+	{ OpA5M1 },      { OpA6X0 },      { OpA7M1 },      { OpA8X0 },      { OpA9M1 },
3700 
+	{ OpAAX0 },      { OpABE0 },      { OpACX0 },      { OpADM1 },      { OpAEX0 },
3701 
+	{ OpAFM1 },      { OpB0E0 },      { OpB1E0M1X0 },  { OpB2E0M1 },    { OpB3M1 },
3702 
+	{ OpB4E0X0 },    { OpB5E0M1 },    { OpB6E0X0 },    { OpB7M1 },      { OpB8 },
3703 
+	{ OpB9M1X0 },    { OpBAX0 },      { OpBBX0 },      { OpBCX0 },      { OpBDM1X0 },
3704 
+	{ OpBEX0 },      { OpBFM1 },      { OpC0X0 },      { OpC1E0M1 },    { OpC2 },
3705 
+	{ OpC3M1 },      { OpC4X0 },      { OpC5M1 },      { OpC6M1 },      { OpC7M1 },
3706 
+	{ OpC8X0 },      { OpC9M1 },      { OpCAX0 },      { OpCB },        { OpCCX0 },
3707 
+	{ OpCDM1 },      { OpCEM1 },      { OpCFM1 },      { OpD0E0 },      { OpD1E0M1X0 },
3708 
+	{ OpD2E0M1 },    { OpD3M1 },      { OpD4E0 },      { OpD5E0M1 },    { OpD6E0M1 },
3709 
+	{ OpD7M1 },      { OpD8 },        { OpD9M1X0 },    { OpDAE0X0 },    { OpDB },
3710 
+	{ OpDC },        { OpDDM1X0 },    { OpDEM1X0 },    { OpDFM1 },      { OpE0X0 },
3711 
+	{ OpE1E0M1 },    { OpE2 },        { OpE3M1 },      { OpE4X0 },      { OpE5M1 },
3712 
+	{ OpE6M1 },      { OpE7M1 },      { OpE8X0 },      { OpE9M1 },      { OpEA },
3713 
+	{ OpEB },        { OpECX0 },      { OpEDM1 },      { OpEEM1 },      { OpEFM1 },
3714 
+	{ OpF0E0 },      { OpF1E0M1X0 },  { OpF2E0M1 },    { OpF3M1 },      { OpF4E0 },
3715 
+	{ OpF5E0M1 },    { OpF6E0M1 },    { OpF7M1 },      { OpF8 },        { OpF9M1X0 },
3716 
+	{ OpFAE0X0 },    { OpFB },        { OpFCE0 },      { OpFDM1X0 },    { OpFEM1X0 },
3717 
+	{ OpFFM1 }
3718 
+};
3719 
+
3720 
+struct SOpcodes S9xOpcodesM0X0[256] =
3721 
+{
3722 
+	{ Op00 },        { Op01E0M0 },    { Op02 },        { Op03M0 },      { Op04M0 },
3723 
+	{ Op05M0 },      { Op06M0 },      { Op07M0 },      { Op08E0 },      { Op09M0 },
3724 
+	{ Op0AM0 },      { Op0BE0 },      { Op0CM0 },      { Op0DM0 },      { Op0EM0 },
3725 
+	{ Op0FM0 },      { Op10E0 },      { Op11E0M0X0 },  { Op12E0M0 },    { Op13M0 },
3726 
+	{ Op14M0 },      { Op15E0M0 },    { Op16E0M0 },    { Op17M0 },      { Op18 },
3727 
+	{ Op19M0X0 },    { Op1AM0 },      { Op1B },        { Op1CM0 },      { Op1DM0X0 },
3728 
+	{ Op1EM0X0 },    { Op1FM0 },      { Op20E0 },      { Op21E0M0 },    { Op22E0 },
3729 
+	{ Op23M0 },      { Op24M0 },      { Op25M0 },      { Op26M0 },      { Op27M0 },
3730 
+	{ Op28E0 },      { Op29M0 },      { Op2AM0 },      { Op2BE0 },      { Op2CM0 },
3731 
+	{ Op2DM0 },      { Op2EM0 },      { Op2FM0 },      { Op30E0 },      { Op31E0M0X0 },
3732 
+	{ Op32E0M0 },    { Op33M0 },      { Op34E0M0 },    { Op35E0M0 },    { Op36E0M0 },
3733 
+	{ Op37M0 },      { Op38 },        { Op39M0X0 },    { Op3AM0 },      { Op3B },
3734 
+	{ Op3CM0X0 },    { Op3DM0X0 },    { Op3EM0X0 },    { Op3FM0 },      { Op40Slow },
3735 
+	{ Op41E0M0 },    { Op42 },        { Op43M0 },      { Op44X0 },      { Op45M0 },
3736 
+	{ Op46M0 },      { Op47M0 },      { Op48E0M0 },    { Op49M0 },      { Op4AM0 },
3737 
+	{ Op4BE0 },      { Op4C },        { Op4DM0 },      { Op4EM0 },      { Op4FM0 },
3738 
+	{ Op50E0 },      { Op51E0M0X0 },  { Op52E0M0 },    { Op53M0 },      { Op54X0 },
3739 
+	{ Op55E0M0 },    { Op56E0M0 },    { Op57M0 },      { Op58 },        { Op59M0X0 },
3740 
+	{ Op5AE0X0 },    { Op5B },        { Op5C },        { Op5DM0X0 },    { Op5EM0X0 },
3741 
+	{ Op5FM0 },      { Op60E0 },      { Op61E0M0 },    { Op62E0 },      { Op63M0 },
3742 
+	{ Op64M0 },      { Op65M0 },      { Op66M0 },      { Op67M0 },      { Op68E0M0 },
3743 
+	{ Op69M0 },      { Op6AM0 },      { Op6BE0 },      { Op6C },        { Op6DM0 },
3744 
+	{ Op6EM0 },      { Op6FM0 },      { Op70E0 },      { Op71E0M0X0 },  { Op72E0M0 },
3745 
+	{ Op73M0 },      { Op74E0M0 },    { Op75E0M0 },    { Op76E0M0 },    { Op77M0 },
3746 
+	{ Op78 },        { Op79M0X0 },    { Op7AE0X0 },    { Op7B },        { Op7C },
3747 
+	{ Op7DM0X0 },    { Op7EM0X0 },    { Op7FM0 },      { Op80E0 },      { Op81E0M0 },
3748 
+	{ Op82 },        { Op83M0 },      { Op84X0 },      { Op85M0 },      { Op86X0 },
3749 
+	{ Op87M0 },      { Op88X0 },      { Op89M0 },      { Op8AM0 },      { Op8BE0 },
3750 
+	{ Op8CX0 },      { Op8DM0 },      { Op8EX0 },      { Op8FM0 },      { Op90E0 },
3751 
+	{ Op91E0M0X0 },  { Op92E0M0 },    { Op93M0 },      { Op94E0X0 },    { Op95E0M0 },
3752 
+	{ Op96E0X0 },    { Op97M0 },      { Op98M0 },      { Op99M0X0 },    { Op9A },
3753 
+	{ Op9BX0 },      { Op9CM0 },      { Op9DM0X0 },    { Op9EM0X0 },    { Op9FM0 },
3754 
+	{ OpA0X0 },      { OpA1E0M0 },    { OpA2X0 },      { OpA3M0 },      { OpA4X0 },
3755 
+	{ OpA5M0 },      { OpA6X0 },      { OpA7M0 },      { OpA8X0 },      { OpA9M0 },
3756 
+	{ OpAAX0 },      { OpABE0 },      { OpACX0 },      { OpADM0 },      { OpAEX0 },
3757 
+	{ OpAFM0 },      { OpB0E0 },      { OpB1E0M0X0 },  { OpB2E0M0 },    { OpB3M0 },
3758 
+	{ OpB4E0X0 },    { OpB5E0M0 },    { OpB6E0X0 },    { OpB7M0 },      { OpB8 },
3759 
+	{ OpB9M0X0 },    { OpBAX0 },      { OpBBX0 },      { OpBCX0 },      { OpBDM0X0 },
3760 
+	{ OpBEX0 },      { OpBFM0 },      { OpC0X0 },      { OpC1E0M0 },    { OpC2 },
3761 
+	{ OpC3M0 },      { OpC4X0 },      { OpC5M0 },      { OpC6M0 },      { OpC7M0 },
3762 
+	{ OpC8X0 },      { OpC9M0 },      { OpCAX0 },      { OpCB },        { OpCCX0 },
3763 
+	{ OpCDM0 },      { OpCEM0 },      { OpCFM0 },      { OpD0E0 },      { OpD1E0M0X0 },
3764 
+	{ OpD2E0M0 },    { OpD3M0 },      { OpD4E0 },      { OpD5E0M0 },    { OpD6E0M0 },
3765 
+	{ OpD7M0 },      { OpD8 },        { OpD9M0X0 },    { OpDAE0X0 },    { OpDB },
3766 
+	{ OpDC },        { OpDDM0X0 },    { OpDEM0X0 },    { OpDFM0 },      { OpE0X0 },
3767 
+	{ OpE1E0M0 },    { OpE2 },        { OpE3M0 },      { OpE4X0 },      { OpE5M0 },
3768 
+	{ OpE6M0 },      { OpE7M0 },      { OpE8X0 },      { OpE9M0 },      { OpEA },
3769 
+	{ OpEB },        { OpECX0 },      { OpEDM0 },      { OpEEM0 },      { OpEFM0 },
3770 
+	{ OpF0E0 },      { OpF1E0M0X0 },  { OpF2E0M0 },    { OpF3M0 },      { OpF4E0 },
3771 
+	{ OpF5E0M0 },    { OpF6E0M0 },    { OpF7M0 },      { OpF8 },        { OpF9M0X0 },
3772 
+	{ OpFAE0X0 },    { OpFB },        { OpFCE0 },      { OpFDM0X0 },    { OpFEM0X0 },
3773 
+	{ OpFFM0 }
3774 
+};
3775 
+
3776 
+struct SOpcodes S9xOpcodesM0X1[256] =
3777 
+{
3778 
+	{ Op00 },        { Op01E0M0 },    { Op02 },        { Op03M0 },      { Op04M0 },
3779 
+	{ Op05M0 },      { Op06M0 },      { Op07M0 },      { Op08E0 },      { Op09M0 },
3780 
+	{ Op0AM0 },      { Op0BE0 },      { Op0CM0 },      { Op0DM0 },      { Op0EM0 },
3781 
+	{ Op0FM0 },      { Op10E0 },      { Op11E0M0X1 },  { Op12E0M0 },    { Op13M0 },
3782 
+	{ Op14M0 },      { Op15E0M0 },    { Op16E0M0 },    { Op17M0 },      { Op18 },
3783 
+	{ Op19M0X1 },    { Op1AM0 },      { Op1B },        { Op1CM0 },      { Op1DM0X1 },
3784 
+	{ Op1EM0X1 },    { Op1FM0 },      { Op20E0 },      { Op21E0M0 },    { Op22E0 },
3785 
+	{ Op23M0 },      { Op24M0 },      { Op25M0 },      { Op26M0 },      { Op27M0 },
3786 
+	{ Op28E0 },      { Op29M0 },      { Op2AM0 },      { Op2BE0 },      { Op2CM0 },
3787 
+	{ Op2DM0 },      { Op2EM0 },      { Op2FM0 },      { Op30E0 },      { Op31E0M0X1 },
3788 
+	{ Op32E0M0 },    { Op33M0 },      { Op34E0M0 },    { Op35E0M0 },    { Op36E0M0 },
3789 
+	{ Op37M0 },      { Op38 },        { Op39M0X1 },    { Op3AM0 },      { Op3B },
3790 
+	{ Op3CM0X1 },    { Op3DM0X1 },    { Op3EM0X1 },    { Op3FM0 },      { Op40Slow },
3791 
+	{ Op41E0M0 },    { Op42 },        { Op43M0 },      { Op44X1 },      { Op45M0 },
3792 
+	{ Op46M0 },      { Op47M0 },      { Op48E0M0 },    { Op49M0 },      { Op4AM0 },
3793 
+	{ Op4BE0 },      { Op4C },        { Op4DM0 },      { Op4EM0 },      { Op4FM0 },
3794 
+	{ Op50E0 },      { Op51E0M0X1 },  { Op52E0M0 },    { Op53M0 },      { Op54X1 },
3795 
+	{ Op55E0M0 },    { Op56E0M0 },    { Op57M0 },      { Op58 },        { Op59M0X1 },
3796 
+	{ Op5AE0X1 },    { Op5B },        { Op5C },        { Op5DM0X1 },    { Op5EM0X1 },
3797 
+	{ Op5FM0 },      { Op60E0 },      { Op61E0M0 },    { Op62E0 },      { Op63M0 },
3798 
+	{ Op64M0 },      { Op65M0 },      { Op66M0 },      { Op67M0 },      { Op68E0M0 },
3799 
+	{ Op69M0 },      { Op6AM0 },      { Op6BE0 },      { Op6C },        { Op6DM0 },
3800 
+	{ Op6EM0 },      { Op6FM0 },      { Op70E0 },      { Op71E0M0X1 },  { Op72E0M0 },
3801 
+	{ Op73M0 },      { Op74E0M0 },    { Op75E0M0 },    { Op76E0M0 },    { Op77M0 },
3802 
+	{ Op78 },        { Op79M0X1 },    { Op7AE0X1 },    { Op7B },        { Op7C },
3803 
+	{ Op7DM0X1 },    { Op7EM0X1 },    { Op7FM0 },      { Op80E0 },      { Op81E0M0 },
3804 
+	{ Op82 },        { Op83M0 },      { Op84X1 },      { Op85M0 },      { Op86X1 },
3805 
+	{ Op87M0 },      { Op88X1 },      { Op89M0 },      { Op8AM0 },      { Op8BE0 },
3806 
+	{ Op8CX1 },      { Op8DM0 },      { Op8EX1 },      { Op8FM0 },      { Op90E0 },
3807 
+	{ Op91E0M0X1 },  { Op92E0M0 },    { Op93M0 },      { Op94E0X1 },    { Op95E0M0 },
3808 
+	{ Op96E0X1 },    { Op97M0 },      { Op98M0 },      { Op99M0X1 },    { Op9A },
3809 
+	{ Op9BX1 },      { Op9CM0 },      { Op9DM0X1 },    { Op9EM0X1 },    { Op9FM0 },
3810 
+	{ OpA0X1 },      { OpA1E0M0 },    { OpA2X1 },      { OpA3M0 },      { OpA4X1 },
3811 
+	{ OpA5M0 },      { OpA6X1 },      { OpA7M0 },      { OpA8X1 },      { OpA9M0 },
3812 
+	{ OpAAX1 },      { OpABE0 },      { OpACX1 },      { OpADM0 },      { OpAEX1 },
3813 
+	{ OpAFM0 },      { OpB0E0 },      { OpB1E0M0X1 },  { OpB2E0M0 },    { OpB3M0 },
3814 
+	{ OpB4E0X1 },    { OpB5E0M0 },    { OpB6E0X1 },    { OpB7M0 },      { OpB8 },
3815 
+	{ OpB9M0X1 },    { OpBAX1 },      { OpBBX1 },      { OpBCX1 },      { OpBDM0X1 },
3816 
+	{ OpBEX1 },      { OpBFM0 },      { OpC0X1 },      { OpC1E0M0 },    { OpC2 },
3817 
+	{ OpC3M0 },      { OpC4X1 },      { OpC5M0 },      { OpC6M0 },      { OpC7M0 },
3818 
+	{ OpC8X1 },      { OpC9M0 },      { OpCAX1 },      { OpCB },        { OpCCX1 },
3819 
+	{ OpCDM0 },      { OpCEM0 },      { OpCFM0 },      { OpD0E0 },      { OpD1E0M0X1 },
3820 
+	{ OpD2E0M0 },    { OpD3M0 },      { OpD4E0 },      { OpD5E0M0 },    { OpD6E0M0 },
3821 
+	{ OpD7M0 },      { OpD8 },        { OpD9M0X1 },    { OpDAE0X1 },    { OpDB },
3822 
+	{ OpDC },        { OpDDM0X1 },    { OpDEM0X1 },    { OpDFM0 },      { OpE0X1 },
3823 
+	{ OpE1E0M0 },    { OpE2 },        { OpE3M0 },      { OpE4X1 },      { OpE5M0 },
3824 
+	{ OpE6M0 },      { OpE7M0 },      { OpE8X1 },      { OpE9M0 },      { OpEA },
3825 
+	{ OpEB },        { OpECX1 },      { OpEDM0 },      { OpEEM0 },      { OpEFM0 },
3826 
+	{ OpF0E0 },      { OpF1E0M0X1 },  { OpF2E0M0 },    { OpF3M0 },      { OpF4E0 },
3827 
+	{ OpF5E0M0 },    { OpF6E0M0 },    { OpF7M0 },      { OpF8 },        { OpF9M0X1 },
3828 
+	{ OpFAE0X1 },    { OpFB },        { OpFCE0 },      { OpFDM0X1 },    { OpFEM0X1 },
3829 
+	{ OpFFM0 }
3830 
+};
3831 
+
3832 
+struct SOpcodes S9xOpcodesSlow[256] =
3833 
+{
3834 
+	{ Op00 },        { Op01Slow },    { Op02 },        { Op03Slow },    { Op04Slow },
3835 
+	{ Op05Slow },    { Op06Slow },    { Op07Slow },    { Op08Slow },    { Op09Slow },
3836 
+	{ Op0ASlow },    { Op0BSlow },    { Op0CSlow },    { Op0DSlow },    { Op0ESlow },
3837 
+	{ Op0FSlow },    { Op10Slow },    { Op11Slow },    { Op12Slow },    { Op13Slow },
3838 
+	{ Op14Slow },    { Op15Slow },    { Op16Slow },    { Op17Slow },    { Op18 },
3839 
+	{ Op19Slow },    { Op1ASlow },    { Op1B },        { Op1CSlow },    { Op1DSlow },
3840 
+	{ Op1ESlow },    { Op1FSlow },    { Op20Slow },    { Op21Slow },    { Op22Slow },
3841 
+	{ Op23Slow },    { Op24Slow },    { Op25Slow },    { Op26Slow },    { Op27Slow },
3842 
+	{ Op28Slow },    { Op29Slow },    { Op2ASlow },    { Op2BSlow },    { Op2CSlow },
3843 
+	{ Op2DSlow },    { Op2ESlow },    { Op2FSlow },    { Op30Slow },    { Op31Slow },
3844 
+	{ Op32Slow },    { Op33Slow },    { Op34Slow },    { Op35Slow },    { Op36Slow },
3845 
+	{ Op37Slow },    { Op38 },        { Op39Slow },    { Op3ASlow },    { Op3B },
3846 
+	{ Op3CSlow },    { Op3DSlow },    { Op3ESlow },    { Op3FSlow },    { Op40Slow },
3847 
+	{ Op41Slow },    { Op42 },        { Op43Slow },    { Op44Slow },    { Op45Slow },
3848 
+	{ Op46Slow },    { Op47Slow },    { Op48Slow },    { Op49Slow },    { Op4ASlow },
3849 
+	{ Op4BSlow },    { Op4CSlow },    { Op4DSlow },    { Op4ESlow },    { Op4FSlow },
3850 
+	{ Op50Slow },    { Op51Slow },    { Op52Slow },    { Op53Slow },    { Op54Slow },
3851 
+	{ Op55Slow },    { Op56Slow },    { Op57Slow },    { Op58 },        { Op59Slow },
3852 
+	{ Op5ASlow },    { Op5B },        { Op5CSlow },    { Op5DSlow },    { Op5ESlow },
3853 
+	{ Op5FSlow },    { Op60Slow },    { Op61Slow },    { Op62Slow },    { Op63Slow },
3854 
+	{ Op64Slow },    { Op65Slow },    { Op66Slow },    { Op67Slow },    { Op68Slow },
3855 
+	{ Op69Slow },    { Op6ASlow },    { Op6BSlow },    { Op6CSlow },    { Op6DSlow },
3856 
+	{ Op6ESlow },    { Op6FSlow },    { Op70Slow },    { Op71Slow },    { Op72Slow },
3857 
+	{ Op73Slow },    { Op74Slow },    { Op75Slow },    { Op76Slow },    { Op77Slow },
3858 
+	{ Op78 },        { Op79Slow },    { Op7ASlow },    { Op7B },        { Op7CSlow },
3859 
+	{ Op7DSlow },    { Op7ESlow },    { Op7FSlow },    { Op80Slow },    { Op81Slow },
3860 
+	{ Op82Slow },    { Op83Slow },    { Op84Slow },    { Op85Slow },    { Op86Slow },
3861 
+	{ Op87Slow },    { Op88Slow },    { Op89Slow },    { Op8ASlow },    { Op8BSlow },
3862 
+	{ Op8CSlow },    { Op8DSlow },    { Op8ESlow },    { Op8FSlow },    { Op90Slow },
3863 
+	{ Op91Slow },    { Op92Slow },    { Op93Slow },    { Op94Slow },    { Op95Slow },
3864 
+	{ Op96Slow },    { Op97Slow },    { Op98Slow },    { Op99Slow },    { Op9A },
3865 
+	{ Op9BSlow },    { Op9CSlow },    { Op9DSlow },    { Op9ESlow },    { Op9FSlow },
3866 
+	{ OpA0Slow },    { OpA1Slow },    { OpA2Slow },    { OpA3Slow },    { OpA4Slow },
3867 
+	{ OpA5Slow },    { OpA6Slow },    { OpA7Slow },    { OpA8Slow },    { OpA9Slow },
3868 
+	{ OpAASlow },    { OpABSlow },    { OpACSlow },    { OpADSlow },    { OpAESlow },
3869 
+	{ OpAFSlow },    { OpB0Slow },    { OpB1Slow },    { OpB2Slow },    { OpB3Slow },
3870 
+	{ OpB4Slow },    { OpB5Slow },    { OpB6Slow },    { OpB7Slow },    { OpB8 },
3871 
+	{ OpB9Slow },    { OpBASlow },    { OpBBSlow },    { OpBCSlow },    { OpBDSlow },
3872 
+	{ OpBESlow },    { OpBFSlow },    { OpC0Slow },    { OpC1Slow },    { OpC2Slow },
3873 
+	{ OpC3Slow },    { OpC4Slow },    { OpC5Slow },    { OpC6Slow },    { OpC7Slow },
3874 
+	{ OpC8Slow },    { OpC9Slow },    { OpCASlow },    { OpCB },        { OpCCSlow },
3875 
+	{ OpCDSlow },    { OpCESlow },    { OpCFSlow },    { OpD0Slow },    { OpD1Slow },
3876 
+	{ OpD2Slow },    { OpD3Slow },    { OpD4Slow },    { OpD5Slow },    { OpD6Slow },
3877 
+	{ OpD7Slow },    { OpD8 },        { OpD9Slow },    { OpDASlow },    { OpDB },
3878 
+	{ OpDCSlow },    { OpDDSlow },    { OpDESlow },    { OpDFSlow },    { OpE0Slow },
3879 
+	{ OpE1Slow },    { OpE2Slow },    { OpE3Slow },    { OpE4Slow },    { OpE5Slow },
3880 
+	{ OpE6Slow },    { OpE7Slow },    { OpE8Slow },    { OpE9Slow },    { OpEA },
3881 
+	{ OpEB },        { OpECSlow },    { OpEDSlow },    { OpEESlow },    { OpEFSlow },
3882 
+	{ OpF0Slow },    { OpF1Slow },    { OpF2Slow },    { OpF3Slow },    { OpF4Slow },
3883 
+	{ OpF5Slow },    { OpF6Slow },    { OpF7Slow },    { OpF8 },        { OpF9Slow },
3884 
+	{ OpFASlow },    { OpFB },        { OpFCSlow },    { OpFDSlow },    { OpFESlow },
3885 
+	{ OpFFSlow }
3886 
+};