| ... | ... |
@@ -49,7 +49,7 @@ |
| 49 | 49 |
<ClCompile> |
| 50 | 50 |
<WarningLevel>Level4</WarningLevel> |
| 51 | 51 |
<Optimization>Disabled</Optimization> |
| 52 |
- <PreprocessorDefinitions>WIN32;_WINDOWS;_USRDLL;IN_GSF_EXPORTS;_CRT_SECURE_NO_WARNINGS;WINAMP_PLUGIN;NO_DEBUGGER;FINAL_VERSION;C_CORE;_DEBUG;_ITERATOR_DEBUG_LEVEL=0;%(PreprocessorDefinitions)</PreprocessorDefinitions> |
|
| 52 |
+ <PreprocessorDefinitions>WIN32;_WINDOWS;_USRDLL;IN_GSF_EXPORTS;_CRT_SECURE_NO_WARNINGS;WINAMP_PLUGIN;_DEBUG;_ITERATOR_DEBUG_LEVEL=0;%(PreprocessorDefinitions)</PreprocessorDefinitions> |
|
| 53 | 53 |
<AdditionalIncludeDirectories>G:\Code\my_xsf\src;$(zlibRootDir)\include;$(WinampSDKDir);%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories> |
| 54 | 54 |
<DisableSpecificWarnings>4100;4127;4189;4244;4291;4310;4512;4800;%(DisableSpecificWarnings)</DisableSpecificWarnings> |
| 55 | 55 |
</ClCompile> |
| ... | ... |
@@ -66,7 +66,7 @@ |
| 66 | 66 |
<Optimization>MaxSpeed</Optimization> |
| 67 | 67 |
<FunctionLevelLinking>true</FunctionLevelLinking> |
| 68 | 68 |
<IntrinsicFunctions>true</IntrinsicFunctions> |
| 69 |
- <PreprocessorDefinitions>WIN32;_WINDOWS;_USRDLL;IN_GSF_EXPORTS;_CRT_SECURE_NO_WARNINGS;WINAMP_PLUGIN;NO_DEBUGGER;FINAL_VERSION;C_CORE;NDEBUG;%(PreprocessorDefinitions)</PreprocessorDefinitions> |
|
| 69 |
+ <PreprocessorDefinitions>WIN32;_WINDOWS;_USRDLL;IN_GSF_EXPORTS;_CRT_SECURE_NO_WARNINGS;WINAMP_PLUGIN;NDEBUG;%(PreprocessorDefinitions)</PreprocessorDefinitions> |
|
| 70 | 70 |
<AdditionalIncludeDirectories>G:\Code\my_xsf\src;$(zlibRootDir)\include;$(WinampSDKDir);%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories> |
| 71 | 71 |
<DisableSpecificWarnings>4100;4127;4189;4244;4291;4310;4512;4800;%(DisableSpecificWarnings)</DisableSpecificWarnings> |
| 72 | 72 |
</ClCompile> |
| ... | ... |
@@ -1,10 +1,9 @@ |
| 1 | 1 |
// Blip_Buffer 0.4.1. http://www.slack.net/~ant/ |
| 2 | 2 |
|
| 3 |
+#include <limits> |
|
| 3 | 4 |
#include <numeric> |
| 4 |
-#include <cassert> |
|
| 5 | 5 |
#include <cmath> |
| 6 | 6 |
#include <cstring> |
| 7 |
-#include <cstdlib> |
|
| 8 | 7 |
#include "Blip_Buffer.h" |
| 9 | 8 |
|
| 10 | 9 |
/* Copyright (C) 2003-2007 Shay Green. This module is free software; you |
| ... | ... |
@@ -22,7 +21,7 @@ Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ |
| 22 | 21 |
|
| 23 | 22 |
Blip_Buffer::Blip_Buffer() |
| 24 | 23 |
{
|
| 25 |
- this->factor_ = static_cast<uint32_t>(LONG_MAX); |
|
| 24 |
+ this->factor_ = static_cast<uint32_t>(std::numeric_limits<long>::max()); |
|
| 26 | 25 |
this->buffer_.clear(); |
| 27 | 26 |
this->buffer_size_ = 0; |
| 28 | 27 |
this->sample_rate_ = 0; |
| ... | ... |
@@ -71,7 +70,7 @@ void Blip_Buffer::set_sample_rate(long new_rate, int msec) |
| 71 | 70 |
if (s < new_size) |
| 72 | 71 |
new_size = s; |
| 73 | 72 |
else |
| 74 |
- assert(0); // fails if requested buffer length exceeds limit |
|
| 73 |
+ assert(false); // fails if requested buffer length exceeds limit |
|
| 75 | 74 |
} |
| 76 | 75 |
|
| 77 | 76 |
if (this->buffer_size_ != new_size) |
| ... | ... |
@@ -131,7 +130,7 @@ blip_time_t Blip_Buffer::count_clocks(long count) const |
| 131 | 130 |
{
|
| 132 | 131 |
if (!this->factor_) |
| 133 | 132 |
{
|
| 134 |
- assert(0); // sample rate and clock rates must be set first |
|
| 133 |
+ assert(false); // sample rate and clock rates must be set first |
|
| 135 | 134 |
return 0; |
| 136 | 135 |
} |
| 137 | 136 |
|
| ... | ... |
@@ -149,8 +148,8 @@ void Blip_Buffer::remove_samples(long count) |
| 149 | 148 |
|
| 150 | 149 |
// copy remaining samples to beginning and clear old samples |
| 151 | 150 |
long remain = this->samples_avail() + blip_buffer_extra_; |
| 152 |
- memmove(&this->buffer_[0], &this->buffer_[count], remain * sizeof(this->buffer_[0])); |
|
| 153 |
- memset(&this->buffer_[remain], 0, count * sizeof(this->buffer_[0])); |
|
| 151 |
+ memmove(&this->buffer_[0], &this->buffer_[count], remain * sizeof(buf_t_)); |
|
| 152 |
+ memset(&this->buffer_[remain], 0, count * sizeof(buf_t_)); |
|
| 154 | 153 |
} |
| 155 | 154 |
} |
| 156 | 155 |
|
| ... | ... |
@@ -159,8 +158,7 @@ void Blip_Buffer::remove_samples(long count) |
| 159 | 158 |
Blip_Synth_Fast_::Blip_Synth_Fast_() |
| 160 | 159 |
{
|
| 161 | 160 |
this->buf = nullptr; |
| 162 |
- this->last_amp = 0; |
|
| 163 |
- this->delta_factor = 0; |
|
| 161 |
+ this->last_amp = this->delta_factor = 0; |
|
| 164 | 162 |
} |
| 165 | 163 |
|
| 166 | 164 |
void Blip_Synth_Fast_::volume_unit(double new_unit) |
| ... | ... |
@@ -175,8 +173,7 @@ Blip_Synth_::Blip_Synth_(short *p, int w) : impulses(p), width(w) |
| 175 | 173 |
this->volume_unit_ = 0.0; |
| 176 | 174 |
this->kernel_unit = 0; |
| 177 | 175 |
this->buf = nullptr; |
| 178 |
- this->last_amp = 0; |
|
| 179 |
- this->delta_factor = 0; |
|
| 176 |
+ this->last_amp = this->delta_factor = 0; |
|
| 180 | 177 |
} |
| 181 | 178 |
|
| 182 | 179 |
#ifndef M_PI |
| ... | ... |
@@ -193,10 +190,10 @@ static void gen_sinc(float *out, int count, double oversample, double treble, do |
| 193 | 190 |
if (treble > 5.0) |
| 194 | 191 |
treble = 5.0; |
| 195 | 192 |
|
| 196 |
- double const maxh = 4096.0; |
|
| 197 |
- double const rolloff = std::pow(10.0, 1.0 / (maxh * 20.0) * treble / (1.0 - cutoff)); |
|
| 198 |
- double const pow_a_n = std::pow(rolloff, maxh - maxh * cutoff); |
|
| 199 |
- double const to_angle = M_PI / 2 / maxh / oversample; |
|
| 193 |
+ static const double maxh = 4096.0; |
|
| 194 |
+ double rolloff = std::pow(10.0, 1.0 / (maxh * 20.0) * treble / (1.0 - cutoff)); |
|
| 195 |
+ double pow_a_n = std::pow(rolloff, maxh - maxh * cutoff); |
|
| 196 |
+ double to_angle = M_PI / 2 / maxh / oversample; |
|
| 200 | 197 |
for (int i = 0; i < count; ++i) |
| 201 | 198 |
{
|
| 202 | 199 |
double angle = ((i - count) * 2 + 1) * to_angle; |
| ... | ... |
@@ -226,10 +223,10 @@ void blip_eq_t::generate(float *out, int count) const |
| 226 | 223 |
|
| 227 | 224 |
gen_sinc(out, count, blip_res * oversample, this->treble, cutoff); |
| 228 | 225 |
|
| 229 |
- // apply (half of) hann window |
|
| 226 |
+ // apply (half of) hamming window |
|
| 230 | 227 |
double to_fraction = M_PI / (count - 1); |
| 231 | 228 |
for (int i = count; i--; ) |
| 232 |
- out[i] *= 0.5f * (1.0f - static_cast<float>(std::cos(i * to_fraction))); |
|
| 229 |
+ out[i] *= 0.54f - 0.46f * static_cast<float>(std::cos(i * to_fraction)); |
|
| 233 | 230 |
} |
| 234 | 231 |
|
| 235 | 232 |
void Blip_Synth_::adjust_impulse() |
| ... | ... |
@@ -245,7 +242,7 @@ void Blip_Synth_::adjust_impulse() |
| 245 | 242 |
if (p == p2) |
| 246 | 243 |
error /= 2; // phase = 0.5 impulse uses same half for both sides |
| 247 | 244 |
this->impulses[size - blip_res + p] += static_cast<short>(error); |
| 248 |
- //printf("error: %ld\n", error);
|
|
| 245 |
+ //printf( "error: %ld\n", error ); |
|
| 249 | 246 |
} |
| 250 | 247 |
|
| 251 | 248 |
//for (int i = blip_res; i--; printf("\n"))
|
| ... | ... |
@@ -336,7 +333,7 @@ void Blip_Synth_::volume_unit(double new_unit) |
| 336 | 333 |
} |
| 337 | 334 |
} |
| 338 | 335 |
this->delta_factor = static_cast<int>(std::floor(factor + 0.5)); |
| 339 |
- //printf("delta_factor: %d, kernel_unit: %d\n", this->delta_factor, this->kernel_unit);
|
|
| 336 |
+ //printf( "delta_factor: %d, kernel_unit: %d\n", delta_factor, kernel_unit ); |
|
| 340 | 337 |
} |
| 341 | 338 |
} |
| 342 | 339 |
#endif |
| ... | ... |
@@ -349,10 +346,10 @@ long Blip_Buffer::read_samples(blip_sample_t *out_, long max_samples, bool stere |
| 349 | 346 |
|
| 350 | 347 |
if (count) |
| 351 | 348 |
{
|
| 352 |
- int bass = BLIP_READER_BASS(*this); |
|
| 349 |
+ int bass = BLIP_READER_BASS(this); |
|
| 353 | 350 |
BLIP_READER_BEGIN(reader, *this); |
| 354 | 351 |
BLIP_READER_ADJ_(reader, count); |
| 355 |
- auto out = out_ + count; |
|
| 352 |
+ auto out = &out_[count]; |
|
| 356 | 353 |
int32_t offset = static_cast<int32_t>(-count); |
| 357 | 354 |
|
| 358 | 355 |
do |
| ... | ... |
@@ -1,8 +1,7 @@ |
| 1 | 1 |
// Band-limited sound synthesis buffer |
| 2 | 2 |
|
| 3 | 3 |
// Blip_Buffer 0.4.1 |
| 4 |
-#ifndef BLIP_BUFFER_H |
|
| 5 |
-#define BLIP_BUFFER_H |
|
| 4 |
+#pragma once |
|
| 6 | 5 |
|
| 7 | 6 |
#include <vector> |
| 8 | 7 |
#include <cstdint> |
| ... | ... |
@@ -11,7 +10,7 @@ |
| 11 | 10 |
typedef int32_t blip_time_t; |
| 12 | 11 |
|
| 13 | 12 |
// Output samples are 16-bit signed, with a range of -32768 to 32767 |
| 14 |
-typedef short blip_sample_t; |
|
| 13 |
+typedef int16_t blip_sample_t; |
|
| 15 | 14 |
enum { blip_sample_max = 32767 };
|
| 16 | 15 |
|
| 17 | 16 |
class Blip_Buffer |
| ... | ... |
@@ -20,7 +19,7 @@ public: |
| 20 | 19 |
// Sets output sample rate and buffer length in milliseconds (1/1000 sec, defaults |
| 21 | 20 |
// to 1/4 second) and clears buffer. If there isn't enough memory, leaves buffer |
| 22 | 21 |
// untouched and returns "Out of memory", otherwise returns NULL. |
| 23 |
- void set_sample_rate(long samples_per_sec, int msec_length = 1000 / 4); |
|
| 22 |
+ void set_sample_rate(long samples_per_sec, int msec_length = 250); |
|
| 24 | 23 |
|
| 25 | 24 |
// Sets number of source time units per second |
| 26 | 25 |
void clock_rate(long clocks_per_sec); |
| ... | ... |
@@ -89,11 +88,9 @@ public: |
| 89 | 88 |
blip_resampled_time_t resampled_duration(int t) const { return t * this->factor_; }
|
| 90 | 89 |
blip_resampled_time_t resampled_time(blip_time_t t) const { return t * this->factor_ + this->offset_; }
|
| 91 | 90 |
blip_resampled_time_t clock_rate_factor(long clock_rate) const; |
| 91 |
+ |
|
| 92 | 92 |
Blip_Buffer(); |
| 93 | 93 |
virtual ~Blip_Buffer(); |
| 94 |
- |
|
| 95 |
- // Deprecated |
|
| 96 |
- typedef blip_resampled_time_t resampled_time_t; |
|
| 97 | 94 |
private: |
| 98 | 95 |
// noncopyable |
| 99 | 96 |
Blip_Buffer(const Blip_Buffer &); |
| ... | ... |
@@ -116,22 +113,28 @@ private: |
| 116 | 113 |
|
| 117 | 114 |
// Number of bits in resample ratio fraction. Higher values give a more accurate ratio |
| 118 | 115 |
// but reduce maximum buffer size. |
| 119 |
-const int BLIP_BUFFER_ACCURACY = 16; |
|
| 116 |
+enum { BLIP_BUFFER_ACCURACY = 16 };
|
|
| 120 | 117 |
|
| 121 | 118 |
// Number bits in phase offset. Fewer than 6 bits (64 phase offsets) results in |
| 122 | 119 |
// noticeable broadband noise when synthesizing high frequency square waves. |
| 123 | 120 |
// Affects size of Blip_Synth objects since they store the waveform directly. |
| 121 |
+enum |
|
| 122 |
+{
|
|
| 124 | 123 |
#if BLIP_BUFFER_FAST |
| 125 |
-const int BLIP_PHASE_BITS = 8; |
|
| 124 |
+ BLIP_PHASE_BITS = 8 |
|
| 126 | 125 |
#else |
| 127 |
-const int BLIP_PHASE_BITS = 6; |
|
| 126 |
+ BLIP_PHASE_BITS = 6 |
|
| 128 | 127 |
#endif |
| 128 |
+}; |
|
| 129 | 129 |
|
| 130 | 130 |
// Internal |
| 131 | 131 |
typedef uint32_t blip_resampled_time_t; |
| 132 |
-const int blip_widest_impulse_ = 16; |
|
| 133 |
-const int blip_buffer_extra_ = blip_widest_impulse_ + 2; |
|
| 134 |
-const int blip_res = 1 << BLIP_PHASE_BITS; |
|
| 132 |
+enum |
|
| 133 |
+{
|
|
| 134 |
+ blip_widest_impulse_ = 16, |
|
| 135 |
+ blip_buffer_extra_ = blip_widest_impulse_ + 2, |
|
| 136 |
+ blip_res = 1 << BLIP_PHASE_BITS |
|
| 137 |
+}; |
|
| 135 | 138 |
class blip_eq_t; |
| 136 | 139 |
|
| 137 | 140 |
class Blip_Synth_Fast_ |
| ... | ... |
@@ -166,9 +169,12 @@ private: |
| 166 | 169 |
}; |
| 167 | 170 |
|
| 168 | 171 |
// Quality level, better = slower. In general, use blip_good_quality. |
| 169 |
-const int blip_med_quality = 8; |
|
| 170 |
-const int blip_good_quality = 12; |
|
| 171 |
-const int blip_high_quality = 16; |
|
| 172 |
+enum |
|
| 173 |
+{
|
|
| 174 |
+ blip_med_quality = 8, |
|
| 175 |
+ blip_good_quality = 12, |
|
| 176 |
+ blip_high_quality = 16 |
|
| 177 |
+}; |
|
| 172 | 178 |
|
| 173 | 179 |
// Range specifies the greatest expected change in amplitude. Calculate it |
| 174 | 180 |
// by finding the difference between the maximum and minimum expected |
| ... | ... |
@@ -216,7 +222,7 @@ private: |
| 216 | 222 |
Blip_Synth_Fast_ impl; |
| 217 | 223 |
#else |
| 218 | 224 |
Blip_Synth_ impl; |
| 219 |
- typedef short imp_t; |
|
| 225 |
+ typedef int16_t imp_t; |
|
| 220 | 226 |
imp_t impulses[blip_res * (quality / 2) + 1]; |
| 221 | 227 |
public: |
| 222 | 228 |
Blip_Synth() : impl(impulses, quality) { }
|
| ... | ... |
@@ -243,21 +249,21 @@ private: |
| 243 | 249 |
friend class Blip_Synth_; |
| 244 | 250 |
}; |
| 245 | 251 |
|
| 246 |
-const int blip_sample_bits = 30; |
|
| 252 |
+enum { blip_sample_bits = 30 };
|
|
| 247 | 253 |
|
| 248 | 254 |
// Optimized reading from Blip_Buffer, for use in custom sample output |
| 249 | 255 |
|
| 250 | 256 |
// Begins reading from buffer. Name should be unique to the current block. |
| 251 | 257 |
#define BLIP_READER_BEGIN(name, blip_buffer) \ |
| 252 |
- auto name##_reader_buf = &(blip_buffer).buffer_[0]; \ |
|
| 258 |
+ const Blip_Buffer::buf_t_ *name##_reader_buf = &(blip_buffer).buffer_[0]; \ |
|
| 253 | 259 |
int32_t name##_reader_accum = (blip_buffer).reader_accum_ |
| 254 | 260 |
|
| 255 | 261 |
// Gets value to pass to BLIP_READER_NEXT() |
| 256 |
-inline int BLIP_READER_BASS(const Blip_Buffer &blip_buffer) { return blip_buffer.bass_shift_; }
|
|
| 262 |
+inline int BLIP_READER_BASS(const Blip_Buffer *blip_buffer) { return blip_buffer->bass_shift_; }
|
|
| 257 | 263 |
|
| 258 | 264 |
// Constant value to use instead of BLIP_READER_BASS(), for slightly more optimal |
| 259 | 265 |
// code at the cost of having no bass control |
| 260 |
-const int blip_reader_default_bass = 9; |
|
| 266 |
+enum { blip_reader_default_bass = 9 };
|
|
| 261 | 267 |
|
| 262 | 268 |
// Current sample |
| 263 | 269 |
#define BLIP_READER_READ(name) (name##_reader_accum >> (blip_sample_bits - 16)) |
| ... | ... |
@@ -283,12 +289,6 @@ const int blip_reader_default_bass = 9; |
| 283 | 289 |
name##_reader_accum += name##_reader_buf[(idx)]; \ |
| 284 | 290 |
} |
| 285 | 291 |
|
| 286 |
-#define BLIP_READER_NEXT_RAW_IDX_(name, bass, idx) \ |
|
| 287 |
-{ \
|
|
| 288 |
- name##_reader_accum -= name##_reader_accum >> (bass); \ |
|
| 289 |
- name##_reader_accum += *reinterpret_cast<const Blip_Buffer::buf_t_ *>(reinterpret_cast<const char *>(name##_reader_buf) + (idx)); \ |
|
| 290 |
-} |
|
| 291 |
- |
|
| 292 | 292 |
#if defined(_M_IX86) || defined(_M_IA64) || defined(__i486__) || defined(__x86_64__) || defined(__ia64__) || defined(__i386__) |
| 293 | 293 |
template<typename T> inline bool BLIP_CLAMP_(const T &in) { return in < -0x8000 || 0x7FFF < in; }
|
| 294 | 294 |
#else |
| ... | ... |
@@ -304,9 +304,7 @@ template<typename T1, typename T2> inline void BLIP_CLAMP(const T1 &sample, T2 & |
| 304 | 304 |
|
| 305 | 305 |
// End of public interface |
| 306 | 306 |
|
| 307 |
-#ifndef assert |
|
| 308 |
-# include <cassert> |
|
| 309 |
-#endif |
|
| 307 |
+#include <cassert> |
|
| 310 | 308 |
|
| 311 | 309 |
template<int quality, int range> inline void Blip_Synth<quality, range>::offset_resampled(blip_resampled_time_t time, int delta, Blip_Buffer *blip_buf) const |
| 312 | 310 |
{
|
| ... | ... |
@@ -316,7 +314,7 @@ template<int quality, int range> inline void Blip_Synth<quality, range>::offset_ |
| 316 | 314 |
|
| 317 | 315 |
delta *= this->impl.delta_factor; |
| 318 | 316 |
auto buf = &blip_buf->buffer_[time >> BLIP_BUFFER_ACCURACY]; |
| 319 |
- int phase = static_cast<int>((time >> (BLIP_BUFFER_ACCURACY - BLIP_PHASE_BITS)) & (blip_res - 1)); |
|
| 317 |
+ int phase = static_cast<int>(time >> (BLIP_BUFFER_ACCURACY - BLIP_PHASE_BITS) & (blip_res - 1)); |
|
| 320 | 318 |
|
| 321 | 319 |
#if BLIP_BUFFER_FAST |
| 322 | 320 |
int32_t left = buf[0] + delta; |
| ... | ... |
@@ -335,12 +333,12 @@ template<int quality, int range> inline void Blip_Synth<quality, range>::offset_ |
| 335 | 333 |
int rev = fwd + quality - 2; |
| 336 | 334 |
int mid = quality / 2 - 1; |
| 337 | 335 |
|
| 338 |
- auto imp = this->impulses + blip_res - phase; |
|
| 336 |
+ auto imp = &this->impulses[blip_res - phase]; |
|
| 339 | 337 |
|
| 340 | 338 |
# if defined(_M_IX86) || defined(_M_IA64) || defined(__i486__) || defined(__x86_64__) || defined(__ia64__) || defined(__i386__) |
| 341 | 339 |
// this straight forward version gave in better code on GCC for x86 |
| 342 | 340 |
|
| 343 |
- auto ADD_IMP = [&](int out, int in) { buf[out] += static_cast<int32_t>(imp[blip_res * in] * delta); };
|
|
| 341 |
+ auto ADD_IMP = [&](int out, int in) { buf[out] += static_cast<int32_t>(imp[blip_res * in]) * delta; };
|
|
| 344 | 342 |
|
| 345 | 343 |
auto BLIP_FWD = [&](int i) { ADD_IMP(fwd + i, i); ADD_IMP(fwd + 1 + i, i + 1); };
|
| 346 | 344 |
auto BLIP_REV = [&](int r) { ADD_IMP(rev - r, r + 1); ADD_IMP(rev + 1 - r, r); };
|
| ... | ... |
@@ -352,7 +350,7 @@ template<int quality, int range> inline void Blip_Synth<quality, range>::offset_ |
| 352 | 350 |
BLIP_FWD(4); |
| 353 | 351 |
ADD_IMP(fwd + mid - 1, mid - 1); |
| 354 | 352 |
ADD_IMP(fwd + mid, mid); |
| 355 |
- imp = this->impulses + phase; |
|
| 353 |
+ imp = &this->impulses[phase]; |
|
| 356 | 354 |
if (quality > 12) |
| 357 | 355 |
BLIP_REV(6); |
| 358 | 356 |
if (quality > 8) |
| ... | ... |
@@ -390,7 +388,7 @@ template<int quality, int range> inline void Blip_Synth<quality, range>::offset_ |
| 390 | 388 |
BLIP_FWD(4); |
| 391 | 389 |
int32_t t0 = i0 * delta + buf[fwd + mid - 1]; |
| 392 | 390 |
int32_t t1 = imp[blip_res * mid] * delta + buf[fwd + mid]; |
| 393 |
- imp = this->impulses + phase; |
|
| 391 |
+ imp = &this->impulses[phase]; |
|
| 394 | 392 |
i0 = imp[blip_res * mid]; |
| 395 | 393 |
buf[fwd + mid - 1] = t0; |
| 396 | 394 |
buf[fwd + mid] = t1; |
| ... | ... |
@@ -442,7 +440,8 @@ inline uint32_t Blip_Buffer::unsettled() const |
| 442 | 440 |
return this->reader_accum_ >> (blip_sample_bits - 16); |
| 443 | 441 |
} |
| 444 | 442 |
|
| 445 |
-const int blip_max_length = 0; |
|
| 446 |
-const int blip_default_length = 250; // 1/4 second |
|
| 447 |
- |
|
| 448 |
-#endif |
|
| 443 |
+enum |
|
| 444 |
+{
|
|
| 445 |
+ blip_max_length = 0, |
|
| 446 |
+ blip_default_length = 250 // 1/4 second |
|
| 447 |
+}; |
| ... | ... |
@@ -30,7 +30,7 @@ void Gb_Apu::treble_eq(const blip_eq_t &eq) |
| 30 | 30 |
int Gb_Apu::calc_output(int osc) const |
| 31 | 31 |
{
|
| 32 | 32 |
int bits = this->regs[stereo_reg - start_addr] >> osc; |
| 33 |
- return ((bits >> 3) & 2) | (bits & 1); |
|
| 33 |
+ return (bits >> 3 & 2) | (bits & 1); |
|
| 34 | 34 |
} |
| 35 | 35 |
|
| 36 | 36 |
void Gb_Apu::set_output(Blip_Buffer *center, Blip_Buffer *left, Blip_Buffer *right, int osc) |
| ... | ... |
@@ -65,7 +65,7 @@ void Gb_Apu::apply_volume() |
| 65 | 65 |
// TODO: Doesn't handle differing left and right volumes (panning). |
| 66 | 66 |
// Not worth the complexity. |
| 67 | 67 |
int data = this->regs[vol_reg - start_addr]; |
| 68 |
- int left = (data >> 4) & 7; |
|
| 68 |
+ int left = data >> 4 & 7; |
|
| 69 | 69 |
int right = data & 7; |
| 70 | 70 |
//if ( data & 0x88 ) dprintf( "Vin: %02X\n", data & 0x88 ); |
| 71 | 71 |
//if ( left != right ) dprintf( "l: %d r: %d\n", left, right ); |
| ... | ... |
@@ -83,8 +83,7 @@ void Gb_Apu::volume(double v) |
| 83 | 83 |
|
| 84 | 84 |
void Gb_Apu::reset_regs() |
| 85 | 85 |
{
|
| 86 |
- for (int i = 0; i < 0x20; ++i) |
|
| 87 |
- this->regs[i] = 0; |
|
| 86 |
+ std::fill(&this->regs[0], &this->regs[0x20], 0); |
|
| 88 | 87 |
|
| 89 | 88 |
this->square1.reset(); |
| 90 | 89 |
this->square2.reset(); |
| ... | ... |
@@ -173,11 +172,7 @@ Gb_Apu::Gb_Apu() |
| 173 | 172 |
{
|
| 174 | 173 |
auto &o = *this->oscs[i]; |
| 175 | 174 |
o.regs = &this->regs[i * 5]; |
| 176 |
- o.output = nullptr; |
|
| 177 |
- o.outputs[0] = nullptr; |
|
| 178 |
- o.outputs[1] = nullptr; |
|
| 179 |
- o.outputs[2] = nullptr; |
|
| 180 |
- o.outputs[3] = nullptr; |
|
| 175 |
+ o.output = o.outputs[0] = o.outputs[1] = o.outputs[2] = o.outputs[3] = nullptr; |
|
| 181 | 176 |
o.good_synth = &this->good_synth; |
| 182 | 177 |
o.med_synth = &this->med_synth; |
| 183 | 178 |
} |
| ... | ... |
@@ -190,7 +185,7 @@ Gb_Apu::Gb_Apu() |
| 190 | 185 |
|
| 191 | 186 |
void Gb_Apu::run_until_(blip_time_t end_time) |
| 192 | 187 |
{
|
| 193 |
- while (1) |
|
| 188 |
+ while (true) |
|
| 194 | 189 |
{
|
| 195 | 190 |
// run oscillators |
| 196 | 191 |
blip_time_t time = end_time; |
| ... | ... |
@@ -1,8 +1,7 @@ |
| 1 | 1 |
// Nintendo Game Boy sound hardware emulator with save state support |
| 2 | 2 |
|
| 3 | 3 |
// Gb_Snd_Emu 0.2.0 |
| 4 |
-#ifndef GB_APU_H |
|
| 5 |
-#define GB_APU_H |
|
| 4 |
+#pragma once |
|
| 6 | 5 |
|
| 7 | 6 |
#include "Gb_Oscs.h" |
| 8 | 7 |
|
| ... | ... |
@@ -64,7 +63,7 @@ public: |
| 64 | 63 |
// Treble and bass values for various hardware. |
| 65 | 64 |
enum |
| 66 | 65 |
{
|
| 67 |
- speaker_treble = -47, // speaker on system |
|
| 66 |
+ speaker_treble = -47, // speaker on system |
|
| 68 | 67 |
speaker_bass = 2000, |
| 69 | 68 |
dmg_treble = 0, // headphones on each system |
| 70 | 69 |
dmg_bass = 30, |
| ... | ... |
@@ -114,10 +113,7 @@ private: |
| 114 | 113 |
void run_until(blip_time_t); |
| 115 | 114 |
void silence_osc(Gb_Osc &); |
| 116 | 115 |
void write_osc(int index, int reg, int old_data, int data); |
| 117 |
- friend class Gb_Apu_Tester; |
|
| 118 | 116 |
|
| 119 | 117 |
public: |
| 120 | 118 |
int read_status(); |
| 121 | 119 |
}; |
| 122 |
- |
|
| 123 |
-#endif |
| ... | ... |
@@ -22,8 +22,7 @@ static const int length_enabled = 0x40; |
| 22 | 22 |
void Gb_Osc::reset() |
| 23 | 23 |
{
|
| 24 | 24 |
this->output = nullptr; |
| 25 |
- this->last_amp = 0; |
|
| 26 |
- this->delay = 0; |
|
| 25 |
+ this->last_amp = this->delay = 0; |
|
| 27 | 26 |
this->phase = 0; |
| 28 | 27 |
this->enabled = false; |
| 29 | 28 |
} |
| ... | ... |
@@ -90,7 +89,7 @@ void Gb_Sweep_Square::calc_sweep(bool update) |
| 90 | 89 |
this->sweep_freq = freq; |
| 91 | 90 |
|
| 92 | 91 |
this->regs[3] = freq & 0xFF; |
| 93 |
- this->regs[4] = (this->regs[4] & ~0x07) | ((freq >> 8) & 0x07); |
|
| 92 |
+ this->regs[4] = (this->regs[4] & ~0x07) | (freq >> 8 & 0x07); |
|
| 94 | 93 |
} |
| 95 | 94 |
} |
| 96 | 95 |
|
| ... | ... |
@@ -441,7 +440,7 @@ static unsigned run_lfsr(unsigned s, unsigned mask, int count) |
| 441 | 440 |
{
|
| 442 | 441 |
// won't fully replace upper 8 bits, so have to do the unoptimized way |
| 443 | 442 |
while (--count >= 0) |
| 444 |
- s = ((s >> 1) | mask) ^ (mask & (0 - ((s - 1) & 2))); |
|
| 443 |
+ s = (s >> 1 | mask) ^ (mask & (0 - ((s - 1) & 2))); |
|
| 445 | 444 |
} |
| 446 | 445 |
else |
| 447 | 446 |
{
|
| ... | ... |
@@ -453,7 +452,7 @@ static unsigned run_lfsr(unsigned s, unsigned mask, int count) |
| 453 | 452 |
} |
| 454 | 453 |
|
| 455 | 454 |
// Need to keep one extra bit of history |
| 456 |
- s = (s << 1) & 0xFF; |
|
| 455 |
+ s = s << 1 & 0xFF; |
|
| 457 | 456 |
|
| 458 | 457 |
// Convert from Fibonacci to Galois configuration, |
| 459 | 458 |
// shifted left 2 bits |
| ... | ... |
@@ -471,7 +470,7 @@ static unsigned run_lfsr(unsigned s, unsigned mask, int count) |
| 471 | 470 |
|
| 472 | 471 |
// Convert back to Fibonacci configuration and |
| 473 | 472 |
// repeat last 8 bits above significant 7 |
| 474 |
- s = ((s << 7) & 0x7F80) | ((s >> 1) & 0x7F); |
|
| 473 |
+ s = (s << 7 & 0x7F80) | (s >> 1 & 0x7F); |
|
| 475 | 474 |
} |
| 476 | 475 |
|
| 477 | 476 |
return s; |
| ... | ... |
@@ -514,15 +513,13 @@ void Gb_Noise::run(blip_time_t time, blip_time_t end_time) |
| 514 | 513 |
// Run timer and calculate time of next LFSR clock |
| 515 | 514 |
static const uint8_t period1s[] = { 1, 2, 4, 6, 8, 10, 12, 14 };
|
| 516 | 515 |
int period1 = period1s[this->regs[3] & 7] * clk_mul; |
| 517 |
- {
|
|
| 518 |
- int extra = (end_time - time) - this->delay; |
|
| 519 |
- int per2 = this->period2(); |
|
| 520 |
- time += this->delay + ((this->divider ^ (per2 >> 1)) & (per2 - 1)) * period1; |
|
| 516 |
+ int extra = (end_time - time) - this->delay; |
|
| 517 |
+ int per2 = this->period2(); |
|
| 518 |
+ time += this->delay + ((this->divider ^ (per2 >> 1)) & (per2 - 1)) * period1; |
|
| 521 | 519 |
|
| 522 |
- int count = extra < 0 ? 0 : (extra + period1 - 1) / period1; |
|
| 523 |
- this->divider = (this->divider - count) & period2_mask; |
|
| 524 |
- this->delay = count * period1 - extra; |
|
| 525 |
- } |
|
| 520 |
+ int count = extra < 0 ? 0 : (extra + period1 - 1) / period1; |
|
| 521 |
+ this->divider = (this->divider - count) & period2_mask; |
|
| 522 |
+ this->delay = count * period1 - extra; |
|
| 526 | 523 |
|
| 527 | 524 |
// Generate wave |
| 528 | 525 |
if (time < end_time) |
| ... | ... |
@@ -547,7 +544,7 @@ void Gb_Noise::run(blip_time_t time, blip_time_t end_time) |
| 547 | 544 |
do |
| 548 | 545 |
{
|
| 549 | 546 |
unsigned changed = bits + 1; |
| 550 |
- bits = (bits >> 1) & mask; |
|
| 547 |
+ bits = bits >> 1 & mask; |
|
| 551 | 548 |
if (changed & 2) |
| 552 | 549 |
{
|
| 553 | 550 |
bits |= ~mask; |
| ... | ... |
@@ -569,11 +566,11 @@ void Gb_Wave::run(blip_time_t time, blip_time_t end_time) |
| 569 | 566 |
// Calc volume |
| 570 | 567 |
static const uint8_t volumes[] = { 0, 4, 2, 1, 3, 3, 3, 3 };
|
| 571 | 568 |
static const int volume_shift = 2; |
| 572 |
- int volume_idx = (this->regs[2] >> 5) & (this->agb_mask | 3); // 2 bits on DMG/CGB, 3 on AGB |
|
| 569 |
+ int volume_idx = this->regs[2] >> 5 & (this->agb_mask | 3); // 2 bits on DMG/CGB, 3 on AGB |
|
| 573 | 570 |
int volume_mul = volumes[volume_idx]; |
| 574 | 571 |
|
| 575 | 572 |
// Determine what will be generated |
| 576 |
- int playing = false; |
|
| 573 |
+ int playing = 0; |
|
| 577 | 574 |
auto out = this->output; |
| 578 | 575 |
if (out) |
| 579 | 576 |
{
|
| ... | ... |
@@ -587,9 +584,9 @@ void Gb_Wave::run(blip_time_t time, blip_time_t end_time) |
| 587 | 584 |
if (this->frequency() <= 0x7FB || this->delay > 15 * clk_mul) |
| 588 | 585 |
{
|
| 589 | 586 |
if (volume_mul) |
| 590 |
- playing = this->enabled; |
|
| 587 |
+ playing = static_cast<int>(this->enabled); |
|
| 591 | 588 |
|
| 592 |
- amp = (this->sample_buf << ((this->phase << 2) & 4) & 0xF0) * playing; |
|
| 589 |
+ amp = (this->sample_buf << (this->phase << 2 & 4) & 0xF0) * playing; |
|
| 593 | 590 |
} |
| 594 | 591 |
|
| 595 | 592 |
amp = ((amp * volume_mul) >> (volume_shift + 4)) - dac_bias; |
| ... | ... |
@@ -632,7 +629,7 @@ void Gb_Wave::run(blip_time_t time, blip_time_t end_time) |
| 632 | 629 |
do |
| 633 | 630 |
{
|
| 634 | 631 |
// Extract nybble |
| 635 |
- int nybble = (wave[ph >> 1] << ((ph << 2) & 4)) & 0xF0; |
|
| 632 |
+ int nybble = wave[ph >> 1] << (ph << 2 & 4) & 0xF0; |
|
| 636 | 633 |
ph = (ph + 1) & wave_mask; |
| 637 | 634 |
|
| 638 | 635 |
// Scale by volume |
| ... | ... |
@@ -1,8 +1,7 @@ |
| 1 | 1 |
// Private oscillators used by Gb_Apu |
| 2 | 2 |
|
| 3 | 3 |
// Gb_Snd_Emu 0.2.0 |
| 4 |
-#ifndef GB_OSCS_H |
|
| 5 |
-#define GB_OSCS_H |
|
| 4 |
+#pragma once |
|
| 6 | 5 |
|
| 7 | 6 |
#include "blargg_common.h" |
| 8 | 7 |
#include "Blip_Buffer.h" |
| ... | ... |
@@ -170,7 +169,7 @@ private: |
| 170 | 169 |
|
| 171 | 170 |
void corrupt_wave(); |
| 172 | 171 |
|
| 173 |
- uint8_t *wave_bank() const { return &this->wave_ram[((~this->regs[0] & bank40_mask) >> 2) & agb_mask]; }
|
|
| 172 |
+ uint8_t *wave_bank() const { return &this->wave_ram[(~this->regs[0] & bank40_mask) >> 2 & this->agb_mask]; }
|
|
| 174 | 173 |
|
| 175 | 174 |
// Wave index that would be accessed, or -1 if no access would occur |
| 176 | 175 |
int access(unsigned addr) const; |
| ... | ... |
@@ -188,5 +187,3 @@ inline void Gb_Wave::write(unsigned addr, int data) |
| 188 | 187 |
if (index >= 0) |
| 189 | 188 |
this->wave_bank()[index] = data; |
| 190 | 189 |
} |
| 191 |
- |
|
| 192 |
-#endif |
| ... | ... |
@@ -14,10 +14,6 @@ details. You should have received a copy of the GNU Lesser General Public |
| 14 | 14 |
License along with this module; if not, write to the Free Software Foundation, |
| 15 | 15 |
Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ |
| 16 | 16 |
|
| 17 |
-#ifdef BLARGG_ENABLE_OPTIMIZER |
|
| 18 |
-# include BLARGG_ENABLE_OPTIMIZER |
|
| 19 |
-#endif |
|
| 20 |
- |
|
| 21 | 17 |
Multi_Buffer::Multi_Buffer(int spf) : samples_per_frame_(spf) |
| 22 | 18 |
{
|
| 23 | 19 |
this->length_ = 0; |
| ... | ... |
@@ -177,7 +173,7 @@ void Stereo_Mixer::read_pairs(blip_sample_t *out, int count) |
| 177 | 173 |
|
| 178 | 174 |
void Stereo_Mixer::mix_mono(blip_sample_t *out_, int count) |
| 179 | 175 |
{
|
| 180 |
- int bass = BLIP_READER_BASS(*this->bufs[2]); |
|
| 176 |
+ int bass = BLIP_READER_BASS(this->bufs[2]); |
|
| 181 | 177 |
BLIP_READER_BEGIN(center, *this->bufs[2]); |
| 182 | 178 |
BLIP_READER_ADJ_(center, this->samples_read); |
| 183 | 179 |
|
| ... | ... |
@@ -198,16 +194,16 @@ void Stereo_Mixer::mix_mono(blip_sample_t *out_, int count) |
| 198 | 194 |
|
| 199 | 195 |
void Stereo_Mixer::mix_stereo(blip_sample_t *out_, int count) |
| 200 | 196 |
{
|
| 201 |
- auto out = out_ + count * stereo; |
|
| 197 |
+ auto out = &out_[count * stereo]; |
|
| 202 | 198 |
|
| 203 | 199 |
// do left + center and right + center separately to reduce register load |
| 204 | 200 |
auto buf = &this->bufs[2]; |
| 205 |
- while (1) // loop runs twice |
|
| 201 |
+ while (true) // loop runs twice |
|
| 206 | 202 |
{
|
| 207 | 203 |
--buf; |
| 208 | 204 |
--out; |
| 209 | 205 |
|
| 210 |
- int bass = BLIP_READER_BASS(*this->bufs[2]); |
|
| 206 |
+ int bass = BLIP_READER_BASS(this->bufs[2]); |
|
| 211 | 207 |
BLIP_READER_BEGIN(side, **buf); |
| 212 | 208 |
BLIP_READER_BEGIN(center, *this->bufs[2]); |
| 213 | 209 |
|
| ... | ... |
@@ -1,8 +1,7 @@ |
| 1 | 1 |
// Multi-channel sound buffer interface, and basic mono and stereo buffers |
| 2 | 2 |
|
| 3 | 3 |
// Blip_Buffer 0.4.1 |
| 4 |
-#ifndef MULTI_BUFFER_H |
|
| 5 |
-#define MULTI_BUFFER_H |
|
| 4 |
+#pragma once |
|
| 6 | 5 |
|
| 7 | 6 |
#include "blargg_common.h" |
| 8 | 7 |
#include "Blip_Buffer.h" |
| ... | ... |
@@ -19,7 +18,7 @@ public: |
| 19 | 18 |
// (type information used by Effects_Buffer) |
| 20 | 19 |
enum { type_index_mask = 0xFF };
|
| 21 | 20 |
enum { wave_type = 0x100, noise_type = 0x200, mixed_type = wave_type | noise_type };
|
| 22 |
- virtual void set_channel_count(int, const int* types = nullptr); |
|
| 21 |
+ virtual void set_channel_count(int, const int *types = nullptr); |
|
| 23 | 22 |
int channel_count() const { return this->channel_count_; }
|
| 24 | 23 |
|
| 25 | 24 |
// Gets indexed channel, from 0 to channel count - 1 |
| ... | ... |
@@ -152,5 +151,3 @@ inline void Multi_Buffer::set_channel_count(int n, const int *types) |
| 152 | 151 |
this->channel_count_ = n; |
| 153 | 152 |
this->channel_types_ = types; |
| 154 | 153 |
} |
| 155 |
- |
|
| 156 |
-#endif |
| ... | ... |
@@ -2,18 +2,12 @@ |
| 2 | 2 |
// To change configuration options, modify blargg_config.h, not this file. |
| 3 | 3 |
|
| 4 | 4 |
// Gb_Snd_Emu 0.2.0 |
| 5 |
-#ifndef BLARGG_COMMON_H |
|
| 6 |
-#define BLARGG_COMMON_H |
|
| 5 |
+#pragma once |
|
| 7 | 6 |
|
| 8 | 7 |
#include <cstdlib> |
| 9 | 8 |
#include <cassert> |
| 10 | 9 |
#include <cstdint> |
| 11 |
- |
|
| 12 |
-#undef BLARGG_COMMON_H |
|
| 13 |
-// allow blargg_config.h to #include blargg_common.h |
|
| 14 | 10 |
#include "blargg_config.h" |
| 15 |
-#ifndef BLARGG_COMMON_H |
|
| 16 |
-#define BLARGG_COMMON_H |
|
| 17 | 11 |
|
| 18 | 12 |
// BLARGG_COMPILER_HAS_BOOL: If 0, provides bool support for old compiler. If 1, |
| 19 | 13 |
// compiler is assumed to support bool. If undefined, availability is determined. |
| ... | ... |
@@ -38,6 +32,3 @@ typedef int bool; |
| 38 | 32 |
const bool true = 1; |
| 39 | 33 |
const bool false = 0; |
| 40 | 34 |
#endif |
| 41 |
- |
|
| 42 |
-#endif |
|
| 43 |
-#endif |
| ... | ... |
@@ -1,7 +1,6 @@ |
| 1 | 1 |
// $package user configuration file. Don't replace when updating library. |
| 2 | 2 |
|
| 3 |
-#ifndef BLARGG_CONFIG_H |
|
| 4 |
-#define BLARGG_CONFIG_H |
|
| 3 |
+#pragma once |
|
| 5 | 4 |
|
| 6 | 5 |
// Uncomment to have Gb_Apu run at 4x normal clock rate (16777216 Hz), useful in |
| 7 | 6 |
// a Game Boy Advance emulator. |
| ... | ... |
@@ -9,5 +8,3 @@ |
| 9 | 8 |
|
| 10 | 9 |
// Uncomment if you get errors in the bool section of blargg_common.h |
| 11 | 10 |
//#define BLARGG_COMPILER_HAS_BOOL 1 |
| 12 |
- |
|
| 13 |
-#endif |
| ... | ... |
@@ -1,28 +1,25 @@ |
| 1 |
-#ifndef PORT_H |
|
| 2 |
-#define PORT_H |
|
| 1 |
+#pragma once |
|
| 3 | 2 |
|
| 4 | 3 |
#include <cstdint> |
| 5 | 4 |
|
| 6 | 5 |
#ifdef WORDS_BIGENDIAN |
| 7 |
-#if defined(__GNUC__) && defined(__ppc__) |
|
| 6 |
+# if defined(__GNUC__) && defined(__ppc__) |
|
| 8 | 7 |
#define READ16LE(base) \ |
| 9 |
- ({ \
|
|
| 10 |
- unsigned short lhbrxResult; \ |
|
| 11 |
- __asm__("lhbrx %0, 0, %1" : "=r" (lhbrxResult) : "r" (base) : "memory"); \
|
|
| 12 |
- lhbrxResult; \ |
|
| 13 |
- }) |
|
| 8 |
+ ({ unsigned short lhbrxResult; \
|
|
| 9 |
+ __asm__ ("lhbrx %0, 0, %1" : "=r" (lhbrxResult) : "r" (base) : "memory"); \
|
|
| 10 |
+ lhbrxResult; }) |
|
| 14 | 11 |
|
| 15 | 12 |
#define READ32LE(base) \ |
| 16 |
- ({ \
|
|
| 17 |
- unsigned long lwbrxResult; \ |
|
| 18 |
- __asm__("lwbrx %0, 0, %1" : "=r" (lwbrxResult) : "r" (base) : "memory"); \
|
|
| 19 |
- lwbrxResult; \ |
|
| 20 |
- }) |
|
| 13 |
+ ({ unsigned long lwbrxResult; \
|
|
| 14 |
+ __asm__ ("lwbrx %0, 0, %1" : "=r" (lwbrxResult) : "r" (base) : "memory"); \
|
|
| 15 |
+ lwbrxResult; }) |
|
| 21 | 16 |
|
| 22 |
-#define WRITE16LE(base, value) __asm__("sthbrx %0, 0, %1" : : "r" (value), "r" (base) : "memory")
|
|
| 17 |
+#define WRITE16LE(base, value) \ |
|
| 18 |
+ __asm__ ("sthbrx %0, 0, %1" : : "r" (value), "r" (base) : "memory")
|
|
| 23 | 19 |
|
| 24 |
-#define WRITE32LE(base, value) __asm__("stwbrx %0, 0, %1" : : "r" (value), "r" (base) : "memory")
|
|
| 25 |
-#else |
|
| 20 |
+#define WRITE32LE(base, value) \ |
|
| 21 |
+ __asm__ ("stwbrx %0, 0, %1" : : "r" (value), "r" (base) : "memory")
|
|
| 22 |
+# else |
|
| 26 | 23 |
// swaps a 16-bit value |
| 27 | 24 |
inline uint16_t swap16(uint16_t v) |
| 28 | 25 |
{
|
| ... | ... |
@@ -35,16 +32,14 @@ inline uint32_t swap32(uint32_t v) |
| 35 | 32 |
return (v << 24) | ((v << 8) & 0xff0000) | ((v >> 8) & 0xff00) | (v >> 24); |
| 36 | 33 |
} |
| 37 | 34 |
|
| 38 |
-template<typename T> inline uint16_t READ16LE(T *x) { return swap16(*reinterpret_cast<uint16_t *>(x)); }
|
|
| 39 |
-template<typename T> inline uint32_t READ32LE(T *x) { return swap32(*reinterpret_cast<uint32_t *>(x)); }
|
|
| 35 |
+template<typename T> inline uint16_t READ16LE(const T *x) { return swap16(*reinterpret_cast<const uint16_t *>(x)); }
|
|
| 36 |
+template<typename T> inline uint32_t READ32LE(const T *x) { return swap32(*reinterpret_cast<const uint32_t *>(x)); }
|
|
| 40 | 37 |
template<typename T> inline void WRITE16LE(T *x, uint16_t v) { *reinterpret_cast<uint16_t *>(x) = swap16(v); }
|
| 41 | 38 |
template<typename T> inline void WRITE32LE(T *x, uint32_t v) { *reinterpret_cast<uint32_t *>(x) = swap32(v); }
|
| 42 |
-#endif |
|
| 39 |
+# endif |
|
| 43 | 40 |
#else |
| 44 |
-template<typename T> inline uint16_t READ16LE(T *x) { return *reinterpret_cast<uint16_t *>(x); }
|
|
| 45 |
-template<typename T> inline uint32_t READ32LE(T *x) { return *reinterpret_cast<uint32_t *>(x); }
|
|
| 41 |
+template<typename T> inline uint16_t READ16LE(const T *x) { return *reinterpret_cast<const uint16_t *>(x); }
|
|
| 42 |
+template<typename T> inline uint32_t READ32LE(const T *x) { return *reinterpret_cast<const uint32_t *>(x); }
|
|
| 46 | 43 |
template<typename T> inline void WRITE16LE(T *x, uint16_t v) { *reinterpret_cast<uint16_t *>(x) = v; }
|
| 47 | 44 |
template<typename T> inline void WRITE32LE(T *x, uint32_t v) { *reinterpret_cast<uint32_t *>(x) = v; }
|
| 48 | 45 |
#endif |
| 49 |
- |
|
| 50 |
-#endif // PORT_H |
| ... | ... |
@@ -15,8 +15,7 @@ |
| 15 | 15 |
// along with this program; if not, write to the Free Software Foundation, |
| 16 | 16 |
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
| 17 | 17 |
|
| 18 |
-#ifndef __VBA_SOUND_DRIVER_H__ |
|
| 19 |
-#define __VBA_SOUND_DRIVER_H__ |
|
| 18 |
+#pragma once |
|
| 20 | 19 |
|
| 21 | 20 |
#include <cstdint> |
| 22 | 21 |
|
| ... | ... |
@@ -60,5 +59,3 @@ public: |
| 60 | 59 |
|
| 61 | 60 |
virtual void setThrottle(unsigned short throttle) { }
|
| 62 | 61 |
}; |
| 63 |
- |
|
| 64 |
-#endif // __VBA_SOUND_DRIVER_H__ |
| ... | ... |
@@ -52,578 +52,6 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }
|
| 52 | 52 |
// RRX_OFFSET: Used to rotate (RRX) the `offset' parameter for LDR and |
| 53 | 53 |
// STR instructions. |
| 54 | 54 |
|
| 55 |
-#ifndef C_CORE |
|
| 56 |
-# if 0 // definitions have changed |
|
| 57 |
-//#ifdef __POWERPC__ |
|
| 58 |
-# define OP_SUBS \ |
|
| 59 |
-{ \
|
|
| 60 |
- register int Flags; \ |
|
| 61 |
- register int Result; \ |
|
| 62 |
- asm volatile("subco. %0, %2, %3\n" \
|
|
| 63 |
- "mcrxr cr1\n" \ |
|
| 64 |
- "mfcr %1\n" \ |
|
| 65 |
- : "=r" (Result), \ |
|
| 66 |
- "=r" (Flags) \ |
|
| 67 |
- : "r" (reg[base].I), \ |
|
| 68 |
- "r" (value) \ |
|
| 69 |
- ); \ |
|
| 70 |
- reg[dest].I = Result; \ |
|
| 71 |
- Z_FLAG = (Flags >> 29) & 1; \ |
|
| 72 |
- N_FLAG = (Flags >> 31) & 1; \ |
|
| 73 |
- C_FLAG = (Flags >> 25) & 1; \ |
|
| 74 |
- V_FLAG = (Flags >> 26) & 1; \ |
|
| 75 |
-} |
|
| 76 |
-# define OP_RSBS \ |
|
| 77 |
-{ \
|
|
| 78 |
- register int Flags; \ |
|
| 79 |
- register int Result; \ |
|
| 80 |
- asm volatile("subfco. %0, %2, %3\n" \
|
|
| 81 |
- "mcrxr cr1\n" \ |
|
| 82 |
- "mfcr %1\n" \ |
|
| 83 |
- : "=r" (Result), \ |
|
| 84 |
- "=r" (Flags) \ |
|
| 85 |
- : "r" (reg[base].I), \ |
|
| 86 |
- "r" (value) \ |
|
| 87 |
- ); \ |
|
| 88 |
- reg[dest].I = Result; \ |
|
| 89 |
- Z_FLAG = (Flags >> 29) & 1; \ |
|
| 90 |
- N_FLAG = (Flags >> 31) & 1; \ |
|
| 91 |
- C_FLAG = (Flags >> 25) & 1; \ |
|
| 92 |
- V_FLAG = (Flags >> 26) & 1; \ |
|
| 93 |
-} |
|
| 94 |
-# define OP_ADDS \ |
|
| 95 |
-{ \
|
|
| 96 |
- register int Flags; \ |
|
| 97 |
- register int Result; \ |
|
| 98 |
- asm volatile("addco. %0, %2, %3\n" \
|
|
| 99 |
- "mcrxr cr1\n" \ |
|
| 100 |
- "mfcr %1\n" \ |
|
| 101 |
- : "=r" (Result), \ |
|
| 102 |
- "=r" (Flags) \ |
|
| 103 |
- : "r" (reg[base].I), \ |
|
| 104 |
- "r" (value) \ |
|
| 105 |
- ); \ |
|
| 106 |
- reg[dest].I = Result; \ |
|
| 107 |
- Z_FLAG = (Flags >> 29) & 1; \ |
|
| 108 |
- N_FLAG = (Flags >> 31) & 1; \ |
|
| 109 |
- C_FLAG = (Flags >> 25) & 1; \ |
|
| 110 |
- V_FLAG = (Flags >> 26) & 1; \ |
|
| 111 |
-} |
|
| 112 |
-# define OP_ADCS \ |
|
| 113 |
-{ \
|
|
| 114 |
- register int Flags; \ |
|
| 115 |
- register int Result; \ |
|
| 116 |
- asm volatile("mtspr xer, %4\n" \
|
|
| 117 |
- "addeo. %0, %2, %3\n" \ |
|
| 118 |
- "mcrxr cr1\n" \ |
|
| 119 |
- "mfcr %1\n" \ |
|
| 120 |
- : "=r" (Result), \ |
|
| 121 |
- "=r" (Flags) \ |
|
| 122 |
- : "r" (reg[base].I), \ |
|
| 123 |
- "r" (value), \ |
|
| 124 |
- "r" (C_FLAG << 29) \ |
|
| 125 |
- ); \ |
|
| 126 |
- reg[dest].I = Result; \ |
|
| 127 |
- Z_FLAG = (Flags >> 29) & 1; \ |
|
| 128 |
- N_FLAG = (Flags >> 31) & 1; \ |
|
| 129 |
- C_FLAG = (Flags >> 25) & 1; \ |
|
| 130 |
- V_FLAG = (Flags >> 26) & 1; \ |
|
| 131 |
-} |
|
| 132 |
-# define OP_SBCS \ |
|
| 133 |
-{ \
|
|
| 134 |
- register int Flags; \ |
|
| 135 |
- register int Result; \ |
|
| 136 |
- asm volatile("mtspr xer, %4\n" \
|
|
| 137 |
- "subfeo. %0, %3, %2\n" \ |
|
| 138 |
- "mcrxr cr1\n" \ |
|
| 139 |
- "mfcr %1\n" \ |
|
| 140 |
- : "=r" (Result), \ |
|
| 141 |
- "=r" (Flags) \ |
|
| 142 |
- : "r" (reg[base].I), \ |
|
| 143 |
- "r" (value), \ |
|
| 144 |
- "r" (C_FLAG << 29) \ |
|
| 145 |
- ); \ |
|
| 146 |
- reg[dest].I = Result; \ |
|
| 147 |
- Z_FLAG = (Flags >> 29) & 1; \ |
|
| 148 |
- N_FLAG = (Flags >> 31) & 1; \ |
|
| 149 |
- C_FLAG = (Flags >> 25) & 1; \ |
|
| 150 |
- V_FLAG = (Flags >> 26) & 1; \ |
|
| 151 |
-} |
|
| 152 |
-# define OP_RSCS \ |
|
| 153 |
-{ \
|
|
| 154 |
- register int Flags; \ |
|
| 155 |
- register int Result; \ |
|
| 156 |
- asm volatile("mtspr xer, %4\n"\
|
|
| 157 |
- "subfeo. %0, %2, %3\n" \ |
|
| 158 |
- "mcrxr cr1\n" \ |
|
| 159 |
- "mfcr %1\n" \ |
|
| 160 |
- : "=r" (Result), \ |
|
| 161 |
- "=r" (Flags) \ |
|
| 162 |
- : "r" (reg[base].I), \ |
|
| 163 |
- "r" (value), \ |
|
| 164 |
- "r" (C_FLAG << 29) \ |
|
| 165 |
- ); \ |
|
| 166 |
- reg[dest].I = Result; \ |
|
| 167 |
- Z_FLAG = (Flags >> 29) & 1; \ |
|
| 168 |
- N_FLAG = (Flags >> 31) & 1; \ |
|
| 169 |
- C_FLAG = (Flags >> 25) & 1; \ |
|
| 170 |
- V_FLAG = (Flags >> 26) & 1; \ |
|
| 171 |
-} |
|
| 172 |
-# define OP_CMP \ |
|
| 173 |
-{ \
|
|
| 174 |
- register int Flags; \ |
|
| 175 |
- register int Result; \ |
|
| 176 |
- asm volatile("subco. %0, %2, %3\n" \
|
|
| 177 |
- "mcrxr cr1\n" \ |
|
| 178 |
- "mfcr %1\n" \ |
|
| 179 |
- : "=r" (Result), \ |
|
| 180 |
- "=r" (Flags) \ |
|
| 181 |
- : "r" (reg[base].I), \ |
|
| 182 |
- "r" (value) \ |
|
| 183 |
- ); \ |
|
| 184 |
- Z_FLAG = (Flags >> 29) & 1; \ |
|
| 185 |
- N_FLAG = (Flags >> 31) & 1; \ |
|
| 186 |
- C_FLAG = (Flags >> 25) & 1; \ |
|
| 187 |
- V_FLAG = (Flags >> 26) & 1; \ |
|
| 188 |
-} |
|
| 189 |
-# define OP_CMN \ |
|
| 190 |
-{ \
|
|
| 191 |
- register int Flags; \ |
|
| 192 |
- register int Result; \ |
|
| 193 |
- asm volatile("addco. %0, %2, %3\n" \
|
|
| 194 |
- "mcrxr cr1\n" \ |
|
| 195 |
- "mfcr %1\n" \ |
|
| 196 |
- : "=r" (Result), \ |
|
| 197 |
- "=r" (Flags) \ |
|
| 198 |
- : "r" (reg[base].I), \ |
|
| 199 |
- "r" (value) \ |
|
| 200 |
- ); \ |
|
| 201 |
- Z_FLAG = (Flags >> 29) & 1; \ |
|
| 202 |
- N_FLAG = (Flags >> 31) & 1; \ |
|
| 203 |
- C_FLAG = (Flags >> 25) & 1; \ |
|
| 204 |
- V_FLAG = (Flags >> 26) & 1; \ |
|
| 205 |
-} |
|
| 206 |
-# else // !__POWERPC__ |
|
| 207 |
-// Macros to emit instructions in the format used by the particular compiler. |
|
| 208 |
-// We use GNU assembler syntax: "op src, dest" rather than "op dest, src" |
|
| 209 |
- |
|
| 210 |
-# ifdef __GNUC__ |
|
| 211 |
-# define ALU_HEADER asm("mov %%ecx, %%edi; "
|
|
| 212 |
-# define ALU_TRAILER : "=D" (opcode) : "c" (opcode) : "eax", "ebx", "edx", "esi") |
|
| 213 |
-# define EMIT0(op) #op "; " |
|
| 214 |
-# define EMIT1(op, arg) #op " " arg "; " |
|
| 215 |
-# define EMIT2(op, src, dest) #op " " src ", " dest "; " |
|
| 216 |
-# define KONST(val) "$" #val |
|
| 217 |
-# define ASMVAR(cvar) ASMVAR2(__USER_LABEL_PREFIX__, cvar) |
|
| 218 |
-# define ASMVAR2(prefix, cvar) STRING(prefix) cvar |
|
| 219 |
-# define STRING(x) #x |
|
| 220 |
-# define VAR(var) ASMVAR(#var) |
|
| 221 |
-# define VARL(var) ASMVAR(#var) |
|
| 222 |
-# define REGREF1(index) ASMVAR("reg(" index ")")
|
|
| 223 |
-# define REGREF2(index, scale) ASMVAR("reg(," index "," #scale ")")
|
|
| 224 |
-# define LABEL(n) #n ": " |
|
| 225 |
-# define LABELREF(n, dir) #n#dir |
|
| 226 |
-# define al "%%al" |
|
| 227 |
-# define ah "%%ah" |
|
| 228 |
-# define eax "%%eax" |
|
| 229 |
-# define bl "%%bl" |
|
| 230 |
-# define bh "%%bh" |
|
| 231 |
-# define ebx "%%ebx" |
|
| 232 |
-# define cl "%%cl" |
|
| 233 |
-# define ch "%%ch" |
|
| 234 |
-# define ecx "%%ecx" |
|
| 235 |
-# define dl "%%dl" |
|
| 236 |
-# define dh "%%dh" |
|
| 237 |
-# define edx "%%edx" |
|
| 238 |
-# define esp "%%esp" |
|
| 239 |
-# define ebp "%%ebp" |
|
| 240 |
-# define esi "%%esi" |
|
| 241 |
-# define edi "%%edi" |
|
| 242 |
-# define movzx movzb |
|
| 243 |
-# else |
|
| 244 |
-# define ALU_HEADER __asm { __asm mov ecx, opcode
|
|
| 245 |
-# define ALU_TRAILER } |
|
| 246 |
-# define EMIT0(op) __asm op |
|
| 247 |
-# define EMIT1(op, arg) __asm op arg |
|
| 248 |
-# define EMIT2(op, src, dest) __asm op dest, src |
|
| 249 |
-# define KONST(val) val |
|
| 250 |
-# define VAR(var) var |
|
| 251 |
-# define VARL(var) dword ptr var |
|
| 252 |
-# define REGREF1(index) reg[index] |
|
| 253 |
-# define REGREF2(index, scale) reg[index * scale] |
|
| 254 |
-# define LABEL(n) __asm l##n: |
|
| 255 |
-# define LABELREF(n, dir) l##n |
|
| 256 |
-# endif |
|
| 257 |
- |
|
| 258 |
-//X//#ifndef _MSC_VER |
|
| 259 |
-// ALU op register usage: |
|
| 260 |
-// EAX -> 2nd operand value, result (RSB/RSC) |
|
| 261 |
-// EBX -> C_OUT (carry flag from shift/rotate) |
|
| 262 |
-// ECX -> opcode (input), shift/rotate count |
|
| 263 |
-// EDX -> Rn (base) value, result (all except RSB/RSC) |
|
| 264 |
-// ESI -> Rd (destination) index * 4 |
|
| 265 |
- |
|
| 266 |
-// Helper macros for loading value / shift count |
|
| 267 |
-# define VALUE_LOAD_IMM \ |
|
| 268 |
- EMIT2(and, KONST(0x0F), eax) \ |
|
| 269 |
- EMIT2(mov, REGREF2(eax, 4), eax) \ |
|
| 270 |
- EMIT2(shr, KONST(7), ecx) \ |
|
| 271 |
- EMIT2(and, KONST(0x1F), ecx) |
|
| 272 |
-# define VALUE_LOAD_REG \ |
|
| 273 |
- EMIT2(and, KONST(0x0F), eax) \ |
|
| 274 |
- EMIT2(cmp, KONST(0x0F), eax) \ |
|
| 275 |
- EMIT2(mov, REGREF2(eax, 4), eax) \ |
|
| 276 |
- EMIT1(jne, LABELREF(3, f)) \ |
|
| 277 |
- EMIT2(add, KONST(4), eax) \ |
|
| 278 |
- LABEL(3) \ |
|
| 279 |
- EMIT2(movzx, ch, ecx) \ |
|
| 280 |
- EMIT2(and, KONST(0x0F), ecx) \ |
|
| 281 |
- EMIT2(mov, REGREF2(ecx, 4), ecx) |
|
| 282 |
- |
|
| 283 |
-// Helper macros for setting flags |
|
| 284 |
-# define SETCOND_LOGICAL \ |
|
| 285 |
- EMIT1(sets, VAR(N_FLAG)) \ |
|
| 286 |
- EMIT1(setz, VAR(Z_FLAG)) \ |
|
| 287 |
- EMIT2(mov, bl, VAR(C_FLAG)) |
|
| 288 |
-# define SETCOND_ADD \ |
|
| 289 |
- EMIT1(sets, VAR(N_FLAG)) \ |
|
| 290 |
- EMIT1(setz, VAR(Z_FLAG)) \ |
|
| 291 |
- EMIT1(seto, VAR(V_FLAG)) \ |
|
| 292 |
- EMIT1(setc, VAR(C_FLAG)) |
|
| 293 |
-# define SETCOND_SUB \ |
|
| 294 |
- EMIT1(sets, VAR(N_FLAG)) \ |
|
| 295 |
- EMIT1(setz, VAR(Z_FLAG)) \ |
|
| 296 |
- EMIT1(seto, VAR(V_FLAG)) \ |
|
| 297 |
- EMIT1(setnc, VAR(C_FLAG)) |
|
| 298 |
- |
|
| 299 |
-// ALU initialization |
|
| 300 |
-# define ALU_INIT(LOAD_C_FLAG) \ |
|
| 301 |
- ALU_HEADER \ |
|
| 302 |
- LOAD_C_FLAG \ |
|
| 303 |
- EMIT2(mov, ecx, edx) \ |
|
| 304 |
- EMIT2(shr, KONST(14), edx) \ |
|
| 305 |
- EMIT2(mov, ecx, eax) \ |
|
| 306 |
- EMIT2(mov, ecx, esi) \ |
|
| 307 |
- EMIT2(shr, KONST(10), esi) \ |
|
| 308 |
- EMIT2(and, KONST(0x3C), edx) \ |
|
| 309 |
- EMIT2(mov, REGREF1(edx), edx) \ |
|
| 310 |
- EMIT2(and, KONST(0x3C), esi) |
|
| 311 |
- |
|
| 312 |
-# define LOAD_C_FLAG_YES EMIT2(mov, VAR(C_FLAG), bl) |
|
| 313 |
-# define LOAD_C_FLAG_NO /*nothing*/ |
|
| 314 |
-# define ALU_INIT_C ALU_INIT(LOAD_C_FLAG_YES) |
|
| 315 |
-# define ALU_INIT_NC ALU_INIT(LOAD_C_FLAG_NO) |
|
| 316 |
- |
|
| 317 |
-// Macros to load the value operand for an ALU op; these all set N/Z |
|
| 318 |
-// according to the value |
|
| 319 |
- |
|
| 320 |
-// OP Rd,Rb,Rm LSL # |
|
| 321 |
-# define VALUE_LSL_IMM_C \ |
|
| 322 |
- VALUE_LOAD_IMM \ |
|
| 323 |
- EMIT1(jnz, LABELREF(1, f)) \ |
|
| 324 |
- EMIT1(jmp, LABELREF(0, f)) \ |
|
| 325 |
- LABEL(1) \ |
|
| 326 |
- EMIT2(shl, cl, eax) \ |
|
| 327 |
- EMIT1(setc, bl) \ |
|
| 328 |
- LABEL(0) |
|
| 329 |
-# define VALUE_LSL_IMM_NC \ |
|
| 330 |
- VALUE_LOAD_IMM \ |
|
| 331 |
- EMIT2(shl, cl, eax) |
|
| 332 |
- |
|
| 333 |
-// OP Rd,Rb,Rm LSL Rs |
|
| 334 |
-# define VALUE_LSL_REG_C \ |
|
| 335 |
- VALUE_LOAD_REG \ |
|
| 336 |
- EMIT2(test, cl, cl) \ |
|
| 337 |
- EMIT1(jz, LABELREF(0, f)) \ |
|
| 338 |
- EMIT2(cmp, KONST(0x20), cl) \ |
|
| 339 |
- EMIT1(je, LABELREF(1, f)) \ |
|
| 340 |
- EMIT1(ja, LABELREF(2, f)) \ |
|
| 341 |
- EMIT2(shl, cl, eax) \ |
|
| 342 |
- EMIT1(setc, bl) \ |
|
| 343 |
- EMIT1(jmp, LABELREF(0, f)) \ |
|
| 344 |
- LABEL(1) \ |
|
| 345 |
- EMIT2(test, KONST(1), al) \ |
|
| 346 |
- EMIT1(setnz, bl) \ |
|
| 347 |
- EMIT2(xor, eax, eax) \ |
|
| 348 |
- EMIT1(jmp, LABELREF(0, f)) \ |
|
| 349 |
- LABEL(2) \ |
|
| 350 |
- EMIT2(xor, ebx, ebx) \ |
|
| 351 |
- EMIT2(xor, eax, eax) \ |
|
| 352 |
- LABEL(0) |
|
| 353 |
-# define VALUE_LSL_REG_NC \ |
|
| 354 |
- VALUE_LOAD_REG \ |
|
| 355 |
- EMIT2(cmp, KONST(0x20), cl) \ |
|
| 356 |
- EMIT1(jae, LABELREF(1, f)) \ |
|
| 357 |
- EMIT2(shl, cl, eax) \ |
|
| 358 |
- EMIT1(jmp, LABELREF(0, f)) \ |
|
| 359 |
- LABEL(1) \ |
|
| 360 |
- EMIT2(xor, eax, eax) \ |
|
| 361 |
- LABEL(0) |
|
| 362 |
- |
|
| 363 |
-// OP Rd,Rb,Rm LSR # |
|
| 364 |
-# define VALUE_LSR_IMM_C \ |
|
| 365 |
- VALUE_LOAD_IMM \ |
|
| 366 |
- EMIT1(jz, LABELREF(1, f)) \ |
|
| 367 |
- EMIT2(shr, cl, eax) \ |
|
| 368 |
- EMIT1(setc, bl) \ |
|
| 369 |
- EMIT1(jmp, LABELREF(0, f)) \ |
|
| 370 |
- LABEL(1) \ |
|
| 371 |
- EMIT2(test, eax, eax) \ |
|
| 372 |
- EMIT1(sets, bl) \ |
|
| 373 |
- EMIT2(xor, eax, eax) \ |
|
| 374 |
- LABEL(0) |
|
| 375 |
-# define VALUE_LSR_IMM_NC \ |
|
| 376 |
- VALUE_LOAD_IMM \ |
|
| 377 |
- EMIT1(jz, LABELREF(1, f)) \ |
|
| 378 |
- EMIT2(shr, cl, eax) \ |
|
| 379 |
- EMIT1(jmp, LABELREF(0, f)) \ |
|
| 380 |
- LABEL(1) \ |
|
| 381 |
- EMIT2(xor, eax, eax) \ |
|
| 382 |
- LABEL(0) |
|
| 383 |
- |
|
| 384 |
-// OP Rd,Rb,Rm LSR Rs |
|
| 385 |
-# define VALUE_LSR_REG_C \ |
|
| 386 |
- VALUE_LOAD_REG \ |
|
| 387 |
- EMIT2(test, cl, cl) \ |
|
| 388 |
- EMIT1(jz, LABELREF(0, f)) \ |
|
| 389 |
- EMIT2(cmp, KONST(0x20), cl) \ |
|
| 390 |
- EMIT1(je, LABELREF(1, f)) \ |
|
| 391 |
- EMIT1(ja, LABELREF(2, f)) \ |
|
| 392 |
- EMIT2(shr, cl, eax) \ |
|
| 393 |
- EMIT1(setc, bl) \ |
|
| 394 |
- EMIT1(jmp, LABELREF(0, f)) \ |
|
| 395 |
- LABEL(1) \ |
|
| 396 |
- EMIT2(test, eax, eax) \ |
|
| 397 |
- EMIT1(sets, bl) \ |
|
| 398 |
- EMIT2(xor, eax, eax) \ |
|
| 399 |
- EMIT1(jmp, LABELREF(0, f)) \ |
|
| 400 |
- LABEL(2) \ |
|
| 401 |
- EMIT2(xor, ebx, ebx) \ |
|
| 402 |
- EMIT2(xor, eax, eax) \ |
|
| 403 |
- LABEL(0) |
|
| 404 |
-# define VALUE_LSR_REG_NC \ |
|
| 405 |
- VALUE_LOAD_REG \ |
|
| 406 |
- EMIT2(cmp, KONST(0x20), cl) \ |
|
| 407 |
- EMIT1(jae, LABELREF(1, f)) \ |
|
| 408 |
- EMIT2(shr, cl, eax) \ |
|
| 409 |
- EMIT1(jmp, LABELREF(0, f)) \ |
|
| 410 |
- LABEL(1) \ |
|
| 411 |
- EMIT2(xor, eax, eax) \ |
|
| 412 |
- LABEL(0) |
|
| 413 |
- |
|
| 414 |
-// OP Rd,Rb,Rm ASR # |
|
| 415 |
-# define VALUE_ASR_IMM_C \ |
|
| 416 |
- VALUE_LOAD_IMM \ |
|
| 417 |
- EMIT1(jz, LABELREF(1, f)) \ |
|
| 418 |
- EMIT2(sar, cl, eax) \ |
|
| 419 |
- EMIT1(setc, bl) \ |
|
| 420 |
- EMIT1(jmp, LABELREF(0, f)) \ |
|
| 421 |
- LABEL(1) \ |
|
| 422 |
- EMIT2(sar, KONST(31), eax) \ |
|
| 423 |
- EMIT1(sets, bl) \ |
|
| 424 |
- LABEL(0) |
|
| 425 |
-# define VALUE_ASR_IMM_NC \ |
|
| 426 |
- VALUE_LOAD_IMM \ |
|
| 427 |
- EMIT1(jz, LABELREF(1, f)) \ |
|
| 428 |
- EMIT2(sar, cl, eax) \ |
|
| 429 |
- EMIT1(jmp, LABELREF(0, f)) \ |
|
| 430 |
- LABEL(1) \ |
|
| 431 |
- EMIT2(sar, KONST(31), eax) \ |
|
| 432 |
- LABEL(0) |
|
| 433 |
- |
|
| 434 |
-// OP Rd,Rb,Rm ASR Rs |
|
| 435 |
-# define VALUE_ASR_REG_C \ |
|
| 436 |
- VALUE_LOAD_REG \ |
|
| 437 |
- EMIT2(test, cl, cl) \ |
|
| 438 |
- EMIT1(jz, LABELREF(0, f)) \ |
|
| 439 |
- EMIT2(cmp, KONST(0x20), cl) \ |
|
| 440 |
- EMIT1(jae, LABELREF(1, f)) \ |
|
| 441 |
- EMIT2(sar, cl, eax) \ |
|
| 442 |
- EMIT1(setc, bl) \ |
|
| 443 |
- EMIT1(jmp, LABELREF(0, f)) \ |
|
| 444 |
- LABEL(1) \ |
|
| 445 |
- EMIT2(sar, KONST(31), eax) \ |
|
| 446 |
- EMIT1(sets, bl) \ |
|
| 447 |
- LABEL(0) |
|
| 448 |
-# define VALUE_ASR_REG_NC \ |
|
| 449 |
- VALUE_LOAD_REG \ |
|
| 450 |
- EMIT2(cmp, KONST(0x20), cl) \ |
|
| 451 |
- EMIT1(jae, LABELREF(1, f)) \ |
|
| 452 |
- EMIT2(sar, cl, eax) \ |
|
| 453 |
- EMIT1(jmp, LABELREF(0, f)) \ |
|
| 454 |
- LABEL(1) \ |
|
| 455 |
- EMIT2(sar, KONST(31), eax) \ |
|
| 456 |
- LABEL(0) |
|
| 457 |
- |
|
| 458 |
-// OP Rd,Rb,Rm ROR # |
|
| 459 |
-# define VALUE_ROR_IMM_C \ |
|
| 460 |
- VALUE_LOAD_IMM \ |
|
| 461 |
- EMIT1(jz, LABELREF(1, f)) \ |
|
| 462 |
- EMIT2(ror, cl, eax) \ |
|
| 463 |
- EMIT1(jmp, LABELREF(0, f)) \ |
|
| 464 |
- LABEL(1) \ |
|
| 465 |
- EMIT2(bt, KONST(0), ebx) \ |
|
| 466 |
- EMIT2(rcr, KONST(1), eax) \ |
|
| 467 |
- LABEL(0) \ |
|
| 468 |
- EMIT1(setc, bl) |
|
| 469 |
-# define VALUE_ROR_IMM_NC \ |
|
| 470 |
- VALUE_LOAD_IMM \ |
|
| 471 |
- EMIT1(jz, LABELREF(1, f)) \ |
|
| 472 |
- EMIT2(ror, cl, eax) \ |
|
| 473 |
- EMIT1(jmp, LABELREF(0, f)) \ |
|
| 474 |
- LABEL(1) \ |
|
| 475 |
- EMIT2(bt, KONST(0), VARL(C_FLAG)) \ |
|
| 476 |
- EMIT2(rcr, KONST(1), eax) \ |
|
| 477 |
- LABEL(0) |
|
| 478 |
- |
|
| 479 |
-// OP Rd,Rb,Rm ROR Rs |
|
| 480 |
-# define VALUE_ROR_REG_C \ |
|
| 481 |
- VALUE_LOAD_REG \ |
|
| 482 |
- EMIT2(bt, KONST(0), ebx) \ |
|
| 483 |
- EMIT2(ror, cl, eax) \ |
|
| 484 |
- EMIT1(setc, bl) |
|
| 485 |
-# define VALUE_ROR_REG_NC \ |
|
| 486 |
- VALUE_LOAD_REG \ |
|
| 487 |
- EMIT2(ror, cl, eax) |
|
| 488 |
- |
|
| 489 |
-// OP Rd,Rb,# ROR # |
|
| 490 |
-# define VALUE_IMM_C \ |
|
| 491 |
- EMIT2(movzx, ch, ecx) \ |
|
| 492 |
- EMIT2(add, ecx, ecx) \ |
|
| 493 |
- EMIT2(movzx, al, eax) \ |
|
| 494 |
- EMIT2(bt, KONST(0), ebx) \ |
|
| 495 |
- EMIT2(ror, cl, eax) \ |
|
| 496 |
- EMIT1(setc, bl) |
|
| 497 |
-# define VALUE_IMM_NC \ |
|
| 498 |
- EMIT2(movzx, ch, ecx) \ |
|
| 499 |
- EMIT2(add, ecx, ecx) \ |
|
| 500 |
- EMIT2(movzx, al, eax) \ |
|
| 501 |
- EMIT2(ror, cl, eax) |
|
| 502 |
- |
|
| 503 |
-// Macros to perform ALU ops |
|
| 504 |
- |
|
| 505 |
-// Set condition codes iff the destination register is not R15 (PC) |
|
| 506 |
-# define CHECK_PC(OP, SETCOND) \ |
|
| 507 |
- EMIT2(cmp, KONST(0x3C), esi) \ |
|
| 508 |
- EMIT1(je, LABELREF(8, f)) \ |
|
| 509 |
- OP SETCOND \ |
|
| 510 |
- EMIT1(jmp, LABELREF(9, f)) \ |
|
| 511 |
- LABEL(8) \ |
|
| 512 |
- OP \ |
|
| 513 |
- LABEL(9) |
|
| 514 |
- |
|
| 515 |
-# define OP_AND \ |
|
| 516 |
- EMIT2(and, eax, edx) \ |
|
| 517 |
- EMIT2(mov, edx, REGREF1(esi)) |
|
| 518 |
-# define OP_ANDS CHECK_PC(OP_AND, SETCOND_LOGICAL) |
|
| 519 |
-# define OP_EOR \ |
|
| 520 |
- EMIT2(xor, eax, edx) \ |
|
| 521 |
- EMIT2(mov, edx, REGREF1(esi)) |
|
| 522 |
-# define OP_EORS CHECK_PC(OP_EOR, SETCOND_LOGICAL) |
|
| 523 |
-# define OP_SUB \ |
|
| 524 |
- EMIT2(sub, eax, edx) \ |
|
| 525 |
- EMIT2(mov, edx, REGREF1(esi)) |
|
| 526 |
-# define OP_SUBS CHECK_PC(OP_SUB, SETCOND_SUB) |
|
| 527 |
-# define OP_RSB \ |
|
| 528 |
- EMIT2(sub, edx, eax) \ |
|
| 529 |
- EMIT2(mov, eax, REGREF1(esi)) |
|
| 530 |
-# define OP_RSBS CHECK_PC(OP_RSB, SETCOND_SUB) |
|
| 531 |
-# define OP_ADD \ |
|
| 532 |
- EMIT2(add, eax, edx) \ |
|
| 533 |
- EMIT2(mov, edx, REGREF1(esi)) |
|
| 534 |
-# define OP_ADDS CHECK_PC(OP_ADD, SETCOND_ADD) |
|
| 535 |
-# define OP_ADC \ |
|
| 536 |
- EMIT2(bt, KONST(0), VARL(C_FLAG)) \ |
|
| 537 |
- EMIT2(adc, eax, edx) \ |
|
| 538 |
- EMIT2(mov, edx, REGREF1(esi)) |
|
| 539 |
-# define OP_ADCS CHECK_PC(OP_ADC, SETCOND_ADD) |
|
| 540 |
-# define OP_SBC \ |
|
| 541 |
- EMIT2(bt, KONST(0), VARL(C_FLAG)) \ |
|
| 542 |
- EMIT0(cmc) \ |
|
| 543 |
- EMIT2(sbb, eax, edx) \ |
|
| 544 |
- EMIT2(mov, edx, REGREF1(esi)) |
|
| 545 |
-# define OP_SBCS CHECK_PC(OP_SBC, SETCOND_SUB) |
|
| 546 |
-# define OP_RSC \ |
|
| 547 |
- EMIT2(bt, KONST(0), VARL(C_FLAG)) \ |
|
| 548 |
- EMIT0(cmc) \ |
|
| 549 |
- EMIT2(sbb, edx, eax) \ |
|
| 550 |
- EMIT2(mov, eax, REGREF1(esi)) |
|
| 551 |
-# define OP_RSCS CHECK_PC(OP_RSC, SETCOND_SUB) |
|
| 552 |
-# define OP_TST \ |
|
| 553 |
- EMIT2(and, eax, edx) \ |
|
| 554 |
- SETCOND_LOGICAL |
|
| 555 |
-# define OP_TEQ \ |
|
| 556 |
- EMIT2(xor, eax, edx) \ |
|
| 557 |
- SETCOND_LOGICAL |
|
| 558 |
-# define OP_CMP \ |
|
| 559 |
- EMIT2(sub, eax, edx) \ |
|
| 560 |
- SETCOND_SUB |
|
| 561 |
-# define OP_CMN \ |
|
| 562 |
- EMIT2(add, eax, edx) \ |
|
| 563 |
- SETCOND_ADD |
|
| 564 |
-# define OP_ORR \ |
|
| 565 |
- EMIT2(or, eax, edx) \ |
|
| 566 |
- EMIT2(mov, edx, REGREF1(esi)) |
|
| 567 |
-# define OP_ORRS CHECK_PC(OP_ORR, SETCOND_LOGICAL) |
|
| 568 |
-# define OP_MOV \ |
|
| 569 |
- EMIT2(mov, eax, REGREF1(esi)) |
|
| 570 |
-# define OP_MOVS CHECK_PC(EMIT2(test, eax, eax) EMIT2(mov, eax, REGREF1(esi)), SETCOND_LOGICAL) |
|
| 571 |
-# define OP_BIC \ |
|
| 572 |
- EMIT1(not, eax) \ |
|
| 573 |
- EMIT2(and, eax, edx) \ |
|
| 574 |
- EMIT2(mov, edx, REGREF1(esi)) |
|
| 575 |
-# define OP_BICS CHECK_PC(OP_BIC, SETCOND_LOGICAL) |
|
| 576 |
-# define OP_MVN \ |
|
| 577 |
- EMIT1(not, eax) \ |
|
| 578 |
- EMIT2(mov, eax, REGREF1(esi)) |
|
| 579 |
-# define OP_MVNS CHECK_PC(OP_MVN EMIT2(test, eax, eax), SETCOND_LOGICAL) |
|
| 580 |
- |
|
| 581 |
-// ALU cleanup macro |
|
| 582 |
-# define ALU_FINISH ALU_TRAILER |
|
| 583 |
- |
|
| 584 |
-// End of ALU macros |
|
| 585 |
-//X//#endif //_MSC_VER |
|
| 586 |
-# ifdef __GNUC__ |
|
| 587 |
-# define ROR_IMM_MSR \ |
|
| 588 |
- asm("ror %%cl, %%eax;" \
|
|
| 589 |
- : "=a" (value) \ |
|
| 590 |
- : "a" (opcode & 0xFF), "c" (shift)); |
|
| 591 |
- |
|
| 592 |
-# define ROR_OFFSET \ |
|
| 593 |
- asm("ror %%cl, %0" \
|
|
| 594 |
- : "=r" (offset) \ |
|
| 595 |
- : "0" (offset), "c" (shift)); |
|
| 596 |
- |
|
| 597 |
-# define RRX_OFFSET \ |
|
| 598 |
- asm(EMIT2(btl, KONST(0), VAR(C_FLAG)) \ |
|
| 599 |
- "rcr $1, %0" \ |
|
| 600 |
- : "=r" (offset) \ |
|
| 601 |
- : "0" (offset)); |
|
| 602 |
-# else // !__GNUC__, i.e. Visual C++ |
|
| 603 |
-# define ROR_IMM_MSR \ |
|
| 604 |
- __asm \ |
|
| 605 |
- { \
|
|
| 606 |
- __asm mov ecx, shift \ |
|
| 607 |
- __asm ror value, cl \ |
|
| 608 |
- } |
|
| 609 |
- |
|
| 610 |
-# define ROR_OFFSET \ |
|
| 611 |
- __asm \ |
|
| 612 |
- { \
|
|
| 613 |
- __asm mov ecx, shift \ |
|
| 614 |
- __asm ror offset, cl \ |
|
| 615 |
- } |
|
| 616 |
- |
|
| 617 |
-# define RRX_OFFSET \ |
|
| 618 |
- __asm \ |
|
| 619 |
- { \
|
|
| 620 |
- __asm bt dword ptr C_FLAG, 0 \ |
|
| 621 |
- __asm rcr offset, 1 \ |
|
| 622 |
- } |
|
| 623 |
-# endif // !__GNUC__ |
|
| 624 |
-# endif // !__POWERPC__ |
|
| 625 |
-#endif // !C_CORE |
|
| 626 |
- |
|
| 627 | 55 |
// C core |
| 628 | 56 |
|
| 629 | 57 |
#define C_SETCOND_LOGICAL \ |
| ... | ... |
@@ -641,15 +69,12 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }
|
| 641 | 69 |
V_FLAG = !!((NEG(lhs) & POS(rhs) & POS(res)) | (POS(lhs) & NEG(rhs) & NEG(res))); \ |
| 642 | 70 |
C_FLAG = !!((NEG(lhs) & POS(rhs)) | (NEG(lhs) & POS(res)) | (POS(rhs) & POS(res))); |
| 643 | 71 |
|
| 644 |
-#ifndef ALU_INIT_C |
|
| 645 |
-# define ALU_INIT_C \ |
|
| 72 |
+#define ALU_INIT_C \ |
|
| 646 | 73 |
int dest = (opcode >> 12) & 15; \ |
| 647 | 74 |
bool C_OUT = C_FLAG; \ |
| 648 | 75 |
uint32_t value; |
| 649 |
-#endif |
|
| 650 | 76 |
// OP Rd,Rb,Rm LSL # |
| 651 |
-#ifndef VALUE_LSL_IMM_C |
|
| 652 |
-# define VALUE_LSL_IMM_C \ |
|
| 77 |
+#define VALUE_LSL_IMM_C \ |
|
| 653 | 78 |
unsigned shift = (opcode >> 7) & 0x1F; \ |
| 654 | 79 |
if (LIKELY(!shift)) /* LSL #0 most common? */ \ |
| 655 | 80 |
value = reg[opcode & 0x0F].I; \ |
| ... | ... |
@@ -659,10 +84,8 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }
|
| 659 | 84 |
C_OUT = !!((v >> (32 - shift)) & 1); \ |
| 660 | 85 |
value = v << shift; \ |
| 661 | 86 |
} |
| 662 |
-#endif |
|
| 663 | 87 |
// OP Rd,Rb,Rm LSL Rs |
| 664 |
-#ifndef VALUE_LSL_REG_C |
|
| 665 |
-# define VALUE_LSL_REG_C \ |
|
| 88 |
+#define VALUE_LSL_REG_C \ |
|
| 666 | 89 |
uint32_t shift = reg[(opcode >> 8) & 15].B.B0; \ |
| 667 | 90 |
uint32_t rm = reg[opcode & 0x0F].I; \ |
| 668 | 91 |
if ((opcode & 0x0F) == 15) \ |
| ... | ... |
@@ -688,10 +111,8 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }
|
| 688 | 111 |
} \ |
| 689 | 112 |
else \ |
| 690 | 113 |
value = rm; |
| 691 |
-#endif |
|
| 692 | 114 |
// OP Rd,Rb,Rm LSR # |
| 693 |
-#ifndef VALUE_LSR_IMM_C |
|
| 694 |
-# define VALUE_LSR_IMM_C \ |
|
| 115 |
+#define VALUE_LSR_IMM_C \ |
|
| 695 | 116 |
uint32_t shift = (opcode >> 7) & 0x1F; \ |
| 696 | 117 |
if (LIKELY(shift)) \ |
| 697 | 118 |
{ \
|
| ... | ... |
@@ -704,10 +125,8 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }
|
| 704 | 125 |
value = 0; \ |
| 705 | 126 |
C_OUT = !!(reg[opcode & 0x0F].I & 0x80000000); \ |
| 706 | 127 |
} |
| 707 |
-#endif |
|
| 708 | 128 |
// OP Rd,Rb,Rm LSR Rs |
| 709 |
-#ifndef VALUE_LSR_REG_C |
|
| 710 |
-# define VALUE_LSR_REG_C \ |
|
| 129 |
+#define VALUE_LSR_REG_C \ |
|
| 711 | 130 |
unsigned shift = reg[(opcode >> 8) & 15].B.B0; \ |
| 712 | 131 |
uint32_t rm = reg[opcode & 0x0F].I; \ |
| 713 | 132 |
if ((opcode & 0x0F) == 15) \ |
| ... | ... |
@@ -733,10 +152,8 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }
|
| 733 | 152 |
} \ |
| 734 | 153 |
else \ |
| 735 | 154 |
value = rm; |
| 736 |
-#endif |
|
| 737 | 155 |
// OP Rd,Rb,Rm ASR # |
| 738 |
-#ifndef VALUE_ASR_IMM_C |
|
| 739 |
-# define VALUE_ASR_IMM_C \ |
|
| 156 |
+#define VALUE_ASR_IMM_C \ |
|
| 740 | 157 |
unsigned shift = (opcode >> 7) & 0x1F; \ |
| 741 | 158 |
if (LIKELY(shift)) \ |
| 742 | 159 |
{ \
|
| ... | ... |
@@ -758,10 +175,8 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }
|
| 758 | 175 |
C_OUT = false; \ |
| 759 | 176 |
} \ |
| 760 | 177 |
} |
| 761 |
-#endif |
|
| 762 | 178 |
// OP Rd,Rb,Rm ASR Rs |
| 763 |
-#ifndef VALUE_ASR_REG_C |
|
| 764 |
-# define VALUE_ASR_REG_C \ |
|
| 179 |
+#define VALUE_ASR_REG_C \ |
|
| 765 | 180 |
unsigned shift = reg[(opcode >> 8) & 15].B.B0; \ |
| 766 | 181 |
uint32_t rm = reg[opcode & 0x0F].I; \ |
| 767 | 182 |
if ((opcode & 0x0F) == 15) \ |
| ... | ... |
@@ -790,10 +205,8 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }
|
| 790 | 205 |
C_OUT = false; \ |
| 791 | 206 |
} \ |
| 792 | 207 |
} |
| 793 |
-#endif |
|
| 794 | 208 |
// OP Rd,Rb,Rm ROR # |
| 795 |
-#ifndef VALUE_ROR_IMM_C |
|
| 796 |
-# define VALUE_ROR_IMM_C \ |
|
| 209 |
+#define VALUE_ROR_IMM_C \ |
|
| 797 | 210 |
unsigned shift = (opcode >> 7) & 0x1F; \ |
| 798 | 211 |
uint32_t v = reg[opcode & 0x0F].I; \ |
| 799 | 212 |
if (LIKELY(shift)) \ |
| ... | ... |
@@ -806,10 +219,8 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }
|
| 806 | 219 |
C_OUT = !!(v & 1); \ |
| 807 | 220 |
value = (v >> 1) | (C_FLAG << 31); \ |
| 808 | 221 |
} |
| 809 |
-#endif |
|
| 810 | 222 |
// OP Rd,Rb,Rm ROR Rs |
| 811 |
-#ifndef VALUE_ROR_REG_C |
|
| 812 |
-# define VALUE_ROR_REG_C \ |
|
| 223 |
+#define VALUE_ROR_REG_C \ |
|
| 813 | 224 |
unsigned shift = reg[(opcode >> 8) & 15].B.B0; \ |
| 814 | 225 |
uint32_t rm = reg[opcode & 0x0F].I; \ |
| 815 | 226 |
if ((opcode & 0x0F) == 15) \ |
| ... | ... |
@@ -826,10 +237,8 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }
|
| 826 | 237 |
if (shift) \ |
| 827 | 238 |
C_OUT = !!(value & 0x80000000); \ |
| 828 | 239 |
} |
| 829 |
-#endif |
|
| 830 | 240 |
// OP Rd,Rb,# ROR # |
| 831 |
-#ifndef VALUE_IMM_C |
|
| 832 |
-# define VALUE_IMM_C \ |
|
| 241 |
+#define VALUE_IMM_C \ |
|
| 833 | 242 |
int shift = (opcode & 0xF00) >> 7; \ |
| 834 | 243 |
if (UNLIKELY(shift)) \ |
| 835 | 244 |
{ \
|
| ... | ... |
@@ -839,206 +248,115 @@ template<typename T> static inline T POS(const T &i) { return ~i >> 31; }
|
| 839 | 248 |
} \ |
| 840 | 249 |
else \ |
| 841 | 250 |
value = opcode & 0xFF; |
| 842 |
-#endif |
|
| 843 | 251 |
|
| 844 | 252 |
// Make the non-carry versions default to the carry versions |
| 845 | 253 |
// (this is fine for C--the compiler will optimize the dead code out) |
| 846 |
-#ifndef ALU_INIT_NC |
|
| 847 |
-# define ALU_INIT_NC ALU_INIT_C |
|
| 848 |
-#endif |
|
| 849 |
-#ifndef VALUE_LSL_IMM_NC |
|
| 850 |
-# define VALUE_LSL_IMM_NC VALUE_LSL_IMM_C |
|
| 851 |
-#endif |
|
| 852 |
-#ifndef VALUE_LSL_REG_NC |
|
| 853 |
-# define VALUE_LSL_REG_NC VALUE_LSL_REG_C |
|
| 854 |
-#endif |
|
| 855 |
-#ifndef VALUE_LSR_IMM_NC |
|
| 856 |
-# define VALUE_LSR_IMM_NC VALUE_LSR_IMM_C |
|
| 857 |
-#endif |
|
| 858 |
-#ifndef VALUE_LSR_REG_NC |
|
| 859 |
-# define VALUE_LSR_REG_NC VALUE_LSR_REG_C |
|
| 860 |
-#endif |
|
| 861 |
-#ifndef VALUE_ASR_IMM_NC |
|
| 862 |
-# define VALUE_ASR_IMM_NC VALUE_ASR_IMM_C |
|
| 863 |
-#endif |
|
| 864 |
-#ifndef VALUE_ASR_REG_NC |
|
| 865 |
-# define VALUE_ASR_REG_NC VALUE_ASR_REG_C |
|
| 866 |
-#endif |
|
| 867 |
-#ifndef VALUE_ROR_IMM_NC |
|
| 868 |
-# define VALUE_ROR_IMM_NC VALUE_ROR_IMM_C |
|
| 869 |
-#endif |
|
| 870 |
-#ifndef VALUE_ROR_REG_NC |
|
| 871 |
-# define VALUE_ROR_REG_NC VALUE_ROR_REG_C |
|
| 872 |
-#endif |
|
| 873 |
-#ifndef VALUE_IMM_NC |
|
| 874 |
-# define VALUE_IMM_NC VALUE_IMM_C |
|
| 875 |
-#endif |
|
| 254 |
+#define ALU_INIT_NC ALU_INIT_C |
|
| 255 |
+#define VALUE_LSL_IMM_NC VALUE_LSL_IMM_C |
|
| 256 |
+#define VALUE_LSL_REG_NC VALUE_LSL_REG_C |
|
| 257 |
+#define VALUE_LSR_IMM_NC VALUE_LSR_IMM_C |
|
| 258 |
+#define VALUE_LSR_REG_NC VALUE_LSR_REG_C |
|
| 259 |
+#define VALUE_ASR_IMM_NC VALUE_ASR_IMM_C |
|
| 260 |
+#define VALUE_ASR_REG_NC VALUE_ASR_REG_C |
|
| 261 |
+#define VALUE_ROR_IMM_NC VALUE_ROR_IMM_C |
|
| 262 |
+#define VALUE_ROR_REG_NC VALUE_ROR_REG_C |
|
| 263 |
+#define VALUE_IMM_NC VALUE_IMM_C |
|
| 876 | 264 |
|
| 877 | 265 |
#define C_CHECK_PC(SETCOND) if (LIKELY(dest != 15)) { SETCOND }
|
| 878 |
-#ifndef OP_AND |
|
| 879 |
-# define OP_AND \ |
|
| 266 |
+#define OP_AND \ |
|
| 880 | 267 |
uint32_t res = reg[(opcode >> 16) & 15].I & value; \ |
| 881 |
- reg[dest].I = res; |
|
| 882 |
-#endif |
|
| 883 |
-#ifndef OP_ANDS |
|
| 884 |
-# define OP_ANDS OP_AND C_CHECK_PC(C_SETCOND_LOGICAL) |
|
| 885 |
-#endif |
|
| 886 |
-#ifndef OP_EOR |
|
| 887 |
-# define OP_EOR \ |
|
| 268 |
+ reg[dest].I = res; |
|
| 269 |
+#define OP_ANDS OP_AND C_CHECK_PC(C_SETCOND_LOGICAL) |
|
| 270 |
+#define OP_EOR \ |
|
| 888 | 271 |
uint32_t res = reg[(opcode >> 16) & 15].I ^ value; \ |
| 889 | 272 |
reg[dest].I = res; |
| 890 |
-#endif |
|
| 891 |
-#ifndef OP_EORS |
|
| 892 |
-# define OP_EORS OP_EOR C_CHECK_PC(C_SETCOND_LOGICAL) |
|
| 893 |
-#endif |
|
| 894 |
-#ifndef OP_SUB |
|
| 895 |
-# define OP_SUB \ |
|
| 273 |
+#define OP_EORS OP_EOR C_CHECK_PC(C_SETCOND_LOGICAL) |
|
| 274 |
+#define OP_SUB \ |
|
| 896 | 275 |
uint32_t lhs = reg[(opcode >> 16) & 15].I; \ |
| 897 | 276 |
uint32_t rhs = value; \ |
| 898 | 277 |
uint32_t res = lhs - rhs; \ |
| 899 | 278 |
reg[dest].I = res; |
| 900 |
-#endif |
|
| 901 |
-#ifndef OP_SUBS |
|
| 902 |
-# define OP_SUBS OP_SUB C_CHECK_PC(C_SETCOND_SUB) |
|
| 903 |
-#endif |
|
| 904 |
-#ifndef OP_RSB |
|
| 905 |
-# define OP_RSB \ |
|
| 279 |
+#define OP_SUBS OP_SUB C_CHECK_PC(C_SETCOND_SUB) |
|
| 280 |
+#define OP_RSB \ |
|
| 906 | 281 |
uint32_t lhs = value; \ |
| 907 | 282 |
uint32_t rhs = reg[(opcode >> 16) & 15].I; \ |
| 908 | 283 |
uint32_t res = lhs - rhs; \ |
| 909 | 284 |
reg[dest].I = res; |
| 910 |
-#endif |
|
| 911 |
-#ifndef OP_RSBS |
|
| 912 |
-# define OP_RSBS OP_RSB C_CHECK_PC(C_SETCOND_SUB) |
|
| 913 |
-#endif |
|
| 914 |
-#ifndef OP_ADD |
|
| 915 |
-# define OP_ADD \ |
|
| 285 |
+#define OP_RSBS OP_RSB C_CHECK_PC(C_SETCOND_SUB) |
|
| 286 |
+#define OP_ADD \ |
|
| 916 | 287 |
uint32_t lhs = reg[(opcode >> 16) & 15].I; \ |
| 917 | 288 |
uint32_t rhs = value; \ |
| 918 | 289 |
uint32_t res = lhs + rhs; \ |
| 919 | 290 |
reg[dest].I = res; |
| 920 |
-#endif |
|
| 921 |
-#ifndef OP_ADDS |
|
| 922 |
-# define OP_ADDS OP_ADD C_CHECK_PC(C_SETCOND_ADD) |
|
| 923 |
-#endif |
|
| 924 |
-#ifndef OP_ADC |
|
| 925 |
-# define OP_ADC \ |
|
| 291 |
+#define OP_ADDS OP_ADD C_CHECK_PC(C_SETCOND_ADD) |
|
| 292 |
+#define OP_ADC \ |
|
| 926 | 293 |
uint32_t lhs = reg[(opcode >> 16) & 15].I; \ |
| 927 | 294 |
uint32_t rhs = value; \ |
| 928 | 295 |
uint32_t res = lhs + rhs + static_cast<uint32_t>(C_FLAG); \ |
| 929 | 296 |
reg[dest].I = res; |
| 930 |
-#endif |
|
| 931 |
-#ifndef OP_ADCS |
|
| 932 |
-# define OP_ADCS OP_ADC C_CHECK_PC(C_SETCOND_ADD) |
|
| 933 |
-#endif |
|
| 934 |
-#ifndef OP_SBC |
|
| 935 |
-# define OP_SBC \ |
|
| 297 |
+#define OP_ADCS OP_ADC C_CHECK_PC(C_SETCOND_ADD) |
|
| 298 |
+#define OP_SBC \ |
|
| 936 | 299 |
uint32_t lhs = reg[(opcode >> 16) & 15].I; \ |
| 937 | 300 |
uint32_t rhs = value; \ |
| 938 | 301 |
uint32_t res = lhs - rhs - !static_cast<uint32_t>(C_FLAG); \ |
| 939 | 302 |
reg[dest].I = res; |
| 940 |
-#endif |
|
| 941 |
-#ifndef OP_SBCS |
|
| 942 |
-# define OP_SBCS OP_SBC C_CHECK_PC(C_SETCOND_SUB) |
|
| 943 |
-#endif |
|
| 944 |
-#ifndef OP_RSC |
|
| 945 |
-# define OP_RSC \ |
|
| 303 |
+#define OP_SBCS OP_SBC C_CHECK_PC(C_SETCOND_SUB) |
|
| 304 |
+#define OP_RSC \ |
|
| 946 | 305 |
uint32_t lhs = value; \ |
| 947 | 306 |
uint32_t rhs = reg[(opcode >> 16) & 15].I; \ |
| 948 | 307 |
uint32_t res = lhs - rhs - !static_cast<uint32_t>(C_FLAG); \ |
| 949 | 308 |
reg[dest].I = res; |
| 950 |
-#endif |
|
| 951 |
-#ifndef OP_RSCS |
|
| 952 |
-# define OP_RSCS OP_RSC C_CHECK_PC(C_SETCOND_SUB) |
|
| 953 |
-#endif |
|
| 954 |
-#ifndef OP_TST |
|
| 955 |
-# define OP_TST \ |
|
| 309 |
+#define OP_RSCS OP_RSC C_CHECK_PC(C_SETCOND_SUB) |
|
| 310 |
+#define OP_TST \ |
|
| 956 | 311 |
uint32_t res = reg[(opcode >> 16) & 0x0F].I & value; \ |
| 957 | 312 |
C_SETCOND_LOGICAL; |
| 958 |
-#endif |
|
| 959 |
-#ifndef OP_TEQ |
|
| 960 |
-# define OP_TEQ \ |
|
| 313 |
+#define OP_TEQ \ |
|
| 961 | 314 |
uint32_t res = reg[(opcode >> 16) & 0x0F].I ^ value; \ |
| 962 | 315 |
C_SETCOND_LOGICAL; |
| 963 |
-#endif |
|
| 964 |
-#ifndef OP_CMP |
|
| 965 |
-# define OP_CMP \ |
|
| 316 |
+#define OP_CMP \ |
|
| 966 | 317 |
uint32_t lhs = reg[(opcode >> 16) & 15].I; \ |
| 967 | 318 |
uint32_t rhs = value; \ |
| 968 | 319 |
uint32_t res = lhs - rhs; \ |
| 969 | 320 |
C_SETCOND_SUB; |
| 970 |
-#endif |
|
| 971 |
-#ifndef OP_CMN |
|
| 972 |
-# define OP_CMN \ |
|
| 321 |
+#define OP_CMN \ |
|
| 973 | 322 |
uint32_t lhs = reg[(opcode >> 16) & 15].I; \ |
| 974 | 323 |
uint32_t rhs = value; \ |
| 975 | 324 |
uint32_t res = lhs + rhs; \ |
| 976 | 325 |
C_SETCOND_ADD; |
| 977 |
-#endif |
|
| 978 |
-#ifndef OP_ORR |
|
| 979 |
-# define OP_ORR \ |
|
| 326 |
+#define OP_ORR \ |
|
| 980 | 327 |
uint32_t res = reg[(opcode >> 16) & 0x0F].I | value; \ |
| 981 | 328 |
reg[dest].I = res; |
| 982 |
-#endif |
|
| 983 |
-#ifndef OP_ORRS |
|
| 984 |
-# define OP_ORRS OP_ORR C_CHECK_PC(C_SETCOND_LOGICAL) |
|
| 985 |
-#endif |
|
| 986 |
-#ifndef OP_MOV |
|
| 987 |
-# define OP_MOV \ |
|
| 329 |
+#define OP_ORRS OP_ORR C_CHECK_PC(C_SETCOND_LOGICAL) |
|
| 330 |
+#define OP_MOV \ |
|
| 988 | 331 |
uint32_t res = value; \ |
| 989 | 332 |
reg[dest].I = res; |
| 990 |
-#endif |
|
| 991 |
-#ifndef OP_MOVS |
|
| 992 |
-# define OP_MOVS OP_MOV C_CHECK_PC(C_SETCOND_LOGICAL) |
|
| 993 |
-#endif |
|
| 994 |
-#ifndef OP_BIC |
|
| 995 |
-# define OP_BIC \ |
|
| 333 |
+#define OP_MOVS OP_MOV C_CHECK_PC(C_SETCOND_LOGICAL) |
|
| 334 |
+#define OP_BIC \ |
|
| 996 | 335 |
uint32_t res = reg[(opcode >> 16) & 0x0F].I & ~value; \ |
| 997 | 336 |
reg[dest].I = res; |
| 998 |
-#endif |
|
| 999 |
-#ifndef OP_BICS |
|
| 1000 |
-# define OP_BICS OP_BIC C_CHECK_PC(C_SETCOND_LOGICAL) |
|
| 1001 |
-#endif |
|
| 1002 |
-#ifndef OP_MVN |
|
| 1003 |
-# define OP_MVN \ |
|
| 337 |
+#define OP_BICS OP_BIC C_CHECK_PC(C_SETCOND_LOGICAL) |
|
| 338 |
+#define OP_MVN \ |
|
| 1004 | 339 |
uint32_t res = ~value; \ |
| 1005 | 340 |
reg[dest].I = res; |
| 1006 |
-#endif |
|
| 1007 |
-#ifndef OP_MVNS |
|
| 1008 |
-# define OP_MVNS OP_MVN C_CHECK_PC(C_SETCOND_LOGICAL) |
|
| 1009 |
-#endif |
|
| 341 |
+#define OP_MVNS OP_MVN C_CHECK_PC(C_SETCOND_LOGICAL) |
|
| 1010 | 342 |
|
| 1011 |
-#ifndef SETCOND_NONE |
|
| 1012 |
-# define SETCOND_NONE /*nothing*/ |
|
| 1013 |
-#endif |
|
| 1014 |
-#ifndef SETCOND_MUL |
|
| 1015 |
-# define SETCOND_MUL \ |
|
| 343 |
+#define SETCOND_NONE /*nothing*/ |
|
| 344 |
+#define SETCOND_MUL \ |
|
| 1016 | 345 |
N_FLAG = static_cast<int32_t>(reg[dest].I) < 0; \ |
| 1017 | 346 |
Z_FLAG = !reg[dest].I; |
| 1018 |
-#endif |
|
| 1019 |
-#ifndef SETCOND_MULL |
|
| 1020 |
-# define SETCOND_MULL \ |
|
| 347 |
+#define SETCOND_MULL \ |
|
| 1021 | 348 |
N_FLAG = !!(reg[dest].I & 0x80000000); \ |
| 1022 | 349 |
Z_FLAG = !(reg[dest].I || reg[acc].I); |
| 1023 |
-#endif |
|
| 1024 | 350 |
|
| 1025 |
-#ifndef ALU_FINISH |
|
| 1026 |
-# define ALU_FINISH /*nothing*/ |
|
| 1027 |
-#endif |
|
| 351 |
+#define ALU_FINISH /*nothing*/ |
|
| 1028 | 352 |
|
| 1029 |
-#ifndef ROR_IMM_MSR |
|
| 1030 |
-# define ROR_IMM_MSR \ |
|
| 353 |
+#define ROR_IMM_MSR \ |
|
| 1031 | 354 |
uint32_t v = opcode & 0xff; \ |
| 1032 | 355 |
value = (v << (32 - shift)) | (v >> shift); |
| 1033 |
-#endif |
|
| 1034 |
-#ifndef ROR_OFFSET |
|
| 1035 |
-# define ROR_OFFSET \ |
|
| 356 |
+#define ROR_OFFSET \ |
|
| 1036 | 357 |
offset = (offset << (32 - shift)) | (offset >> shift); |
| 1037 |
-#endif |
|
| 1038 |
-#ifndef RRX_OFFSET |
|
| 1039 |
-# define RRX_OFFSET \ |
|
| 358 |
+#define RRX_OFFSET \ |
|
| 1040 | 359 |
offset = (offset >> 1) | (static_cast<int>(C_FLAG) << 31); |
| 1041 |
-#endif |
|
| 1042 | 360 |
|
| 1043 | 361 |
// ALU ops (except multiply) ////////////////////////////////////////////// |
| 1044 | 362 |
|
| ... | ... |
@@ -1461,13 +779,9 @@ static INSN_REGPARM void arm121(uint32_t opcode) |
| 1461 | 779 |
int shift = (opcode >> 7) & 31; \ |
| 1462 | 780 |
uint32_t offset = reg[opcode & 15].I; \ |
| 1463 | 781 |
if (shift) \ |
| 1464 |
- { \
|
|
| 1465 |
- ROR_OFFSET; \ |
|
| 1466 |
- } \ |
|
| 782 |
+ ROR_OFFSET \ |
|
| 1467 | 783 |
else \ |
| 1468 |
- { \
|
|
| 1469 |
- RRX_OFFSET; \ |
|
| 1470 |
- } |
|
| 784 |
+ RRX_OFFSET |
|
| 1471 | 785 |
|
| 1472 | 786 |
#define ADDRESS_POST (reg[base].I) |
| 1473 | 787 |
#define ADDRESS_PREDEC (reg[base].I - offset) |
| ... | ... |
@@ -2241,9 +1555,9 @@ static INSN_REGPARM void arm8A0(uint32_t opcode) |
| 2241 | 1555 |
if (!busPrefetchCount) |
| 2242 | 1556 |
busPrefetch = busPrefetchEnable; |
| 2243 | 1557 |
int base = (opcode & 0x000F0000) >> 16; |
| 2244 |
- uint32_t temp = reg[base].I + 4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]); |
|
| 2245 | 1558 |
uint32_t address = reg[base].I & 0xFFFFFFFC; |
| 2246 | 1559 |
int count = 0; |
| 1560 |
+ uint32_t temp = reg[base].I + 4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]); |
|
| 2247 | 1561 |
STMW_ALL; |
| 2248 | 1562 |
clockTicks += 1 + codeTicksAccess32(armNextPC); |
| 2249 | 1563 |
} |
| ... | ... |
@@ -2294,9 +1608,9 @@ static INSN_REGPARM void arm8E0(uint32_t opcode) |
| 2294 | 1608 |
if (!busPrefetchCount) |
| 2295 | 1609 |
busPrefetch = busPrefetchEnable; |
| 2296 | 1610 |
int base = (opcode & 0x000F0000) >> 16; |
| 2297 |
- uint32_t temp = reg[base].I + 4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]); |
|
| 2298 | 1611 |
uint32_t address = reg[base].I & 0xFFFFFFFC; |
| 2299 | 1612 |
int count = 0; |
| 1613 |
+ uint32_t temp = reg[base].I + 4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]); |
|
| 2300 | 1614 |
STMW_ALL_2; |
| 2301 | 1615 |
clockTicks += 1 + codeTicksAccess32(armNextPC); |
| 2302 | 1616 |
} |
| ... | ... |
@@ -2457,9 +1771,9 @@ static INSN_REGPARM void arm9A0(uint32_t opcode) |
| 2457 | 1771 |
if (!busPrefetchCount) |
| 2458 | 1772 |
busPrefetch = busPrefetchEnable; |
| 2459 | 1773 |
int base = (opcode & 0x000F0000) >> 16; |
| 2460 |
- uint32_t temp = reg[base].I + 4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]); |
|
| 2461 | 1774 |
uint32_t address = (reg[base].I + 4) & 0xFFFFFFFC; |
| 2462 | 1775 |
int count = 0; |
| 1776 |
+ uint32_t temp = reg[base].I + 4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]); |
|
| 2463 | 1777 |
STMW_ALL; |
| 2464 | 1778 |
clockTicks += 1 + codeTicksAccess32(armNextPC); |
| 2465 | 1779 |
} |
| ... | ... |
@@ -2510,9 +1824,9 @@ static INSN_REGPARM void arm9E0(uint32_t opcode) |
| 2510 | 1824 |
if (!busPrefetchCount) |
| 2511 | 1825 |
busPrefetch = busPrefetchEnable; |
| 2512 | 1826 |
int base = (opcode & 0x000F0000) >> 16; |
| 2513 |
- uint32_t temp = reg[base].I + 4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]); |
|
| 2514 | 1827 |
uint32_t address = (reg[base].I + 4) & 0xFFFFFFFC; |
| 2515 | 1828 |
int count = 0; |
| 1829 |
+ uint32_t temp = reg[base].I + 4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]); |
|
| 2516 | 1830 |
STMW_ALL_2; |
| 2517 | 1831 |
clockTicks += 1 + codeTicksAccess32(armNextPC); |
| 2518 | 1832 |
} |
| ... | ... |
@@ -2766,7 +2080,7 @@ static insnfunc_t armInsnTable[] = |
| 2766 | 2080 |
REP16(arm_UI),REP16(arm_UI),REP16(arm_UI),REP16(arm_UI), // E80 |
| 2767 | 2081 |
REP16(arm_UI),REP16(arm_UI),REP16(arm_UI),REP16(arm_UI), // EC0 |
| 2768 | 2082 |
|
| 2769 |
- REP256(armF00), // F00 |
|
| 2083 |
+ REP256(armF00) // F00 |
|
| 2770 | 2084 |
}; |
| 2771 | 2085 |
|
| 2772 | 2086 |
// Wrapper routine (execution loop) /////////////////////////////////////// |
| ... | ... |
@@ -19,671 +19,27 @@ static INSN_REGPARM void thumbUnknownInsn(uint32_t opcode) |
| 19 | 19 |
template<typename T> static inline T NEG(const T &i) { return i >> 31; }
|
| 20 | 20 |
template<typename T> static inline T POS(const T &i) { return ~i >> 31; }
|
| 21 | 21 |
|
| 22 |
-#ifndef C_CORE |
|
| 23 |
-# ifdef __GNUC__ |
|
| 24 |
-# ifdef __POWERPC__ |
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| 25 |
-# define ADD_RD_RS_RN(N) \ |
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| 26 |
-{ \
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| 27 |
- register int Flags; \ |
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| 28 |
- register int Result; \ |
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| 29 |
- asm volatile("addco. %0, %2, %3\n" \
|
|
| 30 |
- "mcrxr cr1\n" \ |
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| 31 |
- "mfcr %1\n" \ |
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| 32 |
- : "=r" (Result), \ |
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| 33 |
- "=r" (Flags) \ |
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| 34 |
- : "r" (reg[source].I), \ |
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| 35 |
- "r" (reg[N].I) \ |
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| 36 |
- ); \ |
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| 37 |
- reg[dest].I = Result; \ |
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| 38 |
- Z_FLAG = (Flags >> 29) & 1; \ |
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| 39 |
- N_FLAG = (Flags >> 31) & 1; \ |
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| 40 |
- C_FLAG = (Flags >> 25) & 1; \ |
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| 41 |
- V_FLAG = (Flags >> 26) & 1; \ |
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| 42 |
-} |
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| 43 |
-# define ADD_RD_RS_O3(N) \ |
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| 44 |
-{ \
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| 45 |
- register int Flags; \ |
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| 46 |
- register int Result; \ |
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| 47 |
- asm volatile("addco. %0, %2, %3\n" \
|
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| 48 |
- "mcrxr cr1\n" \ |
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| 49 |
- "mfcr %1\n" \ |
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| 50 |
- : "=r" (Result), \ |
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| 51 |
- "=r" (Flags) \ |
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| 52 |
- : "r" (reg[source].I), \ |
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| 53 |
- "r" (N) \ |
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| 54 |
- ); \ |
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| 55 |
- reg[dest].I = Result; \ |
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| 56 |
- Z_FLAG = (Flags >> 29) & 1; \ |
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| 57 |
- N_FLAG = (Flags >> 31) & 1; \ |
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| 58 |
- C_FLAG = (Flags >> 25) & 1; \ |
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| 59 |
- V_FLAG = (Flags >> 26) & 1; \ |
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| 60 |
-} |
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| 61 |
-# define ADD_RD_RS_O3_0 ADD_RD_RS_O3 |
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| 62 |
-# define ADD_RN_O8(d) \ |
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| 63 |
-{ \
|
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| 64 |
- register int Flags; \ |
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| 65 |
- register int Result; \ |
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| 66 |
- asm volatile("addco. %0, %2, %3\n" \
|
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| 67 |
- "mcrxr cr1\n" \ |
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| 68 |
- "mfcr %1\n" \ |
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| 69 |
- : "=r" (Result), \ |
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| 70 |
- "=r" (Flags) \ |
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| 71 |
- : "r" (reg[(d)].I), \ |
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| 72 |
- "r" (opcode & 255) \ |
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| 73 |
- ); \ |
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| 74 |
- reg[(d)].I = Result; \ |
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| 75 |
- Z_FLAG = (Flags >> 29) & 1; \ |
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| 76 |
- N_FLAG = (Flags >> 31) & 1; \ |
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| 77 |
- C_FLAG = (Flags >> 25) & 1; \ |
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| 78 |
- V_FLAG = (Flags >> 26) & 1; \ |
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| 79 |
-} |
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| 80 |
-# define CMN_RD_RS \ |
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| 81 |
-{ \
|
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| 82 |
- register int Flags; \ |
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| 83 |
- register int Result; \ |
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| 84 |
- asm volatile("addco. %0, %2, %3\n" \
|
|
| 85 |
- "mcrxr cr1\n" \ |
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| 86 |
- "mfcr %1\n" \ |
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| 87 |
- : "=r" (Result), \ |
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| 88 |
- "=r" (Flags) \ |
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| 89 |
- : "r" (reg[dest].I), \ |
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| 90 |
- "r" (value) \ |
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| 91 |
- ); \ |
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| 92 |
- Z_FLAG = (Flags >> 29) & 1; \ |
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| 93 |
- N_FLAG = (Flags >> 31) & 1; \ |
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| 94 |
- C_FLAG = (Flags >> 25) & 1; \ |
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| 95 |
- V_FLAG = (Flags >> 26) & 1; \ |
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| 96 |
-} |
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| 97 |
-# define ADC_RD_RS \ |
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| 98 |
-{ \
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| 99 |
- register int Flags; \ |
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| 100 |
- register int Result; \ |
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| 101 |
- asm volatile("mtspr 1, %4\n" \ /* reg 1 is xer */
|
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| 102 |
- "addeo. %0, %2, %3\n" \ |
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| 103 |
- "mcrxr cr1\n" \ |
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| 104 |
- "mfcr %1\n" \ |
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| 105 |
- : "=r" (Result), \ |
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| 106 |
- "=r" (Flags) \ |
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| 107 |
- : "r" (reg[dest].I), \ |
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| 108 |
- "r" (value), \ |
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| 109 |
- "r" (C_FLAG << 29) \ |
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| 110 |
- ); \ |
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| 111 |
- reg[dest].I = Result; \ |
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| 112 |
- Z_FLAG = (Flags >> 29) & 1; \ |
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| 113 |
- N_FLAG = (Flags >> 31) & 1; \ |
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| 114 |
- C_FLAG = (Flags >> 25) & 1; \ |
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| 115 |
- V_FLAG = (Flags >> 26) & 1; \ |
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| 116 |
-} |
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| 117 |
-# define SUB_RD_RS_RN(N) \ |
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| 118 |
-{ \
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| 119 |
- register int Flags; \ |
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| 120 |
- register int Result; \ |
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| 121 |
- asm volatile("subco. %0, %2, %3\n" \
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| 122 |
- "mcrxr cr1\n" \ |
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| 123 |
- "mfcr %1\n" \ |
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| 124 |
- : "=r" (Result), \ |
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| 125 |
- "=r" (Flags) \ |
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| 126 |
- : "r" (reg[source].I), \ |
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| 127 |
- "r" (reg[N].I) \ |
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| 128 |
- ); \ |
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| 129 |
- reg[dest].I = Result; \ |
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| 130 |
- Z_FLAG = (Flags >> 29) & 1; \ |
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| 131 |
- N_FLAG = (Flags >> 31) & 1; \ |
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| 132 |
- C_FLAG = (Flags >> 25) & 1; \ |
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| 133 |
- V_FLAG = (Flags >> 26) & 1; \ |
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| 134 |
-} |
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| 135 |
-# define SUB_RD_RS_O3(N) \ |
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| 136 |
-{ \
|
|
| 137 |
- register int Flags; \ |
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| 138 |
- register int Result; \ |
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| 139 |
- asm volatile("subco. %0, %2, %3\n" \
|
|
| 140 |
- "mcrxr cr1\n" \ |
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| 141 |
- "mfcr %1\n" \ |
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| 142 |
- : "=r" (Result), \ |
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| 143 |
- "=r" (Flags) \ |
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| 144 |
- : "r" (reg[source].I), \ |
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| 145 |
- "r" (N) \ |
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| 146 |
- ); \ |
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| 147 |
- reg[dest].I = Result; \ |
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| 148 |
- Z_FLAG = (Flags >> 29) & 1; \ |
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| 149 |
- N_FLAG = (Flags >> 31) & 1; \ |
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| 150 |
- C_FLAG = (Flags >> 25) & 1; \ |
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| 151 |
- V_FLAG = (Flags >> 26) & 1; \ |
|
| 152 |
-} |
|
| 153 |
-# define SUB_RD_RS_O3_0 SUB_RD_RS_O3 |
|
| 154 |
-# define SUB_RN_O8(d) \ |
|
| 155 |
-{ \
|
|
| 156 |
- register int Flags; \ |
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| 157 |
- register int Result; \ |
|
| 158 |
- asm volatile("subco. %0, %2, %3\n" \
|
|
| 159 |
- "mcrxr cr1\n" \ |
|
| 160 |
- "mfcr %1\n" \ |
|
| 161 |
- : "=r" (Result), \ |
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| 162 |
- "=r" (Flags) \ |
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| 163 |
- : "r" (reg[(d)].I), \ |
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| 164 |
- "r" (opcode & 255) \ |
|
| 165 |
- ); \ |
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| 166 |
- reg[(d)].I = Result; \ |
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| 167 |
- Z_FLAG = (Flags >> 29) & 1; \ |
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| 168 |
- N_FLAG = (Flags >> 31) & 1; \ |
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| 169 |
- C_FLAG = (Flags >> 25) & 1; \ |
|
| 170 |
- V_FLAG = (Flags >> 26) & 1; \ |
|
| 171 |
-} |
|
| 172 |
-# define CMP_RN_O8(d) \ |
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| 173 |
-{ \
|
|
| 174 |
- register int Flags; \ |
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| 175 |
- register int Result; \ |
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| 176 |
- asm volatile("subco. %0, %2, %3\n" \
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|
| 177 |
- "mcrxr cr1\n" \ |
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| 178 |
- "mfcr %1\n" \ |
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| 179 |
- : "=r" (Result), \ |
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| 180 |
- "=r" (Flags) \ |
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| 181 |
- : "r" (reg[(d)].I), \ |
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| 182 |
- "r" (opcode & 255) \ |
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| 183 |
- ); \ |
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| 184 |
- Z_FLAG = (Flags >> 29) & 1; \ |
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| 185 |
- N_FLAG = (Flags >> 31) & 1; \ |
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| 186 |
- C_FLAG = (Flags >> 25) & 1; \ |
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| 187 |
- V_FLAG = (Flags >> 26) & 1; \ |
|
| 188 |
-} |
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| 189 |
-# define SBC_RD_RS \ |
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| 190 |
-{ \
|
|
| 191 |
- register int Flags; \ |
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| 192 |
- register int Result; \ |
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| 193 |
- asm volatile("mtspr 1, %4\n" \ /* reg 1 is xer */
|
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| 194 |
- "subfeo. %0, %3, %2\n" \ |
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| 195 |
- "mcrxr cr1\n" \ |
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| 196 |
- "mfcr %1\n" \ |
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| 197 |
- : "=r" (Result), \ |
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| 198 |
- "=r" (Flags) \ |
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| 199 |
- : "r" (reg[dest].I), \ |
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| 200 |
- "r" (value), \ |
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| 201 |
- "r" (C_FLAG << 29) \ |
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| 202 |
- ); \ |
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| 203 |
- reg[dest].I = Result; \ |
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| 204 |
- Z_FLAG = (Flags >> 29) & 1; \ |
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| 205 |
- N_FLAG = (Flags >> 31) & 1; \ |
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| 206 |
- C_FLAG = (Flags >> 25) & 1; \ |
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| 207 |
- V_FLAG = (Flags >> 26) & 1; \ |
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| 208 |
-} |
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| 209 |
-# define NEG_RD_RS \ |
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| 210 |
-{ \
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|
| 211 |
- register int Flags; \ |
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| 212 |
- register int Result; \ |
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| 213 |
- asm volatile("subfco. %0, %2, %3\n" \
|
|
| 214 |
- "mcrxr cr1\n" \ |
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| 215 |
- "mfcr %1\n" \ |
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| 216 |
- : "=r" (Result), \ |
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| 217 |
- "=r" (Flags) \ |
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| 218 |
- : "r" (reg[source].I), \ |
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| 219 |
- "r" (0) \ |
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| 220 |
- ); \ |
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| 221 |
- reg[dest].I = Result; \ |
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| 222 |
- Z_FLAG = (Flags >> 29) & 1; \ |
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| 223 |
- N_FLAG = (Flags >> 31) & 1; \ |
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| 224 |
- C_FLAG = (Flags >> 25) & 1; \ |
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| 225 |
- V_FLAG = (Flags >> 26) & 1; \ |
|
| 226 |
-} |
|
| 227 |
-# define CMP_RD_RS \ |
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| 228 |
-{ \
|
|
| 229 |
- register int Flags; \ |
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| 230 |
- register int Result; \ |
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| 231 |
- asm volatile("subco. %0, %2, %3\n" \
|
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| 232 |
- "mcrxr cr1\n" \ |
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| 233 |
- "mfcr %1\n" \ |
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| 234 |
- : "=r" (Result), \ |
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| 235 |
- "=r" (Flags) \ |
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| 236 |
- : "r" (reg[dest].I), \ |
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| 237 |
- "r" (value) \ |
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| 238 |
- ); \ |
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| 239 |
- Z_FLAG = (Flags >> 29) & 1; \ |
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| 240 |
- N_FLAG = (Flags >> 31) & 1; \ |
|
| 241 |
- C_FLAG = (Flags >> 25) & 1; \ |
|
| 242 |
- V_FLAG = (Flags >> 26) & 1; \ |
|
| 243 |
-} |
|
| 244 |
-# else |
|
| 245 |
-# define EMIT1(op, arg) #op " " arg "; " |
|
| 246 |
-# define EMIT2(op, src, dest) #op " " src ", " dest "; " |
|
| 247 |
-# define KONST(val) "$" #val |
|
| 248 |
-# define ASMVAR(cvar) ASMVAR2(__USER_LABEL_PREFIX__, cvar) |
|
| 249 |
-# define ASMVAR2(prefix, cvar) STRING(prefix) cvar |
|
| 250 |
-# define STRING(x) #x |
|
| 251 |
-# define VAR(var) ASMVAR(#var) |
|
| 252 |
-# define REGREF1(index) ASMVAR("reg(" index ")")
|
|
| 253 |
-# define REGREF2(index, scale) ASMVAR("reg(," index "," #scale ")")
|
|
| 254 |
-# define eax "%%eax" |
|
| 255 |
-# define ecx "%%ecx" |
|
| 256 |
-# define edx "%%edx" |
|
| 257 |
-# define ADD_RN_O8(d) \ |
|
| 258 |
- asm("andl $0xFF, %%eax;" \
|
|
| 259 |
- "addl %%eax, %0;" \ |
|
| 260 |
- EMIT1(setsb, VAR(N_FLAG)) \ |
|
| 261 |
- EMIT1(setzb, VAR(Z_FLAG)) \ |
|
| 262 |
- EMIT1(setcb, VAR(C_FLAG)) \ |
|
| 263 |
- EMIT1(setob, VAR(V_FLAG)) \ |
|
| 264 |
- : "=m" (reg[(d)].I)); |
|
| 265 |
-# define CMN_RD_RS \ |
|
| 266 |
- asm("add %0, %1;" \
|
|
| 267 |
- EMIT1(setsb, VAR(N_FLAG)) \ |
|
| 268 |
- EMIT1(setzb, VAR(Z_FLAG)) \ |
|
| 269 |
- EMIT1(setcb, VAR(C_FLAG)) \ |
|
| 270 |
- EMIT1(setob, VAR(V_FLAG)) \ |
|
| 271 |
- : \ |
|
| 272 |
- : "r" (value), "r" (reg[dest].I) : "1"); |
|
| 273 |
-# define ADC_RD_RS \ |
|
| 274 |
- asm(EMIT2(bt, KONST(0), VAR(C_FLAG)) \ |
|
| 275 |
- "adc %1, %%ebx;" \ |
|
| 276 |
- EMIT1(setsb, VAR(N_FLAG)) \ |
|
| 277 |
- EMIT1(setzb, VAR(Z_FLAG)) \ |
|
| 278 |
- EMIT1(setcb, VAR(C_FLAG)) \ |
|
| 279 |
- EMIT1(setob, VAR(V_FLAG)) \ |
|
| 280 |
- : "=b" (reg[dest].I) \ |
|
| 281 |
- : "r" (value), "b" (reg[dest].I)); |
|
| 282 |
-# define SUB_RN_O8(d) \ |
|
| 283 |
- asm("andl $0xFF, %%eax;" \
|
|
| 284 |
- "subl %%eax, %0;" \ |
|
| 285 |
- EMIT1(setsb, VAR(N_FLAG)) \ |
|
| 286 |
- EMIT1(setzb, VAR(Z_FLAG)) \ |
|
| 287 |
- EMIT1(setncb, VAR(C_FLAG)) \ |
|
| 288 |
- EMIT1(setob, VAR(V_FLAG)) \ |
|
| 289 |
- : "=m" (reg[(d)].I)); |
|
| 290 |
-# define MOV_RN_O8(d) \ |
|
| 291 |
- asm("andl $0xFF, %%eax;" \
|
|
| 292 |
- EMIT2(movb, KONST(0), VAR(N_FLAG)) \ |
|
| 293 |
- "movl %%eax, %0;" \ |
|
| 294 |
- EMIT1(setzb, VAR(Z_FLAG)) \ |
|
| 295 |
- : "=m" (reg[(d)].I)); |
|
| 296 |
-# define CMP_RN_O8(d) \ |
|
| 297 |
- asm("andl $0xFF, %%eax;" \
|
|
| 298 |
- "cmpl %%eax, %0;" \ |
|
| 299 |
- EMIT1(setsb, VAR(N_FLAG)) \ |
|
| 300 |
- EMIT1(setzb, VAR(Z_FLAG)) \ |
|
| 301 |
- EMIT1(setncb, VAR(C_FLAG)) \ |
|
| 302 |
- EMIT1(setob, VAR(V_FLAG)) \ |
|
| 303 |
- : \ |
|
| 304 |
- : "m" (reg[(d)].I)); |
|
| 305 |
-# define SBC_RD_RS \ |
|
| 306 |
- asm volatile(EMIT2(bt, KONST(0), VAR(C_FLAG)) \ |
|
| 307 |
- "cmc;" \ |
|
| 308 |
- "sbb %1, %%ebx;" \ |
|
| 309 |
- EMIT1(setsb, VAR(N_FLAG)) \ |
|
| 310 |
- EMIT1(setzb, VAR(Z_FLAG)) \ |
|
| 311 |
- EMIT1(setncb, VAR(C_FLAG)) \ |
|
| 312 |
- EMIT1(setob, VAR(V_FLAG)) \ |
|
| 313 |
- : "=b" (reg[dest].I) \ |
|
| 314 |
- : "r" (value), "b" (reg[dest].I) : "cc", "memory"); |
|
| 315 |
-# define LSL_RD_RS \ |
|
| 316 |
- asm("shl %%cl, %%eax;" \
|
|
| 317 |
- EMIT1(setcb, VAR(C_FLAG)) \ |
|
| 318 |
- : "=a" (value) \ |
|
| 319 |
- : "a" (reg[dest].I), "c" (value)); |
|
| 320 |
-# define LSR_RD_RS \ |
|
| 321 |
- asm("shr %%cl, %%eax;" \
|
|
| 322 |
- EMIT1(setcb, VAR(C_FLAG)) \ |
|
| 323 |
- : "=a" (value) \ |
|
| 324 |
- : "a" (reg[dest].I), "c" (value)); |
|
| 325 |
-# define ASR_RD_RS \ |
|
| 326 |
- asm("sar %%cl, %%eax;" \
|
|
| 327 |
- EMIT1(setcb, VAR(C_FLAG)) \ |
|
| 328 |
- : "=a" (value) \ |
|
| 329 |
- : "a" (reg[dest].I), "c" (value)); |
|
| 330 |
-# define ROR_RD_RS \ |
|
| 331 |
- asm("ror %%cl, %%eax;" \
|
|
| 332 |
- EMIT1(setcb, VAR(C_FLAG)) \ |
|
| 333 |
- : "=a" (value) \ |
|
| 334 |
- : "a" (reg[dest].I), "c" (value)); |
|
| 335 |
-# define NEG_RD_RS \ |
|
| 336 |
- asm("neg %%ebx;" \
|
|
| 337 |
- EMIT1(setsb, VAR(N_FLAG)) \ |
|
| 338 |
- EMIT1(setzb, VAR(Z_FLAG)) \ |
|
| 339 |
- EMIT1(setncb, VAR(C_FLAG)) \ |
|
| 340 |
- EMIT1(setob, VAR(V_FLAG)) \ |
|
| 341 |
- : "=b" (reg[dest].I) \ |
|
| 342 |
- : "b" (reg[source].I)); |
|
| 343 |
-# define CMP_RD_RS \ |
|
| 344 |
- asm("sub %0, %1;" \
|
|
| 345 |
- EMIT1(setsb, VAR(N_FLAG)) \ |
|
| 346 |
- EMIT1(setzb, VAR(Z_FLAG)) \ |
|
| 347 |
- EMIT1(setncb, VAR(C_FLAG)) \ |
|
| 348 |
- EMIT1(setob, VAR(V_FLAG)) \ |
|
| 349 |
- : \ |
|
| 350 |
- : "r" (value), "r" (reg[dest].I) : "1"); |
|
| 351 |
-# define IMM5_INSN(OP, N) \ |
|
| 352 |
- asm("movl %%eax,%%ecx;" \
|
|
| 353 |
- "shrl $1,%%eax;" \ |
|
| 354 |
- "andl $7,%%ecx;" \ |
|
| 355 |
- "andl $0x1C,%%eax;" \ |
|
| 356 |
- EMIT2(movl, REGREF1(eax), edx) \ |
|
| 357 |
- OP \ |
|
| 358 |
- EMIT1(setsb, VAR(N_FLAG)) \ |
|
| 359 |
- EMIT1(setzb, VAR(Z_FLAG)) \ |
|
| 360 |
- EMIT2(movl, edx, REGREF2(ecx, 4)) \ |
|
| 361 |
- : : "i" (N)) |
|
| 362 |
-# define IMM5_INSN_0(OP) \ |
|
| 363 |
- asm("movl %%eax,%%ecx;" \
|
|
| 364 |
- "shrl $1,%%eax;" \ |
|
| 365 |
- "andl $7,%%ecx;" \ |
|
| 366 |
- "andl $0x1C,%%eax;" \ |
|
| 367 |
- EMIT2(movl, REGREF1(eax), edx) \ |
|
| 368 |
- OP \ |
|
| 369 |
- EMIT1(setsb, VAR(N_FLAG)) \ |
|
| 370 |
- EMIT1(setzb, VAR(Z_FLAG)) \ |
|
| 371 |
- EMIT2(movl, edx, REGREF2(ecx, 4)) \ |
|
| 372 |
- : : ) |
|
| 373 |
-# define IMM5_LSL \ |
|
| 374 |
- "shll %0,%%edx;" \ |
|
| 375 |
- EMIT1(setcb, VAR(C_FLAG)) |
|
| 376 |
-# define IMM5_LSL_0 \ |
|
| 377 |
- "testl %%edx,%%edx;" |
|
| 378 |
-# define IMM5_LSR \ |
|
| 379 |
- "shrl %0,%%edx;" \ |
|
| 380 |
- EMIT1(setcb, VAR(C_FLAG)) |
|
| 381 |
-# define IMM5_LSR_0 \ |
|
| 382 |
- "testl %%edx,%%edx;" \ |
|
| 383 |
- EMIT1(setsb, VAR(C_FLAG)) \ |
|
| 384 |
- "xorl %%edx,%%edx;" |
|
| 385 |
-# define IMM5_ASR \ |
|
| 386 |
- "sarl %0,%%edx;" \ |
|
| 387 |
- EMIT1(setcb, VAR(C_FLAG)) |
|
| 388 |
-# define IMM5_ASR_0 \ |
|
| 389 |
- "sarl $31,%%edx;" \ |
|
| 390 |
- EMIT1(setsb, VAR(C_FLAG)) |
|
| 391 |
-# define THREEARG_INSN(OP, N) \ |
|
| 392 |
- asm("movl %%eax,%%edx;" \
|
|
| 393 |
- "shrl $1,%%edx;" \ |
|
| 394 |
- "andl $0x1C,%%edx;" \ |
|
| 395 |
- "andl $7,%%eax;" \ |
|
| 396 |
- EMIT2(movl, REGREF1(edx), ecx) \ |
|
| 397 |
- OP(N) \ |
|
| 398 |
- EMIT1(setsb, VAR(N_FLAG)) \ |
|
| 399 |
- EMIT1(setzb, VAR(Z_FLAG)) \ |
|
| 400 |
- EMIT2(movl, ecx, REGREF2(eax, 4)) \ |
|
| 401 |
- : : ) |
|
| 402 |
-# define ADD_RD_RS_RN(N) \ |
|
| 403 |
- EMIT2(add, VAR(reg) "+" #N "*4", ecx) \ |
|
| 404 |
- EMIT1(setcb, VAR(C_FLAG)) \ |
|
| 405 |
- EMIT1(setob, VAR(V_FLAG)) |
|
| 406 |
-# define ADD_RD_RS_O3(N) \ |
|
| 407 |
- "add $" #N ",%%ecx;" \ |
|
| 408 |
- EMIT1(setcb, VAR(C_FLAG)) \ |
|
| 409 |
- EMIT1(setob, VAR(V_FLAG)) |
|
| 410 |
-# define ADD_RD_RS_O3_0(N) \ |
|
| 411 |
- EMIT2(movb, KONST(0), VAR(C_FLAG)) \ |
|
| 412 |
- "add $0,%%ecx;" \ |
|
| 413 |
- EMIT2(movb, KONST(0), VAR(V_FLAG)) |
|
| 414 |
-# define SUB_RD_RS_RN(N) \ |
|
| 415 |
- EMIT2(sub, VAR(reg) "+" #N "*4", ecx) \ |
|
| 416 |
- EMIT1(setncb, VAR(C_FLAG)) \ |
|
| 417 |
- EMIT1(setob, VAR(V_FLAG)) |
|
| 418 |
-# define SUB_RD_RS_O3(N) \ |
|
| 419 |
- "sub $" #N ",%%ecx;" \ |
|
| 420 |
- EMIT1(setncb, VAR(C_FLAG)) \ |
|
| 421 |
- EMIT1(setob, VAR(V_FLAG)) |
|
| 422 |
-# define SUB_RD_RS_O3_0(N) \ |
|
| 423 |
- EMIT2(movb, KONST(1), VAR(C_FLAG)) \ |
|
| 424 |
- "sub $0,%%ecx;" \ |
|
| 425 |
- EMIT2(movb, KONST(0), VAR(V_FLAG)) |
|
| 426 |
-# endif |
|
| 427 |
-# else // !__GNUC__ |
|
| 428 |
-# define ADD_RD_RS_RN(N) \ |
|
| 429 |
-{ \
|
|
| 430 |
- __asm mov eax, source \ |
|
| 431 |
- __asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \ |
|
| 432 |
- __asm add ebx, dword ptr [OFFSET reg + 4 * N] \ |
|
| 433 |
- __asm mov eax, dest \ |
|
| 434 |
- __asm mov dword ptr [OFFSET reg + 4 * eax], ebx \ |
|
| 435 |
- __asm sets byte ptr N_FLAG \ |
|
| 436 |
- __asm setz byte ptr Z_FLAG \ |
|
| 437 |
- __asm setc byte ptr C_FLAG \ |
|
| 438 |
- __asm seto byte ptr V_FLAG \ |
|
| 439 |
-} |
|
| 440 |
-# define ADD_RD_RS_O3(N) \ |
|
| 441 |
-{ \
|
|
| 442 |
- __asm mov eax, source \ |
|
| 443 |
- __asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \ |
|
| 444 |
- __asm add ebx, N \ |
|
| 445 |
- __asm mov eax, dest \ |
|
| 446 |
- __asm mov dword ptr [OFFSET reg + 4 * eax], ebx \ |
|
| 447 |
- __asm sets byte ptr N_FLAG \ |
|
| 448 |
- __asm setz byte ptr Z_FLAG \ |
|
| 449 |
- __asm setc byte ptr C_FLAG \ |
|
| 450 |
- __asm seto byte ptr V_FLAG \ |
|
| 451 |
-} |
|
| 452 |
-# define ADD_RD_RS_O3_0 \ |
|
| 453 |
-{ \
|
|
| 454 |
- __asm mov eax, source \ |
|
| 455 |
- __asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \ |
|
| 456 |
- __asm add ebx, 0 \ |
|
| 457 |
- __asm mov eax, dest \ |
|
| 458 |
- __asm mov dword ptr [OFFSET reg + 4 * eax], ebx \ |
|
| 459 |
- __asm sets byte ptr N_FLAG \ |
|
| 460 |
- __asm setz byte ptr Z_FLAG \ |
|
| 461 |
- __asm mov byte ptr C_FLAG, 0 \ |
|
| 462 |
- __asm mov byte ptr V_FLAG, 0 \ |
|
| 463 |
-} |
|
| 464 |
-# define ADD_RN_O8(d) \ |
|
| 465 |
-{ \
|
|
| 466 |
- __asm mov ebx, opcode \ |
|
| 467 |
- __asm and ebx, 255 \ |
|
| 468 |
- __asm add dword ptr [OFFSET reg + 4 * (d)], ebx \ |
|
| 469 |
- __asm sets byte ptr N_FLAG \ |
|
| 470 |
- __asm setz byte ptr Z_FLAG \ |
|
| 471 |
- __asm setc byte ptr C_FLAG \ |
|
| 472 |
- __asm seto byte ptr V_FLAG \ |
|
| 473 |
-} |
|
| 474 |
-# define CMN_RD_RS \ |
|
| 475 |
-{ \
|
|
| 476 |
- __asm mov eax, dest \ |
|
| 477 |
- __asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \ |
|
| 478 |
- __asm add ebx, value \ |
|
| 479 |
- __asm sets byte ptr N_FLAG \ |
|
| 480 |
- __asm setz byte ptr Z_FLAG \ |
|
| 481 |
- __asm setc byte ptr C_FLAG \ |
|
| 482 |
- __asm seto byte ptr V_FLAG \ |
|
| 483 |
-} |
|
| 484 |
-# define ADC_RD_RS \ |
|
| 485 |
-{ \
|
|
| 486 |
- __asm mov ebx, dest \ |
|
| 487 |
- __asm mov ebx, dword ptr [OFFSET reg + 4 * ebx] \ |
|
| 488 |
- __asm bt word ptr C_FLAG, 0 \ |
|
| 489 |
- __asm adc ebx, value \ |
|
| 490 |
- __asm mov eax, dest \ |
|
| 491 |
- __asm mov dword ptr [OFFSET reg + 4 * eax], ebx \ |
|
| 492 |
- __asm sets byte ptr N_FLAG \ |
|
| 493 |
- __asm setz byte ptr Z_FLAG \ |
|
| 494 |
- __asm setc byte ptr C_FLAG \ |
|
| 495 |
- __asm seto byte ptr V_FLAG \ |
|
| 496 |
-} |
|
| 497 |
-# define SUB_RD_RS_RN(N) \ |
|
| 498 |
-{ \
|
|
| 499 |
- __asm mov eax, source \ |
|
| 500 |
- __asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \ |
|
| 501 |
- __asm sub ebx, dword ptr [OFFSET reg + 4 * N] \ |
|
| 502 |
- __asm mov eax, dest \ |
|
| 503 |
- __asm mov dword ptr [OFFSET reg + 4 * eax], ebx \ |
|
| 504 |
- __asm sets byte ptr N_FLAG \ |
|
| 505 |
- __asm setz byte ptr Z_FLAG \ |
|
| 506 |
- __asm setnc byte ptr C_FLAG \ |
|
| 507 |
- __asm seto byte ptr V_FLAG \ |
|
| 508 |
-} |
|
| 509 |
-# define SUB_RD_RS_O3(N) \ |
|
| 510 |
-{ \
|
|
| 511 |
- __asm mov eax, source \ |
|
| 512 |
- __asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \ |
|
| 513 |
- __asm sub ebx, N \ |
|
| 514 |
- __asm mov eax, dest \ |
|
| 515 |
- __asm mov dword ptr [OFFSET reg + 4 * eax], ebx \ |
|
| 516 |
- __asm sets byte ptr N_FLAG \ |
|
| 517 |
- __asm setz byte ptr Z_FLAG \ |
|
| 518 |
- __asm setnc byte ptr C_FLAG \ |
|
| 519 |
- __asm seto byte ptr V_FLAG \ |
|
| 520 |
-} |
|
| 521 |
-# define SUB_RD_RS_O3_0 \ |
|
| 522 |
-{ \
|
|
| 523 |
- __asm mov eax, source \ |
|
| 524 |
- __asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \ |
|
| 525 |
- __asm sub ebx, 0 \ |
|
| 526 |
- __asm mov eax, dest \ |
|
| 527 |
- __asm mov dword ptr [OFFSET reg + 4 * eax], ebx \ |
|
| 528 |
- __asm sets byte ptr N_FLAG \ |
|
| 529 |
- __asm setz byte ptr Z_FLAG \ |
|
| 530 |
- __asm mov byte ptr C_FLAG, 1 \ |
|
| 531 |
- __asm mov byte ptr V_FLAG, 0 \ |
|
| 532 |
-} |
|
| 533 |
-# define SUB_RN_O8(d) \ |
|
| 534 |
-{ \
|
|
| 535 |
- __asm mov ebx, opcode \ |
|
| 536 |
- __asm and ebx, 255 \ |
|
| 537 |
- __asm sub dword ptr [OFFSET reg + 4 * (d)], ebx \ |
|
| 538 |
- __asm sets byte ptr N_FLAG \ |
|
| 539 |
- __asm setz byte ptr Z_FLAG \ |
|
| 540 |
- __asm setnc byte ptr C_FLAG \ |
|
| 541 |
- __asm seto byte ptr V_FLAG \ |
|
| 542 |
-} |
|
| 543 |
-# define MOV_RN_O8(d) \ |
|
| 544 |
-{ \
|
|
| 545 |
- __asm mov eax, opcode \ |
|
| 546 |
- __asm and eax, 255 \ |
|
| 547 |
- __asm mov dword ptr [OFFSET reg + 4 * (d)], eax \ |
|
| 548 |
- __asm sets byte ptr N_FLAG \ |
|
| 549 |
- __asm setz byte ptr Z_FLAG \ |
|
| 550 |
-} |
|
| 551 |
-# define CMP_RN_O8(d) \ |
|
| 552 |
-{ \
|
|
| 553 |
- __asm mov eax, dword ptr [OFFSET reg + 4 * (d)] \ |
|
| 554 |
- __asm mov ebx, opcode \ |
|
| 555 |
- __asm and ebx, 255 \ |
|
| 556 |
- __asm sub eax, ebx \ |
|
| 557 |
- __asm sets byte ptr N_FLAG \ |
|
| 558 |
- __asm setz byte ptr Z_FLAG \ |
|
| 559 |
- __asm setnc byte ptr C_FLAG \ |
|
| 560 |
- __asm seto byte ptr V_FLAG \ |
|
| 561 |
-} |
|
| 562 |
-# define SBC_RD_RS \ |
|
| 563 |
-{ \
|
|
| 564 |
- __asm mov ebx, dest \ |
|
| 565 |
- __asm mov ebx, dword ptr [OFFSET reg + 4 * ebx] \ |
|
| 566 |
- __asm mov eax, value \ |
|
| 567 |
- __asm bt word ptr C_FLAG, 0 \ |
|
| 568 |
- __asm cmc \ |
|
| 569 |
- __asm sbb ebx, eax \ |
|
| 570 |
- __asm mov eax, dest \ |
|
| 571 |
- __asm mov dword ptr [OFFSET reg + 4 * eax], ebx \ |
|
| 572 |
- __asm sets byte ptr N_FLAG \ |
|
| 573 |
- __asm setz byte ptr Z_FLAG \ |
|
| 574 |
- __asm setnc byte ptr C_FLAG \ |
|
| 575 |
- __asm seto byte ptr V_FLAG \ |
|
| 576 |
-} |
|
| 577 |
-# define LSL_RD_RM_I5 \ |
|
| 578 |
-{ \
|
|
| 579 |
- __asm mov eax, source \ |
|
| 580 |
- __asm mov eax, dword ptr [OFFSET reg + 4 * eax] \ |
|
| 581 |
- __asm mov cl, byte ptr shift \ |
|
| 582 |
- __asm shl eax, cl \ |
|
| 583 |
- __asm mov value, eax \ |
|
| 584 |
- __asm setc byte ptr C_FLAG \ |
|
| 585 |
-} |
|
| 586 |
-# define LSL_RD_RS \ |
|
| 587 |
-{ \
|
|
| 588 |
- __asm mov eax, dest \ |
|
| 589 |
- __asm mov eax, dword ptr [OFFSET reg + 4 * eax] \ |
|
| 590 |
- __asm mov cl, byte ptr value \ |
|
| 591 |
- __asm shl eax, cl \ |
|
| 592 |
- __asm mov value, eax \ |
|
| 593 |
- __asm setc byte ptr C_FLAG \ |
|
| 594 |
-} |
|
| 595 |
-# define LSR_RD_RM_I5 \ |
|
| 596 |
-{ \
|
|
| 597 |
- __asm mov eax, source \ |
|
| 598 |
- __asm mov eax, dword ptr [OFFSET reg + 4 * eax] \ |
|
| 599 |
- __asm mov cl, byte ptr shift \ |
|
| 600 |
- __asm shr eax, cl \ |
|
| 601 |
- __asm mov value, eax \ |
|
| 602 |
- __asm setc byte ptr C_FLAG \ |
|
| 603 |
-} |
|
| 604 |
-# define LSR_RD_RS \ |
|
| 605 |
-{ \
|
|
| 606 |
- __asm mov eax, dest \ |
|
| 607 |
- __asm mov eax, dword ptr [OFFSET reg + 4 * eax] \ |
|
| 608 |
- __asm mov cl, byte ptr value \ |
|
| 609 |
- __asm shr eax, cl \ |
|
| 610 |
- __asm mov value, eax \ |
|
| 611 |
- __asm setc byte ptr C_FLAG \ |
|
| 612 |
-} |
|
| 613 |
-# define ASR_RD_RM_I5 \ |
|
| 614 |
-{ \
|
|
| 615 |
- __asm mov eax, source \ |
|
| 616 |
- __asm mov eax, dword ptr [OFFSET reg + 4 * eax] \ |
|
| 617 |
- __asm mov cl, byte ptr shift \ |
|
| 618 |
- __asm sar eax, cl \ |
|
| 619 |
- __asm mov value, eax \ |
|
| 620 |
- __asm setc byte ptr C_FLAG \ |
|
| 621 |
-} |
|
| 622 |
-# define ASR_RD_RS \ |
|
| 623 |
-{ \
|
|
| 624 |
- __asm mov eax, dest \ |
|
| 625 |
- __asm mov eax, dword ptr [OFFSET reg + 4 * eax] \ |
|
| 626 |
- __asm mov cl, byte ptr value \ |
|
| 627 |
- __asm sar eax, cl \ |
|
| 628 |
- __asm mov value, eax \ |
|
| 629 |
- __asm setc byte ptr C_FLAG \ |
|
| 630 |
-} |
|
| 631 |
-# define ROR_RD_RS \ |
|
| 632 |
-{ \
|
|
| 633 |
- __asm mov eax, dest \ |
|
| 634 |
- __asm mov eax, dword ptr [OFFSET reg + 4 * eax] \ |
|
| 635 |
- __asm mov cl, byte ptr value \ |
|
| 636 |
- __asm ror eax, cl \ |
|
| 637 |
- __asm mov value, eax \ |
|
| 638 |
- __asm setc byte ptr C_FLAG \ |
|
| 639 |
-} |
|
| 640 |
-# define NEG_RD_RS \ |
|
| 641 |
-{ \
|
|
| 642 |
- __asm mov ebx, source \ |
|
| 643 |
- __asm mov ebx, dword ptr [OFFSET reg + 4 * ebx] \ |
|
| 644 |
- __asm neg ebx \ |
|
| 645 |
- __asm mov eax, dest \ |
|
| 646 |
- __asm mov dword ptr [OFFSET reg + 4 * eax], ebx \ |
|
| 647 |
- __asm sets byte ptr N_FLAG \ |
|
| 648 |
- __asm setz byte ptr Z_FLAG \ |
|
| 649 |
- __asm setnc byte ptr C_FLAG \ |
|
| 650 |
- __asm seto byte ptr V_FLAG \ |
|
| 651 |
-} |
|
| 652 |
-# define CMP_RD_RS \ |
|
| 653 |
-{ \
|
|
| 654 |
- __asm mov eax, dest \ |
|
| 655 |
- __asm mov ebx, dword ptr [OFFSET reg + 4 * eax] \ |
|
| 656 |
- __asm sub ebx, value \ |
|
| 657 |
- __asm sets byte ptr N_FLAG \ |
|
| 658 |
- __asm setz byte ptr Z_FLAG \ |
|
| 659 |
- __asm setnc byte ptr C_FLAG \ |
|
| 660 |
- __asm seto byte ptr V_FLAG \ |
|
| 661 |
-} |
|
| 662 |
-# endif |
|
| 663 |
-#endif |
|
| 664 |
- |
|
| 665 | 22 |
// C core |
| 666 |
-static inline void ADDCARRY(uint32_t a, uint32_t b, uint32_t c) |
|
| 23 |
+auto ADDCARRY = [](uint32_t a, uint32_t b, uint32_t c) |
|
| 667 | 24 |
{
|
| 668 | 25 |
C_FLAG = !!((NEG(a) & NEG(b)) | (NEG(a) & POS(c)) | (NEG(b) & POS(c))); |
| 669 |
-} |
|
| 670 |
-static inline void ADDOVERFLOW(uint32_t a, uint32_t b, uint32_t c) |
|
| 26 |
+}; |
|
| 27 |
+auto ADDOVERFLOW = [](uint32_t a, uint32_t b, uint32_t c) |
|
| 671 | 28 |
{
|
| 672 | 29 |
V_FLAG = !!((NEG(a) & NEG(b) & POS(c)) | (POS(a) & POS(b) & NEG(c))); |
| 673 |
-} |
|
| 674 |
-static inline void SUBCARRY(uint32_t a, uint32_t b, uint32_t c) |
|
| 30 |
+}; |
|
| 31 |
+auto SUBCARRY = [](uint32_t a, uint32_t b, uint32_t c) |
|
| 675 | 32 |
{
|
| 676 | 33 |
C_FLAG = !!((NEG(a) & POS(b)) | (NEG(a) & POS(c)) | (POS(b) & POS(c))); |
| 677 |
-} |
|
| 678 |
-static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c) |
|
| 34 |
+}; |
|
| 35 |
+auto SUBOVERFLOW = [](uint32_t a, uint32_t b, uint32_t c) |
|
| 679 | 36 |
{
|
| 680 | 37 |
V_FLAG = !!((NEG(a) & POS(b) & POS(c)) | (POS(a) & NEG(b) & NEG(c))); |
| 681 |
-} |
|
| 682 |
-#ifndef ADD_RD_RS_RN |
|
| 683 |
-# define ADD_RD_RS_RN(N) \ |
|
| 38 |
+}; |
|
| 39 |
+#define ADD_RD_RS_RN(N) \ |
|
| 684 | 40 |
{ \
|
| 685 | 41 |
uint32_t lhs = reg[source].I; \ |
| 686 |
- uint32_t rhs = reg[N].I; \ |
|
| 42 |
+ uint32_t rhs = reg[(N)].I; \ |
|
| 687 | 43 |
uint32_t res = lhs + rhs; \ |
| 688 | 44 |
reg[dest].I = res; \ |
| 689 | 45 |
Z_FLAG = !res; \ |
| ... | ... |
@@ -691,12 +47,10 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c) |
| 691 | 47 |
ADDCARRY(lhs, rhs, res); \ |
| 692 | 48 |
ADDOVERFLOW(lhs, rhs, res); \ |
| 693 | 49 |
} |
| 694 |
-#endif |
|
| 695 |
-#ifndef ADD_RD_RS_O3 |
|
| 696 |
-# define ADD_RD_RS_O3(N) \ |
|
| 50 |
+#define ADD_RD_RS_O3(N) \ |
|
| 697 | 51 |
{ \
|
| 698 | 52 |
uint32_t lhs = reg[source].I; \ |
| 699 |
- uint32_t rhs = N; \ |
|
| 53 |
+ uint32_t rhs = (N); \ |
|
| 700 | 54 |
uint32_t res = lhs + rhs; \ |
| 701 | 55 |
reg[dest].I = res; \ |
| 702 | 56 |
Z_FLAG = !res; \ |
| ... | ... |
@@ -704,12 +58,8 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c) |
| 704 | 58 |
ADDCARRY(lhs, rhs, res); \ |
| 705 | 59 |
ADDOVERFLOW(lhs, rhs, res); \ |
| 706 | 60 |
} |
| 707 |
-#endif |
|
| 708 |
-#ifndef ADD_RD_RS_O3_0 |
|
| 709 |
-# define ADD_RD_RS_O3_0 ADD_RD_RS_O3 |
|
| 710 |
-#endif |
|
| 711 |
-#ifndef ADD_RN_O8 |
|
| 712 |
-# define ADD_RN_O8(d) \ |
|
| 61 |
+#define ADD_RD_RS_O3_0 ADD_RD_RS_O3 |
|
| 62 |
+#define ADD_RN_O8(d) \ |
|
| 713 | 63 |
{ \
|
| 714 | 64 |
uint32_t lhs = reg[(d)].I; \ |
| 715 | 65 |
uint32_t rhs = opcode & 255; \ |
| ... | ... |
@@ -720,9 +70,7 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c) |
| 720 | 70 |
ADDCARRY(lhs, rhs, res); \ |
| 721 | 71 |
ADDOVERFLOW(lhs, rhs, res); \ |
| 722 | 72 |
} |
| 723 |
-#endif |
|
| 724 |
-#ifndef CMN_RD_RS |
|
| 725 |
-# define CMN_RD_RS \ |
|
| 73 |
+#define CMN_RD_RS \ |
|
| 726 | 74 |
{ \
|
| 727 | 75 |
uint32_t lhs = reg[dest].I; \ |
| 728 | 76 |
uint32_t rhs = value; \ |
| ... | ... |
@@ -732,9 +80,7 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c) |
| 732 | 80 |
ADDCARRY(lhs, rhs, res); \ |
| 733 | 81 |
ADDOVERFLOW(lhs, rhs, res); \ |
| 734 | 82 |
} |
| 735 |
-#endif |
|
| 736 |
-#ifndef ADC_RD_RS |
|
| 737 |
-# define ADC_RD_RS \ |
|
| 83 |
+#define ADC_RD_RS \ |
|
| 738 | 84 |
{ \
|
| 739 | 85 |
uint32_t lhs = reg[dest].I; \ |
| 740 | 86 |
uint32_t rhs = value; \ |
| ... | ... |
@@ -745,12 +91,10 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c) |
| 745 | 91 |
ADDCARRY(lhs, rhs, res); \ |
| 746 | 92 |
ADDOVERFLOW(lhs, rhs, res); \ |
| 747 | 93 |
} |
| 748 |
-#endif |
|
| 749 |
-#ifndef SUB_RD_RS_RN |
|
| 750 |
-# define SUB_RD_RS_RN(N) \ |
|
| 94 |
+#define SUB_RD_RS_RN(N) \ |
|
| 751 | 95 |
{ \
|
| 752 | 96 |
uint32_t lhs = reg[source].I; \ |
| 753 |
- uint32_t rhs = reg[N].I; \ |
|
| 97 |
+ uint32_t rhs = reg[(N)].I; \ |
|
| 754 | 98 |
uint32_t res = lhs - rhs; \ |
| 755 | 99 |
reg[dest].I = res; \ |
| 756 | 100 |
Z_FLAG = !res; \ |
| ... | ... |
@@ -758,25 +102,19 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c) |
| 758 | 102 |
SUBCARRY(lhs, rhs, res); \ |
| 759 | 103 |
SUBOVERFLOW(lhs, rhs, res); \ |
| 760 | 104 |
} |
| 761 |
-#endif |
|
| 762 |
-#ifndef SUB_RD_RS_O3 |
|
| 763 |
-# define SUB_RD_RS_O3(N) \ |
|
| 105 |
+#define SUB_RD_RS_O3(N) \ |
|
| 764 | 106 |
{ \
|
| 765 | 107 |
uint32_t lhs = reg[source].I; \ |
| 766 |
- uint32_t rhs = N; \ |
|
| 108 |
+ uint32_t rhs = (N); \ |
|
| 767 | 109 |
uint32_t res = lhs - rhs; \ |
| 768 |
- reg[dest].I = res; \ |
|
| 110 |
+ reg[dest].I = res;\ |
|
| 769 | 111 |
Z_FLAG = !res; \ |
| 770 | 112 |
N_FLAG = !!NEG(res); \ |
| 771 | 113 |
SUBCARRY(lhs, rhs, res); \ |
| 772 | 114 |
SUBOVERFLOW(lhs, rhs, res); \ |
| 773 | 115 |
} |
| 774 |
-#endif |
|
| 775 |
-#ifndef SUB_RD_RS_O3_0 |
|
| 776 |
-# define SUB_RD_RS_O3_0 SUB_RD_RS_O3 |
|
| 777 |
-#endif |
|
| 778 |
-#ifndef SUB_RN_O8 |
|
| 779 |
-# define SUB_RN_O8(d) \ |
|
| 116 |
+#define SUB_RD_RS_O3_0 SUB_RD_RS_O3 |
|
| 117 |
+#define SUB_RN_O8(d) \ |
|
| 780 | 118 |
{ \
|
| 781 | 119 |
uint32_t lhs = reg[(d)].I; \ |
| 782 | 120 |
uint32_t rhs = opcode & 255; \ |
| ... | ... |
@@ -787,17 +125,13 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c) |
| 787 | 125 |
SUBCARRY(lhs, rhs, res); \ |
| 788 | 126 |
SUBOVERFLOW(lhs, rhs, res); \ |
| 789 | 127 |
} |
| 790 |
-#endif |
|
| 791 |
-#ifndef MOV_RN_O8 |
|
| 792 |
-# define MOV_RN_O8(d) \ |
|
| 128 |
+#define MOV_RN_O8(d) \ |
|
| 793 | 129 |
{ \
|
| 794 |
- reg[d].I = opcode & 255; \ |
|
| 130 |
+ reg[(d)].I = opcode & 255; \ |
|
| 795 | 131 |
N_FLAG = false; \ |
| 796 | 132 |
Z_FLAG = !reg[d].I; \ |
| 797 | 133 |
} |
| 798 |
-#endif |
|
| 799 |
-#ifndef CMP_RN_O8 |
|
| 800 |
-# define CMP_RN_O8(d) \ |
|
| 134 |
+#define CMP_RN_O8(d) \ |
|
| 801 | 135 |
{ \
|
| 802 | 136 |
uint32_t lhs = reg[(d)].I; \ |
| 803 | 137 |
uint32_t rhs = opcode & 255; \ |
| ... | ... |
@@ -807,9 +141,7 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c) |
| 807 | 141 |
SUBCARRY(lhs, rhs, res); \ |
| 808 | 142 |
SUBOVERFLOW(lhs, rhs, res); \ |
| 809 | 143 |
} |
| 810 |
-#endif |
|
| 811 |
-#ifndef SBC_RD_RS |
|
| 812 |
-# define SBC_RD_RS \ |
|
| 144 |
+#define SBC_RD_RS \ |
|
| 813 | 145 |
{ \
|
| 814 | 146 |
uint32_t lhs = reg[dest].I; \ |
| 815 | 147 |
uint32_t rhs = value; \ |
| ... | ... |
@@ -820,58 +152,42 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c) |
| 820 | 152 |
SUBCARRY(lhs, rhs, res); \ |
| 821 | 153 |
SUBOVERFLOW(lhs, rhs, res); \ |
| 822 | 154 |
} |
| 823 |
-#endif |
|
| 824 |
-#ifndef LSL_RD_RM_I5 |
|
| 825 |
-# define LSL_RD_RM_I5 \ |
|
| 155 |
+#define LSL_RD_RM_I5 \ |
|
| 826 | 156 |
{ \
|
| 827 | 157 |
C_FLAG = !!((reg[source].I >> (32 - shift)) & 1); \ |
| 828 | 158 |
value = reg[source].I << shift; \ |
| 829 | 159 |
} |
| 830 |
-#endif |
|
| 831 |
-#ifndef LSL_RD_RS |
|
| 832 |
-# define LSL_RD_RS \ |
|
| 160 |
+#define LSL_RD_RS \ |
|
| 833 | 161 |
{ \
|
| 834 | 162 |
C_FLAG = !!((reg[dest].I >> (32 - value)) & 1); \ |
| 835 | 163 |
value = reg[dest].I << value; \ |
| 836 | 164 |
} |
| 837 |
-#endif |
|
| 838 |
-#ifndef LSR_RD_RM_I5 |
|
| 839 |
-# define LSR_RD_RM_I5 \ |
|
| 165 |
+#define LSR_RD_RM_I5 \ |
|
| 840 | 166 |
{ \
|
| 841 | 167 |
C_FLAG = !!((reg[source].I >> (shift - 1)) & 1); \ |
| 842 | 168 |
value = reg[source].I >> shift; \ |
| 843 | 169 |
} |
| 844 |
-#endif |
|
| 845 |
-#ifndef LSR_RD_RS |
|
| 846 |
-# define LSR_RD_RS \ |
|
| 170 |
+#define LSR_RD_RS \ |
|
| 847 | 171 |
{ \
|
| 848 | 172 |
C_FLAG = !!((reg[dest].I >> (value - 1)) & 1); \ |
| 849 | 173 |
value = reg[dest].I >> value; \ |
| 850 | 174 |
} |
| 851 |
-#endif |
|
| 852 |
-#ifndef ASR_RD_RM_I5 |
|
| 853 |
-# define ASR_RD_RM_I5 \ |
|
| 175 |
+#define ASR_RD_RM_I5 \ |
|
| 854 | 176 |
{ \
|
| 855 | 177 |
C_FLAG = !!((static_cast<int32_t>(reg[source].I) >> static_cast<int>(shift - 1)) & 1); \ |
| 856 | 178 |
value = static_cast<int32_t>(reg[source].I) >> static_cast<int>(shift); \ |
| 857 | 179 |
} |
| 858 |
-#endif |
|
| 859 |
-#ifndef ASR_RD_RS |
|
| 860 |
-# define ASR_RD_RS \ |
|
| 180 |
+#define ASR_RD_RS \ |
|
| 861 | 181 |
{ \
|
| 862 | 182 |
C_FLAG = !!((static_cast<int32_t>(reg[dest].I) >> static_cast<int>(value - 1)) & 1); \ |
| 863 | 183 |
value = static_cast<int32_t>(reg[dest].I) >> static_cast<int>(value); \ |
| 864 | 184 |
} |
| 865 |
-#endif |
|
| 866 |
-#ifndef ROR_RD_RS |
|
| 867 |
-# define ROR_RD_RS \ |
|
| 185 |
+#define ROR_RD_RS \ |
|
| 868 | 186 |
{ \
|
| 869 | 187 |
C_FLAG = !!((reg[dest].I >> (value - 1)) & 1); \ |
| 870 | 188 |
value = (reg[dest].I << (32 - value)) | (reg[dest].I >> value); \ |
| 871 |
-} |
|
| 872 |
-#endif |
|
| 873 |
-#ifndef NEG_RD_RS |
|
| 874 |
-# define NEG_RD_RS \ |
|
| 189 |
+ } |
|
| 190 |
+#define NEG_RD_RS \ |
|
| 875 | 191 |
{ \
|
| 876 | 192 |
uint32_t lhs = reg[source].I; \ |
| 877 | 193 |
uint32_t rhs = 0; \ |
| ... | ... |
@@ -882,9 +198,7 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c) |
| 882 | 198 |
SUBCARRY(rhs, lhs, res); \ |
| 883 | 199 |
SUBOVERFLOW(rhs, lhs, res); \ |
| 884 | 200 |
} |
| 885 |
-#endif |
|
| 886 |
-#ifndef CMP_RD_RS |
|
| 887 |
-# define CMP_RD_RS \ |
|
| 201 |
+#define CMP_RD_RS \ |
|
| 888 | 202 |
{ \
|
| 889 | 203 |
uint32_t lhs = reg[dest].I; \ |
| 890 | 204 |
uint32_t rhs = value; \ |
| ... | ... |
@@ -894,17 +208,15 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c) |
| 894 | 208 |
SUBCARRY(lhs, rhs, res); \ |
| 895 | 209 |
SUBOVERFLOW(lhs, rhs, res); \ |
| 896 | 210 |
} |
| 897 |
-#endif |
|
| 898 |
-#ifndef IMM5_INSN |
|
| 899 |
-# define IMM5_INSN(OP, N) \ |
|
| 211 |
+#define IMM5_INSN(OP, N) \ |
|
| 900 | 212 |
int dest = opcode & 0x07; \ |
| 901 | 213 |
int source = (opcode >> 3) & 0x07; \ |
| 902 | 214 |
uint32_t value; \ |
| 903 |
- OP(N); \ |
|
| 215 |
+ OP((N)); \ |
|
| 904 | 216 |
reg[dest].I = value; \ |
| 905 | 217 |
N_FLAG = !!(value & 0x80000000); \ |
| 906 | 218 |
Z_FLAG = !value; |
| 907 |
-# define IMM5_INSN_0(OP) \ |
|
| 219 |
+#define IMM5_INSN_0(OP) \ |
|
| 908 | 220 |
int dest = opcode & 0x07; \ |
| 909 | 221 |
int source = (opcode >> 3) & 0x07; \ |
| 910 | 222 |
uint32_t value; \ |
| ... | ... |
@@ -912,21 +224,21 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c) |
| 912 | 224 |
reg[dest].I = value; \ |
| 913 | 225 |
N_FLAG = !!(value & 0x80000000); \ |
| 914 | 226 |
Z_FLAG = !value; |
| 915 |
-# define IMM5_LSL(N) \ |
|
| 916 |
- int shift = N; \ |
|
| 227 |
+#define IMM5_LSL(N) \ |
|
| 228 |
+ int shift = (N); \ |
|
| 917 | 229 |
LSL_RD_RM_I5; |
| 918 |
-# define IMM5_LSL_0 \ |
|
| 230 |
+#define IMM5_LSL_0 \ |
|
| 919 | 231 |
value = reg[source].I; |
| 920 |
-# define IMM5_LSR(N) \ |
|
| 921 |
- int shift = N; \ |
|
| 232 |
+#define IMM5_LSR(N) \ |
|
| 233 |
+ int shift = (N); \ |
|
| 922 | 234 |
LSR_RD_RM_I5; |
| 923 |
-# define IMM5_LSR_0 \ |
|
| 235 |
+#define IMM5_LSR_0 \ |
|
| 924 | 236 |
C_FLAG = !!(reg[source].I & 0x80000000); \ |
| 925 | 237 |
value = 0; |
| 926 |
-# define IMM5_ASR(N) \ |
|
| 927 |
- int shift = N; \ |
|
| 238 |
+#define IMM5_ASR(N) \ |
|
| 239 |
+ int shift = (N); \ |
|
| 928 | 240 |
ASR_RD_RM_I5; |
| 929 |
-# define IMM5_ASR_0 \ |
|
| 241 |
+#define IMM5_ASR_0 \ |
|
| 930 | 242 |
if (reg[source].I & 0x80000000) \ |
| 931 | 243 |
{ \
|
| 932 | 244 |
value = 0xFFFFFFFF; \ |
| ... | ... |
@@ -937,13 +249,10 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c) |
| 937 | 249 |
value = 0; \ |
| 938 | 250 |
C_FLAG = false; \ |
| 939 | 251 |
} |
| 940 |
-#endif |
|
| 941 |
-#ifndef THREEARG_INSN |
|
| 942 |
-# define THREEARG_INSN(OP, N) \ |
|
| 252 |
+#define THREEARG_INSN(OP, N) \ |
|
| 943 | 253 |
int dest = opcode & 0x07; \ |
| 944 | 254 |
int source = (opcode >> 3) & 0x07; \ |
| 945 |
- OP(N); |
|
| 946 |
-#endif |
|
| 255 |
+ OP((N)); |
|
| 947 | 256 |
|
| 948 | 257 |
// Shift instructions ///////////////////////////////////////////////////// |
| 949 | 258 |
|
| ... | ... |
@@ -958,28 +267,28 @@ static inline void SUBOVERFLOW(uint32_t a, uint32_t b, uint32_t c) |
| 958 | 267 |
static INSN_REGPARM void thumb##BASE##_07(uint32_t opcode) { IMM5_INSN(OP, 7); } \
|
| 959 | 268 |
static INSN_REGPARM void thumb##BASE##_08(uint32_t opcode) { IMM5_INSN(OP, 8); } \
|
| 960 | 269 |
static INSN_REGPARM void thumb##BASE##_09(uint32_t opcode) { IMM5_INSN(OP, 9); } \
|
| 961 |
- static INSN_REGPARM void thumb##BASE##_0A(uint32_t opcode) { IMM5_INSN(OP, 10); } \
|
|
| 962 |
- static INSN_REGPARM void thumb##BASE##_0B(uint32_t opcode) { IMM5_INSN(OP, 11); } \
|
|
| 963 |
- static INSN_REGPARM void thumb##BASE##_0C(uint32_t opcode) { IMM5_INSN(OP, 12); } \
|
|
| 964 |
- static INSN_REGPARM void thumb##BASE##_0D(uint32_t opcode) { IMM5_INSN(OP, 13); } \
|
|
| 965 |
- static INSN_REGPARM void thumb##BASE##_0E(uint32_t opcode) { IMM5_INSN(OP, 14); } \
|
|
| 966 |
- static INSN_REGPARM void thumb##BASE##_0F(uint32_t opcode) { IMM5_INSN(OP, 15); } \
|
|
| 967 |
- static INSN_REGPARM void thumb##BASE##_10(uint32_t opcode) { IMM5_INSN(OP, 16); } \
|
|
| 968 |
- static INSN_REGPARM void thumb##BASE##_11(uint32_t opcode) { IMM5_INSN(OP, 17); } \
|
|
| 969 |
- static INSN_REGPARM void thumb##BASE##_12(uint32_t opcode) { IMM5_INSN(OP, 18); } \
|
|
| 970 |
- static INSN_REGPARM void thumb##BASE##_13(uint32_t opcode) { IMM5_INSN(OP, 19); } \
|
|
| 971 |
- static INSN_REGPARM void thumb##BASE##_14(uint32_t opcode) { IMM5_INSN(OP, 20); } \
|
|
| 972 |
- static INSN_REGPARM void thumb##BASE##_15(uint32_t opcode) { IMM5_INSN(OP, 21); } \
|
|
| 973 |
- static INSN_REGPARM void thumb##BASE##_16(uint32_t opcode) { IMM5_INSN(OP, 22); } \
|
|
| 974 |
- static INSN_REGPARM void thumb##BASE##_17(uint32_t opcode) { IMM5_INSN(OP, 23); } \
|
|
| 975 |
- static INSN_REGPARM void thumb##BASE##_18(uint32_t opcode) { IMM5_INSN(OP, 24); } \
|
|
| 976 |
- static INSN_REGPARM void thumb##BASE##_19(uint32_t opcode) { IMM5_INSN(OP, 25); } \
|
|
| 977 |
- static INSN_REGPARM void thumb##BASE##_1A(uint32_t opcode) { IMM5_INSN(OP, 26); } \
|
|
| 978 |
- static INSN_REGPARM void thumb##BASE##_1B(uint32_t opcode) { IMM5_INSN(OP, 27); } \
|
|
| 979 |
- static INSN_REGPARM void thumb##BASE##_1C(uint32_t opcode) { IMM5_INSN(OP, 28); } \
|
|
| 980 |
- static INSN_REGPARM void thumb##BASE##_1D(uint32_t opcode) { IMM5_INSN(OP, 29); } \
|
|
| 981 |
- static INSN_REGPARM void thumb##BASE##_1E(uint32_t opcode) { IMM5_INSN(OP, 30); } \
|
|
| 982 |
- static INSN_REGPARM void thumb##BASE##_1F(uint32_t opcode) { IMM5_INSN(OP, 31); }
|
|
| 270 |
+ static INSN_REGPARM void thumb##BASE##_0A(uint32_t opcode) { IMM5_INSN(OP,10); } \
|
|
| 271 |
+ static INSN_REGPARM void thumb##BASE##_0B(uint32_t opcode) { IMM5_INSN(OP,11); } \
|
|
| 272 |
+ static INSN_REGPARM void thumb##BASE##_0C(uint32_t opcode) { IMM5_INSN(OP,12); } \
|
|
| 273 |
+ static INSN_REGPARM void thumb##BASE##_0D(uint32_t opcode) { IMM5_INSN(OP,13); } \
|
|
| 274 |
+ static INSN_REGPARM void thumb##BASE##_0E(uint32_t opcode) { IMM5_INSN(OP,14); } \
|
|
| 275 |
+ static INSN_REGPARM void thumb##BASE##_0F(uint32_t opcode) { IMM5_INSN(OP,15); } \
|
|
| 276 |
+ static INSN_REGPARM void thumb##BASE##_10(uint32_t opcode) { IMM5_INSN(OP,16); } \
|
|
| 277 |
+ static INSN_REGPARM void thumb##BASE##_11(uint32_t opcode) { IMM5_INSN(OP,17); } \
|
|
| 278 |
+ static INSN_REGPARM void thumb##BASE##_12(uint32_t opcode) { IMM5_INSN(OP,18); } \
|
|
| 279 |
+ static INSN_REGPARM void thumb##BASE##_13(uint32_t opcode) { IMM5_INSN(OP,19); } \
|
|
| 280 |
+ static INSN_REGPARM void thumb##BASE##_14(uint32_t opcode) { IMM5_INSN(OP,20); } \
|
|
| 281 |
+ static INSN_REGPARM void thumb##BASE##_15(uint32_t opcode) { IMM5_INSN(OP,21); } \
|
|
| 282 |
+ static INSN_REGPARM void thumb##BASE##_16(uint32_t opcode) { IMM5_INSN(OP,22); } \
|
|
| 283 |
+ static INSN_REGPARM void thumb##BASE##_17(uint32_t opcode) { IMM5_INSN(OP,23); } \
|
|
| 284 |
+ static INSN_REGPARM void thumb##BASE##_18(uint32_t opcode) { IMM5_INSN(OP,24); } \
|
|
| 285 |
+ static INSN_REGPARM void thumb##BASE##_19(uint32_t opcode) { IMM5_INSN(OP,25); } \
|
|
| 286 |
+ static INSN_REGPARM void thumb##BASE##_1A(uint32_t opcode) { IMM5_INSN(OP,26); } \
|
|
| 287 |
+ static INSN_REGPARM void thumb##BASE##_1B(uint32_t opcode) { IMM5_INSN(OP,27); } \
|
|
| 288 |
+ static INSN_REGPARM void thumb##BASE##_1C(uint32_t opcode) { IMM5_INSN(OP,28); } \
|
|
| 289 |
+ static INSN_REGPARM void thumb##BASE##_1D(uint32_t opcode) { IMM5_INSN(OP,29); } \
|
|
| 290 |
+ static INSN_REGPARM void thumb##BASE##_1E(uint32_t opcode) { IMM5_INSN(OP,30); } \
|
|
| 291 |
+ static INSN_REGPARM void thumb##BASE##_1F(uint32_t opcode) { IMM5_INSN(OP,31); }
|
|
| 983 | 292 |
|
| 984 | 293 |
// LSL Rd, Rm, #Imm 5 |
| 985 | 294 |
DEFINE_IMM5_INSN(IMM5_LSL, 00) |
| ... | ... |
@@ -991,24 +300,24 @@ DEFINE_IMM5_INSN(IMM5_ASR, 10) |
| 991 | 300 |
// 3-argument ADD/SUB ///////////////////////////////////////////////////// |
| 992 | 301 |
|
| 993 | 302 |
#define DEFINE_REG3_INSN(OP, BASE) \ |
| 994 |
- static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP, 0); } \
|
|
| 995 |
- static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP, 1); } \
|
|
| 996 |
- static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP, 2); } \
|
|
| 997 |
- static INSN_REGPARM void thumb##BASE##_3(uint32_t opcode) { THREEARG_INSN(OP, 3); } \
|
|
| 998 |
- static INSN_REGPARM void thumb##BASE##_4(uint32_t opcode) { THREEARG_INSN(OP, 4); } \
|
|
| 999 |
- static INSN_REGPARM void thumb##BASE##_5(uint32_t opcode) { THREEARG_INSN(OP, 5); } \
|
|
| 1000 |
- static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP, 6); } \
|
|
| 1001 |
- static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP, 7); }
|
|
| 303 |
+ static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP,0); } \
|
|
| 304 |
+ static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP,1); } \
|
|
| 305 |
+ static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP,2); } \
|
|
| 306 |
+ static INSN_REGPARM void thumb##BASE##_3(uint32_t opcode) { THREEARG_INSN(OP,3); } \
|
|
| 307 |
+ static INSN_REGPARM void thumb##BASE##_4(uint32_t opcode) { THREEARG_INSN(OP,4); } \
|
|
| 308 |
+ static INSN_REGPARM void thumb##BASE##_5(uint32_t opcode) { THREEARG_INSN(OP,5); } \
|
|
| 309 |
+ static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP,6); } \
|
|
| 310 |
+ static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP,7); }
|
|
| 1002 | 311 |
|
| 1003 | 312 |
#define DEFINE_IMM3_INSN(OP, BASE) \ |
| 1004 |
- static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP##_0, 0); } \
|
|
| 1005 |
- static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP, 1); } \
|
|
| 1006 |
- static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP, 2); } \
|
|
| 1007 |
- static INSN_REGPARM void thumb##BASE##_3(uint32_t opcode) { THREEARG_INSN(OP, 3); } \
|
|
| 1008 |
- static INSN_REGPARM void thumb##BASE##_4(uint32_t opcode) { THREEARG_INSN(OP, 4); } \
|
|
| 1009 |
- static INSN_REGPARM void thumb##BASE##_5(uint32_t opcode) { THREEARG_INSN(OP, 5); } \
|
|
| 1010 |
- static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP, 6); } \
|
|
| 1011 |
- static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP, 7); }
|
|
| 313 |
+ static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP##_0,0); } \
|
|
| 314 |
+ static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP,1); } \
|
|
| 315 |
+ static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP,2); } \
|
|
| 316 |
+ static INSN_REGPARM void thumb##BASE##_3(uint32_t opcode) { THREEARG_INSN(OP,3); } \
|
|
| 317 |
+ static INSN_REGPARM void thumb##BASE##_4(uint32_t opcode) { THREEARG_INSN(OP,4); } \
|
|
| 318 |
+ static INSN_REGPARM void thumb##BASE##_5(uint32_t opcode) { THREEARG_INSN(OP,5); } \
|
|
| 319 |
+ static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP,6); } \
|
|
| 320 |
+ static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP,7); }
|
|
| 1012 | 321 |
|
| 1013 | 322 |
// ADD Rd, Rs, Rn |
| 1014 | 323 |
DEFINE_REG3_INSN(ADD_RD_RS_RN, 18) |
| ... | ... |
@@ -1122,9 +431,7 @@ static INSN_REGPARM void thumb40_2(uint32_t opcode) |
| 1122 | 431 |
C_FLAG = !!(reg[dest].I & 1); |
| 1123 | 432 |
} |
| 1124 | 433 |
else if (value < 32) |
| 1125 |
- {
|
|
| 1126 |
- LSL_RD_RS; |
|
| 1127 |
- } |
|
| 434 |
+ LSL_RD_RS |
|
| 1128 | 435 |
else |
| 1129 | 436 |
{
|
| 1130 | 437 |
value = 0; |
| ... | ... |
@@ -1150,9 +457,7 @@ static INSN_REGPARM void thumb40_3(uint32_t opcode) |
| 1150 | 457 |
C_FLAG = !!(reg[dest].I & 0x80000000); |
| 1151 | 458 |
} |
| 1152 | 459 |
else if (value < 32) |
| 1153 |
- {
|
|
| 1154 |
- LSR_RD_RS; |
|
| 1155 |
- } |
|
| 460 |
+ LSR_RD_RS |
|
| 1156 | 461 |
else |
| 1157 | 462 |
{
|
| 1158 | 463 |
value = 0; |
| ... | ... |
@@ -1220,7 +525,7 @@ static INSN_REGPARM void thumb41_3(uint32_t opcode) |
| 1220 | 525 |
|
| 1221 | 526 |
if (value) |
| 1222 | 527 |
{
|
| 1223 |
- value = value & 0x1f; |
|
| 528 |
+ value &= 0x1f; |
|
| 1224 | 529 |
if (!value) |
| 1225 | 530 |
C_FLAG = !!(reg[dest].I & 0x80000000); |
| 1226 | 531 |
else |
| ... | ... |
@@ -1229,9 +534,9 @@ static INSN_REGPARM void thumb41_3(uint32_t opcode) |
| 1229 | 534 |
reg[dest].I = value; |
| 1230 | 535 |
} |
| 1231 | 536 |
} |
| 537 |
+ clockTicks = codeTicksAccess16(armNextPC) + 2; |
|
| 1232 | 538 |
N_FLAG = !!(reg[dest].I & 0x80000000); |
| 1233 | 539 |
Z_FLAG = !reg[dest].I; |
| 1234 |
- clockTicks = codeTicksAccess16(armNextPC) + 2; |
|
| 1235 | 540 |
} |
| 1236 | 541 |
|
| 1237 | 542 |
// TST Rd, Rs |
| ... | ... |
@@ -1271,8 +576,8 @@ static INSN_REGPARM void thumb43_0(uint32_t opcode) |
| 1271 | 576 |
{
|
| 1272 | 577 |
int dest = opcode & 7; |
| 1273 | 578 |
reg[dest].I |= reg[(opcode >> 3) & 7].I; |
| 1274 |
- N_FLAG = !!(reg[dest].I & 0x80000000); |
|
| 1275 | 579 |
Z_FLAG = !reg[dest].I; |
| 580 |
+ N_FLAG = !!(reg[dest].I & 0x80000000); |
|
| 1276 | 581 |
} |
| 1277 | 582 |
|
| 1278 | 583 |
// MUL Rd, Rs |
| ... | ... |
@@ -1293,9 +598,9 @@ static INSN_REGPARM void thumb43_1(uint32_t opcode) |
| 1293 | 598 |
else |
| 1294 | 599 |
clockTicks += 3; |
| 1295 | 600 |
busPrefetchCount = (busPrefetchCount << clockTicks) | (0xFF >> (8 - clockTicks)); |
| 1296 |
- N_FLAG = !!(reg[dest].I & 0x80000000); |
|
| 1297 |
- Z_FLAG = !reg[dest].I; |
|
| 1298 | 601 |
clockTicks += codeTicksAccess16(armNextPC) + 1; |
| 602 |
+ Z_FLAG = !reg[dest].I; |
|
| 603 |
+ N_FLAG = !!(reg[dest].I & 0x80000000); |
|
| 1299 | 604 |
} |
| 1300 | 605 |
|
| 1301 | 606 |
// BIC Rd, Rs |
| ... | ... |
@@ -1303,8 +608,8 @@ static INSN_REGPARM void thumb43_2(uint32_t opcode) |
| 1303 | 608 |
{
|
| 1304 | 609 |
int dest = opcode & 7; |
| 1305 | 610 |
reg[dest].I &= ~reg[(opcode >> 3) & 7].I; |
| 1306 |
- N_FLAG = !!(reg[dest].I & 0x80000000); |
|
| 1307 | 611 |
Z_FLAG = !reg[dest].I; |
| 612 |
+ N_FLAG = !!(reg[dest].I & 0x80000000); |
|
| 1308 | 613 |
} |
| 1309 | 614 |
|
| 1310 | 615 |
// MVN Rd, Rs |
| ... | ... |
@@ -1312,8 +617,8 @@ static INSN_REGPARM void thumb43_3(uint32_t opcode) |
| 1312 | 617 |
{
|
| 1313 | 618 |
int dest = opcode & 7; |
| 1314 | 619 |
reg[dest].I = ~reg[(opcode >> 3) & 7].I; |
| 1315 |
- N_FLAG = !!(reg[dest].I & 0x80000000); |
|
| 1316 | 620 |
Z_FLAG = !reg[dest].I; |
| 621 |
+ N_FLAG = !!(reg[dest].I & 0x80000000); |
|
| 1317 | 622 |
} |
| 1318 | 623 |
|
| 1319 | 624 |
// High-register instructions and BX ////////////////////////////////////// |
| ... | ... |
@@ -1321,7 +626,7 @@ static INSN_REGPARM void thumb43_3(uint32_t opcode) |
| 1321 | 626 |
// ADD Rd, Hs |
| 1322 | 627 |
static INSN_REGPARM void thumb44_1(uint32_t opcode) |
| 1323 | 628 |
{
|
| 1324 |
- reg[opcode & 7].I += reg[((opcode >> 3) & 7) + 8].I; |
|
| 629 |
+ reg[opcode&7].I += reg[((opcode >> 3) & 7) + 8].I; |
|
| 1325 | 630 |
} |
| 1326 | 631 |
|
| 1327 | 632 |
// ADD Hd, Rs |
| ... | ... |
@@ -1379,7 +684,7 @@ static INSN_REGPARM void thumb45_3(uint32_t opcode) |
| 1379 | 684 |
// MOV Rd, Rs |
| 1380 | 685 |
static INSN_REGPARM void thumb46_0(uint32_t opcode) |
| 1381 | 686 |
{
|
| 1382 |
- reg[opcode & 7].I = reg[(opcode >> 3) & 7].I; |
|
| 687 |
+ reg[opcode & 7].I = reg[((opcode >> 3) & 7)].I; |
|
| 1383 | 688 |
clockTicks = codeTicksAccessSeq16(armNextPC) + 1; |
| 1384 | 689 |
} |
| 1385 | 690 |
|
| ... | ... |
@@ -1650,29 +955,33 @@ static INSN_REGPARM void thumbB0(uint32_t opcode) |
| 1650 | 955 |
|
| 1651 | 956 |
// Push and pop /////////////////////////////////////////////////////////// |
| 1652 | 957 |
|
| 1653 |
-#define PUSH_REG(val, r) \ |
|
| 1654 |
- if (opcode & (val)) \ |
|
| 1655 |
- { \
|
|
| 1656 |
- CPUWriteMemory(address, reg[(r)].I); \ |
|
| 1657 |
- if (!count) \ |
|
| 1658 |
- clockTicks += 1 + dataTicksAccess32(address); \ |
|
| 1659 |
- else \ |
|
| 1660 |
- clockTicks += 1 + dataTicksAccessSeq32(address); \ |
|
| 1661 |
- ++count; \ |
|
| 1662 |
- address += 4; \ |
|
| 958 |
+auto PUSH_REG = [](uint32_t opcode, uint32_t &address, int &count, uint32_t val, uint32_t r) |
|
| 959 |
+{
|
|
| 960 |
+ if (opcode & val) |
|
| 961 |
+ {
|
|
| 962 |
+ CPUWriteMemory(address, reg[r].I); |
|
| 963 |
+ if (!count) |
|
| 964 |
+ clockTicks += 1 + dataTicksAccess32(address); |
|
| 965 |
+ else |
|
| 966 |
+ clockTicks += 1 + dataTicksAccessSeq32(address); |
|
| 967 |
+ ++count; |
|
| 968 |
+ address += 4; |
|
| 1663 | 969 |
} |
| 970 |
+}; |
|
| 1664 | 971 |
|
| 1665 |
-#define POP_REG(val, r) \ |
|
| 1666 |
- if (opcode & (val)) \ |
|
| 1667 |
- { \
|
|
| 1668 |
- reg[(r)].I = CPUReadMemory(address); \ |
|
| 1669 |
- if (!count) \ |
|
| 1670 |
- clockTicks += 1 + dataTicksAccess32(address); \ |
|
| 1671 |
- else \ |
|
| 1672 |
- clockTicks += 1 + dataTicksAccessSeq32(address); \ |
|
| 1673 |
- ++count; \ |
|
| 1674 |
- address += 4; \ |
|
| 972 |
+auto POP_REG = [](uint32_t opcode, uint32_t &address, int &count, uint32_t val, uint32_t r) |
|
| 973 |
+{
|
|
| 974 |
+ if (opcode & val) |
|
| 975 |
+ {
|
|
| 976 |
+ reg[r].I = CPUReadMemory(address); |
|
| 977 |
+ if (!count) |
|
| 978 |
+ clockTicks += 1 + dataTicksAccess32(address); |
|
| 979 |
+ else |
|
| 980 |
+ clockTicks += 1 + dataTicksAccessSeq32(address); |
|
| 981 |
+ ++count; |
|
| 982 |
+ address += 4; |
|
| 1675 | 983 |
} |
| 984 |
+}; |
|
| 1676 | 985 |
|
| 1677 | 986 |
// PUSH {Rlist}
|
| 1678 | 987 |
static INSN_REGPARM void thumbB4(uint32_t opcode) |
| ... | ... |
@@ -1682,14 +991,14 @@ static INSN_REGPARM void thumbB4(uint32_t opcode) |
| 1682 | 991 |
int count = 0; |
| 1683 | 992 |
uint32_t temp = reg[13].I - 4 * cpuBitsSet[opcode & 0xff]; |
| 1684 | 993 |
uint32_t address = temp & 0xFFFFFFFC; |
| 1685 |
- PUSH_REG(1, 0); |
|
| 1686 |
- PUSH_REG(2, 1); |
|
| 1687 |
- PUSH_REG(4, 2); |
|
| 1688 |
- PUSH_REG(8, 3); |
|
| 1689 |
- PUSH_REG(16, 4); |
|
| 1690 |
- PUSH_REG(32, 5); |
|
| 1691 |
- PUSH_REG(64, 6); |
|
| 1692 |
- PUSH_REG(128, 7); |
|
| 994 |
+ PUSH_REG(opcode, address, count, 1, 0); |
|
| 995 |
+ PUSH_REG(opcode, address, count, 2, 1); |
|
| 996 |
+ PUSH_REG(opcode, address, count, 4, 2); |
|
| 997 |
+ PUSH_REG(opcode, address, count, 8, 3); |
|
| 998 |
+ PUSH_REG(opcode, address, count, 16, 4); |
|
| 999 |
+ PUSH_REG(opcode, address, count, 32, 5); |
|
| 1000 |
+ PUSH_REG(opcode, address, count, 64, 6); |
|
| 1001 |
+ PUSH_REG(opcode, address, count, 128, 7); |
|
| 1693 | 1002 |
clockTicks += 1 + codeTicksAccess16(armNextPC); |
| 1694 | 1003 |
reg[13].I = temp; |
| 1695 | 1004 |
} |
| ... | ... |
@@ -1702,15 +1011,15 @@ static INSN_REGPARM void thumbB5(uint32_t opcode) |
| 1702 | 1011 |
int count = 0; |
| 1703 | 1012 |
uint32_t temp = reg[13].I - 4 - 4 * cpuBitsSet[opcode & 0xff]; |
| 1704 | 1013 |
uint32_t address = temp & 0xFFFFFFFC; |
| 1705 |
- PUSH_REG(1, 0); |
|
| 1706 |
- PUSH_REG(2, 1); |
|
| 1707 |
- PUSH_REG(4, 2); |
|
| 1708 |
- PUSH_REG(8, 3); |
|
| 1709 |
- PUSH_REG(16, 4); |
|
| 1710 |
- PUSH_REG(32, 5); |
|
| 1711 |
- PUSH_REG(64, 6); |
|
| 1712 |
- PUSH_REG(128, 7); |
|
| 1713 |
- PUSH_REG(256, 14); |
|
| 1014 |
+ PUSH_REG(opcode, address, count, 1, 0); |
|
| 1015 |
+ PUSH_REG(opcode, address, count, 2, 1); |
|
| 1016 |
+ PUSH_REG(opcode, address, count, 4, 2); |
|
| 1017 |
+ PUSH_REG(opcode, address, count, 8, 3); |
|
| 1018 |
+ PUSH_REG(opcode, address, count, 16, 4); |
|
| 1019 |
+ PUSH_REG(opcode, address, count, 32, 5); |
|
| 1020 |
+ PUSH_REG(opcode, address, count, 64, 6); |
|
| 1021 |
+ PUSH_REG(opcode, address, count, 128, 7); |
|
| 1022 |
+ PUSH_REG(opcode, address, count, 256, 14); |
|
| 1714 | 1023 |
clockTicks += 1 + codeTicksAccess16(armNextPC); |
| 1715 | 1024 |
reg[13].I = temp; |
| 1716 | 1025 |
} |
| ... | ... |
@@ -1723,14 +1032,14 @@ static INSN_REGPARM void thumbBC(uint32_t opcode) |
| 1723 | 1032 |
int count = 0; |
| 1724 | 1033 |
uint32_t address = reg[13].I & 0xFFFFFFFC; |
| 1725 | 1034 |
uint32_t temp = reg[13].I + 4 * cpuBitsSet[opcode & 0xFF]; |
| 1726 |
- POP_REG(1, 0); |
|
| 1727 |
- POP_REG(2, 1); |
|
| 1728 |
- POP_REG(4, 2); |
|
| 1729 |
- POP_REG(8, 3); |
|
| 1730 |
- POP_REG(16, 4); |
|
| 1731 |
- POP_REG(32, 5); |
|
| 1732 |
- POP_REG(64, 6); |
|
| 1733 |
- POP_REG(128, 7); |
|
| 1035 |
+ POP_REG(opcode, address, count, 1, 0); |
|
| 1036 |
+ POP_REG(opcode, address, count, 2, 1); |
|
| 1037 |
+ POP_REG(opcode, address, count, 4, 2); |
|
| 1038 |
+ POP_REG(opcode, address, count, 8, 3); |
|
| 1039 |
+ POP_REG(opcode, address, count, 16, 4); |
|
| 1040 |
+ POP_REG(opcode, address, count, 32, 5); |
|
| 1041 |
+ POP_REG(opcode, address, count, 64, 6); |
|
| 1042 |
+ POP_REG(opcode, address, count, 128, 7); |
|
| 1734 | 1043 |
reg[13].I = temp; |
| 1735 | 1044 |
clockTicks = 2 + codeTicksAccess16(armNextPC); |
| 1736 | 1045 |
} |
| ... | ... |
@@ -1743,14 +1052,14 @@ static INSN_REGPARM void thumbBD(uint32_t opcode) |
| 1743 | 1052 |
int count = 0; |
| 1744 | 1053 |
uint32_t address = reg[13].I & 0xFFFFFFFC; |
| 1745 | 1054 |
uint32_t temp = reg[13].I + 4 + 4 * cpuBitsSet[opcode & 0xFF]; |
| 1746 |
- POP_REG(1, 0); |
|
| 1747 |
- POP_REG(2, 1); |
|
| 1748 |
- POP_REG(4, 2); |
|
| 1749 |
- POP_REG(8, 3); |
|
| 1750 |
- POP_REG(16, 4); |
|
| 1751 |
- POP_REG(32, 5); |
|
| 1752 |
- POP_REG(64, 6); |
|
| 1753 |
- POP_REG(128, 7); |
|
| 1055 |
+ POP_REG(opcode, address, count, 1, 0); |
|
| 1056 |
+ POP_REG(opcode, address, count, 2, 1); |
|
| 1057 |
+ POP_REG(opcode, address, count, 4, 2); |
|
| 1058 |
+ POP_REG(opcode, address, count, 8, 3); |
|
| 1059 |
+ POP_REG(opcode, address, count, 16, 4); |
|
| 1060 |
+ POP_REG(opcode, address, count, 32, 5); |
|
| 1061 |
+ POP_REG(opcode, address, count, 64, 6); |
|
| 1062 |
+ POP_REG(opcode, address, count, 128, 7); |
|
| 1754 | 1063 |
reg[15].I = CPUReadMemory(address) & 0xFFFFFFFE; |
| 1755 | 1064 |
if (!count) |
| 1756 | 1065 |
clockTicks += 1 + dataTicksAccess32(address); |
| ... | ... |
@@ -1777,7 +1086,7 @@ static INSN_REGPARM void thumbC0(uint32_t opcode) |
| 1777 | 1086 |
uint32_t temp = reg[regist].I + 4 * cpuBitsSet[opcode & 0xff]; |
| 1778 | 1087 |
int count = 0; |
| 1779 | 1088 |
// store |
| 1780 |
- auto THUMB_STM_REG = [&](int val, int r, uint8_t b) |
|
| 1089 |
+ auto THUMB_STM_REG = [&](uint32_t val, uint32_t r, uint8_t b) |
|
| 1781 | 1090 |
{
|
| 1782 | 1091 |
if (opcode & val) |
| 1783 | 1092 |
{
|
| ... | ... |
@@ -1812,7 +1121,7 @@ static INSN_REGPARM void thumbC8(uint32_t opcode) |
| 1812 | 1121 |
uint32_t temp = reg[regist].I + 4 * cpuBitsSet[opcode & 0xFF]; |
| 1813 | 1122 |
int count = 0; |
| 1814 | 1123 |
// load |
| 1815 |
- auto THUMB_LDM_REG = [&](int val, int r) |
|
| 1124 |
+ auto THUMB_LDM_REG = [&](uint32_t val, uint32_t r) |
|
| 1816 | 1125 |
{
|
| 1817 | 1126 |
if (opcode & val) |
| 1818 | 1127 |
{
|
| ... | ... |
@@ -2055,6 +1364,8 @@ static INSN_REGPARM void thumbDD(uint32_t opcode) |
| 2055 | 1364 |
// SWI #comment |
| 2056 | 1365 |
static INSN_REGPARM void thumbDF(uint32_t opcode) |
| 2057 | 1366 |
{
|
| 1367 |
+ uint32_t address = 0; |
|
| 1368 |
+ //clockTicks = codeTicksAccessSeq16(address) * 2 + codeTicksAccess16(address) + 3; |
|
| 2058 | 1369 |
clockTicks = 3; |
| 2059 | 1370 |
busPrefetchCount = 0; |
| 2060 | 1371 |
CPUSoftwareInterrupt(opcode & 0xFF); |
| ... | ... |
@@ -2238,7 +1549,7 @@ static insnfunc_t thumbInsnTable[] = |
| 2238 | 1549 |
thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8, // F8 |
| 2239 | 1550 |
thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8, |
| 2240 | 1551 |
thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8, |
| 2241 |
- thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8, |
|
| 1552 |
+ thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8 |
|
| 2242 | 1553 |
}; |
| 2243 | 1554 |
|
| 2244 | 1555 |
// Wrapper routine (execution loop) /////////////////////////////////////// |
| ... | ... |
@@ -2247,6 +1558,9 @@ int thumbExecute() |
| 2247 | 1558 |
{
|
| 2248 | 1559 |
do |
| 2249 | 1560 |
{
|
| 1561 |
+ //if ((armNextPC & 0x0803FFFF) == 0x08020000) |
|
| 1562 |
+ // busPrefetchCount = 0x100; |
|
| 1563 |
+ |
|
| 2250 | 1564 |
uint32_t opcode = cpuPrefetch[0]; |
| 2251 | 1565 |
cpuPrefetch[0] = cpuPrefetch[1]; |
| 2252 | 1566 |
|
| ... | ... |
@@ -1,6 +1,4 @@ |
| 1 | 1 |
#include <algorithm> |
| 2 |
-#include <cstdlib> |
|
| 3 |
-#include <cstring> |
|
| 4 | 2 |
#include "GBA.h" |
| 5 | 3 |
#include "GBAcpu.h" |
| 6 | 4 |
#include "GBAinline.h" |
| ... | ... |
@@ -19,7 +17,8 @@ bool busPrefetch = false; |
| 19 | 17 |
bool busPrefetchEnable = false; |
| 20 | 18 |
uint32_t busPrefetchCount = 0; |
| 21 | 19 |
static int cpuDmaTicksToUpdate = 0; |
| 22 |
-static uint32_t cpuDmaLast = 0; |
|
| 20 |
+bool cpuDmaHack = false; |
|
| 21 |
+uint32_t cpuDmaLast = 0; |
|
| 23 | 22 |
static int dummyAddress = 0; |
| 24 | 23 |
|
| 25 | 24 |
int cpuNextEvent = 0; |
| ... | ... |
@@ -27,7 +26,6 @@ int cpuNextEvent = 0; |
| 27 | 26 |
static bool intState = false; |
| 28 | 27 |
bool stopState = false; |
| 29 | 28 |
bool holdState = false; |
| 30 |
-int holdType = 0; |
|
| 31 | 29 |
|
| 32 | 30 |
uint32_t cpuPrefetch[2]; |
| 33 | 31 |
|
| ... | ... |
@@ -63,8 +61,6 @@ uint32_t dma2Source = 0; |
| 63 | 61 |
uint32_t dma2Dest = 0; |
| 64 | 62 |
uint32_t dma3Source = 0; |
| 65 | 63 |
uint32_t dma3Dest = 0; |
| 66 |
-char buffer[1024]; |
|
| 67 |
-int count = 0; |
|
| 68 | 64 |
|
| 69 | 65 |
static const int TIMER_TICKS[] = { 0, 6, 8, 10 };
|
| 70 | 66 |
|
| ... | ... |
@@ -80,6 +76,14 @@ uint8_t memoryWait32[] = { 0, 0, 5, 0, 0, 1, 1, 0, 7, 7, 9, 9, 13, 13, 4, 0 };
|
| 80 | 76 |
uint8_t memoryWaitSeq[] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4, 0 };
|
| 81 | 77 |
uint8_t memoryWaitSeq32[] = { 0, 0, 5, 0, 0, 1, 1, 0, 5, 5, 9, 9, 17, 17, 4, 0 };
|
| 82 | 78 |
|
| 79 |
+// The videoMemoryWait constants are used to add some waitstates |
|
| 80 |
+// if the opcode access video memory data outside of vblank/hblank |
|
| 81 |
+// It seems to happen on only one ticks for each pixel. |
|
| 82 |
+// Not used for now (too problematic with current code). |
|
| 83 |
+//const u8 videoMemoryWait[16] = |
|
| 84 |
+// {0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0};
|
|
| 85 |
+ |
|
| 86 |
+ |
|
| 83 | 87 |
uint8_t biosProtected[4]; |
| 84 | 88 |
|
| 85 | 89 |
#ifdef WORDS_BIGENDIAN |
| ... | ... |
@@ -294,17 +298,18 @@ int CPULoadRom() |
| 294 | 298 |
{
|
| 295 | 299 |
romSize = 0x2000000; |
| 296 | 300 |
|
| 301 |
+ memset(&rom[0], 0, 0x2000000); |
|
| 297 | 302 |
memset(&workRAM[0], 0, 0x40000); |
| 298 | 303 |
|
| 299 | 304 |
if (cpuIsMultiBoot) |
| 300 |
- mapgsf(workRAM, 0x40000, romSize); |
|
| 305 |
+ mapgsf(&workRAM[0], 0x40000, romSize); |
|
| 301 | 306 |
else |
| 302 |
- mapgsf(rom, 0x2000000, romSize); |
|
| 307 |
+ mapgsf(&rom[0], 0x2000000, romSize); |
|
| 303 | 308 |
|
| 304 |
- uint16_t *temp = reinterpret_cast<uint16_t *>(rom + ((romSize + 1) & ~1)); |
|
| 309 |
+ auto temp = reinterpret_cast<uint16_t *>(&rom[(romSize + 1) & ~1]); |
|
| 305 | 310 |
for (int i = (romSize + 1) & ~1; i < 0x2000000; i += 2) |
| 306 | 311 |
{
|
| 307 |
- WRITE16LE(temp, (i >> 1) & 0xFFFF); |
|
| 312 |
+ WRITE16LE(&temp[0], (i >> 1) & 0xFFFF); |
|
| 308 | 313 |
++temp; |
| 309 | 314 |
} |
| 310 | 315 |
|
| ... | ... |
@@ -353,6 +358,9 @@ void CPUUpdateFlags(bool breakLoop) |
| 353 | 358 |
|
| 354 | 359 |
void CPUSwitchMode(int mode, bool saveState, bool breakLoop) |
| 355 | 360 |
{
|
| 361 |
+ //if(armMode == mode) |
|
| 362 |
+ // return; |
|
| 363 |
+ |
|
| 356 | 364 |
CPUUpdateCPSR(); |
| 357 | 365 |
|
| 358 | 366 |
switch (armMode) |
| ... | ... |
@@ -505,7 +513,6 @@ void CPUSoftwareInterrupt(int comment) |
| 505 | 513 |
break; |
| 506 | 514 |
case 0x02: |
| 507 | 515 |
holdState = true; |
| 508 |
- holdType = -1; |
|
| 509 | 516 |
cpuNextEvent = cpuTotalTicks; |
| 510 | 517 |
break; |
| 511 | 518 |
case 0x03: |
| ... | ... |
@@ -526,41 +533,41 @@ void CPUSoftwareInterrupt(int comment) |
| 526 | 533 |
BIOS_ArcTan2(); |
| 527 | 534 |
break; |
| 528 | 535 |
case 0x0B: |
| 529 |
- {
|
|
| 530 |
- int len = (reg[2].I & 0x1FFFFF) >> 1; |
|
| 531 |
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + len) & 0xe000000))) |
|
| 532 | 536 |
{
|
| 533 |
- if ((reg[2].I >> 24) & 1) |
|
| 537 |
+ int len = (reg[2].I & 0x1FFFFF) >> 1; |
|
| 538 |
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + len) & 0xe000000))) |
|
| 534 | 539 |
{
|
| 535 |
- if ((reg[2].I >> 26) & 1) |
|
| 536 |
- SWITicks = (7 + memoryWait32[(reg[1].I >> 24) & 0xF]) * (len >> 1); |
|
| 537 |
- else |
|
| 538 |
- SWITicks = (8 + memoryWait[(reg[1].I >> 24) & 0xF]) * len; |
|
| 539 |
- } |
|
| 540 |
- else |
|
| 541 |
- {
|
|
| 542 |
- if ((reg[2].I >> 26) & 1) |
|
| 543 |
- SWITicks = (10 + memoryWait32[(reg[0].I >> 24) & 0xF] + memoryWait32[(reg[1].I >> 24) & 0xF]) * (len >> 1); |
|
| 540 |
+ if ((reg[2].I >> 24) & 1) |
|
| 541 |
+ {
|
|
| 542 |
+ if ((reg[2].I >> 26) & 1) |
|
| 543 |
+ SWITicks = (7 + memoryWait32[(reg[1].I >> 24) & 0xF]) * (len >> 1); |
|
| 544 |
+ else |
|
| 545 |
+ SWITicks = (8 + memoryWait[(reg[1].I >> 24) & 0xF]) * len; |
|
| 546 |
+ } |
|
| 544 | 547 |
else |
| 545 |
- SWITicks = (11 + memoryWait[(reg[0].I >> 24) & 0xF] + memoryWait[(reg[1].I >> 24) & 0xF]) * len; |
|
| 548 |
+ {
|
|
| 549 |
+ if ((reg[2].I >> 26) & 1) |
|
| 550 |
+ SWITicks = (10 + memoryWait32[(reg[0].I >> 24) & 0xF] + memoryWait32[(reg[1].I >> 24) & 0xF]) * (len >> 1); |
|
| 551 |
+ else |
|
| 552 |
+ SWITicks = (11 + memoryWait[(reg[0].I >> 24) & 0xF] + memoryWait[(reg[1].I >> 24) & 0xF]) * len; |
|
| 553 |
+ } |
|
| 546 | 554 |
} |
| 547 | 555 |
} |
| 548 | 556 |
BIOS_CpuSet(); |
| 549 | 557 |
break; |
| 550 |
- } |
|
| 551 | 558 |
case 0x0C: |
| 552 |
- {
|
|
| 553 |
- int len = (reg[2].I & 0x1FFFFF) >> 5; |
|
| 554 |
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + len) & 0xe000000))) |
|
| 555 | 559 |
{
|
| 556 |
- if ((reg[2].I >> 24) & 1) |
|
| 557 |
- SWITicks = (6 + memoryWait32[(reg[1].I >> 24) & 0xF] + 7 * (memoryWaitSeq32[(reg[1].I >> 24) & 0xF] + 1)) * len; |
|
| 558 |
- else |
|
| 559 |
- SWITicks = (9 + memoryWait32[(reg[0].I >> 24) & 0xF] + memoryWait32[(reg[1].I >> 24) & 0xF] + 7 * (memoryWaitSeq32[(reg[0].I >> 24) & 0xF] + memoryWaitSeq32[(reg[1].I >> 24) & 0xF] + 2)) * len; |
|
| 560 |
+ int len = (reg[2].I & 0x1FFFFF) >> 5; |
|
| 561 |
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + len) & 0xe000000))) |
|
| 562 |
+ {
|
|
| 563 |
+ if ((reg[2].I >> 24) & 1) |
|
| 564 |
+ SWITicks = (6 + memoryWait32[(reg[1].I >> 24) & 0xF] + 7 * (memoryWaitSeq32[(reg[1].I >> 24) & 0xF] + 1)) * len; |
|
| 565 |
+ else |
|
| 566 |
+ SWITicks = (9 + memoryWait32[(reg[0].I >> 24) & 0xF] + memoryWait32[(reg[1].I >> 24) & 0xF] + 7 * (memoryWaitSeq32[(reg[0].I >> 24) & 0xF] + memoryWaitSeq32[(reg[1].I >> 24) & 0xF] + 2)) * len; |
|
| 567 |
+ } |
|
| 560 | 568 |
} |
| 561 | 569 |
BIOS_CpuFastSet(); |
| 562 | 570 |
break; |
| 563 |
- } |
|
| 564 | 571 |
case 0x0D: |
| 565 | 572 |
BIOS_GetBiosChecksum(); |
| 566 | 573 |
break; |
| ... | ... |
@@ -571,77 +578,77 @@ void CPUSoftwareInterrupt(int comment) |
| 571 | 578 |
BIOS_ObjAffineSet(); |
| 572 | 579 |
break; |
| 573 | 580 |
case 0x10: |
| 574 |
- {
|
|
| 575 |
- int len = CPUReadHalfWord(reg[2].I); |
|
| 576 |
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + len) & 0xe000000))) |
|
| 577 |
- SWITicks = (32 + memoryWait[(reg[0].I >> 24) & 0xF]) * len; |
|
| 581 |
+ {
|
|
| 582 |
+ int len = CPUReadHalfWord(reg[2].I); |
|
| 583 |
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + len) & 0xe000000))) |
|
| 584 |
+ SWITicks = (32 + memoryWait[(reg[0].I >> 24) & 0xF]) * len; |
|
| 585 |
+ } |
|
| 578 | 586 |
BIOS_BitUnPack(); |
| 579 | 587 |
break; |
| 580 |
- } |
|
| 581 | 588 |
case 0x11: |
| 582 |
- {
|
|
| 583 |
- uint32_t len = CPUReadMemory(reg[0].I) >> 8; |
|
| 584 |
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000))) |
|
| 585 |
- SWITicks = (9 + memoryWait[(reg[1].I >> 24) & 0xF]) * len; |
|
| 589 |
+ {
|
|
| 590 |
+ uint32_t len = CPUReadMemory(reg[0].I) >> 8; |
|
| 591 |
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000))) |
|
| 592 |
+ SWITicks = (9 + memoryWait[(reg[1].I >> 24) & 0xF]) * len; |
|
| 593 |
+ } |
|
| 586 | 594 |
BIOS_LZ77UnCompWram(); |
| 587 | 595 |
break; |
| 588 |
- } |
|
| 589 | 596 |
case 0x12: |
| 590 |
- {
|
|
| 591 |
- uint32_t len = CPUReadMemory(reg[0].I) >> 8; |
|
| 592 |
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000))) |
|
| 593 |
- SWITicks = (19 + memoryWait[(reg[1].I >> 24) & 0xF]) * len; |
|
| 597 |
+ {
|
|
| 598 |
+ uint32_t len = CPUReadMemory(reg[0].I) >> 8; |
|
| 599 |
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000))) |
|
| 600 |
+ SWITicks = (19 + memoryWait[(reg[1].I >> 24) & 0xF]) * len; |
|
| 601 |
+ } |
|
| 594 | 602 |
BIOS_LZ77UnCompVram(); |
| 595 | 603 |
break; |
| 596 |
- } |
|
| 597 | 604 |
case 0x13: |
| 598 |
- {
|
|
| 599 |
- uint32_t len = CPUReadMemory(reg[0].I) >> 8; |
|
| 600 |
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000))) |
|
| 601 |
- SWITicks = (29 + (memoryWait[(reg[0].I >> 24) & 0xF] << 1)) * len; |
|
| 605 |
+ {
|
|
| 606 |
+ uint32_t len = CPUReadMemory(reg[0].I) >> 8; |
|
| 607 |
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000))) |
|
| 608 |
+ SWITicks = (29 + (memoryWait[(reg[0].I >> 24) & 0xF] << 1)) * len; |
|
| 609 |
+ } |
|
| 602 | 610 |
BIOS_HuffUnComp(); |
| 603 | 611 |
break; |
| 604 |
- } |
|
| 605 | 612 |
case 0x14: |
| 606 |
- {
|
|
| 607 |
- uint32_t len = CPUReadMemory(reg[0].I) >> 8; |
|
| 608 |
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000))) |
|
| 609 |
- SWITicks = (11 + memoryWait[(reg[0].I >> 24) & 0xF] + memoryWait[(reg[1].I >> 24) & 0xF]) * len; |
|
| 613 |
+ {
|
|
| 614 |
+ uint32_t len = CPUReadMemory(reg[0].I) >> 8; |
|
| 615 |
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000))) |
|
| 616 |
+ SWITicks = (11 + memoryWait[(reg[0].I >> 24) & 0xF] + memoryWait[(reg[1].I >> 24) & 0xF]) * len; |
|
| 617 |
+ } |
|
| 610 | 618 |
BIOS_RLUnCompWram(); |
| 611 | 619 |
break; |
| 612 |
- } |
|
| 613 | 620 |
case 0x15: |
| 614 |
- {
|
|
| 615 |
- uint32_t len = CPUReadMemory(reg[0].I) >> 9; |
|
| 616 |
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000))) |
|
| 617 |
- SWITicks = (34 + (memoryWait[(reg[0].I >> 24) & 0xF] << 1) + memoryWait[(reg[1].I >> 24) & 0xF]) * len; |
|
| 621 |
+ {
|
|
| 622 |
+ uint32_t len = CPUReadMemory(reg[0].I) >> 9; |
|
| 623 |
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000))) |
|
| 624 |
+ SWITicks = (34 + (memoryWait[(reg[0].I >> 24) & 0xF] << 1) + memoryWait[(reg[1].I >> 24) & 0xF]) * len; |
|
| 625 |
+ } |
|
| 618 | 626 |
BIOS_RLUnCompVram(); |
| 619 | 627 |
break; |
| 620 |
- } |
|
| 621 | 628 |
case 0x16: |
| 622 |
- {
|
|
| 623 |
- uint32_t len = CPUReadMemory(reg[0].I) >> 8; |
|
| 624 |
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000))) |
|
| 625 |
- SWITicks = (13 + memoryWait[(reg[0].I >> 24) & 0xF] + memoryWait[(reg[1].I >> 24) & 0xF]) * len; |
|
| 629 |
+ {
|
|
| 630 |
+ uint32_t len = CPUReadMemory(reg[0].I) >> 8; |
|
| 631 |
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000))) |
|
| 632 |
+ SWITicks = (13 + memoryWait[(reg[0].I >> 24) & 0xF] + memoryWait[(reg[1].I >> 24) & 0xF]) * len; |
|
| 633 |
+ } |
|
| 626 | 634 |
BIOS_Diff8bitUnFilterWram(); |
| 627 | 635 |
break; |
| 628 |
- } |
|
| 629 | 636 |
case 0x17: |
| 630 |
- {
|
|
| 631 |
- uint32_t len = CPUReadMemory(reg[0].I) >> 9; |
|
| 632 |
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000))) |
|
| 633 |
- SWITicks = (39 + (memoryWait[(reg[0].I >> 24) & 0xF] << 1) + memoryWait[(reg[1].I >> 24) & 0xF]) * len; |
|
| 637 |
+ {
|
|
| 638 |
+ uint32_t len = CPUReadMemory(reg[0].I) >> 9; |
|
| 639 |
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000))) |
|
| 640 |
+ SWITicks = (39 + (memoryWait[(reg[0].I >> 24) & 0xF] << 1) + memoryWait[(reg[1].I >> 24) & 0xF]) * len; |
|
| 641 |
+ } |
|
| 634 | 642 |
BIOS_Diff8bitUnFilterVram(); |
| 635 | 643 |
break; |
| 636 |
- } |
|
| 637 | 644 |
case 0x18: |
| 638 |
- {
|
|
| 639 |
- uint32_t len = CPUReadMemory(reg[0].I) >> 9; |
|
| 640 |
- if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000))) |
|
| 641 |
- SWITicks = (13 + memoryWait[(reg[0].I >> 24) & 0xF] + memoryWait[(reg[1].I >> 24) & 0xF]) * len; |
|
| 645 |
+ {
|
|
| 646 |
+ uint32_t len = CPUReadMemory(reg[0].I) >> 9; |
|
| 647 |
+ if (!(!(reg[0].I & 0xe000000) || !((reg[0].I + (len & 0x1fffff)) & 0xe000000))) |
|
| 648 |
+ SWITicks = (13 + memoryWait[(reg[0].I >> 24) & 0xF] + memoryWait[(reg[1].I >> 24) & 0xF]) * len; |
|
| 649 |
+ } |
|
| 642 | 650 |
BIOS_Diff16bitUnFilter(); |
| 643 | 651 |
break; |
| 644 |
- } |
|
| 645 | 652 |
case 0x19: |
| 646 | 653 |
if (reg[0].I) |
| 647 | 654 |
soundPause(); |
| ... | ... |
@@ -657,7 +664,7 @@ void CPUSoftwareInterrupt(int comment) |
| 657 | 664 |
} |
| 658 | 665 |
} |
| 659 | 666 |
|
| 660 |
-void CPUCompareVCOUNT() |
|
| 667 |
+static void CPUCompareVCOUNT() |
|
| 661 | 668 |
{
|
| 662 | 669 |
if (VCOUNT == (DISPSTAT >> 8)) |
| 663 | 670 |
{
|
| ... | ... |
@@ -683,7 +690,7 @@ void CPUCompareVCOUNT() |
| 683 | 690 |
} |
| 684 | 691 |
} |
| 685 | 692 |
|
| 686 |
-void doDMA(uint32_t &s, uint32_t &d, uint32_t si, uint32_t di, uint32_t c, int transfer32) |
|
| 693 |
+static void doDMA(uint32_t &s, uint32_t &d, uint32_t si, uint32_t di, uint32_t c, int transfer32) |
|
| 687 | 694 |
{
|
| 688 | 695 |
int sm = s >> 24; |
| 689 | 696 |
int dm = d >> 24; |
| ... | ... |
@@ -691,12 +698,16 @@ void doDMA(uint32_t &s, uint32_t &d, uint32_t si, uint32_t di, uint32_t c, int t |
| 691 | 698 |
int dw = 0; |
| 692 | 699 |
int sc = c; |
| 693 | 700 |
|
| 701 |
+ cpuDmaHack = true; |
|
| 694 | 702 |
// This is done to get the correct waitstates. |
| 695 | 703 |
if (sm > 15) |
| 696 | 704 |
sm = 15; |
| 697 | 705 |
if (dm > 15) |
| 698 | 706 |
dm = 15; |
| 699 | 707 |
|
| 708 |
+ //if ((sm>=0x05) && (sm<=0x07) || (dm>=0x05) && (dm <=0x07)) |
|
| 709 |
+ // blank = (((DISPSTAT | ((DISPSTAT>>1)&1))==1) ? true : false); |
|
| 710 |
+ |
|
| 700 | 711 |
if (transfer32) |
| 701 | 712 |
{
|
| 702 | 713 |
s &= 0xFFFFFFFC; |
| ... | ... |
@@ -765,185 +776,174 @@ void doDMA(uint32_t &s, uint32_t &d, uint32_t si, uint32_t di, uint32_t c, int t |
| 765 | 776 |
} |
| 766 | 777 |
|
| 767 | 778 |
cpuDmaTicksToUpdate += totalTicks; |
| 779 |
+ cpuDmaHack = false; |
|
| 768 | 780 |
} |
| 769 | 781 |
|
| 770 | 782 |
void CPUCheckDMA(int reason, int dmamask) |
| 771 | 783 |
{
|
| 772 | 784 |
// DMA 0 |
| 773 |
- if ((DM0CNT_H & 0x8000) && (dmamask & 1)) |
|
| 785 |
+ if ((DM0CNT_H & 0x8000) && (dmamask & 1) && ((DM0CNT_H >> 12) & 3) == reason) |
|
| 774 | 786 |
{
|
| 775 |
- if (((DM0CNT_H >> 12) & 3) == reason) |
|
| 787 |
+ uint32_t sourceIncrement = 4; |
|
| 788 |
+ uint32_t destIncrement = 4; |
|
| 789 |
+ switch ((DM0CNT_H >> 7) & 3) |
|
| 776 | 790 |
{
|
| 777 |
- uint32_t sourceIncrement = 4; |
|
| 778 |
- uint32_t destIncrement = 4; |
|
| 779 |
- switch ((DM0CNT_H >> 7) & 3) |
|
| 780 |
- {
|
|
| 781 |
- case 1: |
|
| 782 |
- sourceIncrement = static_cast<uint32_t>(-4); |
|
| 783 |
- break; |
|
| 784 |
- case 2: |
|
| 785 |
- sourceIncrement = 0; |
|
| 786 |
- } |
|
| 787 |
- switch ((DM0CNT_H >> 5) & 3) |
|
| 788 |
- {
|
|
| 789 |
- case 1: |
|
| 790 |
- destIncrement = static_cast<uint32_t>(-4); |
|
| 791 |
- break; |
|
| 792 |
- case 2: |
|
| 793 |
- destIncrement = 0; |
|
| 794 |
- } |
|
| 795 |
- doDMA(dma0Source, dma0Dest, sourceIncrement, destIncrement, DM0CNT_L ? DM0CNT_L : 0x4000, DM0CNT_H & 0x0400); |
|
| 791 |
+ case 1: |
|
| 792 |
+ sourceIncrement = static_cast<uint32_t>(-4); |
|
| 793 |
+ break; |
|
| 794 |
+ case 2: |
|
| 795 |
+ sourceIncrement = 0; |
|
| 796 |
+ } |
|
| 797 |
+ switch ((DM0CNT_H >> 5) & 3) |
|
| 798 |
+ {
|
|
| 799 |
+ case 1: |
|
| 800 |
+ destIncrement = static_cast<uint32_t>(-4); |
|
| 801 |
+ break; |
|
| 802 |
+ case 2: |
|
| 803 |
+ destIncrement = 0; |
|
| 804 |
+ } |
|
| 805 |
+ doDMA(dma0Source, dma0Dest, sourceIncrement, destIncrement, DM0CNT_L ? DM0CNT_L : 0x4000, DM0CNT_H & 0x0400); |
|
| 796 | 806 |
|
| 797 |
- if (DM0CNT_H & 0x4000) |
|
| 798 |
- {
|
|
| 799 |
- IF |= 0x0100; |
|
| 800 |
- UPDATE_REG(0x202, IF); |
|
| 801 |
- cpuNextEvent = cpuTotalTicks; |
|
| 802 |
- } |
|
| 807 |
+ if (DM0CNT_H & 0x4000) |
|
| 808 |
+ {
|
|
| 809 |
+ IF |= 0x0100; |
|
| 810 |
+ UPDATE_REG(0x202, IF); |
|
| 811 |
+ cpuNextEvent = cpuTotalTicks; |
|
| 812 |
+ } |
|
| 803 | 813 |
|
| 804 |
- if (((DM0CNT_H >> 5) & 3) == 3) |
|
| 805 |
- dma0Dest = DM0DAD_L | (DM0DAD_H << 16); |
|
| 814 |
+ if (((DM0CNT_H >> 5) & 3) == 3) |
|
| 815 |
+ dma0Dest = DM0DAD_L | (DM0DAD_H << 16); |
|
| 806 | 816 |
|
| 807 |
- if (!(DM0CNT_H & 0x0200) || !reason) |
|
| 808 |
- {
|
|
| 809 |
- DM0CNT_H &= 0x7FFF; |
|
| 810 |
- UPDATE_REG(0xBA, DM0CNT_H); |
|
| 811 |
- } |
|
| 817 |
+ if (!(DM0CNT_H & 0x0200) || !reason) |
|
| 818 |
+ {
|
|
| 819 |
+ DM0CNT_H &= 0x7FFF; |
|
| 820 |
+ UPDATE_REG(0xBA, DM0CNT_H); |
|
| 812 | 821 |
} |
| 813 | 822 |
} |
| 814 | 823 |
|
| 815 | 824 |
// DMA 1 |
| 816 |
- if ((DM1CNT_H & 0x8000) && (dmamask & 2)) |
|
| 825 |
+ if ((DM1CNT_H & 0x8000) && (dmamask & 2) && ((DM1CNT_H >> 12) & 3) == reason) |
|
| 817 | 826 |
{
|
| 818 |
- if (((DM1CNT_H >> 12) & 3) == reason) |
|
| 827 |
+ uint32_t sourceIncrement = 4; |
|
| 828 |
+ uint32_t destIncrement = 4; |
|
| 829 |
+ switch ((DM1CNT_H >> 7) & 3) |
|
| 819 | 830 |
{
|
| 820 |
- uint32_t sourceIncrement = 4; |
|
| 821 |
- uint32_t destIncrement = 4; |
|
| 822 |
- switch ((DM1CNT_H >> 7) & 3) |
|
| 823 |
- {
|
|
| 824 |
- case 1: |
|
| 825 |
- sourceIncrement = static_cast<uint32_t>(-4); |
|
| 826 |
- break; |
|
| 827 |
- case 2: |
|
| 828 |
- sourceIncrement = 0; |
|
| 829 |
- } |
|
| 830 |
- switch ((DM1CNT_H >> 5) & 3) |
|
| 831 |
- {
|
|
| 832 |
- case 1: |
|
| 833 |
- destIncrement = static_cast<uint32_t>(-4); |
|
| 834 |
- break; |
|
| 835 |
- case 2: |
|
| 836 |
- destIncrement = 0; |
|
| 837 |
- } |
|
| 838 |
- if (reason == 3) |
|
| 839 |
- doDMA(dma1Source, dma1Dest, sourceIncrement, 0, 4, 0x0400); |
|
| 840 |
- else |
|
| 841 |
- doDMA(dma1Source, dma1Dest, sourceIncrement, destIncrement, DM1CNT_L ? DM1CNT_L : 0x4000, DM1CNT_H & 0x0400); |
|
| 831 |
+ case 1: |
|
| 832 |
+ sourceIncrement = static_cast<uint32_t>(-4); |
|
| 833 |
+ break; |
|
| 834 |
+ case 2: |
|
| 835 |
+ sourceIncrement = 0; |
|
| 836 |
+ } |
|
| 837 |
+ switch ((DM1CNT_H >> 5) & 3) |
|
| 838 |
+ {
|
|
| 839 |
+ case 1: |
|
| 840 |
+ destIncrement = static_cast<uint32_t>(-4); |
|
| 841 |
+ break; |
|
| 842 |
+ case 2: |
|
| 843 |
+ destIncrement = 0; |
|
| 844 |
+ } |
|
| 845 |
+ if (reason == 3) |
|
| 846 |
+ doDMA(dma1Source, dma1Dest, sourceIncrement, 0, 4, 0x0400); |
|
| 847 |
+ else |
|
| 848 |
+ doDMA(dma1Source, dma1Dest, sourceIncrement, destIncrement, DM1CNT_L ? DM1CNT_L : 0x4000, DM1CNT_H & 0x0400); |
|
| 842 | 849 |
|
| 843 |
- if (DM1CNT_H & 0x4000) |
|
| 844 |
- {
|
|
| 845 |
- IF |= 0x0200; |
|
| 846 |
- UPDATE_REG(0x202, IF); |
|
| 847 |
- cpuNextEvent = cpuTotalTicks; |
|
| 848 |
- } |
|
| 850 |
+ if (DM1CNT_H & 0x4000) |
|
| 851 |
+ {
|
|
| 852 |
+ IF |= 0x0200; |
|
| 853 |
+ UPDATE_REG(0x202, IF); |
|
| 854 |
+ cpuNextEvent = cpuTotalTicks; |
|
| 855 |
+ } |
|
| 849 | 856 |
|
| 850 |
- if (((DM1CNT_H >> 5) & 3) == 3) |
|
| 851 |
- dma1Dest = DM1DAD_L | (DM1DAD_H << 16); |
|
| 857 |
+ if (((DM1CNT_H >> 5) & 3) == 3) |
|
| 858 |
+ dma1Dest = DM1DAD_L | (DM1DAD_H << 16); |
|
| 852 | 859 |
|
| 853 |
- if (!(DM1CNT_H & 0x0200) || !reason) |
|
| 854 |
- {
|
|
| 855 |
- DM1CNT_H &= 0x7FFF; |
|
| 856 |
- UPDATE_REG(0xC6, DM1CNT_H); |
|
| 857 |
- } |
|
| 860 |
+ if (!(DM1CNT_H & 0x0200) || !reason) |
|
| 861 |
+ {
|
|
| 862 |
+ DM1CNT_H &= 0x7FFF; |
|
| 863 |
+ UPDATE_REG(0xC6, DM1CNT_H); |
|
| 858 | 864 |
} |
| 859 | 865 |
} |
| 860 | 866 |
|
| 861 | 867 |
// DMA 2 |
| 862 |
- if ((DM2CNT_H & 0x8000) && (dmamask & 4)) |
|
| 868 |
+ if ((DM2CNT_H & 0x8000) && (dmamask & 4) && ((DM2CNT_H >> 12) & 3) == reason) |
|
| 863 | 869 |
{
|
| 864 |
- if (((DM2CNT_H >> 12) & 3) == reason) |
|
| 870 |
+ uint32_t sourceIncrement = 4; |
|
| 871 |
+ uint32_t destIncrement = 4; |
|
| 872 |
+ switch ((DM2CNT_H >> 7) & 3) |
|
| 865 | 873 |
{
|
| 866 |
- uint32_t sourceIncrement = 4; |
|
| 867 |
- uint32_t destIncrement = 4; |
|
| 868 |
- switch ((DM2CNT_H >> 7) & 3) |
|
| 869 |
- {
|
|
| 870 |
- case 1: |
|
| 871 |
- sourceIncrement = static_cast<uint32_t>(-4); |
|
| 872 |
- break; |
|
| 873 |
- case 2: |
|
| 874 |
- sourceIncrement = 0; |
|
| 875 |
- } |
|
| 876 |
- switch ((DM2CNT_H >> 5) & 3) |
|
| 877 |
- {
|
|
| 878 |
- case 1: |
|
| 879 |
- destIncrement = static_cast<uint32_t>(-4); |
|
| 880 |
- break; |
|
| 881 |
- case 2: |
|
| 882 |
- destIncrement = 0; |
|
| 883 |
- } |
|
| 884 |
- if (reason == 3) |
|
| 885 |
- doDMA(dma2Source, dma2Dest, sourceIncrement, 0, 4, 0x0400); |
|
| 886 |
- else |
|
| 887 |
- doDMA(dma2Source, dma2Dest, sourceIncrement, destIncrement, DM2CNT_L ? DM2CNT_L : 0x4000, DM2CNT_H & 0x0400); |
|
| 874 |
+ case 1: |
|
| 875 |
+ sourceIncrement = static_cast<uint32_t>(-4); |
|
| 876 |
+ break; |
|
| 877 |
+ case 2: |
|
| 878 |
+ sourceIncrement = 0; |
|
| 879 |
+ } |
|
| 880 |
+ switch ((DM2CNT_H >> 5) & 3) |
|
| 881 |
+ {
|
|
| 882 |
+ case 1: |
|
| 883 |
+ destIncrement = static_cast<uint32_t>(-4); |
|
| 884 |
+ break; |
|
| 885 |
+ case 2: |
|
| 886 |
+ destIncrement = 0; |
|
| 887 |
+ } |
|
| 888 |
+ if (reason == 3) |
|
| 889 |
+ doDMA(dma2Source, dma2Dest, sourceIncrement, 0, 4, 0x0400); |
|
| 890 |
+ else |
|
| 891 |
+ doDMA(dma2Source, dma2Dest, sourceIncrement, destIncrement, DM2CNT_L ? DM2CNT_L : 0x4000, DM2CNT_H & 0x0400); |
|
| 888 | 892 |
|
| 889 |
- if (DM2CNT_H & 0x4000) |
|
| 890 |
- {
|
|
| 891 |
- IF |= 0x0400; |
|
| 892 |
- UPDATE_REG(0x202, IF); |
|
| 893 |
- cpuNextEvent = cpuTotalTicks; |
|
| 894 |
- } |
|
| 893 |
+ if (DM2CNT_H & 0x4000) |
|
| 894 |
+ {
|
|
| 895 |
+ IF |= 0x0400; |
|
| 896 |
+ UPDATE_REG(0x202, IF); |
|
| 897 |
+ cpuNextEvent = cpuTotalTicks; |
|
| 898 |
+ } |
|
| 895 | 899 |
|
| 896 |
- if (((DM2CNT_H >> 5) & 3) == 3) |
|
| 897 |
- dma2Dest = DM2DAD_L | (DM2DAD_H << 16); |
|
| 900 |
+ if (((DM2CNT_H >> 5) & 3) == 3) |
|
| 901 |
+ dma2Dest = DM2DAD_L | (DM2DAD_H << 16); |
|
| 898 | 902 |
|
| 899 |
- if (!(DM2CNT_H & 0x0200) || !reason) |
|
| 900 |
- {
|
|
| 901 |
- DM2CNT_H &= 0x7FFF; |
|
| 902 |
- UPDATE_REG(0xD2, DM2CNT_H); |
|
| 903 |
- } |
|
| 903 |
+ if (!(DM2CNT_H & 0x0200) || !reason) |
|
| 904 |
+ {
|
|
| 905 |
+ DM2CNT_H &= 0x7FFF; |
|
| 906 |
+ UPDATE_REG(0xD2, DM2CNT_H); |
|
| 904 | 907 |
} |
| 905 | 908 |
} |
| 906 | 909 |
|
| 907 | 910 |
// DMA 3 |
| 908 |
- if ((DM3CNT_H & 0x8000) && (dmamask & 8)) |
|
| 911 |
+ if ((DM3CNT_H & 0x8000) && (dmamask & 8) && ((DM3CNT_H >> 12) & 3) == reason) |
|
| 909 | 912 |
{
|
| 910 |
- if (((DM3CNT_H >> 12) & 3) == reason) |
|
| 913 |
+ uint32_t sourceIncrement = 4; |
|
| 914 |
+ uint32_t destIncrement = 4; |
|
| 915 |
+ switch ((DM3CNT_H >> 7) & 3) |
|
| 911 | 916 |
{
|
| 912 |
- uint32_t sourceIncrement = 4; |
|
| 913 |
- uint32_t destIncrement = 4; |
|
| 914 |
- switch ((DM3CNT_H >> 7) & 3) |
|
| 915 |
- {
|
|
| 916 |
- case 1: |
|
| 917 |
- sourceIncrement = static_cast<uint32_t>(-4); |
|
| 918 |
- break; |
|
| 919 |
- case 2: |
|
| 920 |
- sourceIncrement = 0; |
|
| 921 |
- } |
|
| 922 |
- switch ((DM3CNT_H >> 5) & 3) |
|
| 923 |
- {
|
|
| 924 |
- case 1: |
|
| 925 |
- destIncrement = static_cast<uint32_t>(-4); |
|
| 926 |
- break; |
|
| 927 |
- case 2: |
|
| 928 |
- destIncrement = 0; |
|
| 929 |
- } |
|
| 930 |
- doDMA(dma3Source, dma3Dest, sourceIncrement, destIncrement, DM3CNT_L ? DM3CNT_L : 0x10000, DM3CNT_H & 0x0400); |
|
| 931 |
- |
|
| 932 |
- if (DM3CNT_H & 0x4000) |
|
| 933 |
- {
|
|
| 934 |
- IF |= 0x0800; |
|
| 935 |
- UPDATE_REG(0x202, IF); |
|
| 936 |
- cpuNextEvent = cpuTotalTicks; |
|
| 937 |
- } |
|
| 917 |
+ case 1: |
|
| 918 |
+ sourceIncrement = static_cast<uint32_t>(-4); |
|
| 919 |
+ break; |
|
| 920 |
+ case 2: |
|
| 921 |
+ sourceIncrement = 0; |
|
| 922 |
+ } |
|
| 923 |
+ switch ((DM3CNT_H >> 5) & 3) |
|
| 924 |
+ {
|
|
| 925 |
+ case 1: |
|
| 926 |
+ destIncrement = static_cast<uint32_t>(-4); |
|
| 927 |
+ break; |
|
| 928 |
+ case 2: |
|
| 929 |
+ destIncrement = 0; |
|
| 930 |
+ } |
|
| 931 |
+ doDMA(dma3Source, dma3Dest, sourceIncrement, destIncrement, DM3CNT_L ? DM3CNT_L : 0x10000, DM3CNT_H & 0x0400); |
|
| 938 | 932 |
|
| 939 |
- if (((DM3CNT_H >> 5) & 3) == 3) |
|
| 940 |
- dma3Dest = DM3DAD_L | (DM3DAD_H << 16); |
|
| 933 |
+ if (DM3CNT_H & 0x4000) |
|
| 934 |
+ {
|
|
| 935 |
+ IF |= 0x0800; |
|
| 936 |
+ UPDATE_REG(0x202, IF); |
|
| 937 |
+ cpuNextEvent = cpuTotalTicks; |
|
| 938 |
+ } |
|
| 941 | 939 |
|
| 942 |
- if (!(DM3CNT_H & 0x0200) || !reason) |
|
| 943 |
- {
|
|
| 944 |
- DM3CNT_H &= 0x7FFF; |
|
| 945 |
- UPDATE_REG(0xDE, DM3CNT_H); |
|
| 946 |
- } |
|
| 940 |
+ if (((DM3CNT_H >> 5) & 3) == 3) |
|
| 941 |
+ dma3Dest = DM3DAD_L | (DM3DAD_H << 16); |
|
| 942 |
+ |
|
| 943 |
+ if (!(DM3CNT_H & 0x0200) || !reason) |
|
| 944 |
+ {
|
|
| 945 |
+ DM3CNT_H &= 0x7FFF; |
|
| 946 |
+ UPDATE_REG(0xDE, DM3CNT_H); |
|
| 947 | 947 |
} |
| 948 | 948 |
} |
| 949 | 949 |
} |
| ... | ... |
@@ -953,41 +953,41 @@ void CPUUpdateRegister(uint32_t address, uint16_t value) |
| 953 | 953 |
switch (address) |
| 954 | 954 |
{
|
| 955 | 955 |
case 0x00: |
| 956 |
- {
|
|
| 957 |
- if ((value & 7) > 5) |
|
| 958 |
- // display modes above 0-5 are prohibited |
|
| 959 |
- DISPCNT = value & 7; |
|
| 960 |
- bool change = !!((DISPCNT ^ value) & 0x80); |
|
| 961 |
- uint16_t changeBGon = (~DISPCNT & value) & 0x0F00; // these layers are being activated |
|
| 956 |
+ {
|
|
| 957 |
+ if ((value & 7) > 5) |
|
| 958 |
+ // display modes above 0-5 are prohibited |
|
| 959 |
+ DISPCNT = value & 7; |
|
| 960 |
+ bool change = !!((DISPCNT ^ value) & 0x80); |
|
| 961 |
+ uint16_t changeBGon = (~DISPCNT & value) & 0x0F00; // these layers are being activated |
|
| 962 | 962 |
|
| 963 |
- DISPCNT = value & 0xFFF7; // bit 3 can only be accessed by the BIOS to enable GBC mode |
|
| 964 |
- UPDATE_REG(0x00, DISPCNT); |
|
| 963 |
+ DISPCNT = value & 0xFFF7; // bit 3 can only be accessed by the BIOS to enable GBC mode |
|
| 964 |
+ UPDATE_REG(0x00, DISPCNT); |
|
| 965 | 965 |
|
| 966 |
- if (changeBGon) |
|
| 967 |
- {
|
|
| 968 |
- layerEnableDelay = 4; |
|
| 969 |
- layerEnable = layerSettings & value & ~changeBGon; |
|
| 970 |
- } |
|
| 971 |
- else |
|
| 972 |
- {
|
|
| 973 |
- layerEnable = layerSettings & value; |
|
| 974 |
- //CPUUpdateTicks(); |
|
| 975 |
- } |
|
| 966 |
+ if (changeBGon) |
|
| 967 |
+ {
|
|
| 968 |
+ layerEnableDelay = 4; |
|
| 969 |
+ layerEnable = layerSettings & value & ~changeBGon; |
|
| 970 |
+ } |
|
| 971 |
+ else |
|
| 972 |
+ {
|
|
| 973 |
+ layerEnable = layerSettings & value; |
|
| 974 |
+ // CPUUpdateTicks(); |
|
| 975 |
+ } |
|
| 976 | 976 |
|
| 977 |
- if (change && !(value & 0x80)) |
|
| 978 |
- {
|
|
| 979 |
- if (!(DISPSTAT & 1)) |
|
| 977 |
+ if (change && !(value & 0x80)) |
|
| 980 | 978 |
{
|
| 981 |
- lcdTicks = 1008; |
|
| 982 |
- //VCOUNT = 0; |
|
| 983 |
- //UPDATE_REG(0x06, VCOUNT); |
|
| 984 |
- DISPSTAT &= 0xFFFC; |
|
| 985 |
- UPDATE_REG(0x04, DISPSTAT); |
|
| 986 |
- CPUCompareVCOUNT(); |
|
| 979 |
+ if (!(DISPSTAT & 1)) |
|
| 980 |
+ {
|
|
| 981 |
+ //lcdTicks = 1008; |
|
| 982 |
+ //VCOUNT = 0; |
|
| 983 |
+ //UPDATE_REG(0x06, VCOUNT); |
|
| 984 |
+ DISPSTAT &= 0xFFFC; |
|
| 985 |
+ UPDATE_REG(0x04, DISPSTAT); |
|
| 986 |
+ CPUCompareVCOUNT(); |
|
| 987 |
+ } |
|
| 987 | 988 |
} |
| 988 | 989 |
} |
| 989 | 990 |
break; |
| 990 |
- } |
|
| 991 | 991 |
case 0x04: |
| 992 | 992 |
DISPSTAT = (value & 0xFF38) | (DISPSTAT & 7); |
| 993 | 993 |
UPDATE_REG(0x04, DISPSTAT); |
| ... | ... |
@@ -1199,21 +1199,21 @@ void CPUUpdateRegister(uint32_t address, uint16_t value) |
| 1199 | 1199 |
UPDATE_REG(0xB8, 0); |
| 1200 | 1200 |
break; |
| 1201 | 1201 |
case 0xBA: |
| 1202 |
- {
|
|
| 1203 |
- bool start = !!((DM0CNT_H ^ value) & 0x8000); |
|
| 1204 |
- value &= 0xF7E0; |
|
| 1202 |
+ {
|
|
| 1203 |
+ bool start = !!((DM0CNT_H ^ value) & 0x8000); |
|
| 1204 |
+ value &= 0xF7E0; |
|
| 1205 | 1205 |
|
| 1206 |
- DM0CNT_H = value; |
|
| 1207 |
- UPDATE_REG(0xBA, DM0CNT_H); |
|
| 1206 |
+ DM0CNT_H = value; |
|
| 1207 |
+ UPDATE_REG(0xBA, DM0CNT_H); |
|
| 1208 | 1208 |
|
| 1209 |
- if (start && (value & 0x8000)) |
|
| 1210 |
- {
|
|
| 1211 |
- dma0Source = DM0SAD_L | (DM0SAD_H << 16); |
|
| 1212 |
- dma0Dest = DM0DAD_L | (DM0DAD_H << 16); |
|
| 1213 |
- CPUCheckDMA(0, 1); |
|
| 1209 |
+ if (start && (value & 0x8000)) |
|
| 1210 |
+ {
|
|
| 1211 |
+ dma0Source = DM0SAD_L | (DM0SAD_H << 16); |
|
| 1212 |
+ dma0Dest = DM0DAD_L | (DM0DAD_H << 16); |
|
| 1213 |
+ CPUCheckDMA(0, 1); |
|
| 1214 |
+ } |
|
| 1214 | 1215 |
} |
| 1215 | 1216 |
break; |
| 1216 |
- } |
|
| 1217 | 1217 |
case 0xBC: |
| 1218 | 1218 |
DM1SAD_L = value; |
| 1219 | 1219 |
UPDATE_REG(0xBC, DM1SAD_L); |
| ... | ... |
@@ -1235,21 +1235,21 @@ void CPUUpdateRegister(uint32_t address, uint16_t value) |
| 1235 | 1235 |
UPDATE_REG(0xC4, 0); |
| 1236 | 1236 |
break; |
| 1237 | 1237 |
case 0xC6: |
| 1238 |
- {
|
|
| 1239 |
- bool start = !!((DM1CNT_H ^ value) & 0x8000); |
|
| 1240 |
- value &= 0xF7E0; |
|
| 1238 |
+ {
|
|
| 1239 |
+ bool start = !!((DM1CNT_H ^ value) & 0x8000); |
|
| 1240 |
+ value &= 0xF7E0; |
|
| 1241 | 1241 |
|
| 1242 |
- DM1CNT_H = value; |
|
| 1243 |
- UPDATE_REG(0xC6, DM1CNT_H); |
|
| 1242 |
+ DM1CNT_H = value; |
|
| 1243 |
+ UPDATE_REG(0xC6, DM1CNT_H); |
|
| 1244 | 1244 |
|
| 1245 |
- if (start && (value & 0x8000)) |
|
| 1246 |
- {
|
|
| 1247 |
- dma1Source = DM1SAD_L | (DM1SAD_H << 16); |
|
| 1248 |
- dma1Dest = DM1DAD_L | (DM1DAD_H << 16); |
|
| 1249 |
- CPUCheckDMA(0, 2); |
|
| 1245 |
+ if (start && (value & 0x8000)) |
|
| 1246 |
+ {
|
|
| 1247 |
+ dma1Source = DM1SAD_L | (DM1SAD_H << 16); |
|
| 1248 |
+ dma1Dest = DM1DAD_L | (DM1DAD_H << 16); |
|
| 1249 |
+ CPUCheckDMA(0, 2); |
|
| 1250 |
+ } |
|
| 1250 | 1251 |
} |
| 1251 | 1252 |
break; |
| 1252 |
- } |
|
| 1253 | 1253 |
case 0xC8: |
| 1254 | 1254 |
DM2SAD_L = value; |
| 1255 | 1255 |
UPDATE_REG(0xC8, DM2SAD_L); |
| ... | ... |
@@ -1271,21 +1271,21 @@ void CPUUpdateRegister(uint32_t address, uint16_t value) |
| 1271 | 1271 |
UPDATE_REG(0xD0, 0); |
| 1272 | 1272 |
break; |
| 1273 | 1273 |
case 0xD2: |
| 1274 |
- {
|
|
| 1275 |
- bool start = !!((DM2CNT_H ^ value) & 0x8000); |
|
| 1276 |
- value &= 0xF7E0; |
|
| 1274 |
+ {
|
|
| 1275 |
+ bool start = !!((DM2CNT_H ^ value) & 0x8000); |
|
| 1276 |
+ value &= 0xF7E0; |
|
| 1277 | 1277 |
|
| 1278 |
- DM2CNT_H = value; |
|
| 1279 |
- UPDATE_REG(0xD2, DM2CNT_H); |
|
| 1278 |
+ DM2CNT_H = value; |
|
| 1279 |
+ UPDATE_REG(0xD2, DM2CNT_H); |
|
| 1280 | 1280 |
|
| 1281 |
- if (start && (value & 0x8000)) |
|
| 1282 |
- {
|
|
| 1283 |
- dma2Source = DM2SAD_L | (DM2SAD_H << 16); |
|
| 1284 |
- dma2Dest = DM2DAD_L | (DM2DAD_H << 16); |
|
| 1285 |
- CPUCheckDMA(0, 4); |
|
| 1281 |
+ if (start && (value & 0x8000)) |
|
| 1282 |
+ {
|
|
| 1283 |
+ dma2Source = DM2SAD_L | (DM2SAD_H << 16); |
|
| 1284 |
+ dma2Dest = DM2DAD_L | (DM2DAD_H << 16); |
|
| 1285 |
+ CPUCheckDMA(0, 4); |
|
| 1286 |
+ } |
|
| 1286 | 1287 |
} |
| 1287 | 1288 |
break; |
| 1288 |
- } |
|
| 1289 | 1289 |
case 0xD4: |
| 1290 | 1290 |
DM3SAD_L = value; |
| 1291 | 1291 |
UPDATE_REG(0xD4, DM3SAD_L); |
| ... | ... |
@@ -1307,21 +1307,21 @@ void CPUUpdateRegister(uint32_t address, uint16_t value) |
| 1307 | 1307 |
UPDATE_REG(0xDC, 0); |
| 1308 | 1308 |
break; |
| 1309 | 1309 |
case 0xDE: |
| 1310 |
- {
|
|
| 1311 |
- bool start = !!((DM3CNT_H ^ value) & 0x8000); |
|
| 1312 |
- value &= 0xFFE0; |
|
| 1310 |
+ {
|
|
| 1311 |
+ bool start = !!((DM3CNT_H ^ value) & 0x8000); |
|
| 1312 |
+ value &= 0xFFE0; |
|
| 1313 | 1313 |
|
| 1314 |
- DM3CNT_H = value; |
|
| 1315 |
- UPDATE_REG(0xDE, DM3CNT_H); |
|
| 1314 |
+ DM3CNT_H = value; |
|
| 1315 |
+ UPDATE_REG(0xDE, DM3CNT_H); |
|
| 1316 | 1316 |
|
| 1317 |
- if (start && (value & 0x8000)) |
|
| 1318 |
- {
|
|
| 1319 |
- dma3Source = DM3SAD_L | (DM3SAD_H << 16); |
|
| 1320 |
- dma3Dest = DM3DAD_L | (DM3DAD_H << 16); |
|
| 1321 |
- CPUCheckDMA(0, 8); |
|
| 1317 |
+ if (start && (value & 0x8000)) |
|
| 1318 |
+ {
|
|
| 1319 |
+ dma3Source = DM3SAD_L | (DM3SAD_H << 16); |
|
| 1320 |
+ dma3Dest = DM3DAD_L | (DM3DAD_H << 16); |
|
| 1321 |
+ CPUCheckDMA(0, 8); |
|
| 1322 |
+ } |
|
| 1322 | 1323 |
} |
| 1323 | 1324 |
break; |
| 1324 |
- } |
|
| 1325 | 1325 |
case 0x100: |
| 1326 | 1326 |
timer0Reload = value; |
| 1327 | 1327 |
break; |
| ... | ... |
@@ -1396,7 +1396,6 @@ void CPUUpdateRegister(uint32_t address, uint16_t value) |
| 1396 | 1396 |
busPrefetch = false; |
| 1397 | 1397 |
busPrefetchCount = 0; |
| 1398 | 1398 |
UPDATE_REG(0x204, value & 0x7FFF); |
| 1399 |
- |
|
| 1400 | 1399 |
break; |
| 1401 | 1400 |
case 0x208: |
| 1402 | 1401 |
IME = value & 1; |
| ... | ... |
@@ -1414,7 +1413,7 @@ void CPUUpdateRegister(uint32_t address, uint16_t value) |
| 1414 | 1413 |
} |
| 1415 | 1414 |
} |
| 1416 | 1415 |
|
| 1417 |
-void applyTimer() |
|
| 1416 |
+static void applyTimer() |
|
| 1418 | 1417 |
{
|
| 1419 | 1418 |
if (timerOnOffDelay & 1) |
| 1420 | 1419 |
{
|
| ... | ... |
@@ -1478,7 +1477,6 @@ void applyTimer() |
| 1478 | 1477 |
} |
| 1479 | 1478 |
|
| 1480 | 1479 |
uint8_t cpuBitsSet[256]; |
| 1481 |
-uint8_t cpuLowestBitSet[256]; |
|
| 1482 | 1480 |
|
| 1483 | 1481 |
void CPUInit() |
| 1484 | 1482 |
{
|
| ... | ... |
@@ -1491,7 +1489,7 @@ void CPUInit() |
| 1491 | 1489 |
} |
| 1492 | 1490 |
#endif |
| 1493 | 1491 |
|
| 1494 |
- memcpy(&bios[0], &myROM[0], sizeof(myROM)); |
|
| 1492 |
+ memcpy(&bios[0], myROM, sizeof(myROM)); |
|
| 1495 | 1493 |
|
| 1496 | 1494 |
biosProtected[0] = 0x00; |
| 1497 | 1495 |
biosProtected[1] = 0xf0; |
| ... | ... |
@@ -1501,16 +1499,10 @@ void CPUInit() |
| 1501 | 1499 |
for (int i = 0; i < 256; ++i) |
| 1502 | 1500 |
{
|
| 1503 | 1501 |
int count = 0; |
| 1504 |
- int j; |
|
| 1505 |
- for (j = 0; j < 8; ++j) |
|
| 1502 |
+ for (int j = 0; j < 8; ++j) |
|
| 1506 | 1503 |
if (i & (1 << j)) |
| 1507 | 1504 |
++count; |
| 1508 | 1505 |
cpuBitsSet[i] = count; |
| 1509 |
- |
|
| 1510 |
- for (j = 0; j < 8; ++j) |
|
| 1511 |
- if (i & (1 << j)) |
|
| 1512 |
- break; |
|
| 1513 |
- cpuLowestBitSet[i] = j; |
|
| 1514 | 1506 |
} |
| 1515 | 1507 |
|
| 1516 | 1508 |
std::fill(&ioReadable[0], &ioReadable[0x304], true); |
| ... | ... |
@@ -1658,7 +1650,6 @@ void CPUReset() |
| 1658 | 1650 |
|
| 1659 | 1651 |
// reset internal state |
| 1660 | 1652 |
holdState = false; |
| 1661 |
- holdType = 0; |
|
| 1662 | 1653 |
|
| 1663 | 1654 |
biosProtected[0] = 0x00; |
| 1664 | 1655 |
biosProtected[1] = 0xf0; |
| ... | ... |
@@ -1728,10 +1719,12 @@ void CPUReset() |
| 1728 | 1719 |
|
| 1729 | 1720 |
ARM_PREFETCH(); |
| 1730 | 1721 |
|
| 1722 |
+ cpuDmaHack = false; |
|
| 1723 |
+ |
|
| 1731 | 1724 |
SWITicks = 0; |
| 1732 | 1725 |
} |
| 1733 | 1726 |
|
| 1734 |
-void CPUInterrupt() |
|
| 1727 |
+static void CPUInterrupt() |
|
| 1735 | 1728 |
{
|
| 1736 | 1729 |
uint32_t PC = reg[15].I; |
| 1737 | 1730 |
bool savedState = armState; |
| ... | ... |
@@ -1747,7 +1740,7 @@ void CPUInterrupt() |
| 1747 | 1740 |
reg[15].I += 4; |
| 1748 | 1741 |
ARM_PREFETCH(); |
| 1749 | 1742 |
|
| 1750 |
- //if(!holdState) |
|
| 1743 |
+ //if (!holdState) |
|
| 1751 | 1744 |
biosProtected[0] = 0x02; |
| 1752 | 1745 |
biosProtected[1] = 0xc0; |
| 1753 | 1746 |
biosProtected[2] = 0x5e; |
| ... | ... |
@@ -1801,7 +1794,6 @@ void CPULoop(int ticks) |
| 1801 | 1794 |
cpuTotalTicks = 0; |
| 1802 | 1795 |
|
| 1803 | 1796 |
updateLoop: |
| 1804 |
- |
|
| 1805 | 1797 |
if (IRQTicks) |
| 1806 | 1798 |
{
|
| 1807 | 1799 |
IRQTicks -= clockTicks; |
| ... | ... |
@@ -1837,7 +1829,7 @@ void CPULoop(int ticks) |
| 1837 | 1829 |
} |
| 1838 | 1830 |
} |
| 1839 | 1831 |
|
| 1840 |
- if (VCOUNT >= 228) //Reaching last line |
|
| 1832 |
+ if (VCOUNT > 227) //Reaching last line |
|
| 1841 | 1833 |
{
|
| 1842 | 1834 |
DISPSTAT &= 0xFFFC; |
| 1843 | 1835 |
UPDATE_REG(0x04, DISPSTAT); |
| ... | ... |
@@ -1858,10 +1850,6 @@ void CPULoop(int ticks) |
| 1858 | 1850 |
DISPSTAT &= 0xFFFD; |
| 1859 | 1851 |
if (VCOUNT == 160) |
| 1860 | 1852 |
{
|
| 1861 |
- ++count; |
|
| 1862 |
- if (count == 60) |
|
| 1863 |
- count = 0; |
|
| 1864 |
- |
|
| 1865 | 1853 |
DISPSTAT |= 1; |
| 1866 | 1854 |
DISPSTAT &= 0xFFFD; |
| 1867 | 1855 |
UPDATE_REG(0x04, DISPSTAT); |
| ... | ... |
@@ -2070,7 +2058,6 @@ void CPULoop(int ticks) |
| 2070 | 2058 |
intState = false; |
| 2071 | 2059 |
holdState = false; |
| 2072 | 2060 |
stopState = false; |
| 2073 |
- holdType = 0; |
|
| 2074 | 2061 |
} |
| 2075 | 2062 |
} |
| 2076 | 2063 |
else |
| ... | ... |
@@ -2087,7 +2074,6 @@ void CPULoop(int ticks) |
| 2087 | 2074 |
CPUInterrupt(); |
| 2088 | 2075 |
holdState = false; |
| 2089 | 2076 |
stopState = false; |
| 2090 |
- holdType = 0; |
|
| 2091 | 2077 |
} |
| 2092 | 2078 |
} |
| 2093 | 2079 |
|
| ... | ... |
@@ -1,5 +1,4 @@ |
| 1 |
-#ifndef GBA_H |
|
| 2 |
-#define GBA_H |
|
| 1 |
+#pragma once |
|
| 3 | 2 |
|
| 4 | 3 |
#include <cstdint> |
| 5 | 4 |
|
| ... | ... |
@@ -42,9 +41,7 @@ union reg_pair |
| 42 | 41 |
#endif |
| 43 | 42 |
}; |
| 44 | 43 |
|
| 45 |
-#ifndef NO_GBA_MAP |
|
| 46 | 44 |
extern memoryMap map[256]; |
| 47 |
-#endif |
|
| 48 | 45 |
|
| 49 | 46 |
extern reg_pair reg[45]; |
| 50 | 47 |
extern uint8_t biosProtected[4]; |
| ... | ... |
@@ -57,36 +54,37 @@ extern bool armIrqEnable; |
| 57 | 54 |
extern bool armState; |
| 58 | 55 |
extern int armMode; |
| 59 | 56 |
|
| 60 |
-extern int CPULoadRom(); |
|
| 61 |
-extern void CPUUpdateRegister(uint32_t, uint16_t); |
|
| 62 |
-extern void CPUInit(); |
|
| 63 |
-extern void CPUReset(); |
|
| 64 |
-extern void CPULoop(int); |
|
| 65 |
-extern void CPUCheckDMA(int, int); |
|
| 57 |
+int CPULoadRom(); |
|
| 58 |
+void CPUUpdateRegister(uint32_t, uint16_t); |
|
| 59 |
+void CPUInit(); |
|
| 60 |
+void CPUReset(); |
|
| 61 |
+void CPULoop(int); |
|
| 62 |
+void CPUCheckDMA(int, int); |
|
| 66 | 63 |
|
| 67 |
-const uint32_t R13_IRQ = 18; |
|
| 68 |
-const uint32_t R14_IRQ = 19; |
|
| 69 |
-const uint32_t SPSR_IRQ = 20; |
|
| 70 |
-const uint32_t R13_USR = 26; |
|
| 71 |
-const uint32_t R14_USR = 27; |
|
| 72 |
-const uint32_t R13_SVC = 28; |
|
| 73 |
-const uint32_t R14_SVC = 29; |
|
| 74 |
-const uint32_t SPSR_SVC = 30; |
|
| 75 |
-const uint32_t R13_ABT = 31; |
|
| 76 |
-const uint32_t R14_ABT = 32; |
|
| 77 |
-const uint32_t SPSR_ABT = 33; |
|
| 78 |
-const uint32_t R13_UND = 34; |
|
| 79 |
-const uint32_t R14_UND = 35; |
|
| 80 |
-const uint32_t SPSR_UND = 36; |
|
| 81 |
-const uint32_t R8_FIQ = 37; |
|
| 82 |
-const uint32_t R9_FIQ = 38; |
|
| 83 |
-const uint32_t R10_FIQ = 39; |
|
| 84 |
-const uint32_t R11_FIQ = 40; |
|
| 85 |
-const uint32_t R12_FIQ = 41; |
|
| 86 |
-const uint32_t R13_FIQ = 42; |
|
| 87 |
-const uint32_t R14_FIQ = 43; |
|
| 88 |
-const uint32_t SPSR_FIQ = 44; |
|
| 64 |
+enum |
|
| 65 |
+{
|
|
| 66 |
+ R13_IRQ = 18, |
|
| 67 |
+ R14_IRQ, |
|
| 68 |
+ SPSR_IRQ, |
|
| 69 |
+ R13_USR = 26, |
|
| 70 |
+ R14_USR, |
|
| 71 |
+ R13_SVC, |
|
| 72 |
+ R14_SVC, |
|
| 73 |
+ SPSR_SVC, |
|
| 74 |
+ R13_ABT, |
|
| 75 |
+ R14_ABT, |
|
| 76 |
+ SPSR_ABT, |
|
| 77 |
+ R13_UND, |
|
| 78 |
+ R14_UND, |
|
| 79 |
+ SPSR_UND, |
|
| 80 |
+ R8_FIQ, |
|
| 81 |
+ R9_FIQ, |
|
| 82 |
+ R10_FIQ, |
|
| 83 |
+ R11_FIQ, |
|
| 84 |
+ R12_FIQ, |
|
| 85 |
+ R13_FIQ, |
|
| 86 |
+ R14_FIQ, |
|
| 87 |
+ SPSR_FIQ |
|
| 88 |
+}; |
|
| 89 | 89 |
|
| 90 | 90 |
#include "Globals.h" |
| 91 |
- |
|
| 92 |
-#endif // GBA_H |
| ... | ... |
@@ -1,10 +1,9 @@ |
| 1 |
-#ifndef GBACPU_H |
|
| 2 |
-#define GBACPU_H |
|
| 1 |
+#pragma once |
|
| 3 | 2 |
|
| 4 | 3 |
#include "GBAinline.h" |
| 5 | 4 |
|
| 6 |
-extern int armExecute(); |
|
| 7 |
-extern int thumbExecute(); |
|
| 5 |
+int armExecute(); |
|
| 6 |
+int thumbExecute(); |
|
| 8 | 7 |
|
| 9 | 8 |
#ifdef __GNUC__ |
| 10 | 9 |
# ifndef __APPLE__ |
| ... | ... |
@@ -12,8 +11,8 @@ extern int thumbExecute(); |
| 12 | 11 |
# else |
| 13 | 12 |
# define INSN_REGPARM /*nothing*/ |
| 14 | 13 |
# endif |
| 15 |
-# define LIKELY(x) __builtin_expect(!!(x),1) |
|
| 16 |
-# define UNLIKELY(x) __builtin_expect(!!(x),0) |
|
| 14 |
+# define LIKELY(x) __builtin_expect(!!(x), 1) |
|
| 15 |
+# define UNLIKELY(x) __builtin_expect(!!(x), 0) |
|
| 17 | 16 |
#else |
| 18 | 17 |
# define INSN_REGPARM /*nothing*/ |
| 19 | 18 |
# define LIKELY(x) (x) |
| ... | ... |
@@ -49,11 +48,12 @@ extern uint8_t memoryWait32[16]; |
| 49 | 48 |
extern uint8_t memoryWaitSeq[16]; |
| 50 | 49 |
extern uint8_t memoryWaitSeq32[16]; |
| 51 | 50 |
extern uint8_t cpuBitsSet[256]; |
| 52 |
-extern void CPUSwitchMode(int mode, bool saveState, bool breakLoop = true); |
|
| 53 |
-extern void CPUUpdateCPSR(); |
|
| 54 |
-extern void CPUUpdateFlags(bool breakLoop = true); |
|
| 55 |
-extern void CPUUndefinedException(); |
|
| 56 |
-extern void CPUSoftwareInterrupt(int comment); |
|
| 51 |
+ |
|
| 52 |
+void CPUSwitchMode(int mode, bool saveState, bool breakLoop = true); |
|
| 53 |
+void CPUUpdateCPSR(); |
|
| 54 |
+void CPUUpdateFlags(bool breakLoop = true); |
|
| 55 |
+void CPUUndefinedException(); |
|
| 56 |
+void CPUSoftwareInterrupt(int comment); |
|
| 57 | 57 |
|
| 58 | 58 |
// Waitstates when accessing data |
| 59 | 59 |
inline int dataTicksAccess16(uint32_t address) // DATA 8/16bits NON SEQ |
| ... | ... |
@@ -98,27 +98,6 @@ inline int dataTicksAccess32(uint32_t address) // DATA 32bits NON SEQ |
| 98 | 98 |
return value; |
| 99 | 99 |
} |
| 100 | 100 |
|
| 101 |
-inline int dataTicksAccessSeq16(uint32_t address) // DATA 8/16bits SEQ |
|
| 102 |
-{
|
|
| 103 |
- int addr = (address >> 24) & 15; |
|
| 104 |
- int value = memoryWaitSeq[addr]; |
|
| 105 |
- |
|
| 106 |
- if (addr >= 0x08 || addr < 0x02) |
|
| 107 |
- {
|
|
| 108 |
- busPrefetchCount = 0; |
|
| 109 |
- busPrefetch = false; |
|
| 110 |
- } |
|
| 111 |
- else if (busPrefetch) |
|
| 112 |
- {
|
|
| 113 |
- int waitState = value; |
|
| 114 |
- if (!waitState) |
|
| 115 |
- waitState = 1; |
|
| 116 |
- busPrefetchCount = ((busPrefetchCount + 1) << waitState) - 1; |
|
| 117 |
- } |
|
| 118 |
- |
|
| 119 |
- return value; |
|
| 120 |
-} |
|
| 121 |
- |
|
| 122 | 101 |
inline int dataTicksAccessSeq32(uint32_t address) // DATA 32bits SEQ |
| 123 | 102 |
{
|
| 124 | 103 |
int addr = (address >> 24) & 15; |
| ... | ... |
@@ -252,5 +231,3 @@ inline int codeTicksAccessSeq32(uint32_t address) // ARM SEQ |
| 252 | 231 |
else |
| 253 | 232 |
return memoryWaitSeq32[addr]; |
| 254 | 233 |
} |
| 255 |
- |
|
| 256 |
-#endif // GBACPU_H |
| ... | ... |
@@ -1,5 +1,4 @@ |
| 1 |
-#ifndef GBAINLINE_H |
|
| 2 |
-#define GBAINLINE_H |
|
| 1 |
+#pragma once |
|
| 3 | 2 |
|
| 4 | 3 |
#include "../common/Port.h" |
| 5 | 4 |
#include "Sound.h" |
| ... | ... |
@@ -8,8 +7,9 @@ extern const uint32_t objTilesAddress[3]; |
| 8 | 7 |
|
| 9 | 8 |
extern bool stopState; |
| 10 | 9 |
extern bool holdState; |
| 11 |
-extern int holdType; |
|
| 12 | 10 |
extern int cpuNextEvent; |
| 11 |
+extern bool cpuDmaHack; |
|
| 12 |
+extern uint32_t cpuDmaLast; |
|
| 13 | 13 |
extern bool timer0On; |
| 14 | 14 |
extern int timer0Ticks; |
| 15 | 15 |
extern int timer0ClockReload; |
| ... | ... |
@@ -24,6 +24,8 @@ extern int timer3Ticks; |
| 24 | 24 |
extern int timer3ClockReload; |
| 25 | 25 |
extern int cpuTotalTicks; |
| 26 | 26 |
|
| 27 |
+inline uint8_t CPUReadByteQuick(uint32_t addr) { return map[addr >> 24].address[addr & map[addr >> 24].mask]; }
|
|
| 28 |
+ |
|
| 27 | 29 |
inline uint16_t CPUReadHalfWordQuick(uint32_t addr) { return READ16LE(&map[addr >> 24].address[addr & map[addr >> 24].mask]); }
|
| 28 | 30 |
|
| 29 | 31 |
inline uint32_t CPUReadMemoryQuick(uint32_t addr) { return READ32LE(&map[addr >> 24].address[addr & map[addr >> 24].mask]); }
|
| ... | ... |
@@ -42,7 +44,7 @@ inline uint32_t CPUReadMemory(uint32_t address) |
| 42 | 44 |
if (reg[15].I >> 24) |
| 43 | 45 |
{
|
| 44 | 46 |
if (address < 0x4000) |
| 45 |
- value = READ32LE(&biosProtected); |
|
| 47 |
+ value = READ32LE(&biosProtected[0]); |
|
| 46 | 48 |
else |
| 47 | 49 |
goto unreadable; |
| 48 | 50 |
} |
| ... | ... |
@@ -92,45 +94,32 @@ inline uint32_t CPUReadMemory(uint32_t address) |
| 92 | 94 |
break; |
| 93 | 95 |
case 13: |
| 94 | 96 |
case 14: |
| 95 |
- return 0; |
|
| 97 |
+ case 15: |
|
| 98 |
+ value = 0; |
|
| 99 |
+ break; |
|
| 96 | 100 |
// default |
| 97 | 101 |
default: |
| 98 | 102 |
unreadable: |
| 99 |
- if (armState) |
|
| 100 |
- return CPUReadMemoryQuick(reg[15].I); |
|
| 103 |
+ if (cpuDmaHack) |
|
| 104 |
+ value = cpuDmaLast; |
|
| 101 | 105 |
else |
| 102 |
- return CPUReadHalfWordQuick(reg[15].I) | (CPUReadHalfWordQuick(reg[15].I) << 16); |
|
| 106 |
+ {
|
|
| 107 |
+ if (armState) |
|
| 108 |
+ return CPUReadMemoryQuick(reg[15].I); |
|
| 109 |
+ else |
|
| 110 |
+ return CPUReadHalfWordQuick(reg[15].I) | CPUReadHalfWordQuick(reg[15].I) << 16; |
|
| 111 |
+ } |
|
| 103 | 112 |
} |
| 104 | 113 |
|
| 105 | 114 |
if (oldAddress & 3) |
| 106 | 115 |
{
|
| 107 |
-#ifdef C_CORE |
|
| 108 | 116 |
int shift = (oldAddress & 3) << 3; |
| 109 | 117 |
value = (value >> shift) | (value << (32 - shift)); |
| 110 |
-#else |
|
| 111 |
-# ifdef __GNUC__ |
|
| 112 |
- asm("and $3, %%ecx;"
|
|
| 113 |
- "shl $3 ,%%ecx;" |
|
| 114 |
- "ror %%cl, %0" |
|
| 115 |
- : "=r" (value) |
|
| 116 |
- : "r" (value), "c" (oldAddress)); |
|
| 117 |
-# else |
|
| 118 |
- __asm |
|
| 119 |
- {
|
|
| 120 |
- mov ecx, oldAddress; |
|
| 121 |
- and ecx, 3; |
|
| 122 |
- shl ecx, 3; |
|
| 123 |
- ror [dword ptr value], cl; |
|
| 124 |
- } |
|
| 125 |
-# endif |
|
| 126 |
-#endif |
|
| 127 | 118 |
} |
| 128 | 119 |
|
| 129 | 120 |
return value; |
| 130 | 121 |
} |
| 131 | 122 |
|
| 132 |
-extern uint32_t myROM[]; |
|
| 133 |
- |
|
| 134 | 123 |
inline uint32_t CPUReadHalfWord(uint32_t address) |
| 135 | 124 |
{
|
| 136 | 125 |
uint32_t value; |
| ... | ... |
@@ -174,6 +163,8 @@ inline uint32_t CPUReadHalfWord(uint32_t address) |
| 174 | 163 |
value = 0xFFFF - ((timer3Ticks - cpuTotalTicks) >> timer3ClockReload); |
| 175 | 164 |
} |
| 176 | 165 |
} |
| 166 |
+ else if (address < 0x4000400 && ioReadable[address & 0x3fc]) |
|
| 167 |
+ value = 0; |
|
| 177 | 168 |
else |
| 178 | 169 |
goto unreadable; |
| 179 | 170 |
break; |
| ... | ... |
@@ -204,12 +195,24 @@ inline uint32_t CPUReadHalfWord(uint32_t address) |
| 204 | 195 |
else |
| 205 | 196 |
value = READ16LE(&rom[address & 0x1FFFFFE]); |
| 206 | 197 |
break; |
| 198 |
+ case 13: |
|
| 199 |
+ case 14: |
|
| 200 |
+ case 15: |
|
| 201 |
+ value = 0; |
|
| 202 |
+ break; |
|
| 203 |
+ // default |
|
| 207 | 204 |
default: |
| 208 | 205 |
unreadable: |
| 209 |
- if (armState) |
|
| 210 |
- return CPUReadMemoryQuick(reg[15].I); |
|
| 206 |
+ if (cpuDmaHack) |
|
| 207 |
+ value = cpuDmaLast & 0xFFFF; |
|
| 211 | 208 |
else |
| 212 |
- return CPUReadHalfWordQuick(reg[15].I) | (CPUReadHalfWordQuick(reg[15].I) << 16); |
|
| 209 |
+ {
|
|
| 210 |
+ if (armState) |
|
| 211 |
+ value = CPUReadHalfWordQuick(reg[15].I + (address & 2)); |
|
| 212 |
+ else |
|
| 213 |
+ value = CPUReadHalfWordQuick(reg[15].I); |
|
| 214 |
+ } |
|
| 215 |
+ return value; |
|
| 213 | 216 |
} |
| 214 | 217 |
|
| 215 | 218 |
if (oldAddress & 1) |
| ... | ... |
@@ -220,13 +223,7 @@ inline uint32_t CPUReadHalfWord(uint32_t address) |
| 220 | 223 |
|
| 221 | 224 |
inline int16_t CPUReadHalfWordSigned(uint32_t address) |
| 222 | 225 |
{
|
| 223 |
- uint32_t oldAddress = address; |
|
| 224 |
- if (address & 1) |
|
| 225 |
- address &= ~0x01; |
|
| 226 |
- int16_t value = static_cast<int16_t>(CPUReadHalfWord(address)); |
|
| 227 |
- if (oldAddress & 1) |
|
| 228 |
- value = static_cast<int8_t>(value); |
|
| 229 |
- return value; |
|
| 226 |
+ return static_cast<int16_t>(CPUReadHalfWord(address)); |
|
| 230 | 227 |
} |
| 231 | 228 |
|
| 232 | 229 |
inline uint8_t CPUReadByte(uint32_t address) |
| ... | ... |
@@ -239,7 +236,7 @@ inline uint8_t CPUReadByte(uint32_t address) |
| 239 | 236 |
if (address < 0x4000) |
| 240 | 237 |
return biosProtected[address & 3]; |
| 241 | 238 |
else |
| 242 |
- goto unreadable; |
|
| 239 |
+ break; |
|
| 243 | 240 |
} |
| 244 | 241 |
return bios[address & 0x3FFF]; |
| 245 | 242 |
case 2: |
| ... | ... |
@@ -250,7 +247,7 @@ inline uint8_t CPUReadByte(uint32_t address) |
| 250 | 247 |
if (address < 0x4000400 && ioReadable[address & 0x3ff]) |
| 251 | 248 |
return ioMem[address & 0x3ff]; |
| 252 | 249 |
else |
| 253 |
- goto unreadable; |
|
| 250 |
+ break; |
|
| 254 | 251 |
case 5: |
| 255 | 252 |
return paletteRAM[address & 0x3ff]; |
| 256 | 253 |
case 6: |
| ... | ... |
@@ -268,12 +265,19 @@ inline uint8_t CPUReadByte(uint32_t address) |
| 268 | 265 |
case 11: |
| 269 | 266 |
case 12: |
| 270 | 267 |
return rom[address & 0x1FFFFFF]; |
| 271 |
- default: |
|
| 272 |
- unreadable: |
|
| 273 |
- if (armState) |
|
| 274 |
- return CPUReadMemoryQuick(reg[15].I); |
|
| 275 |
- else |
|
| 276 |
- return CPUReadHalfWordQuick(reg[15].I) | (CPUReadHalfWordQuick(reg[15].I) << 16); |
|
| 268 |
+ case 13: |
|
| 269 |
+ case 14: |
|
| 270 |
+ case 15: |
|
| 271 |
+ return 0; |
|
| 272 |
+ } |
|
| 273 |
+ if (cpuDmaHack) |
|
| 274 |
+ return cpuDmaLast & 0xFF; |
|
| 275 |
+ else |
|
| 276 |
+ {
|
|
| 277 |
+ if (armState) |
|
| 278 |
+ return CPUReadByteQuick(reg[15].I + (address & 3)); |
|
| 279 |
+ else |
|
| 280 |
+ return CPUReadByteQuick(reg[15].I + (address & 1)); |
|
| 277 | 281 |
} |
| 278 | 282 |
} |
| 279 | 283 |
|
| ... | ... |
@@ -305,6 +309,7 @@ inline void CPUWriteMemory(uint32_t address, uint32_t value) |
| 305 | 309 |
return; |
| 306 | 310 |
if ((address & 0x18000) == 0x18000) |
| 307 | 311 |
address &= 0x17fff; |
| 312 |
+ |
|
| 308 | 313 |
WRITE32LE(&vram[address], value); |
| 309 | 314 |
break; |
| 310 | 315 |
case 0x07: |
| ... | ... |
@@ -405,7 +410,6 @@ inline void CPUWriteByte(uint32_t address, uint8_t b) |
| 405 | 410 |
if (b == 0x80) |
| 406 | 411 |
stopState = true; |
| 407 | 412 |
holdState = true; |
| 408 |
- holdType = -1; |
|
| 409 | 413 |
cpuNextEvent = cpuTotalTicks; |
| 410 | 414 |
break; |
| 411 | 415 |
default: // every other register |
| ... | ... |
@@ -415,7 +419,6 @@ inline void CPUWriteByte(uint32_t address, uint8_t b) |
| 415 | 419 |
else |
| 416 | 420 |
CPUUpdateRegister(lowerBits, (READ16LE(&ioMem[lowerBits]) & 0xFF00) | b); |
| 417 | 421 |
} |
| 418 |
- break; |
|
| 419 | 422 |
} |
| 420 | 423 |
break; |
| 421 | 424 |
case 5: |
| ... | ... |
@@ -441,5 +444,3 @@ inline void CPUWriteByte(uint32_t address, uint8_t b) |
| 441 | 444 |
break; |
| 442 | 445 |
} |
| 443 | 446 |
} |
| 444 |
- |
|
| 445 |
-#endif // GBAINLINE_H |
| ... | ... |
@@ -8,7 +8,6 @@ |
| 8 | 8 |
#include "../common/SoundDriver.h" |
| 9 | 9 |
|
| 10 | 10 |
extern SoundDriver *systemSoundInit(); |
| 11 |
-bool soundDeclicking = true; |
|
| 12 | 11 |
|
| 13 | 12 |
static const uint32_t NR52 = 0x84; |
| 14 | 13 |
|
| ... | ... |
@@ -20,12 +19,12 @@ static uint16_t soundFinalWave[6400]; |
| 20 | 19 |
static long soundSampleRate = 44100; |
| 21 | 20 |
bool soundInterpolation = true; |
| 22 | 21 |
static bool soundPaused = true; |
| 23 |
-static float soundFiltering = 0.5f; // 0.0 = none, 1.0 = max |
|
| 22 |
+static float soundFiltering = 1.0f; |
|
| 24 | 23 |
int SOUND_CLOCK_TICKS = SOUND_CLOCK_TICKS_; |
| 25 | 24 |
int soundTicks = SOUND_CLOCK_TICKS_; |
| 26 | 25 |
|
| 27 | 26 |
static float soundVolume = 1.0f; |
| 28 |
-static int soundEnableFlag = 0x30f; // emulator channels enabled |
|
| 27 |
+static int soundEnableFlag = 0x3ff; // emulator channels enabled |
|
| 29 | 28 |
static float soundFiltering_ = -1; |
| 30 | 29 |
static float soundVolume_ = -1; |
| 31 | 30 |
|
| ... | ... |
@@ -85,11 +84,11 @@ inline void Gba_Pcm::init() |
| 85 | 84 |
|
| 86 | 85 |
void Gba_Pcm::apply_control(int idx) |
| 87 | 86 |
{
|
| 88 |
- this->shift = (~ioMem[SGCNT0_H] >> (2 + idx)) & 1; |
|
| 87 |
+ this->shift = ~ioMem[SGCNT0_H] >> (2 + idx) & 1; |
|
| 89 | 88 |
|
| 90 | 89 |
int ch = 0; |
| 91 |
- if (((soundEnableFlag >> idx) & 0x100) && (ioMem[NR52] & 0x80)) |
|
| 92 |
- ch = (ioMem[SGCNT0_H + 1] >> (idx * 4)) & 3; |
|
| 90 |
+ if ((soundEnableFlag >> idx & 0x100) && (ioMem[NR52] & 0x80)) |
|
| 91 |
+ ch = ioMem[SGCNT0_H + 1] >> (idx * 4) & 3; |
|
| 93 | 92 |
|
| 94 | 93 |
Blip_Buffer *out = nullptr; |
| 95 | 94 |
switch (ch) |
| ... | ... |
@@ -108,7 +107,7 @@ void Gba_Pcm::apply_control(int idx) |
| 108 | 107 |
{
|
| 109 | 108 |
if (this->output) |
| 110 | 109 |
{
|
| 111 |
- blip_time_t time = blip_time(); |
|
| 110 |
+ auto time = blip_time(); |
|
| 112 | 111 |
|
| 113 | 112 |
this->output->set_modified(); |
| 114 | 113 |
|
| ... | ... |
@@ -147,7 +146,7 @@ void Gba_Pcm::update(int dac) |
| 147 | 146 |
{
|
| 148 | 147 |
if (this->output) |
| 149 | 148 |
{
|
| 150 |
- blip_time_t time = blip_time(); |
|
| 149 |
+ auto time = blip_time(); |
|
| 151 | 150 |
|
| 152 | 151 |
dac = static_cast<int8_t>(dac) >> this->shift; |
| 153 | 152 |
int delta = dac - this->last_amp; |
| ... | ... |
@@ -179,15 +178,19 @@ void Gba_Pcm_Fifo::timer_overflowed(int which_timer) |
| 179 | 178 |
{
|
| 180 | 179 |
if (which_timer == this->timer && this->enabled) |
| 181 | 180 |
{
|
| 182 |
- if (this->count <= 16) |
|
| 181 |
+ /* Mother 3 fix, refined to not break Metroid Fusion */ |
|
| 182 |
+ if (this->count == 16 || !this->count) |
|
| 183 | 183 |
{
|
| 184 | 184 |
// Need to fill FIFO |
| 185 |
+ int saved_count = this->count; |
|
| 185 | 186 |
CPUCheckDMA(3, this->which ? 4 : 2); |
| 186 |
- if (this->count <= 16) |
|
| 187 |
+ if (!saved_count && this->count == 16) |
|
| 188 |
+ CPUCheckDMA(3, this->which ? 4 : 2); |
|
| 189 |
+ if (!this->count) |
|
| 187 | 190 |
{
|
| 188 | 191 |
// Not filled by DMA, so fill with 16 bytes of silence |
| 189 | 192 |
int reg = this->which ? FIFOB_L : FIFOA_L; |
| 190 |
- for (int n = 4; n--; ) |
|
| 193 |
+ for (int n = 8; n--; ) |
|
| 191 | 194 |
{
|
| 192 | 195 |
soundEvent(reg, static_cast<uint16_t>(0)); |
| 193 | 196 |
soundEvent(reg + 2, static_cast<uint16_t>(0)); |
| ... | ... |
@@ -412,7 +415,7 @@ static void apply_muting() |
| 412 | 415 |
if (gb_apu) |
| 413 | 416 |
// APU |
| 414 | 417 |
for (int i = 0; i < 4; ++i) |
| 415 |
- if ((soundEnableFlag >> i) & 1) |
|
| 418 |
+ if (soundEnableFlag >> i & 1) |
|
| 416 | 419 |
gb_apu->set_output(stereo_buffer->center(), stereo_buffer->left(), stereo_buffer->right(), i); |
| 417 | 420 |
else |
| 418 | 421 |
gb_apu->set_output(nullptr, nullptr, nullptr, i); |
| ... | ... |
@@ -420,7 +423,7 @@ static void apply_muting() |
| 420 | 423 |
|
| 421 | 424 |
static void reset_apu() |
| 422 | 425 |
{
|
| 423 |
- gb_apu->reduce_clicks(soundDeclicking); |
|
| 426 |
+ gb_apu->reduce_clicks(true); |
|
| 424 | 427 |
gb_apu->reset(gb_apu->mode_agb, true); |
| 425 | 428 |
|
| 426 | 429 |
if (stereo_buffer) |
| ... | ... |
@@ -1,5 +1,4 @@ |
| 1 |
-#ifndef SOUND_H |
|
| 2 |
-#define SOUND_H |
|
| 1 |
+#pragma once |
|
| 3 | 2 |
|
| 4 | 3 |
// Sound emulation setup/options and GBA sound emulation |
| 5 | 4 |
|
| ... | ... |
@@ -37,11 +36,14 @@ extern bool soundInterpolation; // 1 if PCM should have low-pass filtering |
| 37 | 36 |
//// GBA sound emulation |
| 38 | 37 |
|
| 39 | 38 |
// GBA sound registers |
| 40 |
-const uint32_t SGCNT0_H = 0x82; |
|
| 41 |
-const uint32_t FIFOA_L = 0xa0; |
|
| 42 |
-const uint32_t FIFOA_H = 0xa2; |
|
| 43 |
-const uint32_t FIFOB_L = 0xa4; |
|
| 44 |
-const uint32_t FIFOB_H = 0xa6; |
|
| 39 |
+enum |
|
| 40 |
+{
|
|
| 41 |
+ SGCNT0_H = 0x82, |
|
| 42 |
+ FIFOA_L = 0xa0, |
|
| 43 |
+ FIFOA_H = 0xa2, |
|
| 44 |
+ FIFOB_L = 0xa4, |
|
| 45 |
+ FIFOB_H = 0xa6 |
|
| 46 |
+}; |
|
| 45 | 47 |
|
| 46 | 48 |
// Resets emulated sound hardware |
| 47 | 49 |
void soundReset(); |
| ... | ... |
@@ -61,5 +63,3 @@ extern int soundTicks; // Number of 16.8 MHz clocks until soundTick() will be ca |
| 61 | 63 |
class Multi_Buffer; |
| 62 | 64 |
|
| 63 | 65 |
void flush_samples(Multi_Buffer *buffer); |
| 64 |
- |
|
| 65 |
-#endif // SOUND_H |
| ... | ... |
@@ -62,31 +62,25 @@ void BIOS_ArcTan2() |
| 62 | 62 |
uint32_t res = 0; |
| 63 | 63 |
if (!y) |
| 64 | 64 |
res = (x >> 16) & 0x8000; |
| 65 |
- else |
|
| 65 |
+ else if (!x) |
|
| 66 |
+ res = ((y >> 16) & 0x8000) + 0x4000; |
|
| 67 |
+ else if (std::abs(x) > std::abs(y) || (std::abs(x) == std::abs(y) && !(x < 0 && y < 0))) |
|
| 66 | 68 |
{
|
| 67 |
- if (!x) |
|
| 68 |
- res = ((y >> 16) & 0x8000) + 0x4000; |
|
| 69 |
+ reg[1].I = x; |
|
| 70 |
+ reg[0].I = y << 14; |
|
| 71 |
+ BIOS_Div(); |
|
| 72 |
+ BIOS_ArcTan(); |
|
| 73 |
+ if (x < 0) |
|
| 74 |
+ res = 0x8000 + reg[0].I; |
|
| 69 | 75 |
else |
| 70 |
- {
|
|
| 71 |
- if (std::abs(x) > std::abs(y) || (std::abs(x) == std::abs(y) && !(x < 0 && y < 0))) |
|
| 72 |
- {
|
|
| 73 |
- reg[1].I = x; |
|
| 74 |
- reg[0].I = y << 14; |
|
| 75 |
- BIOS_Div(); |
|
| 76 |
- BIOS_ArcTan(); |
|
| 77 |
- if (x < 0) |
|
| 78 |
- res = 0x8000 + reg[0].I; |
|
| 79 |
- else |
|
| 80 |
- res = (((y >> 16) & 0x8000) << 1) + reg[0].I; |
|
| 81 |
- } |
|
| 82 |
- else |
|
| 83 |
- {
|
|
| 84 |
- reg[0].I = x << 14; |
|
| 85 |
- BIOS_Div(); |
|
| 86 |
- BIOS_ArcTan(); |
|
| 87 |
- res = (0x4000 + ((y >> 16) & 0x8000)) - reg[0].I; |
|
| 88 |
- } |
|
| 89 |
- } |
|
| 76 |
+ res = (((y >> 16) & 0x8000) << 1) + reg[0].I; |
|
| 77 |
+ } |
|
| 78 |
+ else |
|
| 79 |
+ {
|
|
| 80 |
+ reg[0].I = x << 14; |
|
| 81 |
+ BIOS_Div(); |
|
| 82 |
+ BIOS_ArcTan(); |
|
| 83 |
+ res = (0x4000 + ((y >> 16) & 0x8000)) - reg[0].I; |
|
| 90 | 84 |
} |
| 91 | 85 |
reg[0].I = res; |
| 92 | 86 |
} |
| ... | ... |
@@ -118,8 +112,7 @@ void BIOS_BitUnPack() |
| 118 | 112 |
if (len < 0) |
| 119 | 113 |
break; |
| 120 | 114 |
int mask = 0xff >> revbits; |
| 121 |
- uint8_t b = CPUReadByte(source); |
|
| 122 |
- ++source; |
|
| 115 |
+ uint8_t b = CPUReadByte(source++); |
|
| 123 | 116 |
int bitcount = 0; |
| 124 | 117 |
while (1) |
| 125 | 118 |
{
|
| ... | ... |
@@ -629,6 +622,7 @@ void BIOS_LZ77UnCompVram() |
| 629 | 622 |
writeValue |= CPUReadByte(source++) << byteShift; |
| 630 | 623 |
byteShift += 8; |
| 631 | 624 |
++byteCount; |
| 625 |
+ |
|
| 632 | 626 |
if (byteCount == 2) |
| 633 | 627 |
{
|
| 634 | 628 |
CPUWriteHalfWord(dest, writeValue); |
| ... | ... |
@@ -990,7 +984,7 @@ void BIOS_Sqrt() |
| 990 | 984 |
void BIOS_MidiKey2Freq() |
| 991 | 985 |
{
|
| 992 | 986 |
int freq = CPUReadMemory(reg[0].I + 4); |
| 993 |
- double tmp = (180 - reg[1].I) - (reg[2].I / 256.0); |
|
| 987 |
+ double tmp = (180.0 - reg[1].I) - (reg[2].I / 256.0); |
|
| 994 | 988 |
tmp = std::pow(2.0, tmp / 12.0); |
| 995 | 989 |
reg[0].I = static_cast<int>(freq / tmp); |
| 996 | 990 |
} |
| ... | ... |
@@ -1,28 +1,25 @@ |
| 1 |
-#ifndef BIOS_H |
|
| 2 |
-#define BIOS_H |
|
| 1 |
+#pragma once |
|
| 3 | 2 |
|
| 4 |
-extern void BIOS_ArcTan(); |
|
| 5 |
-extern void BIOS_ArcTan2(); |
|
| 6 |
-extern void BIOS_BitUnPack(); |
|
| 7 |
-extern void BIOS_GetBiosChecksum(); |
|
| 8 |
-extern void BIOS_BgAffineSet(); |
|
| 9 |
-extern void BIOS_CpuSet(); |
|
| 10 |
-extern void BIOS_CpuFastSet(); |
|
| 11 |
-extern void BIOS_Diff8bitUnFilterWram(); |
|
| 12 |
-extern void BIOS_Diff8bitUnFilterVram(); |
|
| 13 |
-extern void BIOS_Diff16bitUnFilter(); |
|
| 14 |
-extern void BIOS_Div(); |
|
| 15 |
-extern void BIOS_HuffUnComp(); |
|
| 16 |
-extern void BIOS_LZ77UnCompVram(); |
|
| 17 |
-extern void BIOS_LZ77UnCompWram(); |
|
| 18 |
-extern void BIOS_ObjAffineSet(); |
|
| 19 |
-extern void BIOS_RegisterRamReset(); |
|
| 20 |
-extern void BIOS_RegisterRamReset(uint32_t); |
|
| 21 |
-extern void BIOS_RLUnCompVram(); |
|
| 22 |
-extern void BIOS_RLUnCompWram(); |
|
| 23 |
-extern void BIOS_SoftReset(); |
|
| 24 |
-extern void BIOS_Sqrt(); |
|
| 25 |
-extern void BIOS_MidiKey2Freq(); |
|
| 26 |
-extern void BIOS_SndDriverJmpTableCopy(); |
|
| 27 |
- |
|
| 28 |
-#endif // BIOS_H |
|
| 3 |
+void BIOS_ArcTan(); |
|
| 4 |
+void BIOS_ArcTan2(); |
|
| 5 |
+void BIOS_BitUnPack(); |
|
| 6 |
+void BIOS_GetBiosChecksum(); |
|
| 7 |
+void BIOS_BgAffineSet(); |
|
| 8 |
+void BIOS_CpuSet(); |
|
| 9 |
+void BIOS_CpuFastSet(); |
|
| 10 |
+void BIOS_Diff8bitUnFilterWram(); |
|
| 11 |
+void BIOS_Diff8bitUnFilterVram(); |
|
| 12 |
+void BIOS_Diff16bitUnFilter(); |
|
| 13 |
+void BIOS_Div(); |
|
| 14 |
+void BIOS_HuffUnComp(); |
|
| 15 |
+void BIOS_LZ77UnCompVram(); |
|
| 16 |
+void BIOS_LZ77UnCompWram(); |
|
| 17 |
+void BIOS_ObjAffineSet(); |
|
| 18 |
+void BIOS_RegisterRamReset(); |
|
| 19 |
+void BIOS_RegisterRamReset(uint32_t); |
|
| 20 |
+void BIOS_RLUnCompVram(); |
|
| 21 |
+void BIOS_RLUnCompWram(); |
|
| 22 |
+void BIOS_SoftReset(); |
|
| 23 |
+void BIOS_Sqrt(); |
|
| 24 |
+void BIOS_MidiKey2Freq(); |
|
| 25 |
+void BIOS_SndDriverJmpTableCopy(); |